shell_uart.c 10 KB

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  1. /*
  2. * Copyright (c) 2018 Nordic Semiconductor ASA
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <shell/shell_uart.h>
  7. #include <drivers/uart.h>
  8. #include <init.h>
  9. #include <logging/log.h>
  10. #include <net/buf.h>
  11. #ifdef CONFIG_USB_UART_CONSOLE
  12. #include <drivers/console/uart_usb.h>
  13. #endif
  14. #define LOG_MODULE_NAME shell_uart
  15. LOG_MODULE_REGISTER(shell_uart);
  16. #ifdef CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD
  17. #define RX_POLL_PERIOD K_MSEC(CONFIG_SHELL_BACKEND_SERIAL_RX_POLL_PERIOD)
  18. #else
  19. #define RX_POLL_PERIOD K_NO_WAIT
  20. #endif
  21. #ifdef CONFIG_MCUMGR_SMP_SHELL
  22. NET_BUF_POOL_DEFINE(smp_shell_rx_pool, CONFIG_MCUMGR_SMP_SHELL_RX_BUF_COUNT,
  23. SMP_SHELL_RX_BUF_SIZE, 0, NULL);
  24. #endif /* CONFIG_MCUMGR_SMP_SHELL */
  25. SHELL_UART_DEFINE(shell_transport_uart,
  26. CONFIG_SHELL_BACKEND_SERIAL_TX_RING_BUFFER_SIZE,
  27. CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE);
  28. SHELL_DEFINE(shell_uart, CONFIG_SHELL_PROMPT_UART, &shell_transport_uart,
  29. CONFIG_SHELL_BACKEND_SERIAL_LOG_MESSAGE_QUEUE_SIZE,
  30. CONFIG_SHELL_BACKEND_SERIAL_LOG_MESSAGE_QUEUE_TIMEOUT,
  31. SHELL_FLAG_OLF_CRLF);
  32. #ifdef CONFIG_MAGIC_SYSRQ
  33. void uart_handle_sysrq_char(const struct device * port, char c);
  34. void uart_handle_sysrq_str(const struct device * port, uint8_t *buf, int len)
  35. {
  36. int i;
  37. for(i = 0; i < len ; i++)
  38. uart_handle_sysrq_char(port, buf[i]);
  39. }
  40. #endif
  41. #ifdef CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN
  42. static void uart_rx_handle(const struct device *dev,
  43. const struct shell_uart *sh_uart)
  44. {
  45. uint8_t *data;
  46. uint32_t len;
  47. uint32_t rd_len;
  48. bool new_data = false;
  49. #ifdef CONFIG_MCUMGR_SMP_SHELL
  50. struct smp_shell_data *const smp = &sh_uart->ctrl_blk->smp;
  51. #endif
  52. do {
  53. len = ring_buf_put_claim(sh_uart->rx_ringbuf, &data,
  54. sh_uart->rx_ringbuf->size);
  55. if (len > 0) {
  56. rd_len = uart_fifo_read(dev, data, len);
  57. /* If there is any new data to be either taken into
  58. * ring buffer or consumed by the SMP, signal the
  59. * shell_thread.
  60. */
  61. if (rd_len > 0) {
  62. new_data = true;
  63. #ifdef CONFIG_MAGIC_SYSRQ
  64. uart_handle_sysrq_str(dev, data, rd_len);
  65. #endif
  66. }
  67. #ifdef CONFIG_MCUMGR_SMP_SHELL
  68. /* Divert bytes from shell handling if it is
  69. * part of an mcumgr frame.
  70. */
  71. size_t i = smp_shell_rx_bytes(smp, data, rd_len);
  72. rd_len -= i;
  73. if (rd_len) {
  74. for (uint32_t j = 0; j < rd_len; j++) {
  75. data[j] = data[i + j];
  76. }
  77. }
  78. #endif /* CONFIG_MCUMGR_SMP_SHELL */
  79. int err = ring_buf_put_finish(sh_uart->rx_ringbuf,
  80. rd_len);
  81. (void)err;
  82. __ASSERT_NO_MSG(err == 0);
  83. } else {
  84. uint8_t dummy;
  85. /* No space in the ring buffer - consume byte. */
  86. LOG_WRN("RX ring buffer full.");
  87. rd_len = uart_fifo_read(dev, &dummy, 1);
  88. #ifdef CONFIG_MAGIC_SYSRQ
  89. if(rd_len == 1)
  90. uart_handle_sysrq_char(dev, dummy);
  91. #endif
  92. #ifdef CONFIG_MCUMGR_SMP_SHELL
  93. /* If successful in getting byte from the fifo, try
  94. * feeding it to SMP as a part of mcumgr frame.
  95. */
  96. if ((rd_len != 0) &&
  97. (smp_shell_rx_bytes(smp, &dummy, 1) == 1)) {
  98. new_data = true;
  99. }
  100. #endif /* CONFIG_MCUMGR_SMP_SHELL */
  101. }
  102. } while (rd_len && (rd_len == len));
  103. if (new_data) {
  104. sh_uart->ctrl_blk->handler(SHELL_TRANSPORT_EVT_RX_RDY,
  105. sh_uart->ctrl_blk->context);
  106. }
  107. }
  108. static void uart_dtr_wait(const struct device *dev)
  109. {
  110. if (IS_ENABLED(CONFIG_SHELL_BACKEND_SERIAL_CHECK_DTR)) {
  111. int dtr, err;
  112. while (true) {
  113. err = uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr);
  114. if (err == -ENOSYS || err == -ENOTSUP) {
  115. break;
  116. }
  117. if (dtr) {
  118. break;
  119. }
  120. /* Give CPU resources to low priority threads. */
  121. k_sleep(K_MSEC(100));
  122. }
  123. }
  124. }
  125. #ifndef CONFIG_USB_UART_CONSOLE
  126. static void uart_tx_handle(const struct device *dev,
  127. const struct shell_uart *sh_uart)
  128. {
  129. uint32_t len;
  130. int err;
  131. const uint8_t *data;
  132. len = ring_buf_get_claim(sh_uart->tx_ringbuf, (uint8_t **)&data,
  133. sh_uart->tx_ringbuf->size);
  134. if (len) {
  135. /* Wait for DTR signal before sending anything to output. */
  136. uart_dtr_wait(dev);
  137. len = uart_fifo_fill(dev, data, len);
  138. err = ring_buf_get_finish(sh_uart->tx_ringbuf, len);
  139. __ASSERT_NO_MSG(err == 0);
  140. } else {
  141. uart_irq_tx_disable(dev);
  142. sh_uart->ctrl_blk->tx_busy = 0;
  143. }
  144. sh_uart->ctrl_blk->handler(SHELL_TRANSPORT_EVT_TX_RDY,
  145. sh_uart->ctrl_blk->context);
  146. }
  147. #endif
  148. #ifdef CONFIG_USB_UART_CONSOLE
  149. static void uart_callback(const struct device *dev, void *user_data)
  150. {
  151. const struct shell_uart *sh_uart = (struct shell_uart *)user_data;
  152. uart_usb_update_tx_done();
  153. if (uart_irq_rx_ready(dev)) {
  154. uart_rx_handle(dev, sh_uart);
  155. }
  156. }
  157. #else
  158. static void uart_callback(const struct device *dev, void *user_data)
  159. {
  160. const struct shell_uart *sh_uart = (struct shell_uart *)user_data;
  161. uart_irq_update(dev);
  162. #ifdef CONFIG_USB_UART_CONSOLE
  163. uart_usb_update_tx_done();
  164. #endif
  165. if (uart_irq_rx_ready(dev)) {
  166. uart_rx_handle(dev, sh_uart);
  167. }
  168. if (uart_irq_tx_ready(dev)) {
  169. uart_tx_handle(dev, sh_uart);
  170. }
  171. }
  172. #endif /* CONFIG_USB_UART_CONSOLE */
  173. #endif /* CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN */
  174. static void uart_irq_init(const struct shell_uart *sh_uart)
  175. {
  176. #ifdef CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN
  177. const struct device *dev = sh_uart->ctrl_blk->dev;
  178. ring_buf_reset(sh_uart->tx_ringbuf);
  179. ring_buf_reset(sh_uart->rx_ringbuf);
  180. sh_uart->ctrl_blk->tx_busy = 0;
  181. uart_irq_callback_user_data_set(dev, uart_callback, (void *)sh_uart);
  182. uart_irq_rx_enable(dev);
  183. #endif
  184. }
  185. static void timer_handler(struct k_timer *timer)
  186. {
  187. uint8_t c;
  188. const struct shell_uart *sh_uart = k_timer_user_data_get(timer);
  189. while (uart_poll_in(sh_uart->ctrl_blk->dev, &c) == 0) {
  190. #ifdef CONFIG_MAGIC_SYSRQ
  191. uart_handle_sysrq_char(sh_uart->ctrl_blk->dev, c);
  192. #endif
  193. if (ring_buf_put(sh_uart->rx_ringbuf, &c, 1) == 0U) {
  194. /* ring buffer full. */
  195. LOG_WRN("RX ring buffer full.");
  196. }
  197. sh_uart->ctrl_blk->handler(SHELL_TRANSPORT_EVT_RX_RDY,
  198. sh_uart->ctrl_blk->context);
  199. }
  200. }
  201. static int init(const struct shell_transport *transport,
  202. const void *config,
  203. shell_transport_handler_t evt_handler,
  204. void *context)
  205. {
  206. const struct shell_uart *sh_uart = (struct shell_uart *)transport->ctx;
  207. sh_uart->ctrl_blk->dev = (const struct device *)config;
  208. sh_uart->ctrl_blk->handler = evt_handler;
  209. sh_uart->ctrl_blk->context = context;
  210. #ifdef CONFIG_MCUMGR_SMP_SHELL
  211. sh_uart->ctrl_blk->smp.buf_pool = &smp_shell_rx_pool;
  212. k_fifo_init(&sh_uart->ctrl_blk->smp.buf_ready);
  213. #endif
  214. if (IS_ENABLED(CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN)) {
  215. uart_irq_init(sh_uart);
  216. } else {
  217. k_timer_init(sh_uart->timer, timer_handler, NULL);
  218. k_timer_user_data_set(sh_uart->timer, (void *)sh_uart);
  219. k_timer_start(sh_uart->timer, RX_POLL_PERIOD, RX_POLL_PERIOD);
  220. }
  221. return 0;
  222. }
  223. static int uninit(const struct shell_transport *transport)
  224. {
  225. const struct shell_uart *sh_uart = (struct shell_uart *)transport->ctx;
  226. if (IS_ENABLED(CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN)) {
  227. const struct device *dev = sh_uart->ctrl_blk->dev;
  228. uart_irq_tx_disable(dev);
  229. uart_irq_rx_disable(dev);
  230. } else {
  231. k_timer_stop(sh_uart->timer);
  232. }
  233. return 0;
  234. }
  235. static int enable(const struct shell_transport *transport, bool blocking_tx)
  236. {
  237. const struct shell_uart *sh_uart = (struct shell_uart *)transport->ctx;
  238. sh_uart->ctrl_blk->blocking_tx = blocking_tx;
  239. if (blocking_tx) {
  240. #ifdef CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN
  241. uart_irq_tx_disable(sh_uart->ctrl_blk->dev);
  242. #endif
  243. }
  244. return 0;
  245. }
  246. #ifdef CONFIG_ACTIONS_PRINTK_DMA
  247. extern int uart_dma_send_buf(const uint8_t *buf, int len);
  248. #elif !defined(CONFIG_USB_UART_CONSOLE)
  249. static void irq_write(const struct shell_uart *sh_uart, const void *data,
  250. size_t length, size_t *cnt)
  251. {
  252. *cnt = ring_buf_put(sh_uart->tx_ringbuf, data, length);
  253. if (atomic_set(&sh_uart->ctrl_blk->tx_busy, 1) == 0) {
  254. #ifdef CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN
  255. uart_irq_tx_enable(sh_uart->ctrl_blk->dev);
  256. #endif
  257. }
  258. }
  259. #endif
  260. static int write(const struct shell_transport *transport,
  261. const void *data, size_t length, size_t *cnt)
  262. {
  263. const struct shell_uart *sh_uart = (struct shell_uart *)transport->ctx;
  264. const uint8_t *data8 = (const uint8_t *)data;
  265. #ifdef CONFIG_ACTIONS_PRINTK_DMA
  266. *cnt = uart_dma_send_buf(data8, length);
  267. sh_uart->ctrl_blk->handler(SHELL_TRANSPORT_EVT_TX_RDY,
  268. sh_uart->ctrl_blk->context);
  269. #elif CONFIG_USB_UART_CONSOLE
  270. uart_usb_send(data8, length);
  271. *cnt = length;
  272. sh_uart->ctrl_blk->handler(SHELL_TRANSPORT_EVT_TX_RDY,
  273. sh_uart->ctrl_blk->context);
  274. #else
  275. if (IS_ENABLED(CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN) &&
  276. !sh_uart->ctrl_blk->blocking_tx) {
  277. irq_write(sh_uart, data, length, cnt);
  278. } else {
  279. for (size_t i = 0; i < length; i++) {
  280. uart_poll_out(sh_uart->ctrl_blk->dev, data8[i]);
  281. }
  282. *cnt = length;
  283. sh_uart->ctrl_blk->handler(SHELL_TRANSPORT_EVT_TX_RDY,
  284. sh_uart->ctrl_blk->context);
  285. }
  286. #endif
  287. return 0;
  288. }
  289. static int read(const struct shell_transport *transport,
  290. void *data, size_t length, size_t *cnt)
  291. {
  292. struct shell_uart *sh_uart = (struct shell_uart *)transport->ctx;
  293. *cnt = ring_buf_get(sh_uart->rx_ringbuf, data, length);
  294. return 0;
  295. }
  296. #ifdef CONFIG_MCUMGR_SMP_SHELL
  297. static void update(const struct shell_transport *transport)
  298. {
  299. struct shell_uart *sh_uart = (struct shell_uart *)transport->ctx;
  300. smp_shell_process(&sh_uart->ctrl_blk->smp);
  301. }
  302. #endif /* CONFIG_MCUMGR_SMP_SHELL */
  303. const struct shell_transport_api shell_uart_transport_api = {
  304. .init = init,
  305. .uninit = uninit,
  306. .enable = enable,
  307. .write = write,
  308. .read = read,
  309. #ifdef CONFIG_MCUMGR_SMP_SHELL
  310. .update = update,
  311. #endif /* CONFIG_MCUMGR_SMP_SHELL */
  312. };
  313. static int enable_shell_uart(const struct device *arg)
  314. {
  315. ARG_UNUSED(arg);
  316. const struct device *dev =
  317. device_get_binding(CONFIG_UART_SHELL_ON_DEV_NAME);
  318. bool log_backend = CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL > 0;
  319. uint32_t level =
  320. (CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL > LOG_LEVEL_DBG) ?
  321. CONFIG_LOG_MAX_LEVEL : CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL;
  322. if (!device_is_ready(dev)) {
  323. return -ENODEV;
  324. }
  325. if (IS_ENABLED(CONFIG_MCUMGR_SMP_SHELL)) {
  326. smp_shell_init();
  327. }
  328. shell_init(&shell_uart, dev, true, log_backend, level);
  329. return 0;
  330. }
  331. SYS_INIT(enable_shell_uart, POST_KERNEL,
  332. CONFIG_SHELL_BACKEND_SERIAL_INIT_PRIORITY);
  333. const struct shell *shell_backend_uart_get_ptr(void)
  334. {
  335. return &shell_uart;
  336. }