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zephyr
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drivers
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display
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panel
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panel_er76288a.h

panel_er76288a.h 4.5 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2020 Actions Technology Co., Ltd
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef PANEL_ER76288A_DRIVER_H__
    8. 

  8. #define PANEL_ER76288A_DRIVER_H__
    9. 

  9. 

  10. #define DDIC_CMD_NOP			0x00 /* No Operation */
    11. 

  11. #define DDIC_CMD_SWRESET		0x01 /* Software Reset */
    12. 

  12. #define DDIC_CMD_RDDID			0x04 /* Read Display ID */
    13. 

  13. #define DDIC_CMD_RDNUMED		0x05 /* Read Number of Errors on DSI */
    14. 

  14. #define DDIC_CMD_RDDSTA			0x09 /* Read Display Status */
    15. 

  15. #define DDIC_CMD_RDDPM			0x0A /* Read Display Power Mode */
    16. 

  16. #define DDIC_CMD_RDDMADCTR		0x0B /* Read Display Address Mode */
    17. 

  17. #define DDIC_CMD_RDDCOLMOD		0x0C /* Read Display Pixel Format */
    18. 

  18. #define DDIC_CMD_RDDIM			0x0D /* Read Display Image Mode */
    19. 

  19. #define DDIC_CMD_RDDSM			0x0E /* Read Display Signal Mode */
    20. 

  20. #define DDIC_CMD_SLPIN			0x10 /* Sleep In */
    21. 

  21. #define DDIC_CMD_SLPOUT			0x11 /* Sleep Out */
    22. 

  22. #define DDIC_CMD_PARON			0x12 /* Partial Display Mode On */
    23. 

  23. #define DDIC_CMD_NORON			0x13 /* Normal Display Mode On */
    24. 

  24. #define DDIC_CMD_INVOFF			0x20 /* Display Inversion Off */
    25. 

  25. #define DDIC_CMD_INVON			0x21 /* Display Inversion On */
    26. 

  26. #define DDIC_CMD_ALLPOFF		0x22 /* All Pixel Off */
    27. 

  27. #define DDIC_CMD_ALLPON			0x23 /* All Pixel On */
    28. 

  28. #define DDIC_CMD_DISPOFF		0x28 /* Display Off */
    29. 

  29. #define DDIC_CMD_DISPON			0x29 /* Display On */
    30. 

  30. #define DDIC_CMD_CASET			0x2A /* Column Start Address Set */
    31. 

  31. #define DDIC_CMD_RASET			0x2B /* Row Start Address Set */
    32. 

  32. #define DDIC_CMD_RAMWR			0x2C /* Memory Write Start */
    33. 

  33. #define DDIC_CMD_RAMRD			0x2E /* Memory Read Start */
    34. 

  34. #define DDIC_CMD_PTLAR			0x30 /* Vertical Partial Area Set */
    35. 

  35. #define DDIC_CMD_PTLAR_H		0x31 /* Horizontal Partial Area Set */
    36. 

  36. #define DDIC_CMD_TEOFF			0x34 /* Tearing Effect Line OFF */
    37. 

  37. #define DDIC_CMD_TEON			0x35 /* Tearing Effect Line ON */
    38. 

  38. #define DDIC_CMD_MADCTL			0x36 /* Address Mode Set */
    39. 

  39. #define DDIC_CMD_IDMOFF			0x38 /* Idle Mode Off */
    40. 

  40. #define DDIC_CMD_IDMON			0x39 /* Idle Mode On */
    41. 

  41. #define DDIC_CMD_COLMOD			0x3A /* Control Interface Pixel Format */
    42. 

  42. #define DDIC_CMD_RAMWRC			0x3C /* Memory Write Continue */
    43. 

  43. #define DDIC_CMD_RAMRDC			0x3E /* Memory Read Continue */
    44. 

  44. #define DDIC_CMD_STESL			0x44 /* Set Tearing Effect Scan Line */
    45. 

  45. #define DDIC_CMD_GSL			0x45 /* Get Scan Line */
    46. 

  46. #define DDIC_CMD_WRDISBV		0x51 /* Write Display Brightness Value */
    47. 

  47. #define DDIC_CMD_RDDISBV		0x52 /* Read Display Brightness Value */
    48. 

  48. #define DDIC_CMD_WRCTRLD		0x53 /* Write CTRL Display */
    49. 

  49. #define DDIC_CMD_RDCTRLD		0x54 /* Read CTRL Display */
    50. 

  50. #define DDIC_CMD_WRACL			0x55 /* Write ACL Control */
    51. 

  51. #define DDIC_CMD_RDACL			0x56 /* Read ACL Control */
    52. 

  52. #define DDIC_CMD_WRHBMDISBV		0x63 /* Write HBM Display Brightness Value */
    53. 

  53. #define DDIC_CMD_RDHBMDISBV		0x64 /* Read HBM Display Brightness Value */
    54. 

  54. #define DDIC_CMD_HBMCTL			0x66 /* Set HBM Mode */
    55. 

  55. #define DDIC_CMD_DEEPIDM		0x67 /* Set Deep Idle Mode */
    56. 

  56. #define DDIC_CMD_COLSET0		0x70 /* Interface Pixel Format Set */
    57. 

  57. #define DDIC_CMD_COLSET1		0x71 /* Interface Pixel Format Set */
    58. 

  58. #define DDIC_CMD_COLSET2		0x72 /* Interface Pixel Format Set */
    59. 

  59. #define DDIC_CMD_COLSET3		0x73 /* Interface Pixel Format Set */
    60. 

  60. #define DDIC_CMD_COLSET4		0x74 /* Interface Pixel Format Set */
    61. 

  61. #define DDIC_CMD_COLSET5		0x75 /* Interface Pixel Format Set */
    62. 

  62. #define DDIC_CMD_COLSET6		0x76 /* Interface Pixel Format Set */
    63. 

  63. #define DDIC_CMD_COLSET7		0x77 /* Interface Pixel Format Set */
    64. 

  64. #define DDIC_CMD_COLSET8		0x78 /* Interface Pixel Format Set */
    65. 

  65. #define DDIC_CMD_COLSET9		0x79 /* Interface Pixel Format Set */
    66. 

  66. #define DDIC_CMD_COLSET10		0x7A /* Interface Pixel Format Set */
    67. 

  67. #define DDIC_CMD_COLSET11		0x7B /* Interface Pixel Format Set */
    68. 

  68. #define DDIC_CMD_COLSET12		0x7C /* Interface Pixel Format Set */
    69. 

  69. #define DDIC_CMD_COLSET13		0x7D /* Interface Pixel Format Set */
    70. 

  70. #define DDIC_CMD_COLSET14		0x7E /* Interface Pixel Format Set */
    71. 

  71. #define DDIC_CMD_COLSET15		0x7F /* Interface Pixel Format Set */
    72. 

  72. #define DDIC_CMD_COLOPT			0x80 /* Interface Pixel Format Option */
    73. 

  73. #define DDIC_CMD_RDDDBS			0xA1 /* Read DDB Start */
    74. 

  74. #define DDIC_CMD_RDDDBC			0xA8 /* Read DDB Continue */
    75. 

  75. 

  76. #define DDIC_CMD_SETDSPIMODE	0xC4 /* Set Dual SPI Mode */
    77. 

  77. #define DDIC_CMD_RDDSPIMODE		0xC5 /* Read Dual SPI Mode */
    78. 

  78. #define DDIC_CMD_RDID1			0xDA /* Read ID1 */
    79. 

  79. #define DDIC_CMD_RDID2			0xDB /* Read ID2 */
    80. 

  80. #define DDIC_CMD_RDID3			0xDC /* Read ID3 */
    81. 

  81. #define DDIC_CMD_MSC			0xFE /* CMD Page Switch */
    82. 

  82. 

  83. #define DDIC_QSPI_CMD_RD(cmd)		((0x03 << 24) | ((uint32_t)(cmd) << 8))
    84. 

  84. #define DDIC_QSPI_CMD_WR(cmd)		((0x02 << 24) | ((uint32_t)(cmd) << 8))
    85. 

  85. #define DDIC_QSPI_CMD_RAMWR(cmd)	((0x32 << 24) | ((uint32_t)(cmd) << 8))
    86. 

  86. 

  87. #endif /* PANEL_ER76288A_DRIVER_H__ */
    88.