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zephyr
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include
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drivers
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pcie
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cap.h

cap.h 4.2 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2021 BayLibre, SAS
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  */
    6. 

  6. #ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_CAP_H_
    7. 

  7. #define ZEPHYR_INCLUDE_DRIVERS_PCIE_CAP_H_
    8. 

  8. 

  9. /*
    10. 

  10.  * PCI & PCI Express Capabilities
    11. 

  11.  * from PCI Code and ID Assignment Specification Revision 1.11
    12. 

  12.  */
    13. 

  13. 

  14. #define PCI_CAP_ID_NULL		0x00U	/* Null Capability */
    15. 

  15. #define PCI_CAP_ID_PM		0x01U	/* Power Management */
    16. 

  16. #define PCI_CAP_ID_AGP		0x02U	/* Accelerated Graphics Port */
    17. 

  17. #define PCI_CAP_ID_VPD		0x03U	/* Vital Product Data */
    18. 

  18. #define PCI_CAP_ID_SLOTID	0x04U	/* Slot Identification */
    19. 

  19. #define PCI_CAP_ID_MSI		0x05U	/* Message Signalled Interrupts */
    20. 

  20. #define PCI_CAP_ID_CHSWP	0x06U	/* CompactPCI HotSwap */
    21. 

  21. #define PCI_CAP_ID_PCIX		0x07U	/* PCI-X */
    22. 

  22. #define PCI_CAP_ID_HT		0x08U	/* HyperTransport */
    23. 

  23. #define PCI_CAP_ID_VNDR		0x09U	/* Vendor-Specific */
    24. 

  24. #define PCI_CAP_ID_DBG		0x0AU	/* Debug port */
    25. 

  25. #define PCI_CAP_ID_CCRC		0x0BU	/* CompactPCI Central Resource Control */
    26. 

  26. #define PCI_CAP_ID_SHPC		0x0CU	/* PCI Standard Hot-Plug Controller */
    27. 

  27. #define PCI_CAP_ID_SSVID	0x0DU	/* Bridge subsystem vendor/device ID */
    28. 

  28. #define PCI_CAP_ID_AGP3		0x0EU	/* AGP 8x */
    29. 

  29. #define PCI_CAP_ID_SECDEV	0x0FU	/* Secure Device */
    30. 

  30. #define PCI_CAP_ID_EXP		0x10U	/* PCI Express */
    31. 

  31. #define PCI_CAP_ID_MSIX		0x11U	/* MSI-X */
    32. 

  32. #define PCI_CAP_ID_SATA		0x12U	/* Serial ATA Data/Index Configuration */
    33. 

  33. #define PCI_CAP_ID_AF		0x13U	/* PCI Advanced Features */
    34. 

  34. #define PCI_CAP_ID_EA		0x14U	/* PCI Enhanced Allocation */
    35. 

  35. #define PCI_CAP_ID_FPB		0x14U	/* Flattening Portal Bridge */
    36. 

  36. 

  37. /*
    38. 

  38.  * PCI Express Extended Capabilities
    39. 

  39.  */
    40. 

  40. 

  41. #define PCI_EXT_CAP_ID_NULL	0x0000U	/* Null Capability */
    42. 

  42. #define PCI_EXT_CAP_ID_ERR	0x0001U	/* Advanced Error Reporting */
    43. 

  43. #define PCI_EXT_CAP_ID_VC	0x0002U	/* Virtual Channel when no MFVC */
    44. 

  44. #define PCI_EXT_CAP_ID_DSN	0x0003U	/* Device Serial Number */
    45. 

  45. #define PCI_EXT_CAP_ID_PWR	0x0004U	/* Power Budgeting */
    46. 

  46. #define PCI_EXT_CAP_ID_RCLD	0x0005U	/* Root Complex Link Declaration */
    47. 

  47. #define PCI_EXT_CAP_ID_RCILC	0x0006U	/* Root Complex Internal Link Control */
    48. 

  48. #define PCI_EXT_CAP_ID_RCEC	0x0007U	/* Root Complex Event Collector Endpoint Association */
    49. 

  49. #define PCI_EXT_CAP_ID_MFVC	0x0008U	/* Multi-Function VC Capability */
    50. 

  50. #define PCI_EXT_CAP_ID_MFVC_VC	0x0009U	/* Virtual Channel used with MFVC */
    51. 

  51. #define PCI_EXT_CAP_ID_RCRB	0x000AU	/* Root Complex Register Block */
    52. 

  52. #define PCI_EXT_CAP_ID_VNDR	0x000BU	/* Vendor-Specific Extended Capability */
    53. 

  53. #define PCI_EXT_CAP_ID_CAC	0x000CU	/* Config Access Correlation - obsolete */
    54. 

  54. #define PCI_EXT_CAP_ID_ACS	0x000DU	/* Access Control Services */
    55. 

  55. #define PCI_EXT_CAP_ID_ARI	0x000EU	/* Alternate Routing-ID Interpretation */
    56. 

  56. #define PCI_EXT_CAP_ID_ATS	0x000FU	/* Address Translation Services */
    57. 

  57. #define PCI_EXT_CAP_ID_SRIOV	0x0010U	/* Single Root I/O Virtualization */
    58. 

  58. #define PCI_EXT_CAP_ID_MRIOV	0x0011U	/* Multi Root I/O Virtualization */
    59. 

  59. #define PCI_EXT_CAP_ID_MCAST	0x0012U	/* Multicast */
    60. 

  60. #define PCI_EXT_CAP_ID_PRI	0x0013U	/* Page Request Interface */
    61. 

  61. #define PCI_EXT_CAP_ID_AMD_XXX	0x0014U	/* Reserved for AMD */
    62. 

  62. #define PCI_EXT_CAP_ID_REBAR	0x0015U	/* Resizable BAR */
    63. 

  63. #define PCI_EXT_CAP_ID_DPA	0x0016U	/* Dynamic Power Allocation */
    64. 

  64. #define PCI_EXT_CAP_ID_TPH	0x0017U	/* TPH Requester */
    65. 

  65. #define PCI_EXT_CAP_ID_LTR	0x0018U	/* Latency Tolerance Reporting */
    66. 

  66. #define PCI_EXT_CAP_ID_SECPCI	0x0019U	/* Secondary PCIe Capability */
    67. 

  67. #define PCI_EXT_CAP_ID_PMUX	0x001AU	/* Protocol Multiplexing */
    68. 

  68. #define PCI_EXT_CAP_ID_PASID	0x001BU	/* Process Address Space ID */
    69. 

  69. #define PCI_EXT_CAP_ID_DPC	0x001DU	/* DPC: Downstream Port Containment */
    70. 

  70. #define PCI_EXT_CAP_ID_L1SS	0x001EU	/* L1 PM Substates */
    71. 

  71. #define PCI_EXT_CAP_ID_PTM	0x001FU	/* Precision Time Measurement */
    72. 

  72. #define PCI_EXT_CAP_ID_DVSEC	0x0023U	/* Designated Vendor-Specific Extended Capability */
    73. 

  73. #define PCI_EXT_CAP_ID_DLF	0x0025U	/* Data Link Feature */
    74. 

  74. #define PCI_EXT_CAP_ID_PL_16GT	0x0026U	/* Physical Layer 16.0 GT/s */
    75. 

  75. #define PCI_EXT_CAP_ID_LMR	0x0027U	/* Lane Margining at the Receiver */
    76. 

  76. #define PCI_EXT_CAP_ID_HID	0x0028U	/* Hierarchy ID  */
    77. 

  77. #define PCI_EXT_CAP_ID_NPEM	0x0029U	/* Native PCIe Enclosure Management */
    78. 

  78. #define PCI_EXT_CAP_ID_PL_32GT	0x002AU	/* Physical Layer 32.0 GT/s */
    79. 

  79. #define PCI_EXT_CAP_ID_AP	0x002BU	/* Alternate Protocol */
    80. 

  80. #define PCI_EXT_CAP_ID_SFI	0x002CU	/* System Firmware Intermediary  */
    81. 

  81. 

  82. #endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_CAP_H_ */
    83.