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soc_memctrl.h

soc_memctrl.h 8.2 KB
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  1. /********************************************************************************
    2. 

  2.  *                            USDK(ZS283A)
    3. 

  3.  *                            Module: SYSTEM
    4. 

  4.  *                 Copyright(c) 2003-2017 Actions Semiconductor,
    5. 

  5.  *                            All Rights Reserved.
    6. 

  6.  *
    7. 

  7.  * History:
    8. 

  8.  *      <author>      <time>                      <version >          <desc>
    9. 

  9.  *      wuyufan   2018-10-12-PM12:48:04             1.0             build this file
    10. 

  10.  ********************************************************************************/
    11. 

  11. /*!
    12. 

  12.  * \file     soc_memctrl.h
    13. 

  13.  * \brief
    14. 

  14.  * \author
    15. 

  15.  * \version  1.0
    16. 

  16.  * \date  2018-10-12-PM12:48:04
    17. 

  17.  *******************************************************************************/
    18. 

  18. 

  19. #ifndef SOC_MEMCTRL_H_
    20. 

  20. #define SOC_MEMCTRL_H_
    21. 

  21. 

  22. 

  23. //--------------MemoryController-------------------------------------------//
    24. 

  24. //--------------Register Address---------------------------------------//
    25. 

  25. #define     MemoryController_BASE                                             0x40010000
    26. 

  26. #define     MEMORYCTL                                                         (MemoryController_BASE+0x00000000)
    27. 

  27. #define     CPU_ERROR_ADDR                                                    (MemoryController_BASE+0x00000008)
    28. 

  28. #define     MEMORYCTL2                                                        (MemoryController_BASE+0x00000020)
    29. 

  29. #define     MEMORYCTL3                                                        (MemoryController_BASE+0x00000024)
    30. 

  30. #define     DSP_ERROR_ADDR                                                    (MemoryController_BASE+0x00000030)
    31. 

  31. #define     DBGCTL                                                            (MemoryController_BASE+0x00000040)
    32. 

  32. #define     DSPPAGEADDR0                                                      (MemoryController_BASE+0x00000080)
    33. 

  33. #define     DSPPAGEADDR1                                                      (MemoryController_BASE+0x00000084)
    34. 

  34. #define     DSPPAGEADDR2                                                      (MemoryController_BASE+0x00000088)
    35. 

  35. #define     DSPPAGEADDR3                                                      (MemoryController_BASE+0x0000008c)
    36. 

  36. #define     MPUIE                                                             (MemoryController_BASE+0x00000100)
    37. 

  37. #define     MPUIP                                                             (MemoryController_BASE+0x00000104)
    38. 

  38. #define     MPUCTL0                                                           (MemoryController_BASE+0x00000110)
    39. 

  39. #define     MPUBASE0                                                          (MemoryController_BASE+0x00000114)
    40. 

  40. #define     MPUEND0                                                           (MemoryController_BASE+0x00000118)
    41. 

  41. #define     MPUERRADDR0                                                       (MemoryController_BASE+0x0000011c)
    42. 

  42. #define     MPUCTL1                                                           (MemoryController_BASE+0x00000120)
    43. 

  43. #define     MPUBASE1                                                          (MemoryController_BASE+0x00000124)
    44. 

  44. #define     MPUEND1                                                           (MemoryController_BASE+0x00000128)
    45. 

  45. #define     MPUERRADDR1                                                       (MemoryController_BASE+0x0000012c)
    46. 

  46. #define     MPUCTL2                                                           (MemoryController_BASE+0x00000130)
    47. 

  47. #define     MPUBASE2                                                          (MemoryController_BASE+0x00000134)
    48. 

  48. #define     MPUEND2                                                           (MemoryController_BASE+0x00000138)
    49. 

  49. #define     MPUERRADDR2                                                       (MemoryController_BASE+0x0000013c)
    50. 

  50. #define     MPUCTL3                                                           (MemoryController_BASE+0x00000140)
    51. 

  51. #define     MPUBASE3                                                          (MemoryController_BASE+0x00000144)
    52. 

  52. #define     MPUEND3                                                           (MemoryController_BASE+0x00000148)
    53. 

  53. #define     MPUERRADDR3                                                       (MemoryController_BASE+0x0000014c)
    54. 

  54. #define     BIST_EN0                                                          (MemoryController_BASE+0x00000200)
    55. 

  55. #define     BIST_FIN0                                                         (MemoryController_BASE+0x00000204)
    56. 

  56. #define     BIST_INFO0                                                        (MemoryController_BASE+0x00000208)
    57. 

  57. #define     BIST_EN1                                                          (MemoryController_BASE+0x0000020c)
    58. 

  58. #define     BIST_FIN1                                                         (MemoryController_BASE+0x00000210)
    59. 

  59. #define     BIST_INFO1                                                        (MemoryController_BASE+0x00000214)
    60. 

  60. #define     SPI_CACHE_MAPPING_ADDR0                                           (MemoryController_BASE+0x00000300)
    61. 

  61. #define     SPI_CACHE_ADDR0_ENTRY                                             (MemoryController_BASE+0x00000304)
    62. 

  62. #define     SPI_CACHE_MAPPING_ADDR1                                           (MemoryController_BASE+0x00000308)
    63. 

  63. #define     SPI_CACHE_ADDR1_ENTRY                                             (MemoryController_BASE+0x0000030c)
    64. 

  64. #define     SPI_CACHE_MAPPING_ADDR2                                           (MemoryController_BASE+0x00000310)
    65. 

  65. #define     SPI_CACHE_ADDR2_ENTRY                                             (MemoryController_BASE+0x00000314)
    66. 

  66. #define     SPI_CACHE_MAPPING_ADDR3                                           (MemoryController_BASE+0x00000318)
    67. 

  67. #define     SPI_CACHE_ADDR3_ENTRY                                             (MemoryController_BASE+0x0000031c)
    68. 

  68. #define     SPI_CACHE_MAPPING_ADDR4                                           (MemoryController_BASE+0x00000320)
    69. 

  69. #define     SPI_CACHE_ADDR4_ENTRY                                             (MemoryController_BASE+0x00000324)
    70. 

  70. #define     SPI_CACHE_MAPPING_ADDR5                                           (MemoryController_BASE+0x00000328)
    71. 

  71. #define     SPI_CACHE_ADDR5_ENTRY                                             (MemoryController_BASE+0x0000032c)
    72. 

  72. #define     SPI_CACHE_MAPPING_ADDR6                                           (MemoryController_BASE+0x00000330)
    73. 

  73. #define     SPI_CACHE_ADDR6_ENTRY                                             (MemoryController_BASE+0x00000334)
    74. 

  74. #define     SPI_CACHE_MAPPING_ADDR7                                           (MemoryController_BASE+0x00000338)
    75. 

  75. #define     SPI_CACHE_ADDR7_ENTRY                                             (MemoryController_BASE+0x0000033c)
    76. 

  76. 

  77. #define     CACHE_MAPPING_ITEM_NUM			(8)
    78. 

  78. 

  79. 

  80. #define     MEMORYCTL_BUSERROR_BIT          BIT(3)
    81. 

  81. 

  82. #define     DISPLAY_MMU_CTL 	                                              (MemoryController_BASE+0x00000a00)
    83. 

  83. #define     DISPLAY_MMU_BASEADDR0                                             (MemoryController_BASE+0x00000a10)
    84. 

  84. #define     DISPLAY_MMU_BASEADDR1                                             (MemoryController_BASE+0x00000a14)
    85. 

  85. #define     DISPLAY_MMU_BASEADDR2                                             (MemoryController_BASE+0x00000a18)
    86. 

  86. #define     DISPLAY_MMU_BASEADDR3                                             (MemoryController_BASE+0x00000a1c)
    87. 

  87. 

  88. typedef struct {
    89. 

  89. 	volatile unsigned int mapping_addr;
    90. 

  90. 	volatile unsigned int mapping_entry;
    91. 

  91. } cache_mapping_register_t;
    92. 

  92. 

  93. typedef struct
    94. 

  94. {
    95. 

  95.     volatile uint32_t MPUCTL;
    96. 

  96.     volatile uint32_t MPUBASE;
    97. 

  97.     volatile uint32_t MPUEND;
    98. 

  98.     volatile uint32_t MPUERRADDR;
    99. 

  99. }mpu_base_register_t;
    100. 

  100. 

  101. void soc_memctrl_set_mapping(int idx, u32_t cpu_addr, u32_t nor_bus_addr);
    102. 

  102. int soc_memctrl_mapping(u32_t cpu_addr, u32_t nor_phy_addr, int enable_crc);
    103. 

  103. int soc_memctrl_unmapping(u32_t map_addr);
    104. 

  104. void *soc_memctrl_create_temp_mapping(u32_t nor_phy_addr, int enable_crc);
    105. 

  105. void soc_memctrl_clear_temp_mapping(void *cpu_addr);
    106. 

  106. u32_t soc_memctrl_cpu_to_nor_phy_addr(u32_t cpu_addr);
    107. 

  107. 

  108. void soc_memctrl_config_cache_size(int cache_size_mode);
    109. 

  109. void soc_memctrl_cache_invalid(void);
    110. 

  110. 

  111. static inline void soc_memctrl_set_dsp_mapping(int idx, u32_t map_addr,
    112. 

  112. 					  u32_t phy_addr)
    113. 

  113. {
    114. 

  114.     return;
    115. 

  115. }
    116. 

  116. 

  117. static inline u32_t soc_memctrl_cpu_addr_to_bus_addr(u32_t cpu_addr)
    118. 

  118. {
    119. 

  119. 	u32_t bus_addr;
    120. 

  120. 

  121. 	if (cpu_addr < 0x10000000)
    122. 

  122. 		bus_addr = 0x10000000;
    123. 

  123. 	else
    124. 

  124. 		bus_addr = cpu_addr & ~0xe0000000;
    125. 

  125. 

  126. 	return bus_addr;
    127. 

  127. }
    128. 

  128. 

  129. #endif /* SOC_MEMCTRL_H_ */
    130.