soc_ppi.c 4.5 KB

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  1. /*******************************************************************************
  2. * @file soc_ppi.c
  3. * @author MEMS Application Team
  4. * @version V1.0
  5. * @date 2020-08-12
  6. * @brief leopard hardware access layer
  7. *******************************************************************************/
  8. /******************************************************************************/
  9. //includes
  10. /******************************************************************************/
  11. #include <soc.h>
  12. #include <linker/linker-defs.h>
  13. /******************************************************************************/
  14. //typedefs
  15. /******************************************************************************/
  16. typedef struct {
  17. volatile uint32_t TRIGGER_EN; /*!< (@ 0x00000000) Trigger Enable Register */
  18. volatile uint32_t TRIGGER_EN1; /*!< (@ 0x00000004) Trigger Enable Register */
  19. volatile uint32_t TRIGGER_PD; /*!< (@ 0x00000008) Trigger Pending Register */
  20. volatile uint32_t TRIGGER_PD1; /*!< (@ 0x0000000C) Trigger Pending Register */
  21. volatile uint32_t PPI_CH_CFG[12]; /*!< (@ 0x00000010) PPI Channel Config Register */
  22. } WIC_Type;
  23. #define WIC ((WIC_Type*) WIC_BASE)
  24. /* PPI_CH_CFG */
  25. #define WIC_PPI_CH_CFG_CH_EN_Pos (31UL) /*!< CH_EN (Bit 31) */
  26. #define WIC_PPI_CH_CFG_CH_EN_Msk (0x80000000UL) /*!< CH_EN (Bitfield-Mask: 0x01) */
  27. #define WIC_PPI_CH_CFG_TASK_SEL_Pos (8UL) /*!< TASK_SEL (Bit 8) */
  28. #define WIC_PPI_CH_CFG_TASK_SEL_Msk (0x1f00UL) /*!< TASK_SEL (Bitfield-Mask: 0x1f) */
  29. #define WIC_PPI_CH_CFG_TRIGGER_SEL_Pos (0UL) /*!< TRIGGER_SEL (Bit 0) */
  30. #define WIC_PPI_CH_CFG_TRIGGER_SEL_Msk (0x3fUL) /*!< TRIGGER_SEL (Bitfield-Mask: 0x3f) */
  31. /******************************************************************************/
  32. //functions
  33. /******************************************************************************/
  34. static __sleepfunc int ppi_trig_src_mapping(int trig_src)
  35. {
  36. if (trig_src <= TIMER4) {
  37. return trig_src;
  38. } else if (trig_src <= IO11_IRQ) {
  39. return (trig_src - IO0_IRQ + 16);
  40. } else if (trig_src <= SPIMT1_TASK7_CIP) {
  41. return (trig_src - SPIMT0_TASK0_CIP + 32);
  42. } else if (trig_src <= I2CMT0_TASK3_CIP) {
  43. return (trig_src - I2CMT0_TASK0_CIP + 48);
  44. } else if (trig_src <= I2CMT1_TASK3_CIP) {
  45. return (trig_src - I2CMT0_TASK0_CIP + 48 + 8);
  46. } else if (trig_src == TIMER5) {
  47. return 5;
  48. } else{
  49. return -1;
  50. }
  51. }
  52. void ppi_init(void)
  53. {
  54. int ch;
  55. /* clear trigger enable */
  56. WIC->TRIGGER_EN = 0;
  57. WIC->TRIGGER_EN1 = 0;
  58. /* clear trigger pending */
  59. WIC->TRIGGER_PD = WIC->TRIGGER_PD;
  60. WIC->TRIGGER_PD1 = WIC->TRIGGER_PD1;
  61. /* disable channel */
  62. for (ch = PPI_CH0; ch <= PPI_CH11; ch ++) {
  63. WIC->PPI_CH_CFG[ch] &= ~WIC_PPI_CH_CFG_CH_EN_Msk;
  64. }
  65. }
  66. void ppi_trig_src_en(int trig_src, int enable)
  67. {
  68. int bit_offset = ppi_trig_src_mapping(trig_src);
  69. /* enable trigger source */
  70. if (bit_offset < 32) {
  71. if (enable) {
  72. WIC->TRIGGER_EN |= (1 << bit_offset);
  73. } else {
  74. WIC->TRIGGER_EN &= ~(1 << bit_offset);
  75. }
  76. } else {
  77. if (enable) {
  78. WIC->TRIGGER_EN1 |= (1 << (bit_offset - 32));
  79. } else {
  80. WIC->TRIGGER_EN1 &= ~(1 << (bit_offset - 32));
  81. }
  82. }
  83. }
  84. void ppi_task_trig_config(int ppi_channel, int task_select, int trig_src_select)
  85. {
  86. /* disable channel */
  87. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_CH_EN_Msk;
  88. WIC->PPI_CH_CFG[ppi_channel] |= ((unsigned int)0 << WIC_PPI_CH_CFG_CH_EN_Pos);
  89. /* select task */
  90. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_TASK_SEL_Msk;
  91. WIC->PPI_CH_CFG[ppi_channel] |= (task_select << WIC_PPI_CH_CFG_TASK_SEL_Pos);
  92. /* select trigger source */
  93. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_TRIGGER_SEL_Msk;
  94. WIC->PPI_CH_CFG[ppi_channel] |= (trig_src_select << WIC_PPI_CH_CFG_TRIGGER_SEL_Pos);
  95. /* enable channel */
  96. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_CH_EN_Msk;
  97. WIC->PPI_CH_CFG[ppi_channel] |= ((unsigned int)1 << WIC_PPI_CH_CFG_CH_EN_Pos);
  98. }
  99. int ppi_trig_src_is_pending(int ppi_trig_src)
  100. {
  101. int bit_offset = ppi_trig_src_mapping(ppi_trig_src);
  102. int pending;
  103. if (bit_offset < 32) {
  104. pending = (WIC->TRIGGER_PD & (1 << bit_offset));
  105. } else {
  106. pending = (WIC->TRIGGER_PD1 & (1 << (bit_offset - 32)));
  107. }
  108. return pending;
  109. }
  110. __sleepfunc void ppi_trig_src_clr_pending(int ppi_trig_src)
  111. {
  112. int bit_offset = ppi_trig_src_mapping(ppi_trig_src);
  113. if (bit_offset < 32) {
  114. WIC->TRIGGER_PD = (1 << bit_offset);
  115. } else {
  116. WIC->TRIGGER_PD1 = (1 << (bit_offset - 32));
  117. }
  118. return;
  119. }