soc_ppi.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134
  1. /*******************************************************************************
  2. * @file soc_ppi.c
  3. * @author MEMS Application Team
  4. * @version V1.0
  5. * @date 2020-08-12
  6. * @brief lark hardware access layer
  7. *******************************************************************************/
  8. /******************************************************************************/
  9. //includes
  10. /******************************************************************************/
  11. #include <soc.h>
  12. #include <linker/linker-defs.h>
  13. /******************************************************************************/
  14. //typedefs
  15. /******************************************************************************/
  16. typedef struct {
  17. volatile uint32_t TRIGGER_EN; /*!< (@ 0x00000000) Trigger Enable Register */
  18. volatile uint32_t TRIGGER_EN1; /*!< (@ 0x00000004) Trigger Enable Register */
  19. volatile uint32_t TRIGGER_PD; /*!< (@ 0x00000008) Trigger Pending Register */
  20. volatile uint32_t TRIGGER_PD1; /*!< (@ 0x0000000C) Trigger Pending Register */
  21. volatile uint32_t PPI_CH_CFG[12]; /*!< (@ 0x00000010) PPI Channel Config Register */
  22. } WIC_Type;
  23. #define WIC ((WIC_Type*) WIC_BASE)
  24. /* PPI_CH_CFG */
  25. #define WIC_PPI_CH_CFG_CH_EN_Pos (31UL) /*!< CH_EN (Bit 31) */
  26. #define WIC_PPI_CH_CFG_CH_EN_Msk (0x80000000UL) /*!< CH_EN (Bitfield-Mask: 0x01) */
  27. #define WIC_PPI_CH_CFG_TASK_SEL_Pos (8UL) /*!< TASK_SEL (Bit 8) */
  28. #define WIC_PPI_CH_CFG_TASK_SEL_Msk (0x1f00UL) /*!< TASK_SEL (Bitfield-Mask: 0x1f) */
  29. #define WIC_PPI_CH_CFG_TRIGGER_SEL_Pos (0UL) /*!< TRIGGER_SEL (Bit 0) */
  30. #define WIC_PPI_CH_CFG_TRIGGER_SEL_Msk (0x3fUL) /*!< TRIGGER_SEL (Bitfield-Mask: 0x3f) */
  31. /******************************************************************************/
  32. //functions
  33. /******************************************************************************/
  34. static __sleepfunc int ppi_trig_src_mapping(int trig_src)
  35. {
  36. if (trig_src <= TIMER4) {
  37. return trig_src;
  38. } else if (trig_src <= IO11_IRQ) {
  39. return (trig_src - IO0_IRQ + 16);
  40. } else if (trig_src <= SPIMT1_TASK7_CIP) {
  41. return (trig_src - SPIMT0_TASK0_CIP + 32);
  42. } else if (trig_src <= I2CMT0_TASK3_CIP) {
  43. return (trig_src - I2CMT0_TASK0_CIP + 48);
  44. } else {
  45. return (trig_src - I2CMT1_TASK0_CIP + 56);
  46. }
  47. }
  48. void ppi_init(void)
  49. {
  50. int ch;
  51. /* clear trigger enable */
  52. WIC->TRIGGER_EN = 0;
  53. WIC->TRIGGER_EN1 = 0;
  54. /* clear trigger pending */
  55. WIC->TRIGGER_PD = WIC->TRIGGER_PD;
  56. WIC->TRIGGER_PD1 = WIC->TRIGGER_PD1;
  57. /* disable channel */
  58. for (ch = PPI_CH0; ch <= PPI_CH11; ch ++) {
  59. WIC->PPI_CH_CFG[ch] &= ~WIC_PPI_CH_CFG_CH_EN_Msk;
  60. }
  61. }
  62. void ppi_trig_src_en(int trig_src, int enable)
  63. {
  64. int bit_offset = ppi_trig_src_mapping(trig_src);
  65. /* enable trigger source */
  66. if (bit_offset < 32) {
  67. if (enable) {
  68. WIC->TRIGGER_EN |= (1 << bit_offset);
  69. } else {
  70. WIC->TRIGGER_EN &= ~(1 << bit_offset);
  71. }
  72. } else {
  73. if (enable) {
  74. WIC->TRIGGER_EN1 |= (1 << (bit_offset - 32));
  75. } else {
  76. WIC->TRIGGER_EN1 &= ~(1 << (bit_offset - 32));
  77. }
  78. }
  79. }
  80. void ppi_task_trig_config(int ppi_channel, int task_select, int trig_src_select)
  81. {
  82. /* disable channel */
  83. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_CH_EN_Msk;
  84. WIC->PPI_CH_CFG[ppi_channel] |= ((unsigned int)0 << WIC_PPI_CH_CFG_CH_EN_Pos);
  85. /* select task */
  86. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_TASK_SEL_Msk;
  87. WIC->PPI_CH_CFG[ppi_channel] |= (task_select << WIC_PPI_CH_CFG_TASK_SEL_Pos);
  88. /* select trigger source */
  89. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_TRIGGER_SEL_Msk;
  90. WIC->PPI_CH_CFG[ppi_channel] |= (trig_src_select << WIC_PPI_CH_CFG_TRIGGER_SEL_Pos);
  91. /* enable channel */
  92. WIC->PPI_CH_CFG[ppi_channel] &= ~WIC_PPI_CH_CFG_CH_EN_Msk;
  93. WIC->PPI_CH_CFG[ppi_channel] |= ((unsigned int)1 << WIC_PPI_CH_CFG_CH_EN_Pos);
  94. }
  95. int ppi_trig_src_is_pending(int ppi_trig_src)
  96. {
  97. int bit_offset = ppi_trig_src_mapping(ppi_trig_src);
  98. int pending;
  99. if (bit_offset < 32) {
  100. pending = (WIC->TRIGGER_PD & (1 << bit_offset));
  101. } else {
  102. pending = (WIC->TRIGGER_PD1 & (1 << (bit_offset - 32)));
  103. }
  104. return pending;
  105. }
  106. __sleepfunc void ppi_trig_src_clr_pending(int ppi_trig_src)
  107. {
  108. int bit_offset = ppi_trig_src_mapping(ppi_trig_src);
  109. if (bit_offset < 32) {
  110. WIC->TRIGGER_PD = (1 << bit_offset);
  111. } else {
  112. WIC->TRIGGER_PD1 = (1 << (bit_offset - 32));
  113. }
  114. return;
  115. }