board.c 17 KB

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  1. /*
  2. * Copyright (c) 2019 Actions Semiconductor Co., Ltd
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. /**
  7. * @file
  8. * @brief board init functions
  9. */
  10. #include <kernel.h>
  11. #include <init.h>
  12. #include <device.h>
  13. #include <soc.h>
  14. #include "board.h"
  15. #include <drivers/gpio.h>
  16. #include <board_cfg.h>
  17. #define CONFIG_GPIO_HIGHZ (0x1000)
  18. static const struct acts_pin_config board_pin_config[] = {
  19. /*UART0 */
  20. #if IS_ENABLED(CONFIG_UART_0)
  21. /* uart0 tx */
  22. PIN_MFP_SET(GPIO_28, UART0_MFP_CFG),
  23. /* uart0 rx */
  24. PIN_MFP_SET(GPIO_29, UART0_MFP_CFG),
  25. #endif
  26. /*UART1 */
  27. #if IS_ENABLED(CONFIG_UART_1)
  28. /* uart1 tx */
  29. PIN_MFP_SET(GPIO_16, UART1_MFP_CFG),
  30. /* uart1 rx */
  31. PIN_MFP_SET(GPIO_17, UART1_MFP_CFG),
  32. #endif
  33. #if IS_ENABLED(CONFIG_SPI_FLASH_0)
  34. /* SPI0 CS */
  35. PIN_MFP_SET(GPIO_0, SPINOR_MFP_CFG),
  36. /* SPI0 MISO */
  37. PIN_MFP_SET(GPIO_1, SPINOR_MFP_CFG),
  38. /* SPI0 CLK */
  39. PIN_MFP_SET(GPIO_2, SPINOR_MFP_CFG),
  40. /* SPI0 MOSI */
  41. PIN_MFP_SET(GPIO_3, SPINOR_MFP_CFG),
  42. /* SPI0 IO2 */
  43. PIN_MFP_SET(GPIO_6, SPINOR_MFP_PU_CFG),
  44. /* SPI0 IO3 */
  45. PIN_MFP_SET(GPIO_7, SPINOR_MFP_PU_CFG),
  46. #endif
  47. #if IS_ENABLED(CONFIG_I2CMT_0)
  48. /* I2C CLK*/
  49. PIN_MFP_SET(GPIO_18, I2CMT_MFP_CFG(MFP0_I2CMT)),
  50. /* I2C DATA*/
  51. PIN_MFP_SET(GPIO_19, I2CMT_MFP_CFG(MFP0_I2CMT)),
  52. #endif
  53. #if IS_ENABLED(CONFIG_I2CMT_1)
  54. /* I2C CLK*/
  55. PIN_MFP_SET(GPIO_55, I2CMT_MFP_CFG(MFP1_I2CMT)),
  56. /* I2C DATA*/
  57. PIN_MFP_SET(GPIO_56, I2CMT_MFP_CFG(MFP1_I2CMT)),
  58. #endif
  59. #if IS_ENABLED(CONFIG_I2C_0)
  60. /* I2C CLK*/
  61. PIN_MFP_SET(GPIO_57, I2C_MFP_CFG(MFP0_I2C)),
  62. /* I2C DATA*/
  63. PIN_MFP_SET(GPIO_58, I2C_MFP_CFG(MFP0_I2C)),
  64. #endif
  65. #if IS_ENABLED(CONFIG_I2C_1)
  66. /* I2C CLK*/
  67. PIN_MFP_SET(GPIO_51, I2C_MFP_CFG(MFP1_I2C)),
  68. /* I2C DATA*/
  69. PIN_MFP_SET(GPIO_52, I2C_MFP_CFG(MFP1_I2C)),
  70. #endif
  71. #if IS_ENABLED(CONFIG_I2C_2)
  72. /* I2C CLK*/
  73. PIN_MFP_SET(GPIO_61, I2C_MFP_CFG(MFP2_I2C)),
  74. /* I2C DATA*/
  75. PIN_MFP_SET(GPIO_62, I2C_MFP_CFG(MFP2_I2C)),
  76. #endif
  77. #if IS_ENABLED(CONFIG_I2C_3)
  78. /* I2C CLK*/
  79. PIN_MFP_SET(GPIO_60, I2C_MFP_CFG(MFP3_I2C)),
  80. /* I2C DATA*/
  81. PIN_MFP_SET(GPIO_59, I2C_MFP_CFG(MFP3_I2C)),
  82. #endif
  83. #if IS_ENABLED(CONFIG_CEC)
  84. PIN_MFP_SET(GPIO_12, CEC_MFP_CFG),
  85. #endif
  86. #if IS_ENABLED(CONFIG_SPINAND_3)
  87. /*SPI3 IO2*/
  88. PIN_MFP_SET(GPIO_8, SPINAND_MFP_PU_CFG),
  89. /*SPI3 IO3*/
  90. PIN_MFP_SET(GPIO_9, SPINAND_MFP_PU_CFG),
  91. /*SPI3 SS*/
  92. PIN_MFP_SET(GPIO_10, SPINAND_MFP_CFG),
  93. /*SPI3 CLK*/
  94. PIN_MFP_SET(GPIO_11, SPINAND_MFP_CFG),
  95. /*SPI3 IO1*/
  96. PIN_MFP_SET(GPIO_12, SPINAND_MFP_CFG),
  97. /*SPI3 IO0*/
  98. PIN_MFP_SET(GPIO_13, SPINAND_MFP_CFG),
  99. #endif
  100. #if IS_ENABLED(CONFIG_AUDIO_I2SRX_0)
  101. /*I2SRX0 mclk*/
  102. PIN_MFP_SET(GPIO_53, I2SRX_MFP_CFG),
  103. /*I2SRX0 bclk*/
  104. PIN_MFP_SET(GPIO_54, I2SRX_MFP_CFG),
  105. /*I2SRX0 lrclk*/
  106. PIN_MFP_SET(GPIO_55, I2SRX_MFP_CFG),
  107. /*I2SRX0 d0*/
  108. PIN_MFP_SET(GPIO_56, I2SRX_MFP_CFG),
  109. #endif
  110. #if IS_ENABLED(CONFIG_SPI_1)
  111. /*SPI SS*/
  112. PIN_MFP_SET(GPIO_24, SPI_MFP_CFG(MFP_SPI1)),
  113. /* SPI CLK*/
  114. PIN_MFP_SET(GPIO_25, SPI_MFP_CFG(MFP_SPI1)),
  115. /* SPI MISO*/
  116. PIN_MFP_SET(GPIO_26, SPI_MFP_CFG(MFP_SPI1)),
  117. /* SPI MOSI*/
  118. PIN_MFP_SET(GPIO_27, SPI_MFP_CFG(MFP_SPI1)),
  119. #endif
  120. #if IS_ENABLED(CONFIG_SPI_2)
  121. /*SPI SS*/
  122. PIN_MFP_SET(GPIO_30, SPI_MFP_CFG(MFP_SPI2)),
  123. /* SPI CLK*/
  124. PIN_MFP_SET(GPIO_31, SPI_MFP_CFG(MFP_SPI2)),
  125. /* SPI MISO*/
  126. PIN_MFP_SET(GPIO_32, SPI_MFP_CFG(MFP_SPI2)),
  127. /* SPI MOSI*/
  128. PIN_MFP_SET(GPIO_33, SPI_MFP_CFG(MFP_SPI2)),
  129. #endif
  130. #if IS_ENABLED(CONFIG_SPI_3)
  131. /*SPI SS*/
  132. PIN_MFP_SET(GPIO_20, SPI_MFP_CFG(MFP_SPI3)),
  133. /* SPI CLK*/
  134. PIN_MFP_SET(GPIO_21, SPI_MFP_CFG(MFP_SPI3)),
  135. /* SPI MISO*/
  136. PIN_MFP_SET(GPIO_22, SPI_MFP_CFG(MFP_SPI3)),
  137. /* SPI MOSI*/
  138. PIN_MFP_SET(GPIO_23, SPI_MFP_CFG(MFP_SPI3)),
  139. #endif
  140. #if IS_ENABLED(CONFIG_SPIMT_0)
  141. /* SPI SS*/
  142. PIN_MFP_SET(GPIO_49, SPIMT_MFP_CFG(MFP0_SPIMT)),
  143. /* SPI CLK*/
  144. PIN_MFP_SET(GPIO_50, SPIMT_MFP_CFG(MFP0_SPIMT)),
  145. /* SPI MISO*/
  146. PIN_MFP_SET(GPIO_51, SPIMT_MFP_CFG(MFP0_SPIMT)),
  147. /* SPI MOSI*/
  148. PIN_MFP_SET(GPIO_52, SPIMT_MFP_CFG(MFP0_SPIMT)),
  149. /* SPI SS1*/
  150. PIN_MFP_SET(GPIO_61, SPIMT_MFP_CFG(MFP0_SPIMT)),
  151. #endif
  152. #if IS_ENABLED(CONFIG_SPIMT_1)
  153. /* SPI SS*/
  154. PIN_MFP_SET(GPIO_53, SPIMT_MFP_CFG(MFP1_SPIMT)),
  155. /* SPI CLK*/
  156. PIN_MFP_SET(GPIO_54, SPIMT_MFP_CFG(MFP1_SPIMT)),
  157. /* SPI MISO*/
  158. PIN_MFP_SET(GPIO_55, SPIMT_MFP_CFG(MFP1_SPIMT)),
  159. /* SPI MOSI*/
  160. PIN_MFP_SET(GPIO_56, SPIMT_MFP_CFG(MFP1_SPIMT)),
  161. #endif
  162. };
  163. #if IS_ENABLED(CONFIG_MMC_0)
  164. static const struct acts_pin_config board_mmc0_config[] = {
  165. /* MMC0 CMD*/
  166. PIN_MFP_SET(GPIO_0, SDC0_MFP_CFG_VAL),
  167. /* MMC0 CLK*/
  168. PIN_MFP_SET(GPIO_1, (GPIO_CTL_MFP(SDC0_MFP_SEL)|GPIO_CTL_PADDRV_LEVEL(3))),
  169. /* MMC0 DATA0 */
  170. PIN_MFP_SET(GPIO_2, SDC0_MFP_CFG_VAL),
  171. /* MMC0 DATA1 */
  172. PIN_MFP_SET(GPIO_3, SDC0_MFP_CFG_VAL),
  173. /* MMC0 DATA2 */
  174. PIN_MFP_SET(GPIO_6, SDC0_MFP_CFG_VAL),
  175. /* MMC0 DATA3 */
  176. PIN_MFP_SET(GPIO_7, SDC0_MFP_CFG_VAL),
  177. };
  178. #endif
  179. #if IS_ENABLED(CONFIG_AUDIO_SPDIFTX_0)
  180. static const struct acts_pin_config board_spdiftx0_config[] = {
  181. PIN_MFP_SET(GPIO_9, SPDIFTX_MFP_CFG),
  182. };
  183. #endif
  184. #if IS_ENABLED(CONFIG_AUDIO_SPDIFRX_0)
  185. static const struct acts_pin_config board_spdifrx0_config[] = {
  186. PIN_MFP_SET(GPIO_13, SPDIFRX_MFP_CFG)
  187. };
  188. #endif
  189. #if IS_ENABLED(CONFIG_AUDIO_I2STX_0)
  190. static const struct acts_pin_config board_i2stx0_config[] = {
  191. /*I2STX0 mclk*/
  192. PIN_MFP_SET(GPIO_49, I2STX_MFP_CFG),
  193. /*I2STX0 bclk*/
  194. PIN_MFP_SET(GPIO_50, I2STX_MFP_CFG),
  195. /*I2STX0 lrclk*/
  196. PIN_MFP_SET(GPIO_51, I2STX_MFP_CFG),
  197. /*I2STX0 d0*/
  198. PIN_MFP_SET(GPIO_52, I2STX_MFP_CFG),
  199. };
  200. #endif
  201. #if IS_ENABLED(CONFIG_SPINAND_0)
  202. static const struct acts_pin_config board_spinand_spi0_config[] = {
  203. /* SPI0 CS */
  204. PIN_MFP_SET(GPIO_0, SPINOR_MFP_CFG),
  205. /* SPI0 MISO */
  206. PIN_MFP_SET(GPIO_1, SPINOR_MFP_CFG),
  207. /* SPI0 CLK */
  208. PIN_MFP_SET(GPIO_2, SPINOR_MFP_CFG),
  209. /* SPI0 MOSI */
  210. PIN_MFP_SET(GPIO_3, SPINOR_MFP_CFG),
  211. /* SPI0 IO2 */
  212. PIN_MFP_SET(GPIO_6, SPINOR_MFP_PU_CFG),
  213. /* SPI0 IO3 */
  214. PIN_MFP_SET(GPIO_7, SPINOR_MFP_PU_CFG),
  215. };
  216. static const struct acts_pin_config board_spinand_spi0_gpiohighz_config[] = {
  217. /*SPI0 CS*/
  218. PIN_MFP_SET(GPIO_0, CONFIG_GPIO_HIGHZ),
  219. /*SPI0 MISO*/
  220. PIN_MFP_SET(GPIO_1, CONFIG_GPIO_HIGHZ),
  221. /*SPI0 CLK*/
  222. PIN_MFP_SET(GPIO_2, CONFIG_GPIO_HIGHZ),
  223. /*SPI0 MOSI*/
  224. PIN_MFP_SET(GPIO_3, CONFIG_GPIO_HIGHZ),
  225. /*SPI0 IO2*/
  226. PIN_MFP_SET(GPIO_6, CONFIG_GPIO_HIGHZ),
  227. /*SPI0 IO3*/
  228. PIN_MFP_SET(GPIO_7, CONFIG_GPIO_HIGHZ),
  229. };
  230. #endif
  231. #if IS_ENABLED(CONFIG_PWM)
  232. /* Look at CONFIG_PWM_PIN_CHAN_MAP select the available pwm gpio */
  233. static const struct pwm_acts_pin_config board_pwm_config[] = {
  234. /* GPIO57 used as pwm channel 1*/
  235. PWM_PIN_MFP_SET(GPIO_57, 1, PWM_MFP_CFG),
  236. };
  237. #endif
  238. #if IS_ENABLED(CONFIG_ACTS_BATTERY_NTC)
  239. /* GPIO20 and GPIO_23 are used as lradc2, they can't be used at the same time */
  240. static const struct acts_pin_config board_ntc_config[] = {
  241. PIN_MFP_SET(GPIO_20, BATNTC_MFP_CFG),
  242. PIN_MFP_SET(GPIO_23, CONFIG_GPIO_HIGHZ),
  243. };
  244. static const struct acts_pin_config board_ntc_ref_config[] = {
  245. PIN_MFP_SET(GPIO_20, CONFIG_GPIO_HIGHZ),
  246. /* GPIO23 must be a not use GPIO, use as lradc2 to get ntc scale value */
  247. PIN_MFP_SET(GPIO_23, BATNTC_REF_MFP_CFG),
  248. };
  249. static const struct acts_pin_config board_ntc_disable_config[] = {
  250. PIN_MFP_SET(GPIO_20, CONFIG_GPIO_HIGHZ),
  251. PIN_MFP_SET(GPIO_23, CONFIG_GPIO_HIGHZ),
  252. };
  253. #endif
  254. #if IS_ENABLED(CONFIG_PANEL)
  255. static const struct acts_pin_config board_lcd_pin_config[] = {
  256. /* lcd cs */
  257. PIN_MFP_SET(GPIO_30, (GPIO_CTL_MFP(LCD_MFP_SEL)|GPIO_CTL_PULLUP)),
  258. /* lcd scl */
  259. PIN_MFP_SET(GPIO_34, LCD_MFP_CLK_SEL),
  260. /* lcd_d0*/
  261. PIN_MFP_SET(GPIO_14, LCD_MFP_SEL),
  262. /* lcd_d1*/
  263. PIN_MFP_SET(GPIO_15, LCD_MFP_SEL),
  264. /* lcd_d2*/
  265. PIN_MFP_SET(GPIO_16, LCD_MFP_SEL),
  266. /* lcd_d3*/
  267. PIN_MFP_SET(GPIO_17, LCD_MFP_SEL),
  268. /* lcd power: IOVCC2 */
  269. PIN_MFP_SET(GPIO_33, 0x1F),
  270. };
  271. #endif
  272. #if IS_ENABLED(CONFIG_ADCKEY)
  273. #define CONFIG_ADCKEY_GPIO
  274. #ifdef CONFIG_ADCKEY_GPIO
  275. #define CONFIG_ADCKEY_GPIO_NUM (GPIO_21)
  276. #else
  277. #define CONFIG_ADCKEY_WIO_NUM (WIO_0)
  278. #define CONFIG_ADCKEY_WIO_MFP (3)
  279. #endif
  280. static void board_adckey_pinmux_init(void)
  281. {
  282. #ifdef CONFIG_ADCKEY_GPIO
  283. acts_pinmux_set(CONFIG_ADCKEY_GPIO_NUM, ADCKEY_MFP_CFG);
  284. #else
  285. sys_write32(CONFIG_ADCKEY_WIO_MFP, WIO0_CTL + (CONFIG_ADCKEY_WIO_NUM * 4));
  286. #endif
  287. }
  288. #endif
  289. static int board_early_init(const struct device *arg)
  290. {
  291. ARG_UNUSED(arg);
  292. acts_pinmux_setup_pins(board_pin_config, ARRAY_SIZE(board_pin_config));
  293. #if IS_ENABLED(CONFIG_MMC_0)
  294. acts_pinmux_setup_pins(board_mmc0_config, ARRAY_SIZE(board_mmc0_config));
  295. #endif
  296. #if IS_ENABLED(CONFIG_ADCKEY)
  297. board_adckey_pinmux_init();
  298. #endif
  299. #if IS_ENABLED(CONFIG_PANEL)
  300. acts_pinmux_setup_pins(board_lcd_pin_config, ARRAY_SIZE(board_lcd_pin_config));
  301. #endif
  302. #ifdef CONFIG_RTT_CONSOLE
  303. jtag_set();
  304. #endif
  305. return 0;
  306. }
  307. static int board_later_init(const struct device *arg)
  308. {
  309. ARG_UNUSED(arg);
  310. printk("%s %d: \n", __func__, __LINE__);
  311. return 0;
  312. }
  313. /* UART registers struct */
  314. struct acts_uart_reg {
  315. volatile uint32_t ctrl;
  316. volatile uint32_t rxdat;
  317. volatile uint32_t txdat;
  318. volatile uint32_t stat;
  319. volatile uint32_t br;
  320. } ;
  321. void uart_poll_out_ch(int c)
  322. {
  323. struct acts_uart_reg *uart = (struct acts_uart_reg*)UART0_REG_BASE;
  324. /* Wait for transmitter to be ready */
  325. while (uart->stat & BIT(6));
  326. /* send a character */
  327. uart->txdat = (uint32_t)c;
  328. }
  329. /*for early printk*/
  330. int arch_printk_char_out(int c)
  331. {
  332. if ('\n' == c)
  333. uart_poll_out_ch('\r');
  334. uart_poll_out_ch(c);
  335. return 0;
  336. }
  337. #if 1 //TODO:
  338. static const audio_input_map_t board_audio_input_map[] = {
  339. {AUDIO_LINE_IN0, ADC_CH_INPUT0P, ADC_CH_DISABLE, ADC_CH_INPUT0N, ADC_CH_DISABLE},
  340. {AUDIO_LINE_IN1, ADC_CH_INPUT0NP_DIFF, ADC_CH_INPUT1NP_DIFF, ADC_CH_DISABLE, ADC_CH_DISABLE},
  341. {AUDIO_LINE_IN2, ADC_CH_DISABLE, ADC_CH_INPUT1P, ADC_CH_DISABLE, ADC_CH_INPUT1N},
  342. {AUDIO_ANALOG_MIC0, ADC_CH_INPUT0NP_DIFF, ADC_CH_DISABLE, ADC_CH_DISABLE, ADC_CH_DISABLE},
  343. {AUDIO_ANALOG_MIC1, ADC_CH_INPUT0NP_DIFF, ADC_CH_DISABLE, ADC_CH_DISABLE, ADC_CH_DISABLE},
  344. {AUDIO_ANALOG_MIC2, ADC_CH_INPUT0NP_DIFF, ADC_CH_INPUT1NP_DIFF, ADC_CH_DISABLE, ADC_CH_DISABLE},
  345. {AUDIO_ANALOG_FM0, ADC_CH_INPUT0P, ADC_CH_DISABLE, ADC_CH_INPUT0N, ADC_CH_DISABLE},
  346. {AUDIO_DIGITAL_MIC0, ADC_CH_DMIC, ADC_CH_DMIC, ADC_CH_DISABLE, ADC_CH_DISABLE},
  347. };
  348. int board_audio_device_mapping(audio_input_map_t *input_map)
  349. {
  350. int i;
  351. if (!input_map)
  352. return -EINVAL;
  353. for (i = 0; i < ARRAY_SIZE(board_audio_input_map); i++) {
  354. if (input_map->audio_dev == board_audio_input_map[i].audio_dev) {
  355. input_map->ch0_input = board_audio_input_map[i].ch0_input;
  356. input_map->ch1_input = board_audio_input_map[i].ch1_input;
  357. input_map->ch2_input = board_audio_input_map[i].ch2_input;
  358. input_map->ch3_input = board_audio_input_map[i].ch3_input;
  359. break;
  360. }
  361. }
  362. if (i == ARRAY_SIZE(board_audio_input_map)) {
  363. printk("can not find out audio dev 0x%x\n", input_map->audio_dev);
  364. return -ENOENT;
  365. }
  366. return 0;
  367. }
  368. #endif
  369. #ifdef CONFIG_BOARD_EXTERNAL_PA_ENABLE
  370. #define EXTERN_PA_CTL1_PIN 53
  371. #define EXTERN_PA_CTL_SLEEP_OFF_TIME_MS 160
  372. #define EXTERN_PA_CTL_SLEEP_ON_TIME_MS 20
  373. //#define EXTERN_PA_EIO_CTRL_PIN (0)
  374. //#define EXTERN_PA_EIO_CTRL_PIN_NAME CONFIG_EXTEND_GPIO_NAME
  375. int board_extern_pa_ctl(u8_t pa_class, bool is_on)
  376. {
  377. #ifdef EXTERN_PA_CTL1_PIN
  378. const struct device *pa_gpio_dev;
  379. pa_gpio_dev = device_get_binding(CONFIG_GPIO_PIN2NAME(EXTERN_PA_CTL1_PIN));
  380. if (!pa_gpio_dev)
  381. return -EINVAL;
  382. #endif
  383. #ifdef EXTERN_PA_EIO_CTRL_PIN
  384. const struct device *egpio_dev;
  385. egpio_dev = device_get_binding(EXTERN_PA_EIO_CTRL_PIN_NAME);
  386. if (!egpio_dev)
  387. return -EINVAL;
  388. #endif
  389. if (!is_on) {
  390. /* external PA power off */
  391. printk("audio external PA power off\n");
  392. #ifdef EXTERN_PA_CTL1_PIN
  393. gpio_pin_configure(pa_gpio_dev, EXTERN_PA_CTL1_PIN % 32, GPIO_OUTPUT);
  394. gpio_pin_set(pa_gpio_dev, EXTERN_PA_CTL1_PIN % 32, 0);
  395. /* XA7191D PA spec depicts that shall disable PA for above 150ms when switch work mode */
  396. k_sleep(K_MSEC(EXTERN_PA_CTL_SLEEP_OFF_TIME_MS));
  397. #endif
  398. #ifdef EXTERN_PA_EIO_CTRL_PIN
  399. gpio_pin_configure(egpio_dev, EXTERN_PA_EIO_CTRL_PIN % 32, GPIO_OUTPUT);
  400. gpio_pin_set(egpio_dev, EXTERN_PA_EIO_CTRL_PIN % 32, 0);
  401. #endif
  402. } else {
  403. /* external PA power off */
  404. printk("audio external PA power on\n");
  405. #ifdef EXTERN_PA_CTL1_PIN
  406. gpio_pin_configure(pa_gpio_dev, EXTERN_PA_CTL1_PIN % 32, GPIO_OUTPUT);
  407. gpio_pin_set(pa_gpio_dev, EXTERN_PA_CTL1_PIN % 32, 1);
  408. k_sleep(K_MSEC(EXTERN_PA_CTL_SLEEP_ON_TIME_MS));
  409. #endif
  410. #ifdef EXTERN_PA_EIO_CTRL_PIN
  411. gpio_pin_configure(egpio_dev, EXTERN_PA_EIO_CTRL_PIN % 32, GPIO_OUTPUT);
  412. gpio_pin_set(egpio_dev, EXTERN_PA_EIO_CTRL_PIN % 32, 1);
  413. #endif
  414. }
  415. return 0;
  416. }
  417. #endif
  418. void board_get_mmc0_pinmux_info(struct board_pinmux_info *pinmux_info)
  419. {
  420. #if IS_ENABLED(CONFIG_MMC_0)
  421. pinmux_info->pins_config = board_mmc0_config;
  422. pinmux_info->pins_num = ARRAY_SIZE(board_mmc0_config);
  423. #endif
  424. }
  425. void board_get_spdiftx0_pinmux_info(struct board_pinmux_info *pinmux_info)
  426. {
  427. #if IS_ENABLED(CONFIG_AUDIO_SPDIFTX_0)
  428. pinmux_info->pins_config = board_spdiftx0_config;
  429. pinmux_info->pins_num = ARRAY_SIZE(board_spdiftx0_config);
  430. #endif
  431. }
  432. void board_get_spdifrx0_pinmux_info(struct board_pinmux_info *pinmux_info)
  433. {
  434. #if IS_ENABLED(CONFIG_AUDIO_SPDIFRX_0)
  435. pinmux_info->pins_config = board_spdifrx0_config;
  436. pinmux_info->pins_num = ARRAY_SIZE(board_spdifrx0_config);
  437. #endif
  438. }
  439. void board_get_i2stx0_pinmux_info(struct board_pinmux_info *pinmux_info)
  440. {
  441. #if IS_ENABLED(CONFIG_AUDIO_I2STX_0)
  442. pinmux_info->pins_config = board_i2stx0_config;
  443. pinmux_info->pins_num = ARRAY_SIZE(board_i2stx0_config);
  444. #endif
  445. }
  446. void board_get_pwm_pinmux_info(struct board_pwm_pinmux_info *pinmux_info)
  447. {
  448. #if IS_ENABLED(CONFIG_PWM)
  449. pinmux_info->pins_config = board_pwm_config;
  450. pinmux_info->pins_num = ARRAY_SIZE(board_pwm_config);
  451. #endif
  452. }
  453. void board_get_spinand_pinmux_info(struct board_pinmux_info *pinmux_info)
  454. {
  455. #if IS_ENABLED(CONFIG_SPINAND_0)
  456. pinmux_info->pins_config = board_spinand_spi0_config;
  457. pinmux_info->pins_num = ARRAY_SIZE(board_spinand_spi0_config);
  458. #endif
  459. }
  460. void board_get_spinand_gpiohighz_info(struct board_pinmux_info *pinmux_info)
  461. {
  462. #if IS_ENABLED(CONFIG_SPINAND_0)
  463. pinmux_info->pins_config = board_spinand_spi0_gpiohighz_config;
  464. pinmux_info->pins_num = ARRAY_SIZE(board_spinand_spi0_gpiohighz_config);
  465. #endif
  466. }
  467. void board_set_ntc_pinmux_info(bool enable, bool use_as_ntc)
  468. {
  469. #if IS_ENABLED(CONFIG_ACTS_BATTERY_NTC)
  470. if (enable) {
  471. if (use_as_ntc)
  472. acts_pinmux_setup_pins(board_ntc_config, ARRAY_SIZE(board_ntc_config));
  473. else
  474. acts_pinmux_setup_pins(board_ntc_ref_config, ARRAY_SIZE(board_ntc_ref_config));
  475. } else {
  476. acts_pinmux_setup_pins(board_ntc_disable_config, ARRAY_SIZE(board_ntc_disable_config));
  477. }
  478. #endif
  479. }
  480. #if IS_ENABLED(CONFIG_PANEL)
  481. static uint32_t lcd_pin_backup[3];
  482. void board_lcd_suspend(bool aod_en, bool early_suspend)
  483. {
  484. if (early_suspend) {
  485. lcd_pin_backup[0] = sys_read32(GPION_CTL(35)); /* lcd te */
  486. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(35));
  487. if (aod_en == false) {
  488. lcd_pin_backup[1] = sys_read32(GPION_CTL(21)); /* lcd power */
  489. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(21));
  490. lcd_pin_backup[2] = sys_read32(GPION_CTL(32)); /* lcd reset */
  491. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(32));
  492. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(30)); /* lcd cs */
  493. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(33)); /* lcd power IOVCC2 */
  494. }
  495. }
  496. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(34)); /* lcd scl */
  497. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(14)); /* lcd d0 */
  498. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(15)); /* lcd d1 */
  499. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(16)); /* lcd d2 */
  500. sys_write32(CONFIG_GPIO_HIGHZ, GPION_CTL(17)); /* lcd d3 */
  501. }
  502. void board_lcd_resume(bool aod_en, bool late_resume)
  503. {
  504. acts_pinmux_setup_pins(board_lcd_pin_config, ARRAY_SIZE(board_lcd_pin_config));
  505. if (late_resume) {
  506. sys_write32(lcd_pin_backup[0], GPION_CTL(35)); /* lcd te */
  507. if (aod_en == false) {
  508. sys_write32(lcd_pin_backup[1], GPION_CTL(21)); /* lcd GND_LEDK */
  509. sys_write32(lcd_pin_backup[2], GPION_CTL(32)); /* lcd reset */
  510. }
  511. }
  512. }
  513. #endif /* CONFIG_PANEL */
  514. SYS_INIT(board_early_init, PRE_KERNEL_1, 5);
  515. SYS_INIT(board_later_init, POST_KERNEL, 5);