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soc_memctrl.h

soc_memctrl.h 21 KB
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  1. /********************************************************************************
    2. 

  2.  *                            USDK(ZS283A)
    3. 

  3.  *                            Module: SYSTEM
    4. 

  4.  *                 Copyright(c) 2003-2017 Actions Semiconductor,
    5. 

  5.  *                            All Rights Reserved.
    6. 

  6.  *
    7. 

  7.  * History:
    8. 

  8.  *      <author>      <time>                      <version >          <desc>
    9. 

  9.  *      wuyufan   2018-10-12-PM12:48:04             1.0             build this file
    10. 

  10.  ********************************************************************************/
    11. 

  11. /*!
    12. 

  12.  * \file     soc_memctrl.h
    13. 

  13.  * \brief
    14. 

  14.  * \author
    15. 

  15.  * \version  1.0
    16. 

  16.  * \date  2018-10-12-PM12:48:04
    17. 

  17.  *******************************************************************************/
    18. 

  18. 

  19. #ifndef SOC_MEMCTRL_H_
    20. 

  20. #define SOC_MEMCTRL_H_
    21. 

  21. 

  22. 

  23. //--------------MemoryController-------------------------------------------//
    24. 

  24. //--------------Register Address---------------------------------------//
    25. 

  25. #define     MemoryController_BASE                                             0x40010000
    26. 

  26. #define     MEMORYCTL                                                         (MemoryController_BASE+0x00000000)
    27. 

  27. #define     CPU_ERROR_ADDR                                                    (MemoryController_BASE+0x00000008)
    28. 

  28. #define     MEMORYCTL2                                                        (MemoryController_BASE+0x00000020)
    29. 

  29. #define     DBGCTL                                                            (MemoryController_BASE+0x00000040)
    30. 

  30. #define     DSPPAGEADDR0                                                      (MemoryController_BASE+0x00000080)
    31. 

  31. #define     DSPPAGEADDR1                                                      (MemoryController_BASE+0x00000084)
    32. 

  32. #define     DSPPAGEADDR2                                                      (MemoryController_BASE+0x00000088)
    33. 

  33. #define     DSPPAGEADDR3                                                      (MemoryController_BASE+0x0000008c)
    34. 

  34. #define     MPUIE                                                             (MemoryController_BASE+0x00000100)
    35. 

  35. #define     MPUIP                                                             (MemoryController_BASE+0x00000104)
    36. 

  36. #define     MPUCTL0                                                           (MemoryController_BASE+0x00000110)
    37. 

  37. #define     MPUBASE0                                                          (MemoryController_BASE+0x00000114)
    38. 

  38. #define     MPUEND0                                                           (MemoryController_BASE+0x00000118)
    39. 

  39. #define     MPUERRADDR0                                                       (MemoryController_BASE+0x0000011c)
    40. 

  40. #define     MPUCTL1                                                           (MemoryController_BASE+0x00000120)
    41. 

  41. #define     MPUBASE1                                                          (MemoryController_BASE+0x00000124)
    42. 

  42. #define     MPUEND1                                                           (MemoryController_BASE+0x00000128)
    43. 

  43. #define     MPUERRADDR1                                                       (MemoryController_BASE+0x0000012c)
    44. 

  44. #define     MPUCTL2                                                           (MemoryController_BASE+0x00000130)
    45. 

  45. #define     MPUBASE2                                                          (MemoryController_BASE+0x00000134)
    46. 

  46. #define     MPUEND2                                                           (MemoryController_BASE+0x00000138)
    47. 

  47. #define     MPUERRADDR2                                                       (MemoryController_BASE+0x0000013c)
    48. 

  48. #define     MPUCTL3                                                           (MemoryController_BASE+0x00000140)
    49. 

  49. #define     MPUBASE3                                                          (MemoryController_BASE+0x00000144)
    50. 

  50. #define     MPUEND3                                                           (MemoryController_BASE+0x00000148)
    51. 

  51. #define     MPUERRADDR3                                                       (MemoryController_BASE+0x0000014c)
    52. 

  52. #define     BIST_EN0                                                          (MemoryController_BASE+0x00000200)
    53. 

  53. #define     BIST_FIN0                                                         (MemoryController_BASE+0x00000204)
    54. 

  54. #define     BIST_INFO0                                                        (MemoryController_BASE+0x00000208)
    55. 

  55. #define     BIST_EN1                                                          (MemoryController_BASE+0x0000020c)
    56. 

  56. #define     BIST_FIN1                                                         (MemoryController_BASE+0x00000210)
    57. 

  57. #define     BIST_INFO1                                                        (MemoryController_BASE+0x00000214)
    58. 

  58. #define     SPI_CACHE_MAPPING_ADDR0                                           (MemoryController_BASE+0x00000300)
    59. 

  59. #define     SPI_CACHE_ADDR0_ENTRY                                             (MemoryController_BASE+0x00000304)
    60. 

  60. #define     SPI_CACHE_MAPPING_ADDR1                                           (MemoryController_BASE+0x00000308)
    61. 

  61. #define     SPI_CACHE_ADDR1_ENTRY                                             (MemoryController_BASE+0x0000030c)
    62. 

  62. #define     SPI_CACHE_MAPPING_ADDR2                                           (MemoryController_BASE+0x00000310)
    63. 

  63. #define     SPI_CACHE_ADDR2_ENTRY                                             (MemoryController_BASE+0x00000314)
    64. 

  64. #define     SPI_CACHE_MAPPING_ADDR3                                           (MemoryController_BASE+0x00000318)
    65. 

  65. #define     SPI_CACHE_ADDR3_ENTRY                                             (MemoryController_BASE+0x0000031c)
    66. 

  66. #define     SPI_CACHE_MAPPING_ADDR4                                           (MemoryController_BASE+0x00000320)
    67. 

  67. #define     SPI_CACHE_ADDR4_ENTRY                                             (MemoryController_BASE+0x00000324)
    68. 

  68. #define     SPI_CACHE_MAPPING_ADDR5                                           (MemoryController_BASE+0x00000328)
    69. 

  69. #define     SPI_CACHE_ADDR5_ENTRY                                             (MemoryController_BASE+0x0000032c)
    70. 

  70. #define     SPI_CACHE_MAPPING_ADDR6                                           (MemoryController_BASE+0x00000330)
    71. 

  71. #define     SPI_CACHE_ADDR6_ENTRY                                             (MemoryController_BASE+0x00000334)
    72. 

  72. #define     SPI_CACHE_MAPPING_ADDR7                                           (MemoryController_BASE+0x00000338)
    73. 

  73. #define     SPI_CACHE_ADDR7_ENTRY                                             (MemoryController_BASE+0x0000033c)
    74. 

  74. 

  75. #define     CACHE_MAPPING_ITEM_NUM			(8)
    76. 

  76. 

  77. 

  78. #define     MEMORYCTL_BUSERROR_BIT          BIT(3)
    79. 

  79. 

  80. 

  81. #if 0
    82. 

  82. #define     MEMORYCTL                                                         (MEMORY_CONTROLLER_REG_BASE+0x00000000)
    83. 

  83. #define     ALTERNATEINSTR0                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000004)
    84. 

  84. #define     ALTERNATEINSTR1                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000008)
    85. 

  85. #define     ALTERNATEINSTR2                                                   (MEMORY_CONTROLLER_REG_BASE+0x0000000c)
    86. 

  86. #define     ALTERNATEINSTR3                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000010)
    87. 

  87. #define     ALTERNATEINSTR4                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000014)
    88. 

  88. #define     ALTERNATEINSTR5                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000018)
    89. 

  89. #define     ALTERNATEINSTR6                                                   (MEMORY_CONTROLLER_REG_BASE+0x0000001c)
    90. 

  90. #define     ALTERNATEINSTR7                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000020)
    91. 

  91. #define     ALTERNATEINSTR8                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000024)
    92. 

  92. #define     ALTERNATEINSTR9                                                   (MEMORY_CONTROLLER_REG_BASE+0x00000028)
    93. 

  93. #define     ALTERNATEINSTR10                                                  (MEMORY_CONTROLLER_REG_BASE+0x0000002c)
    94. 

  94. #define     ALTERNATEINSTR11                                                  (MEMORY_CONTROLLER_REG_BASE+0x00000030)
    95. 

  95. #define     ALTERNATEINSTR12                                                  (MEMORY_CONTROLLER_REG_BASE+0x00000034)
    96. 

  96. #define     ALTERNATEINSTR13                                                  (MEMORY_CONTROLLER_REG_BASE+0x00000038)
    97. 

  97. #define     ALTERNATEINSTR14                                                  (MEMORY_CONTROLLER_REG_BASE+0x0000003c)
    98. 

  98. #define     ALTERNATEINSTR15                                                  (MEMORY_CONTROLLER_REG_BASE+0x00000040)
    99. 

  99. #define     FIXADDR0                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000044)
    100. 

  100. #define     FIXADDR1                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000048)
    101. 

  101. #define     FIXADDR2                                                          (MEMORY_CONTROLLER_REG_BASE+0x0000004c)
    102. 

  102. #define     FIXADDR3                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000050)
    103. 

  103. #define     FIXADDR4                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000054)
    104. 

  104. #define     FIXADDR5                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000058)
    105. 

  105. #define     FIXADDR6                                                          (MEMORY_CONTROLLER_REG_BASE+0x0000005c)
    106. 

  106. #define     FIXADDR7                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000060)
    107. 

  107. #define     FIXADDR8                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000064)
    108. 

  108. #define     FIXADDR9                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000068)
    109. 

  109. #define     FIXADDR10                                                         (MEMORY_CONTROLLER_REG_BASE+0x0000006c)
    110. 

  110. #define     FIXADDR11                                                         (MEMORY_CONTROLLER_REG_BASE+0x00000070)
    111. 

  111. #define     FIXADDR12                                                         (MEMORY_CONTROLLER_REG_BASE+0x00000074)
    112. 

  112. #define     FIXADDR13                                                         (MEMORY_CONTROLLER_REG_BASE+0x00000078)
    113. 

  113. #define     FIXADDR14                                                         (MEMORY_CONTROLLER_REG_BASE+0x0000007c)
    114. 

  114. #define     FIXADDR15                                                         (MEMORY_CONTROLLER_REG_BASE+0x00000080)
    115. 

  115. #define     BIST_EN                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000084)
    116. 

  116. #define     BIST_FIN                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000088)
    117. 

  117. #define     BIST_INFO                                                         (MEMORY_CONTROLLER_REG_BASE+0x0000008c)
    118. 

  118. #define     MAPPING_ADDR0                                                     (MEMORY_CONTROLLER_REG_BASE+0x00000090)
    119. 

  119. #define     ADDR0_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x00000094)
    120. 

  120. #define     MAPPING_ADDR1                                                     (MEMORY_CONTROLLER_REG_BASE+0x00000098)
    121. 

  121. #define     ADDR1_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x0000009c)
    122. 

  122. #define     MAPPING_ADDR2                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000a0)
    123. 

  123. #define     ADDR2_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000a4)
    124. 

  124. #define     MAPPING_ADDR3                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000a8)
    125. 

  125. #define     ADDR3_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000ac)
    126. 

  126. #define     MAPPING_ADDR4                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000b0)
    127. 

  127. #define     ADDR4_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000b4)
    128. 

  128. #define     MAPPING_ADDR5                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000b8)
    129. 

  129. #define     ADDR5_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000bc)
    130. 

  130. #define     MAPPING_ADDR6                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000c0)
    131. 

  131. #define     ADDR6_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000c4)
    132. 

  132. #define     MAPPING_ADDR7                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000c8)
    133. 

  133. #define     ADDR7_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000cc)
    134. 

  134. #define     MAPPING_ADDR8                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000d0)
    135. 

  135. #define     ADDR8_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000d4)
    136. 

  136. #define     MAPPING_ADDR9                                                     (MEMORY_CONTROLLER_REG_BASE+0x000000d8)
    137. 

  137. #define     ADDR9_ENTRY                                                       (MEMORY_CONTROLLER_REG_BASE+0x000000dc)
    138. 

  138. #define     MAPPING_ADDR10                                                    (MEMORY_CONTROLLER_REG_BASE+0x000000e0)
    139. 

  139. #define     ADDR10_ENTRY                                                      (MEMORY_CONTROLLER_REG_BASE+0x000000e4)
    140. 

  140. #define     MAPPING_ADDR11                                                    (MEMORY_CONTROLLER_REG_BASE+0x000000e8)
    141. 

  141. #define     ADDR11_ENTRY                                                      (MEMORY_CONTROLLER_REG_BASE+0x000000ec)
    142. 

  142. #define     MAPPING_ADDR12                                                    (MEMORY_CONTROLLER_REG_BASE+0x000000f0)
    143. 

  143. #define     ADDR12_ENTRY                                                      (MEMORY_CONTROLLER_REG_BASE+0x000000f4)
    144. 

  144. #define     MAPPING_ADDR13                                                    (MEMORY_CONTROLLER_REG_BASE+0x000000f8)
    145. 

  145. #define     ADDR13_ENTRY                                                      (MEMORY_CONTROLLER_REG_BASE+0x000000fc)
    146. 

  146. #define     MAPPING_ADDR14                                                    (MEMORY_CONTROLLER_REG_BASE+0x00000100)
    147. 

  147. #define     ADDR14_ENTRY                                                      (MEMORY_CONTROLLER_REG_BASE+0x00000104)
    148. 

  148. #define     MAPPING_ADDR15                                                    (MEMORY_CONTROLLER_REG_BASE+0x00000108)
    149. 

  149. #define     ADDR15_ENTRY                                                      (MEMORY_CONTROLLER_REG_BASE+0x0000010c)
    150. 

  150. #define     DATA_ADDRESS_ERROR_INFO                                           (MEMORY_CONTROLLER_REG_BASE+0x00000110)
    151. 

  151. #define     INSTRUCTION_ADDRESS_ERROR_INFO                                    (MEMORY_CONTROLLER_REG_BASE+0x00000114)
    152. 

  152. #define     SYMBOL_TABLE_PTR0                                                 (MEMORY_CONTROLLER_REG_BASE+0x00000118)
    153. 

  153. #define     SYMBOL_TABLE_PTR1                                                 (MEMORY_CONTROLLER_REG_BASE+0x0000011c)
    154. 

  154. #define     SYMBOL_TABLE_PTR2                                                 (MEMORY_CONTROLLER_REG_BASE+0x00000120)
    155. 

  155. #define     SYMBOL_TABLE_PTR3                                                 (MEMORY_CONTROLLER_REG_BASE+0x00000124)
    156. 

  156. #define     MPUIE_LOW                                                         (MEMORY_CONTROLLER_REG_BASE+0x00000140)
    157. 

  157. #define     MPUIE_HIGH                                                        (MEMORY_CONTROLLER_REG_BASE+0x00000144)
    158. 

  158. #define     MPUIP_LOW                                                         (MEMORY_CONTROLLER_REG_BASE+0x00000148)
    159. 

  159. #define     MPUIP_HIGH                                                        (MEMORY_CONTROLLER_REG_BASE+0x0000014c)
    160. 

  160. #define     MPUCTL0                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000150)
    161. 

  161. #define     MPUBASE0                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000154)
    162. 

  162. #define     MPUEND0                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000158)
    163. 

  163. #define     MPUERRADDR0                                                       (MEMORY_CONTROLLER_REG_BASE+0x0000015c)
    164. 

  164. #define     MPUCTL1                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000160)
    165. 

  165. #define     MPUBASE1                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000164)
    166. 

  166. #define     MPUEND1                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000168)
    167. 

  167. #define     MPUERRADDR1                                                       (MEMORY_CONTROLLER_REG_BASE+0x0000016c)
    168. 

  168. #define     MPUCTL2                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000170)
    169. 

  169. #define     MPUBASE2                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000174)
    170. 

  170. #define     MPUEND2                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000178)
    171. 

  171. #define     MPUERRADDR2                                                       (MEMORY_CONTROLLER_REG_BASE+0x0000017c)
    172. 

  172. #define     MPUCTL3                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000180)
    173. 

  173. #define     MPUBASE3                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000184)
    174. 

  174. #define     MPUEND3                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000188)
    175. 

  175. #define     MPUERRADDR3                                                       (MEMORY_CONTROLLER_REG_BASE+0x0000018c)
    176. 

  176. #define     MPUCTL4                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000190)
    177. 

  177. #define     MPUBASE4                                                          (MEMORY_CONTROLLER_REG_BASE+0x00000194)
    178. 

  178. #define     MPUEND4                                                           (MEMORY_CONTROLLER_REG_BASE+0x00000198)
    179. 

  179. #define     MPUERRADDR4                                                       (MEMORY_CONTROLLER_REG_BASE+0x0000019c)
    180. 

  180. #define     MPUCTL5                                                           (MEMORY_CONTROLLER_REG_BASE+0x000001a0)
    181. 

  181. #define     MPUBASE5                                                          (MEMORY_CONTROLLER_REG_BASE+0x000001a4)
    182. 

  182. #define     MPUEND5                                                           (MEMORY_CONTROLLER_REG_BASE+0x000001a8)
    183. 

  183. #define     MPUERRADDR5                                                       (MEMORY_CONTROLLER_REG_BASE+0x000001ac)
    184. 

  184. #define     MPUCTL6                                                           (MEMORY_CONTROLLER_REG_BASE+0x000001b0)
    185. 

  185. #define     MPUBASE6                                                          (MEMORY_CONTROLLER_REG_BASE+0x000001b4)
    186. 

  186. #define     MPUEND6                                                           (MEMORY_CONTROLLER_REG_BASE+0x000001b8)
    187. 

  187. #define     MPUERRADDR6                                                       (MEMORY_CONTROLLER_REG_BASE+0x000001bc)
    188. 

  188. #define     MPUCTL7                                                           (MEMORY_CONTROLLER_REG_BASE+0x000001c0)
    189. 

  189. #define     MPUBASE7                                                          (MEMORY_CONTROLLER_REG_BASE+0x000001c4)
    190. 

  190. #define     MPUEND7                                                           (MEMORY_CONTROLLER_REG_BASE+0x000001c8)
    191. 

  191. #define     MPUERRADDR7                                                       (MEMORY_CONTROLLER_REG_BASE+0x000001cc)
    192. 

  192. #define     CACHE_CONFLICT_ADDR                                               (MEMORY_CONTROLLER_REG_BASE+0x00000200)
    193. 

  193. 

  194. 

  195. #define     CACHE_MAPPING_REGISTER_BASE	    (MAPPING_ADDR0)
    196. 

  196. 

  197. #define     CACHE_MAPPING_ITEM_NUM			(16)
    198. 

  198. 

  199. #define     MEMORYCTL_BUSERROR_BIT          BIT(18)
    200. 

  200. 

  201. #define     CACHE_LINE_SIZE                 32
    202. 

  202. #define     CACHE_CRC_LINE_SIZE             34
    203. 

  203. 

  204. #define     CACHE_SIZE_32KB                 (0)
    205. 

  205. #define     CACHE_SIZE_16KB                 (1)
    206. 

  206. 

  207. #endif
    208. 

  208. 

  209. 

  210. typedef struct {
    211. 

  211. 	volatile unsigned int mapping_addr;
    212. 

  212. 	volatile unsigned int mapping_entry;
    213. 

  213. } cache_mapping_register_t;
    214. 

  214. 

  215. typedef struct
    216. 

  216. {
    217. 

  217.     volatile uint32_t MPUCTL;
    218. 

  218.     volatile uint32_t MPUBASE;
    219. 

  219.     volatile uint32_t MPUEND;
    220. 

  220.     volatile uint32_t MPUERRADDR;
    221. 

  221. }mpu_base_register_t;
    222. 

  222. 

  223. void soc_memctrl_set_mapping(int idx, u32_t cpu_addr, u32_t nor_bus_addr);
    224. 

  224. int soc_memctrl_mapping(u32_t cpu_addr, u32_t nor_phy_addr, int enable_crc);
    225. 

  225. int soc_memctrl_unmapping(u32_t map_addr);
    226. 

  226. void *soc_memctrl_create_temp_mapping(u32_t nor_phy_addr, int enable_crc);
    227. 

  227. void soc_memctrl_clear_temp_mapping(void *cpu_addr);
    228. 

  228. u32_t soc_memctrl_cpu_to_nor_phy_addr(u32_t cpu_addr);
    229. 

  229. 

  230. void soc_memctrl_config_cache_size(int cache_size_mode);
    231. 

  231. void soc_memctrl_cache_invalid(void);
    232. 

  232. 

  233. static inline void soc_memctrl_set_dsp_mapping(int idx, u32_t map_addr,
    234. 

  234. 					  u32_t phy_addr)
    235. 

  235. {
    236. 

  236.     return;
    237. 

  237. }
    238. 

  238. 

  239. static inline u32_t soc_memctrl_cpu_addr_to_bus_addr(u32_t cpu_addr)
    240. 

  240. {
    241. 

  241. 	u32_t bus_addr;
    242. 

  242. 

  243. 	if (cpu_addr < 0x10000000)
    244. 

  244. 		bus_addr = 0x10000000;
    245. 

  245. 	else
    246. 

  246. 		bus_addr = cpu_addr & ~0xe0000000;
    247. 

  247. 

  248. 	return bus_addr;
    249. 

  249. }
    250. 

  250. 

  251. #endif /* SOC_MEMCTRL_H_ */
    252.