bt_drv.c 31 KB

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  1. /*
  2. * Copyright (c) 2020 Actions Semiconductor Co., Ltd
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. /**
  7. * @file
  8. * @brief Bluetooth driver for Actions SoC
  9. */
  10. #include <stdio.h>
  11. #include <string.h>
  12. #include <errno.h>
  13. #include <sys/__assert.h>
  14. #include <stdbool.h>
  15. #include <kernel.h>
  16. #include <device.h>
  17. #include <init.h>
  18. #include <drivers/ipmsg.h>
  19. #include <sys/printk.h>
  20. #include <sys/byteorder.h>
  21. #include <drivers/bluetooth/bt_drv.h>
  22. #include <compensation.h>
  23. #include "ecc_acts.h"
  24. #ifdef CONFIG_PROPERTY
  25. #include <property_manager.h>
  26. #endif
  27. #include <logging/log.h>
  28. LOG_MODULE_REGISTER(bt_drv, CONFIG_LOG_DEFAULT_LEVEL);
  29. #define CONFIG_HCI_RX_THREAD 1
  30. #define BTDRV_EFUSE_CAP_RECORD (CONFIG_COMPENSATION_FREQ_INDEX_NUM)
  31. #ifdef CONFIG_BT_HCI_TX_PRINT
  32. static const char *tx_type_str[] = {
  33. "NULL:",
  34. "TX:01 ",
  35. "TX:02 ",
  36. "TX:03 ",
  37. "TX:04 "
  38. };
  39. #endif
  40. #ifdef CONFIG_BT_HCI_RX_PRINT
  41. static const char *rx_type_str[] = {
  42. "NULL:",
  43. "RX:01 ",
  44. "RX:02 ",
  45. "RX:03 ",
  46. "RX:04 ",
  47. };
  48. #endif
  49. #define BTC_BIN_ADDR (0x08100000)
  50. #define BTC_BIN_SIZE (0x34000)
  51. enum {
  52. BT_CPU_ENABLE,
  53. BT_CPU_READY,
  54. #ifdef CONFIG_BT_CTRL_TWS
  55. /* Need to clear bt cpu tws0 pending */
  56. BT_CPU_TWS0_PENDING,
  57. BT_CPU_TWS1_PENDING,
  58. #endif
  59. BT_CPU_NUM_FLAGS,
  60. };
  61. #ifdef CONFIG_BT_CTRL_REG
  62. enum {
  63. PENDING_READ_BB_REG,
  64. PENDING_READ_RF_REG,
  65. NUM_REG_FLAGS,
  66. };
  67. #endif
  68. static struct {
  69. struct device *dev;
  70. ATOMIC_DEFINE(flags, BT_CPU_NUM_FLAGS);
  71. btdrv_hci_cb_t *hci_cb;
  72. struct k_sem ready_sem;
  73. struct k_sem hci_rx_sem;
  74. #ifdef CONFIG_BT_CTRL_LOG
  75. struct k_sem log_rx_sem;
  76. #endif
  77. /* message send to bt cpu */
  78. rbuf_msg_t msg;
  79. uint32_t msg_tx_id;
  80. uint32_t msg_rx_id;
  81. uint32_t hci_tx_id;
  82. uint32_t hci_rx_id;
  83. uint32_t log_rx_id;
  84. #ifdef CONFIG_BT_CTRL_TWS
  85. btdrv_tws_cb_t tws0_cb;
  86. btdrv_tws_cb_t tws1_cb;
  87. uint32_t tws_tx_id[2];
  88. uint32_t tws_rx_id[2];
  89. #endif
  90. } btc = {
  91. .ready_sem = Z_SEM_INITIALIZER(btc.ready_sem, 0, 1),
  92. .hci_rx_sem = Z_SEM_INITIALIZER(btc.hci_rx_sem, 0, UINT_MAX),
  93. #ifdef CONFIG_BT_CTRL_LOG
  94. .log_rx_sem = Z_SEM_INITIALIZER(btc.log_rx_sem, 0, UINT_MAX),
  95. #endif
  96. };
  97. #ifdef CONFIG_BT_CTRL_REG
  98. static struct {
  99. struct k_work work;
  100. ATOMIC_DEFINE(flag, NUM_REG_FLAGS);
  101. uint16_t size;
  102. /* baseband register address */
  103. uint32_t bb_reg;
  104. uint16_t rf_reg;
  105. } btc_reg;
  106. #endif
  107. #ifdef CONFIG_BT_ECC_ACTS
  108. static struct ecc_info {
  109. struct k_work work;
  110. ATOMIC_DEFINE(flag, NUM_ECC_FLAGS);
  111. /* ecc request data size */
  112. uint16_t size;
  113. /* ecc request data */
  114. uint8_t req[128];
  115. /* ecc response data */
  116. uint8_t rsp[128];
  117. } btc_ecc;
  118. #endif
  119. #ifdef CONFIG_BT_CTRL_TWS
  120. struct btc_tws {
  121. /* tws interrupt time */
  122. uint32_t bt_clk;
  123. uint16_t intra_off;
  124. /* timer mode: us/navtive */
  125. uint8_t mode;
  126. /* flag of esco/iso pkt */
  127. uint8_t flag;
  128. /* tws interrupt type */
  129. uint8_t type;
  130. /* clear interrup pending counter */
  131. uint8_t pcnt;
  132. /* write data counter */
  133. uint8_t wcnt;
  134. /* read data counter */
  135. uint8_t rcnt;
  136. /* pkt sequence number */
  137. uint16_t seq;
  138. /* data len of hci pkt */
  139. uint16_t data_len;
  140. /* hci pkt */
  141. uint8_t data[256];
  142. } __packed;
  143. #define BT_TWS_SIZE sizeof(struct btc_tws)
  144. /* tws_tx: main -> bt. tws_rx: bt -> main. */
  145. static struct btc_tws *tws_rx[2];
  146. static struct btc_tws *tws_tx[2];
  147. #endif
  148. #if CONFIG_HCI_RX_THREAD
  149. static K_THREAD_STACK_DEFINE(rx_thread_stack, 1024);
  150. static struct k_thread rx_thread_data;
  151. #endif
  152. #ifdef CONFIG_BT_CTRL_LOG
  153. #define BTC_LOG_SIZE (256)
  154. #define CONFIG_BT_LOG_PRIO (1)
  155. #define CONFIG_BT_LOG_STACK_SIZE (1024)
  156. static K_THREAD_STACK_DEFINE(log_thread_stack, CONFIG_BT_LOG_STACK_SIZE);
  157. static struct k_thread log_thread_data;
  158. static char log_buf[BTC_LOG_SIZE + 1];
  159. #endif
  160. /* custom hci buf header */
  161. struct bt_hci_hdr {
  162. /* length of hci packet, round up to 4-byte */
  163. uint16_t len;
  164. /* hci packet type */
  165. uint8_t type;
  166. uint8_t rfu;
  167. } __packed;
  168. #define BT_HCI_HDR_SIZE sizeof(struct bt_hci_hdr)
  169. /* hci rx/tx data transmit on rbuf */
  170. static struct hci_data {
  171. /* hci header */
  172. union {
  173. struct bt_hci_hdr hdr;
  174. uint8_t hdr_buff[BT_HCI_HDR_SIZE];
  175. };
  176. /* hci packet, Core 5.2 [Vol 4, Part E, 5.4] */
  177. uint8_t *pkt;
  178. /* length of hci packet */
  179. uint16_t pkt_len;
  180. /* total length of hci data, round up to 4-byte */
  181. uint16_t total;
  182. /* current offset of hci packet */
  183. uint16_t offset;
  184. /* need to copy header if false */
  185. uint8_t hdr_len;
  186. bool has_hdr;
  187. } rx, tx;
  188. static int print_hex(const char *prefix, const uint8_t *data, int size)
  189. {
  190. int n = 0;
  191. if (!size) {
  192. printk("%s zero-length signal packet\n", prefix);
  193. return 0;
  194. }
  195. if (prefix) {
  196. printk("%s", prefix);
  197. }
  198. while (size--) {
  199. printk("%02x ", *data++);
  200. n++;
  201. if (n % 16 == 0) {
  202. printk("\n");
  203. }
  204. }
  205. if (n % 16) {
  206. printk("\n");
  207. }
  208. return 0;
  209. }
  210. static void rbuf_info_dump(rbuf_t *rbuf)
  211. {
  212. if ((rbuf->tmp_head != rbuf->head) || (rbuf->tmp_tail != rbuf->tail)) {
  213. printk("tmp head %u, head %u, tmp tail %u, tail %u\n",
  214. rbuf->tmp_head, rbuf->head, rbuf->tmp_tail, rbuf->tail);
  215. }
  216. }
  217. #ifdef CONFIG_BT_CTRL_LOG
  218. static int btc_log_handler(void *context, void *data, unsigned int size)
  219. {
  220. #if 1
  221. memcpy((void *)log_buf, data, size);
  222. log_buf[size] = '\0';
  223. printk("%s", log_buf);
  224. #else
  225. printk("%s", (char *)buf);
  226. #endif
  227. return size;
  228. }
  229. static void log_thread(void *p1, void *p2, void *p3)
  230. {
  231. ARG_UNUSED(p1);
  232. ARG_UNUSED(p2);
  233. ARG_UNUSED(p3);
  234. LOG_INF("log thread started");
  235. while (1) {
  236. k_sem_take(&btc.log_rx_sem, K_FOREVER);
  237. if (!ipmsg_pending(btc.log_rx_id)) {
  238. continue;
  239. }
  240. ipmsg_recv(btc.log_rx_id, BTC_LOG_SIZE, btc_log_handler, NULL);
  241. k_yield();
  242. }
  243. }
  244. #endif
  245. static unsigned int rbuf_put_data(uint32_t id, void *data, uint16_t len)
  246. {
  247. uint32_t size;
  248. void *buf = NULL;
  249. if (!data || !len) {
  250. return 0;
  251. }
  252. buf = rbuf_put_claim(RBUF_FR_OF(id), len, &size);
  253. if (!buf) {
  254. return 0;
  255. }
  256. memcpy(buf, data, MIN(len, size));
  257. rbuf_put_finish(RBUF_FR_OF(id), size);
  258. return size;
  259. }
  260. static unsigned int rbuf_get_data(uint32_t id, void *dst, uint16_t len)
  261. {
  262. uint32_t size;
  263. void *buf = NULL;
  264. if (!dst || !len) {
  265. return 0;
  266. }
  267. buf = rbuf_get_claim(RBUF_FR_OF(id), len, &size);
  268. if (!buf) {
  269. return 0;
  270. }
  271. memcpy(dst, buf, MIN(len, size));
  272. rbuf_get_finish(RBUF_FR_OF(id), size);
  273. return size;
  274. }
  275. #ifdef CONFIG_BT_ECC_ACTS
  276. static void ecc_send(int err, void *data, uint16_t len)
  277. {
  278. btc.msg.data.w[0] = err;
  279. btc.msg.data.w[1] = len;
  280. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  281. if (data) {
  282. rbuf_put_data(btc.msg_tx_id, data, len);
  283. }
  284. ipmsg_notify(btc.dev);
  285. }
  286. static int emulate_le_p192_public_key(void)
  287. {
  288. int ret;
  289. struct bt_gen_p192_pk_rsp *rsp = (void *)btc_ecc.rsp;
  290. LOG_INF("gen p192 public key");
  291. ret = ecc_gen_p192_pk(rsp->public_key, rsp->private_key);
  292. if (ret) {
  293. goto done;
  294. }
  295. /* Convert key from big-endian to little-endian */
  296. sys_mem_swap(rsp->public_key, 24);
  297. sys_mem_swap(&rsp->public_key[24], 24);
  298. sys_mem_swap(rsp->private_key, 24);
  299. print_hex("public key: ", rsp->public_key, 48);
  300. print_hex("private key: ", rsp->private_key, 24);
  301. done:
  302. btc.msg.type = MSG_BT_GEN_P192_PK;
  303. ecc_send(ret, rsp, sizeof(*rsp));
  304. return ret;
  305. }
  306. static int emulate_le_p192_dhkey(void)
  307. {
  308. int err;
  309. struct bt_gen_p192_dhkey_req *req = (void *)btc_ecc.req;
  310. struct bt_gen_p192_dhkey_rsp *rsp = (void *)btc_ecc.rsp;
  311. uint16_t size = sizeof(*rsp);
  312. btc.msg.type = MSG_BT_GEN_P192_DHKEY;
  313. LOG_INF("gen p192 dhkey");
  314. print_hex("remote pk: ", req->remote_pk, 48);
  315. print_hex("private key: ", req->private_key, 24);
  316. /* Convert X and Y coordinates from little-endian to
  317. * big-endian (expected by the crypto API).
  318. */
  319. sys_mem_swap(req->remote_pk, 24);
  320. sys_mem_swap(&req->remote_pk[24], 24);
  321. /* valid remote public key first and send the result to btc */
  322. err = ecc_valid_p192_pk(req->remote_pk);
  323. if (err) {
  324. goto done;
  325. }
  326. sys_mem_swap(req->private_key, 24);
  327. err = ecc_gen_p192_dhkey(req->remote_pk, req->private_key, rsp->dhkey);
  328. if (err) {
  329. goto done;
  330. }
  331. /* Convert dhkey from big-endian to little-endian */
  332. sys_mem_swap(rsp->dhkey, 24);
  333. rsp->id = req->id;
  334. print_hex("dhkey: ", rsp->dhkey, 24);
  335. done:
  336. if (err) {
  337. rsp = NULL;
  338. size = req->id;
  339. }
  340. ecc_send(err, rsp, size);
  341. return err;
  342. }
  343. static int emulate_le_p256_public_key(void)
  344. {
  345. int ret;
  346. struct bt_gen_p256_pk_rsp *rsp = (void *)btc_ecc.rsp;
  347. LOG_INF("gen p256 pk");
  348. ret = ecc_gen_p256_pk(rsp->public_key, rsp->private_key);
  349. if (ret) {
  350. goto done;
  351. }
  352. sys_mem_swap(rsp->public_key, 32);
  353. sys_mem_swap(&rsp->public_key[32], 32);
  354. sys_mem_swap(rsp->private_key, 32);
  355. print_hex("public key: ", rsp->public_key, 64);
  356. print_hex("private key: ", rsp->private_key, 32);
  357. done:
  358. btc.msg.type = MSG_BT_GEN_P256_PK;
  359. ecc_send(ret, rsp, sizeof(*rsp));
  360. return ret;
  361. }
  362. static int emulate_le_p256_dhkey(void)
  363. {
  364. int err;
  365. struct bt_gen_p256_dhkey_req *req = (void *)btc_ecc.req;
  366. struct bt_gen_p256_dhkey_rsp *rsp = (void *)btc_ecc.rsp;
  367. uint16_t size = sizeof(*rsp);
  368. btc.msg.type = MSG_BT_GEN_P256_DHKEY;
  369. LOG_INF("gen p256 dhkey");
  370. print_hex("remote pk: ", req->remote_pk, 64);
  371. print_hex("private key: ", req->private_key, 32);
  372. /* Convert X and Y coordinates from little-endian to
  373. * big-endian (expected by the crypto API).
  374. */
  375. sys_mem_swap(req->remote_pk, 32);
  376. sys_mem_swap(&req->remote_pk[32], 32);
  377. /* valid remote public key first and send the result to btc */
  378. err = ecc_valid_p256_pk(req->remote_pk);
  379. if (err) {
  380. goto done;
  381. }
  382. sys_mem_swap(req->private_key, 32);
  383. err = ecc_gen_p256_dhkey(req->remote_pk, req->private_key, rsp->dhkey);
  384. if (err) {
  385. goto done;
  386. }
  387. /* Convert dhkey from little-endian to big-endian */
  388. sys_mem_swap(rsp->dhkey, 32);
  389. rsp->id = req->id;
  390. print_hex("dhkey: ", rsp->dhkey, 32);
  391. done:
  392. if (err) {
  393. rsp = NULL;
  394. size = req->id;
  395. }
  396. ecc_send(err, rsp, size);
  397. return err;
  398. }
  399. static void emulate_key(struct k_work *item)
  400. {
  401. if (btc_ecc.size) {
  402. rbuf_get_data(btc.msg_rx_id, (void *)btc_ecc.req, btc_ecc.size);
  403. }
  404. if (atomic_test_bit(btc_ecc.flag, PENDING_P192_PUB_KEY)) {
  405. emulate_le_p192_public_key();
  406. atomic_clear_bit(btc_ecc.flag, PENDING_P192_PUB_KEY);
  407. } else if (atomic_test_bit(btc_ecc.flag, PENDING_P192_DHKEY)) {
  408. emulate_le_p192_dhkey();
  409. atomic_clear_bit(btc_ecc.flag, PENDING_P192_DHKEY);
  410. } else if (atomic_test_bit(btc_ecc.flag, PENDING_P256_PUB_KEY)) {
  411. emulate_le_p256_public_key();
  412. atomic_clear_bit(btc_ecc.flag, PENDING_P256_PUB_KEY);
  413. } else if (atomic_test_bit(btc_ecc.flag, PENDING_P256_DHKEY)) {
  414. emulate_le_p256_dhkey();
  415. atomic_clear_bit(btc_ecc.flag, PENDING_P256_DHKEY);
  416. } else {
  417. LOG_ERR("Unhandled ECC request");
  418. }
  419. }
  420. #endif
  421. #ifdef CONFIG_BT_CTRL_REG
  422. static void btc_read_reg(struct k_work *work)
  423. {
  424. int size, i;
  425. void *buf;
  426. buf = rbuf_get_claim(RBUF_FR_OF(btc.msg_rx_id), btc_reg.size, &size);
  427. if (!buf) {
  428. return;
  429. }
  430. if (atomic_test_bit(btc_reg.flag, PENDING_READ_BB_REG)) {
  431. uint32_t *reg_32 = buf;
  432. for (i = 0; i < btc_reg.size/4; i++) {
  433. LOG_INF("0x%08x: 0x%08x", btc_reg.bb_reg + i*4, reg_32[i]);
  434. }
  435. atomic_clear_bit(btc_reg.flag, PENDING_READ_BB_REG);
  436. } else if (atomic_test_bit(btc_reg.flag, PENDING_READ_RF_REG)) {
  437. uint16_t *reg_16 = buf;
  438. for (i = 0; i < btc_reg.size/4; i++) {
  439. LOG_INF("0x%04x: 0x%04x", btc_reg.rf_reg + i, reg_16[i]);
  440. }
  441. atomic_clear_bit(btc_reg.flag, PENDING_READ_RF_REG);
  442. } else {
  443. LOG_ERR("Unknown reg to read");
  444. }
  445. rbuf_get_finish(RBUF_FR_OF(btc.msg_rx_id), size);
  446. }
  447. #endif
  448. static void btc_msg_handler(void)
  449. {
  450. uint16_t ret;
  451. rbuf_msg_t rx_msg = {0};
  452. #ifdef CONFIG_BT_ECC_ACTS
  453. /* wait for ecc request processing to complte */
  454. if (atomic_get(btc_ecc.flag)) {
  455. return;
  456. }
  457. #endif
  458. ret = rbuf_get_data(btc.msg_rx_id, &rx_msg, sizeof(rbuf_msg_t));
  459. if (ret != sizeof(rbuf_msg_t)) {
  460. return;
  461. }
  462. LOG_DBG("msg type: %x, data size: %u\n", rx_msg.type, rx_msg.data.w[0]);
  463. switch (rx_msg.type) {
  464. case MSG_BT_HCI_OK:
  465. k_sem_give(&btc.ready_sem);
  466. atomic_set_bit(btc.flags, BT_CPU_READY);
  467. break;
  468. #ifdef CONFIG_BT_ECC_ACTS
  469. case MSG_BT_GEN_P192_PK:
  470. btc_ecc.size = 0;
  471. atomic_set_bit(btc_ecc.flag, PENDING_P192_PUB_KEY);
  472. break;
  473. case MSG_BT_GEN_P192_DHKEY:
  474. //btc_ecc.size = rx_msg->data.w[0];
  475. btc_ecc.size = sizeof(struct bt_gen_p192_dhkey_req);
  476. atomic_set_bit(btc_ecc.flag, PENDING_P192_DHKEY);
  477. break;
  478. case MSG_BT_GEN_P256_PK:
  479. btc_ecc.size = 0;
  480. atomic_set_bit(btc_ecc.flag, PENDING_P256_PUB_KEY);
  481. break;
  482. case MSG_BT_GEN_P256_DHKEY:
  483. //btc_ecc.size = rx_msg->data.w[0];
  484. btc_ecc.size = sizeof(struct bt_gen_p256_dhkey_req);
  485. atomic_set_bit(btc_ecc.flag, PENDING_P256_DHKEY);
  486. break;
  487. #endif
  488. #ifdef CONFIG_BT_CTRL_REG
  489. case MSG_BT_READ_BB_REG:
  490. btc_reg.size = rx_msg.data.w[0];
  491. btc_reg.bb_reg = rx_msg.data.w[1];
  492. atomic_set_bit(btc_reg.flag, PENDING_READ_BB_REG);
  493. break;
  494. case MSG_BT_READ_RF_REG:
  495. btc_reg.size = rx_msg.data.w[0];
  496. btc_reg.rf_reg = rx_msg.data.w[1];
  497. atomic_set_bit(btc_reg.flag, PENDING_READ_RF_REG);
  498. break;
  499. #endif
  500. default:
  501. LOG_ERR("unknown msg(type %x)!", rx_msg.type);
  502. break;
  503. }
  504. #ifdef CONFIG_BT_ECC_ACTS
  505. /* process ecc requests */
  506. if (atomic_get(btc_ecc.flag) > 0) {
  507. //k_work_submit(&btc_ecc.work);
  508. acts_work_submit(&btc_ecc.work);
  509. return;
  510. }
  511. #endif
  512. #ifdef CONFIG_BT_CTRL_REG
  513. if (atomic_get(btc_reg.flag) > 0) {
  514. k_work_submit(&btc_reg.work);
  515. }
  516. #endif
  517. }
  518. /* process hci rx buf after reciving */
  519. static inline void read_complete(void)
  520. {
  521. #ifdef CONFIG_BT_HCI_RX_PRINT
  522. print_hex(rx_type_str[rx.hdr.type], rx.pkt, rx.pkt_len);
  523. #endif
  524. if (btc.hci_cb && rx.pkt) {
  525. btc.hci_cb->recv(rx.pkt_len);
  526. }
  527. memset(&rx, 0, sizeof(struct hci_data));
  528. /* if hci rx rbuf is not empty and hci rx sem is zero, then read again */
  529. if (!k_sem_count_get(&btc.hci_rx_sem) && ipmsg_pending(btc.hci_rx_id)) {
  530. k_sem_give(&btc.hci_rx_sem);
  531. }
  532. }
  533. static uint16_t btdrv_cal_acl_packet_need_len(uint8_t *hdr, uint16_t hdr_size, uint16_t exp_len)
  534. {
  535. uint16_t handle, need_len, l2cap_len;
  536. uint8_t flags;
  537. handle = (hdr[1] <<8 | hdr[0]);
  538. flags = (handle >> 12) & 0xF;
  539. if (flags == BT_ACL_HDL_FLAG_START) {
  540. if (hdr_size >= 6) {
  541. l2cap_len = (hdr[5] << 8 | hdr[4]);
  542. need_len = l2cap_len + HCI_ACL_HDR_SIZE + HCI_L2CAP_HEAD_SIZE;
  543. if (l2cap_len > L2CAP_BR_MAX_MTU_A2DP_AAC || exp_len > need_len) {
  544. LOG_ERR("l2cap_len too length %d exp_len %d hdr %2x %2x %2x %2x %2x %2x\n",
  545. l2cap_len, exp_len, hdr[0], hdr[1], hdr[2], hdr[3], hdr[4], hdr[5]);
  546. }
  547. return (need_len > exp_len)? need_len : exp_len;
  548. } else {
  549. if (BT_MAX_RX_ACL_LEN) {
  550. if (exp_len > BT_MAX_RX_ACL_LEN) {
  551. /* exp_len large than BT_MAX_RX_ACL_LEN, maybe AAC packet,
  552. * but can't calculate AAC packet need length, just use AAC max length.
  553. */
  554. return (L2CAP_BR_MAX_MTU_A2DP_AAC + HCI_ACL_HDR_SIZE + HCI_L2CAP_HEAD_SIZE);
  555. } else {
  556. return (BT_MAX_RX_ACL_LEN > exp_len)? BT_MAX_RX_ACL_LEN : exp_len;
  557. }
  558. } else {
  559. /* default buffer lengh */
  560. return 0;
  561. }
  562. }
  563. } else {
  564. return exp_len;
  565. }
  566. }
  567. static void get_rx_buf(uint8_t *hdr, uint16_t hdr_size)
  568. {
  569. uint8_t evt = 0;
  570. uint16_t need_buf_len;
  571. switch (rx.hdr.type) {
  572. case HCI_ACL:
  573. rx.pkt_len = (hdr[3]<<8 | hdr[2]) + HCI_ACL_HDR_SIZE;
  574. need_buf_len = btdrv_cal_acl_packet_need_len(hdr, hdr_size, rx.pkt_len);
  575. break;
  576. case HCI_SCO:
  577. rx.pkt_len = hdr[2] + HCI_SCO_HDR_SIZE;
  578. need_buf_len = rx.pkt_len;
  579. break;
  580. case HCI_EVT:
  581. evt = hdr[0];
  582. rx.pkt_len = hdr[1] + HCI_EVT_HDR_SIZE;
  583. need_buf_len = rx.pkt_len;
  584. break;
  585. case HCI_ISO:
  586. rx.pkt_len = (hdr[3]<<8 | hdr[2]) + HCI_ISO_HDR_SIZE;
  587. need_buf_len = rx.pkt_len;
  588. break;
  589. default:
  590. rx.pkt_len = 0;
  591. LOG_ERR("get_rx_buf unknow type %d !\n", rx.hdr.type);
  592. return;
  593. }
  594. if (btc.hci_cb && btc.hci_cb->get_buf) {
  595. rx.pkt = btc.hci_cb->get_buf(rx.hdr.type, evt, need_buf_len);
  596. }
  597. }
  598. static inline int read_hdr(void)
  599. {
  600. uint32_t size = 0;
  601. void *data = NULL;
  602. uint8_t read_size = BT_HCI_HDR_SIZE - rx.hdr_len;
  603. if (rx.has_hdr) {
  604. return rx.hdr_len;
  605. }
  606. data = rbuf_get_claim(RBUF_FR_OF(btc.hci_rx_id), read_size, &size);
  607. if (!data) {
  608. if (size) {
  609. LOG_INF("get buf header failed size %d", size);
  610. }
  611. rbuf_info_dump(RBUF_FR_OF(btc.hci_rx_id));
  612. return 0;
  613. }
  614. if (size != read_size) {
  615. LOG_INF("get buf header failed read %d size %d", read_size, size);
  616. }
  617. memcpy(&rx.hdr_buff[rx.hdr_len], data, size);
  618. rx.hdr_len += size;
  619. rbuf_get_finish(RBUF_FR_OF(btc.hci_rx_id), size);
  620. if (rx.hdr_len == BT_HCI_HDR_SIZE) {
  621. rx.total = rx.hdr.len;
  622. rx.has_hdr = true;
  623. }
  624. return rx.hdr_len;
  625. }
  626. static inline int read_buf(void)
  627. {
  628. unsigned int size = 0;
  629. void *data = NULL;
  630. uint16_t cpy_len = 0;
  631. data = rbuf_get_claim(RBUF_FR_OF(btc.hci_rx_id), rx.total, &size);
  632. if (!data) {
  633. LOG_INF("alloc hci rx rbuf failed total %d(%d) size %d", rx.total, rx.hdr.len, size);
  634. return 0;
  635. }
  636. if (!rx.pkt) {
  637. get_rx_buf((uint8_t *)data, (uint16_t)size);
  638. }
  639. if (rx.pkt) {
  640. cpy_len = MIN(rx.pkt_len - rx.offset, size);
  641. memcpy(rx.pkt + rx.offset, data, cpy_len);
  642. rx.offset += cpy_len;
  643. } else {
  644. LOG_ERR("read_buf total %d drop data %d!\n", rx.total, size);
  645. }
  646. rbuf_get_finish(RBUF_FR_OF(btc.hci_rx_id), size);
  647. rx.total -= size;
  648. return size;
  649. }
  650. #if CONFIG_HCI_RX_THREAD
  651. static void rx_thread(void *p1, void *p2, void *p3)
  652. {
  653. unsigned int size = 0;
  654. ARG_UNUSED(p1);
  655. ARG_UNUSED(p2);
  656. ARG_UNUSED(p3);
  657. LOG_INF("rx thread started");
  658. while (1) {
  659. k_sem_take(&btc.hci_rx_sem, K_FOREVER);
  660. //uint32_t cycle = k_cycle_get_32();
  661. if (read_hdr() != BT_HCI_HDR_SIZE) {
  662. continue;
  663. }
  664. do {
  665. size = read_buf();
  666. } while (size && rx.total);
  667. if (!rx.total) {
  668. read_complete();
  669. } else {
  670. if (rx.pkt) {
  671. LOG_INF("read hci rx buf incompletely");
  672. } else {
  673. LOG_INF("read hci rx buf NULL");
  674. }
  675. }
  676. //LOG_DBG("[BT] rx cycle: %u\n", k_cycle_get_32() - cycle);
  677. k_yield();
  678. }
  679. }
  680. #endif
  681. static inline unsigned int send_buf(void)
  682. {
  683. uint8_t *buf = NULL;
  684. uint16_t copy_len;
  685. unsigned int size = 0;
  686. buf = rbuf_put_claim(RBUF_FR_OF(btc.hci_tx_id), tx.total, &size);
  687. if (buf == NULL) {
  688. LOG_ERR("alloc hci tx rbuf failed");
  689. return 0;
  690. }
  691. if (!tx.has_hdr) {
  692. memcpy(buf, &tx.hdr, BT_HCI_HDR_SIZE);
  693. buf += BT_HCI_HDR_SIZE;
  694. copy_len = MIN(size - BT_HCI_HDR_SIZE, tx.pkt_len - tx.offset);
  695. tx.has_hdr = true;
  696. } else {
  697. copy_len = MIN(size, tx.pkt_len - tx.offset);
  698. }
  699. memcpy(buf, tx.pkt + tx.offset, copy_len);
  700. tx.offset += copy_len;
  701. rbuf_put_finish(RBUF_FR_OF(btc.hci_tx_id), size);
  702. tx.total -= size;
  703. return size;
  704. }
  705. /* data fmt: hdr(4) + payload(n) */
  706. int btdrv_send(uint8_t type, uint8_t *data, uint16_t len)
  707. {
  708. int err = 0;
  709. unsigned int size = 0;
  710. //uint32_t cycle = k_cycle_get_32();
  711. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  712. return -EINVAL;
  713. }
  714. if (!data || !len) {
  715. return -EINVAL;
  716. }
  717. tx.pkt = data;
  718. tx.total = ROUND_UP(len, 4) + BT_HCI_HDR_SIZE;
  719. tx.hdr.len = tx.total - BT_HCI_HDR_SIZE;
  720. tx.hdr.type = type;
  721. tx.pkt_len = len;
  722. do {
  723. size = send_buf();
  724. } while (size && tx.total);
  725. if (!tx.total) {
  726. ipmsg_notify(btc.dev);
  727. #ifdef CONFIG_BT_HCI_TX_PRINT
  728. print_hex(tx_type_str[tx.hdr.type], tx.pkt, tx.pkt_len);
  729. #endif
  730. } else {
  731. err = -EINVAL;
  732. LOG_ERR("send hci rbuf failed");
  733. }
  734. memset(&tx, 0, sizeof(struct hci_data));
  735. //LOG_DBG("tx cycle: %u\n", k_cycle_get_32() - cycle);
  736. return err;
  737. }
  738. /* BTC interupt handler */
  739. static void btc_recv_cb(void *context, void *arg)
  740. {
  741. if (ipmsg_pending(btc.msg_rx_id)) {
  742. btc_msg_handler();
  743. }
  744. if (ipmsg_pending(btc.hci_rx_id)) {
  745. #if CONFIG_HCI_RX_THREAD
  746. k_sem_give(&btc.hci_rx_sem);
  747. #endif
  748. }
  749. #ifdef CONFIG_BT_CTRL_LOG
  750. if (ipmsg_pending(btc.log_rx_id)) {
  751. k_sem_give(&btc.log_rx_sem);
  752. }
  753. #endif
  754. #ifdef CONFIG_BT_CTRL_TWS
  755. /* tws0 interrupt pending has been cleared */
  756. if (atomic_test_bit(btc.flags, BT_CPU_TWS0_PENDING) &&
  757. (tws_rx[0]->pcnt == tws_tx[0]->pcnt)) {
  758. atomic_clear_bit(btc.flags, BT_CPU_TWS0_PENDING);
  759. }
  760. if (atomic_test_bit(btc.flags, BT_CPU_TWS1_PENDING) &&
  761. (tws_rx[1]->pcnt == tws_tx[1]->pcnt)) {
  762. atomic_clear_bit(btc.flags, BT_CPU_TWS1_PENDING);
  763. }
  764. #endif
  765. }
  766. #ifdef CONFIG_BT_CTRL_TWS
  767. static void btc_tws0_cb(void *context, void *arg)
  768. {
  769. if (btc.tws0_cb) {
  770. btc.tws0_cb();
  771. }
  772. atomic_set_bit(btc.flags, BT_CPU_TWS0_PENDING);
  773. tws_tx[0]->pcnt++;
  774. ipmsg_notify(btc.dev);
  775. }
  776. static void btc_tws1_cb(void *context, void *arg)
  777. {
  778. if (btc.tws1_cb) {
  779. btc.tws1_cb();
  780. }
  781. atomic_set_bit(btc.flags, BT_CPU_TWS1_PENDING);
  782. tws_tx[1]->pcnt++;
  783. ipmsg_notify(btc.dev);
  784. }
  785. #endif
  786. #ifdef CONFIG_PM_DEVICE
  787. static void bt_log_controler(bool log_on)
  788. {
  789. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  790. return;
  791. }
  792. printk("bt_log_controler:%d\n",log_on);
  793. if (log_on) {
  794. btc.msg.type = MSG_BT_LOG_ON;
  795. btc.msg.data.w[0] = btc.log_rx_id;
  796. } else {
  797. btc.msg.type = MSG_BT_LOG_OFF;
  798. btc.msg.data.w[0] = 1; /* Log out from uart */
  799. }
  800. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  801. ipmsg_notify(btc.dev);
  802. }
  803. static void btc_pm_ctrl_cb(uint32_t command, uint32_t state)
  804. {
  805. switch (state) {
  806. case PM_DEVICE_ACTION_RESUME:
  807. break;
  808. case PM_DEVICE_ACTION_SUSPEND:
  809. break;
  810. case PM_DEVICE_ACTION_EARLY_SUSPEND:
  811. bt_log_controler(false);
  812. break;
  813. case PM_DEVICE_ACTION_LATE_RESUME:
  814. bt_log_controler(true);
  815. break;
  816. default:
  817. break;;
  818. }
  819. }
  820. #else
  821. #define btc_pm_ctrl_cb NULL
  822. #endif
  823. static void set_mac(void)
  824. {
  825. int ret;
  826. const uint8_t *default_mac = "f44efd12a3b4";
  827. uint8_t addr[6], mac_str[13];
  828. #ifdef CONFIG_PROPERTY
  829. ret = property_get(CFG_BT_MAC, mac_str, 12);
  830. if(ret < 12) {
  831. LOG_WRN("property_get CFG_BT_MAC ret: %d", ret);
  832. memcpy(mac_str, default_mac, 12);
  833. }
  834. #else
  835. memcpy(mac_str, default_mac, 12);
  836. #endif
  837. ret = hex2bin(mac_str, 12, addr, 6);
  838. if (ret != 6) {
  839. LOG_ERR("invalid bt address");
  840. return;
  841. }
  842. btc.msg.type = MSG_BT_INIT;
  843. btc.msg.data.w[0] = addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | addr[5];
  844. btc.msg.data.w[1] = addr[0] << 8 | addr[1];
  845. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  846. }
  847. #ifdef CONFIG_BT_CTRL_TWS
  848. static struct btc_tws *tws_init(uint32_t *id)
  849. {
  850. struct btc_tws *tws;
  851. *id = ipmsg_create(RBUF_RAW, BT_TWS_SIZE);
  852. if (*id == 0) {
  853. return NULL;
  854. }
  855. rbuf_t *rbuf = RBUF_FR_OF(*id);
  856. tws = (void *)RBUF_FR_OF(rbuf->buf_off);
  857. memset(tws, 0, sizeof(struct btc_tws));
  858. return tws;
  859. }
  860. #endif
  861. static void send_init_msg(void)
  862. {
  863. set_mac();
  864. #ifdef CONFIG_BT_CTRL_RF_DEBUG
  865. btc.msg.type = MSG_BT_MDM_RF_DEBUG;
  866. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  867. #endif
  868. btc.msg.type = MSG_BT_HCI_BUF;
  869. btc.msg.data.w[0] = btc.hci_rx_id; /* bt -> main */
  870. btc.msg.data.w[1] = btc.hci_tx_id; /* main -> bt */
  871. btc.msg.data.w[2] = btc.log_rx_id; /* bt -> main */
  872. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  873. #ifdef CONFIG_BT_CTRL_TWS
  874. btc.msg.type = MSG_BT_TWS_BUF;
  875. btc.msg.data.w[0] = btc.tws_rx_id[0]; /* bt -> main */
  876. btc.msg.data.w[1] = btc.tws_tx_id[0]; /* main -> bt */
  877. btc.msg.data.w[2] = btc.tws_rx_id[1];
  878. btc.msg.data.w[3] = btc.tws_tx_id[1];
  879. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  880. #endif
  881. }
  882. static void init_rbuf(void)
  883. {
  884. btc.msg_tx_id = rbuf_msg_create(CPU, BT, RB_MSG_SIZE);
  885. btc.msg_rx_id = rbuf_msg_create(BT, CPU, RB_MSG_SIZE);
  886. LOG_INF("msg tx id: %d, msg rx id: %d", btc.msg_tx_id, btc.msg_rx_id);
  887. #ifdef CONFIG_BT_CTRL_LOG
  888. btc.log_rx_id = ipmsg_create(RBUF_RAW, BTC_LOG_SIZE);
  889. LOG_INF("log id: %d", btc.log_rx_id);
  890. #endif
  891. btc.hci_rx_id = ipmsg_create(RBUF_RAW, CONFIG_BT_HCI_RX_RBUF_SIZE);
  892. btc.hci_tx_id = ipmsg_create(RBUF_RAW, CONFIG_BT_HCI_TX_RBUF_SIZE);
  893. LOG_INF("hci rx id: %d, hci tx id: %d", btc.hci_rx_id, btc.hci_tx_id);
  894. #ifdef CONFIG_BT_CTRL_TWS
  895. for (uint8_t i = 0; i < 2; i++) {
  896. tws_rx[i] = tws_init(&btc.tws_rx_id[i]);
  897. tws_tx[i] = tws_init(&btc.tws_tx_id[i]);
  898. LOG_INF("tws%d rx id: %d, tx id: %d", i, btc.tws_rx_id[i], btc.tws_tx_id[i]);
  899. }
  900. #endif
  901. send_init_msg();
  902. }
  903. int btdrv_set_init_param(btdrv_init_param_t *param)
  904. {
  905. ipmsg_btc_init_param_t btc_param;
  906. #ifdef CONFIG_COMPENSATION_ACTS
  907. uint32_t cap_value = 0xFF;
  908. int ret = 0;
  909. #endif
  910. btc.dev = (struct device *)device_get_binding("BTC");
  911. if (!btc.dev) {
  912. LOG_ERR("get device BTC failed");
  913. return -EINVAL;
  914. }
  915. btc_param.hosc_capacity = param->hosc_capacity;
  916. #ifdef CONFIG_COMPENSATION_ACTS
  917. ret = freq_compensation_get_cap(&cap_value);
  918. if(ret == TRIM_CAP_READ_NO_ERROR){
  919. btc_param.hosc_capacity = (cap_value & 0xFF);
  920. }
  921. LOG_INF("efuse cap valid:%d cap:%x",ret,cap_value);
  922. #endif
  923. btc_param.set_hosc_cap = param->set_hosc_cap;
  924. btc_param.set_max_rf_power = param->set_max_rf_power;
  925. btc_param.set_ble_rf_power = param->set_ble_rf_power;
  926. btc_param.bt_max_rf_tx_power = param->bt_max_rf_tx_power;
  927. btc_param.ble_rf_tx_power = param->ble_rf_tx_power;
  928. ipmsg_init_param(btc.dev, &btc_param);
  929. return 0;
  930. }
  931. int btdrv_init(btdrv_hci_cb_t *cb)
  932. {
  933. int ret;
  934. uint8_t irq;
  935. LOG_INF("bt driver init");
  936. if (atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  937. goto start_cpu;
  938. }
  939. if (!cb) {
  940. return -EINVAL;
  941. }
  942. btc.hci_cb = cb;
  943. #ifdef CONFIG_BT_CTRL_REG
  944. k_work_init(&btc_reg.work, btc_read_reg);
  945. #endif
  946. #ifdef CONFIG_BT_ECC_ACTS
  947. ret = ecc_init();
  948. if (ret) {
  949. LOG_ERR("Ecc init failed");
  950. }
  951. k_work_init(&btc_ecc.work, emulate_key);
  952. #endif
  953. btc.dev = (struct device *)device_get_binding("BTC");
  954. if (!btc.dev) {
  955. LOG_ERR("get device BTC failed");
  956. return -EINVAL;
  957. }
  958. irq = IPMSG_BTC_IRQ;
  959. ipmsg_register_callback(btc.dev, btc_recv_cb, &irq);
  960. #ifdef CONFIG_BT_CTRL_TWS
  961. irq = IPMSG_TWS0_IRQ;
  962. ipmsg_register_callback(btc.dev, btc_tws0_cb, &irq);
  963. irq = IPMSG_TWS1_IRQ;
  964. ipmsg_register_callback(btc.dev, btc_tws1_cb, &irq);
  965. #endif
  966. irq = IPMSG_REG_PW_CTRL;
  967. ipmsg_register_callback(btc.dev, (ipmsg_callback_t)btc_pm_ctrl_cb, &irq);
  968. init_rbuf();
  969. #if CONFIG_HCI_RX_THREAD
  970. /* Start RX thread */
  971. k_thread_create(&rx_thread_data, rx_thread_stack,
  972. K_THREAD_STACK_SIZEOF(rx_thread_stack),
  973. rx_thread, NULL, NULL, NULL,
  974. K_PRIO_COOP(CONFIG_BT_HCI_RX_PRIO),
  975. 0, K_NO_WAIT);
  976. k_thread_name_set(&rx_thread_data, "BT HCI RX");
  977. #endif
  978. #ifdef CONFIG_BT_CTRL_LOG
  979. k_thread_create(&log_thread_data, log_thread_stack,
  980. K_THREAD_STACK_SIZEOF(log_thread_stack),
  981. log_thread, NULL, NULL, NULL,
  982. CONFIG_BT_LOG_PRIO,
  983. 0, K_NO_WAIT);
  984. k_thread_name_set(&log_thread_data, "BT LOG");
  985. #endif
  986. atomic_set_bit(btc.flags, BT_CPU_ENABLE);
  987. start_cpu:
  988. if (atomic_test_bit(btc.flags, BT_CPU_READY)) {
  989. return 0;
  990. }
  991. ret = ipmsg_load(btc.dev, (void *)BTC_BIN_ADDR, BTC_BIN_SIZE);
  992. if (ret) {
  993. LOG_ERR("load bt bin failed");
  994. return -EINVAL;
  995. }
  996. /* Start BT CPU */
  997. ret = ipmsg_start(btc.dev, NULL, NULL);
  998. if (ret) {
  999. LOG_ERR("start bt cpu failed");
  1000. return -EINVAL;
  1001. }
  1002. /* BT CPU will let us know when it's ready */
  1003. LOG_INF("wait bt cpu ready...");
  1004. k_sem_take(&btc.ready_sem, K_FOREVER);
  1005. LOG_INF("bt cpu ready");
  1006. return 0;
  1007. }
  1008. int btdrv_exit(void)
  1009. {
  1010. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1011. return -ENODEV;
  1012. }
  1013. LOG_INF("exit");
  1014. ipmsg_stop(btc.dev);
  1015. btc.hci_cb = NULL;
  1016. #ifdef CONFIG_BT_CTRL_TWS
  1017. btc.tws0_cb = NULL;
  1018. btc.tws1_cb = NULL;
  1019. #endif
  1020. // destroy default message queue
  1021. rbuf_msg_destroy(CPU, BT);
  1022. rbuf_msg_destroy(BT, CPU);
  1023. ipmsg_destroy(btc.hci_rx_id);
  1024. ipmsg_destroy(btc.hci_tx_id);
  1025. ipmsg_destroy(btc.log_rx_id);
  1026. #ifdef CONFIG_BT_CTRL_TWS
  1027. for (uint8_t i = 0; i < 2; i++) {
  1028. ipmsg_destroy(btc.tws_rx_id[i]);
  1029. ipmsg_destroy(btc.tws_tx_id[i]);
  1030. }
  1031. #endif
  1032. atomic_clear(btc.flags);
  1033. return 0;
  1034. }
  1035. int btdrv_reset(void)
  1036. {
  1037. /* Reset BT CPU */
  1038. atomic_clear_bit(btc.flags, BT_CPU_READY);
  1039. ipmsg_stop(btc.dev);
  1040. send_init_msg();
  1041. return btdrv_init(NULL);
  1042. }
  1043. #ifdef CONFIG_BT_CTRL_TWS
  1044. int btdrv_tws_irq_enable(uint8_t index)
  1045. {
  1046. if (index > BT_TWS_1) {
  1047. return -EINVAL;
  1048. }
  1049. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1050. return -ENOENT;
  1051. }
  1052. ipmsg_tws_irq_enable(btc.dev, index + 1);
  1053. return 0;
  1054. }
  1055. int btdrv_tws_irq_disable(uint8_t index)
  1056. {
  1057. if (index > BT_TWS_1) {
  1058. return -EINVAL;
  1059. }
  1060. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1061. return -ENOENT;
  1062. }
  1063. ipmsg_tws_irq_disable(btc.dev, index + 1);
  1064. return 0;
  1065. }
  1066. int btdrv_tws_irq_cb_set(uint8_t index, btdrv_tws_cb_t cb)
  1067. {
  1068. if (index > BT_TWS_1) {
  1069. return -EINVAL;
  1070. }
  1071. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1072. return -ENOENT;
  1073. }
  1074. if (index == BT_TWS_0) {
  1075. btc.tws0_cb = cb;
  1076. } else if (index == BT_TWS_1) {
  1077. btc.tws1_cb = cb;
  1078. }
  1079. return 0;
  1080. }
  1081. int btdrv_tws_set_mode(uint8_t index, uint8_t mode)
  1082. {
  1083. if (index > BT_TWS_1) {
  1084. return -EINVAL;
  1085. }
  1086. tws_tx[index]->mode = mode;
  1087. return 0;
  1088. }
  1089. int btdrv_tws_data_read(uint8_t index, uint8_t *buf)
  1090. {
  1091. if ((tws_rx[index]->wcnt - tws_rx[index]->rcnt) == 0) {
  1092. return -ENODATA;
  1093. }
  1094. memcpy(buf, tws_rx[index]->data, tws_rx[index]->data_len);
  1095. tws_rx[index]->rcnt++;
  1096. return tws_rx[index]->data_len;
  1097. }
  1098. int btdrv_tws_data_write(uint8_t index, uint8_t *data, uint16_t len)
  1099. {
  1100. if (!data || !len) {
  1101. return -EINVAL;
  1102. }
  1103. if ((tws_tx[index]->wcnt - tws_tx[index]->rcnt) >= 1) {
  1104. return -ENOBUFS;
  1105. }
  1106. memcpy(tws_tx[index]->data, data, len);
  1107. tws_tx[index]->wcnt++;
  1108. return len;
  1109. }
  1110. #endif
  1111. #if 0 /* Not use message read/write bt/rf register */
  1112. void btdrv_read_bb_reg(uint32_t addr, uint8_t count)
  1113. {
  1114. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  1115. return;
  1116. }
  1117. btc.msg.type = MSG_BT_READ_BB_REG;
  1118. btc.msg.data.w[0] = addr;
  1119. btc.msg.data.w[1] = count;
  1120. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  1121. ipmsg_notify(btc.dev);
  1122. }
  1123. void btdrv_write_bb_reg(uint32_t addr, uint32_t val)
  1124. {
  1125. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  1126. return;
  1127. }
  1128. btc.msg.type = MSG_BT_WRITE_BB_REG;
  1129. btc.msg.data.w[0] = addr;
  1130. btc.msg.data.w[1] = val;
  1131. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  1132. ipmsg_notify(btc.dev);
  1133. }
  1134. void btdrv_read_rf_reg(uint16_t addr, uint8_t count)
  1135. {
  1136. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  1137. return;
  1138. }
  1139. btc.msg.type = MSG_BT_READ_RF_REG;
  1140. btc.msg.data.w[0] = addr;
  1141. btc.msg.data.w[1] = count;
  1142. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  1143. ipmsg_notify(btc.dev);
  1144. }
  1145. void btdrv_write_rf_reg(uint16_t addr, uint16_t val)
  1146. {
  1147. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  1148. return;
  1149. }
  1150. btc.msg.type = MSG_BT_WRITE_RF_REG;
  1151. btc.msg.data.w[0] = addr;
  1152. btc.msg.data.w[1] = val;
  1153. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  1154. ipmsg_notify(btc.dev);
  1155. }
  1156. #else
  1157. extern int bt_bqb_vs_write_bb_reg(uint32_t addr, uint32_t val);
  1158. extern int bt_bqb_vs_read_bb_reg(uint32_t addr, uint8_t size);
  1159. extern int bt_bqb_vs_write_rf_reg(uint16_t addr, uint16_t val);
  1160. extern int bt_bqb_vs_read_rf_reg(uint16_t addr, uint8_t size);
  1161. extern int bt_stack_vs_write_bb_reg(uint32_t addr, uint32_t val);
  1162. extern int bt_stack_vs_read_bb_reg(uint32_t addr, uint8_t size);
  1163. extern int bt_stack_vs_write_rf_reg(uint16_t addr, uint16_t val);
  1164. extern int bt_stack_vs_read_rf_reg(uint16_t addr, uint8_t size);
  1165. extern bool bt_bqb_is_in_test(void);
  1166. int bt_vs_write_bb_reg(uint32_t addr, uint32_t val)
  1167. {
  1168. #ifdef CONFIG_BT_CTRL_BQB
  1169. if (bt_bqb_is_in_test()) {
  1170. return bt_bqb_vs_write_bb_reg(addr, val);
  1171. } else {
  1172. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1173. return bt_stack_vs_write_bb_reg(addr, val);
  1174. #else
  1175. return 0;
  1176. #endif
  1177. }
  1178. #else
  1179. return bt_stack_vs_write_bb_reg(addr, val);
  1180. #endif
  1181. }
  1182. int bt_vs_read_bb_reg(uint32_t addr, uint8_t size)
  1183. {
  1184. #ifdef CONFIG_BT_CTRL_BQB
  1185. if (bt_bqb_is_in_test()) {
  1186. return bt_bqb_vs_read_bb_reg(addr, size);
  1187. } else {
  1188. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1189. return bt_stack_vs_read_bb_reg(addr, size);
  1190. #else
  1191. return 0;
  1192. #endif
  1193. }
  1194. #else
  1195. return bt_stack_vs_read_bb_reg(addr, size);
  1196. #endif
  1197. }
  1198. int bt_vs_write_rf_reg(uint16_t addr, uint16_t val)
  1199. {
  1200. #ifdef CONFIG_BT_CTRL_BQB
  1201. if (bt_bqb_is_in_test()) {
  1202. return bt_bqb_vs_write_rf_reg(addr, val);
  1203. } else {
  1204. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1205. return bt_stack_vs_write_rf_reg(addr, val);
  1206. #else
  1207. return 0;
  1208. #endif
  1209. }
  1210. #else
  1211. return bt_stack_vs_write_rf_reg(addr, val);
  1212. #endif
  1213. }
  1214. int bt_vs_read_rf_reg(uint16_t addr, uint8_t size)
  1215. {
  1216. #ifdef CONFIG_BT_CTRL_BQB
  1217. if (bt_bqb_is_in_test()) {
  1218. return bt_bqb_vs_read_rf_reg(addr, size);
  1219. } else {
  1220. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1221. return bt_stack_vs_read_rf_reg(addr, size);
  1222. #else
  1223. return 0;
  1224. #endif
  1225. }
  1226. #else
  1227. return bt_stack_vs_read_rf_reg(addr, size);
  1228. #endif
  1229. }
  1230. #endif