dc5v_uart.c 24 KB

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  1. /*!
  2. * \file dc5v_uart.c
  3. * \brief DC5V_UART driver interface
  4. * \details
  5. * \author
  6. * \date
  7. * \copyright Actions
  8. */
  9. #include "dc5v_uart.h"
  10. dc5v_uart_context_t dc5v_uart_context;
  11. static void debug_dump_reg(void)
  12. {
  13. printk("rst: 0x%x\n", sys_read32((0x40000000)));
  14. printk("clk: 0x%x\n", sys_read32((0x40001004)));
  15. //dump uart1 reg
  16. printk("ctl: 0x%x\n", sys_read32((0x4003c000 + 0x0)));
  17. printk("rx: 0x%x\n", sys_read32((0x4003c000 + 0x4)));
  18. printk("tx: 0x%x\n", sys_read32((0x4003c000 + 0x8)));
  19. printk("stat: 0x%x\n", sys_read32((0x4003c000 + 0x0c)));
  20. printk("br: 0x%x\n", sys_read32((0x4003c000 + 0x10)));
  21. //dump pmu reg
  22. printk("gdc5v: 0x%x\n", sys_read32((0x40068000 + 0x310)));
  23. printk("sys_set: 0x%x\n", sys_read32((0x40004000 + 0x108)));
  24. #if 1
  25. printk("pmu_det: 0x%x\n", sys_read32((0x40004000 + 0x10)));
  26. printk("ch_ctl: 0x%x\n", sys_read32((0x40004000 + 0x100)));
  27. printk("pmu sys_set: 0x%x\n", sys_read32((0x40004000 + 0x108)));
  28. printk("wk_ctl: 0x%x\n", sys_read32((0x40004000 + 0x110)));
  29. printk("wk_pd: 0x%x\n", sys_read32((0x40004000 + 0x114)));
  30. printk("cmu_s1: 0x%x\n", sys_read32((0x40001000 + 0xd0)));
  31. #endif
  32. }
  33. static u32_t get_diff_time(u32_t end_time, u32_t begin_time)
  34. {
  35. u32_t diff_time;
  36. if (end_time >= begin_time)
  37. {
  38. diff_time = (end_time - begin_time);
  39. }
  40. else
  41. {
  42. diff_time = ((u32_t)-1 - begin_time + end_time + 1);
  43. }
  44. return diff_time;
  45. }
  46. /**
  47. ** set register in pmusvcc
  48. **/
  49. void sys_svcc_reg_write(u32_t reg_addr, u32_t mask, u32_t value)
  50. {
  51. u32_t tmp = sys_read32(reg_addr);
  52. int i;
  53. tmp = (tmp & ~mask) | (value & mask);
  54. for (i = 0; i < 10; i++)
  55. {
  56. sys_write32(tmp, reg_addr);
  57. os_delay(200);
  58. if ((sys_read32(reg_addr) & mask) == (tmp & mask))
  59. {
  60. break;
  61. }
  62. }
  63. }
  64. /**
  65. ** 设置DC5V Uart切换电压
  66. **/
  67. void dc5v_uart_set_switch_volt(u32_t switch_volt)
  68. {
  69. if (switch_volt != DC5V_UART_SWITCH_VOLT_NA)
  70. {
  71. sys_svcc_reg_write
  72. (
  73. (u32_t)PMU_WKUP_CTL_REG,
  74. ((WKEN_CTL_DC5V_LHV_VOL_MASK) |
  75. WKEN_CTL_DC5VLV_WKEN
  76. ),
  77. ((switch_volt << WKEN_CTL_DC5V_LHV_VOL_SHIFT) |
  78. WKEN_CTL_DC5VLV_WKEN)
  79. );
  80. }
  81. else
  82. {
  83. sys_svcc_reg_write
  84. (
  85. (u32_t)PMU_WKUP_CTL_REG,
  86. WKEN_CTL_DC5VLV_WKEN,
  87. (0 << WKEN_CTL_DC5VLV_WKEN_SHIFT)
  88. );
  89. }
  90. /* Must delay some time to take effect?
  91. */
  92. os_sleep(10);
  93. printk("wkup_ctl: 0x%x", sys_read32(PMU_WKUP_CTL_REG));
  94. }
  95. /**
  96. ** 将DC5V Uart 设置到RX模式
  97. **/
  98. void dc5v_uart_set_rx_mode(void)
  99. {
  100. u32_t key = irq_lock();
  101. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  102. printk("Switch to RX!");
  103. dc5v_uart->trx_mode = DC5V_UART_RX_MODE;
  104. //MFP
  105. dc5v_uart->bak_GPIO_DC5V_CTL &= ~DC5V_CTL_AD_SEL;
  106. dc5v_uart->bak_GPIO_DC5V_CTL &= ~DC5V_CTL_MFP_MASK;
  107. if(strcmp(CONFIG_UART_DC5V_ON_DEV_NAME, "UART_1") == 0)
  108. {
  109. dc5v_uart->bak_GPIO_DC5V_CTL |= DC5V_CTL_MFP_UART1RX;
  110. }
  111. else
  112. {
  113. dc5v_uart->bak_GPIO_DC5V_CTL |= DC5V_CTL_MFP_UART2RX;
  114. }
  115. //dc5v_uart->bak_GPIO_DC5V_CTL |= DC5V_CTL_10KPU_EN;
  116. sys_write32(dc5v_uart->bak_GPIO_DC5V_CTL, GPIO_DC5V_CTL_REG);
  117. irq_unlock(key);
  118. }
  119. /**
  120. ** 将DC5V Uart 设置到TX模式
  121. **/
  122. static inline void dc5v_uart_set_tx_mode(void)
  123. {
  124. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  125. printk("Switch to TX!");
  126. k_timer_stop(&dc5v_uart->tx_context.tx_check_timer);
  127. if (dc5v_uart->trx_mode != DC5V_UART_TX_MODE)
  128. {
  129. dc5v_uart->trx_mode = DC5V_UART_TX_MODE;
  130. //MFP
  131. dc5v_uart->bak_GPIO_DC5V_CTL &= ~DC5V_CTL_AD_SEL;
  132. dc5v_uart->bak_GPIO_DC5V_CTL &= ~DC5V_CTL_MFP_MASK;
  133. if(strcmp(CONFIG_UART_DC5V_ON_DEV_NAME, "UART_1") == 0)
  134. {
  135. dc5v_uart->bak_GPIO_DC5V_CTL |= DC5V_CTL_MFP_UART1TX;
  136. }
  137. else
  138. {
  139. dc5v_uart->bak_GPIO_DC5V_CTL |= DC5V_CTL_MFP_UART2TX;
  140. }
  141. //dc5v_uart->bak_GPIO_DC5V_CTL |= DC5V_CTL_10KPU_EN;
  142. sys_write32(dc5v_uart->bak_GPIO_DC5V_CTL, GPIO_DC5V_CTL_REG);
  143. k_timer_stop(&dc5v_uart->tx_context.tx_switch_timer);
  144. dc5v_uart->tx_context.tx_switch_finish = false;
  145. k_timer_start(&dc5v_uart->tx_context.tx_switch_timer, K_USEC(200), K_NO_WAIT);
  146. }
  147. }
  148. /**
  149. ** 使能或关闭DC5V Uart功能
  150. **/
  151. void dc5v_uart_set_enable(bool enable)
  152. {
  153. u32_t key = irq_lock();
  154. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  155. if (enable)
  156. {
  157. printk("enable DC5V Uart!\n\n\n\n\n");
  158. #if 0
  159. dc5v_uart->bak_PMU_SYSTEM_SET_SVCC |= (SYSSET_UART_SW_SEL | SYSSET_UART_SW_MODE | SYSSET_UART_PWR_SEL);
  160. #else
  161. dc5v_uart->bak_PMU_SYSTEM_SET_SVCC &= (~SYSSET_UART_SW_MODE);
  162. dc5v_uart->bak_PMU_SYSTEM_SET_SVCC |= SYSSET_UART_SW_SEL;
  163. #endif
  164. sys_write32(dc5v_uart->bak_PMU_SYSTEM_SET_SVCC, PMU_SYS_SET_REG);
  165. /* Default set RX mode
  166. */
  167. dc5v_uart_set_rx_mode();
  168. }
  169. else
  170. {
  171. //switch to dc5v analog func
  172. printk("disable DC5V Uart!\n\n\n\n\n");
  173. dc5v_uart->bak_GPIO_DC5V_CTL |= DC5V_CTL_AD_SEL;
  174. sys_write32(dc5v_uart->bak_GPIO_DC5V_CTL, GPIO_DC5V_CTL_REG);
  175. }
  176. irq_unlock(key);
  177. }
  178. /**
  179. ** dc5v uart 将buffer数据输出
  180. **/
  181. int dc5v_uart_writedata(struct device *uart, const u8_t* buf, u32_t len, u32_t wait_end)
  182. {
  183. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  184. while(uart_acts_dma_send_complete((struct device *)dc5v_uart->tx_context.tx_dev) == 0)
  185. {
  186. printk("wait tx dma finish!");
  187. }
  188. uart_dma_send((struct device *)dc5v_uart->tx_context.tx_dev, (char*)buf, len);
  189. if (wait_end != 0)
  190. {
  191. /* 等待 TX FIFO 所有数据传输完成 */
  192. while (uart_irq_tx_complete(dc5v_uart->tx_context.tx_dev) == 0)
  193. ;
  194. }
  195. return len;
  196. }
  197. /**
  198. ** dc5v uart 切换到tx模式完成
  199. **/
  200. void dc5v_uart_tx_switch_complete(struct k_timer *timer)
  201. {
  202. u32_t key = irq_lock();
  203. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  204. k_timer_stop(&dc5v_uart->tx_context.tx_switch_timer);
  205. if (dc5v_uart->tx_context.tx_buf != NULL)
  206. {
  207. u8_t* tx_buf = dc5v_uart->tx_context.tx_buf;
  208. u16_t tx_len = dc5v_uart->tx_context.tx_len;
  209. dc5v_uart->tx_context.tx_buf = NULL;
  210. dc5v_uart->tx_context.tx_len = 0;
  211. dc5v_uart_writedata((struct device *)dc5v_uart->tx_context.tx_dev, tx_buf, tx_len, 0);
  212. }
  213. dc5v_uart->tx_context.tx_switch_finish = true;
  214. irq_unlock(key);
  215. }
  216. /**
  217. ** 延时到后,关闭dc5v uart
  218. **/
  219. void dc5v_uart_delay_disable(struct k_timer *timer)
  220. {
  221. u32_t key = irq_lock();
  222. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  223. dc5v_uart->enabled = NO;
  224. k_timer_stop(&dc5v_uart->disable_timer);
  225. dc5v_uart_set_enable(NO);
  226. irq_unlock(key);
  227. }
  228. /**
  229. ** 重启disable timer
  230. **/
  231. static inline void dc5v_uart_reset_delay_disable(void)
  232. {
  233. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  234. if (dc5v_uart->disable_delay_ms > 0)
  235. {
  236. k_timer_stop(&dc5v_uart->disable_timer);
  237. k_timer_start(&dc5v_uart->disable_timer, K_USEC(dc5v_uart->disable_delay_ms * 1000), K_NO_WAIT);
  238. }
  239. }
  240. static inline int dc5v_uart_tx_write(void* buf, int len)
  241. {
  242. u32_t key = irq_lock();
  243. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  244. int ret_val = 0;
  245. // last dma not finish
  246. if(uart_acts_dma_send_complete((struct device *)dc5v_uart->tx_context.tx_dev) == 0)
  247. {
  248. goto end;
  249. }
  250. dc5v_uart_set_tx_mode();
  251. if (!dc5v_uart->tx_context.tx_switch_finish)
  252. {
  253. dc5v_uart->tx_context.tx_buf = (u8_t*)buf;
  254. dc5v_uart->tx_context.tx_len = (u16_t)len;
  255. }
  256. else
  257. {
  258. dc5v_uart_writedata((struct device *)dc5v_uart->tx_context.tx_dev, buf, len, 0);
  259. }
  260. dc5v_uart->last_io_time = k_uptime_get_32();
  261. dc5v_uart_reset_delay_disable();
  262. ret_val = len;
  263. end:
  264. irq_unlock(key);
  265. return ret_val;
  266. }
  267. /**
  268. ** 检查DC5V Uart的写操作是否完成
  269. **/
  270. bool dc5v_uart_check_write_finish(void)
  271. {
  272. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  273. if(uart_acts_dma_send_complete((struct device *)dc5v_uart->tx_context.tx_dev) == 0)
  274. {
  275. return NO;
  276. }
  277. if(uart_irq_tx_complete(dc5v_uart->tx_context.tx_dev) == 0)
  278. {
  279. return NO;
  280. }
  281. return YES;
  282. }
  283. /**
  284. ** DC5V Uart 写接口
  285. **/
  286. int dc5v_uart_api_write(struct device* uart, const u8_t* buf, u32_t len, u32_t flags)
  287. {
  288. int ret_val;
  289. if (buf == NULL || len == 0)
  290. {
  291. return 0;
  292. }
  293. do
  294. {
  295. ret_val = dc5v_uart_tx_write((void*)buf, len);
  296. }
  297. while (ret_val == 0 && (!k_is_in_isr()));
  298. if (ret_val != 0 &&
  299. flags != 0)
  300. {
  301. while (!dc5v_uart_check_write_finish())
  302. ;
  303. }
  304. return ret_val;
  305. }
  306. void re_config_uart_param(u32_t baudrate)
  307. {
  308. struct uart_config uart_cfg;
  309. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  310. uart_cfg.baudrate = baudrate;
  311. uart_cfg.parity = dc5v_uart->cfg.DC5V_UART_Parity_Select;
  312. uart_cfg.stop_bits = UART_CFG_STOP_BITS_1;
  313. uart_cfg.data_bits = UART_CFG_DATA_BITS_8;
  314. uart_cfg.flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
  315. printk("config DC5V Uart BR: %d\n", uart_cfg.baudrate);
  316. uart_configure(dc5v_uart->tx_context.tx_dev, &uart_cfg);
  317. dc5v_uart->baud_rate = uart_cfg.baudrate;
  318. }
  319. int dc5v_uart_api_ioctl(struct device* uart, u32_t mode, void* param1, void* param2)
  320. {
  321. int ret = 0;
  322. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  323. if (dc5v_uart->dc5v_uart_init == 0)
  324. {
  325. return 0;
  326. }
  327. switch (mode)
  328. {
  329. case UART_SET_BAUDRATE:
  330. if(param1 == (void*)0)
  331. {
  332. param1 = (void*)dc5v_uart->cfg.DC5V_UART_Comm_Baudrate;
  333. }
  334. if((u32_t)param1 != dc5v_uart->baud_rate)
  335. {
  336. re_config_uart_param((u32_t)param1);
  337. }
  338. break;
  339. case UART_CHECK_WRITE_FINISH:
  340. ret = dc5v_uart_check_write_finish();
  341. break;
  342. case UART_IS_RX_FIFO_EMPTY:
  343. if(uart_irq_rx_ready(dc5v_uart->rx_context.rx_dev))
  344. {
  345. ret = 0;
  346. }
  347. else
  348. {
  349. ret = 1;
  350. }
  351. break;
  352. case UART_RX_DMA_ACCESS_SWITCH:
  353. if ((u32_t)param1)
  354. {
  355. uart_rx_dma_switch((struct device *)dc5v_uart->rx_context.rx_dev, TRUE, NULL, NULL);
  356. }
  357. else
  358. {
  359. uart_rx_dma_switch((struct device *)dc5v_uart->rx_context.rx_dev, FALSE, NULL, NULL);
  360. }
  361. break;
  362. default:
  363. break;
  364. }
  365. return ret;
  366. }
  367. /**
  368. ** tx finish check timer
  369. **/
  370. void dc5v_uart_check_tx_complete(struct k_timer *timer)
  371. {
  372. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  373. k_timer_stop(&dc5v_uart->tx_context.tx_check_timer);
  374. if(uart_irq_tx_complete(dc5v_uart->tx_context.tx_dev) != 0)
  375. {
  376. dc5v_uart_set_rx_mode();
  377. }
  378. else
  379. {
  380. k_timer_start(&dc5v_uart->tx_context.tx_check_timer, K_USEC(200), K_NO_WAIT);
  381. }
  382. }
  383. /**
  384. ** tx dma handle
  385. **/
  386. void dc5v_uart_tx_dma_handler(const struct device *dev, void *user_data,
  387. u32_t channel, int status)
  388. {
  389. if (status == DC5V_UART_DMA_IRQ_TC)
  390. {
  391. u32_t key = irq_lock();
  392. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  393. k_timer_stop(&dc5v_uart->tx_context.tx_check_timer);
  394. k_timer_start(&dc5v_uart->tx_context.tx_check_timer, K_USEC(200), K_NO_WAIT);
  395. irq_unlock(key);
  396. }
  397. }
  398. /**
  399. ** start dma to receive data
  400. **/
  401. void uart_ctrl_rx_dma_start(struct device *dev)
  402. {
  403. uart_rx_dma_switch(dev, TRUE, NULL, NULL);
  404. uart_dma_receive(dev, dc5v_uart_context.rx_context.dma_buf, UART_CTRL_RX_DMA_BUF_SIZE);
  405. /* 定时一小段时间后将 DMA 接收的数据保存至 data_buf
  406. */
  407. k_timer_start(&dc5v_uart_context.rx_context.rx_timer, K_USEC(UART_CTRL_RX_DMA_TIMER_US), K_NO_WAIT);
  408. }
  409. /**
  410. ** dc5v uart rx irq handle
  411. **/
  412. void dc5v_uart_rx_irq_handler(struct device *dev, void *user_data)
  413. {
  414. u32_t key = irq_lock();
  415. /* 暂时禁止 RX 中断
  416. */
  417. uart_irq_rx_disable(dev);
  418. /* 启用 DMA 进行数据接收
  419. */
  420. uart_ctrl_rx_dma_start(dev);
  421. irq_unlock(key);
  422. }
  423. /**
  424. ** dc5v uart irq handle
  425. **/
  426. static void dc5v_uart_irq_callback(const struct device *dev, void *user_data)
  427. {
  428. //printk("rx irq!\n");
  429. uart_irq_update(dev);
  430. if (uart_irq_rx_ready(dev)) {
  431. dc5v_uart_rx_irq_handler((struct device *)dev, user_data);
  432. }
  433. }
  434. void uart_ctrl_rx_timer_handler(struct k_timer *timer)
  435. {
  436. u32_t key = irq_lock();
  437. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  438. struct device* dev = (struct device *)dc5v_uart->rx_context.rx_dev;
  439. int len, count;
  440. /* 读取 DMA 接收到的数据之前先禁止 DRQ ?
  441. */
  442. uart_dma_receive_drq_switch(dev, FALSE);
  443. /* 等待当前正在进行的 DMA 传输完成?
  444. */
  445. k_busy_wait(1);
  446. k_timer_stop(&dc5v_uart->rx_context.rx_timer);
  447. count = uart_dma_receive_stop(dev);
  448. /* DMA 当前已接收到的数据?
  449. */
  450. len = UART_CTRL_RX_DMA_BUF_SIZE - count;
  451. if (len > 0)
  452. {
  453. /* 保存至 data_buf
  454. */
  455. //printk("put: 0x%x--%d\n", dc5v_uart->rx_context.dma_buf[0], len);
  456. ring_buf_put(&dc5v_uart->rx_context.rx_rbuf, dc5v_uart->rx_context.dma_buf, len);
  457. }
  458. /* RX_FIFO 中还有剩余数据时使用 CPU 进行读取
  459. */
  460. else
  461. {
  462. uart_rx_dma_switch(dev, FALSE, NULL, NULL);
  463. count = uart_fifo_read(dev, dc5v_uart->rx_context.dma_buf, UART_CTRL_RX_DMA_BUF_SIZE);
  464. if(count > 0)
  465. {
  466. //printk("put2: 0x%x--%d\n", dc5v_uart->rx_context.dma_buf[0],count);
  467. ring_buf_put(&dc5v_uart->rx_context.rx_rbuf, dc5v_uart->rx_context.dma_buf, count);
  468. len += count;
  469. }
  470. }
  471. if (len > 0)
  472. {
  473. /* 重新使能 DRQ
  474. */
  475. uart_dma_receive_drq_switch(dev, TRUE);
  476. /* 重新启用 DMA 接收数据
  477. */
  478. uart_ctrl_rx_dma_start(dev);
  479. }
  480. else
  481. {
  482. /* 重新使能 RX 中断
  483. */
  484. uart_irq_rx_enable(dev);
  485. }
  486. irq_unlock(key);
  487. }
  488. /**
  489. ** rx timer handle
  490. **/
  491. void dc5v_uart_rx_timer_handler(struct k_timer *timer)
  492. {
  493. u32_t key = irq_lock();
  494. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  495. u32_t data_count = UART_CTRL_RX_DATA_BUF_SIZE - ring_buf_space_get(&dc5v_uart->rx_context.rx_rbuf);
  496. uart_ctrl_rx_timer_handler(timer);
  497. if ((UART_CTRL_RX_DATA_BUF_SIZE - ring_buf_space_get(&dc5v_uart->rx_context.rx_rbuf)) > data_count)
  498. {
  499. dc5v_uart->last_io_time = k_uptime_get_32();
  500. dc5v_uart_reset_delay_disable();
  501. }
  502. irq_unlock(key);
  503. }
  504. /**
  505. ** read data by dc5v uart
  506. **/
  507. int dc5v_uart_rx_timed_read(void* buf, u32_t len, u32_t timeout_ms)
  508. {
  509. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  510. int count = 0;
  511. u32_t t;
  512. if (dc5v_uart->dc5v_uart_init == 0)
  513. {
  514. return 0;
  515. }
  516. printk("DC5V Uart Read!");
  517. t = k_uptime_get_32();
  518. while (count < len)
  519. {
  520. u8_t* ptr;
  521. int n;
  522. if (buf != NULL)
  523. {
  524. ptr = (u8_t*)buf + count;
  525. }
  526. else
  527. {
  528. ptr = NULL;
  529. }
  530. n = ring_buf_get(&dc5v_uart->rx_context.rx_rbuf, ptr, len - count);
  531. if (n <= 0)
  532. {
  533. os_sleep(1);
  534. n = ring_buf_get(&dc5v_uart->rx_context.rx_rbuf, ptr, len - count);
  535. }
  536. if (n > 0)
  537. {
  538. count += n;
  539. t = k_uptime_get_32();
  540. }
  541. else
  542. {
  543. if (get_diff_time(k_uptime_get_32(), t) >= timeout_ms)
  544. {
  545. break;
  546. }
  547. }
  548. }
  549. return count;
  550. }
  551. /**
  552. ** clear dc5v uart rx buffer
  553. **/
  554. void dc5v_uart_clear_rx_buf(u32_t wait_ms)
  555. {
  556. u32_t key;
  557. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  558. struct ring_buf* rx_buf = &dc5v_uart->rx_context.rx_rbuf;
  559. if (wait_ms > 0)
  560. {
  561. os_sleep(wait_ms);
  562. }
  563. key = irq_lock();
  564. ring_buf_reset(rx_buf);
  565. irq_unlock(key);
  566. }
  567. /**
  568. ** dc5v uart suspend
  569. **/
  570. void dc5v_uart_ctrl_suspend(void)
  571. {
  572. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  573. if (!dc5v_uart->suspended)
  574. {
  575. dc5v_uart->suspended = YES;
  576. while (!dc5v_uart_check_write_finish())
  577. ;
  578. dc5v_uart_set_enable(NO);
  579. dc5v_uart_set_switch_volt(DC5V_UART_SWITCH_VOLT_NA);
  580. }
  581. }
  582. void dc5v_uart_ctrl_resume(void)
  583. {
  584. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  585. if (dc5v_uart->suspended)
  586. {
  587. dc5v_uart->suspended = NO;
  588. dc5v_uart_set_switch_volt(dc5v_uart->cfg.DC5V_UART_Switch_Voltage);
  589. dc5v_uart_set_enable(dc5v_uart->enabled);
  590. dc5v_uart_clear_rx_buf(10);
  591. }
  592. }
  593. void dc5v_uart_set_rx_buf_size(u32_t buf_size)
  594. {
  595. u32_t key = irq_lock();
  596. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  597. if ((u32_t)dc5v_uart->rx_context.rx_rbuf.buf.buf32 != (u32_t)dc5v_uart->rx_context.data_buf)
  598. {
  599. app_mem_free((void*)dc5v_uart->rx_context.rx_rbuf.buf.buf32);
  600. }
  601. if (buf_size <= UART_CTRL_RX_DATA_BUF_SIZE)
  602. {
  603. ring_buf_init(&dc5v_uart->rx_context.rx_rbuf, UART_CTRL_RX_DATA_BUF_SIZE, dc5v_uart->rx_context.data_buf);
  604. }
  605. else
  606. {
  607. void* data_buf = app_mem_malloc(buf_size);
  608. ring_buf_init(&dc5v_uart->rx_context.rx_rbuf, buf_size, data_buf);
  609. }
  610. irq_unlock(key);
  611. }
  612. void dc5v_uart_set_enable_ex(bool enable, u32_t delay_disable)
  613. {
  614. u32_t key = irq_lock();
  615. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  616. if (enable)
  617. {
  618. //dc5v_uart->disable_delay_ms = 0;
  619. k_timer_stop(&dc5v_uart->disable_timer);
  620. if (!dc5v_uart->enabled)
  621. {
  622. dc5v_uart->enabled = YES;
  623. dc5v_uart_set_enable(YES);
  624. }
  625. }
  626. else
  627. {
  628. dc5v_uart->disable_delay_ms = delay_disable;
  629. k_timer_stop(&dc5v_uart->disable_timer);
  630. k_timer_start(&dc5v_uart->disable_timer, K_USEC(dc5v_uart->disable_delay_ms * 1000), K_NO_WAIT);
  631. }
  632. irq_unlock(key);
  633. }
  634. bool dc5v_uart_check_io_time(u32_t ms)
  635. {
  636. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  637. if (dc5v_uart->disable_delay_ms > 0)
  638. {
  639. return YES;
  640. }
  641. if (dc5v_uart->redirect_console_print &&
  642. dc5v_uart->enabled &&
  643. dc5v_uart->suspended == NO)
  644. {
  645. return YES;
  646. }
  647. if (dc5v_uart->last_io_time != 0 &&
  648. get_diff_time(k_uptime_get_32(), dc5v_uart->last_io_time) < ms)
  649. {
  650. return YES;
  651. }
  652. return NO;
  653. }
  654. int dc5v_uart_rx_read_byte(u8_t* byte)
  655. {
  656. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  657. uart_ctrl_rx_context_t* rx = &dc5v_uart->rx_context;
  658. if (ring_buf_get(&rx->rx_rbuf, byte, 1) != 0)
  659. {
  660. printk("Read 1byte: 0x%x\n", *byte);
  661. return 1;
  662. }
  663. return 0;
  664. }
  665. void dc5v_uart_rx_deal(void)
  666. {
  667. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  668. uart_ctrl_rx_context_t* rx = &dc5v_uart->rx_context;
  669. u8_t byte;
  670. while(dc5v_uart->rxdeal_need_quit == 0)
  671. {
  672. if(ring_buf_is_empty(&dc5v_uart->rx_context.rx_rbuf))
  673. {
  674. os_sleep(20);
  675. continue;
  676. }
  677. if (dc5v_uart_rx_read_byte(&byte) == 0)
  678. {
  679. continue;
  680. }
  681. if (rx->rx_data_handler != NULL)
  682. {
  683. //printk("Handle: %d", byte);
  684. rx->rx_data_handler(byte);
  685. }
  686. }
  687. dc5v_uart->rxdeal_quited = 1;
  688. printk("RX deal thread Exit!\n\n");
  689. return;
  690. }
  691. /** init
  692. **/
  693. bool dc5v_uart_ctrl_init(CFG_Type_DC5V_UART_Comm_Settings* cfg)
  694. {
  695. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  696. if (dc5v_uart_context.dc5v_uart_init != 0)
  697. {
  698. return YES;
  699. }
  700. if (cfg->Enable_DC5V_UART_Comm_Mode == NO ||
  701. cfg->DC5V_UART_Switch_Voltage == DC5V_UART_SWITCH_VOLT_NA ||
  702. cfg->DC5V_UART_Comm_Baudrate < 1000)
  703. {
  704. return NO;
  705. }
  706. cfg->Redirect_Console_Print = 0;
  707. memset(dc5v_uart, 0, sizeof(dc5v_uart_context_t));
  708. dc5v_uart->bak_PMU_SYSTEM_SET_SVCC = sys_read32(PMU_SYS_SET_REG);
  709. dc5v_uart->bak_GPIO_DC5V_CTL = sys_read32(GPIO_DC5V_CTL_REG);
  710. dc5v_uart->cfg = *cfg;
  711. /* DC5V_UART_DEV
  712. */
  713. dc5v_uart->tx_context.tx_dev = (struct device *)device_get_binding(CONFIG_UART_DC5V_ON_DEV_NAME);
  714. dc5v_uart->rx_context.rx_dev = (struct device *)device_get_binding(CONFIG_UART_DC5V_ON_DEV_NAME);
  715. /* tx config
  716. */
  717. k_timer_init(&dc5v_uart->tx_context.tx_check_timer, dc5v_uart_check_tx_complete, NULL);
  718. k_timer_init(&dc5v_uart->tx_context.tx_switch_timer, dc5v_uart_tx_switch_complete, NULL);
  719. k_timer_init(&dc5v_uart->disable_timer, dc5v_uart_delay_disable, NULL);
  720. uart_dma_send_init((struct device *)dc5v_uart->tx_context.tx_dev, dc5v_uart_tx_dma_handler, NULL);
  721. uart_tx_dma_switch((struct device *)dc5v_uart->tx_context.tx_dev, TRUE, NULL, NULL);
  722. /* rx config
  723. */
  724. ring_buf_init(&dc5v_uart->rx_context.rx_rbuf, UART_CTRL_RX_DATA_BUF_SIZE, dc5v_uart->rx_context.data_buf);
  725. k_timer_init(&dc5v_uart->rx_context.rx_timer, dc5v_uart_rx_timer_handler, NULL);
  726. uart_dma_receive_init((struct device *)dc5v_uart->rx_context.rx_dev, NULL, NULL);
  727. uart_rx_dma_switch((struct device *)dc5v_uart->rx_context.rx_dev, FALSE, NULL, NULL);
  728. uart_irq_callback_set(dc5v_uart->rx_context.rx_dev, dc5v_uart_irq_callback);
  729. uart_irq_rx_enable(dc5v_uart->rx_context.rx_dev);
  730. /* reconfig uart param
  731. */
  732. re_config_uart_param(dc5v_uart->cfg.DC5V_UART_Comm_Baudrate);
  733. /* set switch volt
  734. */
  735. dc5v_uart_set_switch_volt(cfg->DC5V_UART_Switch_Voltage);
  736. if (cfg->Redirect_Console_Print)
  737. {
  738. dc5v_uart_set_enable((dc5v_uart->enabled = YES));
  739. dc5v_uart_clear_rx_buf(10);
  740. }
  741. else
  742. {
  743. dc5v_uart_set_enable((dc5v_uart->enabled = NO));
  744. }
  745. dc5v_uart->dc5v_uart_init = 1;
  746. return YES;
  747. }
  748. static void dc5v_uart_start_rxdeal(void)
  749. {
  750. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  751. if (dc5v_uart->dc5v_uart_init != 0)
  752. {
  753. dc5v_uart->rxdeal_need_quit = 0;
  754. dc5v_uart->rxdeal_quited = 0;
  755. dc5v_uart->rxdeal_thread_stack = app_mem_malloc(1024);
  756. os_thread_create(dc5v_uart->rxdeal_thread_stack, UART_RX_DATADEAL_STACK,
  757. (void *)dc5v_uart_rx_deal, NULL, NULL, NULL, UART_RX_THREAD_PRIO, 0, 0);
  758. #if 1
  759. dc5v_uart_set_enable((dc5v_uart->enabled = YES));
  760. dc5v_uart_clear_rx_buf(10);
  761. #endif
  762. debug_dump_reg();
  763. }
  764. else
  765. {
  766. printk("Err: dc5v uart not init!\n");
  767. }
  768. }
  769. static void dc5v_uart_stop_rxdeal(void)
  770. {
  771. dc5v_uart_context_t* dc5v_uart = &dc5v_uart_context;
  772. if (!dc5v_uart->rxdeal_thread_stack)
  773. {
  774. return;
  775. }
  776. dc5v_uart->rxdeal_need_quit = 1;
  777. while (!dc5v_uart->rxdeal_quited)
  778. os_sleep(1);
  779. app_mem_free(dc5v_uart->rxdeal_thread_stack);
  780. dc5v_uart->rxdeal_thread_stack = NULL;
  781. }
  782. int dc5v_uart_operate(u32_t cmd, void* param1, u32_t param2, u32_t param3)
  783. {
  784. int ret_val = 0;
  785. if (cmd == DC5V_UART_INIT)
  786. {
  787. ret_val = dc5v_uart_ctrl_init(param1);
  788. return ret_val;
  789. }
  790. if (dc5v_uart_context.dc5v_uart_init == 0)
  791. {
  792. printk("not init yet!");
  793. return 0;
  794. }
  795. switch (cmd)
  796. {
  797. case DC5V_UART_SUSPEND:
  798. {
  799. dc5v_uart_ctrl_suspend();
  800. break;
  801. }
  802. case DC5V_UART_RESUME:
  803. {
  804. dc5v_uart_ctrl_resume();
  805. break;
  806. }
  807. case DC5V_UART_SET_RX_DATA_HANDLER:
  808. {
  809. dc5v_uart_context.rx_context.rx_data_handler = param1;
  810. break;
  811. }
  812. case DC5V_UART_SET_RX_BUF_SIZE:
  813. {
  814. dc5v_uart_set_rx_buf_size(param2);
  815. break;
  816. }
  817. case DC5V_UART_READ:
  818. {
  819. ret_val = dc5v_uart_rx_timed_read(param1, param2, param3);
  820. break;
  821. }
  822. case DC5V_UART_WRITE:
  823. {
  824. ret_val = dc5v_uart_api_write(NULL, param1, param2, param3);
  825. break;
  826. }
  827. case DC5V_UART_IOCTL:
  828. {
  829. ret_val = dc5v_uart_api_ioctl
  830. (
  831. NULL, (u32_t)param1, (void*)param2, (void*)param3
  832. );
  833. break;
  834. }
  835. case DC5V_UART_CHECK_IO_TIME:
  836. {
  837. ret_val = dc5v_uart_check_io_time(param2);
  838. break;
  839. }
  840. case DC5V_UART_SET_ENABLE:
  841. {
  842. dc5v_uart_set_enable_ex(param2, param3);
  843. break;
  844. }
  845. case DC5V_UART_RUN_RXDEAL:
  846. {
  847. dc5v_uart_start_rxdeal();
  848. break;
  849. }
  850. case DC5V_UART_STOP_RXDEAL:
  851. {
  852. dc5v_uart_stop_rxdeal();
  853. break;
  854. }
  855. }
  856. return ret_val;
  857. }