bt_drv.c 39 KB

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  1. /*
  2. * Copyright (c) 2020 Actions Semiconductor Co., Ltd
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. /**
  7. * @file
  8. * @brief Bluetooth driver for Actions SoC
  9. */
  10. #include <stdio.h>
  11. #include <string.h>
  12. #include <errno.h>
  13. #include <sys/__assert.h>
  14. #include <stdbool.h>
  15. #include <kernel.h>
  16. #include <device.h>
  17. #include <init.h>
  18. #include <soc_atp.h>
  19. #include <drivers/ipmsg.h>
  20. #include <sys/printk.h>
  21. #include <sys/byteorder.h>
  22. #include <drivers/bluetooth/bt_drv.h>
  23. #include <compensation.h>
  24. #include "ecc_acts.h"
  25. #ifdef CONFIG_ACTS_HRTIMER
  26. #include <drivers/hrtimer.h>
  27. #endif
  28. #ifdef CONFIG_PROPERTY
  29. #include <property_manager.h>
  30. #endif
  31. #ifdef CONFIG_SYS_WAKELOCK
  32. #include <sys_wakelock.h>
  33. #endif
  34. #ifdef CONFIG_WATCHDOG
  35. #include <watchdog_hal.h>
  36. #endif
  37. #include <debug/ramdump.h>
  38. #include <logging/log.h>
  39. LOG_MODULE_REGISTER(bt_drv, CONFIG_LOG_DEFAULT_LEVEL);
  40. #define CONFIG_HCI_RX_THREAD 1
  41. #define CFG_USE_TWS_SHARERAM_PKT 0
  42. #define BTDRV_EFUSE_CAP_RECORD (CONFIG_COMPENSATION_FREQ_INDEX_NUM)
  43. #ifdef CONFIG_BT_HCI_TX_PRINT
  44. static const char *tx_type_str[] = {
  45. "NULL:",
  46. "TX:01 ",
  47. "TX:02 ",
  48. "TX:03 ",
  49. "TX:04 "
  50. };
  51. #endif
  52. #ifdef CONFIG_BT_HCI_RX_PRINT
  53. static const char *rx_type_str[] = {
  54. "NULL:",
  55. "RX:01 ",
  56. "RX:02 ",
  57. "RX:03 ",
  58. "RX:04 ",
  59. };
  60. #endif
  61. #define BTC_BIN_ADDR (0x08100000)
  62. #define BTC_BIN_SIZE (0x34000)
  63. enum {
  64. BT_CPU_ENABLE,
  65. BT_CPU_READY,
  66. #ifdef CONFIG_BT_CTRL_TWS
  67. /* Need to clear bt cpu tws0 pending */
  68. BT_CPU_TWS0_PENDING,
  69. BT_CPU_TWS1_PENDING,
  70. #endif
  71. BT_CPU_NUM_FLAGS,
  72. };
  73. #ifdef CONFIG_BT_CTRL_REG
  74. enum {
  75. PENDING_READ_BB_REG,
  76. PENDING_READ_RF_REG,
  77. NUM_REG_FLAGS,
  78. };
  79. #endif
  80. static struct {
  81. struct device *dev;
  82. ATOMIC_DEFINE(flags, BT_CPU_NUM_FLAGS);
  83. btdrv_hci_cb_t *hci_cb;
  84. struct k_sem ready_sem;
  85. struct k_sem hci_rx_sem;
  86. #ifdef CONFIG_BT_CTRL_LOG
  87. struct k_sem log_rx_sem;
  88. #endif
  89. /* message send to bt cpu */
  90. rbuf_msg_t msg;
  91. uint32_t msg_tx_id;
  92. uint32_t msg_rx_id;
  93. uint32_t hci_tx_id;
  94. uint32_t hci_rx_id;
  95. uint32_t log_rx_id;
  96. uint32_t bt_info_id;
  97. #ifdef CONFIG_BT_CTRL_TWS
  98. btdrv_tws_cb_t tws0_cb;
  99. btdrv_tws_cb_t tws1_cb;
  100. uint32_t tws_tx_id[2];
  101. uint32_t tws_rx_id[2];
  102. #endif
  103. } btc = {
  104. .ready_sem = Z_SEM_INITIALIZER(btc.ready_sem, 0, 1),
  105. .hci_rx_sem = Z_SEM_INITIALIZER(btc.hci_rx_sem, 0, UINT_MAX),
  106. #ifdef CONFIG_BT_CTRL_LOG
  107. .log_rx_sem = Z_SEM_INITIALIZER(btc.log_rx_sem, 0, UINT_MAX),
  108. #endif
  109. };
  110. #ifdef CONFIG_BT_CTRL_REG
  111. static struct {
  112. struct k_work work;
  113. ATOMIC_DEFINE(flag, NUM_REG_FLAGS);
  114. uint16_t size;
  115. /* baseband register address */
  116. uint32_t bb_reg;
  117. uint16_t rf_reg;
  118. } btc_reg;
  119. #endif
  120. #ifdef CONFIG_BT_ECC_ACTS
  121. static struct ecc_info {
  122. struct k_work work;
  123. ATOMIC_DEFINE(flag, NUM_ECC_FLAGS);
  124. /* ecc request data size */
  125. uint16_t size;
  126. /* ecc request data */
  127. uint8_t req[128];
  128. /* ecc response data */
  129. uint8_t rsp[128];
  130. } btc_ecc;
  131. #endif
  132. #ifdef CONFIG_BT_CTRL_TWS
  133. struct btc_tws {
  134. /* tws interrupt time */
  135. uint32_t bt_clk;
  136. uint16_t intra_off;
  137. /* timer mode: us/navtive */
  138. uint8_t mode;
  139. /* flag of esco/iso pkt */
  140. uint8_t flag;
  141. /* tws interrupt type */
  142. uint8_t type;
  143. /* clear interrup pending counter */
  144. uint8_t pcnt;
  145. /* write data counter */
  146. uint8_t wcnt;
  147. /* read data counter */
  148. uint8_t rcnt;
  149. /* pkt sequence number */
  150. uint16_t seq;
  151. /* data len of hci pkt */
  152. uint16_t data_len;
  153. #if CFG_USE_TWS_SHARERAM_PKT
  154. /* hci pkt */
  155. uint8_t data[256];
  156. #endif
  157. } __packed;
  158. #define BT_TWS_SIZE sizeof(struct btc_tws)
  159. /* tws_tx: main -> bt. tws_rx: bt -> main. */
  160. static struct btc_tws *tws_rx[2];
  161. static struct btc_tws *tws_tx[2];
  162. #endif
  163. #if CONFIG_HCI_RX_THREAD
  164. static K_THREAD_STACK_DEFINE(rx_thread_stack, 1024);
  165. static struct k_thread rx_thread_data;
  166. static bool rx_exit = 0;
  167. #endif
  168. #ifdef CONFIG_BT_CTRL_LOG
  169. #define BTC_LOG_SIZE (256)
  170. #define CONFIG_BT_LOG_PRIO (1)
  171. #define CONFIG_BT_LOG_STACK_SIZE (1024)
  172. static K_THREAD_STACK_DEFINE(log_thread_stack, CONFIG_BT_LOG_STACK_SIZE);
  173. static struct k_thread log_thread_data;
  174. static char log_buf[BTC_LOG_SIZE + 1];
  175. static bool log_exit = 0;
  176. #endif
  177. #ifdef CONFIG_ACTS_HRTIMER
  178. /* For current saft modify, use one independent thread, is better merge in log thread */
  179. #define CONFIG_BT_MONITOR_PRIO (1)
  180. #define CONFIG_BT_MONITOR_STACK_SIZE (1024)
  181. #define BT_MONTIR_HRTIMER_TIME (1000*1000*300) /* 300s */
  182. static uint32_t bt_runing_cnt;
  183. static bool monitor_exit = 0;
  184. static struct hrtimer bt_monitor_hrtimer;
  185. static K_SEM_DEFINE(bt_monnitor_sem, 0, 1);
  186. static struct k_thread bt_monitor_thread_data;
  187. static K_THREAD_STACK_DEFINE(bt_monitor_thread_stack, CONFIG_BT_MONITOR_STACK_SIZE);
  188. static void bt_monitor_thread(void *p1, void *p2, void *p3);
  189. static void bt_monitor_hrtimer_callback(struct hrtimer *timer, void *expiry_fn_arg);
  190. #endif
  191. /* custom hci buf header */
  192. struct bt_hci_hdr {
  193. /* length of hci packet, round up to 4-byte */
  194. uint16_t len;
  195. /* hci packet type */
  196. uint8_t type;
  197. uint8_t rfu;
  198. } __packed;
  199. #define BT_HCI_HDR_SIZE sizeof(struct bt_hci_hdr)
  200. /* hci rx/tx data transmit on rbuf */
  201. static struct hci_data {
  202. /* hci header */
  203. union {
  204. struct bt_hci_hdr hdr;
  205. uint8_t hdr_buff[BT_HCI_HDR_SIZE];
  206. };
  207. /* hci packet, Core 5.2 [Vol 4, Part E, 5.4] */
  208. uint8_t *pkt;
  209. /* length of hci packet */
  210. uint16_t pkt_len;
  211. /* total length of hci data, round up to 4-byte */
  212. uint16_t total;
  213. /* current offset of hci packet */
  214. uint16_t offset;
  215. /* need to copy header if false */
  216. uint8_t hdr_len;
  217. bool has_hdr;
  218. } rx, tx;
  219. #ifdef CONFIG_BT_ECC_ACTS
  220. static int print_hex(const char *prefix, const uint8_t *data, int size)
  221. {
  222. int n = 0;
  223. if (!size) {
  224. printk("%s zero-length signal packet\n", prefix);
  225. return 0;
  226. }
  227. if (prefix) {
  228. printk("%s", prefix);
  229. }
  230. while (size--) {
  231. printk("%02x ", *data++);
  232. n++;
  233. if (n % 16 == 0) {
  234. printk("\n");
  235. }
  236. }
  237. if (n % 16) {
  238. printk("\n");
  239. }
  240. return 0;
  241. }
  242. #endif
  243. static void rbuf_info_dump(rbuf_t *rbuf)
  244. {
  245. if ((rbuf->tmp_head != rbuf->head) || (rbuf->tmp_tail != rbuf->tail)) {
  246. printk("tmp head %u, head %u, tmp tail %u, tail %u\n",
  247. rbuf->tmp_head, rbuf->head, rbuf->tmp_tail, rbuf->tail);
  248. }
  249. }
  250. #ifdef CONFIG_BT_CTRL_LOG
  251. static int log_wait_rd_size;
  252. static int log_already_rd_size;
  253. static int btc_log_handler(void *context, void *data, unsigned int size)
  254. {
  255. memcpy(&log_buf[log_already_rd_size], data, size);
  256. log_already_rd_size += size;
  257. if (log_wait_rd_size == log_already_rd_size) {
  258. log_buf[log_already_rd_size] = '\0';
  259. printk("[BTC] %s", log_buf);
  260. log_wait_rd_size = 0;
  261. }
  262. return size;
  263. }
  264. static void log_thread(void *p1, void *p2, void *p3)
  265. {
  266. ARG_UNUSED(p1);
  267. ARG_UNUSED(p2);
  268. ARG_UNUSED(p3);
  269. LOG_INF("log thread started");
  270. while (1) {
  271. k_sem_take(&btc.log_rx_sem, K_FOREVER);
  272. if (1 == log_exit) {
  273. log_exit = 0;
  274. k_thread_priority_set(k_current_get(), -1);
  275. printk("log thread exit. %d\n",__LINE__);
  276. return;
  277. }
  278. log_wait_rd_size = rbuf_get_length(RBUF_FR_OF(btc.log_rx_id));
  279. if (log_wait_rd_size == 0) {
  280. continue;
  281. }
  282. if (log_wait_rd_size > BTC_LOG_SIZE) {
  283. printk("Len err %d\n", log_wait_rd_size);
  284. log_wait_rd_size = BTC_LOG_SIZE;
  285. }
  286. log_already_rd_size = 0;
  287. ipmsg_recv(btc.log_rx_id, log_wait_rd_size, btc_log_handler, NULL);
  288. if (log_wait_rd_size) {
  289. ipmsg_recv(btc.log_rx_id, (log_wait_rd_size - log_already_rd_size), btc_log_handler, NULL);
  290. }
  291. if (log_wait_rd_size) {
  292. printk("R err %d %d\n", log_wait_rd_size, log_already_rd_size);
  293. }
  294. k_yield();
  295. }
  296. }
  297. #endif
  298. static unsigned int rbuf_put_data(uint32_t id, void *data, uint16_t len)
  299. {
  300. uint32_t size;
  301. void *buf = NULL;
  302. if (!data || !len) {
  303. return 0;
  304. }
  305. buf = rbuf_put_claim(RBUF_FR_OF(id), len, &size);
  306. if (!buf) {
  307. return 0;
  308. }
  309. memcpy(buf, data, MIN(len, size));
  310. rbuf_put_finish(RBUF_FR_OF(id), size);
  311. return size;
  312. }
  313. static unsigned int rbuf_get_data(uint32_t id, void *dst, uint16_t len)
  314. {
  315. uint32_t size;
  316. void *buf = NULL;
  317. if (!dst || !len) {
  318. return 0;
  319. }
  320. buf = rbuf_get_claim(RBUF_FR_OF(id), len, &size);
  321. if (!buf) {
  322. return 0;
  323. }
  324. memcpy(dst, buf, MIN(len, size));
  325. rbuf_get_finish(RBUF_FR_OF(id), size);
  326. return size;
  327. }
  328. #ifdef CONFIG_BT_ECC_ACTS
  329. static void ecc_send(unsigned short type, int err, int id, void *data, uint16_t len)
  330. {
  331. unsigned short flag = 0;
  332. uint8_t *p_data = data;
  333. uint16_t pos = 0, copy_len;
  334. k_sched_lock();
  335. btc.msg.type = type;
  336. btc.msg.flag = flag++;
  337. btc.msg.data.w[0] = err;
  338. btc.msg.data.w[1] = id;
  339. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  340. if ((err == 0) && data) {
  341. while (pos < len) {
  342. btc.msg.type = type;
  343. btc.msg.flag = flag++;
  344. copy_len = ((len - pos) > 16) ? 16 : (len - pos);
  345. memcpy(btc.msg.data.b, &p_data[pos], copy_len);
  346. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  347. pos += copy_len;
  348. }
  349. }
  350. ipmsg_notify(btc.dev);
  351. k_sched_unlock();
  352. }
  353. static int emulate_le_p192_public_key(void)
  354. {
  355. int ret;
  356. struct bt_gen_p192_pk_rsp *rsp = (void *)btc_ecc.rsp;
  357. LOG_INF("gen p192 public key");
  358. ret = ecc_gen_p192_pk(rsp->public_key, rsp->private_key);
  359. if (ret) {
  360. goto done;
  361. }
  362. /* Convert key from big-endian to little-endian */
  363. sys_mem_swap(rsp->public_key, 24);
  364. sys_mem_swap(&rsp->public_key[24], 24);
  365. sys_mem_swap(rsp->private_key, 24);
  366. print_hex("public key: ", rsp->public_key, 48);
  367. print_hex("private key: ", rsp->private_key, 24);
  368. done:
  369. ecc_send(MSG_BT_GEN_P192_PK, ret, sizeof(*rsp), rsp, sizeof(*rsp));
  370. return ret;
  371. }
  372. static int emulate_le_p192_dhkey(void)
  373. {
  374. int err;
  375. struct bt_gen_p192_dhkey_req *req = (void *)btc_ecc.req;
  376. struct bt_gen_p192_dhkey_rsp *rsp = (void *)btc_ecc.rsp;
  377. btc.msg.type = MSG_BT_GEN_P192_DHKEY;
  378. LOG_INF("gen p192 dhkey");
  379. print_hex("remote pk: ", req->remote_pk, 48);
  380. print_hex("private key: ", req->private_key, 24);
  381. /* Convert X and Y coordinates from little-endian to
  382. * big-endian (expected by the crypto API).
  383. */
  384. sys_mem_swap(req->remote_pk, 24);
  385. sys_mem_swap(&req->remote_pk[24], 24);
  386. /* valid remote public key first and send the result to btc */
  387. err = ecc_valid_p192_pk(req->remote_pk);
  388. if (err) {
  389. goto done;
  390. }
  391. sys_mem_swap(req->private_key, 24);
  392. err = ecc_gen_p192_dhkey(req->remote_pk, req->private_key, rsp->dhkey);
  393. if (err) {
  394. goto done;
  395. }
  396. /* Convert dhkey from big-endian to little-endian */
  397. sys_mem_swap(rsp->dhkey, 24);
  398. rsp->id = req->id;
  399. print_hex("dhkey: ", rsp->dhkey, 24);
  400. done:
  401. ecc_send(MSG_BT_GEN_P192_DHKEY, err, (int)req->id, rsp->dhkey, sizeof(rsp->dhkey));
  402. return err;
  403. }
  404. static int emulate_le_p256_public_key(void)
  405. {
  406. int ret;
  407. struct bt_gen_p256_pk_rsp *rsp = (void *)btc_ecc.rsp;
  408. LOG_INF("gen p256 pk");
  409. ret = ecc_gen_p256_pk(rsp->public_key, rsp->private_key);
  410. if (ret) {
  411. goto done;
  412. }
  413. sys_mem_swap(rsp->public_key, 32);
  414. sys_mem_swap(&rsp->public_key[32], 32);
  415. sys_mem_swap(rsp->private_key, 32);
  416. print_hex("public key: ", rsp->public_key, 64);
  417. print_hex("private key: ", rsp->private_key, 32);
  418. done:
  419. ecc_send(MSG_BT_GEN_P256_PK, ret, sizeof(*rsp), rsp, sizeof(*rsp));
  420. return ret;
  421. }
  422. static int emulate_le_p256_dhkey(void)
  423. {
  424. int err;
  425. struct bt_gen_p256_dhkey_req *req = (void *)btc_ecc.req;
  426. struct bt_gen_p256_dhkey_rsp *rsp = (void *)btc_ecc.rsp;
  427. btc.msg.type = MSG_BT_GEN_P256_DHKEY;
  428. LOG_INF("gen p256 dhkey");
  429. print_hex("remote pk: ", req->remote_pk, 64);
  430. print_hex("private key: ", req->private_key, 32);
  431. /* Convert X and Y coordinates from little-endian to
  432. * big-endian (expected by the crypto API).
  433. */
  434. sys_mem_swap(req->remote_pk, 32);
  435. sys_mem_swap(&req->remote_pk[32], 32);
  436. /* valid remote public key first and send the result to btc */
  437. err = ecc_valid_p256_pk(req->remote_pk);
  438. if (err) {
  439. goto done;
  440. }
  441. sys_mem_swap(req->private_key, 32);
  442. err = ecc_gen_p256_dhkey(req->remote_pk, req->private_key, rsp->dhkey);
  443. if (err) {
  444. goto done;
  445. }
  446. /* Convert dhkey from little-endian to big-endian */
  447. sys_mem_swap(rsp->dhkey, 32);
  448. rsp->id = req->id;
  449. print_hex("dhkey: ", rsp->dhkey, 32);
  450. done:
  451. ecc_send(MSG_BT_GEN_P256_DHKEY, err, (int)req->id, rsp->dhkey, sizeof(rsp->dhkey));
  452. return err;
  453. }
  454. static void emulate_key(struct k_work *item)
  455. {
  456. if (btc_ecc.size) {
  457. rbuf_get_data(btc.msg_rx_id, (void *)btc_ecc.req, btc_ecc.size);
  458. }
  459. if (atomic_test_bit(btc_ecc.flag, PENDING_P192_PUB_KEY)) {
  460. emulate_le_p192_public_key();
  461. atomic_clear_bit(btc_ecc.flag, PENDING_P192_PUB_KEY);
  462. } else if (atomic_test_bit(btc_ecc.flag, PENDING_P192_DHKEY)) {
  463. emulate_le_p192_dhkey();
  464. atomic_clear_bit(btc_ecc.flag, PENDING_P192_DHKEY);
  465. } else if (atomic_test_bit(btc_ecc.flag, PENDING_P256_PUB_KEY)) {
  466. emulate_le_p256_public_key();
  467. atomic_clear_bit(btc_ecc.flag, PENDING_P256_PUB_KEY);
  468. } else if (atomic_test_bit(btc_ecc.flag, PENDING_P256_DHKEY)) {
  469. emulate_le_p256_dhkey();
  470. atomic_clear_bit(btc_ecc.flag, PENDING_P256_DHKEY);
  471. } else {
  472. LOG_ERR("Unhandled ECC request");
  473. }
  474. }
  475. #endif
  476. #ifdef CONFIG_BT_CTRL_REG
  477. static void btc_read_reg(struct k_work *work)
  478. {
  479. int size, i;
  480. void *buf;
  481. buf = rbuf_get_claim(RBUF_FR_OF(btc.msg_rx_id), btc_reg.size, &size);
  482. if (!buf) {
  483. return;
  484. }
  485. if (atomic_test_bit(btc_reg.flag, PENDING_READ_BB_REG)) {
  486. uint32_t *reg_32 = buf;
  487. for (i = 0; i < btc_reg.size/4; i++) {
  488. LOG_INF("0x%08x: 0x%08x", btc_reg.bb_reg + i*4, reg_32[i]);
  489. }
  490. atomic_clear_bit(btc_reg.flag, PENDING_READ_BB_REG);
  491. } else if (atomic_test_bit(btc_reg.flag, PENDING_READ_RF_REG)) {
  492. uint16_t *reg_16 = buf;
  493. for (i = 0; i < btc_reg.size/4; i++) {
  494. LOG_INF("0x%04x: 0x%04x", btc_reg.rf_reg + i, reg_16[i]);
  495. }
  496. atomic_clear_bit(btc_reg.flag, PENDING_READ_RF_REG);
  497. } else {
  498. LOG_ERR("Unknown reg to read");
  499. }
  500. rbuf_get_finish(RBUF_FR_OF(btc.msg_rx_id), size);
  501. }
  502. #endif
  503. static void btc_msg_handler(void)
  504. {
  505. uint16_t ret;
  506. rbuf_msg_t rx_msg = {0};
  507. #ifdef CONFIG_BT_ECC_ACTS
  508. /* wait for ecc request processing to complte */
  509. if (atomic_get(btc_ecc.flag)) {
  510. return;
  511. }
  512. #endif
  513. ret = rbuf_get_data(btc.msg_rx_id, &rx_msg, sizeof(rbuf_msg_t));
  514. if (ret != sizeof(rbuf_msg_t)) {
  515. return;
  516. }
  517. LOG_DBG("msg type: %x, data size: %u\n", rx_msg.type, rx_msg.data.w[0]);
  518. switch (rx_msg.type) {
  519. case MSG_BT_HCI_OK:
  520. k_sem_give(&btc.ready_sem);
  521. atomic_set_bit(btc.flags, BT_CPU_READY);
  522. break;
  523. #ifdef CONFIG_BT_ECC_ACTS
  524. case MSG_BT_GEN_P192_PK:
  525. btc_ecc.size = 0;
  526. atomic_set_bit(btc_ecc.flag, PENDING_P192_PUB_KEY);
  527. break;
  528. case MSG_BT_GEN_P192_DHKEY:
  529. btc_ecc.size = sizeof(struct bt_gen_p192_dhkey_req);
  530. atomic_set_bit(btc_ecc.flag, PENDING_P192_DHKEY);
  531. break;
  532. case MSG_BT_GEN_P256_PK:
  533. btc_ecc.size = 0;
  534. atomic_set_bit(btc_ecc.flag, PENDING_P256_PUB_KEY);
  535. break;
  536. case MSG_BT_GEN_P256_DHKEY:
  537. btc_ecc.size = sizeof(struct bt_gen_p256_dhkey_req);
  538. atomic_set_bit(btc_ecc.flag, PENDING_P256_DHKEY);
  539. break;
  540. #endif
  541. default:
  542. LOG_ERR("unknown msg(type %x)!", rx_msg.type);
  543. break;
  544. }
  545. #ifdef CONFIG_BT_ECC_ACTS
  546. /* process ecc requests */
  547. if (atomic_get(btc_ecc.flag) > 0) {
  548. acts_work_submit(&btc_ecc.work);
  549. return;
  550. }
  551. #endif
  552. #ifdef CONFIG_BT_CTRL_REG
  553. if (atomic_get(btc_reg.flag) > 0) {
  554. k_work_submit(&btc_reg.work);
  555. }
  556. #endif
  557. }
  558. /* process hci rx buf after reciving */
  559. static inline void read_complete(void)
  560. {
  561. #ifdef CONFIG_BT_HCI_RX_PRINT
  562. print_hex(rx_type_str[rx.hdr.type], rx.pkt, rx.pkt_len);
  563. #endif
  564. if (btc.hci_cb && rx.pkt) {
  565. btc.hci_cb->recv(rx.pkt_len);
  566. }
  567. memset(&rx, 0, sizeof(struct hci_data));
  568. /* if hci rx rbuf is not empty and hci rx sem is zero, then read again */
  569. if (!k_sem_count_get(&btc.hci_rx_sem) && ipmsg_pending(btc.hci_rx_id)) {
  570. k_sem_give(&btc.hci_rx_sem);
  571. }
  572. }
  573. static uint16_t btdrv_cal_acl_packet_need_len(uint8_t *hdr, uint16_t hdr_size, uint16_t exp_len)
  574. {
  575. uint16_t handle, need_len, l2cap_len;
  576. uint8_t flags;
  577. handle = (hdr[1] <<8 | hdr[0]);
  578. flags = (handle >> 12) & 0xF;
  579. if (flags == BT_ACL_HDL_FLAG_START) {
  580. if (hdr_size >= 6) {
  581. l2cap_len = (hdr[5] << 8 | hdr[4]);
  582. need_len = l2cap_len + HCI_ACL_HDR_SIZE + HCI_L2CAP_HEAD_SIZE;
  583. if (l2cap_len > L2CAP_BR_MAX_MTU_A2DP_AAC || exp_len > need_len) {
  584. LOG_ERR("l2cap_len too length %d exp_len %d hdr %2x %2x %2x %2x %2x %2x\n",
  585. l2cap_len, exp_len, hdr[0], hdr[1], hdr[2], hdr[3], hdr[4], hdr[5]);
  586. }
  587. return (need_len > exp_len)? need_len : exp_len;
  588. } else {
  589. if (BT_MAX_RX_ACL_LEN) {
  590. /* If the packet split by controler in transfer,
  591. * can't calculate the max need length, just alloc max length.
  592. */
  593. return (L2CAP_BR_MAX_MTU_A2DP_AAC + HCI_ACL_HDR_SIZE + HCI_L2CAP_HEAD_SIZE);
  594. } else {
  595. /* default buffer lengh */
  596. return 0;
  597. }
  598. }
  599. } else {
  600. return exp_len;
  601. }
  602. }
  603. static void get_rx_buf(uint8_t *hdr, uint16_t hdr_size)
  604. {
  605. uint8_t evt = 0;
  606. uint16_t need_buf_len;
  607. switch (rx.hdr.type) {
  608. case HCI_ACL:
  609. rx.pkt_len = (hdr[3]<<8 | hdr[2]) + HCI_ACL_HDR_SIZE;
  610. need_buf_len = btdrv_cal_acl_packet_need_len(hdr, hdr_size, rx.pkt_len);
  611. break;
  612. case HCI_SCO:
  613. rx.pkt_len = hdr[2] + HCI_SCO_HDR_SIZE;
  614. need_buf_len = rx.pkt_len;
  615. break;
  616. case HCI_EVT:
  617. evt = hdr[0];
  618. rx.pkt_len = hdr[1] + HCI_EVT_HDR_SIZE;
  619. need_buf_len = rx.pkt_len;
  620. break;
  621. case HCI_ISO:
  622. rx.pkt_len = (hdr[3]<<8 | hdr[2]) + HCI_ISO_HDR_SIZE;
  623. need_buf_len = rx.pkt_len;
  624. break;
  625. default:
  626. rx.pkt_len = 0;
  627. LOG_ERR("get_rx_buf unknow type %d !\n", rx.hdr.type);
  628. return;
  629. }
  630. if (btc.hci_cb && btc.hci_cb->get_buf) {
  631. rx.pkt = btc.hci_cb->get_buf(rx.hdr.type, evt, need_buf_len);
  632. }
  633. }
  634. static inline int read_hdr(void)
  635. {
  636. uint32_t size = 0;
  637. void *data = NULL;
  638. uint8_t read_size = BT_HCI_HDR_SIZE - rx.hdr_len;
  639. if (rx.has_hdr) {
  640. return rx.hdr_len;
  641. }
  642. data = rbuf_get_claim(RBUF_FR_OF(btc.hci_rx_id), read_size, &size);
  643. if (!data) {
  644. if (size) {
  645. LOG_INF("get buf header failed size %d", size);
  646. }
  647. rbuf_info_dump(RBUF_FR_OF(btc.hci_rx_id));
  648. return 0;
  649. }
  650. if (size != read_size) {
  651. LOG_INF("get buf header failed read %d size %d", read_size, size);
  652. }
  653. memcpy(&rx.hdr_buff[rx.hdr_len], data, size);
  654. rx.hdr_len += size;
  655. rbuf_get_finish(RBUF_FR_OF(btc.hci_rx_id), size);
  656. if (rx.hdr_len == BT_HCI_HDR_SIZE) {
  657. rx.total = rx.hdr.len;
  658. rx.has_hdr = true;
  659. }
  660. return rx.hdr_len;
  661. }
  662. static inline int read_buf(void)
  663. {
  664. unsigned int size = 0;
  665. void *data = NULL;
  666. uint16_t cpy_len = 0;
  667. data = rbuf_get_claim(RBUF_FR_OF(btc.hci_rx_id), rx.total, &size);
  668. if (!data) {
  669. LOG_INF("alloc hci rx rbuf failed total %d(%d) size %d", rx.total, rx.hdr.len, size);
  670. return 0;
  671. }
  672. if (!rx.pkt) {
  673. get_rx_buf((uint8_t *)data, (uint16_t)size);
  674. }
  675. if (rx.pkt) {
  676. cpy_len = MIN(rx.pkt_len - rx.offset, size);
  677. memcpy(rx.pkt + rx.offset, data, cpy_len);
  678. rx.offset += cpy_len;
  679. } else {
  680. LOG_ERR("read_buf total %d drop data %d!\n", rx.total, size);
  681. }
  682. rbuf_get_finish(RBUF_FR_OF(btc.hci_rx_id), size);
  683. rx.total -= size;
  684. return size;
  685. }
  686. #if CONFIG_HCI_RX_THREAD
  687. static void rx_thread(void *p1, void *p2, void *p3)
  688. {
  689. unsigned int size = 0;
  690. ARG_UNUSED(p1);
  691. ARG_UNUSED(p2);
  692. ARG_UNUSED(p3);
  693. LOG_INF("rx thread started");
  694. while (1) {
  695. k_sem_take(&btc.hci_rx_sem, K_FOREVER);
  696. if (rx_exit) {
  697. rx_exit = 0;
  698. k_thread_priority_set(k_current_get(), -1);
  699. printk("rx_thread exit.\n");
  700. return;
  701. }
  702. if (read_hdr() != BT_HCI_HDR_SIZE) {
  703. continue;
  704. }
  705. do {
  706. size = read_buf();
  707. } while (size && rx.total);
  708. if (!rx.total) {
  709. read_complete();
  710. } else {
  711. if (rx.pkt) {
  712. LOG_INF("read hci rx buf incompletely");
  713. } else {
  714. LOG_INF("read hci rx buf NULL");
  715. }
  716. }
  717. k_yield();
  718. }
  719. }
  720. #endif
  721. static inline unsigned int send_buf(void)
  722. {
  723. uint8_t *buf = NULL;
  724. uint16_t copy_len;
  725. unsigned int size = 0;
  726. buf = rbuf_put_claim(RBUF_FR_OF(btc.hci_tx_id), tx.total, &size);
  727. if (buf == NULL) {
  728. LOG_ERR("alloc hci tx rbuf failed");
  729. return 0;
  730. }
  731. if (!tx.has_hdr) {
  732. memcpy(buf, &tx.hdr, BT_HCI_HDR_SIZE);
  733. buf += BT_HCI_HDR_SIZE;
  734. copy_len = MIN(size - BT_HCI_HDR_SIZE, tx.pkt_len - tx.offset);
  735. tx.has_hdr = true;
  736. } else {
  737. copy_len = MIN(size, tx.pkt_len - tx.offset);
  738. }
  739. memcpy(buf, tx.pkt + tx.offset, copy_len);
  740. tx.offset += copy_len;
  741. rbuf_put_finish(RBUF_FR_OF(btc.hci_tx_id), size);
  742. tx.total -= size;
  743. return size;
  744. }
  745. /* data fmt: hdr(4) + payload(n) */
  746. int btdrv_send(uint8_t type, uint8_t *data, uint16_t len)
  747. {
  748. int err = 0;
  749. unsigned int size = 0;
  750. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  751. return -EINVAL;
  752. }
  753. if (!data || !len) {
  754. return -EINVAL;
  755. }
  756. tx.pkt = data;
  757. tx.total = ROUND_UP(len, 4) + BT_HCI_HDR_SIZE;
  758. tx.hdr.len = tx.total - BT_HCI_HDR_SIZE;
  759. tx.hdr.type = type;
  760. tx.pkt_len = len;
  761. do {
  762. size = send_buf();
  763. } while (size && tx.total);
  764. if (!tx.total) {
  765. ipmsg_notify(btc.dev);
  766. #ifdef CONFIG_BT_HCI_TX_PRINT
  767. print_hex(tx_type_str[tx.hdr.type], tx.pkt, tx.pkt_len);
  768. #endif
  769. } else {
  770. err = -EINVAL;
  771. LOG_ERR("send hci rbuf failed");
  772. }
  773. memset(&tx, 0, sizeof(struct hci_data));
  774. return err;
  775. }
  776. /* BTC interupt handler */
  777. static void btc_recv_cb(void *context, void *arg)
  778. {
  779. if (ipmsg_pending(btc.msg_rx_id)) {
  780. btc_msg_handler();
  781. #ifdef CONFIG_ACTS_HRTIMER
  782. bt_runing_cnt++;
  783. #endif
  784. }
  785. if (ipmsg_pending(btc.hci_rx_id)) {
  786. #if CONFIG_HCI_RX_THREAD
  787. k_sem_give(&btc.hci_rx_sem);
  788. #endif
  789. #ifdef CONFIG_ACTS_HRTIMER
  790. bt_runing_cnt++;
  791. #endif
  792. }
  793. #ifdef CONFIG_BT_CTRL_LOG
  794. if (ipmsg_pending(btc.log_rx_id)) {
  795. k_sem_give(&btc.log_rx_sem);
  796. }
  797. #endif
  798. #ifdef CONFIG_BT_CTRL_TWS
  799. /* tws0 interrupt pending has been cleared */
  800. if (atomic_test_bit(btc.flags, BT_CPU_TWS0_PENDING) &&
  801. (tws_rx[0]->pcnt == tws_tx[0]->pcnt)) {
  802. atomic_clear_bit(btc.flags, BT_CPU_TWS0_PENDING);
  803. }
  804. if (atomic_test_bit(btc.flags, BT_CPU_TWS1_PENDING) &&
  805. (tws_rx[1]->pcnt == tws_tx[1]->pcnt)) {
  806. atomic_clear_bit(btc.flags, BT_CPU_TWS1_PENDING);
  807. }
  808. #endif
  809. }
  810. #ifdef CONFIG_BT_CTRL_TWS
  811. static void btc_tws0_cb(void *context, void *arg)
  812. {
  813. if (btc.tws0_cb) {
  814. btc.tws0_cb();
  815. }
  816. atomic_set_bit(btc.flags, BT_CPU_TWS0_PENDING);
  817. tws_tx[0]->pcnt++;
  818. ipmsg_notify(btc.dev);
  819. }
  820. static void btc_tws1_cb(void *context, void *arg)
  821. {
  822. if (btc.tws1_cb) {
  823. btc.tws1_cb();
  824. }
  825. atomic_set_bit(btc.flags, BT_CPU_TWS1_PENDING);
  826. tws_tx[1]->pcnt++;
  827. ipmsg_notify(btc.dev);
  828. }
  829. #endif
  830. #ifdef CONFIG_BT_CTRL_LOG
  831. #ifdef CONFIG_PM_DEVICE
  832. static void bt_log_controler(bool log_on)
  833. {
  834. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  835. return;
  836. }
  837. //printk("bt_log_controler:%d\n",log_on);
  838. if (log_on) {
  839. btc.msg.type = MSG_BT_LOG_ON;
  840. btc.msg.data.w[0] = btc.log_rx_id;
  841. } else {
  842. btc.msg.type = MSG_BT_LOG_OFF;
  843. btc.msg.data.w[0] = 1; /* Log out from uart */
  844. }
  845. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  846. ipmsg_notify(btc.dev);
  847. }
  848. static void btc_pm_ctrl_cb(uint32_t command, uint32_t state)
  849. {
  850. switch (state) {
  851. case PM_DEVICE_ACTION_RESUME:
  852. bt_log_controler(true);
  853. break;
  854. case PM_DEVICE_ACTION_SUSPEND:
  855. bt_log_controler(false);
  856. break;
  857. case PM_DEVICE_ACTION_EARLY_SUSPEND:
  858. break;
  859. case PM_DEVICE_ACTION_LATE_RESUME:
  860. break;
  861. default:
  862. break;;
  863. }
  864. }
  865. #else
  866. #define btc_pm_ctrl_cb NULL
  867. #endif
  868. #endif
  869. static void set_mac(void)
  870. {
  871. int ret;
  872. const uint8_t *default_mac = "f44efd12a3b4";
  873. uint8_t addr[6], mac_str[13];
  874. #ifdef CONFIG_PROPERTY
  875. ret = property_get(CFG_BT_MAC, mac_str, 12);
  876. if(ret < 12) {
  877. LOG_WRN("property_get CFG_BT_MAC ret: %d", ret);
  878. memcpy(mac_str, default_mac, 12);
  879. }
  880. #else
  881. memcpy(mac_str, default_mac, 12);
  882. #endif
  883. ret = hex2bin(mac_str, 12, addr, 6);
  884. if (ret != 6) {
  885. LOG_ERR("invalid bt address");
  886. return;
  887. }
  888. btc.msg.type = MSG_BT_INIT;
  889. btc.msg.data.w[0] = addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | addr[5];
  890. btc.msg.data.w[1] = addr[0] << 8 | addr[1];
  891. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  892. }
  893. #ifdef CONFIG_BT_CTRL_TWS
  894. static struct btc_tws *tws_init(uint32_t *id)
  895. {
  896. struct btc_tws *tws;
  897. *id = ipmsg_create(RBUF_RAW, BT_TWS_SIZE);
  898. if (*id == 0) {
  899. return NULL;
  900. }
  901. rbuf_t *rbuf = RBUF_FR_OF(*id);
  902. tws = (void *)RBUF_FR_OF(rbuf->buf_off);
  903. memset(tws, 0, sizeof(struct btc_tws));
  904. return tws;
  905. }
  906. #endif
  907. static void send_init_msg(void)
  908. {
  909. set_mac();
  910. #ifdef CONFIG_BT_CTRL_RF_DEBUG
  911. btc.msg.type = MSG_BT_MDM_RF_DEBUG;
  912. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  913. #endif
  914. btc.msg.type = MSG_BT_HCI_BUF;
  915. btc.msg.data.w[0] = btc.hci_rx_id; /* bt -> main */
  916. btc.msg.data.w[1] = btc.hci_tx_id; /* main -> bt */
  917. btc.msg.data.w[2] = btc.log_rx_id; /* bt -> main */
  918. btc.msg.data.w[3] = btc.bt_info_id; /* bt store info for main */
  919. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  920. #ifdef CONFIG_BT_CTRL_TWS
  921. btc.msg.type = MSG_BT_TWS_INT;
  922. btc.msg.data.w[0] = btc.tws_rx_id[0]; /* bt -> main */
  923. btc.msg.data.w[1] = btc.tws_tx_id[0]; /* main -> bt */
  924. btc.msg.data.w[2] = btc.tws_rx_id[1];
  925. btc.msg.data.w[3] = btc.tws_tx_id[1];
  926. rbuf_put_data(btc.msg_tx_id, &btc.msg, sizeof(rbuf_msg_t));
  927. #endif
  928. }
  929. static void init_rbuf(void)
  930. {
  931. unsigned int *pdata;
  932. LOG_INF("Bt share ram size %d", INTER_RAM_SIZE);
  933. btc.msg_tx_id = rbuf_msg_create(CPU, BT, RB_MSG_SIZE);
  934. btc.msg_rx_id = rbuf_msg_create(BT, CPU, RB_MSG_SIZE);
  935. LOG_INF("msg tx id: %d, msg rx id: %d", btc.msg_tx_id, btc.msg_rx_id);
  936. #ifdef CONFIG_BT_CTRL_LOG
  937. btc.log_rx_id = ipmsg_create(RBUF_RAW, BTC_LOG_SIZE);
  938. LOG_INF("log id: %d", btc.log_rx_id);
  939. #endif
  940. btc.hci_rx_id = ipmsg_create(RBUF_RAW, CONFIG_BT_HCI_RX_RBUF_SIZE);
  941. btc.hci_tx_id = ipmsg_create(RBUF_RAW, CONFIG_BT_HCI_TX_RBUF_SIZE);
  942. LOG_INF("hci rx id: %d, hci tx id: %d", btc.hci_rx_id, btc.hci_tx_id);
  943. btc.bt_info_id = ipmsg_create(RBUF_RAW, BT_INFO_SHARE_SIZE);
  944. pdata = (unsigned int*)RBUF_FR_OF((RBUF_FR_OF(btc.bt_info_id))->buf_off);
  945. memset(pdata, 0, BT_INFO_SHARE_SIZE);
  946. LOG_INF("bt info id: %d %p", btc.bt_info_id, pdata);
  947. #ifdef CONFIG_BT_CTRL_TWS
  948. for (uint8_t i = 0; i < 2; i++) {
  949. tws_rx[i] = tws_init(&btc.tws_rx_id[i]);
  950. tws_tx[i] = tws_init(&btc.tws_tx_id[i]);
  951. LOG_INF("tws%d rx id: %d, tx id: %d", i, btc.tws_rx_id[i], btc.tws_tx_id[i]);
  952. }
  953. #endif
  954. send_init_msg();
  955. }
  956. int btdrv_set_init_param(btdrv_init_param_t *param)
  957. {
  958. ipmsg_btc_init_param_t btc_param;
  959. btc.dev = (struct device *)device_get_binding("BTC");
  960. if (!btc.dev) {
  961. LOG_ERR("get device BTC failed");
  962. return -EINVAL;
  963. }
  964. btc_param.hosc_capacity = param->hosc_capacity;
  965. #ifdef CONFIG_BT_QC_TEST
  966. LOG_INF("BT_QC_TEST cap %d", btc_param.hosc_capacity);
  967. #else
  968. #ifdef CONFIG_COMPENSATION_ACTS
  969. uint32_t cap_value = 0xFF;
  970. int ret = 0;
  971. ret = freq_compensation_get_cap(&cap_value);
  972. if (ret == TRIM_CAP_READ_NO_ERROR) {
  973. btc_param.hosc_capacity = (cap_value & 0xFF);
  974. LOG_INF("efuse cap valid %d cap %d", ret, btc_param.hosc_capacity);
  975. } else {
  976. LOG_INF("Not efuse cap, set cap %d", btc_param.hosc_capacity);
  977. }
  978. #ifdef CONFIG_TEMP_COMPENSATION_ACTS
  979. extern int cap_temp_comp_init(uint8_t base_cap);
  980. cap_temp_comp_init(btc_param.hosc_capacity);
  981. #endif
  982. #endif
  983. #endif
  984. btc_param.set_hosc_cap = param->set_hosc_cap;
  985. btc_param.set_max_rf_power = param->set_max_rf_power;
  986. btc_param.set_ble_rf_power = param->set_ble_rf_power;
  987. btc_param.bt_max_rf_tx_power = param->bt_max_rf_tx_power;
  988. btc_param.ble_rf_tx_power = param->ble_rf_tx_power;
  989. ipmsg_init_param(btc.dev, &btc_param);
  990. return 0;
  991. }
  992. #ifdef CONFIG_BT_FCC_TEST
  993. #define BT_UART_MFP_SEL 23
  994. static const struct acts_pin_config btc_fcc_uart[] = {
  995. {28, BT_UART_MFP_SEL | GPIO_CTL_PADDRV_LEVEL(1) | GPIO_CTL_PULLUP},
  996. {29, BT_UART_MFP_SEL | GPIO_CTL_PADDRV_LEVEL(1) | GPIO_CTL_PULLUP},
  997. };
  998. static void btdrv_run_fcc(void)
  999. {
  1000. unsigned int *cmd_reg_write, *cmd_reg_write_addr, *cmd_reg_write_val;
  1001. unsigned int *cmd_reg_read, *cmd_reg_read_addr, *cmd_reg_read_val;
  1002. unsigned int *cmd_efuse_write, *cmd_efuse_write_addr, *cmd_efuse_write_val;
  1003. unsigned int *cmd_efuse_read, *cmd_efuse_read_addr, *cmd_efuse_read_val;
  1004. unsigned int *cmd_bt_test_end;
  1005. unsigned int *cmd_rf_printf, *cmd_rf_printf_addr;
  1006. uint32_t flags;
  1007. flags = irq_lock();
  1008. k_sched_lock();
  1009. cmd_reg_write =(unsigned int *)(INTER_RAM_ADDR + 2*4);
  1010. cmd_reg_write_addr =(unsigned int *)(INTER_RAM_ADDR + 3*4);
  1011. cmd_reg_write_val =(unsigned int *)(INTER_RAM_ADDR + 4*4);
  1012. *cmd_reg_write = 0;
  1013. cmd_reg_read =(unsigned int *)(INTER_RAM_ADDR + 5*4);
  1014. cmd_reg_read_addr =(unsigned int *)(INTER_RAM_ADDR + 6*4);
  1015. cmd_reg_read_val =(unsigned int *)(INTER_RAM_ADDR + 7*4);
  1016. *cmd_reg_read = 0;
  1017. cmd_efuse_write =(unsigned int *)(INTER_RAM_ADDR + 8*4);
  1018. cmd_efuse_write_addr =(unsigned int *)(INTER_RAM_ADDR + 9*4);
  1019. cmd_efuse_write_val =(unsigned int *)(INTER_RAM_ADDR + 10*4);
  1020. *cmd_efuse_write = 0;
  1021. cmd_efuse_read =(unsigned int *)(INTER_RAM_ADDR + 11*4);
  1022. cmd_efuse_read_addr =(unsigned int *)(INTER_RAM_ADDR + 12*4);
  1023. cmd_efuse_read_val =(unsigned int *)(INTER_RAM_ADDR + 13*4);
  1024. *cmd_efuse_read = 0;
  1025. cmd_bt_test_end =(unsigned int *)(INTER_RAM_ADDR + 14*4);
  1026. *cmd_bt_test_end = 0;
  1027. cmd_rf_printf=(unsigned int *)(INTER_RAM_ADDR + 1024*4);
  1028. cmd_rf_printf_addr =(unsigned int *)(INTER_RAM_ADDR + 1028*4);
  1029. *cmd_rf_printf = 0;
  1030. LOG_INF("Enter FCC test mode!!\n");
  1031. k_sleep(K_MSEC(10));
  1032. acts_pinmux_setup_pins(btc_fcc_uart, ARRAY_SIZE(btc_fcc_uart));
  1033. #ifdef CONFIG_WATCHDOG
  1034. watchdog_stop();
  1035. #endif
  1036. #ifdef CONFIG_SYS_WAKELOCK
  1037. sys_wake_lock_ext(PARTIAL_WAKE_LOCK, BT_WAKE_LOCK_USER);
  1038. #endif
  1039. while (true) {
  1040. if (*cmd_reg_write == 0x88888888) {
  1041. LOG_INF("cmd_reg_write\n");
  1042. *cmd_reg_write = 0;
  1043. }
  1044. if (*cmd_reg_read == 0x88888888) {
  1045. LOG_INF("cmd_reg_read\n");
  1046. *cmd_reg_read = 0;
  1047. }
  1048. if (*cmd_efuse_write == 0x88888888) {
  1049. LOG_INF("cmd_efuse_write\n");
  1050. *cmd_efuse_write = 0;
  1051. }
  1052. if (*cmd_efuse_read == 0x88888888) {
  1053. if ((*cmd_efuse_read_addr) == 6) {
  1054. if (soc_atp_get_fcc_param(0, cmd_efuse_read_val)) {
  1055. *cmd_efuse_read_val = 0;
  1056. LOG_INF("invoked efuse\n");
  1057. }
  1058. } else if ((*cmd_efuse_read_addr) == 7) {
  1059. if (soc_atp_get_fcc_param(1, cmd_efuse_read_val)) {
  1060. *cmd_efuse_read_val = 0;
  1061. LOG_INF("invoked efuse\n");
  1062. }
  1063. } else {
  1064. *cmd_efuse_read_val = 0;
  1065. }
  1066. LOG_INF("cmd_efuse_read addr 0x%x value 0x%x\n", *cmd_efuse_read_addr, *cmd_efuse_read_val);
  1067. *cmd_efuse_read = 0;
  1068. }
  1069. if (*cmd_rf_printf == 0x88888888) {
  1070. LOG_INF("cmd_rf_printf %s\n", (const char *)cmd_rf_printf_addr);
  1071. *cmd_rf_printf = 0;
  1072. }
  1073. if (*cmd_bt_test_end == 0x88888888) {
  1074. LOG_INF("cmd_bt_test_end\n");
  1075. *cmd_bt_test_end = 0;
  1076. k_sched_unlock();
  1077. irq_unlock(flags);
  1078. break;
  1079. }
  1080. }
  1081. }
  1082. #endif
  1083. int btdrv_init(btdrv_hci_cb_t *cb)
  1084. {
  1085. int ret;
  1086. uint8_t irq;
  1087. LOG_INF("bt driver init");
  1088. if (atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1089. goto start_cpu;
  1090. }
  1091. if (!cb) {
  1092. return -EINVAL;
  1093. }
  1094. btc.hci_cb = cb;
  1095. #ifdef CONFIG_BT_CTRL_REG
  1096. k_work_init(&btc_reg.work, btc_read_reg);
  1097. #endif
  1098. #ifdef CONFIG_BT_ECC_ACTS
  1099. if (!btc_ecc.work.handler) {
  1100. ret = ecc_init();
  1101. if (ret) {
  1102. LOG_ERR("Ecc init failed");
  1103. }
  1104. k_work_init(&btc_ecc.work, emulate_key);
  1105. }
  1106. #endif
  1107. btc.dev = (struct device *)device_get_binding("BTC");
  1108. if (!btc.dev) {
  1109. LOG_ERR("get device BTC failed");
  1110. return -EINVAL;
  1111. }
  1112. irq = IPMSG_BTC_IRQ;
  1113. ipmsg_register_callback(btc.dev, btc_recv_cb, &irq);
  1114. #ifdef CONFIG_BT_CTRL_TWS
  1115. irq = IPMSG_TWS0_IRQ;
  1116. ipmsg_register_callback(btc.dev, btc_tws0_cb, &irq);
  1117. irq = IPMSG_TWS1_IRQ;
  1118. ipmsg_register_callback(btc.dev, btc_tws1_cb, &irq);
  1119. #endif
  1120. #ifdef CONFIG_BT_CTRL_LOG
  1121. irq = IPMSG_REG_PW_CTRL;
  1122. ipmsg_register_callback(btc.dev, (ipmsg_callback_t)btc_pm_ctrl_cb, &irq);
  1123. #endif
  1124. init_rbuf();
  1125. #if CONFIG_HCI_RX_THREAD
  1126. /* Start RX thread */
  1127. k_thread_create(&rx_thread_data, rx_thread_stack,
  1128. K_THREAD_STACK_SIZEOF(rx_thread_stack),
  1129. rx_thread, NULL, NULL, NULL,
  1130. K_PRIO_COOP(CONFIG_BT_HCI_RX_PRIO),
  1131. 0, K_NO_WAIT);
  1132. k_thread_name_set(&rx_thread_data, "BT HCI RX");
  1133. #endif
  1134. #ifdef CONFIG_BT_CTRL_LOG
  1135. k_thread_create(&log_thread_data, log_thread_stack,
  1136. K_THREAD_STACK_SIZEOF(log_thread_stack),
  1137. log_thread, NULL, NULL, NULL,
  1138. CONFIG_BT_LOG_PRIO,
  1139. 0, K_NO_WAIT);
  1140. k_thread_name_set(&log_thread_data, "BT LOG");
  1141. #endif
  1142. #ifdef CONFIG_ACTS_HRTIMER
  1143. k_thread_create(&bt_monitor_thread_data, bt_monitor_thread_stack,
  1144. K_THREAD_STACK_SIZEOF(bt_monitor_thread_stack),
  1145. bt_monitor_thread, NULL, NULL, NULL,
  1146. CONFIG_BT_MONITOR_PRIO, 0, K_NO_WAIT);
  1147. k_thread_name_set(&bt_monitor_thread_data, "BT MONITOR");
  1148. hrtimer_init(&bt_monitor_hrtimer, bt_monitor_hrtimer_callback, NULL);
  1149. hrtimer_start(&bt_monitor_hrtimer, BT_MONTIR_HRTIMER_TIME, BT_MONTIR_HRTIMER_TIME);
  1150. #endif
  1151. atomic_set_bit(btc.flags, BT_CPU_ENABLE);
  1152. start_cpu:
  1153. if (atomic_test_bit(btc.flags, BT_CPU_READY)) {
  1154. return 0;
  1155. }
  1156. ret = ipmsg_load(btc.dev, (void *)BTC_BIN_ADDR, BTC_BIN_SIZE);
  1157. if (ret) {
  1158. LOG_ERR("load bt bin failed");
  1159. return -EINVAL;
  1160. }
  1161. /* Start BT CPU */
  1162. ret = ipmsg_start(btc.dev, NULL, NULL);
  1163. if (ret) {
  1164. LOG_ERR("start bt cpu failed");
  1165. return -EINVAL;
  1166. }
  1167. #ifdef CONFIG_BT_FCC_TEST
  1168. btdrv_run_fcc();
  1169. #endif
  1170. /* BT CPU will let us know when it's ready */
  1171. LOG_INF("wait bt cpu ready...");
  1172. k_sem_take(&btc.ready_sem, K_FOREVER);
  1173. LOG_INF("bt cpu ready");
  1174. return 0;
  1175. }
  1176. int btdrv_exit(void)
  1177. {
  1178. uint8_t irq;
  1179. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1180. return -ENODEV;
  1181. }
  1182. LOG_INF("exit");
  1183. if (hrtimer_is_running(&bt_monitor_hrtimer)) {
  1184. hrtimer_stop(&bt_monitor_hrtimer);
  1185. }
  1186. ipmsg_stop(btc.dev);
  1187. btc.hci_cb = NULL;
  1188. #ifdef CONFIG_ACTS_HRTIMER
  1189. monitor_exit = 1;
  1190. k_sem_give(&bt_monnitor_sem);
  1191. #endif
  1192. #ifdef CONFIG_BT_CTRL_LOG
  1193. log_exit = 1;
  1194. k_sem_give(&btc.log_rx_sem);
  1195. #endif
  1196. #if CONFIG_HCI_RX_THREAD
  1197. rx_exit = 1;
  1198. k_sem_give(&btc.hci_rx_sem);
  1199. #endif
  1200. #ifdef CONFIG_ACTS_HRTIMER
  1201. bt_runing_cnt = 0;
  1202. #endif
  1203. btc.hci_cb = NULL;
  1204. #ifdef CONFIG_BT_CTRL_TWS
  1205. btc.tws0_cb = NULL;
  1206. btc.tws1_cb = NULL;
  1207. #endif
  1208. irq = IPMSG_BTC_IRQ;
  1209. ipmsg_register_callback(btc.dev, NULL, &irq);
  1210. #ifdef CONFIG_BT_CTRL_TWS
  1211. irq = IPMSG_TWS0_IRQ;
  1212. ipmsg_register_callback(btc.dev, NULL, &irq);
  1213. irq = IPMSG_TWS1_IRQ;
  1214. ipmsg_register_callback(btc.dev, NULL, &irq);
  1215. #endif
  1216. #ifdef CONFIG_BT_CTRL_LOG
  1217. irq = IPMSG_REG_PW_CTRL;
  1218. ipmsg_register_callback(btc.dev, NULL, &irq);
  1219. #endif
  1220. #ifdef CONFIG_BT_ECC_ACTS
  1221. k_work_cancel_sync(&btc_ecc.work, NULL);
  1222. #endif
  1223. #ifdef CONFIG_BT_CTRL_REG
  1224. k_work_cancel_sync(&btc_reg.work, NULL);
  1225. #endif
  1226. // destroy default message queue
  1227. rbuf_msg_destroy(CPU, BT);
  1228. rbuf_msg_destroy(BT, CPU);
  1229. ipmsg_destroy(btc.hci_rx_id);
  1230. ipmsg_destroy(btc.hci_tx_id);
  1231. #ifdef CONFIG_BT_CTRL_LOG
  1232. ipmsg_destroy(btc.log_rx_id);
  1233. #endif
  1234. ipmsg_destroy(btc.bt_info_id);
  1235. #ifdef CONFIG_BT_CTRL_TWS
  1236. for (uint8_t i = 0; i < 2; i++) {
  1237. ipmsg_destroy(btc.tws_rx_id[i]);
  1238. ipmsg_destroy(btc.tws_tx_id[i]);
  1239. }
  1240. #endif
  1241. atomic_clear(btc.flags);
  1242. #ifdef CONFIG_BT_ECC_ACTS
  1243. atomic_clear(btc_ecc.flag);
  1244. #endif
  1245. return 0;
  1246. }
  1247. int btdrv_reset(void)
  1248. {
  1249. /* Reset BT CPU */
  1250. atomic_clear_bit(btc.flags, BT_CPU_READY);
  1251. ipmsg_stop(btc.dev);
  1252. ramdump_save(NULL, 1);
  1253. btdrv_exit();
  1254. //send_init_msg();
  1255. return btdrv_init(NULL);
  1256. }
  1257. void* btdrv_dump_btcpu_info(void)
  1258. {
  1259. int i;
  1260. unsigned int *pdata;
  1261. if (!btc.bt_info_id) {
  1262. return NULL;
  1263. }
  1264. pdata = (unsigned int*)RBUF_FR_OF((RBUF_FR_OF(btc.bt_info_id))->buf_off);
  1265. if (pdata) {
  1266. printk("Dump btcpu info\n");
  1267. for (i=0; i<(BT_INFO_SHARE_SIZE/4);) {
  1268. printk("%x: %08x %08x %08x %08x\n", (i*4), pdata[i], pdata[i + 1], pdata[i + 2], pdata[i + 3]);
  1269. i +=4;
  1270. }
  1271. }
  1272. return (void*)pdata;
  1273. }
  1274. #ifdef CONFIG_BT_CTRL_TWS
  1275. int btdrv_tws_irq_enable(uint8_t index)
  1276. {
  1277. if (index > BT_TWS_1) {
  1278. return -EINVAL;
  1279. }
  1280. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1281. return -ENOENT;
  1282. }
  1283. ipmsg_tws_irq_enable(btc.dev, index + 1);
  1284. return 0;
  1285. }
  1286. int btdrv_tws_irq_disable(uint8_t index)
  1287. {
  1288. if (index > BT_TWS_1) {
  1289. return -EINVAL;
  1290. }
  1291. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1292. return -ENOENT;
  1293. }
  1294. ipmsg_tws_irq_disable(btc.dev, index + 1);
  1295. return 0;
  1296. }
  1297. int btdrv_tws_irq_cb_set(uint8_t index, btdrv_tws_cb_t cb)
  1298. {
  1299. if (index > BT_TWS_1) {
  1300. return -EINVAL;
  1301. }
  1302. if (!atomic_test_bit(btc.flags, BT_CPU_ENABLE)) {
  1303. return -ENOENT;
  1304. }
  1305. if (index == BT_TWS_0) {
  1306. btc.tws0_cb = cb;
  1307. } else if (index == BT_TWS_1) {
  1308. btc.tws1_cb = cb;
  1309. }
  1310. return 0;
  1311. }
  1312. int btdrv_tws_set_mode(uint8_t index, uint8_t mode)
  1313. {
  1314. if (index > BT_TWS_1) {
  1315. return -EINVAL;
  1316. }
  1317. tws_tx[index]->mode = mode;
  1318. return 0;
  1319. }
  1320. int btdrv_tws_data_read(uint8_t index, uint8_t *buf)
  1321. {
  1322. #if CFG_USE_TWS_SHARERAM_PKT
  1323. if ((tws_rx[index]->wcnt - tws_rx[index]->rcnt) == 0) {
  1324. return -ENODATA;
  1325. }
  1326. memcpy(buf, tws_rx[index]->data, tws_rx[index]->data_len);
  1327. tws_rx[index]->rcnt++;
  1328. return tws_rx[index]->data_len;
  1329. #else
  1330. return 0;
  1331. #endif
  1332. }
  1333. int btdrv_tws_data_write(uint8_t index, uint8_t *data, uint16_t len)
  1334. {
  1335. #if CFG_USE_TWS_SHARERAM_PKT
  1336. if (!data || !len) {
  1337. return -EINVAL;
  1338. }
  1339. if ((tws_tx[index]->wcnt - tws_tx[index]->rcnt) >= 1) {
  1340. return -ENOBUFS;
  1341. }
  1342. memcpy(tws_tx[index]->data, data, len);
  1343. tws_tx[index]->wcnt++;
  1344. return len;
  1345. #else
  1346. return 0;
  1347. #endif
  1348. }
  1349. #endif
  1350. extern int bt_bqb_vs_write_bb_reg(uint32_t addr, uint32_t val);
  1351. extern int bt_bqb_vs_read_bb_reg(uint32_t addr, uint8_t size);
  1352. extern int bt_bqb_vs_write_rf_reg(uint16_t addr, uint16_t val);
  1353. extern int bt_bqb_vs_read_rf_reg(uint16_t addr, uint8_t size);
  1354. extern int bt_stack_vs_write_bb_reg(uint32_t addr, uint32_t val);
  1355. extern int bt_stack_vs_read_bb_reg(uint32_t addr, uint8_t size);
  1356. extern int bt_stack_vs_write_rf_reg(uint16_t addr, uint16_t val);
  1357. extern int bt_stack_vs_read_rf_reg(uint16_t addr, uint8_t size);
  1358. extern bool bt_bqb_is_in_test(void);
  1359. int bt_vs_write_bb_reg(uint32_t addr, uint32_t val)
  1360. {
  1361. #ifdef CONFIG_BT_CTRL_BQB
  1362. if (bt_bqb_is_in_test()) {
  1363. return bt_bqb_vs_write_bb_reg(addr, val);
  1364. }
  1365. #endif
  1366. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1367. return bt_stack_vs_write_bb_reg(addr, val);
  1368. #else
  1369. return 0;
  1370. #endif
  1371. }
  1372. int bt_vs_read_bb_reg(uint32_t addr, uint8_t size)
  1373. {
  1374. #ifdef CONFIG_BT_CTRL_BQB
  1375. if (bt_bqb_is_in_test()) {
  1376. return bt_bqb_vs_read_bb_reg(addr, size);
  1377. }
  1378. #endif
  1379. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1380. return bt_stack_vs_read_bb_reg(addr, size);
  1381. #else
  1382. return 0;
  1383. #endif
  1384. }
  1385. int bt_vs_write_rf_reg(uint16_t addr, uint16_t val)
  1386. {
  1387. #ifdef CONFIG_BT_CTRL_BQB
  1388. if (bt_bqb_is_in_test()) {
  1389. return bt_bqb_vs_write_rf_reg(addr, val);
  1390. }
  1391. #endif
  1392. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1393. return bt_stack_vs_write_rf_reg(addr, val);
  1394. #else
  1395. return 0;
  1396. #endif
  1397. }
  1398. int bt_vs_read_rf_reg(uint16_t addr, uint8_t size)
  1399. {
  1400. #ifdef CONFIG_BT_CTRL_BQB
  1401. if (bt_bqb_is_in_test()) {
  1402. return bt_bqb_vs_read_rf_reg(addr, size);
  1403. }
  1404. #endif
  1405. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1406. return bt_stack_vs_read_rf_reg(addr, size);
  1407. #else
  1408. return 0;
  1409. #endif
  1410. }
  1411. #ifdef CONFIG_ACTS_HRTIMER
  1412. /* Just need trigger hci read, read timeout will trigger restart. */
  1413. static void bt_monitor_check_runing(void)
  1414. {
  1415. #ifdef CONFIG_BT_CTRL_BQB
  1416. if (bt_bqb_is_in_test()) {
  1417. return;
  1418. }
  1419. #endif
  1420. #if defined(CONFIG_BT_HCI) || defined(CONFIG_BT_HCI_ACTS)
  1421. #define CHECK_READ_REG_ADDR 0xc0176100
  1422. bt_stack_vs_read_bb_reg(CHECK_READ_REG_ADDR, 1);
  1423. #endif
  1424. }
  1425. static void bt_monitor_thread(void *p1, void *p2, void *p3)
  1426. {
  1427. static uint32_t pre_bt_runing_cnt;
  1428. ARG_UNUSED(p1);
  1429. ARG_UNUSED(p2);
  1430. ARG_UNUSED(p3);
  1431. LOG_INF("bt monitor thread started");
  1432. while (1) {
  1433. k_sem_take(&bt_monnitor_sem, K_FOREVER);
  1434. if (monitor_exit) {
  1435. monitor_exit = 0;
  1436. k_thread_priority_set(k_current_get(), -1);
  1437. printk("monitor thread exit %d.\n",__LINE__);
  1438. return;
  1439. }
  1440. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  1441. continue;
  1442. }
  1443. if (pre_bt_runing_cnt != bt_runing_cnt) {
  1444. /* Bt core still runing, continue */
  1445. pre_bt_runing_cnt = bt_runing_cnt;
  1446. continue;
  1447. }
  1448. #ifdef CONFIG_SYS_WAKELOCK
  1449. sys_wake_lock_ext(PARTIAL_WAKE_LOCK, BT_WAKE_LOCK_USER);
  1450. #endif
  1451. bt_monitor_check_runing();
  1452. pre_bt_runing_cnt = bt_runing_cnt;
  1453. #ifdef CONFIG_SYS_WAKELOCK
  1454. sys_wake_unlock_ext(PARTIAL_WAKE_LOCK, BT_WAKE_LOCK_USER);
  1455. #endif
  1456. }
  1457. }
  1458. static void bt_monitor_hrtimer_callback(struct hrtimer *timer, void *expiry_fn_arg)
  1459. {
  1460. if (!atomic_test_bit(btc.flags, BT_CPU_READY)) {
  1461. return;
  1462. }
  1463. k_sem_give(&bt_monnitor_sem);
  1464. }
  1465. #endif