#ifndef _HV_PAGE_HT7315_COMBOTX_PHY_3_H_
#define _HV_PAGE_HT7315_COMBOTX_PHY_3_H_

#ifndef HV_COMBOTX_PHY_3_BASE_ADDRESS
    #define HV_COMBOTX_PHY_3_BASE_ADDRESS                                         0x1105F300
#endif


#define TX_COMBOTX_PHY_3_TX00_MUX_CTRL                                   (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0x60)

#define TX_COMBOTX_PHY_3_TX00_MUX_CTRL_struct                            rs_tx_combotx_phy_3_tx00_mux_ctrl

typedef struct _rs_tx_combotx_phy_3_tx00_mux_ctrl  rs_tx_combotx_phy_3_tx00_mux_ctrl;
struct _rs_tx_combotx_phy_3_tx00_mux_ctrl {
    unsigned int reg_txphy_00_0_mux_sel                     : 6;
    unsigned int reg_txphy_00_1_mux_sel                     : 6;
    unsigned int reg_txphy_00_2_mux_sel                     : 6;
    unsigned int reg_txphy_00_3_mux_sel                     : 6;
    unsigned int reg_txphy_00_pn_swap_lane0                 : 1;
    unsigned int reg_txphy_00_pn_swap_lane1                 : 1;
    unsigned int reg_txphy_00_pn_swap_lane2                 : 1;
    unsigned int reg_txphy_00_pn_swap_lane3                 : 1;
    unsigned int reserved                                   : 4;
};
#define tx_combotx_phy_3_tx00_mux_ctrl(val) ((rs_tx_combotx_phy_3_tx00_mux_ctrl*)&(val))



#define TX_COMBOTX_PHY_3_TX01_MUX_CTRL                                   (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0x64)

#define TX_COMBOTX_PHY_3_TX01_MUX_CTRL_struct                            rs_tx_combotx_phy_3_tx01_mux_ctrl

typedef struct _rs_tx_combotx_phy_3_tx01_mux_ctrl  rs_tx_combotx_phy_3_tx01_mux_ctrl;
struct _rs_tx_combotx_phy_3_tx01_mux_ctrl {
    unsigned int reg_txphy_01_0_mux_sel                     : 6;
    unsigned int reg_txphy_01_1_mux_sel                     : 6;
    unsigned int reg_txphy_01_2_mux_sel                     : 6;
    unsigned int reg_txphy_01_3_mux_sel                     : 6;
    unsigned int reg_txphy_01_pn_swap_lane0                 : 1;
    unsigned int reg_txphy_01_pn_swap_lane1                 : 1;
    unsigned int reg_txphy_01_pn_swap_lane2                 : 1;
    unsigned int reg_txphy_01_pn_swap_lane3                 : 1;
    unsigned int reserved                                   : 4;
};
#define tx_combotx_phy_3_tx01_mux_ctrl(val) ((rs_tx_combotx_phy_3_tx01_mux_ctrl*)&(val))



#define TX_COMBOTX_PHY_3_TX02_MUX_CTRL                                   (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0x68)

#define TX_COMBOTX_PHY_3_TX02_MUX_CTRL_struct                            rs_tx_combotx_phy_3_tx02_mux_ctrl

typedef struct _rs_tx_combotx_phy_3_tx02_mux_ctrl  rs_tx_combotx_phy_3_tx02_mux_ctrl;
struct _rs_tx_combotx_phy_3_tx02_mux_ctrl {
    unsigned int reg_txphy_02_0_mux_sel                     : 6;
    unsigned int reg_txphy_02_1_mux_sel                     : 6;
    unsigned int reg_txphy_02_2_mux_sel                     : 6;
    unsigned int reg_txphy_02_3_mux_sel                     : 6;
    unsigned int reg_txphy_02_pn_swap_lane0                 : 1;
    unsigned int reg_txphy_02_pn_swap_lane1                 : 1;
    unsigned int reg_txphy_02_pn_swap_lane2                 : 1;
    unsigned int reg_txphy_02_pn_swap_lane3                 : 1;
    unsigned int reserved                                   : 4;
};
#define tx_combotx_phy_3_tx02_mux_ctrl(val) ((rs_tx_combotx_phy_3_tx02_mux_ctrl*)&(val))



#define TX_COMBOTX_PHY_3_TX00_TX01_OFFSET_CTRL                           (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0x90)

#define TX_COMBOTX_PHY_3_TX00_TX01_OFFSET_CTRL_struct                    rs_tx_combotx_phy_3_tx00_tx01_offset_ctrl

typedef struct _rs_tx_combotx_phy_3_tx00_tx01_offset_ctrl  rs_tx_combotx_phy_3_tx00_tx01_offset_ctrl;
struct _rs_tx_combotx_phy_3_tx00_tx01_offset_ctrl {
    unsigned int reg_txphy_00_delay_offset_lane0            : 4;
    unsigned int reg_txphy_00_delay_offset_lane1            : 4;
    unsigned int reg_txphy_00_delay_offset_lane2            : 4;
    unsigned int reg_txphy_00_delay_offset_lane3            : 4;
    unsigned int reg_txphy_01_delay_offset_lane0            : 4;
    unsigned int reg_txphy_01_delay_offset_lane1            : 4;
    unsigned int reg_txphy_01_delay_offset_lane2            : 4;
    unsigned int reg_txphy_01_delay_offset_lane3            : 4;
};
#define tx_combotx_phy_3_tx00_tx01_offset_ctrl(val) ((rs_tx_combotx_phy_3_tx00_tx01_offset_ctrl*)&(val))



#define TX_COMBOTX_PHY_3_TX02_TX03_OFFSET_CTRL                           (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0x94)

#define TX_COMBOTX_PHY_3_TX02_TX03_OFFSET_CTRL_struct                    rs_tx_combotx_phy_3_tx02_tx03_offset_ctrl

typedef struct _rs_tx_combotx_phy_3_tx02_tx03_offset_ctrl  rs_tx_combotx_phy_3_tx02_tx03_offset_ctrl;
struct _rs_tx_combotx_phy_3_tx02_tx03_offset_ctrl {
    unsigned int reg_txphy_02_delay_offset_lane0            : 4;
    unsigned int reg_txphy_02_delay_offset_lane1            : 4;
    unsigned int reg_txphy_02_delay_offset_lane2            : 4;
    unsigned int reg_txphy_02_delay_offset_lane3            : 4;
    unsigned int reserved                                   :16;
};
#define tx_combotx_phy_3_tx02_tx03_offset_ctrl(val) ((rs_tx_combotx_phy_3_tx02_tx03_offset_ctrl*)&(val))



#define TX_COMBOTX_PHY_3_TX01_EXT                                        (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0xA0)

#define TX_COMBOTX_PHY_3_TX01_EXT_struct                                 rs_tx_combotx_phy_3_tx01_ext

typedef struct _rs_tx_combotx_phy_3_tx01_ext  rs_tx_combotx_phy_3_tx01_ext;
struct _rs_tx_combotx_phy_3_tx01_ext {
    unsigned int reg_txphy_00_ext_en_lane0                  : 1;
    unsigned int reg_txphy_00_ext_en_lane1                  : 1;
    unsigned int reg_txphy_00_ext_en_lane2                  : 1;
    unsigned int reg_txphy_00_ext_en_lane3                  : 1;
    unsigned int reg_txphy_01_ext_en_lane0                  : 1;
    unsigned int reg_txphy_01_ext_en_lane1                  : 1;
    unsigned int reg_txphy_01_ext_en_lane2                  : 1;
    unsigned int reg_txphy_01_ext_en_lane3                  : 1;
    unsigned int reg_txphy_02_ext_en_lane0                  : 1;
    unsigned int reg_txphy_02_ext_en_lane1                  : 1;
    unsigned int reg_txphy_02_ext_en_lane2                  : 1;
    unsigned int reg_txphy_02_ext_en_lane3                  : 1;
    unsigned int reserved                                   :20;
};
#define tx_combotx_phy_3_tx01_ext(val) ((rs_tx_combotx_phy_3_tx01_ext*)&(val))



#define TX_COMBOTX_PHY_3_TX_CTRL                                         (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0xA4)

#define TX_COMBOTX_PHY_3_TX_CTRL_struct                                  rs_tx_combotx_phy_3_tx_ctrl

typedef struct _rs_tx_combotx_phy_3_tx_ctrl  rs_tx_combotx_phy_3_tx_ctrl;
struct _rs_tx_combotx_phy_3_tx_ctrl {
    unsigned int reg_txgrp_00_pif_conv_mode                 : 5;
    unsigned int reg_txgrp_00_pif_tx_w2r_dly                : 5;
    unsigned int reg_txgrp_00_pif_tx_start                  : 1;
    unsigned int reserved                                   :21;
};
#define tx_combotx_phy_3_tx_ctrl(val) ((rs_tx_combotx_phy_3_tx_ctrl*)&(val))



#define TX_COMBOTX_PHY_3_B0                                              (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0xB0)

#define TX_COMBOTX_PHY_3_B0_struct                                       rs_tx_combotx_phy_3_b0

typedef struct _rs_tx_combotx_phy_3_b0  rs_tx_combotx_phy_3_b0;
struct _rs_tx_combotx_phy_3_b0 {
    unsigned int reg_txphy_pulldown_from_mac_en             : 1;
    unsigned int reg_txphy_pullow_sel                       : 2;
    unsigned int reserved                                   :28;
    unsigned int reg_tx_afifo_readback_clear                : 1;
};
#define tx_combotx_phy_3_b0(val) ((rs_tx_combotx_phy_3_b0*)&(val))



#define TX_COMBOTX_PHY_3_B4                                              (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0xB4)

#define TX_COMBOTX_PHY_3_B4_struct                                       rs_tx_combotx_phy_3_b4

typedef struct _rs_tx_combotx_phy_3_b4  rs_tx_combotx_phy_3_b4;
struct _rs_tx_combotx_phy_3_b4 {
    unsigned int reg_txphy_ext_afifo_wen                    : 1;
    unsigned int reg_txphy_ext_afifo_ren                    : 1;
    unsigned int reg_txphy_ext_afifo_wclr                   : 1;
    unsigned int reg_txphy_ext_afifo_rclr                   : 1;
    unsigned int reserved                                   :28;
};
#define tx_combotx_phy_3_b4(val) ((rs_tx_combotx_phy_3_b4*)&(val))



#define TX_COMBOTX_PHY_3_F0                                              (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0xF0)

#define TX_COMBOTX_PHY_3_F0_struct                                       rs_tx_combotx_phy_3_f0

typedef struct _rs_tx_combotx_phy_3_f0  rs_tx_combotx_phy_3_f0;
struct _rs_tx_combotx_phy_3_f0 {
    unsigned int regr_txphy_ext_afifo_full                  : 4;
    unsigned int regr_txphy_ext_afifo_empty                 : 4;
    unsigned int reserved                                   :24;
};
#define tx_combotx_phy_3_f0(val) ((rs_tx_combotx_phy_3_f0*)&(val))



#define TX_COMBOTX_PHY_3_TX_AFIFO_RO_0                                   (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0xF4)

#define TX_COMBOTX_PHY_3_TX_AFIFO_RO_0_struct                            rs_tx_combotx_phy_3_tx_afifo_ro_0

typedef struct _rs_tx_combotx_phy_3_tx_afifo_ro_0  rs_tx_combotx_phy_3_tx_afifo_ro_0;
struct _rs_tx_combotx_phy_3_tx_afifo_ro_0 {
    unsigned int regr_txphy_00_afifo_overflow               : 4;
    unsigned int regr_txphy_01_afifo_overflow               : 4;
    unsigned int regr_txphy_02_afifo_overflow               : 4;
    unsigned int reserved                                   :20;
};
#define tx_combotx_phy_3_tx_afifo_ro_0(val) ((rs_tx_combotx_phy_3_tx_afifo_ro_0*)&(val))



#define TX_COMBOTX_PHY_3_TX_AFIFO_RO_1                                   (HV_COMBOTX_PHY_3_BASE_ADDRESS + 0xF8)

#define TX_COMBOTX_PHY_3_TX_AFIFO_RO_1_struct                            rs_tx_combotx_phy_3_tx_afifo_ro_1

typedef struct _rs_tx_combotx_phy_3_tx_afifo_ro_1  rs_tx_combotx_phy_3_tx_afifo_ro_1;
struct _rs_tx_combotx_phy_3_tx_afifo_ro_1 {
    unsigned int regr_txphy_00_afifo_underflow              : 4;
    unsigned int regr_txphy_01_afifo_underflow              : 4;
    unsigned int regr_txphy_02_afifo_underflow              : 4;
    unsigned int reserved                                   :20;
};
#define tx_combotx_phy_3_tx_afifo_ro_1(val) ((rs_tx_combotx_phy_3_tx_afifo_ro_1*)&(val))



#endif