#ifndef _HV_PAGE_HT7315_HDMI_RX_HDCP2X_01_00_H_
#define _HV_PAGE_HT7315_HDMI_RX_HDCP2X_01_00_H_

#ifndef HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS
    #define HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS                                         0x1104D800
#endif


#define RX_HDMI_RX_HDCP2X_01_00_00                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x00)

#define RX_HDMI_RX_HDCP2X_01_00_00_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_00

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_00  rs_rx_hdmi_rx_hdcp2x_01_00_00;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_00 {
    unsigned int reg_00_hdmirx_hdcp2x_message256            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message257            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message258            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message259            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_00(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_00*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_04                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x04)

#define RX_HDMI_RX_HDCP2X_01_00_04_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_04

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_04  rs_rx_hdmi_rx_hdcp2x_01_00_04;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_04 {
    unsigned int reg_00_hdmirx_hdcp2x_message260            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message261            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message262            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message263            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_04(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_04*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_08                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x08)

#define RX_HDMI_RX_HDCP2X_01_00_08_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_08

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_08  rs_rx_hdmi_rx_hdcp2x_01_00_08;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_08 {
    unsigned int reg_00_hdmirx_hdcp2x_message264            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message265            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message266            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message267            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_08(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_08*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_0C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x0C)

#define RX_HDMI_RX_HDCP2X_01_00_0C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_0c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_0c  rs_rx_hdmi_rx_hdcp2x_01_00_0c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_0c {
    unsigned int reg_00_hdmirx_hdcp2x_message268            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message269            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message270            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message271            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_0c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_0c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_10                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x10)

#define RX_HDMI_RX_HDCP2X_01_00_10_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_10

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_10  rs_rx_hdmi_rx_hdcp2x_01_00_10;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_10 {
    unsigned int reg_00_hdmirx_hdcp2x_message272            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message273            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message274            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message275            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_10(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_10*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_14                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x14)

#define RX_HDMI_RX_HDCP2X_01_00_14_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_14

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_14  rs_rx_hdmi_rx_hdcp2x_01_00_14;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_14 {
    unsigned int reg_00_hdmirx_hdcp2x_message276            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message277            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message278            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message279            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_14(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_14*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_18                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x18)

#define RX_HDMI_RX_HDCP2X_01_00_18_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_18

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_18  rs_rx_hdmi_rx_hdcp2x_01_00_18;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_18 {
    unsigned int reg_00_hdmirx_hdcp2x_message280            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message281            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message282            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message283            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_18(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_18*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_1C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x1C)

#define RX_HDMI_RX_HDCP2X_01_00_1C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_1c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_1c  rs_rx_hdmi_rx_hdcp2x_01_00_1c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_1c {
    unsigned int reg_00_hdmirx_hdcp2x_message284            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message285            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message286            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message287            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_1c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_1c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_20                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x20)

#define RX_HDMI_RX_HDCP2X_01_00_20_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_20

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_20  rs_rx_hdmi_rx_hdcp2x_01_00_20;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_20 {
    unsigned int reg_00_hdmirx_hdcp2x_message288            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message289            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message290            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message291            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_20(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_20*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_24                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x24)

#define RX_HDMI_RX_HDCP2X_01_00_24_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_24

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_24  rs_rx_hdmi_rx_hdcp2x_01_00_24;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_24 {
    unsigned int reg_00_hdmirx_hdcp2x_message292            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message293            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message294            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message295            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_24(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_24*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_28                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x28)

#define RX_HDMI_RX_HDCP2X_01_00_28_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_28

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_28  rs_rx_hdmi_rx_hdcp2x_01_00_28;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_28 {
    unsigned int reg_00_hdmirx_hdcp2x_message296            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message297            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message298            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message299            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_28(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_28*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_2C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x2C)

#define RX_HDMI_RX_HDCP2X_01_00_2C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_2c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_2c  rs_rx_hdmi_rx_hdcp2x_01_00_2c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_2c {
    unsigned int reg_00_hdmirx_hdcp2x_message300            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message301            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message302            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message303            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_2c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_2c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_30                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x30)

#define RX_HDMI_RX_HDCP2X_01_00_30_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_30

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_30  rs_rx_hdmi_rx_hdcp2x_01_00_30;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_30 {
    unsigned int reg_00_hdmirx_hdcp2x_message304            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message305            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message306            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message307            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_30(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_30*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_34                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x34)

#define RX_HDMI_RX_HDCP2X_01_00_34_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_34

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_34  rs_rx_hdmi_rx_hdcp2x_01_00_34;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_34 {
    unsigned int reg_00_hdmirx_hdcp2x_message308            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message309            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message310            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message311            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_34(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_34*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_38                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x38)

#define RX_HDMI_RX_HDCP2X_01_00_38_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_38

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_38  rs_rx_hdmi_rx_hdcp2x_01_00_38;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_38 {
    unsigned int reg_00_hdmirx_hdcp2x_message312            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message313            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message314            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message315            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_38(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_38*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_3C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x3C)

#define RX_HDMI_RX_HDCP2X_01_00_3C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_3c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_3c  rs_rx_hdmi_rx_hdcp2x_01_00_3c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_3c {
    unsigned int reg_00_hdmirx_hdcp2x_message316            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message317            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message318            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message319            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_3c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_3c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_40                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x40)

#define RX_HDMI_RX_HDCP2X_01_00_40_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_40

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_40  rs_rx_hdmi_rx_hdcp2x_01_00_40;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_40 {
    unsigned int reg_00_hdmirx_hdcp2x_message320            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message321            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message322            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message323            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_40(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_40*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_44                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x44)

#define RX_HDMI_RX_HDCP2X_01_00_44_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_44

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_44  rs_rx_hdmi_rx_hdcp2x_01_00_44;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_44 {
    unsigned int reg_00_hdmirx_hdcp2x_message324            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message325            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message326            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message327            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_44(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_44*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_48                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x48)

#define RX_HDMI_RX_HDCP2X_01_00_48_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_48

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_48  rs_rx_hdmi_rx_hdcp2x_01_00_48;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_48 {
    unsigned int reg_00_hdmirx_hdcp2x_message328            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message329            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message330            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message331            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_48(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_48*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_4C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x4C)

#define RX_HDMI_RX_HDCP2X_01_00_4C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_4c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_4c  rs_rx_hdmi_rx_hdcp2x_01_00_4c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_4c {
    unsigned int reg_00_hdmirx_hdcp2x_message332            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message333            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message334            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message335            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_4c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_4c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_50                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x50)

#define RX_HDMI_RX_HDCP2X_01_00_50_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_50

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_50  rs_rx_hdmi_rx_hdcp2x_01_00_50;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_50 {
    unsigned int reg_00_hdmirx_hdcp2x_message336            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message337            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message338            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message339            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_50(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_50*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_54                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x54)

#define RX_HDMI_RX_HDCP2X_01_00_54_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_54

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_54  rs_rx_hdmi_rx_hdcp2x_01_00_54;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_54 {
    unsigned int reg_00_hdmirx_hdcp2x_message340            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message341            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message342            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message343            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_54(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_54*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_58                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x58)

#define RX_HDMI_RX_HDCP2X_01_00_58_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_58

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_58  rs_rx_hdmi_rx_hdcp2x_01_00_58;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_58 {
    unsigned int reg_00_hdmirx_hdcp2x_message344            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message345            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message346            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message347            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_58(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_58*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_5C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x5C)

#define RX_HDMI_RX_HDCP2X_01_00_5C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_5c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_5c  rs_rx_hdmi_rx_hdcp2x_01_00_5c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_5c {
    unsigned int reg_00_hdmirx_hdcp2x_message348            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message349            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message350            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message351            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_5c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_5c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_60                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x60)

#define RX_HDMI_RX_HDCP2X_01_00_60_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_60

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_60  rs_rx_hdmi_rx_hdcp2x_01_00_60;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_60 {
    unsigned int reg_00_hdmirx_hdcp2x_message352            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message353            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message354            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message355            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_60(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_60*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_64                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x64)

#define RX_HDMI_RX_HDCP2X_01_00_64_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_64

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_64  rs_rx_hdmi_rx_hdcp2x_01_00_64;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_64 {
    unsigned int reg_00_hdmirx_hdcp2x_message356            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message357            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message358            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message359            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_64(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_64*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_68                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x68)

#define RX_HDMI_RX_HDCP2X_01_00_68_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_68

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_68  rs_rx_hdmi_rx_hdcp2x_01_00_68;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_68 {
    unsigned int reg_00_hdmirx_hdcp2x_message360            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message361            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message362            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message363            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_68(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_68*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_6C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x6C)

#define RX_HDMI_RX_HDCP2X_01_00_6C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_6c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_6c  rs_rx_hdmi_rx_hdcp2x_01_00_6c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_6c {
    unsigned int reg_00_hdmirx_hdcp2x_message364            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message365            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message366            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message367            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_6c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_6c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_70                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x70)

#define RX_HDMI_RX_HDCP2X_01_00_70_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_70

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_70  rs_rx_hdmi_rx_hdcp2x_01_00_70;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_70 {
    unsigned int reg_00_hdmirx_hdcp2x_message368            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message369            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message370            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message371            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_70(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_70*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_74                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x74)

#define RX_HDMI_RX_HDCP2X_01_00_74_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_74

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_74  rs_rx_hdmi_rx_hdcp2x_01_00_74;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_74 {
    unsigned int reg_00_hdmirx_hdcp2x_message372            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message373            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message374            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message375            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_74(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_74*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_78                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x78)

#define RX_HDMI_RX_HDCP2X_01_00_78_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_78

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_78  rs_rx_hdmi_rx_hdcp2x_01_00_78;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_78 {
    unsigned int reg_00_hdmirx_hdcp2x_message376            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message377            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message378            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message379            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_78(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_78*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_7C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x7C)

#define RX_HDMI_RX_HDCP2X_01_00_7C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_7c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_7c  rs_rx_hdmi_rx_hdcp2x_01_00_7c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_7c {
    unsigned int reg_00_hdmirx_hdcp2x_message380            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message381            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message382            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message383            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_7c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_7c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_80                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x80)

#define RX_HDMI_RX_HDCP2X_01_00_80_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_80

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_80  rs_rx_hdmi_rx_hdcp2x_01_00_80;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_80 {
    unsigned int reg_00_hdmirx_hdcp2x_message384            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message385            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message386            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message387            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_80(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_80*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_84                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x84)

#define RX_HDMI_RX_HDCP2X_01_00_84_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_84

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_84  rs_rx_hdmi_rx_hdcp2x_01_00_84;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_84 {
    unsigned int reg_00_hdmirx_hdcp2x_message388            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message389            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message390            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message391            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_84(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_84*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_88                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x88)

#define RX_HDMI_RX_HDCP2X_01_00_88_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_88

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_88  rs_rx_hdmi_rx_hdcp2x_01_00_88;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_88 {
    unsigned int reg_00_hdmirx_hdcp2x_message392            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message393            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message394            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message395            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_88(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_88*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_8C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x8C)

#define RX_HDMI_RX_HDCP2X_01_00_8C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_8c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_8c  rs_rx_hdmi_rx_hdcp2x_01_00_8c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_8c {
    unsigned int reg_00_hdmirx_hdcp2x_message396            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message397            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message398            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message399            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_8c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_8c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_90                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x90)

#define RX_HDMI_RX_HDCP2X_01_00_90_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_90

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_90  rs_rx_hdmi_rx_hdcp2x_01_00_90;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_90 {
    unsigned int reg_00_hdmirx_hdcp2x_message400            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message401            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message402            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message403            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_90(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_90*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_94                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x94)

#define RX_HDMI_RX_HDCP2X_01_00_94_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_94

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_94  rs_rx_hdmi_rx_hdcp2x_01_00_94;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_94 {
    unsigned int reg_00_hdmirx_hdcp2x_message404            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message405            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message406            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message407            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_94(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_94*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_98                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x98)

#define RX_HDMI_RX_HDCP2X_01_00_98_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_98

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_98  rs_rx_hdmi_rx_hdcp2x_01_00_98;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_98 {
    unsigned int reg_00_hdmirx_hdcp2x_message408            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message409            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message410            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message411            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_98(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_98*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_9C                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0x9C)

#define RX_HDMI_RX_HDCP2X_01_00_9C_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_9c

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_9c  rs_rx_hdmi_rx_hdcp2x_01_00_9c;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_9c {
    unsigned int reg_00_hdmirx_hdcp2x_message412            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message413            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message414            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message415            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_9c(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_9c*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_A0                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xA0)

#define RX_HDMI_RX_HDCP2X_01_00_A0_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_a0

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_a0  rs_rx_hdmi_rx_hdcp2x_01_00_a0;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_a0 {
    unsigned int reg_00_hdmirx_hdcp2x_message416            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message417            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message418            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message419            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_a0(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_a0*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_A4                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xA4)

#define RX_HDMI_RX_HDCP2X_01_00_A4_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_a4

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_a4  rs_rx_hdmi_rx_hdcp2x_01_00_a4;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_a4 {
    unsigned int reg_00_hdmirx_hdcp2x_message420            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message421            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message422            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message423            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_a4(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_a4*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_A8                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xA8)

#define RX_HDMI_RX_HDCP2X_01_00_A8_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_a8

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_a8  rs_rx_hdmi_rx_hdcp2x_01_00_a8;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_a8 {
    unsigned int reg_00_hdmirx_hdcp2x_message424            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message425            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message426            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message427            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_a8(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_a8*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_AC                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xAC)

#define RX_HDMI_RX_HDCP2X_01_00_AC_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_ac

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_ac  rs_rx_hdmi_rx_hdcp2x_01_00_ac;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_ac {
    unsigned int reg_00_hdmirx_hdcp2x_message428            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message429            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message430            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message431            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_ac(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_ac*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_B0                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xB0)

#define RX_HDMI_RX_HDCP2X_01_00_B0_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_b0

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_b0  rs_rx_hdmi_rx_hdcp2x_01_00_b0;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_b0 {
    unsigned int reg_00_hdmirx_hdcp2x_message432            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message433            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message434            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message435            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_b0(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_b0*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_B4                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xB4)

#define RX_HDMI_RX_HDCP2X_01_00_B4_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_b4

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_b4  rs_rx_hdmi_rx_hdcp2x_01_00_b4;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_b4 {
    unsigned int reg_00_hdmirx_hdcp2x_message436            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message437            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message438            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message439            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_b4(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_b4*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_B8                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xB8)

#define RX_HDMI_RX_HDCP2X_01_00_B8_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_b8

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_b8  rs_rx_hdmi_rx_hdcp2x_01_00_b8;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_b8 {
    unsigned int reg_00_hdmirx_hdcp2x_message440            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message441            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message442            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message443            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_b8(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_b8*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_BC                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xBC)

#define RX_HDMI_RX_HDCP2X_01_00_BC_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_bc

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_bc  rs_rx_hdmi_rx_hdcp2x_01_00_bc;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_bc {
    unsigned int reg_00_hdmirx_hdcp2x_message444            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message445            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message446            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message447            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_bc(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_bc*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_C0                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xC0)

#define RX_HDMI_RX_HDCP2X_01_00_C0_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_c0

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_c0  rs_rx_hdmi_rx_hdcp2x_01_00_c0;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_c0 {
    unsigned int reg_00_hdmirx_hdcp2x_message448            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message449            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message450            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message451            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_c0(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_c0*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_C4                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xC4)

#define RX_HDMI_RX_HDCP2X_01_00_C4_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_c4

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_c4  rs_rx_hdmi_rx_hdcp2x_01_00_c4;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_c4 {
    unsigned int reg_00_hdmirx_hdcp2x_message452            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message453            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message454            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message455            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_c4(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_c4*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_C8                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xC8)

#define RX_HDMI_RX_HDCP2X_01_00_C8_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_c8

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_c8  rs_rx_hdmi_rx_hdcp2x_01_00_c8;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_c8 {
    unsigned int reg_00_hdmirx_hdcp2x_message456            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message457            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message458            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message459            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_c8(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_c8*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_CC                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xCC)

#define RX_HDMI_RX_HDCP2X_01_00_CC_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_cc

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_cc  rs_rx_hdmi_rx_hdcp2x_01_00_cc;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_cc {
    unsigned int reg_00_hdmirx_hdcp2x_message460            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message461            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message462            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message463            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_cc(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_cc*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_D0                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xD0)

#define RX_HDMI_RX_HDCP2X_01_00_D0_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_d0

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_d0  rs_rx_hdmi_rx_hdcp2x_01_00_d0;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_d0 {
    unsigned int reg_00_hdmirx_hdcp2x_message464            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message465            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message466            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message467            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_d0(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_d0*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_D4                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xD4)

#define RX_HDMI_RX_HDCP2X_01_00_D4_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_d4

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_d4  rs_rx_hdmi_rx_hdcp2x_01_00_d4;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_d4 {
    unsigned int reg_00_hdmirx_hdcp2x_message468            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message469            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message470            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message471            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_d4(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_d4*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_D8                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xD8)

#define RX_HDMI_RX_HDCP2X_01_00_D8_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_d8

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_d8  rs_rx_hdmi_rx_hdcp2x_01_00_d8;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_d8 {
    unsigned int reg_00_hdmirx_hdcp2x_message472            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message473            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message474            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message475            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_d8(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_d8*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_DC                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xDC)

#define RX_HDMI_RX_HDCP2X_01_00_DC_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_dc

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_dc  rs_rx_hdmi_rx_hdcp2x_01_00_dc;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_dc {
    unsigned int reg_00_hdmirx_hdcp2x_message476            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message477            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message478            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message479            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_dc(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_dc*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_E0                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xE0)

#define RX_HDMI_RX_HDCP2X_01_00_E0_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_e0

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_e0  rs_rx_hdmi_rx_hdcp2x_01_00_e0;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_e0 {
    unsigned int reg_00_hdmirx_hdcp2x_message480            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message481            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message482            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message483            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_e0(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_e0*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_E4                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xE4)

#define RX_HDMI_RX_HDCP2X_01_00_E4_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_e4

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_e4  rs_rx_hdmi_rx_hdcp2x_01_00_e4;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_e4 {
    unsigned int reg_00_hdmirx_hdcp2x_message484            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message485            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message486            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message487            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_e4(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_e4*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_E8                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xE8)

#define RX_HDMI_RX_HDCP2X_01_00_E8_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_e8

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_e8  rs_rx_hdmi_rx_hdcp2x_01_00_e8;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_e8 {
    unsigned int reg_00_hdmirx_hdcp2x_message488            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message489            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message490            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message491            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_e8(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_e8*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_EC                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xEC)

#define RX_HDMI_RX_HDCP2X_01_00_EC_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_ec

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_ec  rs_rx_hdmi_rx_hdcp2x_01_00_ec;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_ec {
    unsigned int reg_00_hdmirx_hdcp2x_message492            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message493            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message494            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message495            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_ec(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_ec*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_F0                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xF0)

#define RX_HDMI_RX_HDCP2X_01_00_F0_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_f0

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_f0  rs_rx_hdmi_rx_hdcp2x_01_00_f0;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_f0 {
    unsigned int reg_00_hdmirx_hdcp2x_message496            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message497            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message498            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message499            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_f0(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_f0*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_F4                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xF4)

#define RX_HDMI_RX_HDCP2X_01_00_F4_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_f4

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_f4  rs_rx_hdmi_rx_hdcp2x_01_00_f4;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_f4 {
    unsigned int reg_00_hdmirx_hdcp2x_message500            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message501            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message502            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message503            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_f4(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_f4*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_F8                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xF8)

#define RX_HDMI_RX_HDCP2X_01_00_F8_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_f8

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_f8  rs_rx_hdmi_rx_hdcp2x_01_00_f8;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_f8 {
    unsigned int reg_00_hdmirx_hdcp2x_message504            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message505            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message506            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message507            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_f8(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_f8*)&(val))



#define RX_HDMI_RX_HDCP2X_01_00_FC                                       (HV_HDMI_RX_HDCP2X_01_00_BASE_ADDRESS + 0xFC)

#define RX_HDMI_RX_HDCP2X_01_00_FC_struct                                rs_rx_hdmi_rx_hdcp2x_01_00_fc

typedef struct _rs_rx_hdmi_rx_hdcp2x_01_00_fc  rs_rx_hdmi_rx_hdcp2x_01_00_fc;
struct _rs_rx_hdmi_rx_hdcp2x_01_00_fc {
    unsigned int reg_00_hdmirx_hdcp2x_message508            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message509            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message510            : 8;
    unsigned int reg_00_hdmirx_hdcp2x_message511            : 8;
};
#define rx_hdmi_rx_hdcp2x_01_00_fc(val) ((rs_rx_hdmi_rx_hdcp2x_01_00_fc*)&(val))



#endif