/**
 * @file hv_cal_DpuSubScaler.h.c
 * @brief DpuScaler CAL module driver
 * @details This module provide interfaces for DRV level.
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20220903
 * @copyright Copyright(c),2022-9, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date             <th>Details
 * <tr><td>HiView SoC Software Team       <td>20220903         <td>Create and first Version.
 * </table>
 **/


#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Log.h"
#include "hv_comm_Assert.h"
#include "hv_cal_DpuSubScaler.h"
#include "hv_cal_PLL.h"
#include "PanelConfig.h"
#include "hv_chip_Clk.h"
#include "hv_comm_DataBase.h"

extern VOID Hv_Cal_DpuScaler_SubChannelInit(VOID);
VOID Hv_Cal_DpuScaler_SubInit(VOID)
{
    Hv_Cal_DpuScaler_SubChannelInit();
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_00, reg_01_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_68, reg_01_tbl_id_gmi, 4);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_68, reg_01_tbl_id_ootf, 5);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_68, reg_01_tbl_id_gmd, 6);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_01_6C, reg_01_dm_tbl_byte_len4, 0x4800);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_01_74, reg_01_dm_tbl_byte_len5, 0x800);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_01_7C, reg_01_dm_tbl_byte_len6, 0x6180);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_01_C8, reg_01_dm_tbl_burst_len, 0x1f);
    return;
}

#ifdef HV_SCALER_DEBUG_VERSION
VOID Hv_Cal_DpuScaler_CapVgsfPattSettingsSub(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_14, reg_01_ca_in_pat_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_1C, reg_01_ca_in_pat_vtotal, pstVideoConfigParams->uiInputVideoVtotal);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_14, reg_01_ca_in_pat_hact, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_1C, reg_01_ca_in_pat_vact, pstVideoConfigParams->uiInputVideoHight);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_18, reg_01_ca_in_pat_hwdth, 1);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_20, reg_01_ca_in_pat_vwdth, 1);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_18, reg_01_ca_in_pat_hbp, 10);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_20, reg_01_ca_in_pat_vbp, 10);
    return;
}
#endif

/***********Dpu cap vgsf settings begin*********************/

USHORT16 Hv_Cal_DpuScaler_GetSubCuVsize(VOID)
{
    HV_R32_DECL_VAR();
    USHORT16 usSubCutVstart = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_01_8C, reg_01_ca_out_cut_vstart);
    USHORT16 usSubCutVend = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_01_8C, reg_01_ca_out_cut_vend);
    if (usSubCutVend > usSubCutVstart)
    {
        return usSubCutVend - usSubCutVstart;
    }
    else
    {
        return 0;
    }
}

VOID Hv_Cal_DpuScaler_SetCapVgsfSubCutParam(DpuCapCutParam* pstDpuCapCutParam)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_88, reg_01_ca_out_cut_hstart, pstDpuCapCutParam->usCutHstart);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_88, reg_01_ca_out_cut_hend, pstDpuCapCutParam->usCutHend);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_8C, reg_01_ca_out_cut_vstart, pstDpuCapCutParam->usCutVstart);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_8C, reg_01_ca_out_cut_vend, pstDpuCapCutParam->usCutVend);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubInOutSize(const VideoConfigParams* pstVideoConfigParams)
{
    HV_W32_FIELD(DISP_TOP_C420_422_01_08, reg_01_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_C420_422_01_0C, reg_01_hact, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(DISP_TOP_C420_422_01_0C, reg_01_vact, pstVideoConfigParams->uiInputVideoHight);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_28, reg_01_hdr_act_hsize, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_28, reg_01_hdr_act_vsize, pstVideoConfigParams->uiInputVideoHight);
    HV_W32_FIELD(DISP_TOP_C422_420_01_08, reg_01_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_C422_420_01_0C, reg_01_hact, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_C422_420_01_0C, reg_01_vact, pstVideoConfigParams->uiDdrOrWtrVideoHight);

    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_04, reg_01_ca_in_hsize, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_04, reg_01_ca_in_vsize, pstVideoConfigParams ->uiInputVideoHight);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_90, reg_01_ca_out_hsize, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_90, reg_01_ca_out_vsize, pstVideoConfigParams->uiDdrOrWtrVideoHight);
    HV_W32_FIELD(DISP_TOP_DPU_CA_SYNC_01_04, reg_01_ca_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_DPU_CA_SYNC_01_04, reg_01_ca_vact, pstVideoConfigParams->uiInputVideoHight);
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_04, reg_01_sc_hszin, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_08, reg_01_sc_vszin, pstVideoConfigParams->uiDdrOrWtrVideoHight);
    if (pstVideoConfigParams->bMainFakeSwitch)
    {
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_10, reg_01_sc_hszout, pstVideoConfigParams->usMainFakeHsize);
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_14 , reg_01_sc_vszout, pstVideoConfigParams->usMainFakeVsize);
        //Must config Matrix H,V size in Sub
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_B8, reg_mtx_hsize, pstVideoConfigParams->usMainFakeHsize);
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_B8, reg_mtx_vsize, pstVideoConfigParams->usMainFakeVsize);
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_58, reg_sr_hcb_hsize, pstVideoConfigParams->usMainFakeHsize);
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_58, reg_sr_hcb_vsize, pstVideoConfigParams->usMainFakeVsize);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_10, reg_01_sc_hszout, pstVideoConfigParams->uiOutputVideoWidth);
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_14 , reg_01_sc_vszout, pstVideoConfigParams->uiOutputVideoHight);
        //Must config Matrix H,V size in Sub
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_B8, reg_mtx_hsize, pstVideoConfigParams->uiOutputVideoWidth);
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_B8, reg_mtx_vsize, pstVideoConfigParams->uiOutputVideoHight);
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_58, reg_sr_hcb_hsize, pstVideoConfigParams->uiOutputVideoWidth);
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_58, reg_sr_hcb_vsize, pstVideoConfigParams->uiOutputVideoHight);
    }
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_0C, reg_s_upk_width, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_0C, reg_s_upk_height, pstVideoConfigParams->uiDdrOrWtrVideoHight);
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_3C, reg_sr_hcb_pre_hsize, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_3C, reg_sr_hcb_pre_vsize, pstVideoConfigParams->uiDdrOrWtrVideoHight);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_28, reg_01_hdr_act_hsize, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_28, reg_01_hdr_act_vsize, pstVideoConfigParams->uiInputVideoHight);
    return;
}

/*cap vgsf mask setting end*/

/*cap vgsf c02 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC02ClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_24, reg_01_ca_vg_c02_func_clk_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubC02Enable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_C420_422_01_00, reg_01_420_422_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubC02DeEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_C420_422_01_08, reg_01_de_en, uiValue);
    return;
}
/*cap vgsf c02 setting end*/

/*cap vgsf c24 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC24ClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_28, reg_01_ca_vg_yuv422to444_func_clk_en, uiValue);
    return;
}

/*cap vgsf c24 setting end*/

/*cap vgsf csc1 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubCsc1Config(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    if (ColorFormatType_RGB != pstVideoConfigParams->stColor.eClrFormat)
    {
        /*YUV 配置*/
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_cs1_convert_func_clk_en, 1);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_en, 1);
        if(pstVideoConfigParams->stColor.eClrRange == ColorRangeType_Full_Range)
        {
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_mode_mux, 0);
        }
        else
        {
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_mode_mux, 1);
        }

        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_hdr_csc1_ofs_in_v, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_3C, reg_01_ca_vg_hdr_csc1_ofs_in_y, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_48, reg_01_ca_vg_hdr_csc1_ofs_in_u, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_38, reg_01_ca_vg_csc1_y_r_coef, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_40, reg_01_ca_vg_csc1_u_g_coef, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_48, reg_01_ca_vg_csc1_v_b_coef, 0);
    }
    else /*RGB*/
    {
        /*RGB limited需要转化成RGB full 颜色才正确，否则会偏白色*/
        if (ColorRangeType_Limited_Range == pstVideoConfigParams->stColor.eClrRange)
        {
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_cs1_convert_func_clk_en, 1);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_en, 1);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_mode_mux, 7);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_hdr_csc1_ofs_in_v, 0xF00);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_3C, reg_01_ca_vg_hdr_csc1_ofs_in_y, 0xF00);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_48, reg_01_ca_vg_hdr_csc1_ofs_in_u, 0xF00);

            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_38, reg_01_ca_vg_csc1_y_r_coef, 0x12A1);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_40, reg_01_ca_vg_csc1_u_g_coef, 0x12A1);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_48, reg_01_ca_vg_csc1_v_b_coef, 0x12A1);
        }
        else /*RGB full 不必做转化关闭CSC1*/
        {
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_cs1_convert_func_clk_en, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_en, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_mode_mux, 0);

            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_hdr_csc1_ofs_in_v, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_3C, reg_01_ca_vg_hdr_csc1_ofs_in_y, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_48, reg_01_ca_vg_hdr_csc1_ofs_in_u, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_38, reg_01_ca_vg_csc1_y_r_coef, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_40, reg_01_ca_vg_csc1_u_g_coef, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_48, reg_01_ca_vg_csc1_v_b_coef, 0);
        }
    }
    return;
}

BOOL Hv_Cal_DpuScaler_GetCapVgsfSubCsc1FunctionOn()
{
    UINT32 uiValueClkEn = 0;
    UINT32 uiValueCsc1En = 0;
    HV_R32_DECL_VAR();
    uiValueClkEn = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_cs1_convert_func_clk_en);
    uiValueCsc1En = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_01_30, reg_01_ca_vg_csc1_en);
    return (1 == uiValueClkEn) && (1 == uiValueCsc1En);
}
/*cap vgsf csc1 setting end*/

/*cap vgsf csc2 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubCsc2ClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_50, reg_01_ca_vg_cs2_convert_func_clk_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCsc2ConvertOn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_50, reg_01_ca_vg_cs2_convert_on, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCsc2ConvertMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_50, reg_01_ca_vg_cs2_convert_mode, uiValue);
    return;
}
/*cap vgsf csc2 setting end*/

/*C42 begin*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC42FuncClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_90, reg_01_ca_vg_c42_func_clk_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubC42On(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_90, reg_01_ca_vg_c42_on, uiValue);
    return;
}
/*C42 end*/

/*C20 begin*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC20FuncClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_90, reg_01_ca_vg_c20_func_clk_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubC20Enable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_C422_420_01_00, reg_01_422_420_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubC20CbCrPosAdjEnable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_C422_420_01_04, reg_01_cbcr_pos_adj, bEn);
    return;
}
/*C20 end*/

/*cap vgsf scf down setting start*/

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgMsfYhMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_6C, reg_01_ca_vg_msf_yhmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgMsfYvMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_6C, reg_01_ca_vg_msf_yvmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgHsfInSize(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_78, reg_01_ca_vg_hsf_in_size, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgHsfOutSize(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_7C, reg_01_ca_vg_hsf_out_size, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVghfilbase(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_80, reg_01_ca_vg_hfilbase, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgVsfInSize(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_78, reg_01_ca_vg_vsf_in_size, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgVsfOutSize(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_7C, reg_01_ca_vg_vsf_out_size, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgVfilbase(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_84, reg_01_ca_vg_vfilbase, uiValue);
    return;
}

/***********Dpu cap vgsf settings end*********************/


/***********dpc cap settings begin*********************/

VOID Hv_Cal_DpuScaler_DpcCapSubVmDataMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_01_04, reg_01_ca_data_mode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpcCapSubVmDataBitWidth(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_01_04, reg_01_ca_data_bitwidth, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpcCapSubEncPackWork(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_01_04, reg_01_ca_enc_pack_work, uiValue);
    return;
}

/***********dpc cap settings begin*********************/

/*****************dpc srp  settings begin*****************/

/*Sub*/
VOID Hv_Cal_DpuScaler_DpcSrpSubUnpackClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_10, reg_s_unpack_clk_en, uiValue);   /*sub throuth*/
    return;
}

VOID Hv_Cal_DpuScaler_DpcSrpSubUpHbp(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_10, reg_s_upk_hbp, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_DpcSrpSubUpLastMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_10, reg_s_upk_last_mode, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_DpcSrpSubDataMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_10, reg_s_data_mode, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_DpcSrpSubDataWidth(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_10, reg_s_data_width, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_DpcSrpSubFrcFrameSyncSel(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_10, reg_s_frc_framesync_sel, uiValue);
    return;
}

/*****************dpc srp  settings end*****************/

/***********srp top main settings begin*********************/

/*srp top sub*/
VOID Hv_Cal_DpuScaler_SrpTopSubSrPassthrough(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_04, reg_sr_passthrough, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubSrSpatOn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_48, reg_sr_spat_on, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubSrSpatMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_48, reg_sr_spat_mode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubSrSpatWith(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_48, reg_sr_spat_width, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubC02Config(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    UINT32 uiWidthScf  = pstVideoConfigParams->uiDdrOrWtrVideoWidth;
    UINT32 uiHeightScf = pstVideoConfigParams->uiDdrOrWtrVideoHight;

    if (ColorFormatType_YCbCr420 != pstVideoConfigParams->stFrameBufferCfg.enFBColorFormat)
    {
        HV_W32_FIELD(DISP_TOP_C420_422_03_00, reg_03_420_422_en, 0);
        HV_W32_FIELD(DISP_TOP_C420_422_03_08, reg_03_cbcr_pos_adj, 0);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_C420_422_03_00, reg_03_420_422_en, 1);
        HV_W32_FIELD(DISP_TOP_C420_422_03_08, reg_03_cbcr_pos_adj, 1);
    }

    HV_W32_FIELD(DISP_TOP_C420_422_03_08, reg_03_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_C420_422_03_08, reg_03_de_en, 0);
    HV_W32_FIELD(DISP_TOP_C420_422_03_0C, reg_03_hact, uiWidthScf);
    HV_W32_FIELD(DISP_TOP_C420_422_03_0C, reg_03_vact, uiHeightScf);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubSrC24Config(const VideoConfigParams* pstVideoConfigParams)
{    
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    UINT32 uiWidthScf  = pstVideoConfigParams->uiDdrOrWtrVideoWidth;
    UINT32 uiHeightScf = pstVideoConfigParams->uiDdrOrWtrVideoHight;

    if (ColorFormatType_YCbCr420 == pstVideoConfigParams->stFrameBufferCfg.enFBColorFormat
    || (ColorFormatType_YCbCr422 == pstVideoConfigParams->stFrameBufferCfg.enFBColorFormat))
    {
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_08, reg_sr_c24_on, 1);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_SRP_S_TOP_08, reg_sr_c24_on, 0);
    }

    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_08, reg_sr_c24_mode, 1);/*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_08, reg_sr_c24_htap1, 0x48);/*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_08, reg_sr_c24_htap2, 0xF8);/*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_0C, reg_sr_c24_hsize, uiWidthScf);
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_0C, reg_sr_c24_vsize, uiHeightScf);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubSrCbScfOn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_04, reg_sr_cb_scf_on, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScThrouSw(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_sc_throu_sw, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScCvmode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_sc_cvmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScChmode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_sc_chmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScYvmode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_sc_yvmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScYhmode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_sc_yhmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScUpClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_clk_en_core_A, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScHfilbase(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_2C, reg_01_sc_hfilbase, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubScVfilbase(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_30, reg_01_sc_vfilbase, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubSrScfTableId(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_A0, reg_01_sr_scf_table_id, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubCtSrCbMtxOn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_04, reg_ct_sr_cb_mtx_on, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_SrpTopSubScHflip(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_sc_h_flip, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubMtxCtEnUsrmxThrough(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_B8, reg_mtx_ct_en_usrmx_through, uiValue);
    return;
}


VOID Hv_Cal_DpuScaler_SrpTopSubSrCs1ConvertOn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_14, reg_sr_cs1_convert_on, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopSubSrCs1ConvertMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_14, reg_sr_cs1_convert_mode, uiValue);
    return;
}

/***********srp top settings end*********************/

VOID Hv_Cal_DpuScaler_SetSubWindowConifg(DpuWindowParam* pstSubChannelWindowParam)
{
    UINT32 uiTtimingSel = 0;
    HV_R32_DECL_VAR();
    uiTtimingSel = HV_R32_FIELD(DISP_TOP_DTC_TOP_0C, reg_dtc_timing_sel);
    if (uiTtimingSel == 3)
    {
        HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_seamless_en, 0);
    }
    HV_W32_FIELD(DISP_TOP_DTC_TOP_60, reg_dtc_ch2_hsta, pstSubChannelWindowParam->usDtcChHsta);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_60, reg_dtc_ch2_hend, pstSubChannelWindowParam->usDtcChHend);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_64, reg_dtc_ch2_vsta, pstSubChannelWindowParam->usDtcChVsta);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_64, reg_dtc_ch2_vend, pstSubChannelWindowParam->usDtcChVend);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_7C, reg_sub_border_hstart, pstSubChannelWindowParam->usBorderHstart);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_7C, reg_sub_border_vstart, pstSubChannelWindowParam->usBorderVstart);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_80, reg_sub_border_length, pstSubChannelWindowParam->usBorderLength);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_80, reg_sub_border_height, pstSubChannelWindowParam->usBorderHeight);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_68, reg_sub_border_width, pstSubChannelWindowParam->ucBorderWidth);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_70, reg_sub_border_color, pstSubChannelWindowParam->ucBborderColor);
    if (uiTtimingSel == 3)
    {
        HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_seamless_en, 1);
    }
}

VOID Hv_Cal_DpuScaler_DtcSubWindowEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_68, reg_dtc_ch2_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_LdgSubBorderEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_68, reg_sub_border_en, bEn);
    return;
}

/*****************vdm settings begin**************************/
/*WDMA line Mode Setting*/

VOID Hv_Cal_DpuScaler_DpuWvdm01WrEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_08, reg_01_dm_wr_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpuRvdm01LineRdEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_04, reg_01_dm_rd_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpuVdmSubConfig(const DpuVdmConfigSettings *pstDpuVdmConfigSettings)
{
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_04, reg_01_dm_rd_col_step_dir, pstDpuVdmConfigSettings->ucDmRdColStepDir);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_04, reg_01_dm_rd_line_step_dir, pstDpuVdmConfigSettings->ucDmRdLineStepDir);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_2C, reg_01_dm_start_adr2, pstDpuVdmConfigSettings->uiDmRdStartAdr2);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_2C, reg_01_dm_start_adr2, pstDpuVdmConfigSettings->uiDmWrStartAdr2);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_0C, reg_01_dm_rd_col_step, pstDpuVdmConfigSettings->uiDmColStep);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_18, reg_01_dm_rd_col_dat_num, pstDpuVdmConfigSettings->usDmRdColDatNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_20, reg_01_dm_rd_total_col_num, pstDpuVdmConfigSettings->usDmTotalColNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_04, reg_01_dm_rd_burst_len, pstDpuVdmConfigSettings->ucDmBurstLen);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_08, reg_01_dm_rd_burst_num, pstDpuVdmConfigSettings->uiDmBurstNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_04, reg_01_dm_rd_burst_rmd, pstDpuVdmConfigSettings->ucDmBurstRmd);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_10, reg_01_dm_rd_line_step, pstDpuVdmConfigSettings->uiDmLineStep);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_20, reg_01_dm_rd_total_line_num, pstDpuVdmConfigSettings->usDmTotalLineNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_04, reg_01_dm_rd_outstanding, pstDpuVdmConfigSettings->ucDmOutstanding);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_14, reg_01_dm_rd_start_adr, pstDpuVdmConfigSettings->uiDmRdStartAdr);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_24, reg_01_dm_start_adr0, pstDpuVdmConfigSettings->uiDmRdStartAdr0);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_28, reg_01_dm_start_adr1, pstDpuVdmConfigSettings->uiDmRdStartAdr1);

    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_10, reg_01_dm_wr_col_step, pstDpuVdmConfigSettings->uiDmColStep);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_1C, reg_01_dm_wr_total_col_num, pstDpuVdmConfigSettings->usDmTotalColNum);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_08, reg_01_dm_wr_burst_len, pstDpuVdmConfigSettings->ucDmBurstLen);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_0C, reg_01_dm_wr_burst_num, pstDpuVdmConfigSettings->uiDmBurstNum);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_08, reg_01_dm_wr_burst_rmd, pstDpuVdmConfigSettings->ucDmBurstRmd);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_14, reg_01_dm_wr_line_step, pstDpuVdmConfigSettings->uiDmLineStep);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_1C, reg_01_dm_wr_total_line_num, pstDpuVdmConfigSettings->usDmTotalLineNum);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_08, reg_01_dm_wr_outstanding, pstDpuVdmConfigSettings->ucDmOutstanding);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_18, reg_01_dm_wr_start_adr, pstDpuVdmConfigSettings->uiDmWrStartAdr);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_24, reg_01_dm_start_adr0, pstDpuVdmConfigSettings->uiDmWrStartAdr0);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_28, reg_01_dm_start_adr1, pstDpuVdmConfigSettings->uiDmWrStartAdr1);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubVdmReadAddr0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_24, reg_01_dm_start_adr0, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubVdmReadAddr1(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_01_28, reg_01_dm_start_adr1, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubVdmWirteAddr0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_24, reg_01_dm_start_adr0, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubVdmWirteAddr1(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_01_28, reg_01_dm_start_adr1, uiValue);
    return;
}

UINT32 Hv_Cal_DpuScaler_GetSubVdmReadAddr0(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DPU_RVDM_01_24, reg_01_dm_start_adr0);
}

UINT32 Hv_Cal_DpuScaler_GetSubVdmReadAddr1(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DPU_RVDM_01_28, reg_01_dm_start_adr1);
}
/*****************vdm settings end*****************************/

/*****************sub ldg top settings begin***************************/

/*sub*/
VOID Hv_Cal_DpuScaler_SubLdgTopSubCscEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_38, reg_sub_csc_en, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_SubLdgTopSubBlendEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_68, reg_sub_blend_en, uiValue);
    return;
}

/*****************sub ldg top settings end***************************/

VOID Hv_Cal_DpuScaler_ScSubPhosPsA0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_24, reg_01_sc_phos_ps_A, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubPhosPsB0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_28, reg_01_sc_phos_ps_B, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubOrfCrlev(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_38, reg_01_sc_orf_crlev, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubOrfCblev(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_38, reg_01_sc_orf_cblev, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubOrfYlev(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_38, reg_01_sc_orf_ylev, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubPvosPs0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_20, reg_01_sc_pvos_ps0, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubPvosPs1(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_A0, reg_01_sc_pvos_ps1, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubFeildSel(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_A0, reg_01_sc_field_sel, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScSubFeildPolar(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_A0, reg_01_sc_field_polar, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubHdrPassthrough(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_00, reg_01_ct_ldg_hdr_passthrough, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubHdrGmiEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_00, reg_01_ct_en_gmi_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubHdrOotfEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_04, reg_01_ct_en_ootf_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubHdrGmdEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_14, reg_01_ct_en_gmd_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubHdrLutGmiEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_58, reg_01_lut_hdr_gmi_en, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_CapVgsfSubHdrLutOotfEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_58, reg_01_lut_hdr_ootf_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfSubHdrLutGmdEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_01_58, reg_01_lut_hdr_gmd_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpuVdmTblRdSubEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_01_04, reg_01_dm_rd_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpuVdmTblRdSubTblTblEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_01_C8, reg_01_dm_tbl_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubFrcIndex(BOOL bStart)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_A0, reg_frc_s_index_start, bStart);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubSrpLatch(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_00, reg_en_no_latch, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_DpuDtcSubReadFreeze(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_9C, reg_frc_s_read_freeze, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_DpuDtcSubRx2ClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_00, reg_rx2_clk_en, bEn);     /*sub 通道*/
    return;
}



