#ifndef _HV_PAGE_HT7315_SH5_AXI_BUS_MONITOR_REGMAP5_H_
#define _HV_PAGE_HT7315_SH5_AXI_BUS_MONITOR_REGMAP5_H_

#ifndef HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS
    #define HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS                                         0x11011700
#endif


#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_00                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x00)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_00_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_00

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_00  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_00;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_00 {
    unsigned int reg_sh5_axi_bus_bandwidth_monitor_reg_test_num:32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_00(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_00*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_04                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x04)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_04_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_04

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_04  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_04;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_04 {
    unsigned int reg_sh5_latency_monitor_reg_required_latency:32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_04(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_04*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_08                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x08)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_08_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_08

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_08  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_08;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_08 {
    unsigned int reg_sh5_latency_monitor_reg_average_latency_begin_time:32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_08(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_08*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_0C                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x0C)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_0C_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_0c

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_0c  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_0c;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_0c {
    unsigned int reg_sh5_latency_monitor_reg_average_latency_time:32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_0c(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_0c*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_10                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x10)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_10_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_10

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_10  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_10;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_10 {
    unsigned int reg_sh5_latency_monitor_o_w_max_latency    :32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_10(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_10*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_14                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x14)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_14_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_14

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_14  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_14;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_14 {
    unsigned int reg_sh5_latency_monitor_o_r_max_latency    :32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_14(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_14*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_18                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x18)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_18_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_18

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_18  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_18;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_18 {
    unsigned int reg_sh5_latency_monitor_o_w_average_latency:32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_18(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_18*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_1C                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x1C)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_1C_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_1c

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_1c  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_1c;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_1c {
    unsigned int reg_sh5_latency_monitor_o_r_average_latency:32;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_1c(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_1c*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_20                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x20)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_20_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_20

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_20  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_20;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_20 {
    unsigned int reg_sh5_axi_bus_monitor_en                 : 1;
    unsigned int reg_sh5_axi_bus_bandwidth_monitor_en       : 1;
    unsigned int reg_sh5_cpu_cmd_monitor_en                 : 1;
    unsigned int reg_sh5_latency_monitor_en                 : 1;
    unsigned int reg_sh5_latency_monitor_INT_en             : 1;
    unsigned int reg_axi_signal_sel                         : 3;
    unsigned int reserved                                   :24;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_20(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_20*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_24                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x24)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_24_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_24

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_24  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_24;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_24 {
    unsigned int reg_sh5_latency_monitor_o_sh5_latency_monitor_INT: 1;
    unsigned int reg_sh5_latency_monitor_o_w_overtime_occur : 1;
    unsigned int reg_sh5_latency_monitor_o_r_overtime_occur : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_sh5_latency_monitor_o_w_exokay_response_occur: 1;
    unsigned int reg_sh5_latency_monitor_o_w_slverr_response_occur: 1;
    unsigned int reg_sh5_latency_monitor_o_w_decerr_response_occur: 1;
    unsigned int reg_sh5_latency_monitor_o_r_exokay_response_occur: 1;
    unsigned int reg_sh5_latency_monitor_o_r_slverr_response_occur: 1;
    unsigned int reg_sh5_latency_monitor_o_r_decerr_response_occur: 1;
    unsigned int reserved_1                                 :22;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_24(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_24*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_28                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x28)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_28_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_28

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_28  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_28;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_28 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size0_burst0:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size0_burst1:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_28(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_28*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_2C                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x2C)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_2C_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_2c

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_2c  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_2c;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_2c {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size0_burst2:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size1_burst0:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_2c(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_2c*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_30                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x30)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_30_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_30

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_30  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_30;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_30 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size1_burst1:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size1_burst2:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_30(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_30*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_34                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x34)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_34_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_34

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_34  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_34;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_34 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size2_burst0:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size2_burst1:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_34(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_34*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_38                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x38)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_38_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_38

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_38  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_38;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_38 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size2_burst2:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size3_burst0:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_38(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_38*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_3C                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x3C)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_3C_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_3c

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_3c  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_3c;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_3c {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size3_burst1:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size3_burst2:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_3c(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_3c*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_40                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x40)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_40_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_40

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_40  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_40;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_40 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size4_burst0:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size4_burst1:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_40(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_40*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_44                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x44)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_44_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_44

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_44  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_44;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_44 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size4_burst2:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size5_burst0:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_44(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_44*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_48                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x48)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_48_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_48

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_48  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_48;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_48 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size5_burst1:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size5_burst2:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_48(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_48*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_4C                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x4C)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_4C_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_4c

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_4c  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_4c;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_4c {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size6_burst0:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size6_burst1:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_4c(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_4c*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_50                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x50)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_50_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_50

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_50  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_50;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_50 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size6_burst2:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size7_burst0:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_50(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_50*)&(val))



#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_54                     (HV_SH5_AXI_BUS_MONITOR_REGMAP5_BASE_ADDRESS + 0x54)

#define SYS_SH5_AXI_BUS_MONITOR_REGMAP5_FIELD_ENH_54_struct              rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_54

typedef struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_54  rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_54;
struct _rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_54 {
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size7_burst1:16;
    unsigned int reg_sh5_cpu_cmd_monitor_o_num_ar_size7_burst2:16;
};
#define sys_sh5_axi_bus_monitor_regmap5_field_enh_54(val) ((rs_sys_sh5_axi_bus_monitor_regmap5_field_enh_54*)&(val))



#endif