#ifndef _HV_PAGE_HT7315_QSPI_H_
#define _HV_PAGE_HT7315_QSPI_H_

#ifndef HV_QSPI_BASE_ADDRESS
    #define HV_QSPI_BASE_ADDRESS                                         0x110A0000
#endif


#define CPU_SYS_2_QSPI_CTRLR0                                            (HV_QSPI_BASE_ADDRESS + 0x000)

#define CPU_SYS_2_QSPI_CTRLR0_struct                                     rs_cpu_sys_2_qspi_ctrlr0

typedef struct _rs_cpu_sys_2_qspi_ctrlr0  rs_cpu_sys_2_qspi_ctrlr0;
struct _rs_cpu_sys_2_qspi_ctrlr0 {
    unsigned int DFS                                        : 5;
    unsigned int reserved                                   : 1;
    unsigned int FRF                                        : 2;
    unsigned int SCPH                                       : 1;
    unsigned int SCPOL                                      : 1;
    unsigned int TMOD                                       : 2;
    unsigned int SLV_OE                                     : 1;
    unsigned int SRL                                        : 1;
    unsigned int SSTE                                       : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int CFS                                        : 4;
    unsigned int reserved_2                                 : 2;
    unsigned int SPI_FRF                                    : 2;
    unsigned int SPI_HYPERBUS_EN                            : 1;
    unsigned int reserved_3                                 : 6;
    unsigned int SSI_IS_MST                                 : 1;
};
#define cpu_sys_2_qspi_ctrlr0(val) ((rs_cpu_sys_2_qspi_ctrlr0*)&(val))



#define CPU_SYS_2_QSPI_CTRLR1                                            (HV_QSPI_BASE_ADDRESS + 0x004)

#define CPU_SYS_2_QSPI_CTRLR1_struct                                     rs_cpu_sys_2_qspi_ctrlr1

typedef struct _rs_cpu_sys_2_qspi_ctrlr1  rs_cpu_sys_2_qspi_ctrlr1;
struct _rs_cpu_sys_2_qspi_ctrlr1 {
    unsigned int NDF                                        :16;
    unsigned int RSCD_CTRLR1                                :16;
};
#define cpu_sys_2_qspi_ctrlr1(val) ((rs_cpu_sys_2_qspi_ctrlr1*)&(val))



#define CPU_SYS_2_QSPI_SSIENR                                            (HV_QSPI_BASE_ADDRESS + 0x008)

#define CPU_SYS_2_QSPI_SSIENR_struct                                     rs_cpu_sys_2_qspi_ssienr

typedef struct _rs_cpu_sys_2_qspi_ssienr  rs_cpu_sys_2_qspi_ssienr;
struct _rs_cpu_sys_2_qspi_ssienr {
    unsigned int SSIC_EN                                    : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_ssienr(val) ((rs_cpu_sys_2_qspi_ssienr*)&(val))



#define CPU_SYS_2_QSPI_MWCR                                              (HV_QSPI_BASE_ADDRESS + 0x00C)

#define CPU_SYS_2_QSPI_MWCR_struct                                       rs_cpu_sys_2_qspi_mwcr

typedef struct _rs_cpu_sys_2_qspi_mwcr  rs_cpu_sys_2_qspi_mwcr;
struct _rs_cpu_sys_2_qspi_mwcr {
    unsigned int MWMOD                                      : 1;
    unsigned int MDD                                        : 1;
    unsigned int MHS                                        : 1;
    unsigned int reserved                                   :29;
};
#define cpu_sys_2_qspi_mwcr(val) ((rs_cpu_sys_2_qspi_mwcr*)&(val))



#define CPU_SYS_2_QSPI_SER                                               (HV_QSPI_BASE_ADDRESS + 0x010)

#define CPU_SYS_2_QSPI_SER_struct                                        rs_cpu_sys_2_qspi_ser

typedef struct _rs_cpu_sys_2_qspi_ser  rs_cpu_sys_2_qspi_ser;
struct _rs_cpu_sys_2_qspi_ser {
    unsigned int SER                                        : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_ser(val) ((rs_cpu_sys_2_qspi_ser*)&(val))



#define CPU_SYS_2_QSPI_BAUDR                                             (HV_QSPI_BASE_ADDRESS + 0x014)

#define CPU_SYS_2_QSPI_BAUDR_struct                                      rs_cpu_sys_2_qspi_baudr

typedef struct _rs_cpu_sys_2_qspi_baudr  rs_cpu_sys_2_qspi_baudr;
struct _rs_cpu_sys_2_qspi_baudr {
    unsigned int reserved                                   : 1;
    unsigned int SCKDV                                      :15;
    unsigned int reserved_1                                 :16;
};
#define cpu_sys_2_qspi_baudr(val) ((rs_cpu_sys_2_qspi_baudr*)&(val))



#define CPU_SYS_2_QSPI_TXFTLR                                            (HV_QSPI_BASE_ADDRESS + 0x018)

#define CPU_SYS_2_QSPI_TXFTLR_struct                                     rs_cpu_sys_2_qspi_txftlr

typedef struct _rs_cpu_sys_2_qspi_txftlr  rs_cpu_sys_2_qspi_txftlr;
struct _rs_cpu_sys_2_qspi_txftlr {
    unsigned int TFT                                        : 4;
    unsigned int reserved                                   :12;
    unsigned int TXFTHR                                     : 4;
    unsigned int reserved_1                                 :12;
};
#define cpu_sys_2_qspi_txftlr(val) ((rs_cpu_sys_2_qspi_txftlr*)&(val))



#define CPU_SYS_2_QSPI_RXFTLR                                            (HV_QSPI_BASE_ADDRESS + 0x01C)

#define CPU_SYS_2_QSPI_RXFTLR_struct                                     rs_cpu_sys_2_qspi_rxftlr

typedef struct _rs_cpu_sys_2_qspi_rxftlr  rs_cpu_sys_2_qspi_rxftlr;
struct _rs_cpu_sys_2_qspi_rxftlr {
    unsigned int RFT                                        : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_2_qspi_rxftlr(val) ((rs_cpu_sys_2_qspi_rxftlr*)&(val))



#define CPU_SYS_2_QSPI_TXFLR                                             (HV_QSPI_BASE_ADDRESS + 0x020)

#define CPU_SYS_2_QSPI_TXFLR_struct                                      rs_cpu_sys_2_qspi_txflr

typedef struct _rs_cpu_sys_2_qspi_txflr  rs_cpu_sys_2_qspi_txflr;
struct _rs_cpu_sys_2_qspi_txflr {
    unsigned int TXTFL                                      : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_2_qspi_txflr(val) ((rs_cpu_sys_2_qspi_txflr*)&(val))



#define CPU_SYS_2_QSPI_RXFLR                                             (HV_QSPI_BASE_ADDRESS + 0x024)

#define CPU_SYS_2_QSPI_RXFLR_struct                                      rs_cpu_sys_2_qspi_rxflr

typedef struct _rs_cpu_sys_2_qspi_rxflr  rs_cpu_sys_2_qspi_rxflr;
struct _rs_cpu_sys_2_qspi_rxflr {
    unsigned int RXTFL                                      : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_2_qspi_rxflr(val) ((rs_cpu_sys_2_qspi_rxflr*)&(val))



#define CPU_SYS_2_QSPI_SR                                                (HV_QSPI_BASE_ADDRESS + 0x028)

#define CPU_SYS_2_QSPI_SR_struct                                         rs_cpu_sys_2_qspi_sr

typedef struct _rs_cpu_sys_2_qspi_sr  rs_cpu_sys_2_qspi_sr;
struct _rs_cpu_sys_2_qspi_sr {
    unsigned int BUSY                                       : 1;
    unsigned int TFNF                                       : 1;
    unsigned int TFE                                        : 1;
    unsigned int RFNE                                       : 1;
    unsigned int RFF                                        : 1;
    unsigned int TXE                                        : 1;
    unsigned int DCOL                                       : 1;
    unsigned int reserved                                   :25;
};
#define cpu_sys_2_qspi_sr(val) ((rs_cpu_sys_2_qspi_sr*)&(val))



#define CPU_SYS_2_QSPI_IMR                                               (HV_QSPI_BASE_ADDRESS + 0x02C)

#define CPU_SYS_2_QSPI_IMR_struct                                        rs_cpu_sys_2_qspi_imr

typedef struct _rs_cpu_sys_2_qspi_imr  rs_cpu_sys_2_qspi_imr;
struct _rs_cpu_sys_2_qspi_imr {
    unsigned int TXEIM                                      : 1;
    unsigned int TXOIM                                      : 1;
    unsigned int RXUIM                                      : 1;
    unsigned int RXOIM                                      : 1;
    unsigned int RXFIM                                      : 1;
    unsigned int MSTIM                                      : 1;
    unsigned int XRXOIM                                     : 1;
    unsigned int reserved                                   :25;
};
#define cpu_sys_2_qspi_imr(val) ((rs_cpu_sys_2_qspi_imr*)&(val))



#define CPU_SYS_2_QSPI_ISR                                               (HV_QSPI_BASE_ADDRESS + 0x030)

#define CPU_SYS_2_QSPI_ISR_struct                                        rs_cpu_sys_2_qspi_isr

typedef struct _rs_cpu_sys_2_qspi_isr  rs_cpu_sys_2_qspi_isr;
struct _rs_cpu_sys_2_qspi_isr {
    unsigned int TXEIS                                      : 1;
    unsigned int TXOIS                                      : 1;
    unsigned int RXUIS                                      : 1;
    unsigned int RXOIS                                      : 1;
    unsigned int RXFIS                                      : 1;
    unsigned int MSTIS                                      : 1;
    unsigned int XRXOIS                                     : 1;
    unsigned int reserved                                   :25;
};
#define cpu_sys_2_qspi_isr(val) ((rs_cpu_sys_2_qspi_isr*)&(val))



#define CPU_SYS_2_QSPI_RISR                                              (HV_QSPI_BASE_ADDRESS + 0x034)

#define CPU_SYS_2_QSPI_RISR_struct                                       rs_cpu_sys_2_qspi_risr

typedef struct _rs_cpu_sys_2_qspi_risr  rs_cpu_sys_2_qspi_risr;
struct _rs_cpu_sys_2_qspi_risr {
    unsigned int TXEIR                                      : 1;
    unsigned int TXOIR                                      : 1;
    unsigned int RXUIR                                      : 1;
    unsigned int RXOIR                                      : 1;
    unsigned int RXFIR                                      : 1;
    unsigned int MSTIR                                      : 1;
    unsigned int XRXOIR                                     : 1;
    unsigned int reserved                                   :25;
};
#define cpu_sys_2_qspi_risr(val) ((rs_cpu_sys_2_qspi_risr*)&(val))



#define CPU_SYS_2_QSPI_TXOICR                                            (HV_QSPI_BASE_ADDRESS + 0x038)

#define CPU_SYS_2_QSPI_TXOICR_struct                                     rs_cpu_sys_2_qspi_txoicr

typedef struct _rs_cpu_sys_2_qspi_txoicr  rs_cpu_sys_2_qspi_txoicr;
struct _rs_cpu_sys_2_qspi_txoicr {
    unsigned int TXOICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_txoicr(val) ((rs_cpu_sys_2_qspi_txoicr*)&(val))



#define CPU_SYS_2_QSPI_RXOICR                                            (HV_QSPI_BASE_ADDRESS + 0x03C)

#define CPU_SYS_2_QSPI_RXOICR_struct                                     rs_cpu_sys_2_qspi_rxoicr

typedef struct _rs_cpu_sys_2_qspi_rxoicr  rs_cpu_sys_2_qspi_rxoicr;
struct _rs_cpu_sys_2_qspi_rxoicr {
    unsigned int RXOICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_rxoicr(val) ((rs_cpu_sys_2_qspi_rxoicr*)&(val))



#define CPU_SYS_2_QSPI_RXUICR                                            (HV_QSPI_BASE_ADDRESS + 0x040)

#define CPU_SYS_2_QSPI_RXUICR_struct                                     rs_cpu_sys_2_qspi_rxuicr

typedef struct _rs_cpu_sys_2_qspi_rxuicr  rs_cpu_sys_2_qspi_rxuicr;
struct _rs_cpu_sys_2_qspi_rxuicr {
    unsigned int RXUICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_rxuicr(val) ((rs_cpu_sys_2_qspi_rxuicr*)&(val))



#define CPU_SYS_2_QSPI_MSTICR                                            (HV_QSPI_BASE_ADDRESS + 0x044)

#define CPU_SYS_2_QSPI_MSTICR_struct                                     rs_cpu_sys_2_qspi_msticr

typedef struct _rs_cpu_sys_2_qspi_msticr  rs_cpu_sys_2_qspi_msticr;
struct _rs_cpu_sys_2_qspi_msticr {
    unsigned int MSTICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_msticr(val) ((rs_cpu_sys_2_qspi_msticr*)&(val))



#define CPU_SYS_2_QSPI_ICR                                               (HV_QSPI_BASE_ADDRESS + 0x048)

#define CPU_SYS_2_QSPI_ICR_struct                                        rs_cpu_sys_2_qspi_icr

typedef struct _rs_cpu_sys_2_qspi_icr  rs_cpu_sys_2_qspi_icr;
struct _rs_cpu_sys_2_qspi_icr {
    unsigned int ICR                                        : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_icr(val) ((rs_cpu_sys_2_qspi_icr*)&(val))



#define CPU_SYS_2_QSPI_DMACR                                             (HV_QSPI_BASE_ADDRESS + 0x04C)

#define CPU_SYS_2_QSPI_DMACR_struct                                      rs_cpu_sys_2_qspi_dmacr

typedef struct _rs_cpu_sys_2_qspi_dmacr  rs_cpu_sys_2_qspi_dmacr;
struct _rs_cpu_sys_2_qspi_dmacr {
    unsigned int RDMAE                                      : 1;
    unsigned int TDMAE                                      : 1;
    unsigned int reserved                                   :30;
};
#define cpu_sys_2_qspi_dmacr(val) ((rs_cpu_sys_2_qspi_dmacr*)&(val))



#define CPU_SYS_2_QSPI_DMATDLR                                           (HV_QSPI_BASE_ADDRESS + 0x050)

#define CPU_SYS_2_QSPI_DMATDLR_struct                                    rs_cpu_sys_2_qspi_dmatdlr

typedef struct _rs_cpu_sys_2_qspi_dmatdlr  rs_cpu_sys_2_qspi_dmatdlr;
struct _rs_cpu_sys_2_qspi_dmatdlr {
    unsigned int DMATDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_2_qspi_dmatdlr(val) ((rs_cpu_sys_2_qspi_dmatdlr*)&(val))



#define CPU_SYS_2_QSPI_DMARDLR                                           (HV_QSPI_BASE_ADDRESS + 0x054)

#define CPU_SYS_2_QSPI_DMARDLR_struct                                    rs_cpu_sys_2_qspi_dmardlr

typedef struct _rs_cpu_sys_2_qspi_dmardlr  rs_cpu_sys_2_qspi_dmardlr;
struct _rs_cpu_sys_2_qspi_dmardlr {
    unsigned int DMARDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_2_qspi_dmardlr(val) ((rs_cpu_sys_2_qspi_dmardlr*)&(val))



#define CPU_SYS_2_QSPI_IDR                                               (HV_QSPI_BASE_ADDRESS + 0x058)

#define CPU_SYS_2_QSPI_IDR_struct                                        rs_cpu_sys_2_qspi_idr

typedef struct _rs_cpu_sys_2_qspi_idr  rs_cpu_sys_2_qspi_idr;
struct _rs_cpu_sys_2_qspi_idr {
    unsigned int IDCODE                                     :32;
};
#define cpu_sys_2_qspi_idr(val) ((rs_cpu_sys_2_qspi_idr*)&(val))



#define CPU_SYS_2_QSPI_SSIC_VERSION_ID                                   (HV_QSPI_BASE_ADDRESS + 0x05C)

#define CPU_SYS_2_QSPI_SSIC_VERSION_ID_struct                            rs_cpu_sys_2_qspi_ssic_version_id

typedef struct _rs_cpu_sys_2_qspi_ssic_version_id  rs_cpu_sys_2_qspi_ssic_version_id;
struct _rs_cpu_sys_2_qspi_ssic_version_id {
    unsigned int SSIC_COMP_VERSION                          :32;
};
#define cpu_sys_2_qspi_ssic_version_id(val) ((rs_cpu_sys_2_qspi_ssic_version_id*)&(val))



#define CPU_SYS_2_QSPI_DR0                                               (HV_QSPI_BASE_ADDRESS + 0x060)

#define CPU_SYS_2_QSPI_DR0_struct                                        rs_cpu_sys_2_qspi_dr0

typedef struct _rs_cpu_sys_2_qspi_dr0  rs_cpu_sys_2_qspi_dr0;
struct _rs_cpu_sys_2_qspi_dr0 {
    unsigned int DR0                                        :32;
};
#define cpu_sys_2_qspi_dr0(val) ((rs_cpu_sys_2_qspi_dr0*)&(val))



#define CPU_SYS_2_QSPI_DR1                                               (HV_QSPI_BASE_ADDRESS + 0x064)

#define CPU_SYS_2_QSPI_DR1_struct                                        rs_cpu_sys_2_qspi_dr1

typedef struct _rs_cpu_sys_2_qspi_dr1  rs_cpu_sys_2_qspi_dr1;
struct _rs_cpu_sys_2_qspi_dr1 {
    unsigned int DR1                                        :32;
};
#define cpu_sys_2_qspi_dr1(val) ((rs_cpu_sys_2_qspi_dr1*)&(val))



#define CPU_SYS_2_QSPI_DR2                                               (HV_QSPI_BASE_ADDRESS + 0x068)

#define CPU_SYS_2_QSPI_DR2_struct                                        rs_cpu_sys_2_qspi_dr2

typedef struct _rs_cpu_sys_2_qspi_dr2  rs_cpu_sys_2_qspi_dr2;
struct _rs_cpu_sys_2_qspi_dr2 {
    unsigned int DR2                                        :32;
};
#define cpu_sys_2_qspi_dr2(val) ((rs_cpu_sys_2_qspi_dr2*)&(val))



#define CPU_SYS_2_QSPI_DR3                                               (HV_QSPI_BASE_ADDRESS + 0x06C)

#define CPU_SYS_2_QSPI_DR3_struct                                        rs_cpu_sys_2_qspi_dr3

typedef struct _rs_cpu_sys_2_qspi_dr3  rs_cpu_sys_2_qspi_dr3;
struct _rs_cpu_sys_2_qspi_dr3 {
    unsigned int DR3                                        :32;
};
#define cpu_sys_2_qspi_dr3(val) ((rs_cpu_sys_2_qspi_dr3*)&(val))



#define CPU_SYS_2_QSPI_DR4                                               (HV_QSPI_BASE_ADDRESS + 0x070)

#define CPU_SYS_2_QSPI_DR4_struct                                        rs_cpu_sys_2_qspi_dr4

typedef struct _rs_cpu_sys_2_qspi_dr4  rs_cpu_sys_2_qspi_dr4;
struct _rs_cpu_sys_2_qspi_dr4 {
    unsigned int DR4                                        :32;
};
#define cpu_sys_2_qspi_dr4(val) ((rs_cpu_sys_2_qspi_dr4*)&(val))



#define CPU_SYS_2_QSPI_DR5                                               (HV_QSPI_BASE_ADDRESS + 0x074)

#define CPU_SYS_2_QSPI_DR5_struct                                        rs_cpu_sys_2_qspi_dr5

typedef struct _rs_cpu_sys_2_qspi_dr5  rs_cpu_sys_2_qspi_dr5;
struct _rs_cpu_sys_2_qspi_dr5 {
    unsigned int DR5                                        :32;
};
#define cpu_sys_2_qspi_dr5(val) ((rs_cpu_sys_2_qspi_dr5*)&(val))



#define CPU_SYS_2_QSPI_DR6                                               (HV_QSPI_BASE_ADDRESS + 0x078)

#define CPU_SYS_2_QSPI_DR6_struct                                        rs_cpu_sys_2_qspi_dr6

typedef struct _rs_cpu_sys_2_qspi_dr6  rs_cpu_sys_2_qspi_dr6;
struct _rs_cpu_sys_2_qspi_dr6 {
    unsigned int DR6                                        :32;
};
#define cpu_sys_2_qspi_dr6(val) ((rs_cpu_sys_2_qspi_dr6*)&(val))



#define CPU_SYS_2_QSPI_DR7                                               (HV_QSPI_BASE_ADDRESS + 0x07C)

#define CPU_SYS_2_QSPI_DR7_struct                                        rs_cpu_sys_2_qspi_dr7

typedef struct _rs_cpu_sys_2_qspi_dr7  rs_cpu_sys_2_qspi_dr7;
struct _rs_cpu_sys_2_qspi_dr7 {
    unsigned int DR7                                        :32;
};
#define cpu_sys_2_qspi_dr7(val) ((rs_cpu_sys_2_qspi_dr7*)&(val))



#define CPU_SYS_2_QSPI_DR8                                               (HV_QSPI_BASE_ADDRESS + 0x080)

#define CPU_SYS_2_QSPI_DR8_struct                                        rs_cpu_sys_2_qspi_dr8

typedef struct _rs_cpu_sys_2_qspi_dr8  rs_cpu_sys_2_qspi_dr8;
struct _rs_cpu_sys_2_qspi_dr8 {
    unsigned int DR8                                        :32;
};
#define cpu_sys_2_qspi_dr8(val) ((rs_cpu_sys_2_qspi_dr8*)&(val))



#define CPU_SYS_2_QSPI_DR9                                               (HV_QSPI_BASE_ADDRESS + 0x084)

#define CPU_SYS_2_QSPI_DR9_struct                                        rs_cpu_sys_2_qspi_dr9

typedef struct _rs_cpu_sys_2_qspi_dr9  rs_cpu_sys_2_qspi_dr9;
struct _rs_cpu_sys_2_qspi_dr9 {
    unsigned int DR9                                        :32;
};
#define cpu_sys_2_qspi_dr9(val) ((rs_cpu_sys_2_qspi_dr9*)&(val))



#define CPU_SYS_2_QSPI_DR10                                              (HV_QSPI_BASE_ADDRESS + 0x088)

#define CPU_SYS_2_QSPI_DR10_struct                                       rs_cpu_sys_2_qspi_dr10

typedef struct _rs_cpu_sys_2_qspi_dr10  rs_cpu_sys_2_qspi_dr10;
struct _rs_cpu_sys_2_qspi_dr10 {
    unsigned int DR10                                       :32;
};
#define cpu_sys_2_qspi_dr10(val) ((rs_cpu_sys_2_qspi_dr10*)&(val))



#define CPU_SYS_2_QSPI_DR11                                              (HV_QSPI_BASE_ADDRESS + 0x08C)

#define CPU_SYS_2_QSPI_DR11_struct                                       rs_cpu_sys_2_qspi_dr11

typedef struct _rs_cpu_sys_2_qspi_dr11  rs_cpu_sys_2_qspi_dr11;
struct _rs_cpu_sys_2_qspi_dr11 {
    unsigned int DR11                                       :32;
};
#define cpu_sys_2_qspi_dr11(val) ((rs_cpu_sys_2_qspi_dr11*)&(val))



#define CPU_SYS_2_QSPI_DR12                                              (HV_QSPI_BASE_ADDRESS + 0x090)

#define CPU_SYS_2_QSPI_DR12_struct                                       rs_cpu_sys_2_qspi_dr12

typedef struct _rs_cpu_sys_2_qspi_dr12  rs_cpu_sys_2_qspi_dr12;
struct _rs_cpu_sys_2_qspi_dr12 {
    unsigned int DR12                                       :32;
};
#define cpu_sys_2_qspi_dr12(val) ((rs_cpu_sys_2_qspi_dr12*)&(val))



#define CPU_SYS_2_QSPI_DR13                                              (HV_QSPI_BASE_ADDRESS + 0x094)

#define CPU_SYS_2_QSPI_DR13_struct                                       rs_cpu_sys_2_qspi_dr13

typedef struct _rs_cpu_sys_2_qspi_dr13  rs_cpu_sys_2_qspi_dr13;
struct _rs_cpu_sys_2_qspi_dr13 {
    unsigned int DR13                                       :32;
};
#define cpu_sys_2_qspi_dr13(val) ((rs_cpu_sys_2_qspi_dr13*)&(val))



#define CPU_SYS_2_QSPI_DR14                                              (HV_QSPI_BASE_ADDRESS + 0x098)

#define CPU_SYS_2_QSPI_DR14_struct                                       rs_cpu_sys_2_qspi_dr14

typedef struct _rs_cpu_sys_2_qspi_dr14  rs_cpu_sys_2_qspi_dr14;
struct _rs_cpu_sys_2_qspi_dr14 {
    unsigned int DR14                                       :32;
};
#define cpu_sys_2_qspi_dr14(val) ((rs_cpu_sys_2_qspi_dr14*)&(val))



#define CPU_SYS_2_QSPI_DR15                                              (HV_QSPI_BASE_ADDRESS + 0x09C)

#define CPU_SYS_2_QSPI_DR15_struct                                       rs_cpu_sys_2_qspi_dr15

typedef struct _rs_cpu_sys_2_qspi_dr15  rs_cpu_sys_2_qspi_dr15;
struct _rs_cpu_sys_2_qspi_dr15 {
    unsigned int DR15                                       :32;
};
#define cpu_sys_2_qspi_dr15(val) ((rs_cpu_sys_2_qspi_dr15*)&(val))



#define CPU_SYS_2_QSPI_DR16                                              (HV_QSPI_BASE_ADDRESS + 0x0A0)

#define CPU_SYS_2_QSPI_DR16_struct                                       rs_cpu_sys_2_qspi_dr16

typedef struct _rs_cpu_sys_2_qspi_dr16  rs_cpu_sys_2_qspi_dr16;
struct _rs_cpu_sys_2_qspi_dr16 {
    unsigned int DR16                                       :32;
};
#define cpu_sys_2_qspi_dr16(val) ((rs_cpu_sys_2_qspi_dr16*)&(val))



#define CPU_SYS_2_QSPI_DR17                                              (HV_QSPI_BASE_ADDRESS + 0x0A4)

#define CPU_SYS_2_QSPI_DR17_struct                                       rs_cpu_sys_2_qspi_dr17

typedef struct _rs_cpu_sys_2_qspi_dr17  rs_cpu_sys_2_qspi_dr17;
struct _rs_cpu_sys_2_qspi_dr17 {
    unsigned int DR17                                       :32;
};
#define cpu_sys_2_qspi_dr17(val) ((rs_cpu_sys_2_qspi_dr17*)&(val))



#define CPU_SYS_2_QSPI_DR18                                              (HV_QSPI_BASE_ADDRESS + 0x0A8)

#define CPU_SYS_2_QSPI_DR18_struct                                       rs_cpu_sys_2_qspi_dr18

typedef struct _rs_cpu_sys_2_qspi_dr18  rs_cpu_sys_2_qspi_dr18;
struct _rs_cpu_sys_2_qspi_dr18 {
    unsigned int DR18                                       :32;
};
#define cpu_sys_2_qspi_dr18(val) ((rs_cpu_sys_2_qspi_dr18*)&(val))



#define CPU_SYS_2_QSPI_DR19                                              (HV_QSPI_BASE_ADDRESS + 0x0AC)

#define CPU_SYS_2_QSPI_DR19_struct                                       rs_cpu_sys_2_qspi_dr19

typedef struct _rs_cpu_sys_2_qspi_dr19  rs_cpu_sys_2_qspi_dr19;
struct _rs_cpu_sys_2_qspi_dr19 {
    unsigned int DR19                                       :32;
};
#define cpu_sys_2_qspi_dr19(val) ((rs_cpu_sys_2_qspi_dr19*)&(val))



#define CPU_SYS_2_QSPI_DR20                                              (HV_QSPI_BASE_ADDRESS + 0x0B0)

#define CPU_SYS_2_QSPI_DR20_struct                                       rs_cpu_sys_2_qspi_dr20

typedef struct _rs_cpu_sys_2_qspi_dr20  rs_cpu_sys_2_qspi_dr20;
struct _rs_cpu_sys_2_qspi_dr20 {
    unsigned int DR20                                       :32;
};
#define cpu_sys_2_qspi_dr20(val) ((rs_cpu_sys_2_qspi_dr20*)&(val))



#define CPU_SYS_2_QSPI_DR21                                              (HV_QSPI_BASE_ADDRESS + 0x0B4)

#define CPU_SYS_2_QSPI_DR21_struct                                       rs_cpu_sys_2_qspi_dr21

typedef struct _rs_cpu_sys_2_qspi_dr21  rs_cpu_sys_2_qspi_dr21;
struct _rs_cpu_sys_2_qspi_dr21 {
    unsigned int DR21                                       :32;
};
#define cpu_sys_2_qspi_dr21(val) ((rs_cpu_sys_2_qspi_dr21*)&(val))



#define CPU_SYS_2_QSPI_DR22                                              (HV_QSPI_BASE_ADDRESS + 0x0B8)

#define CPU_SYS_2_QSPI_DR22_struct                                       rs_cpu_sys_2_qspi_dr22

typedef struct _rs_cpu_sys_2_qspi_dr22  rs_cpu_sys_2_qspi_dr22;
struct _rs_cpu_sys_2_qspi_dr22 {
    unsigned int DR22                                       :32;
};
#define cpu_sys_2_qspi_dr22(val) ((rs_cpu_sys_2_qspi_dr22*)&(val))



#define CPU_SYS_2_QSPI_DR23                                              (HV_QSPI_BASE_ADDRESS + 0x0BC)

#define CPU_SYS_2_QSPI_DR23_struct                                       rs_cpu_sys_2_qspi_dr23

typedef struct _rs_cpu_sys_2_qspi_dr23  rs_cpu_sys_2_qspi_dr23;
struct _rs_cpu_sys_2_qspi_dr23 {
    unsigned int DR23                                       :32;
};
#define cpu_sys_2_qspi_dr23(val) ((rs_cpu_sys_2_qspi_dr23*)&(val))



#define CPU_SYS_2_QSPI_DR24                                              (HV_QSPI_BASE_ADDRESS + 0x0C0)

#define CPU_SYS_2_QSPI_DR24_struct                                       rs_cpu_sys_2_qspi_dr24

typedef struct _rs_cpu_sys_2_qspi_dr24  rs_cpu_sys_2_qspi_dr24;
struct _rs_cpu_sys_2_qspi_dr24 {
    unsigned int DR24                                       :32;
};
#define cpu_sys_2_qspi_dr24(val) ((rs_cpu_sys_2_qspi_dr24*)&(val))



#define CPU_SYS_2_QSPI_DR25                                              (HV_QSPI_BASE_ADDRESS + 0x0C4)

#define CPU_SYS_2_QSPI_DR25_struct                                       rs_cpu_sys_2_qspi_dr25

typedef struct _rs_cpu_sys_2_qspi_dr25  rs_cpu_sys_2_qspi_dr25;
struct _rs_cpu_sys_2_qspi_dr25 {
    unsigned int DR25                                       :32;
};
#define cpu_sys_2_qspi_dr25(val) ((rs_cpu_sys_2_qspi_dr25*)&(val))



#define CPU_SYS_2_QSPI_DR26                                              (HV_QSPI_BASE_ADDRESS + 0x0C8)

#define CPU_SYS_2_QSPI_DR26_struct                                       rs_cpu_sys_2_qspi_dr26

typedef struct _rs_cpu_sys_2_qspi_dr26  rs_cpu_sys_2_qspi_dr26;
struct _rs_cpu_sys_2_qspi_dr26 {
    unsigned int DR26                                       :32;
};
#define cpu_sys_2_qspi_dr26(val) ((rs_cpu_sys_2_qspi_dr26*)&(val))



#define CPU_SYS_2_QSPI_DR27                                              (HV_QSPI_BASE_ADDRESS + 0x0CC)

#define CPU_SYS_2_QSPI_DR27_struct                                       rs_cpu_sys_2_qspi_dr27

typedef struct _rs_cpu_sys_2_qspi_dr27  rs_cpu_sys_2_qspi_dr27;
struct _rs_cpu_sys_2_qspi_dr27 {
    unsigned int DR27                                       :32;
};
#define cpu_sys_2_qspi_dr27(val) ((rs_cpu_sys_2_qspi_dr27*)&(val))



#define CPU_SYS_2_QSPI_DR28                                              (HV_QSPI_BASE_ADDRESS + 0x0D0)

#define CPU_SYS_2_QSPI_DR28_struct                                       rs_cpu_sys_2_qspi_dr28

typedef struct _rs_cpu_sys_2_qspi_dr28  rs_cpu_sys_2_qspi_dr28;
struct _rs_cpu_sys_2_qspi_dr28 {
    unsigned int DR28                                       :32;
};
#define cpu_sys_2_qspi_dr28(val) ((rs_cpu_sys_2_qspi_dr28*)&(val))



#define CPU_SYS_2_QSPI_DR29                                              (HV_QSPI_BASE_ADDRESS + 0x0D4)

#define CPU_SYS_2_QSPI_DR29_struct                                       rs_cpu_sys_2_qspi_dr29

typedef struct _rs_cpu_sys_2_qspi_dr29  rs_cpu_sys_2_qspi_dr29;
struct _rs_cpu_sys_2_qspi_dr29 {
    unsigned int DR29                                       :32;
};
#define cpu_sys_2_qspi_dr29(val) ((rs_cpu_sys_2_qspi_dr29*)&(val))



#define CPU_SYS_2_QSPI_DR30                                              (HV_QSPI_BASE_ADDRESS + 0x0D8)

#define CPU_SYS_2_QSPI_DR30_struct                                       rs_cpu_sys_2_qspi_dr30

typedef struct _rs_cpu_sys_2_qspi_dr30  rs_cpu_sys_2_qspi_dr30;
struct _rs_cpu_sys_2_qspi_dr30 {
    unsigned int DR30                                       :32;
};
#define cpu_sys_2_qspi_dr30(val) ((rs_cpu_sys_2_qspi_dr30*)&(val))



#define CPU_SYS_2_QSPI_DR31                                              (HV_QSPI_BASE_ADDRESS + 0x0DC)

#define CPU_SYS_2_QSPI_DR31_struct                                       rs_cpu_sys_2_qspi_dr31

typedef struct _rs_cpu_sys_2_qspi_dr31  rs_cpu_sys_2_qspi_dr31;
struct _rs_cpu_sys_2_qspi_dr31 {
    unsigned int DR31                                       :32;
};
#define cpu_sys_2_qspi_dr31(val) ((rs_cpu_sys_2_qspi_dr31*)&(val))



#define CPU_SYS_2_QSPI_DR32                                              (HV_QSPI_BASE_ADDRESS + 0x0E0)

#define CPU_SYS_2_QSPI_DR32_struct                                       rs_cpu_sys_2_qspi_dr32

typedef struct _rs_cpu_sys_2_qspi_dr32  rs_cpu_sys_2_qspi_dr32;
struct _rs_cpu_sys_2_qspi_dr32 {
    unsigned int DR32                                       :32;
};
#define cpu_sys_2_qspi_dr32(val) ((rs_cpu_sys_2_qspi_dr32*)&(val))



#define CPU_SYS_2_QSPI_DR33                                              (HV_QSPI_BASE_ADDRESS + 0x0E4)

#define CPU_SYS_2_QSPI_DR33_struct                                       rs_cpu_sys_2_qspi_dr33

typedef struct _rs_cpu_sys_2_qspi_dr33  rs_cpu_sys_2_qspi_dr33;
struct _rs_cpu_sys_2_qspi_dr33 {
    unsigned int DR33                                       :32;
};
#define cpu_sys_2_qspi_dr33(val) ((rs_cpu_sys_2_qspi_dr33*)&(val))



#define CPU_SYS_2_QSPI_DR34                                              (HV_QSPI_BASE_ADDRESS + 0x0E8)

#define CPU_SYS_2_QSPI_DR34_struct                                       rs_cpu_sys_2_qspi_dr34

typedef struct _rs_cpu_sys_2_qspi_dr34  rs_cpu_sys_2_qspi_dr34;
struct _rs_cpu_sys_2_qspi_dr34 {
    unsigned int DR34                                       :32;
};
#define cpu_sys_2_qspi_dr34(val) ((rs_cpu_sys_2_qspi_dr34*)&(val))



#define CPU_SYS_2_QSPI_DR35                                              (HV_QSPI_BASE_ADDRESS + 0x0EC)

#define CPU_SYS_2_QSPI_DR35_struct                                       rs_cpu_sys_2_qspi_dr35

typedef struct _rs_cpu_sys_2_qspi_dr35  rs_cpu_sys_2_qspi_dr35;
struct _rs_cpu_sys_2_qspi_dr35 {
    unsigned int DR35                                       :32;
};
#define cpu_sys_2_qspi_dr35(val) ((rs_cpu_sys_2_qspi_dr35*)&(val))



#define CPU_SYS_2_QSPI_RX_SAMPLE_DELAY                                   (HV_QSPI_BASE_ADDRESS + 0x0F0)

#define CPU_SYS_2_QSPI_RX_SAMPLE_DELAY_struct                            rs_cpu_sys_2_qspi_rx_sample_delay

typedef struct _rs_cpu_sys_2_qspi_rx_sample_delay  rs_cpu_sys_2_qspi_rx_sample_delay;
struct _rs_cpu_sys_2_qspi_rx_sample_delay {
    unsigned int RSD                                        : 8;
    unsigned int reserved                                   : 8;
    unsigned int SE                                         : 1;
    unsigned int reserved_1                                 :15;
};
#define cpu_sys_2_qspi_rx_sample_delay(val) ((rs_cpu_sys_2_qspi_rx_sample_delay*)&(val))



#define CPU_SYS_2_QSPI_SPI_CTRLR0                                        (HV_QSPI_BASE_ADDRESS + 0x0F4)

#define CPU_SYS_2_QSPI_SPI_CTRLR0_struct                                 rs_cpu_sys_2_qspi_spi_ctrlr0

typedef struct _rs_cpu_sys_2_qspi_spi_ctrlr0  rs_cpu_sys_2_qspi_spi_ctrlr0;
struct _rs_cpu_sys_2_qspi_spi_ctrlr0 {
    unsigned int TRANS_TYPE                                 : 2;
    unsigned int ADDR_L                                     : 4;
    unsigned int reserved                                   : 1;
    unsigned int XIP_MD_BIT_EN                              : 1;
    unsigned int INST_L                                     : 2;
    unsigned int reserved_1                                 : 1;
    unsigned int WAIT_CYCLES                                : 5;
    unsigned int SPI_DDR_EN                                 : 1;
    unsigned int INST_DDR_EN                                : 1;
    unsigned int SPI_RXDS_EN                                : 1;
    unsigned int XIP_DFS_HC                                 : 1;
    unsigned int XIP_INST_EN                                : 1;
    unsigned int SSIC_XIP_CONT_XFER_EN                      : 1;
    unsigned int reserved_2                                 : 2;
    unsigned int SPI_DM_EN                                  : 1;
    unsigned int SPI_RXDS_SIG_EN                            : 1;
    unsigned int XIP_MBL                                    : 2;
    unsigned int reserved_3                                 : 1;
    unsigned int XIP_PREFETCH_EN                            : 1;
    unsigned int CLK_STRETCH_EN                             : 1;
    unsigned int reserved_4                                 : 1;
};
#define cpu_sys_2_qspi_spi_ctrlr0(val) ((rs_cpu_sys_2_qspi_spi_ctrlr0*)&(val))



#define CPU_SYS_2_QSPI_0F8                                               (HV_QSPI_BASE_ADDRESS + 0x0F8)

#define CPU_SYS_2_QSPI_0F8_struct                                        rs_cpu_sys_2_qspi_0f8

typedef struct _rs_cpu_sys_2_qspi_0f8  rs_cpu_sys_2_qspi_0f8;
struct _rs_cpu_sys_2_qspi_0f8 {
    unsigned int TDE                                        : 8;
    unsigned int RSVD_DDR_DRIVE_EDGE                        :24;
};
#define cpu_sys_2_qspi_0f8(val) ((rs_cpu_sys_2_qspi_0f8*)&(val))



#define CPU_SYS_2_QSPI_XIP_MODE_BITS                                     (HV_QSPI_BASE_ADDRESS + 0x0FC)

#define CPU_SYS_2_QSPI_XIP_MODE_BITS_struct                              rs_cpu_sys_2_qspi_xip_mode_bits

typedef struct _rs_cpu_sys_2_qspi_xip_mode_bits  rs_cpu_sys_2_qspi_xip_mode_bits;
struct _rs_cpu_sys_2_qspi_xip_mode_bits {
    unsigned int XIP_MD_BITS                                :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_2_qspi_xip_mode_bits(val) ((rs_cpu_sys_2_qspi_xip_mode_bits*)&(val))



#define CPU_SYS_2_QSPI_XIP_INCR_INST                                     (HV_QSPI_BASE_ADDRESS + 0x100)

#define CPU_SYS_2_QSPI_XIP_INCR_INST_struct                              rs_cpu_sys_2_qspi_xip_incr_inst

typedef struct _rs_cpu_sys_2_qspi_xip_incr_inst  rs_cpu_sys_2_qspi_xip_incr_inst;
struct _rs_cpu_sys_2_qspi_xip_incr_inst {
    unsigned int INCR_INST                                  :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_2_qspi_xip_incr_inst(val) ((rs_cpu_sys_2_qspi_xip_incr_inst*)&(val))



#define CPU_SYS_2_QSPI_XIP_WRAP_INST                                     (HV_QSPI_BASE_ADDRESS + 0x104)

#define CPU_SYS_2_QSPI_XIP_WRAP_INST_struct                              rs_cpu_sys_2_qspi_xip_wrap_inst

typedef struct _rs_cpu_sys_2_qspi_xip_wrap_inst  rs_cpu_sys_2_qspi_xip_wrap_inst;
struct _rs_cpu_sys_2_qspi_xip_wrap_inst {
    unsigned int WRAP_INST                                  :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_2_qspi_xip_wrap_inst(val) ((rs_cpu_sys_2_qspi_xip_wrap_inst*)&(val))



#define CPU_SYS_2_QSPI_XPI_CTRL                                          (HV_QSPI_BASE_ADDRESS + 0x108)

#define CPU_SYS_2_QSPI_XPI_CTRL_struct                                   rs_cpu_sys_2_qspi_xpi_ctrl

typedef struct _rs_cpu_sys_2_qspi_xpi_ctrl  rs_cpu_sys_2_qspi_xpi_ctrl;
struct _rs_cpu_sys_2_qspi_xpi_ctrl {
    unsigned int FRF                                        : 2;
    unsigned int TRANS_TYPE                                 : 2;
    unsigned int ADDR_L                                     : 4;
    unsigned int reserved                                   : 1;
    unsigned int INST_L                                     : 2;
    unsigned int reserved_1                                 : 1;
    unsigned int MD_BITS_EN                                 : 1;
    unsigned int WAIT_CYCLES                                : 5;
    unsigned int DFS_HC                                     : 1;
    unsigned int DDR_EN                                     : 1;
    unsigned int INST_DDR_EN                                : 1;
    unsigned int RXDS_EN                                    : 1;
    unsigned int INST_EN                                    : 1;
    unsigned int CONT_XFER_EN                               : 1;
    unsigned int XIP_HYPERBUS_EN                            : 1;
    unsigned int RXDS_SIG_EN                                : 1;
    unsigned int XIP_MBL                                    : 2;
    unsigned int reserved_2                                 : 1;
    unsigned int XIP_PREFETCH_EN                            : 1;
    unsigned int reserved_3                                 : 2;
};
#define cpu_sys_2_qspi_xpi_ctrl(val) ((rs_cpu_sys_2_qspi_xpi_ctrl*)&(val))



#define CPU_SYS_2_QSPI_XIP_SER                                           (HV_QSPI_BASE_ADDRESS + 0x10C)

#define CPU_SYS_2_QSPI_XIP_SER_struct                                    rs_cpu_sys_2_qspi_xip_ser

typedef struct _rs_cpu_sys_2_qspi_xip_ser  rs_cpu_sys_2_qspi_xip_ser;
struct _rs_cpu_sys_2_qspi_xip_ser {
    unsigned int SER                                        : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_xip_ser(val) ((rs_cpu_sys_2_qspi_xip_ser*)&(val))



#define CPU_SYS_2_QSPI_XRXOICR                                           (HV_QSPI_BASE_ADDRESS + 0x110)

#define CPU_SYS_2_QSPI_XRXOICR_struct                                    rs_cpu_sys_2_qspi_xrxoicr

typedef struct _rs_cpu_sys_2_qspi_xrxoicr  rs_cpu_sys_2_qspi_xrxoicr;
struct _rs_cpu_sys_2_qspi_xrxoicr {
    unsigned int XRXOICR                                    : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_2_qspi_xrxoicr(val) ((rs_cpu_sys_2_qspi_xrxoicr*)&(val))



#define CPU_SYS_2_QSPI_XIP_CNT_TIME_OUT                                  (HV_QSPI_BASE_ADDRESS + 0x114)

#define CPU_SYS_2_QSPI_XIP_CNT_TIME_OUT_struct                           rs_cpu_sys_2_qspi_xip_cnt_time_out

typedef struct _rs_cpu_sys_2_qspi_xip_cnt_time_out  rs_cpu_sys_2_qspi_xip_cnt_time_out;
struct _rs_cpu_sys_2_qspi_xip_cnt_time_out {
    unsigned int XTOC                                       : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_2_qspi_xip_cnt_time_out(val) ((rs_cpu_sys_2_qspi_xip_cnt_time_out*)&(val))



#endif