#ifndef _HV_PAGE_HT7315_RX_DPLL_01_H_
#define _HV_PAGE_HT7315_RX_DPLL_01_H_

#ifndef HV_RX_DPLL_01_BASE_ADDRESS
    #define HV_RX_DPLL_01_BASE_ADDRESS                                         0x11046900
#endif


#define RX_RX_DPLL_01_00                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x00)

#define RX_RX_DPLL_01_00_struct                                          rs_rx_rx_dpll_01_00

typedef struct _rs_rx_rx_dpll_01_00  rs_rx_rx_dpll_01_00;
struct _rs_rx_rx_dpll_01_00 {
    unsigned int reg_01_rx_dpll_en                          : 1;
    unsigned int reg_01_rx_dpll_dac_en                      : 1;
    unsigned int reg_01_rx_dpll_rstn                        : 1;
    unsigned int reg_01_rx_dpll_div_mode                    : 1;
    unsigned int reg_01_rx_dpll_rnd_mode                    : 1;
    unsigned int reg_01_rx_dpll_test_mode                   : 1;
    unsigned int reg_01_rx_dpll_free_run                    : 1;
    unsigned int reg_01_rx_dpll_overflow_rst_en             : 1;
    unsigned int reg_01_rx_dpll_lock_force                  : 1;
    unsigned int reg_01_rx_dpll_lock_cnt_sel                : 1;
    unsigned int reg_01_rx_dpll_lock_wd_sel                 : 2;
    unsigned int reg_01_rx_dpll_ana_test_sel                : 4;
    unsigned int reg_01_rx_dpll_dummy                       : 8;
    unsigned int reserved                                   : 8;
};
#define rx_rx_dpll_01_00(val) ((rs_rx_rx_dpll_01_00*)&(val))



#define RX_RX_DPLL_01_04                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x04)

#define RX_RX_DPLL_01_04_struct                                          rs_rx_rx_dpll_01_04

typedef struct _rs_rx_rx_dpll_01_04  rs_rx_rx_dpll_01_04;
struct _rs_rx_rx_dpll_01_04 {
    unsigned int reg_01_rx_dpll_dly_ctrl                    : 3;
    unsigned int reg_01_rx_dpll_icp_bias_tune               : 3;
    unsigned int reg_01_rx_dpll_icp_ctrl1                   : 4;
    unsigned int reg_01_rx_dpll_icp_ctrl2                   : 3;
    unsigned int reg_01_rx_dpll_ib5u_sel                    : 1;
    unsigned int reg_01_rx_dpll_lpf_ctrl                    : 4;
    unsigned int reserved                                   : 4;
    unsigned int reg_01_rx_dpll_stb_en                      : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_01_rx_dpll_kvco_ctrl                   : 6;
    unsigned int reg_01_rx_dpll_ckref_sel                   : 2;
};
#define rx_rx_dpll_01_04(val) ((rs_rx_rx_dpll_01_04*)&(val))



#define RX_RX_DPLL_01_08                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x08)

#define RX_RX_DPLL_01_08_struct                                          rs_rx_rx_dpll_01_08

typedef struct _rs_rx_rx_dpll_01_08  rs_rx_rx_dpll_01_08;
struct _rs_rx_rx_dpll_01_08 {
    unsigned int reg_01_rx_dpll_prediv                      : 6;
    unsigned int reg_01_rx_dpll_fbdiv_int                   :10;
    unsigned int reg_01_rx_dpll_fbdiv_frac                  :16;
};
#define rx_rx_dpll_01_08(val) ((rs_rx_rx_dpll_01_08*)&(val))



#define RX_RX_DPLL_01_0C                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x0C)

#define RX_RX_DPLL_01_0C_struct                                          rs_rx_rx_dpll_01_0c

typedef struct _rs_rx_rx_dpll_01_0c  rs_rx_rx_dpll_01_0c;
struct _rs_rx_rx_dpll_01_0c {
    unsigned int reg_01_rx_dpll_postdiv0                    :10;
    unsigned int reg_01_rx_dpll_postdiv1                    :10;
    unsigned int reg_01_rx_dpll_postdiv2                    :10;
    unsigned int reserved                                   : 2;
};
#define rx_rx_dpll_01_0c(val) ((rs_rx_rx_dpll_01_0c*)&(val))



#define RX_RX_DPLL_01_10                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x10)

#define RX_RX_DPLL_01_10_struct                                          rs_rx_rx_dpll_01_10

typedef struct _rs_rx_rx_dpll_01_10  rs_rx_rx_dpll_01_10;
struct _rs_rx_rx_dpll_01_10 {
    unsigned int reg_01_rx_dpll_postdiv0_div2               : 1;
    unsigned int reg_01_rx_dpll_postdiv0_0                  : 6;
    unsigned int reg_01_rx_dpll_postdiv0_1                  : 6;
    unsigned int reg_01_rx_dpll_postdiv_lvds                : 2;
    unsigned int reg_01_rx_dpll_cklvds_al_skew              : 4;
    unsigned int reg_01_rx_dpll_cklvds_ar_skew              : 4;
    unsigned int reg_01_rx_dpll_cklvds_en                   : 1;
    unsigned int reg_01_rx_dpll_cklvds_lr_sel               : 2;
    unsigned int reserved                                   : 6;
};
#define rx_rx_dpll_01_10(val) ((rs_rx_rx_dpll_01_10*)&(val))



#define RX_RX_DPLL_01_20                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x20)

#define RX_RX_DPLL_01_20_struct                                          rs_rx_rx_dpll_01_20

typedef struct _rs_rx_rx_dpll_01_20  rs_rx_rx_dpll_01_20;
struct _rs_rx_rx_dpll_01_20 {
    unsigned int reserved                                   :27;
    unsigned int reg_01_rx_dpll_lockdet_fw_mode             : 1;
    unsigned int reg_01_rx_dpll_lockdet_fw_value            : 1;
    unsigned int reg_01_rx_dpll_lockdet_det_win             : 3;
};
#define rx_rx_dpll_01_20(val) ((rs_rx_rx_dpll_01_20*)&(val))



#define RX_RX_DPLL_01_24                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x24)

#define RX_RX_DPLL_01_24_struct                                          rs_rx_rx_dpll_01_24

typedef struct _rs_rx_rx_dpll_01_24  rs_rx_rx_dpll_01_24;
struct _rs_rx_rx_dpll_01_24 {
    unsigned int reg_01_rx_dpll_lockdet_locked_num          : 4;
    unsigned int reg_01_rx_dpll_lockdet_unlocked_num        : 4;
    unsigned int reg_01_rx_dpll_lockdet_lock_err_range      : 8;
    unsigned int reg_01_rx_dpll_lockdet_fast_err_range      : 8;
    unsigned int reg_01_rx_dpll_lockdet_no_clk_th           : 8;
};
#define rx_rx_dpll_01_24(val) ((rs_rx_rx_dpll_01_24*)&(val))



#define RX_RX_DPLL_01_38                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x38)

#define RX_RX_DPLL_01_38_struct                                          rs_rx_rx_dpll_01_38

typedef struct _rs_rx_rx_dpll_01_38  rs_rx_rx_dpll_01_38;
struct _rs_rx_rx_dpll_01_38 {
    unsigned int reg_01_rx_dpll_clkdet_en                   : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_rx_dpll_clkdet_abn_mode             : 4;
    unsigned int reg_01_rx_dpll_clkdet_window_size          :16;
    unsigned int reg_01_rx_dpll_clkdet_stable_th            : 8;
};
#define rx_rx_dpll_01_38(val) ((rs_rx_rx_dpll_01_38*)&(val))



#define RX_RX_DPLL_01_3C                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0x3C)

#define RX_RX_DPLL_01_3C_struct                                          rs_rx_rx_dpll_01_3c

typedef struct _rs_rx_rx_dpll_01_3c  rs_rx_rx_dpll_01_3c;
struct _rs_rx_rx_dpll_01_3c {
    unsigned int reg_01_rx_dpll_clkdet_low_th               :16;
    unsigned int reg_01_rx_dpll_clkdet_high_th              :16;
};
#define rx_rx_dpll_01_3c(val) ((rs_rx_rx_dpll_01_3c*)&(val))



#define RX_RX_DPLL_01_B0                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0xB0)

#define RX_RX_DPLL_01_B0_struct                                          rs_rx_rx_dpll_01_b0

typedef struct _rs_rx_rx_dpll_01_b0  rs_rx_rx_dpll_01_b0;
struct _rs_rx_rx_dpll_01_b0 {
    unsigned int regr_01_rx_dpll_lockdet_ref_int_value      :16;
    unsigned int regr_01_rx_dpll_lockdet_vco_int_value      :16;
};
#define rx_rx_dpll_01_b0(val) ((rs_rx_rx_dpll_01_b0*)&(val))



#define RX_RX_DPLL_01_B4                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0xB4)

#define RX_RX_DPLL_01_B4_struct                                          rs_rx_rx_dpll_01_b4

typedef struct _rs_rx_rx_dpll_01_b4  rs_rx_rx_dpll_01_b4;
struct _rs_rx_rx_dpll_01_b4 {
    unsigned int regr_01_rx_dpll_lockdet_ref_clk_fast       : 1;
    unsigned int regr_01_rx_dpll_lockdet_vco_clk_fast       : 1;
    unsigned int regr_01_rx_dpll_lockdet_ref_no_clk         : 1;
    unsigned int regr_01_rx_dpll_lockdet_vco_no_clk         : 1;
    unsigned int regr_01_rx_dpll_lockdet_pll_lock           : 1;
    unsigned int reserved                                   :27;
};
#define rx_rx_dpll_01_b4(val) ((rs_rx_rx_dpll_01_b4*)&(val))



#define RX_RX_DPLL_01_B8                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0xB8)

#define RX_RX_DPLL_01_B8_struct                                          rs_rx_rx_dpll_01_b8

typedef struct _rs_rx_rx_dpll_01_b8  rs_rx_rx_dpll_01_b8;
struct _rs_rx_rx_dpll_01_b8 {
    unsigned int regr_01_rx_dpll_clkdet_freq_cnt            :32;
};
#define rx_rx_dpll_01_b8(val) ((rs_rx_rx_dpll_01_b8*)&(val))



#define RX_RX_DPLL_01_BC                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0xBC)

#define RX_RX_DPLL_01_BC_struct                                          rs_rx_rx_dpll_01_bc

typedef struct _rs_rx_rx_dpll_01_bc  rs_rx_rx_dpll_01_bc;
struct _rs_rx_rx_dpll_01_bc {
    unsigned int regr_01_rx_dpll_clkdet_abn_nck             : 1;
    unsigned int regr_01_rx_dpll_clkdet_abn_low             : 1;
    unsigned int regr_01_rx_dpll_clkdet_abn_high            : 1;
    unsigned int regr_01_rx_dpll_clkdet_abn_nstb            : 1;
    unsigned int reserved                                   :28;
};
#define rx_rx_dpll_01_bc(val) ((rs_rx_rx_dpll_01_bc*)&(val))



#define RX_RX_DPLL_01_E0                                                 (HV_RX_DPLL_01_BASE_ADDRESS + 0xE0)

#define RX_RX_DPLL_01_E0_struct                                          rs_rx_rx_dpll_01_e0

typedef struct _rs_rx_rx_dpll_01_e0  rs_rx_rx_dpll_01_e0;
struct _rs_rx_rx_dpll_01_e0 {
    unsigned int regr_01_rx_dpll_dbg_test                   :10;
    unsigned int regr_01_rx_dpll_dbg_lock_cnt_en            : 1;
    unsigned int regr_01_rx_dpll_dbg_lock_flag              : 1;
    unsigned int regr_01_rx_dpll_dbg_overflow_flag          : 1;
    unsigned int regr_01_rx_dpll_dbg_phase_error_flag       : 1;
    unsigned int reserved                                   :18;
};
#define rx_rx_dpll_01_e0(val) ((rs_rx_rx_dpll_01_e0*)&(val))



#endif