/**
 * @file hv_pm51_driver_ADC.c
 * @brief 
 * @details 
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20230301
 * @copyright Copyright(c),2023-3, Hiview Software. All rights reserved.
 * @par History: 
 * <table>
 * <tr><th>author                     <th>date           <th>description
 * <tr><td>HiView SoC Software Team   <td>20230301       <td>Create and first Version.
 * </table>
**/

#include "hv_pm51_Base.h"
#include "hv_pm51_Reg.h"
#include "hv_pm51_Setting.h"
#include "hv_pm51_driver_Reg.h"
#include "hv_pm51_driver_UART.h"
#include "hv_pm51_driver_ADC.h"

#if ADC_ENABLE

static void PM51_Adc_Phy_Init(AdcNum enAdcNum)
{
    if(enAdcNum == E_ADC0)
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_pd_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_pd_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_pd_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_puls_mod_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_puls_mod_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_puls_mod_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_bridge_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_bridge_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_bridge_BITEND, 0x8);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_ib_comp_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_ib_comp_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_ib_comp_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_odmode_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_odmode_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_odmode_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_clk_div_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_clk_div_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_clk_div_BITEND, 0x3);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_vref_sel_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_vref_sel_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_vref_sel_BITEND, 0x0);
    }
    else
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_pd_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_pd_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_pd_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_puls_mod_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_puls_mod_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_puls_mod_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_bridge_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_bridge_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_bridge_BITEND, 0x8);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_ib_comp_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_ib_comp_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_ib_comp_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_odmode_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_odmode_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_odmode_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_clk_div_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_clk_div_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_clk_div_BITEND, 0x3);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_vref_sel_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_vref_sel_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_vref_sel_BITEND, 0x0);
    }
}

void Hv_PM51_Adc_Init(AdcNum enAdcNum, iBOOL bIsUseInterrupt)
{
    xULONG32 ulRData32;
    
    if(enAdcNum == E_ADC0)
    {
        PM51_Adc_Phy_Init(enAdcNum);
        
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_adc0_clk_en_ADDR,
                          HS_Standby__standby_mcu_reg__reg_adc0_clk_en_BITSTART,
                          HS_Standby__standby_mcu_reg__reg_adc0_clk_en_BITEND, 1);/* reg_adc0_clk_en */

        if(bIsUseInterrupt == HV_TRUE)
        {
            ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR);
            Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR,
                          (ulRData32 | BIT_4 | BIT_20));  /* reg_wake_int_edge_p, reg_wake_int_edge_n */

            /* clear adc0 wake int status */
            Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_clr_ADDR, 4, 4, 1);

            /* reg_wake_int_en, adc0 */
            ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR); 
            Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR, 
                          (ulRData32 | BIT_20));
        }
    }
    else
    {
        PM51_Adc_Phy_Init(enAdcNum);
        
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_adc1_clk_en_ADDR, 
                          HS_Standby__standby_mcu_reg__reg_adc1_clk_en_BITSTART,
                          HS_Standby__standby_mcu_reg__reg_adc1_clk_en_BITEND, 1);/* reg_adc1_clk_en */

        if(bIsUseInterrupt == HV_TRUE)
        {
            
            ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR);
            Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR, 
                          (ulRData32 | BIT_5 | BIT_21));

            /* clear adc1 wake int status */
            Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_clr_ADDR, 5, 5, 1);

            /* reg_wake_int_en, adc1 */
            ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR);
            Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR, 
                          (ulRData32 | BIT_21));
        }
    }
}

void Hv_PM51_Adc_Enable(AdcNum enAdcNum)
{
    if(enAdcNum == E_ADC0)
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_en_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc0_en_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_en_BITEND, 1);/* reg_adc0_en */
    }
    else
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_en_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc1_en_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_en_BITEND, 1);/* reg_adc1_en */
    }
}

void Hv_PM51_Adc_Disable(AdcNum enAdcNum)
{
    if(enAdcNum == E_ADC0)
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_en_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc0_en_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc0_en_BITEND, 0);/* reg_adc0_en */
    }
    else
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_en_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc1_en_BITSTART,
                          HS_Standby__standby_peri_reg__reg_adc1_en_BITEND, 0);/* reg_adc1_en */
    }
}

void Hv_PM51_Adc_SetTheshold(AdcNum enAdcNum, xUSHORT16 usLow, xUSHORT16 usHigh)
{

    if(usLow > usHigh)
    {
        return;
    }

    if(enAdcNum == E_ADC0)
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_lth_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc0_lth_BITSTART, 
                          HS_Standby__standby_peri_reg__reg_adc0_lth_BITEND, (usLow & 0xFFF));/* reg_adc0_lth */
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_hth_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc0_hth_BITSTART, 
                          HS_Standby__standby_peri_reg__reg_adc0_hth_BITEND, (usHigh & 0xFFF));/* reg_adc0_hth */
    }
    else
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_lth_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc1_lth_BITSTART, 
                          HS_Standby__standby_peri_reg__reg_adc1_lth_BITEND, (usLow & 0xFFF));/* reg_adc1_lth */
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_hth_ADDR, 
                          HS_Standby__standby_peri_reg__reg_adc1_hth_BITSTART, 
                          HS_Standby__standby_peri_reg__reg_adc1_hth_BITEND, (usHigh & 0xFFF));/* reg_adc1_hth */
    }
}

ULONG32 Hv_PM51_Adc_ReadVal(AdcNum enAdcNum)
{
    xULONG32 ulAdcVal;

    if(enAdcNum == E_ADC0)
    {
        ulAdcVal = Hv_PM51_Reg_ReadMask(HS_Standby__standby_peri_reg__regr_adc0_data_ADDR,
                                     HS_Standby__standby_peri_reg__regr_adc0_data_BITSTART,
                                     HS_Standby__standby_peri_reg__regr_adc0_data_BITEND);
    }
    else
    {
        ulAdcVal = Hv_PM51_Reg_ReadMask(HS_Standby__standby_peri_reg__regr_adc1_data_ADDR,
                                     HS_Standby__standby_peri_reg__regr_adc1_data_BITSTART,
                                     HS_Standby__standby_peri_reg__regr_adc1_data_BITEND);
    }

    return ulAdcVal;
}

void Hv_PM51_Adc_SetFilterNum(AdcNum enAdcNum, xULONG32 ulFilterNum)
{
    if(enAdcNum == E_ADC0)
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc0_filter_num_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc0_filter_num_BITSTART, 
                          HS_Standby__standby_peri_reg__reg_adc0_filter_num_BITEND, ulFilterNum);
    }
    else
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_adc1_filter_num_ADDR,
                          HS_Standby__standby_peri_reg__reg_adc1_filter_num_BITSTART, 
                          HS_Standby__standby_peri_reg__reg_adc1_filter_num_BITEND, ulFilterNum);
    }
}

#endif
