#ifndef _HV_PAGE_HT7315_I2C0_H_
#define _HV_PAGE_HT7315_I2C0_H_

#ifndef HV_I2C0_BASE_ADDRESS
    #define HV_I2C0_BASE_ADDRESS                                         0x11080000
#endif


#define CPU_SYS_I2C0_IC_CON                                              (HV_I2C0_BASE_ADDRESS + 0x00)

#define CPU_SYS_I2C0_IC_CON_struct                                       rs_cpu_sys_i2c0_ic_con

typedef struct _rs_cpu_sys_i2c0_ic_con  rs_cpu_sys_i2c0_ic_con;
struct _rs_cpu_sys_i2c0_ic_con {
    unsigned int MASTER_MODE                                : 1;
    unsigned int SPEED                                      : 2;
    unsigned int IC_10BITADDR_SLAVE                         : 1;
    unsigned int IC_10BITADDR_MASTER                        : 1;
    unsigned int IC_RESTART_EN                              : 1;
    unsigned int IC_SLAVE_DISABLE                           : 1;
    unsigned int STOP_DET_IFADDRESSED                       : 1;
    unsigned int TX_EMPTY_CTRL                              : 1;
    unsigned int RX_FIFO_FULL_HLD_CTRL                      : 1;
    unsigned int STOP_DET_IF_MASTER_ACTIVE                  : 1;
    unsigned int BUS_CLEAR_FEATURE_CTRL                     : 1;
    unsigned int reserved                                   :20;
};
#define cpu_sys_i2c0_ic_con(val) ((rs_cpu_sys_i2c0_ic_con*)&(val))



#define CPU_SYS_I2C0_IC_TAR                                              (HV_I2C0_BASE_ADDRESS + 0x04)

#define CPU_SYS_I2C0_IC_TAR_struct                                       rs_cpu_sys_i2c0_ic_tar

typedef struct _rs_cpu_sys_i2c0_ic_tar  rs_cpu_sys_i2c0_ic_tar;
struct _rs_cpu_sys_i2c0_ic_tar {
    unsigned int IC_TAR                                     :10;
    unsigned int GC_OR_START                                : 1;
    unsigned int SPECIAL                                    : 1;
    unsigned int IC_10BITADDR_MASTER                        : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_i2c0_ic_tar(val) ((rs_cpu_sys_i2c0_ic_tar*)&(val))



#define CPU_SYS_I2C0_IC_SAR                                              (HV_I2C0_BASE_ADDRESS + 0x08)

#define CPU_SYS_I2C0_IC_SAR_struct                                       rs_cpu_sys_i2c0_ic_sar

typedef struct _rs_cpu_sys_i2c0_ic_sar  rs_cpu_sys_i2c0_ic_sar;
struct _rs_cpu_sys_i2c0_ic_sar {
    unsigned int IC_SAR                                     :10;
    unsigned int reserved                                   :22;
};
#define cpu_sys_i2c0_ic_sar(val) ((rs_cpu_sys_i2c0_ic_sar*)&(val))



#define CPU_SYS_I2C0_IC_HS_MADDR                                         (HV_I2C0_BASE_ADDRESS + 0x0C)

#define CPU_SYS_I2C0_IC_HS_MADDR_struct                                  rs_cpu_sys_i2c0_ic_hs_maddr

typedef struct _rs_cpu_sys_i2c0_ic_hs_maddr  rs_cpu_sys_i2c0_ic_hs_maddr;
struct _rs_cpu_sys_i2c0_ic_hs_maddr {
    unsigned int IC_HS_MAR                                  : 3;
    unsigned int reserved                                   :29;
};
#define cpu_sys_i2c0_ic_hs_maddr(val) ((rs_cpu_sys_i2c0_ic_hs_maddr*)&(val))



#define CPU_SYS_I2C0_IC_DATA_CMD                                         (HV_I2C0_BASE_ADDRESS + 0x10)

#define CPU_SYS_I2C0_IC_DATA_CMD_struct                                  rs_cpu_sys_i2c0_ic_data_cmd

typedef struct _rs_cpu_sys_i2c0_ic_data_cmd  rs_cpu_sys_i2c0_ic_data_cmd;
struct _rs_cpu_sys_i2c0_ic_data_cmd {
    unsigned int DAT                                        : 8;
    unsigned int CMD                                        : 1;
    unsigned int STOP                                       : 1;
    unsigned int RESTART                                    : 1;
    unsigned int FIRST_DATA_BYTE                            : 1;
    unsigned int reserved                                   :20;
};
#define cpu_sys_i2c0_ic_data_cmd(val) ((rs_cpu_sys_i2c0_ic_data_cmd*)&(val))



#define CPU_SYS_I2C0_IC_SS_SCL_HCNT                                      (HV_I2C0_BASE_ADDRESS + 0x14)

#define CPU_SYS_I2C0_IC_SS_SCL_HCNT_struct                               rs_cpu_sys_i2c0_ic_ss_scl_hcnt

typedef struct _rs_cpu_sys_i2c0_ic_ss_scl_hcnt  rs_cpu_sys_i2c0_ic_ss_scl_hcnt;
struct _rs_cpu_sys_i2c0_ic_ss_scl_hcnt {
    unsigned int IC_SS_SCL_HCNT                             :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_i2c0_ic_ss_scl_hcnt(val) ((rs_cpu_sys_i2c0_ic_ss_scl_hcnt*)&(val))



#define CPU_SYS_I2C0_IC_SS_SCL_LCNT                                      (HV_I2C0_BASE_ADDRESS + 0x18)

#define CPU_SYS_I2C0_IC_SS_SCL_LCNT_struct                               rs_cpu_sys_i2c0_ic_ss_scl_lcnt

typedef struct _rs_cpu_sys_i2c0_ic_ss_scl_lcnt  rs_cpu_sys_i2c0_ic_ss_scl_lcnt;
struct _rs_cpu_sys_i2c0_ic_ss_scl_lcnt {
    unsigned int IC_SS_SCL_LCNT                             :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_i2c0_ic_ss_scl_lcnt(val) ((rs_cpu_sys_i2c0_ic_ss_scl_lcnt*)&(val))



#define CPU_SYS_I2C0_IC_FS_SCL_HCNT                                      (HV_I2C0_BASE_ADDRESS + 0x1C)

#define CPU_SYS_I2C0_IC_FS_SCL_HCNT_struct                               rs_cpu_sys_i2c0_ic_fs_scl_hcnt

typedef struct _rs_cpu_sys_i2c0_ic_fs_scl_hcnt  rs_cpu_sys_i2c0_ic_fs_scl_hcnt;
struct _rs_cpu_sys_i2c0_ic_fs_scl_hcnt {
    unsigned int IC_FS_SCL_HCNT                             :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_i2c0_ic_fs_scl_hcnt(val) ((rs_cpu_sys_i2c0_ic_fs_scl_hcnt*)&(val))



#define CPU_SYS_I2C0_IC_FS_SCL_LCNT                                      (HV_I2C0_BASE_ADDRESS + 0x20)

#define CPU_SYS_I2C0_IC_FS_SCL_LCNT_struct                               rs_cpu_sys_i2c0_ic_fs_scl_lcnt

typedef struct _rs_cpu_sys_i2c0_ic_fs_scl_lcnt  rs_cpu_sys_i2c0_ic_fs_scl_lcnt;
struct _rs_cpu_sys_i2c0_ic_fs_scl_lcnt {
    unsigned int IC_FS_SCL_LCNT                             :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_i2c0_ic_fs_scl_lcnt(val) ((rs_cpu_sys_i2c0_ic_fs_scl_lcnt*)&(val))



#define CPU_SYS_I2C0_IC_INTR_STAT                                        (HV_I2C0_BASE_ADDRESS + 0x2C)

#define CPU_SYS_I2C0_IC_INTR_STAT_struct                                 rs_cpu_sys_i2c0_ic_intr_stat

typedef struct _rs_cpu_sys_i2c0_ic_intr_stat  rs_cpu_sys_i2c0_ic_intr_stat;
struct _rs_cpu_sys_i2c0_ic_intr_stat {
    unsigned int R_RX_UNDER                                 : 1;
    unsigned int R_RX_OVER                                  : 1;
    unsigned int R_RX_FULL                                  : 1;
    unsigned int R_TX_OVER                                  : 1;
    unsigned int R_TX_EMPTY                                 : 1;
    unsigned int R_RD_REQ                                   : 1;
    unsigned int R_TX_ABRT                                  : 1;
    unsigned int R_RX_DONE                                  : 1;
    unsigned int R_ACTIVITY                                 : 1;
    unsigned int R_STOP_DET                                 : 1;
    unsigned int R_START_DET                                : 1;
    unsigned int R_GEN_CALL                                 : 1;
    unsigned int R_RESTART_DET                              : 1;
    unsigned int R_MASTER_ON_HOLD                           : 1;
    unsigned int R_SCL_STUCK_AT_LOW                         : 1;
    unsigned int reserved                                   :17;
};
#define cpu_sys_i2c0_ic_intr_stat(val) ((rs_cpu_sys_i2c0_ic_intr_stat*)&(val))



#define CPU_SYS_I2C0_IC_INTR_MASK                                        (HV_I2C0_BASE_ADDRESS + 0x30)

#define CPU_SYS_I2C0_IC_INTR_MASK_struct                                 rs_cpu_sys_i2c0_ic_intr_mask

typedef struct _rs_cpu_sys_i2c0_ic_intr_mask  rs_cpu_sys_i2c0_ic_intr_mask;
struct _rs_cpu_sys_i2c0_ic_intr_mask {
    unsigned int M_RX_UNDER                                 : 1;
    unsigned int M_RX_OVER                                  : 1;
    unsigned int M_RX_FULL                                  : 1;
    unsigned int M_TX_OVER                                  : 1;
    unsigned int M_TX_EMPTY                                 : 1;
    unsigned int M_RD_REQ                                   : 1;
    unsigned int M_TX_ABRT                                  : 1;
    unsigned int M_RX_DONE                                  : 1;
    unsigned int M_ACTIVITY                                 : 1;
    unsigned int M_STOP_DET                                 : 1;
    unsigned int M_START_DET                                : 1;
    unsigned int M_GEN_CALL                                 : 1;
    unsigned int M_RESTART_DET                              : 1;
    unsigned int M_MASTER_ON_HOLD                           : 1;
    unsigned int M_SCL_STUCK_AT_LOW                         : 1;
    unsigned int reserved                                   :17;
};
#define cpu_sys_i2c0_ic_intr_mask(val) ((rs_cpu_sys_i2c0_ic_intr_mask*)&(val))



#define CPU_SYS_I2C0_IC_RAW_INTR_STAT                                    (HV_I2C0_BASE_ADDRESS + 0x34)

#define CPU_SYS_I2C0_IC_RAW_INTR_STAT_struct                             rs_cpu_sys_i2c0_ic_raw_intr_stat

typedef struct _rs_cpu_sys_i2c0_ic_raw_intr_stat  rs_cpu_sys_i2c0_ic_raw_intr_stat;
struct _rs_cpu_sys_i2c0_ic_raw_intr_stat {
    unsigned int RX_UNDER                                   : 1;
    unsigned int RX_OVER                                    : 1;
    unsigned int RX_FULL                                    : 1;
    unsigned int TX_OVER                                    : 1;
    unsigned int TX_EMPTY                                   : 1;
    unsigned int RD_REQ                                     : 1;
    unsigned int TX_ABRT                                    : 1;
    unsigned int RX_DONE                                    : 1;
    unsigned int ACTIVITY                                   : 1;
    unsigned int STOP_DET                                   : 1;
    unsigned int START_DET                                  : 1;
    unsigned int GEN_CALL                                   : 1;
    unsigned int RESTART_DET                                : 1;
    unsigned int MASTER_ON_HOLD                             : 1;
    unsigned int SCL_STUCK_AT_LOW                           : 1;
    unsigned int reserved                                   :17;
};
#define cpu_sys_i2c0_ic_raw_intr_stat(val) ((rs_cpu_sys_i2c0_ic_raw_intr_stat*)&(val))



#define CPU_SYS_I2C0_IC_RX_TL                                            (HV_I2C0_BASE_ADDRESS + 0x38)

#define CPU_SYS_I2C0_IC_RX_TL_struct                                     rs_cpu_sys_i2c0_ic_rx_tl

typedef struct _rs_cpu_sys_i2c0_ic_rx_tl  rs_cpu_sys_i2c0_ic_rx_tl;
struct _rs_cpu_sys_i2c0_ic_rx_tl {
    unsigned int RX_TL                                      : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_i2c0_ic_rx_tl(val) ((rs_cpu_sys_i2c0_ic_rx_tl*)&(val))



#define CPU_SYS_I2C0_IC_TX_TL                                            (HV_I2C0_BASE_ADDRESS + 0x3C)

#define CPU_SYS_I2C0_IC_TX_TL_struct                                     rs_cpu_sys_i2c0_ic_tx_tl

typedef struct _rs_cpu_sys_i2c0_ic_tx_tl  rs_cpu_sys_i2c0_ic_tx_tl;
struct _rs_cpu_sys_i2c0_ic_tx_tl {
    unsigned int TX_TL                                      : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_i2c0_ic_tx_tl(val) ((rs_cpu_sys_i2c0_ic_tx_tl*)&(val))



#define CPU_SYS_I2C0_IC_CLR_INT                                          (HV_I2C0_BASE_ADDRESS + 0x40)

#define CPU_SYS_I2C0_IC_CLR_INT_struct                                   rs_cpu_sys_i2c0_ic_clr_int

typedef struct _rs_cpu_sys_i2c0_ic_clr_int  rs_cpu_sys_i2c0_ic_clr_int;
struct _rs_cpu_sys_i2c0_ic_clr_int {
    unsigned int CLR_INTR                                   : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_int(val) ((rs_cpu_sys_i2c0_ic_clr_int*)&(val))



#define CPU_SYS_I2C0_CLR_RX_UNDER                                        (HV_I2C0_BASE_ADDRESS + 0x44)

#define CPU_SYS_I2C0_CLR_RX_UNDER_struct                                 rs_cpu_sys_i2c0_clr_rx_under

typedef struct _rs_cpu_sys_i2c0_clr_rx_under  rs_cpu_sys_i2c0_clr_rx_under;
struct _rs_cpu_sys_i2c0_clr_rx_under {
    unsigned int CLR_RX_UNDER                               : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_clr_rx_under(val) ((rs_cpu_sys_i2c0_clr_rx_under*)&(val))



#define CPU_SYS_I2C0_IC_CLR_RX_OVER                                      (HV_I2C0_BASE_ADDRESS + 0x48)

#define CPU_SYS_I2C0_IC_CLR_RX_OVER_struct                               rs_cpu_sys_i2c0_ic_clr_rx_over

typedef struct _rs_cpu_sys_i2c0_ic_clr_rx_over  rs_cpu_sys_i2c0_ic_clr_rx_over;
struct _rs_cpu_sys_i2c0_ic_clr_rx_over {
    unsigned int IC_CLR_RX_OVER                             : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_rx_over(val) ((rs_cpu_sys_i2c0_ic_clr_rx_over*)&(val))



#define CPU_SYS_I2C0_IC_CLR_TX_OVER                                      (HV_I2C0_BASE_ADDRESS + 0x4C)

#define CPU_SYS_I2C0_IC_CLR_TX_OVER_struct                               rs_cpu_sys_i2c0_ic_clr_tx_over

typedef struct _rs_cpu_sys_i2c0_ic_clr_tx_over  rs_cpu_sys_i2c0_ic_clr_tx_over;
struct _rs_cpu_sys_i2c0_ic_clr_tx_over {
    unsigned int IC_CLR_TX_OVER                             : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_tx_over(val) ((rs_cpu_sys_i2c0_ic_clr_tx_over*)&(val))



#define CPU_SYS_I2C0_IC_CLR_RD_REQ                                       (HV_I2C0_BASE_ADDRESS + 0x50)

#define CPU_SYS_I2C0_IC_CLR_RD_REQ_struct                                rs_cpu_sys_i2c0_ic_clr_rd_req

typedef struct _rs_cpu_sys_i2c0_ic_clr_rd_req  rs_cpu_sys_i2c0_ic_clr_rd_req;
struct _rs_cpu_sys_i2c0_ic_clr_rd_req {
    unsigned int IC_CLR_RD_REQ                              : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_rd_req(val) ((rs_cpu_sys_i2c0_ic_clr_rd_req*)&(val))



#define CPU_SYS_I2C0_IC_CLR_TX_ABRT                                      (HV_I2C0_BASE_ADDRESS + 0x54)

#define CPU_SYS_I2C0_IC_CLR_TX_ABRT_struct                               rs_cpu_sys_i2c0_ic_clr_tx_abrt

typedef struct _rs_cpu_sys_i2c0_ic_clr_tx_abrt  rs_cpu_sys_i2c0_ic_clr_tx_abrt;
struct _rs_cpu_sys_i2c0_ic_clr_tx_abrt {
    unsigned int IC_CLR_TX_ABRT                             : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_tx_abrt(val) ((rs_cpu_sys_i2c0_ic_clr_tx_abrt*)&(val))



#define CPU_SYS_I2C0_IC_CLR_RX_DONE                                      (HV_I2C0_BASE_ADDRESS + 0x58)

#define CPU_SYS_I2C0_IC_CLR_RX_DONE_struct                               rs_cpu_sys_i2c0_ic_clr_rx_done

typedef struct _rs_cpu_sys_i2c0_ic_clr_rx_done  rs_cpu_sys_i2c0_ic_clr_rx_done;
struct _rs_cpu_sys_i2c0_ic_clr_rx_done {
    unsigned int IC_CLR_RX_DONE                             : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_rx_done(val) ((rs_cpu_sys_i2c0_ic_clr_rx_done*)&(val))



#define CPU_SYS_I2C0_IC_CLR_ACTIVITY                                     (HV_I2C0_BASE_ADDRESS + 0x5C)

#define CPU_SYS_I2C0_IC_CLR_ACTIVITY_struct                              rs_cpu_sys_i2c0_ic_clr_activity

typedef struct _rs_cpu_sys_i2c0_ic_clr_activity  rs_cpu_sys_i2c0_ic_clr_activity;
struct _rs_cpu_sys_i2c0_ic_clr_activity {
    unsigned int IC_CLR_ACTIVITY                            : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_activity(val) ((rs_cpu_sys_i2c0_ic_clr_activity*)&(val))



#define CPU_SYS_I2C0_IC_CLR_STOP_DET                                     (HV_I2C0_BASE_ADDRESS + 0x60)

#define CPU_SYS_I2C0_IC_CLR_STOP_DET_struct                              rs_cpu_sys_i2c0_ic_clr_stop_det

typedef struct _rs_cpu_sys_i2c0_ic_clr_stop_det  rs_cpu_sys_i2c0_ic_clr_stop_det;
struct _rs_cpu_sys_i2c0_ic_clr_stop_det {
    unsigned int IC_CLR_STOP_DET                            : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_stop_det(val) ((rs_cpu_sys_i2c0_ic_clr_stop_det*)&(val))



#define CPU_SYS_I2C0_IC_CLR_START_DET                                    (HV_I2C0_BASE_ADDRESS + 0x64)

#define CPU_SYS_I2C0_IC_CLR_START_DET_struct                             rs_cpu_sys_i2c0_ic_clr_start_det

typedef struct _rs_cpu_sys_i2c0_ic_clr_start_det  rs_cpu_sys_i2c0_ic_clr_start_det;
struct _rs_cpu_sys_i2c0_ic_clr_start_det {
    unsigned int IC_CLR_START_DET                           : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_start_det(val) ((rs_cpu_sys_i2c0_ic_clr_start_det*)&(val))



#define CPU_SYS_I2C0_IC_CLR_GEN_CALL                                     (HV_I2C0_BASE_ADDRESS + 0x68)

#define CPU_SYS_I2C0_IC_CLR_GEN_CALL_struct                              rs_cpu_sys_i2c0_ic_clr_gen_call

typedef struct _rs_cpu_sys_i2c0_ic_clr_gen_call  rs_cpu_sys_i2c0_ic_clr_gen_call;
struct _rs_cpu_sys_i2c0_ic_clr_gen_call {
    unsigned int IC_CLR_GEN_CALL                            : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_gen_call(val) ((rs_cpu_sys_i2c0_ic_clr_gen_call*)&(val))



#define CPU_SYS_I2C0_IC_ENABLE                                           (HV_I2C0_BASE_ADDRESS + 0x6C)

#define CPU_SYS_I2C0_IC_ENABLE_struct                                    rs_cpu_sys_i2c0_ic_enable

typedef struct _rs_cpu_sys_i2c0_ic_enable  rs_cpu_sys_i2c0_ic_enable;
struct _rs_cpu_sys_i2c0_ic_enable {
    unsigned int ENABLE                                     : 1;
    unsigned int ABORT                                      : 1;
    unsigned int TX_CMD_BLOCK                               : 1;
    unsigned int SDA_STUCK_RECOVERY_ENABLE                  : 1;
    unsigned int reserved                                   :28;
};
#define cpu_sys_i2c0_ic_enable(val) ((rs_cpu_sys_i2c0_ic_enable*)&(val))



#define CPU_SYS_I2C0_IC_STATUS                                           (HV_I2C0_BASE_ADDRESS + 0x70)

#define CPU_SYS_I2C0_IC_STATUS_struct                                    rs_cpu_sys_i2c0_ic_status

typedef struct _rs_cpu_sys_i2c0_ic_status  rs_cpu_sys_i2c0_ic_status;
struct _rs_cpu_sys_i2c0_ic_status {
    unsigned int ACTIVITY                                   : 1;
    unsigned int TFNF                                       : 1;
    unsigned int TFE                                        : 1;
    unsigned int RFNE                                       : 1;
    unsigned int RFF                                        : 1;
    unsigned int MST_ACTIVITY                               : 1;
    unsigned int SLV_ACTIVITY                               : 1;
    unsigned int MST_HOLD_TX_FIFO_EMPTY                     : 1;
    unsigned int MST_HOLD_RX_FIFO_FULL                      : 1;
    unsigned int SLV_HOLD_TX_FIFO_EMPTY                     : 1;
    unsigned int SLV_HOLD_RX_FIFO_FULL                      : 1;
    unsigned int SDA_STUCK_NOT_RECOVERED                    : 1;
    unsigned int reserved                                   :20;
};
#define cpu_sys_i2c0_ic_status(val) ((rs_cpu_sys_i2c0_ic_status*)&(val))



#define CPU_SYS_I2C0_TXFLR                                               (HV_I2C0_BASE_ADDRESS + 0x74)

#define CPU_SYS_I2C0_TXFLR_struct                                        rs_cpu_sys_i2c0_txflr

typedef struct _rs_cpu_sys_i2c0_txflr  rs_cpu_sys_i2c0_txflr;
struct _rs_cpu_sys_i2c0_txflr {
    unsigned int TXFLR                                      : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_i2c0_txflr(val) ((rs_cpu_sys_i2c0_txflr*)&(val))



#define CPU_SYS_I2C0_RXFLR                                               (HV_I2C0_BASE_ADDRESS + 0x78)

#define CPU_SYS_I2C0_RXFLR_struct                                        rs_cpu_sys_i2c0_rxflr

typedef struct _rs_cpu_sys_i2c0_rxflr  rs_cpu_sys_i2c0_rxflr;
struct _rs_cpu_sys_i2c0_rxflr {
    unsigned int RXFLR                                      : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_i2c0_rxflr(val) ((rs_cpu_sys_i2c0_rxflr*)&(val))



#define CPU_SYS_I2C0_IC_SDA_HOLD                                         (HV_I2C0_BASE_ADDRESS + 0x7C)

#define CPU_SYS_I2C0_IC_SDA_HOLD_struct                                  rs_cpu_sys_i2c0_ic_sda_hold

typedef struct _rs_cpu_sys_i2c0_ic_sda_hold  rs_cpu_sys_i2c0_ic_sda_hold;
struct _rs_cpu_sys_i2c0_ic_sda_hold {
    unsigned int IC_SDA_TX_HOLD                             :16;
    unsigned int IC_SDA_RX_HOLD                             : 8;
    unsigned int reserved                                   : 8;
};
#define cpu_sys_i2c0_ic_sda_hold(val) ((rs_cpu_sys_i2c0_ic_sda_hold*)&(val))



#define CPU_SYS_I2C0_IC_TX_ABRT_SOURCE                                   (HV_I2C0_BASE_ADDRESS + 0x80)

#define CPU_SYS_I2C0_IC_TX_ABRT_SOURCE_struct                            rs_cpu_sys_i2c0_ic_tx_abrt_source

typedef struct _rs_cpu_sys_i2c0_ic_tx_abrt_source  rs_cpu_sys_i2c0_ic_tx_abrt_source;
struct _rs_cpu_sys_i2c0_ic_tx_abrt_source {
    unsigned int ABRT_7B_ADDR_NOACK                         : 1;
    unsigned int ABRT_10ADDR1_NOACK                         : 1;
    unsigned int ABRT_10ADDR2_NOACK                         : 1;
    unsigned int ABRT_TXDATA_NOACK                          : 1;
    unsigned int ABRT_GCALL_NOACK                           : 1;
    unsigned int ABRT_GCALL_READ                            : 1;
    unsigned int ABRT_HS_ACKDET                             : 1;
    unsigned int ABRT_SBYTE_ACKDET                          : 1;
    unsigned int ABRT_HS_NORSTRT                            : 1;
    unsigned int ABRT_SBYTE_NORSTRT                         : 1;
    unsigned int ABRT_10B_RD_NORSTRT                        : 1;
    unsigned int ABRT_MASTER_DIS                            : 1;
    unsigned int ARB_LOST                                   : 1;
    unsigned int ABRT_SLVFLUSH_TXFIFO                       : 1;
    unsigned int ABRT_SLV_ARBLOST                           : 1;
    unsigned int ABRT_SLVRD_INTX                            : 1;
    unsigned int ABRT_USER_ABRT                             : 1;
    unsigned int ABRT_SDA_STUCK_AT_LOW                      : 1;
    unsigned int reserved                                   : 5;
    unsigned int TX_FLUSH_CNT                               : 9;
};
#define cpu_sys_i2c0_ic_tx_abrt_source(val) ((rs_cpu_sys_i2c0_ic_tx_abrt_source*)&(val))



#define CPU_SYS_I2C0_IC_SLV_DATA_NACK_ONLY                               (HV_I2C0_BASE_ADDRESS + 0x84)

#define CPU_SYS_I2C0_IC_SLV_DATA_NACK_ONLY_struct                        rs_cpu_sys_i2c0_ic_slv_data_nack_only

typedef struct _rs_cpu_sys_i2c0_ic_slv_data_nack_only  rs_cpu_sys_i2c0_ic_slv_data_nack_only;
struct _rs_cpu_sys_i2c0_ic_slv_data_nack_only {
    unsigned int NACK                                       : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_slv_data_nack_only(val) ((rs_cpu_sys_i2c0_ic_slv_data_nack_only*)&(val))



#define CPU_SYS_I2C0_IC_DMA_CR                                           (HV_I2C0_BASE_ADDRESS + 0x88)

#define CPU_SYS_I2C0_IC_DMA_CR_struct                                    rs_cpu_sys_i2c0_ic_dma_cr

typedef struct _rs_cpu_sys_i2c0_ic_dma_cr  rs_cpu_sys_i2c0_ic_dma_cr;
struct _rs_cpu_sys_i2c0_ic_dma_cr {
    unsigned int RDMAE                                      : 1;
    unsigned int TDMAE                                      : 1;
    unsigned int reserved                                   :30;
};
#define cpu_sys_i2c0_ic_dma_cr(val) ((rs_cpu_sys_i2c0_ic_dma_cr*)&(val))



#define CPU_SYS_I2C0_IC_DMA_TDLR                                         (HV_I2C0_BASE_ADDRESS + 0x8C)

#define CPU_SYS_I2C0_IC_DMA_TDLR_struct                                  rs_cpu_sys_i2c0_ic_dma_tdlr

typedef struct _rs_cpu_sys_i2c0_ic_dma_tdlr  rs_cpu_sys_i2c0_ic_dma_tdlr;
struct _rs_cpu_sys_i2c0_ic_dma_tdlr {
    unsigned int DMATDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_i2c0_ic_dma_tdlr(val) ((rs_cpu_sys_i2c0_ic_dma_tdlr*)&(val))



#define CPU_SYS_I2C0_IC_DMA_RDLR                                         (HV_I2C0_BASE_ADDRESS + 0x90)

#define CPU_SYS_I2C0_IC_DMA_RDLR_struct                                  rs_cpu_sys_i2c0_ic_dma_rdlr

typedef struct _rs_cpu_sys_i2c0_ic_dma_rdlr  rs_cpu_sys_i2c0_ic_dma_rdlr;
struct _rs_cpu_sys_i2c0_ic_dma_rdlr {
    unsigned int DMARDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_i2c0_ic_dma_rdlr(val) ((rs_cpu_sys_i2c0_ic_dma_rdlr*)&(val))



#define CPU_SYS_I2C0_IC_SDA_SETUP                                        (HV_I2C0_BASE_ADDRESS + 0x94)

#define CPU_SYS_I2C0_IC_SDA_SETUP_struct                                 rs_cpu_sys_i2c0_ic_sda_setup

typedef struct _rs_cpu_sys_i2c0_ic_sda_setup  rs_cpu_sys_i2c0_ic_sda_setup;
struct _rs_cpu_sys_i2c0_ic_sda_setup {
    unsigned int SDA_SETUP                                  : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_i2c0_ic_sda_setup(val) ((rs_cpu_sys_i2c0_ic_sda_setup*)&(val))



#define CPU_SYS_I2C0_IC_ACK_GENERAL_CALL                                 (HV_I2C0_BASE_ADDRESS + 0x98)

#define CPU_SYS_I2C0_IC_ACK_GENERAL_CALL_struct                          rs_cpu_sys_i2c0_ic_ack_general_call

typedef struct _rs_cpu_sys_i2c0_ic_ack_general_call  rs_cpu_sys_i2c0_ic_ack_general_call;
struct _rs_cpu_sys_i2c0_ic_ack_general_call {
    unsigned int ACK_GEN_CALL                               : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_ack_general_call(val) ((rs_cpu_sys_i2c0_ic_ack_general_call*)&(val))



#define CPU_SYS_I2C0_IC_ENABLE_STATUS                                    (HV_I2C0_BASE_ADDRESS + 0x9C)

#define CPU_SYS_I2C0_IC_ENABLE_STATUS_struct                             rs_cpu_sys_i2c0_ic_enable_status

typedef struct _rs_cpu_sys_i2c0_ic_enable_status  rs_cpu_sys_i2c0_ic_enable_status;
struct _rs_cpu_sys_i2c0_ic_enable_status {
    unsigned int IC_EN                                      : 1;
    unsigned int SLV_DISABLED_WHILE_BUSY                    : 1;
    unsigned int SLV_RX_DATA_LOST                           : 1;
    unsigned int reserved                                   :29;
};
#define cpu_sys_i2c0_ic_enable_status(val) ((rs_cpu_sys_i2c0_ic_enable_status*)&(val))



#define CPU_SYS_I2C0_IC_FS_SPKLEN                                        (HV_I2C0_BASE_ADDRESS + 0xA0)

#define CPU_SYS_I2C0_IC_FS_SPKLEN_struct                                 rs_cpu_sys_i2c0_ic_fs_spklen

typedef struct _rs_cpu_sys_i2c0_ic_fs_spklen  rs_cpu_sys_i2c0_ic_fs_spklen;
struct _rs_cpu_sys_i2c0_ic_fs_spklen {
    unsigned int IC_FS_SPKLEN                               : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_i2c0_ic_fs_spklen(val) ((rs_cpu_sys_i2c0_ic_fs_spklen*)&(val))



#define CPU_SYS_I2C0_IC_CLR_RESTART_DET                                  (HV_I2C0_BASE_ADDRESS + 0xA8)

#define CPU_SYS_I2C0_IC_CLR_RESTART_DET_struct                           rs_cpu_sys_i2c0_ic_clr_restart_det

typedef struct _rs_cpu_sys_i2c0_ic_clr_restart_det  rs_cpu_sys_i2c0_ic_clr_restart_det;
struct _rs_cpu_sys_i2c0_ic_clr_restart_det {
    unsigned int CLR_RESTART_DET                            : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_restart_det(val) ((rs_cpu_sys_i2c0_ic_clr_restart_det*)&(val))



#define CPU_SYS_I2C0_IC_SCL_STUCK_LOW_TIMEOUT                            (HV_I2C0_BASE_ADDRESS + 0xAC)

#define CPU_SYS_I2C0_IC_SCL_STUCK_LOW_TIMEOUT_struct                     rs_cpu_sys_i2c0_ic_scl_stuck_low_timeout

typedef struct _rs_cpu_sys_i2c0_ic_scl_stuck_low_timeout  rs_cpu_sys_i2c0_ic_scl_stuck_low_timeout;
struct _rs_cpu_sys_i2c0_ic_scl_stuck_low_timeout {
    unsigned int IC_SCL_STUCK_LOW_TIMEOUT                   :32;
};
#define cpu_sys_i2c0_ic_scl_stuck_low_timeout(val) ((rs_cpu_sys_i2c0_ic_scl_stuck_low_timeout*)&(val))



#define CPU_SYS_I2C0_IC_SDA_STUCK_LOW_TIMEOUT                            (HV_I2C0_BASE_ADDRESS + 0xB0)

#define CPU_SYS_I2C0_IC_SDA_STUCK_LOW_TIMEOUT_struct                     rs_cpu_sys_i2c0_ic_sda_stuck_low_timeout

typedef struct _rs_cpu_sys_i2c0_ic_sda_stuck_low_timeout  rs_cpu_sys_i2c0_ic_sda_stuck_low_timeout;
struct _rs_cpu_sys_i2c0_ic_sda_stuck_low_timeout {
    unsigned int IC_SDA_STUCK_LOW_TIMEOUT                   :32;
};
#define cpu_sys_i2c0_ic_sda_stuck_low_timeout(val) ((rs_cpu_sys_i2c0_ic_sda_stuck_low_timeout*)&(val))



#define CPU_SYS_I2C0_IC_CLR_SCL_STUCK_DET                                (HV_I2C0_BASE_ADDRESS + 0xB4)

#define CPU_SYS_I2C0_IC_CLR_SCL_STUCK_DET_struct                         rs_cpu_sys_i2c0_ic_clr_scl_stuck_det

typedef struct _rs_cpu_sys_i2c0_ic_clr_scl_stuck_det  rs_cpu_sys_i2c0_ic_clr_scl_stuck_det;
struct _rs_cpu_sys_i2c0_ic_clr_scl_stuck_det {
    unsigned int CLR_SCL_STUCK_DET                          : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_i2c0_ic_clr_scl_stuck_det(val) ((rs_cpu_sys_i2c0_ic_clr_scl_stuck_det*)&(val))



#define CPU_SYS_I2C0_REG_TIMEOUT_RST                                     (HV_I2C0_BASE_ADDRESS + 0xF0)

#define CPU_SYS_I2C0_REG_TIMEOUT_RST_struct                              rs_cpu_sys_i2c0_reg_timeout_rst

typedef struct _rs_cpu_sys_i2c0_reg_timeout_rst  rs_cpu_sys_i2c0_reg_timeout_rst;
struct _rs_cpu_sys_i2c0_reg_timeout_rst {
    unsigned int rw                                         : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_i2c0_reg_timeout_rst(val) ((rs_cpu_sys_i2c0_reg_timeout_rst*)&(val))



#define CPU_SYS_I2C0_IC_COMP_PARAM_1                                     (HV_I2C0_BASE_ADDRESS + 0xF4)

#define CPU_SYS_I2C0_IC_COMP_PARAM_1_struct                              rs_cpu_sys_i2c0_ic_comp_param_1

typedef struct _rs_cpu_sys_i2c0_ic_comp_param_1  rs_cpu_sys_i2c0_ic_comp_param_1;
struct _rs_cpu_sys_i2c0_ic_comp_param_1 {
    unsigned int APB_DATA_WIDTH                             : 2;
    unsigned int MAX_SPEED_MODE                             : 2;
    unsigned int HC_COUNT_VALUES                            : 1;
    unsigned int INTR_IO                                    : 1;
    unsigned int HAS_DMA                                    : 1;
    unsigned int ADD_ENCODED_PARAMS                         : 1;
    unsigned int RX_BUFFER_DEPTH                            : 8;
    unsigned int TX_BUFFER_DEPTH                            : 8;
    unsigned int reserved                                   : 8;
};
#define cpu_sys_i2c0_ic_comp_param_1(val) ((rs_cpu_sys_i2c0_ic_comp_param_1*)&(val))



#define CPU_SYS_I2C0_IC_COMP_VERSION                                     (HV_I2C0_BASE_ADDRESS + 0xF8)

#define CPU_SYS_I2C0_IC_COMP_VERSION_struct                              rs_cpu_sys_i2c0_ic_comp_version

typedef struct _rs_cpu_sys_i2c0_ic_comp_version  rs_cpu_sys_i2c0_ic_comp_version;
struct _rs_cpu_sys_i2c0_ic_comp_version {
    unsigned int IC_COMP_VERSION                            :32;
};
#define cpu_sys_i2c0_ic_comp_version(val) ((rs_cpu_sys_i2c0_ic_comp_version*)&(val))



#define CPU_SYS_I2C0_IC_COMP_TYPE                                        (HV_I2C0_BASE_ADDRESS + 0xFC)

#define CPU_SYS_I2C0_IC_COMP_TYPE_struct                                 rs_cpu_sys_i2c0_ic_comp_type

typedef struct _rs_cpu_sys_i2c0_ic_comp_type  rs_cpu_sys_i2c0_ic_comp_type;
struct _rs_cpu_sys_i2c0_ic_comp_type {
    unsigned int IC_COMP_TYPE                               :32;
};
#define cpu_sys_i2c0_ic_comp_type(val) ((rs_cpu_sys_i2c0_ic_comp_type*)&(val))



#endif