#ifndef _HV_PAGE_HT7315_EDP_RX_DPCD_3_REG_00_H_
#define _HV_PAGE_HT7315_EDP_RX_DPCD_3_REG_00_H_

#ifndef HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS
    #define HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS                                         0x11048300
#endif


#define RX_EDP_RX_DPCD_3_REG_00_00                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_DPCD_3_REG_00_00_struct                                rs_rx_edp_rx_dpcd_3_reg_00_00

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_00  rs_rx_edp_rx_dpcd_3_reg_00_00;
struct _rs_rx_edp_rx_dpcd_3_reg_00_00 {
    unsigned int reg_00_dprx_dpcd_source_ieee_oui           :24;
    unsigned int reg_00_dprx_dpcd_source_device_identification_string0: 8;
};
#define rx_edp_rx_dpcd_3_reg_00_00(val) ((rs_rx_edp_rx_dpcd_3_reg_00_00*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_04                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_DPCD_3_REG_00_04_struct                                rs_rx_edp_rx_dpcd_3_reg_00_04

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_04  rs_rx_edp_rx_dpcd_3_reg_00_04;
struct _rs_rx_edp_rx_dpcd_3_reg_00_04 {
    unsigned int reg_00_dprx_dpcd_source_device_identification_string1:32;
};
#define rx_edp_rx_dpcd_3_reg_00_04(val) ((rs_rx_edp_rx_dpcd_3_reg_00_04*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_08                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_DPCD_3_REG_00_08_struct                                rs_rx_edp_rx_dpcd_3_reg_00_08

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_08  rs_rx_edp_rx_dpcd_3_reg_00_08;
struct _rs_rx_edp_rx_dpcd_3_reg_00_08 {
    unsigned int reg_00_dprx_dpcd_source_device_identification_string2: 8;
    unsigned int reg_00_dprx_dpcd_source_hardware_minor_revision: 4;
    unsigned int reg_00_dprx_dpcd_source_hardware_major_revision: 4;
    unsigned int reg_00_dprx_dpcd_source_firmware_software_major_revision: 8;
    unsigned int reg_00_dprx_dpcd_source_firmware_software_minor_revision: 8;
};
#define rx_edp_rx_dpcd_3_reg_00_08(val) ((rs_rx_edp_rx_dpcd_3_reg_00_08*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_20                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_DPCD_3_REG_00_20_struct                                rs_rx_edp_rx_dpcd_3_reg_00_20

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_20  rs_rx_edp_rx_dpcd_3_reg_00_20;
struct _rs_rx_edp_rx_dpcd_3_reg_00_20 {
    unsigned int reg_00_dprx_dpcd_sink_ieee_oui             :24;
    unsigned int reg_00_dprx_dpcd_sink_device_identification_string0: 8;
};
#define rx_edp_rx_dpcd_3_reg_00_20(val) ((rs_rx_edp_rx_dpcd_3_reg_00_20*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_24                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_DPCD_3_REG_00_24_struct                                rs_rx_edp_rx_dpcd_3_reg_00_24

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_24  rs_rx_edp_rx_dpcd_3_reg_00_24;
struct _rs_rx_edp_rx_dpcd_3_reg_00_24 {
    unsigned int reg_00_dprx_dpcd_sink_device_identification_string1:32;
};
#define rx_edp_rx_dpcd_3_reg_00_24(val) ((rs_rx_edp_rx_dpcd_3_reg_00_24*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_28                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_DPCD_3_REG_00_28_struct                                rs_rx_edp_rx_dpcd_3_reg_00_28

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_28  rs_rx_edp_rx_dpcd_3_reg_00_28;
struct _rs_rx_edp_rx_dpcd_3_reg_00_28 {
    unsigned int reg_00_dprx_dpcd_sink_device_identification_string2: 8;
    unsigned int reg_00_dprx_dpcd_sink_hardware_minor_revision: 4;
    unsigned int reg_00_dprx_dpcd_sink_hardware_major_revision: 4;
    unsigned int reg_00_dprx_dpcd_sink_firmware_software_major_revision: 8;
    unsigned int reg_00_dprx_dpcd_sink_firmware_software_minor_revision: 8;
};
#define rx_edp_rx_dpcd_3_reg_00_28(val) ((rs_rx_edp_rx_dpcd_3_reg_00_28*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_40                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_DPCD_3_REG_00_40_struct                                rs_rx_edp_rx_dpcd_3_reg_00_40

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_40  rs_rx_edp_rx_dpcd_3_reg_00_40;
struct _rs_rx_edp_rx_dpcd_3_reg_00_40 {
    unsigned int reg_00_dprx_dpcd_branch_ieee_oui           :24;
    unsigned int reg_00_dprx_dpcd_branch_device_identification_string0: 8;
};
#define rx_edp_rx_dpcd_3_reg_00_40(val) ((rs_rx_edp_rx_dpcd_3_reg_00_40*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_44                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_DPCD_3_REG_00_44_struct                                rs_rx_edp_rx_dpcd_3_reg_00_44

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_44  rs_rx_edp_rx_dpcd_3_reg_00_44;
struct _rs_rx_edp_rx_dpcd_3_reg_00_44 {
    unsigned int reg_00_dprx_dpcd_branch_device_identification_string1:32;
};
#define rx_edp_rx_dpcd_3_reg_00_44(val) ((rs_rx_edp_rx_dpcd_3_reg_00_44*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_48                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_DPCD_3_REG_00_48_struct                                rs_rx_edp_rx_dpcd_3_reg_00_48

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_48  rs_rx_edp_rx_dpcd_3_reg_00_48;
struct _rs_rx_edp_rx_dpcd_3_reg_00_48 {
    unsigned int reg_00_dprx_dpcd_branch_device_identification_string2: 8;
    unsigned int reg_00_dprx_dpcd_branch_hardware_minor_revision: 4;
    unsigned int reg_00_dprx_dpcd_branch_hardware_major_revision: 4;
    unsigned int reg_00_dprx_dpcd_branch_firmware_software_major_revision: 8;
    unsigned int reg_00_dprx_dpcd_branch_firmware_software_minor_revision: 8;
};
#define rx_edp_rx_dpcd_3_reg_00_48(val) ((rs_rx_edp_rx_dpcd_3_reg_00_48*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_60                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_DPCD_3_REG_00_60_struct                                rs_rx_edp_rx_dpcd_3_reg_00_60

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_60  rs_rx_edp_rx_dpcd_3_reg_00_60;
struct _rs_rx_edp_rx_dpcd_3_reg_00_60 {
    unsigned int reg_00_dprx_dpcd_set_power_state           : 3;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_dprx_dpcd_set_dn_device_dp_pwr_5v   : 1;
    unsigned int reg_00_dprx_dpcd_set_dn_device_dp_pwr_12v  : 1;
    unsigned int reg_00_dprx_dpcd_set_dn_device_dp_pwr_18v  : 1;
    unsigned int reserved_1                                 :24;
};
#define rx_edp_rx_dpcd_3_reg_00_60(val) ((rs_rx_edp_rx_dpcd_3_reg_00_60*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_84                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x84)

#define RX_EDP_RX_DPCD_3_REG_00_84_struct                                rs_rx_edp_rx_dpcd_3_reg_00_84

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_84  rs_rx_edp_rx_dpcd_3_reg_00_84;
struct _rs_rx_edp_rx_dpcd_3_reg_00_84 {
    unsigned int reg_00_dprx_dpcd_output_htotal             :16;
    unsigned int reg_00_dprx_dpcd_output_hstart             :16;
};
#define rx_edp_rx_dpcd_3_reg_00_84(val) ((rs_rx_edp_rx_dpcd_3_reg_00_84*)&(val))



#define RX_EDP_RX_DPCD_3_REG_00_88                                       (HV_EDP_RX_DPCD_3_REG_00_BASE_ADDRESS + 0x88)

#define RX_EDP_RX_DPCD_3_REG_00_88_struct                                rs_rx_edp_rx_dpcd_3_reg_00_88

typedef struct _rs_rx_edp_rx_dpcd_3_reg_00_88  rs_rx_edp_rx_dpcd_3_reg_00_88;
struct _rs_rx_edp_rx_dpcd_3_reg_00_88 {
    unsigned int reg_00_dprx_dpcd_output_hsp_hsw            :15;
    unsigned int reg_00_dprx_dpcd_output_hsp                : 1;
    unsigned int reserved                                   :16;
};
#define rx_edp_rx_dpcd_3_reg_00_88(val) ((rs_rx_edp_rx_dpcd_3_reg_00_88*)&(val))



#endif