#ifndef _HV_PAGE_HT7315_SH08_TOP_RX_H_
#define _HV_PAGE_HT7315_SH08_TOP_RX_H_

#ifndef HV_SH08_TOP_RX_BASE_ADDRESS
    #define HV_SH08_TOP_RX_BASE_ADDRESS                                         0x11044800
#endif


#define RX_SH08_TOP_RX_CTRL_0                                            (HV_SH08_TOP_RX_BASE_ADDRESS + 0x00)

#define RX_SH08_TOP_RX_CTRL_0_struct                                     rs_rx_sh08_top_rx_ctrl_0

typedef struct _rs_rx_sh08_top_rx_ctrl_0  rs_rx_sh08_top_rx_ctrl_0;
struct _rs_rx_sh08_top_rx_ctrl_0 {
    unsigned int reg_gpio0_func_sel                         : 1;
    unsigned int reg_gpio19_func_sel                        : 3;
    unsigned int reg_gpio1_func_sel                         : 1;
    unsigned int reg_gpio20_func_sel                        : 3;
    unsigned int reg_gpio21_func_sel                        : 3;
    unsigned int reg_gpio22_func_sel                        : 3;
    unsigned int reg_gpio23_func_sel                        : 3;
    unsigned int reg_gpio24_func_sel                        : 3;
    unsigned int reg_gpio25_func_sel                        : 3;
    unsigned int reg_gpio26_func_sel                        : 3;
    unsigned int reg_gpio27_func_sel                        : 3;
    unsigned int reg_gpio2_func_sel                         : 1;
    unsigned int reg_gpio3_func_sel                         : 1;
    unsigned int reg_gpio4_func_sel                         : 1;
};
#define rx_sh08_top_rx_ctrl_0(val) ((rs_rx_sh08_top_rx_ctrl_0*)&(val))



#define RX_SH08_TOP_RX_CTRL_4                                            (HV_SH08_TOP_RX_BASE_ADDRESS + 0x04)

#define RX_SH08_TOP_RX_CTRL_4_struct                                     rs_rx_sh08_top_rx_ctrl_4

typedef struct _rs_rx_sh08_top_rx_ctrl_4  rs_rx_sh08_top_rx_ctrl_4;
struct _rs_rx_sh08_top_rx_ctrl_4 {
    unsigned int reg_gpio5_func_sel                         : 1;
    unsigned int reg_gpio6_func_sel                         : 1;
    unsigned int reg_gpio7_func_sel                         : 1;
    unsigned int reg_i2cs0_scl_func_sel                     : 2;
    unsigned int reg_i2cs0_sda_func_sel                     : 2;
    unsigned int reg_uart0_rx_func_sel                      : 1;
    unsigned int reg_gpio28_func_sel                        : 2;
    unsigned int reg_uart1_tx_func_sel                      : 2;
    unsigned int reg_uart0_tx_func_sel                      : 2;
    unsigned int reg_uart1_rx_func_sel                      : 2;
    unsigned int reg_gpio29_func_sel                        : 2;
    unsigned int reg_aging_in_in_sel                        : 2;
    unsigned int reg_bist_patt_in_in_sel                    : 2;
    unsigned int reg_ejtag_dint_in_sel                      : 2;
    unsigned int reg_ejtag_tck_in_sel                       : 2;
    unsigned int reg_ejtag_tdi_in_sel                       : 2;
    unsigned int reg_ejtag_tms_in_sel                       : 2;
    unsigned int reg_ejtag_trstn_in_sel                     : 2;
};
#define rx_sh08_top_rx_ctrl_4(val) ((rs_rx_sh08_top_rx_ctrl_4*)&(val))



#define RX_SH08_TOP_RX_CTRL_8                                            (HV_SH08_TOP_RX_BASE_ADDRESS + 0x08)

#define RX_SH08_TOP_RX_CTRL_8_struct                                     rs_rx_sh08_top_rx_ctrl_8

typedef struct _rs_rx_sh08_top_rx_ctrl_8  rs_rx_sh08_top_rx_ctrl_8;
struct _rs_rx_sh08_top_rx_ctrl_8 {
    unsigned int reg_gpio_in_rx_in_sel                      : 2;
    unsigned int reg_i2s_sck_in_pad_in_sel                  : 2;
    unsigned int reg_i2s_sd_in_pad_in_sel                   : 2;
    unsigned int reg_i2s_ws_in_pad_in_sel                   : 2;
    unsigned int reg_i_x_sin_in_sel                         : 2;
    unsigned int reg_m_scl_in_in_sel                        : 2;
    unsigned int reg_m_sda_in_in_sel                        : 2;
    unsigned int reserved                                   : 2;
    unsigned int reg_s_scl_in_in_sel                        : 2;
    unsigned int reg_s_sda_in_in_sel                        : 2;
    unsigned int reg_spdif_in_pad_in_sel                    : 2;
    unsigned int reg_uart0_sin_in_sel                       : 2;
    unsigned int reg_uart1_sin_in_sel                       : 2;
    unsigned int reg_gpio0_pin_sel                          : 2;
    unsigned int reg_gpio19_pin_sel                         : 2;
    unsigned int reg_gpio1_pin_sel                          : 2;
};
#define rx_sh08_top_rx_ctrl_8(val) ((rs_rx_sh08_top_rx_ctrl_8*)&(val))



#define RX_SH08_TOP_RX_CTRL_C                                            (HV_SH08_TOP_RX_BASE_ADDRESS + 0x0C)

#define RX_SH08_TOP_RX_CTRL_C_struct                                     rs_rx_sh08_top_rx_ctrl_c

typedef struct _rs_rx_sh08_top_rx_ctrl_c  rs_rx_sh08_top_rx_ctrl_c;
struct _rs_rx_sh08_top_rx_ctrl_c {
    unsigned int reg_gpio20_pin_sel                         : 2;
    unsigned int reg_gpio21_pin_sel                         : 2;
    unsigned int reg_gpio22_pin_sel                         : 2;
    unsigned int reg_gpio23_pin_sel                         : 2;
    unsigned int reg_gpio24_pin_sel                         : 2;
    unsigned int reg_gpio25_pin_sel                         : 2;
    unsigned int reg_gpio26_pin_sel                         : 2;
    unsigned int reg_gpio27_pin_sel                         : 2;
    unsigned int reg_gpio2_pin_sel                          : 2;
    unsigned int reg_gpio3_pin_sel                          : 2;
    unsigned int reg_gpio4_pin_sel                          : 2;
    unsigned int reg_gpio5_pin_sel                          : 2;
    unsigned int reg_gpio6_pin_sel                          : 2;
    unsigned int reg_gpio7_pin_sel                          : 2;
    unsigned int reg_i2cs0_scl_pin_sel                      : 2;
    unsigned int reg_i2cs0_sda_pin_sel                      : 2;
};
#define rx_sh08_top_rx_ctrl_c(val) ((rs_rx_sh08_top_rx_ctrl_c*)&(val))



#define RX_SH08_TOP_RX_CTRL_10                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x10)

#define RX_SH08_TOP_RX_CTRL_10_struct                                    rs_rx_sh08_top_rx_ctrl_10

typedef struct _rs_rx_sh08_top_rx_ctrl_10  rs_rx_sh08_top_rx_ctrl_10;
struct _rs_rx_sh08_top_rx_ctrl_10 {
    unsigned int reg_uart0_rx_pin_sel                       : 2;
    unsigned int reg_uart0_tx_pin_sel                       : 2;
    unsigned int reg_uart1_rx_pin_sel                       : 2;
    unsigned int reg_uart1_tx_pin_sel                       : 2;
    unsigned int reg_gpio28_pin_sel                         : 2;
    unsigned int reg_gpio29_pin_sel                         : 2;
    unsigned int reg_gpio0_ptg_sel                          : 5;
    unsigned int reg_gpio19_ptg_sel                         : 5;
    unsigned int reg_gpio1_ptg_sel                          : 5;
    unsigned int reg_gpio20_ptg_sel                         : 5;
};
#define rx_sh08_top_rx_ctrl_10(val) ((rs_rx_sh08_top_rx_ctrl_10*)&(val))



#define RX_SH08_TOP_RX_CTRL_14                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x14)

#define RX_SH08_TOP_RX_CTRL_14_struct                                    rs_rx_sh08_top_rx_ctrl_14

typedef struct _rs_rx_sh08_top_rx_ctrl_14  rs_rx_sh08_top_rx_ctrl_14;
struct _rs_rx_sh08_top_rx_ctrl_14 {
    unsigned int reg_gpio21_ptg_sel                         : 5;
    unsigned int reg_gpio22_ptg_sel                         : 5;
    unsigned int reg_gpio23_ptg_sel                         : 5;
    unsigned int reg_gpio24_ptg_sel                         : 5;
    unsigned int reg_gpio25_ptg_sel                         : 5;
    unsigned int reg_gpio26_ptg_sel                         : 5;
    unsigned int reserved                                   : 2;
};
#define rx_sh08_top_rx_ctrl_14(val) ((rs_rx_sh08_top_rx_ctrl_14*)&(val))



#define RX_SH08_TOP_RX_CTRL_18                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x18)

#define RX_SH08_TOP_RX_CTRL_18_struct                                    rs_rx_sh08_top_rx_ctrl_18

typedef struct _rs_rx_sh08_top_rx_ctrl_18  rs_rx_sh08_top_rx_ctrl_18;
struct _rs_rx_sh08_top_rx_ctrl_18 {
    unsigned int reg_gpio27_ptg_sel                         : 5;
    unsigned int reg_gpio2_ptg_sel                          : 5;
    unsigned int reg_gpio3_ptg_sel                          : 5;
    unsigned int reg_gpio4_ptg_sel                          : 5;
    unsigned int reg_gpio5_ptg_sel                          : 5;
    unsigned int reg_gpio6_ptg_sel                          : 5;
    unsigned int reserved                                   : 2;
};
#define rx_sh08_top_rx_ctrl_18(val) ((rs_rx_sh08_top_rx_ctrl_18*)&(val))



#define RX_SH08_TOP_RX_CTRL_1C                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x1C)

#define RX_SH08_TOP_RX_CTRL_1C_struct                                    rs_rx_sh08_top_rx_ctrl_1c

typedef struct _rs_rx_sh08_top_rx_ctrl_1c  rs_rx_sh08_top_rx_ctrl_1c;
struct _rs_rx_sh08_top_rx_ctrl_1c {
    unsigned int reg_gpio7_ptg_sel                          : 5;
    unsigned int reg_i2cs0_scl_ptg_sel                      : 5;
    unsigned int reg_i2cs0_sda_ptg_sel                      : 5;
    unsigned int reg_uart0_rx_ptg_sel                       : 5;
    unsigned int reg_uart0_tx_ptg_sel                       : 5;
    unsigned int reg_uart1_rx_ptg_sel                       : 5;
    unsigned int reserved                                   : 2;
};
#define rx_sh08_top_rx_ctrl_1c(val) ((rs_rx_sh08_top_rx_ctrl_1c*)&(val))



#define RX_SH08_TOP_RX_CTRL_20                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x20)

#define RX_SH08_TOP_RX_CTRL_20_struct                                    rs_rx_sh08_top_rx_ctrl_20

typedef struct _rs_rx_sh08_top_rx_ctrl_20  rs_rx_sh08_top_rx_ctrl_20;
struct _rs_rx_sh08_top_rx_ctrl_20 {
    unsigned int reg_uart1_tx_ptg_sel                       : 5;
    unsigned int reg_gpio0_mon_sel                          : 3;
    unsigned int reg_gpio19_mon_sel                         : 3;
    unsigned int reg_gpio1_mon_sel                          : 3;
    unsigned int reg_gpio20_mon_sel                         : 3;
    unsigned int reg_gpio21_mon_sel                         : 3;
    unsigned int reg_gpio22_mon_sel                         : 3;
    unsigned int reg_gpio23_mon_sel                         : 3;
    unsigned int reg_gpio24_mon_sel                         : 3;
    unsigned int reg_gpio25_mon_sel                         : 3;
};
#define rx_sh08_top_rx_ctrl_20(val) ((rs_rx_sh08_top_rx_ctrl_20*)&(val))



#define RX_SH08_TOP_RX_CTRL_24                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x24)

#define RX_SH08_TOP_RX_CTRL_24_struct                                    rs_rx_sh08_top_rx_ctrl_24

typedef struct _rs_rx_sh08_top_rx_ctrl_24  rs_rx_sh08_top_rx_ctrl_24;
struct _rs_rx_sh08_top_rx_ctrl_24 {
    unsigned int reg_gpio2_mon_sel                          : 3;
    unsigned int reg_gpio3_mon_sel                          : 3;
    unsigned int reg_gpio4_mon_sel                          : 3;
    unsigned int reg_gpio5_mon_sel                          : 3;
    unsigned int reg_gpio6_mon_sel                          : 3;
    unsigned int reg_gpio7_mon_sel                          : 3;
    unsigned int reg_uart0_rx_mon_sel                       : 3;
    unsigned int reg_gpio0_io_ctrl                          : 5;
    unsigned int reserved                                   : 6;
};
#define rx_sh08_top_rx_ctrl_24(val) ((rs_rx_sh08_top_rx_ctrl_24*)&(val))



#define RX_SH08_TOP_RX_CTRL_28                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x28)

#define RX_SH08_TOP_RX_CTRL_28_struct                                    rs_rx_sh08_top_rx_ctrl_28

typedef struct _rs_rx_sh08_top_rx_ctrl_28  rs_rx_sh08_top_rx_ctrl_28;
struct _rs_rx_sh08_top_rx_ctrl_28 {
    unsigned int reg_gpio19_io_ctrl                         : 8;
    unsigned int reg_gpio1_io_ctrl                          : 5;
    unsigned int reserved                                   : 3;
    unsigned int reg_gpio20_io_ctrl                         : 8;
    unsigned int reg_gpio21_io_ctrl                         : 8;
};
#define rx_sh08_top_rx_ctrl_28(val) ((rs_rx_sh08_top_rx_ctrl_28*)&(val))



#define RX_SH08_TOP_RX_CTRL_2C                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x2C)

#define RX_SH08_TOP_RX_CTRL_2C_struct                                    rs_rx_sh08_top_rx_ctrl_2c

typedef struct _rs_rx_sh08_top_rx_ctrl_2c  rs_rx_sh08_top_rx_ctrl_2c;
struct _rs_rx_sh08_top_rx_ctrl_2c {
    unsigned int reg_gpio22_io_ctrl                         : 8;
    unsigned int reg_gpio23_io_ctrl                         : 8;
    unsigned int reg_gpio24_io_ctrl                         : 8;
    unsigned int reg_gpio25_io_ctrl                         : 8;
};
#define rx_sh08_top_rx_ctrl_2c(val) ((rs_rx_sh08_top_rx_ctrl_2c*)&(val))



#define RX_SH08_TOP_RX_CTRL_30                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x30)

#define RX_SH08_TOP_RX_CTRL_30_struct                                    rs_rx_sh08_top_rx_ctrl_30

typedef struct _rs_rx_sh08_top_rx_ctrl_30  rs_rx_sh08_top_rx_ctrl_30;
struct _rs_rx_sh08_top_rx_ctrl_30 {
    unsigned int reg_gpio26_io_ctrl                         : 8;
    unsigned int reg_gpio27_io_ctrl                         : 8;
    unsigned int reg_gpio2_io_ctrl                          : 8;
    unsigned int reg_gpio3_io_ctrl                          : 8;
};
#define rx_sh08_top_rx_ctrl_30(val) ((rs_rx_sh08_top_rx_ctrl_30*)&(val))



#define RX_SH08_TOP_RX_CTRL_34                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x34)

#define RX_SH08_TOP_RX_CTRL_34_struct                                    rs_rx_sh08_top_rx_ctrl_34

typedef struct _rs_rx_sh08_top_rx_ctrl_34  rs_rx_sh08_top_rx_ctrl_34;
struct _rs_rx_sh08_top_rx_ctrl_34 {
    unsigned int reg_gpio4_io_ctrl                          : 8;
    unsigned int reg_gpio5_io_ctrl                          : 8;
    unsigned int reg_gpio6_io_ctrl                          : 8;
    unsigned int reg_gpio7_io_ctrl                          : 8;
};
#define rx_sh08_top_rx_ctrl_34(val) ((rs_rx_sh08_top_rx_ctrl_34*)&(val))



#define RX_SH08_TOP_RX_CTRL_38                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x38)

#define RX_SH08_TOP_RX_CTRL_38_struct                                    rs_rx_sh08_top_rx_ctrl_38

typedef struct _rs_rx_sh08_top_rx_ctrl_38  rs_rx_sh08_top_rx_ctrl_38;
struct _rs_rx_sh08_top_rx_ctrl_38 {
    unsigned int reg_i2cs0_scl_io_ctrl                      : 8;
    unsigned int reg_i2cs0_sda_io_ctrl                      : 8;
    unsigned int reg_uart0_rx_io_ctrl                       : 8;
    unsigned int reg_uart0_tx_io_ctrl                       : 8;
};
#define rx_sh08_top_rx_ctrl_38(val) ((rs_rx_sh08_top_rx_ctrl_38*)&(val))



#define RX_SH08_TOP_RX_CTRL_3C                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x3C)

#define RX_SH08_TOP_RX_CTRL_3C_struct                                    rs_rx_sh08_top_rx_ctrl_3c

typedef struct _rs_rx_sh08_top_rx_ctrl_3c  rs_rx_sh08_top_rx_ctrl_3c;
struct _rs_rx_sh08_top_rx_ctrl_3c {
    unsigned int reg_gpio28_io_ctrl                         : 5;
    unsigned int reserved                                   : 3;
    unsigned int reg_gpio29_io_ctrl                         : 5;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_uart1_rx_io_ctrl                       : 8;
    unsigned int reg_uart1_tx_io_ctrl                       : 8;
};
#define rx_sh08_top_rx_ctrl_3c(val) ((rs_rx_sh08_top_rx_ctrl_3c*)&(val))



#define RX_SH08_TOP_RX_0X40                                              (HV_SH08_TOP_RX_BASE_ADDRESS + 0x40)

#define RX_SH08_TOP_RX_0X40_struct                                       rs_rx_sh08_top_rx_0x40

typedef struct _rs_rx_sh08_top_rx_0x40  rs_rx_sh08_top_rx_0x40;
struct _rs_rx_sh08_top_rx_0x40 {
    unsigned int reg_gpio28_ptg_sel                         : 5;
    unsigned int reg_gpio29_ptg_sel                         : 5;
    unsigned int reserved                                   : 6;
    unsigned int reg_ate_sel                                : 2;
    unsigned int reg_io_user_mode                           : 1;
    unsigned int reg_s_scl_in_use_sel                       : 2;
    unsigned int reg_s_sda_in_use_sel                       : 2;
    unsigned int reg_spdif_in_pad_use_sel                   : 1;
    unsigned int reg_uart1_sin_use_sel                      : 1;
    unsigned int reserved_1                                 : 7;
};
#define rx_sh08_top_rx_0x40(val) ((rs_rx_sh08_top_rx_0x40*)&(val))



#define RX_SH08_TOP_RX_CTRL_44                                           (HV_SH08_TOP_RX_BASE_ADDRESS + 0x44)

#define RX_SH08_TOP_RX_CTRL_44_struct                                    rs_rx_sh08_top_rx_ctrl_44

typedef struct _rs_rx_sh08_top_rx_ctrl_44  rs_rx_sh08_top_rx_ctrl_44;
struct _rs_rx_sh08_top_rx_ctrl_44 {
    unsigned int reg_gpio19_pin_filter                      :16;
    unsigned int reg_gpio20_pin_filter                      :16;
};
#define rx_sh08_top_rx_ctrl_44(val) ((rs_rx_sh08_top_rx_ctrl_44*)&(val))



#define RX_SH08_TOP_RX_RO_D0                                             (HV_SH08_TOP_RX_BASE_ADDRESS + 0xD0)

#define RX_SH08_TOP_RX_RO_D0_struct                                      rs_rx_sh08_top_rx_ro_d0

typedef struct _rs_rx_sh08_top_rx_ro_d0  rs_rx_sh08_top_rx_ro_d0;
struct _rs_rx_sh08_top_rx_ro_d0 {
    unsigned int regr_gpio0_di                              : 1;
    unsigned int regr_gpio19_di                             : 1;
    unsigned int regr_gpio1_di                              : 1;
    unsigned int regr_gpio20_di                             : 1;
    unsigned int regr_gpio21_di                             : 1;
    unsigned int regr_gpio22_di                             : 1;
    unsigned int regr_gpio23_di                             : 1;
    unsigned int regr_gpio24_di                             : 1;
    unsigned int regr_gpio25_di                             : 1;
    unsigned int regr_gpio26_di                             : 1;
    unsigned int regr_gpio27_di                             : 1;
    unsigned int regr_gpio2_di                              : 1;
    unsigned int regr_gpio3_di                              : 1;
    unsigned int regr_gpio4_di                              : 1;
    unsigned int regr_gpio5_di                              : 1;
    unsigned int regr_gpio6_di                              : 1;
    unsigned int regr_gpio7_di                              : 1;
    unsigned int regr_i2cs0_scl_di                          : 1;
    unsigned int regr_i2cs0_sda_di                          : 1;
    unsigned int regr_uart0_rx_di                           : 1;
    unsigned int regr_uart0_tx_di                           : 1;
    unsigned int regr_uart1_rx_di                           : 1;
    unsigned int regr_uart1_tx_di                           : 1;
    unsigned int regr_bond0_di                              : 1;
    unsigned int regr_bond1_di                              : 1;
    unsigned int regr_bond2_di                              : 1;
    unsigned int regr_bond3_di                              : 1;
    unsigned int regr_gpio28_di                             : 1;
    unsigned int regr_gpio29_di                             : 1;
    unsigned int reserved                                   : 3;
};
#define rx_sh08_top_rx_ro_d0(val) ((rs_rx_sh08_top_rx_ro_d0*)&(val))



#define RX_SH08_TOP_RX_RO_D4                                             (HV_SH08_TOP_RX_BASE_ADDRESS + 0xD4)

#define RX_SH08_TOP_RX_RO_D4_struct                                      rs_rx_sh08_top_rx_ro_d4

typedef struct _rs_rx_sh08_top_rx_ro_d4  rs_rx_sh08_top_rx_ro_d4;
struct _rs_rx_sh08_top_rx_ro_d4 {
    unsigned int regr_mrom_version                          : 8;
    unsigned int reserved                                   :24;
};
#define rx_sh08_top_rx_ro_d4(val) ((rs_rx_sh08_top_rx_ro_d4*)&(val))



#endif