#ifndef _HV_PAGE_HT7315_TM0_REGC_H_
#define _HV_PAGE_HT7315_TM0_REGC_H_

#ifndef HV_TM0_REGC_BASE_ADDRESS
    #define HV_TM0_REGC_BASE_ADDRESS                                         0x11085000
#endif


#define CPU_SYS_TM0_REGC_TMRC0                                           (HV_TM0_REGC_BASE_ADDRESS + 0x000)

#define CPU_SYS_TM0_REGC_TMRC0_struct                                    rs_cpu_sys_tm0_regc_tmrc0

typedef struct _rs_cpu_sys_tm0_regc_tmrc0  rs_cpu_sys_tm0_regc_tmrc0;
struct _rs_cpu_sys_tm0_regc_tmrc0 {
    unsigned int reserved                                   : 5;
    unsigned int CRE0                                       : 1;
    unsigned int CCDE0                                      : 1;
    unsigned int TCE0                                       : 1;
    unsigned int reserved_1                                 :24;
};
#define cpu_sys_tm0_regc_tmrc0(val) ((rs_cpu_sys_tm0_regc_tmrc0*)&(val))



#define CPU_SYS_TM0_REGC_TMRINT0                                         (HV_TM0_REGC_BASE_ADDRESS + 0x004)

#define CPU_SYS_TM0_REGC_TMRINT0_struct                                  rs_cpu_sys_tm0_regc_tmrint0

typedef struct _rs_cpu_sys_tm0_regc_tmrint0  rs_cpu_sys_tm0_regc_tmrint0;
struct _rs_cpu_sys_tm0_regc_tmrint0 {
    unsigned int TIIS0                                      : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_tm0_regc_tmrint0(val) ((rs_cpu_sys_tm0_regc_tmrint0*)&(val))



#define CPU_SYS_TM0_REGC_TMRCMP0                                         (HV_TM0_REGC_BASE_ADDRESS + 0x008)

#define CPU_SYS_TM0_REGC_TMRCMP0_struct                                  rs_cpu_sys_tm0_regc_tmrcmp0

typedef struct _rs_cpu_sys_tm0_regc_tmrcmp0  rs_cpu_sys_tm0_regc_tmrcmp0;
struct _rs_cpu_sys_tm0_regc_tmrcmp0 {
    unsigned int TCVA0                                      :32;
};
#define cpu_sys_tm0_regc_tmrcmp0(val) ((rs_cpu_sys_tm0_regc_tmrcmp0*)&(val))



#define CPU_SYS_TM0_REGC_TMRIVL0                                         (HV_TM0_REGC_BASE_ADDRESS + 0x00C)

#define CPU_SYS_TM0_REGC_TMRIVL0_struct                                  rs_cpu_sys_tm0_regc_tmrivl0

typedef struct _rs_cpu_sys_tm0_regc_tmrivl0  rs_cpu_sys_tm0_regc_tmrivl0;
struct _rs_cpu_sys_tm0_regc_tmrivl0 {
    unsigned int TZCE0                                      : 1;
    unsigned int reserved                                   :14;
    unsigned int TIIE0                                      : 1;
    unsigned int reserved_1                                 :16;
};
#define cpu_sys_tm0_regc_tmrivl0(val) ((rs_cpu_sys_tm0_regc_tmrivl0*)&(val))



#define CPU_SYS_TM0_REGC_TMRDIV0                                         (HV_TM0_REGC_BASE_ADDRESS + 0x050)

#define CPU_SYS_TM0_REGC_TMRDIV0_struct                                  rs_cpu_sys_tm0_regc_tmrdiv0

typedef struct _rs_cpu_sys_tm0_regc_tmrdiv0  rs_cpu_sys_tm0_regc_tmrdiv0;
struct _rs_cpu_sys_tm0_regc_tmrdiv0 {
    unsigned int CCD0                                       : 3;
    unsigned int reserved                                   :29;
};
#define cpu_sys_tm0_regc_tmrdiv0(val) ((rs_cpu_sys_tm0_regc_tmrdiv0*)&(val))



#define CPU_SYS_TM0_REGC_TMRCNT0                                         (HV_TM0_REGC_BASE_ADDRESS + 0x0F0)

#define CPU_SYS_TM0_REGC_TMRCNT0_struct                                  rs_cpu_sys_tm0_regc_tmrcnt0

typedef struct _rs_cpu_sys_tm0_regc_tmrcnt0  rs_cpu_sys_tm0_regc_tmrcnt0;
struct _rs_cpu_sys_tm0_regc_tmrcnt0 {
    unsigned int TCNT0                                      :32;
};
#define cpu_sys_tm0_regc_tmrcnt0(val) ((rs_cpu_sys_tm0_regc_tmrcnt0*)&(val))



#define CPU_SYS_TM0_REGC_TMRC1                                           (HV_TM0_REGC_BASE_ADDRESS + 0x100)

#define CPU_SYS_TM0_REGC_TMRC1_struct                                    rs_cpu_sys_tm0_regc_tmrc1

typedef struct _rs_cpu_sys_tm0_regc_tmrc1  rs_cpu_sys_tm0_regc_tmrc1;
struct _rs_cpu_sys_tm0_regc_tmrc1 {
    unsigned int reserved                                   : 5;
    unsigned int CRE1                                       : 1;
    unsigned int CCDE1                                      : 1;
    unsigned int TCE1                                       : 1;
    unsigned int reserved_1                                 :24;
};
#define cpu_sys_tm0_regc_tmrc1(val) ((rs_cpu_sys_tm0_regc_tmrc1*)&(val))



#define CPU_SYS_TM0_REGC_TMRINT1                                         (HV_TM0_REGC_BASE_ADDRESS + 0x104)

#define CPU_SYS_TM0_REGC_TMRINT1_struct                                  rs_cpu_sys_tm0_regc_tmrint1

typedef struct _rs_cpu_sys_tm0_regc_tmrint1  rs_cpu_sys_tm0_regc_tmrint1;
struct _rs_cpu_sys_tm0_regc_tmrint1 {
    unsigned int TIIS1                                      : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_tm0_regc_tmrint1(val) ((rs_cpu_sys_tm0_regc_tmrint1*)&(val))



#define CPU_SYS_TM0_REGC_TMRCMP1                                         (HV_TM0_REGC_BASE_ADDRESS + 0x108)

#define CPU_SYS_TM0_REGC_TMRCMP1_struct                                  rs_cpu_sys_tm0_regc_tmrcmp1

typedef struct _rs_cpu_sys_tm0_regc_tmrcmp1  rs_cpu_sys_tm0_regc_tmrcmp1;
struct _rs_cpu_sys_tm0_regc_tmrcmp1 {
    unsigned int TCVA1                                      :32;
};
#define cpu_sys_tm0_regc_tmrcmp1(val) ((rs_cpu_sys_tm0_regc_tmrcmp1*)&(val))



#define CPU_SYS_TM0_REGC_TMRIVL1                                         (HV_TM0_REGC_BASE_ADDRESS + 0x10C)

#define CPU_SYS_TM0_REGC_TMRIVL1_struct                                  rs_cpu_sys_tm0_regc_tmrivl1

typedef struct _rs_cpu_sys_tm0_regc_tmrivl1  rs_cpu_sys_tm0_regc_tmrivl1;
struct _rs_cpu_sys_tm0_regc_tmrivl1 {
    unsigned int TZCE1                                      : 1;
    unsigned int reserved                                   :14;
    unsigned int TIIE1                                      : 1;
    unsigned int reserved_1                                 :16;
};
#define cpu_sys_tm0_regc_tmrivl1(val) ((rs_cpu_sys_tm0_regc_tmrivl1*)&(val))



#define CPU_SYS_TM0_REGC_TMRDIV1                                         (HV_TM0_REGC_BASE_ADDRESS + 0x150)

#define CPU_SYS_TM0_REGC_TMRDIV1_struct                                  rs_cpu_sys_tm0_regc_tmrdiv1

typedef struct _rs_cpu_sys_tm0_regc_tmrdiv1  rs_cpu_sys_tm0_regc_tmrdiv1;
struct _rs_cpu_sys_tm0_regc_tmrdiv1 {
    unsigned int CCD1                                       : 3;
    unsigned int reserved                                   :29;
};
#define cpu_sys_tm0_regc_tmrdiv1(val) ((rs_cpu_sys_tm0_regc_tmrdiv1*)&(val))



#define CPU_SYS_TM0_REGC_TMRCNT1                                         (HV_TM0_REGC_BASE_ADDRESS + 0x1F0)

#define CPU_SYS_TM0_REGC_TMRCNT1_struct                                  rs_cpu_sys_tm0_regc_tmrcnt1

typedef struct _rs_cpu_sys_tm0_regc_tmrcnt1  rs_cpu_sys_tm0_regc_tmrcnt1;
struct _rs_cpu_sys_tm0_regc_tmrcnt1 {
    unsigned int TCNT1                                      :32;
};
#define cpu_sys_tm0_regc_tmrcnt1(val) ((rs_cpu_sys_tm0_regc_tmrcnt1*)&(val))



#define CPU_SYS_TM0_REGC_TMRC2                                           (HV_TM0_REGC_BASE_ADDRESS + 0x200)

#define CPU_SYS_TM0_REGC_TMRC2_struct                                    rs_cpu_sys_tm0_regc_tmrc2

typedef struct _rs_cpu_sys_tm0_regc_tmrc2  rs_cpu_sys_tm0_regc_tmrc2;
struct _rs_cpu_sys_tm0_regc_tmrc2 {
    unsigned int reserved                                   : 5;
    unsigned int CRE2                                       : 1;
    unsigned int CCDE2                                      : 1;
    unsigned int TCE2                                       : 1;
    unsigned int reserved_1                                 :24;
};
#define cpu_sys_tm0_regc_tmrc2(val) ((rs_cpu_sys_tm0_regc_tmrc2*)&(val))



#define CPU_SYS_TM0_REGC_TMRINT2                                         (HV_TM0_REGC_BASE_ADDRESS + 0x204)

#define CPU_SYS_TM0_REGC_TMRINT2_struct                                  rs_cpu_sys_tm0_regc_tmrint2

typedef struct _rs_cpu_sys_tm0_regc_tmrint2  rs_cpu_sys_tm0_regc_tmrint2;
struct _rs_cpu_sys_tm0_regc_tmrint2 {
    unsigned int TIIS2                                      : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_tm0_regc_tmrint2(val) ((rs_cpu_sys_tm0_regc_tmrint2*)&(val))



#define CPU_SYS_TM0_REGC_TMRCMP2                                         (HV_TM0_REGC_BASE_ADDRESS + 0x208)

#define CPU_SYS_TM0_REGC_TMRCMP2_struct                                  rs_cpu_sys_tm0_regc_tmrcmp2

typedef struct _rs_cpu_sys_tm0_regc_tmrcmp2  rs_cpu_sys_tm0_regc_tmrcmp2;
struct _rs_cpu_sys_tm0_regc_tmrcmp2 {
    unsigned int TCVA2                                      :32;
};
#define cpu_sys_tm0_regc_tmrcmp2(val) ((rs_cpu_sys_tm0_regc_tmrcmp2*)&(val))



#define CPU_SYS_TM0_REGC_TMRIVL2                                         (HV_TM0_REGC_BASE_ADDRESS + 0x20C)

#define CPU_SYS_TM0_REGC_TMRIVL2_struct                                  rs_cpu_sys_tm0_regc_tmrivl2

typedef struct _rs_cpu_sys_tm0_regc_tmrivl2  rs_cpu_sys_tm0_regc_tmrivl2;
struct _rs_cpu_sys_tm0_regc_tmrivl2 {
    unsigned int TZCE2                                      : 1;
    unsigned int reserved                                   :14;
    unsigned int TIIE2                                      : 1;
    unsigned int reserved_1                                 :16;
};
#define cpu_sys_tm0_regc_tmrivl2(val) ((rs_cpu_sys_tm0_regc_tmrivl2*)&(val))



#define CPU_SYS_TM0_REGC_TMRDIV2                                         (HV_TM0_REGC_BASE_ADDRESS + 0x250)

#define CPU_SYS_TM0_REGC_TMRDIV2_struct                                  rs_cpu_sys_tm0_regc_tmrdiv2

typedef struct _rs_cpu_sys_tm0_regc_tmrdiv2  rs_cpu_sys_tm0_regc_tmrdiv2;
struct _rs_cpu_sys_tm0_regc_tmrdiv2 {
    unsigned int CCD2                                       : 3;
    unsigned int reserved                                   :29;
};
#define cpu_sys_tm0_regc_tmrdiv2(val) ((rs_cpu_sys_tm0_regc_tmrdiv2*)&(val))



#define CPU_SYS_TM0_REGC_TMRCNT2                                         (HV_TM0_REGC_BASE_ADDRESS + 0x2F0)

#define CPU_SYS_TM0_REGC_TMRCNT2_struct                                  rs_cpu_sys_tm0_regc_tmrcnt2

typedef struct _rs_cpu_sys_tm0_regc_tmrcnt2  rs_cpu_sys_tm0_regc_tmrcnt2;
struct _rs_cpu_sys_tm0_regc_tmrcnt2 {
    unsigned int TCNT2                                      :32;
};
#define cpu_sys_tm0_regc_tmrcnt2(val) ((rs_cpu_sys_tm0_regc_tmrcnt2*)&(val))



#define CPU_SYS_TM0_REGC_TMRC3                                           (HV_TM0_REGC_BASE_ADDRESS + 0x300)

#define CPU_SYS_TM0_REGC_TMRC3_struct                                    rs_cpu_sys_tm0_regc_tmrc3

typedef struct _rs_cpu_sys_tm0_regc_tmrc3  rs_cpu_sys_tm0_regc_tmrc3;
struct _rs_cpu_sys_tm0_regc_tmrc3 {
    unsigned int reserved                                   : 5;
    unsigned int CRE3                                       : 1;
    unsigned int CCDE3                                      : 1;
    unsigned int TCE3                                       : 1;
    unsigned int reserved_1                                 :24;
};
#define cpu_sys_tm0_regc_tmrc3(val) ((rs_cpu_sys_tm0_regc_tmrc3*)&(val))



#define CPU_SYS_TM0_REGC_TMRINT3                                         (HV_TM0_REGC_BASE_ADDRESS + 0x304)

#define CPU_SYS_TM0_REGC_TMRINT3_struct                                  rs_cpu_sys_tm0_regc_tmrint3

typedef struct _rs_cpu_sys_tm0_regc_tmrint3  rs_cpu_sys_tm0_regc_tmrint3;
struct _rs_cpu_sys_tm0_regc_tmrint3 {
    unsigned int TIIS3                                      : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_tm0_regc_tmrint3(val) ((rs_cpu_sys_tm0_regc_tmrint3*)&(val))



#define CPU_SYS_TM0_REGC_TMRCMP3                                         (HV_TM0_REGC_BASE_ADDRESS + 0x308)

#define CPU_SYS_TM0_REGC_TMRCMP3_struct                                  rs_cpu_sys_tm0_regc_tmrcmp3

typedef struct _rs_cpu_sys_tm0_regc_tmrcmp3  rs_cpu_sys_tm0_regc_tmrcmp3;
struct _rs_cpu_sys_tm0_regc_tmrcmp3 {
    unsigned int TCVA3                                      :32;
};
#define cpu_sys_tm0_regc_tmrcmp3(val) ((rs_cpu_sys_tm0_regc_tmrcmp3*)&(val))



#define CPU_SYS_TM0_REGC_TMRIVL3                                         (HV_TM0_REGC_BASE_ADDRESS + 0x30C)

#define CPU_SYS_TM0_REGC_TMRIVL3_struct                                  rs_cpu_sys_tm0_regc_tmrivl3

typedef struct _rs_cpu_sys_tm0_regc_tmrivl3  rs_cpu_sys_tm0_regc_tmrivl3;
struct _rs_cpu_sys_tm0_regc_tmrivl3 {
    unsigned int TZCE3                                      : 1;
    unsigned int reserved                                   :14;
    unsigned int TIIE3                                      : 1;
    unsigned int reserved_1                                 :16;
};
#define cpu_sys_tm0_regc_tmrivl3(val) ((rs_cpu_sys_tm0_regc_tmrivl3*)&(val))



#define CPU_SYS_TM0_REGC_TMRDIV3                                         (HV_TM0_REGC_BASE_ADDRESS + 0x350)

#define CPU_SYS_TM0_REGC_TMRDIV3_struct                                  rs_cpu_sys_tm0_regc_tmrdiv3

typedef struct _rs_cpu_sys_tm0_regc_tmrdiv3  rs_cpu_sys_tm0_regc_tmrdiv3;
struct _rs_cpu_sys_tm0_regc_tmrdiv3 {
    unsigned int CCD3                                       : 3;
    unsigned int reserved                                   :29;
};
#define cpu_sys_tm0_regc_tmrdiv3(val) ((rs_cpu_sys_tm0_regc_tmrdiv3*)&(val))



#endif