/**
 * @file hv_cal_Osd.c
 * @brief Osd Cal entrance c file.
 * @details This file provides the following functions: \n
 *          (1) Osd CAL layer initialization functions \n
 *
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-31
 * @copyright Copyright(c),2022-8, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author         <th>Date        <th>Change Description
 * <tr><td>OSD Group      <td>2022-08-31   <td>create
 * </table>
*/

#include "hv_drv_Osd.h"
#include "hv_cal_Osd.h"


VOID Hv_Cal_Osd_TimeDelayMs(UINT32 uiDelayMs)
{
    UINT32 uiCount = 0;
    UINT32 uiMulti = 1000;
    for (uiCount = 0; uiCount < uiDelayMs * 34 * uiMulti; uiCount++)
    {
        __asm__("nop");
    }
}

UCHAR8 Hv_Cal_Osd_GetPixelBits(OsdPixelFormat enFormat)
{
    switch (enFormat)
    {
        case OSD_PIXEL_FORMAT_RGBA8888:
        {
            return 32;
        }
        case OSD_PIXEL_FORMAT_RGBA4444:
        {
            return 16;
        }
        case OSD_PIXEL_FORMAT_RGB565:
        {
            return 16;
        }
        case OSD_PIXEL_FORMAT_Alpha8:
        {
            return 8;
        }
        case OSD_PIXEL_FORMAT_Alpha4:
        {
            return 4;
        }
        case OSD_PIXEL_FORMAT_RGB888:
        {
            return 24;
        }
        default:
        {
            break;
        }
    }

    return 16;
}

VOID Hv_Cal_Osd_InitSync(VOID)
{
    HV_W32_FIELD(DISP_TOP_KOSD_TOP_00, reg_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_03_00, reg_03_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_03_00, reg_03_en, 0);

    HV_W32_FIELD(DISP_TOP_DPU_RVDM_02_4C, reg_02_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_02_4C, reg_02_en, 0);

    HV_W32_FIELD(DISP_TOP_DPU_RVDM_04_4C, reg_04_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_04_4C, reg_04_en, 0);

    /* scaler */
    HV_W32_FIELD(DISP_TOP_REG_OSD_CUBIC_SCALER_V2_00_00, reg_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_REG_OSD_CUBIC_SCALER_V2_00_00, reg_en, 0);

    /* dpu_ldg_sync */
    HV_W32_FIELD(DISP_TOP_DPU_LDG_SYNC_00, reg_en, 1);
    HV_W32_FIELD(DISP_TOP_DPU_LDG_SYNC_00, reg_en_no_latch, 0);

    HV_W32_FIELD(DISP_TOP_DPU_LDG_SYNC_04, reg_ld_ref_vdly, 1);
    // same as above
    HV_W32_FIELD(DISP_TOP_DPU_SR_SYNC_RW3, reg_sr_sync_data_trig_vdly, 1);
    HV_W32_FIELD(DISP_TOP_DPU_LDG_SYNC_08, reg_ld_osd_ref_vdly, 0);
}

VOID Hv_Cal_OsdInit(VOID)
{

    Hv_Cal_OsdDDR_Init();

    Hv_Cal_OsdDP_Init();

    Hv_Cal_OsdGraphic_Init();

    Hv_Cal_OsdBlend_Init();

    Hv_Cal_OsdScaler_Init();

    Hv_Cal_OsdWindow_Init();
}
