/**
 * @file hv_cal_DpuMainScaler.h
 * @brief Header file of mute module.
 *
 * @verbatim
 * ==============================================================================
 *                        ##### How to use #####
 * ==============================================================================
 *
 * @endverbatim
 *
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-22
 */

#ifndef __HV_CAL_DPU_MAIN_SCALER_H__
#define __HV_CAL_DPU_MAIN_SCALER_H__

#include "hv_comm_DataType.h"
//#include "hv_cal_DpuScaler.h"
#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Define.h"



VOID Hv_Cal_DpuScaler_Init(const PanelParam stPanelParam);
VOID Hv_Cal_DpuScaler_ResetClock_Enable(VOID);

VOID Hv_Cal_DpuScaler_DtcTopTimingParam(const DpuDtcTopTimingParam* pstDpuDtcTopTimingParam);
VOID Hv_Cal_DpuScaler_DtcFrameSyncHtotal(USHORT16 usHtotal);

/*DTC config settings begin*/
VOID Hv_Cal_DpuScaler_DtcClkDelayConfig(const VideoConfigParams* pstVideoConfigParams, DpuDtcTopTimingParam* pstDpuDtcTopTimingParam);

VOID Hv_Cal_DpuScaler_DtcTimingSel(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcFrameSyncVrrModeEn(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_DtcTxVdeDummyNum(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_DtcReset(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_DtcMainWindowHstart(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcMainWindowHend(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcMainWindowVstart(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcMainWindowVend(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcFrcBufNum01(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcFrcRdDoneTh01(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcFrcWrDoneTh01(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DtcDelayMode(UCHAR8 ucValue);
/*DTC config settings end*/
/***********Dpu cap vgsf settings begin*********************/
/*main patt start*/

#ifdef HV_SCALER_DEBUG_VERSION
VOID Hv_Cal_DpuScaler_CapVgsfPattSettingsMain(const VideoConfigParams* pstVideoConfigParams);
#endif

/*cap ip enable*/
VOID Hv_Cal_DpuScaler_CapVgsfMainInCutEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainOutCutEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC02ClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC02Enable(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC02DeEnable(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC24ClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainCs1FuncClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainCs1En(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrSwitch(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainCsc2ClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainCsc2ConvertOn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapMsfFuncClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC42FuncClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC42On(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC20FuncClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_CapVgsfMainC20Enable(BOOL bEn);

VOID Hv_Cal_DpuScaler_CapVgsfMainC20CbCrPosAdjEnable(BOOL bEn);
/*cap ip dynamic config start*/
VOID Hv_Cal_DpuScaler_SetCapVgsfMainInCutParam(DpuCapCutParam* pstDpuCapCutParam);
VOID Hv_Cal_DpuScaler_SetCapVgsfMainOutCutParam(DpuCapCutParam* pstDpuCapCutParam);
VOID Hv_Cal_DpuScaler_CapVgsfMainCapInSize(UINT32 uiRxInHact, UINT32 uiRxInVact);
VOID Hv_Cal_DpuScaler_CapVgsfMainInOutSize(const VideoConfigParams* pstVideoConfigParams);
VOID Hv_Cal_DpuScaler_CapVgsfMainCsc2ConvertMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainCaVgMsfYhMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainCaVgMsfYvMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainScfDown(BOOL bCprMode, const DpucScalerParam* pstDpucScalerParam);
/*cap ip dynamic config end*/

/*cap vgsf csc1 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfMainCsc1Config(const VideoConfigParams* pstVideoConfigParams);
BOOL Hv_Cal_DpuScaler_GetCapVgsfMainCsc1FunctionOn();
/*cap vgsf csc1 setting end*/

/*****************dpc srp  settings begin*****************/
VOID Hv_Cal_DpuScaler_DpcSrpMainUpkWidth(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpMainUpkHeight(UINT32 uiValue);
/*****************dpc srp  settings end*****************/

/***********srp top main settings begin*********************/
VOID Hv_Cal_DpuScaler_SrpTopMainSrPassthrough(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopMainSrSpatOn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopMainSrSpatMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopMainSrSpatWith(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopMainC02Config(const VideoConfigParams* pstVideoConfigParams);
VOID Hv_Cal_DpuScaler_SrpTopMainSrC24Config(const VideoConfigParams* pstVideoConfigParams);
VOID Hv_Cal_DpuScaler_SrpTopMainConfig(const VideoConfigParams* pstVideoConfigParams);
VOID Hv_Cal_DpuScaler_SrpTopMainScHfilbase(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopMainScVfilbase(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopMainScHflip(UINT32 uiValue);
/***********srp top settings end*********************/


/*****************vdm settings begin**************************/
VOID Hv_Cal_DpuScaler_DpuWvdm00WrEnable(BOOL bEn);
VOID Hv_Cal_DpuScaler_DpuRvdm00RdEnable(BOOL bEn);
VOID Hv_Cal_DpuScaler_DpuVdmMainConfig(const DpuVdmConfigSettings *pstDpuVdmConfigSettings);
VOID Hv_Cal_DpuScaler_MainReadFreezeEn(BOOL bEn);
/*****************vdm settings end*****************************/

/*****************sub ldg top settings begin***************************/
/*common config*/
VOID Hv_Cal_DpuScaler_SubLdgTopByPass(UINT32 uiValue);
/*main*/
VOID Hv_Cal_DpuScaler_SubLdgTopMainCscEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopMainBlendEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopMainBorderEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopBorderMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopVsReleaseBlackEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertColor(UCHAR8 ucR, UCHAR8 ucG, UCHAR8 ucB);
VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopldgMtxThrough(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertFwMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertFwEnable(UINT32 uiValue);
UINT32 Hv_Cal_DpuScaler_GetSubLdgTopBlackInsertFwMode();
UINT32 Hv_Cal_DpuScaler_GetSubLdgTopBlackInsertFwEnable();
/*****************sub ldg top settings end***************************/

VOID Hv_Cal_DpuScaler_SetPortMux(UINT32 uiValue);
UINT32 Hv_Cal_DpuScaler_GetPortMux();

VOID Hv_Cal_DpuScaler_ScMainPvosPs0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScMainPvosPs1(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScMainFeildSel(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScMainFeildPolar(UINT32 uiValue);

/********************PQ begin************************/
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrPassthrough(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrGmiEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrGmdEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrLutGmiEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrLutOotfEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrLutGmdEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrGmiPatternEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrPattern(UINT32 uiR, UINT32 uiG, UINT32 uiB);

VOID Hv_Cal_DpuScaler_DpuVdmTblRdMainEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpuVdmTblRdMainTblTblEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrOotfEnable(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_ScMainPhosPsA0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScMainPhosPsB0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScMainOrfCrlev(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScMainOrfCblev(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScMainOrfYlev(UINT32 uiValue);
/********************PQ end************************/
VOID Hv_Cal_DpuScaler_GetDpuInt(DpuInterruptDefine* pstDpuInterrupt);
VOID Hv_Cal_DpuScaler_ClearDpuInt();
VOID Hv_Cal_DpuScaler_GetDtcInt(DtcInterruptDefine* pstDtcInterrupt);
VOID Hv_Cal_DpuScaler_ClearDtcInt();
VOID Hv_Cal_DpuScaler_GetHsIpInt(DisplayInterruptType enType, HsIpInterruptDefine* pstHsIpInterrupt);
VOID Hv_Cal_DpuScaler_ClearHsIpInt(DisplayInterruptType enType);
VOID Hv_Cal_DpuScaler_SendRemainKspiDataInISR();
VOID Hv_Cal_DpuScaler_DtcClockConfig(VOID);

UINT32 Hv_Cal_DpuScaler_GetDpcCapMainSyncHtotal();
VOID Hv_Cal_DpuScaler_SetIntDispEnHs24(UINT32 uiValue);
UINT32 Hv_Cal_DpuScaler_GetFrmsyncState(VOID);
UINT32 Hv_Cal_DpuScaler_GetDtcState(VOID);
UINT32 Hv_Cal_DpuScaler_GetFrcWindex(VOID);
UINT32 Hv_Cal_DpuScaler_GetFrcRindex(VOID);
UINT32 Hv_Cal_DpuScaler_GetFrcBufStatus(VOID);
VOID Hv_Cal_DpuScaler_SetMainFrcIndexStart(BOOL bStart);
VOID Hv_Cal_DpuScaler_SetMainFrcOverWrite(BOOL bEn);
VOID Hv_Cal_DpuScaler_SetLineInt(UCHAR8 ucIndex, USHORT16 usLine);
VOID Hv_Cal_DpuScaler_SetLineIntEn(UINT32 uiEn);
VOID Hv_Cal_DpuScaler_SetDpuInt(UCHAR8 ucEn);
USHORT16 Hv_Cal_DpuScaler_GetDtcVtotal(VOID);
VOID Hv_Cal_DpuScaler_SetLdgLatch(BOOL bEn);
VOID Hv_Cal_DpuScaler_SetMainChannelState(USHORT16 usState);
VOID Hv_Cal_DpuScaler_SetSubChannelState(USHORT16 usState);
VOID Hv_Cal_DpuScaler_SetMianFrcIndexFwMode(BOOL bEn);
VOID Hv_Cal_DpuScaler_SetSeamlessSwitchFlag(BOOL bEn);
VOID Hv_Cal_DpuScaler_ToggleMainFrcReadIndex(VOID);
#if (HV_CONFIG_ON == HV_PROJECT_CONFIG_DPU_BRIGHT_FRAME)
VOID Hv_Cal_DpuScaler_MainFrcLowLatencyMode(BOOL bEn, UINT32 uiVact);
BOOL Hv_Cal_DpuScaler_GetBrightFrameLowLatency(VOID);
VOID Hv_Cal_DpuScaler_SetBrightFrameLowLatency(BOOL bEn);
#endif
#endif
