#ifndef _HV_PAGE_HT7315_HDMI21_RX20_PRE_PROC_REG_00_H_
#define _HV_PAGE_HT7315_HDMI21_RX20_PRE_PROC_REG_00_H_

#ifndef HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS
    #define HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS                                         0x1104D200
#endif


#define RX_HDMI21_RX20_PRE_PROC_REG_00_00                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_00_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_00

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_00  rs_rx_hdmi21_rx20_pre_proc_reg_00_00;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_00 {
    unsigned int reg_00_hd21rx_hd20_enable                  : 1;
    unsigned int reg_00_hd21rx_hd21_enable                  : 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_hd21rx_lane_valid                   : 4;
    unsigned int reg_00_hd21rx_lane_valid_bf_swp            : 4;
    unsigned int reserved_1                                 :20;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_00(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_00*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_04                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_04_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_04

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_04  rs_rx_hdmi21_rx20_pre_proc_reg_00_04;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_04 {
    unsigned int reg_00_hd21rx20_aln_cnt                    : 9;
    unsigned int reg_00_hd21rx20_aln_rst                    : 1;
    unsigned int reg_00_hd21rx20_aln_alys_on                : 1;
    unsigned int reg_00_hd21rx20_aln_sw_en                  : 3;
    unsigned int reg_00_hd21rx20_aln_change_flag_clr        : 1;
    unsigned int reserved                                   :17;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_04(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_04*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_08                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_08_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_08

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_08  rs_rx_hdmi21_rx20_pre_proc_reg_00_08;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_08 {
    unsigned int reg_00_hd21rx20_aln_sw_value0              : 4;
    unsigned int reg_00_hd21rx20_aln_sw_value1              : 4;
    unsigned int reg_00_hd21rx20_aln_sw_value2              : 4;
    unsigned int reserved                                   :20;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_08(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_08*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_18                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_18_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_18

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_18  rs_rx_hdmi21_rx20_pre_proc_reg_00_18;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_18 {
    unsigned int reg_00_hd21rx20_deskew_preamble_num        : 6;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_hd21rx20_deskew_max                 : 5;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_hd21rx20_deskew_keep_cnt            : 8;
    unsigned int reg_00_hd21rx20_deskew_bypass_en           : 1;
    unsigned int reg_00_hd21rx20_deskew_cnt_clr_en          : 1;
    unsigned int reg_00_hd21rx20_deskew_sw_en               : 1;
    unsigned int reserved_2                                 : 5;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_18(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_18*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_1C                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_1C_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_1c

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_1c  rs_rx_hdmi21_rx20_pre_proc_reg_00_1c;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_1c {
    unsigned int reg_00_hd21rx20_deskew_sw_value0           : 4;
    unsigned int reg_00_hd21rx20_deskew_sw_value1           : 4;
    unsigned int reg_00_hd21rx20_deskew_sw_value2           : 4;
    unsigned int reserved                                   :20;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_1c(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_1c*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_30                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x30)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_30_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_30

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_30  rs_rx_hdmi21_rx20_pre_proc_reg_00_30;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_30 {
    unsigned int regr_00_phy_cr_done                        : 4;
    unsigned int reserved                                   :16;
    unsigned int regr_00_hd21rx20_aln_ch_lock               : 3;
    unsigned int reserved_1                                 : 1;
    unsigned int regr_00_hd21rx20_aln_change_flag           : 3;
    unsigned int reserved_2                                 : 5;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_30(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_30*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_34                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_34_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_34

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_34  rs_rx_hdmi21_rx20_pre_proc_reg_00_34;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_34 {
    unsigned int regr_00_hd21rx20_aln_hw_value0             : 4;
    unsigned int regr_00_hd21rx20_aln_hw_value1             : 4;
    unsigned int regr_00_hd21rx20_aln_hw_value2             : 4;
    unsigned int reserved                                   :20;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_34(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_34*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_38                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_38_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_38

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_38  rs_rx_hdmi21_rx20_pre_proc_reg_00_38;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_38 {
    unsigned int regr_00_hd21rx20_lane0_deskew_num          : 5;
    unsigned int regr_00_hd21rx20_lane1_deskew_num          : 5;
    unsigned int regr_00_hd21rx20_lane2_deskew_num          : 5;
    unsigned int regr_00_hd21rx20_lane_deskew_lock          : 1;
    unsigned int reserved                                   :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_38(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_38*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_3C                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_3C_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_3c

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_3c  rs_rx_hdmi21_rx20_pre_proc_reg_00_3c;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_3c {
    unsigned int reg_00_hd21rx_afifo_hw_auto_clr_on         : 1;
    unsigned int reg_00_hd21rx_afifo_rd_thd                 : 3;
    unsigned int reg_00_hd21rx_afifo_clr                    : 1;
    unsigned int reg_00_hd21rx_afifo_filter_thd             : 5;
    unsigned int reserved                                   :22;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_3c(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_3c*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_40                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x40)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_40_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_40

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_40  rs_rx_hdmi21_rx20_pre_proc_reg_00_40;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_40 {
    unsigned int regr_00_phy_lane0_data                     :18;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_40(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_40*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_44                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x44)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_44_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_44

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_44  rs_rx_hdmi21_rx20_pre_proc_reg_00_44;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_44 {
    unsigned int regr_00_phy_lane1_data                     :18;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_44(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_44*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_48                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x48)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_48_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_48

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_48  rs_rx_hdmi21_rx20_pre_proc_reg_00_48;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_48 {
    unsigned int regr_00_phy_lane2_data                     :18;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_48(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_48*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_4C                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x4C)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_4C_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_4c

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_4c  rs_rx_hdmi21_rx20_pre_proc_reg_00_4c;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_4c {
    unsigned int regr_00_phy_lane3_data                     :18;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_4c(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_4c*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_68                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x68)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_68_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_68

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_68  rs_rx_hdmi21_rx20_pre_proc_reg_00_68;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_68 {
    unsigned int reg_00_hd21rx_phy_mon_enable               : 6;
    unsigned int reg_00_hd21rx_phy_mon_sel                  : 8;
    unsigned int reg_00_hd21rx_phy_mon_clr                  : 1;
    unsigned int reg_00_hd21rx_phy_mon_axi_enable           : 1;
    unsigned int reg_00_hd21rx_phy_mon_debug_sel            : 8;
    unsigned int reg_00_hd21rx_phy_mon_axi_length           : 8;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_68(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_68*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_6C                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x6C)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_6C_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_6c

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_6c  rs_rx_hdmi21_rx20_pre_proc_reg_00_6c;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_6c {
    unsigned int reg_00_hd21rx_phy_mon_axi_st_addr          :32;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_6c(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_6c*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_70                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x70)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_70_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_70

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_70  rs_rx_hdmi21_rx20_pre_proc_reg_00_70;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_70 {
    unsigned int reg_00_hd21rx_phy_mon_axi_ed_addr          :32;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_70(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_70*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_74                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x74)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_74_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_74

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_74  rs_rx_hdmi21_rx20_pre_proc_reg_00_74;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_74 {
    unsigned int reg_00_tmdsrx_auto_eq_permit_enable        : 1;
    unsigned int reg_00_tmdsrx_code_err_auto_phy_init_en    : 1;
    unsigned int reg_00_tmdsrx_clk_not_good_auto_phy_init_en: 1;
    unsigned int reg_00_tmdsrx_phy_config_bypass            : 1;
    unsigned int reg_00_tmdsrx_phy_init_bypass              : 1;
    unsigned int reg_00_tmdsrx_check_crdone0_bypass         : 1;
    unsigned int reg_00_tmdsrx_check_ckgood0_bypass         : 1;
    unsigned int reg_00_tmdsrx_check_aln0_bypass            : 1;
    unsigned int reg_00_tmdsrx_check_crdone1_bypass         : 1;
    unsigned int reg_00_tmdsrx_check_ckgood1_bypass         : 1;
    unsigned int reg_00_tmdsrx_check_aln1_bypass            : 1;
    unsigned int reg_00_tmdsrx_check_deskew_bypass          : 1;
    unsigned int reg_00_tmdsrx_check_eqdone_bypass          : 1;
    unsigned int reg_00_tmdsrx_dfe_permit_bypass            : 1;
    unsigned int reg_00_tmdsrx_eq_permit0_bypass            : 1;
    unsigned int reg_00_tmdsrx_eq_permit1_bypass            : 1;
    unsigned int reg_00_tmdsrx_phy_config_sw_trig           : 1;
    unsigned int reg_00_tmdsrx_eq_permit_sw_trig            : 1;
    unsigned int reg_00_tmdsrx_phy_config_done              : 1;
    unsigned int reg_00_tmdsrx_link_training_mode           : 1;
    unsigned int reserved                                   : 4;
    unsigned int reg_00_tmdsrx_cycle_oscclk_phy_init        : 8;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_74(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_74*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_78                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x78)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_78_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_78

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_78  rs_rx_hdmi21_rx20_pre_proc_reg_00_78;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_78 {
    unsigned int reg_00_tmdsrx_cycle_oscclk_eq_permit       : 8;
    unsigned int reg_00_tmdsrx_cycle_oscclk_dfe_permit      : 8;
    unsigned int reg_00_tmdsrx_cycle_oscclk_x64_crdone_timeout:16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_78(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_78*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_7C                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x7C)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_7C_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_7c

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_7c  rs_rx_hdmi21_rx20_pre_proc_reg_00_7c;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_7c {
    unsigned int reg_00_tmdsrx_cycle_oscclk_x64_ckgood_timeout:16;
    unsigned int reg_00_tmdsrx_cycle_oscclk_x64_aln_timeout :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_7c(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_7c*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_80                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x80)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_80_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_80

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_80  rs_rx_hdmi21_rx20_pre_proc_reg_00_80;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_80 {
    unsigned int reg_00_tmdsrx_cycle_oscclk_x64_deskew_timeout:16;
    unsigned int reg_00_tmdsrx_cycle_oscclk_x64_eqdone_timeout:16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_80(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_80*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_84                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x84)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_84_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_84

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_84  rs_rx_hdmi21_rx20_pre_proc_reg_00_84;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_84 {
    unsigned int reg_00_tmdsrx_cycle_oscclk_x64_check_clk_time:16;
    unsigned int reserved                                   :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_84(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_84*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_88                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x88)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_88_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_88

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_88  rs_rx_hdmi21_rx20_pre_proc_reg_00_88;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_88 {
    unsigned int reg_00_tmdsrx_cycle_oscclk_x64_autoeq_err_det:20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_88(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_88*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_8C                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0x8C)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_8C_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_8c

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_8c  rs_rx_hdmi21_rx20_pre_proc_reg_00_8c;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_8c {
    unsigned int reg_00_tmdsrx_eq_permit_err_th             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_tmdsrx_phy_init_err_th              :15;
    unsigned int reg_00_tmdsrx_auto_eq_debug_clr            : 1;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_8c(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_8c*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_AC                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xAC)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_AC_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_ac

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_ac  rs_rx_hdmi21_rx20_pre_proc_reg_00_ac;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_ac {
    unsigned int reg_00_hd21rx_clkdet_frq_low_th_phy_tmds   :16;
    unsigned int reg_00_hd21rx_clkdet_frq_high_th_phy_tmds  :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_ac(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_ac*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_B0                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xB0)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_B0_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_b0

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_b0  rs_rx_hdmi21_rx20_pre_proc_reg_00_b0;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_b0 {
    unsigned int reg_00_hd21rx_clkdet_window_size           :16;
    unsigned int reg_00_hd21rx_clkdet_window_stable         : 8;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_b0(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_b0*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_B4                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xB4)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_B4_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_b4

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_b4  rs_rx_hdmi21_rx20_pre_proc_reg_00_b4;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_b4 {
    unsigned int reg_00_hd21rx_clkdet_frq_low_th            :16;
    unsigned int reg_00_hd21rx_clkdet_frq_high_th           :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_b4(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_b4*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_B8                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xB8)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_B8_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_b8

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_b8  rs_rx_hdmi21_rx20_pre_proc_reg_00_b8;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_b8 {
    unsigned int reg_00_hd21rx_clkdet_frq_good_en           : 6;
    unsigned int reg_00_hd21rx_clkdet_frq_good_sel          : 1;
    unsigned int reg_00_hd21rx_clkdet_frq_good_sw           : 1;
    unsigned int reserved                                   :24;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_b8(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_b8*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_BC                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xBC)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_BC_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_bc

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_bc  rs_rx_hdmi21_rx20_pre_proc_reg_00_bc;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_bc {
    unsigned int regr_00_hd21rx_lane_clk_frq_0              :16;
    unsigned int regr_00_hd21rx_lane_clk_frq_1              :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_bc(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_bc*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_C0                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xC0)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_C0_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_c0

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_c0  rs_rx_hdmi21_rx20_pre_proc_reg_00_c0;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_c0 {
    unsigned int regr_00_hd21rx_lane_clk_frq_2              :16;
    unsigned int regr_00_hd21rx_lane_clk_frq_3              :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_c0(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_c0*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_C4                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xC4)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_C4_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_c4

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_c4  rs_rx_hdmi21_rx20_pre_proc_reg_00_c4;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_c4 {
    unsigned int regr_00_hd21rx_tmds_clk_frq                :16;
    unsigned int regr_00_hd21rx_phy_tmds_clk_frq            :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_c4(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_c4*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_C8                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xC8)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_C8_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_c8

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_c8  rs_rx_hdmi21_rx20_pre_proc_reg_00_c8;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_c8 {
    unsigned int regr_00_hd21rx_lane_clk_state_0            : 3;
    unsigned int regr_00_hd21rx_lane_clk_state_1            : 3;
    unsigned int regr_00_hd21rx_lane_clk_state_2            : 3;
    unsigned int regr_00_hd21rx_lane_clk_state_3            : 3;
    unsigned int regr_00_hd21rx_tmds_clk_state              : 3;
    unsigned int regr_00_hd21rx_phy_tmds_clk_state          : 3;
    unsigned int regr_00_hd21rx_clk_frq_good                : 1;
    unsigned int reserved                                   : 9;
    unsigned int regr_00_tmdsrx_auto_eq_ctrl_state          : 4;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_c8(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_c8*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_CC                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xCC)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_CC_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_cc

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_cc  rs_rx_hdmi21_rx20_pre_proc_reg_00_cc;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_cc {
    unsigned int regr_00_hd21rx_phy_afifo0_wdepth           : 6;
    unsigned int regr_00_hd21rx_phy_afifo1_wdepth           : 6;
    unsigned int regr_00_hd21rx_phy_afifo2_wdepth           : 6;
    unsigned int regr_00_hd21rx_phy_afifo3_wdepth           : 6;
    unsigned int regr_00_hd21rx_phy_afifo_valid             : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_hd21rx_lane_valid_sync             : 1;
    unsigned int reserved_1                                 : 2;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_cc(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_cc*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_D0                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xD0)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_D0_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_d0

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_d0  rs_rx_hdmi21_rx20_pre_proc_reg_00_d0;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_d0 {
    unsigned int regr_00_hd21rx_phy_mon_debug_data_0        :32;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_d0(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_d0*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_D4                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xD4)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_D4_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_d4

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_d4  rs_rx_hdmi21_rx20_pre_proc_reg_00_d4;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_d4 {
    unsigned int regr_00_hd21rx_phy_mon_debug_data_1        :32;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_d4(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_d4*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_D8                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xD8)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_D8_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_d8

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_d8  rs_rx_hdmi21_rx20_pre_proc_reg_00_d8;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_d8 {
    unsigned int regr_00_hd21rx_phy_mon_debug_data_2        :32;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_d8(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_d8*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_DC                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xDC)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_DC_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_dc

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_dc  rs_rx_hdmi21_rx20_pre_proc_reg_00_dc;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_dc {
    unsigned int regr_00_hd21rx_phy_mon_debug_data_3        :32;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_dc(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_dc*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_E0                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xE0)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_E0_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_e0

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_e0  rs_rx_hdmi21_rx20_pre_proc_reg_00_e0;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_e0 {
    unsigned int regr_00_tmdsrx_auto_eq_debug_phy_init_cnt  : 8;
    unsigned int regr_00_tmdsrx_auto_eq_debug_eq_permit_cnt : 8;
    unsigned int reserved                                   :16;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_e0(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_e0*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_F0                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xF0)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_F0_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_f0

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_f0  rs_rx_hdmi21_rx20_pre_proc_reg_00_f0;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_f0 {
    unsigned int regr_00_hd21rx_rx20_werdet0                :15;
    unsigned int regr_00_hd21rx_rx20_werdet0_vld            : 1;
    unsigned int regr_00_hd21rx_rx20_werdet1                :15;
    unsigned int regr_00_hd21rx_rx20_werdet1_vld            : 1;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_f0(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_f0*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_F4                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xF4)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_F4_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_f4

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_f4  rs_rx_hdmi21_rx20_pre_proc_reg_00_f4;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_f4 {
    unsigned int regr_00_hd21rx_rx20_werdet2                :15;
    unsigned int regr_00_hd21rx_rx20_werdet2_vld            : 1;
    unsigned int regr_00_tmdsrx_auto_eq_err_value_ch0       :15;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_f4(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_f4*)&(val))



#define RX_HDMI21_RX20_PRE_PROC_REG_00_F8                                (HV_HDMI21_RX20_PRE_PROC_REG_00_BASE_ADDRESS + 0xF8)

#define RX_HDMI21_RX20_PRE_PROC_REG_00_F8_struct                         rs_rx_hdmi21_rx20_pre_proc_reg_00_f8

typedef struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_f8  rs_rx_hdmi21_rx20_pre_proc_reg_00_f8;
struct _rs_rx_hdmi21_rx20_pre_proc_reg_00_f8 {
    unsigned int regr_00_tmdsrx_auto_eq_err_value_ch1       :15;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_tmdsrx_auto_eq_err_value_ch2       :15;
    unsigned int reserved_1                                 : 1;
};
#define rx_hdmi21_rx20_pre_proc_reg_00_f8(val) ((rs_rx_hdmi21_rx20_pre_proc_reg_00_f8*)&(val))



#endif