#ifndef _HV_PAGE_HT7315_DPU_CA_SYNC_00_H_
#define _HV_PAGE_HT7315_DPU_CA_SYNC_00_H_

#ifndef HV_DPU_CA_SYNC_00_BASE_ADDRESS
    #define HV_DPU_CA_SYNC_00_BASE_ADDRESS                                         0x11020D00
#endif


#define DISP_TOP_DPU_CA_SYNC_00_00                                       (HV_DPU_CA_SYNC_00_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_CA_SYNC_00_00_struct                                rs_disp_top_dpu_ca_sync_00_00

typedef struct _rs_disp_top_dpu_ca_sync_00_00  rs_disp_top_dpu_ca_sync_00_00;
struct _rs_disp_top_dpu_ca_sync_00_00 {
    unsigned int reg_00_en                                  : 1;
    unsigned int reg_00_en_no_latch                         : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_ca_sync_00_00(val) ((rs_disp_top_dpu_ca_sync_00_00*)&(val))



#define DISP_TOP_DPU_CA_SYNC_00_04                                       (HV_DPU_CA_SYNC_00_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_CA_SYNC_00_04_struct                                rs_disp_top_dpu_ca_sync_00_04

typedef struct _rs_disp_top_dpu_ca_sync_00_04  rs_disp_top_dpu_ca_sync_00_04;
struct _rs_disp_top_dpu_ca_sync_00_04 {
    unsigned int reg_00_ca_htotal                           :14;
    unsigned int reg_00_ca_vact                             :14;
    unsigned int reg_00_ca_sw_tbl_go                        : 1;
    unsigned int reg_00_ca_sw_tbl_go_en                     : 1;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_ca_sync_00_04(val) ((rs_disp_top_dpu_ca_sync_00_04*)&(val))



#define DISP_TOP_DPU_CA_SYNC_00_08                                       (HV_DPU_CA_SYNC_00_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_CA_SYNC_00_08_struct                                rs_disp_top_dpu_ca_sync_00_08

typedef struct _rs_disp_top_dpu_ca_sync_00_08  rs_disp_top_dpu_ca_sync_00_08;
struct _rs_disp_top_dpu_ca_sync_00_08 {
    unsigned int reg_00_ca_sync_frc_trig_vdly               :14;
    unsigned int reg_00_ca_sync_frc_trig_hdly               :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_sync_00_08(val) ((rs_disp_top_dpu_ca_sync_00_08*)&(val))



#define DISP_TOP_DPU_CA_SYNC_00_0C                                       (HV_DPU_CA_SYNC_00_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_CA_SYNC_00_0C_struct                                rs_disp_top_dpu_ca_sync_00_0c

typedef struct _rs_disp_top_dpu_ca_sync_00_0c  rs_disp_top_dpu_ca_sync_00_0c;
struct _rs_disp_top_dpu_ca_sync_00_0c {
    unsigned int reg_00_ca_sync_data_trig_vdly              :14;
    unsigned int reg_00_ca_sync_data_trig_hdly              :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_sync_00_0c(val) ((rs_disp_top_dpu_ca_sync_00_0c*)&(val))



#define DISP_TOP_DPU_CA_SYNC_00_10                                       (HV_DPU_CA_SYNC_00_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_CA_SYNC_00_10_struct                                rs_disp_top_dpu_ca_sync_00_10

typedef struct _rs_disp_top_dpu_ca_sync_00_10  rs_disp_top_dpu_ca_sync_00_10;
struct _rs_disp_top_dpu_ca_sync_00_10 {
    unsigned int reg_00_ca_sync_tbl_trig_vdly               :14;
    unsigned int reg_00_ca_sync_tbl_trig_hdly               :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_sync_00_10(val) ((rs_disp_top_dpu_ca_sync_00_10*)&(val))



#endif