#ifndef _HV_PAGE_HT7315_VBY1_TOP_H_
#define _HV_PAGE_HT7315_VBY1_TOP_H_

#ifndef HV_VBY1_TOP_BASE_ADDRESS
    #define HV_VBY1_TOP_BASE_ADDRESS                                         0x1105E300
#endif


#define TX_VBY1_TOP_VBY1TX_SET_0                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x00)

#define TX_VBY1_TOP_VBY1TX_SET_0_struct                                  rs_tx_vby1_top_vby1tx_set_0

typedef struct _rs_tx_vby1_top_vby1tx_set_0  rs_tx_vby1_top_vby1tx_set_0;
struct _rs_tx_vby1_top_vby1tx_set_0 {
    unsigned int reg_win                                    :10;
    unsigned int reg_color_format                           : 4;
    unsigned int reserved                                   : 2;
    unsigned int reg_vby1_dclk_in_sel                       : 1;
    unsigned int reserved_1                                 :15;
};
#define tx_vby1_top_vby1tx_set_0(val) ((rs_tx_vby1_top_vby1tx_set_0*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_1                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x04)

#define TX_VBY1_TOP_VBY1TX_SET_1_struct                                  rs_tx_vby1_top_vby1tx_set_1

typedef struct _rs_tx_vby1_top_vby1tx_set_1  rs_tx_vby1_top_vby1tx_set_1;
struct _rs_tx_vby1_top_vby1tx_set_1 {
    unsigned int reg_byte_mode                              : 3;
    unsigned int reg_section                                : 5;
    unsigned int reg_lane_count                             : 5;
    unsigned int reg_pixel_mode                             : 3;
    unsigned int reserved                                   :16;
};
#define tx_vby1_top_vby1tx_set_1(val) ((rs_tx_vby1_top_vby1tx_set_1*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_2                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x08)

#define TX_VBY1_TOP_VBY1TX_SET_2_struct                                  rs_tx_vby1_top_vby1tx_set_2

typedef struct _rs_tx_vby1_top_vby1tx_set_2  rs_tx_vby1_top_vby1tx_set_2;
struct _rs_tx_vby1_top_vby1tx_set_2 {
    unsigned int reg_ctl                                    :24;
    unsigned int reserved                                   : 8;
};
#define tx_vby1_top_vby1tx_set_2(val) ((rs_tx_vby1_top_vby1tx_set_2*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_3                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x0C)

#define TX_VBY1_TOP_VBY1TX_SET_3_struct                                  rs_tx_vby1_top_vby1tx_set_3

typedef struct _rs_tx_vby1_top_vby1tx_set_3  rs_tx_vby1_top_vby1tx_set_3;
struct _rs_tx_vby1_top_vby1tx_set_3 {
    unsigned int reg_reg_boundary                           : 5;
    unsigned int reserved                                   :27;
};
#define tx_vby1_top_vby1tx_set_3(val) ((rs_tx_vby1_top_vby1tx_set_3*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_4                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x10)

#define TX_VBY1_TOP_VBY1TX_SET_4_struct                                  rs_tx_vby1_top_vby1tx_set_4

typedef struct _rs_tx_vby1_top_vby1tx_set_4  rs_tx_vby1_top_vby1tx_set_4;
struct _rs_tx_vby1_top_vby1tx_set_4 {
    unsigned int reg_reg_delay                              :22;
    unsigned int reg_debounce_cnt                           : 4;
    unsigned int reg_video_trans_mode                       : 1;
    unsigned int reg_transfer_en                            : 1;
    unsigned int reg_pll_stable                             : 1;
    unsigned int reg_reg_en                                 : 1;
    unsigned int reserved                                   : 2;
};
#define tx_vby1_top_vby1tx_set_4(val) ((rs_tx_vby1_top_vby1tx_set_4*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_5                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x14)

#define TX_VBY1_TOP_VBY1TX_SET_5_struct                                  rs_tx_vby1_top_vby1tx_set_5

typedef struct _rs_tx_vby1_top_vby1tx_set_5  rs_tx_vby1_top_vby1tx_set_5;
struct _rs_tx_vby1_top_vby1tx_set_5 {
    unsigned int reg_reset_sel                              : 1;
    unsigned int reserved                                   :31;
};
#define tx_vby1_top_vby1tx_set_5(val) ((rs_tx_vby1_top_vby1tx_set_5*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_6                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x18)

#define TX_VBY1_TOP_VBY1TX_SET_6_struct                                  rs_tx_vby1_top_vby1tx_set_6

typedef struct _rs_tx_vby1_top_vby1tx_set_6  rs_tx_vby1_top_vby1tx_set_6;
struct _rs_tx_vby1_top_vby1tx_set_6 {
    unsigned int reg_three_en                               : 1;
    unsigned int reg_three_mode                             : 2;
    unsigned int reserved                                   :29;
};
#define tx_vby1_top_vby1tx_set_6(val) ((rs_tx_vby1_top_vby1tx_set_6*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_7                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x1C)

#define TX_VBY1_TOP_VBY1TX_SET_7_struct                                  rs_tx_vby1_top_vby1tx_set_7

typedef struct _rs_tx_vby1_top_vby1tx_set_7  rs_tx_vby1_top_vby1tx_set_7;
struct _rs_tx_vby1_top_vby1tx_set_7 {
    unsigned int reg_int_cts_empty_en                       : 1;
    unsigned int reg_int_cts_full_en                        : 1;
    unsigned int reg_int_async_under_boundary_en            : 1;
    unsigned int reg_int_async_over_boundary_en             : 1;
    unsigned int reserved                                   :28;
};
#define tx_vby1_top_vby1tx_set_7(val) ((rs_tx_vby1_top_vby1tx_set_7*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_8                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x20)

#define TX_VBY1_TOP_VBY1TX_SET_8_struct                                  rs_tx_vby1_top_vby1tx_set_8

typedef struct _rs_tx_vby1_top_vby1tx_set_8  rs_tx_vby1_top_vby1tx_set_8;
struct _rs_tx_vby1_top_vby1tx_set_8 {
    unsigned int reg_reg_crc_conti                          : 1;
    unsigned int reg_reg_crc_start                          : 1;
    unsigned int reserved                                   :30;
};
#define tx_vby1_top_vby1tx_set_8(val) ((rs_tx_vby1_top_vby1tx_set_8*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_9                                         (HV_VBY1_TOP_BASE_ADDRESS + 0x24)

#define TX_VBY1_TOP_VBY1TX_SET_9_struct                                  rs_tx_vby1_top_vby1tx_set_9

typedef struct _rs_tx_vby1_top_vby1tx_set_9  rs_tx_vby1_top_vby1tx_set_9;
struct _rs_tx_vby1_top_vby1tx_set_9 {
    unsigned int reg_rd_addr_initial                        : 4;
    unsigned int reg_full_boundary                          : 4;
    unsigned int reg_empty_boundary                         : 4;
    unsigned int reg_force_rstn_delay_en                    : 1;
    unsigned int reg_force_rstn                             : 1;
    unsigned int reg_en_bypass                              : 1;
    unsigned int reg_mem_ls                                 : 1;
    unsigned int reserved                                   :16;
};
#define tx_vby1_top_vby1tx_set_9(val) ((rs_tx_vby1_top_vby1tx_set_9*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_11                                        (HV_VBY1_TOP_BASE_ADDRESS + 0x2C)

#define TX_VBY1_TOP_VBY1TX_SET_11_struct                                 rs_tx_vby1_top_vby1tx_set_11

typedef struct _rs_tx_vby1_top_vby1tx_set_11  rs_tx_vby1_top_vby1tx_set_11;
struct _rs_tx_vby1_top_vby1tx_set_11 {
    unsigned int reg_debug_mode                             : 6;
    unsigned int reserved                                   :26;
};
#define tx_vby1_top_vby1tx_set_11(val) ((rs_tx_vby1_top_vby1tx_set_11*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_12                                        (HV_VBY1_TOP_BASE_ADDRESS + 0x30)

#define TX_VBY1_TOP_VBY1TX_SET_12_struct                                 rs_tx_vby1_top_vby1tx_set_12

typedef struct _rs_tx_vby1_top_vby1tx_set_12  rs_tx_vby1_top_vby1tx_set_12;
struct _rs_tx_vby1_top_vby1tx_set_12 {
    unsigned int reg_htpdn_mode_ctrl                        : 1;
    unsigned int reg_lockn_mode_ctrl                        : 1;
    unsigned int reg_fw_htpdn_set                           : 1;
    unsigned int reg_fw_lockn_set                           : 1;
    unsigned int reg_htpdn_ie                               : 1;
    unsigned int reg_lockn_ie                               : 1;
    unsigned int reg_de_only_mode_vs_set                    : 1;
    unsigned int reg_de_only_mode_hs_set                    : 1;
    unsigned int reg_de_only_mode                           : 1;
    unsigned int reserved                                   :23;
};
#define tx_vby1_top_vby1tx_set_12(val) ((rs_tx_vby1_top_vby1tx_set_12*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_13                                        (HV_VBY1_TOP_BASE_ADDRESS + 0x34)

#define TX_VBY1_TOP_VBY1TX_SET_13_struct                                 rs_tx_vby1_top_vby1tx_set_13

typedef struct _rs_tx_vby1_top_vby1tx_set_13  rs_tx_vby1_top_vby1tx_set_13;
struct _rs_tx_vby1_top_vby1tx_set_13 {
    unsigned int reg_lsb_msb_swap                           : 1;
    unsigned int reg_lane_swap                              : 1;
    unsigned int reserved                                   :30;
};
#define tx_vby1_top_vby1tx_set_13(val) ((rs_tx_vby1_top_vby1tx_set_13*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_14                                        (HV_VBY1_TOP_BASE_ADDRESS + 0x38)

#define TX_VBY1_TOP_VBY1TX_SET_14_struct                                 rs_tx_vby1_top_vby1tx_set_14

typedef struct _rs_tx_vby1_top_vby1tx_set_14  rs_tx_vby1_top_vby1tx_set_14;
struct _rs_tx_vby1_top_vby1tx_set_14 {
    unsigned int reg_bit_shift_enable                       : 1;
    unsigned int reg_output_bit                             : 4;
    unsigned int reg_shift_bit                              : 2;
    unsigned int reserved                                   :25;
};
#define tx_vby1_top_vby1tx_set_14(val) ((rs_tx_vby1_top_vby1tx_set_14*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_17                                        (HV_VBY1_TOP_BASE_ADDRESS + 0x3C)

#define TX_VBY1_TOP_VBY1TX_SET_17_struct                                 rs_tx_vby1_top_vby1tx_set_17

typedef struct _rs_tx_vby1_top_vby1tx_set_17  rs_tx_vby1_top_vby1tx_set_17;
struct _rs_tx_vby1_top_vby1tx_set_17 {
    unsigned int reg_lane_0_crc_conti                       : 1;
    unsigned int reg_lane_0_crc_start                       : 1;
    unsigned int reg_lane_1_crc_conti                       : 1;
    unsigned int reg_lane_1_crc_start                       : 1;
    unsigned int reg_lane_2_crc_conti                       : 1;
    unsigned int reg_lane_2_crc_start                       : 1;
    unsigned int reg_lane_3_crc_conti                       : 1;
    unsigned int reg_lane_3_crc_start                       : 1;
    unsigned int reg_lane_4_crc_conti                       : 1;
    unsigned int reg_lane_4_crc_start                       : 1;
    unsigned int reg_lane_5_crc_conti                       : 1;
    unsigned int reg_lane_5_crc_start                       : 1;
    unsigned int reg_lane_6_crc_conti                       : 1;
    unsigned int reg_lane_6_crc_start                       : 1;
    unsigned int reg_lane_7_crc_conti                       : 1;
    unsigned int reg_lane_7_crc_start                       : 1;
    unsigned int reg_lane_8_crc_conti                       : 1;
    unsigned int reg_lane_8_crc_start                       : 1;
    unsigned int reg_lane_9_crc_conti                       : 1;
    unsigned int reg_lane_9_crc_start                       : 1;
    unsigned int reg_lane_10_crc_conti                      : 1;
    unsigned int reg_lane_10_crc_start                      : 1;
    unsigned int reg_lane_11_crc_conti                      : 1;
    unsigned int reg_lane_11_crc_start                      : 1;
    unsigned int reg_lane_12_crc_conti                      : 1;
    unsigned int reg_lane_12_crc_start                      : 1;
    unsigned int reg_lane_13_crc_conti                      : 1;
    unsigned int reg_lane_13_crc_start                      : 1;
    unsigned int reg_lane_14_crc_conti                      : 1;
    unsigned int reg_lane_14_crc_start                      : 1;
    unsigned int reg_lane_15_crc_conti                      : 1;
    unsigned int reg_lane_15_crc_start                      : 1;
};
#define tx_vby1_top_vby1tx_set_17(val) ((rs_tx_vby1_top_vby1tx_set_17*)&(val))



#define TX_VBY1_TOP_VBY1TX_SET_18                                        (HV_VBY1_TOP_BASE_ADDRESS + 0x40)

#define TX_VBY1_TOP_VBY1TX_SET_18_struct                                 rs_tx_vby1_top_vby1tx_set_18

typedef struct _rs_tx_vby1_top_vby1tx_set_18  rs_tx_vby1_top_vby1tx_set_18;
struct _rs_tx_vby1_top_vby1tx_set_18 {
    unsigned int reg_capture_lane_sel                       : 4;
    unsigned int reg_capture_active_only                    : 1;
    unsigned int reg_capture_v                              :11;
    unsigned int reg_capture_h                              :13;
    unsigned int reserved                                   : 3;
};
#define tx_vby1_top_vby1tx_set_18(val) ((rs_tx_vby1_top_vby1tx_set_18*)&(val))



#define TX_VBY1_TOP_VBY1TX_PHY_SET_0                                     (HV_VBY1_TOP_BASE_ADDRESS + 0x44)

#define TX_VBY1_TOP_VBY1TX_PHY_SET_0_struct                              rs_tx_vby1_top_vby1tx_phy_set_0

typedef struct _rs_tx_vby1_top_vby1tx_phy_set_0  rs_tx_vby1_top_vby1tx_phy_set_0;
struct _rs_tx_vby1_top_vby1tx_phy_set_0 {
    unsigned int reg_scramble_default                       : 1;
    unsigned int reg_scramble_dis                           : 1;
    unsigned int reg_enhance_mode                           : 1;
    unsigned int reg_debug_sel                              : 8;
    unsigned int reserved                                   :21;
};
#define tx_vby1_top_vby1tx_phy_set_0(val) ((rs_tx_vby1_top_vby1tx_phy_set_0*)&(val))



#define TX_VBY1_TOP_VBY1TX_PHY_SET_1                                     (HV_VBY1_TOP_BASE_ADDRESS + 0x48)

#define TX_VBY1_TOP_VBY1TX_PHY_SET_1_struct                              rs_tx_vby1_top_vby1tx_phy_set_1

typedef struct _rs_tx_vby1_top_vby1tx_phy_set_1  rs_tx_vby1_top_vby1tx_phy_set_1;
struct _rs_tx_vby1_top_vby1tx_phy_set_1 {
    unsigned int reg_lane_enable                            :32;
};
#define tx_vby1_top_vby1tx_phy_set_1(val) ((rs_tx_vby1_top_vby1tx_phy_set_1*)&(val))



#define TX_VBY1_TOP_VBY1TX_WCLR_0                                        (HV_VBY1_TOP_BASE_ADDRESS + 0x74)

#define TX_VBY1_TOP_VBY1TX_WCLR_0_struct                                 rs_tx_vby1_top_vby1tx_wclr_0

typedef struct _rs_tx_vby1_top_vby1tx_wclr_0  rs_tx_vby1_top_vby1tx_wclr_0;
struct _rs_tx_vby1_top_vby1tx_wclr_0 {
    unsigned int int_async_over_boundary_wclr_out           : 1;
    unsigned int int_async_under_boundary_wclr_out          : 1;
    unsigned int int_cts_full_wclr_out                      : 1;
    unsigned int int_cts_empty_wclr_out                     : 1;
    unsigned int full_mask_error_wclr_out                   : 1;
    unsigned int empty_mask_error_wclr_out                  : 1;
    unsigned int htpdn_int_status_wclr_out                  : 1;
    unsigned int lockn_int_status_wclr_out                  : 1;
    unsigned int reserved                                   :24;
};
#define tx_vby1_top_vby1tx_wclr_0(val) ((rs_tx_vby1_top_vby1tx_wclr_0*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_0                                    (HV_VBY1_TOP_BASE_ADDRESS + 0x80)

#define TX_VBY1_TOP_VBY1TX_READBACK_0_struct                             rs_tx_vby1_top_vby1tx_readback_0

typedef struct _rs_tx_vby1_top_vby1tx_readback_0  rs_tx_vby1_top_vby1tx_readback_0;
struct _rs_tx_vby1_top_vby1tx_readback_0 {
    unsigned int over_boundary_ro                           : 1;
    unsigned int under_boundary_ro                          : 1;
    unsigned int num_check_fail_ro                          : 1;
    unsigned int aln_finish_ro                              : 1;
    unsigned int initial_finish_ro                          : 1;
    unsigned int cdr_out_en_ro                              : 1;
    unsigned int video_en_ro                                : 1;
    unsigned int aln_en_ro                                  : 1;
    unsigned int initial_en_ro                              : 1;
    unsigned int int_async_over_boundary_ro                 : 1;
    unsigned int int_async_under_boundary_ro                : 1;
    unsigned int int_cts_full_ro                            : 1;
    unsigned int int_cts_empty_ro                           : 1;
    unsigned int htpdn_int_status_ro                        : 1;
    unsigned int lockn_int_status_ro                        : 1;
    unsigned int htpdn_ro                                   : 1;
    unsigned int lockn_ro                                   : 1;
    unsigned int hw_htpdn_ro                                : 1;
    unsigned int hw_lockn_ro                                : 1;
    unsigned int full_mask_error_ro                         : 1;
    unsigned int empty_mask_error_ro                        : 1;
    unsigned int reserved                                   :11;
};
#define tx_vby1_top_vby1tx_readback_0(val) ((rs_tx_vby1_top_vby1tx_readback_0*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_3                                    (HV_VBY1_TOP_BASE_ADDRESS + 0x8C)

#define TX_VBY1_TOP_VBY1TX_READBACK_3_struct                             rs_tx_vby1_top_vby1tx_readback_3

typedef struct _rs_tx_vby1_top_vby1tx_readback_3  rs_tx_vby1_top_vby1tx_readback_3;
struct _rs_tx_vby1_top_vby1tx_readback_3 {
    unsigned int crc_result_ro                              :32;
};
#define tx_vby1_top_vby1tx_readback_3(val) ((rs_tx_vby1_top_vby1tx_readback_3*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_4                                    (HV_VBY1_TOP_BASE_ADDRESS + 0x90)

#define TX_VBY1_TOP_VBY1TX_READBACK_4_struct                             rs_tx_vby1_top_vby1tx_readback_4

typedef struct _rs_tx_vby1_top_vby1tx_readback_4  rs_tx_vby1_top_vby1tx_readback_4;
struct _rs_tx_vby1_top_vby1tx_readback_4 {
    unsigned int lane_0_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_4(val) ((rs_tx_vby1_top_vby1tx_readback_4*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_5                                    (HV_VBY1_TOP_BASE_ADDRESS + 0x94)

#define TX_VBY1_TOP_VBY1TX_READBACK_5_struct                             rs_tx_vby1_top_vby1tx_readback_5

typedef struct _rs_tx_vby1_top_vby1tx_readback_5  rs_tx_vby1_top_vby1tx_readback_5;
struct _rs_tx_vby1_top_vby1tx_readback_5 {
    unsigned int lane_1_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_5(val) ((rs_tx_vby1_top_vby1tx_readback_5*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_6                                    (HV_VBY1_TOP_BASE_ADDRESS + 0x98)

#define TX_VBY1_TOP_VBY1TX_READBACK_6_struct                             rs_tx_vby1_top_vby1tx_readback_6

typedef struct _rs_tx_vby1_top_vby1tx_readback_6  rs_tx_vby1_top_vby1tx_readback_6;
struct _rs_tx_vby1_top_vby1tx_readback_6 {
    unsigned int lane_2_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_6(val) ((rs_tx_vby1_top_vby1tx_readback_6*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_7                                    (HV_VBY1_TOP_BASE_ADDRESS + 0x9C)

#define TX_VBY1_TOP_VBY1TX_READBACK_7_struct                             rs_tx_vby1_top_vby1tx_readback_7

typedef struct _rs_tx_vby1_top_vby1tx_readback_7  rs_tx_vby1_top_vby1tx_readback_7;
struct _rs_tx_vby1_top_vby1tx_readback_7 {
    unsigned int lane_3_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_7(val) ((rs_tx_vby1_top_vby1tx_readback_7*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_8                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xA0)

#define TX_VBY1_TOP_VBY1TX_READBACK_8_struct                             rs_tx_vby1_top_vby1tx_readback_8

typedef struct _rs_tx_vby1_top_vby1tx_readback_8  rs_tx_vby1_top_vby1tx_readback_8;
struct _rs_tx_vby1_top_vby1tx_readback_8 {
    unsigned int lane_4_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_8(val) ((rs_tx_vby1_top_vby1tx_readback_8*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_9                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xA4)

#define TX_VBY1_TOP_VBY1TX_READBACK_9_struct                             rs_tx_vby1_top_vby1tx_readback_9

typedef struct _rs_tx_vby1_top_vby1tx_readback_9  rs_tx_vby1_top_vby1tx_readback_9;
struct _rs_tx_vby1_top_vby1tx_readback_9 {
    unsigned int lane_5_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_9(val) ((rs_tx_vby1_top_vby1tx_readback_9*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_A                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xA8)

#define TX_VBY1_TOP_VBY1TX_READBACK_A_struct                             rs_tx_vby1_top_vby1tx_readback_a

typedef struct _rs_tx_vby1_top_vby1tx_readback_a  rs_tx_vby1_top_vby1tx_readback_a;
struct _rs_tx_vby1_top_vby1tx_readback_a {
    unsigned int lane_6_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_a(val) ((rs_tx_vby1_top_vby1tx_readback_a*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_B                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xAC)

#define TX_VBY1_TOP_VBY1TX_READBACK_B_struct                             rs_tx_vby1_top_vby1tx_readback_b

typedef struct _rs_tx_vby1_top_vby1tx_readback_b  rs_tx_vby1_top_vby1tx_readback_b;
struct _rs_tx_vby1_top_vby1tx_readback_b {
    unsigned int lane_7_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_b(val) ((rs_tx_vby1_top_vby1tx_readback_b*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_C                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xB0)

#define TX_VBY1_TOP_VBY1TX_READBACK_C_struct                             rs_tx_vby1_top_vby1tx_readback_c

typedef struct _rs_tx_vby1_top_vby1tx_readback_c  rs_tx_vby1_top_vby1tx_readback_c;
struct _rs_tx_vby1_top_vby1tx_readback_c {
    unsigned int lane_8_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_c(val) ((rs_tx_vby1_top_vby1tx_readback_c*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_D                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xB4)

#define TX_VBY1_TOP_VBY1TX_READBACK_D_struct                             rs_tx_vby1_top_vby1tx_readback_d

typedef struct _rs_tx_vby1_top_vby1tx_readback_d  rs_tx_vby1_top_vby1tx_readback_d;
struct _rs_tx_vby1_top_vby1tx_readback_d {
    unsigned int lane_9_crc_result_ro                       :32;
};
#define tx_vby1_top_vby1tx_readback_d(val) ((rs_tx_vby1_top_vby1tx_readback_d*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_E                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xB8)

#define TX_VBY1_TOP_VBY1TX_READBACK_E_struct                             rs_tx_vby1_top_vby1tx_readback_e

typedef struct _rs_tx_vby1_top_vby1tx_readback_e  rs_tx_vby1_top_vby1tx_readback_e;
struct _rs_tx_vby1_top_vby1tx_readback_e {
    unsigned int lane_10_crc_result_ro                      :32;
};
#define tx_vby1_top_vby1tx_readback_e(val) ((rs_tx_vby1_top_vby1tx_readback_e*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_F                                    (HV_VBY1_TOP_BASE_ADDRESS + 0xBC)

#define TX_VBY1_TOP_VBY1TX_READBACK_F_struct                             rs_tx_vby1_top_vby1tx_readback_f

typedef struct _rs_tx_vby1_top_vby1tx_readback_f  rs_tx_vby1_top_vby1tx_readback_f;
struct _rs_tx_vby1_top_vby1tx_readback_f {
    unsigned int lane_11_crc_result_ro                      :32;
};
#define tx_vby1_top_vby1tx_readback_f(val) ((rs_tx_vby1_top_vby1tx_readback_f*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_10                                   (HV_VBY1_TOP_BASE_ADDRESS + 0xC0)

#define TX_VBY1_TOP_VBY1TX_READBACK_10_struct                            rs_tx_vby1_top_vby1tx_readback_10

typedef struct _rs_tx_vby1_top_vby1tx_readback_10  rs_tx_vby1_top_vby1tx_readback_10;
struct _rs_tx_vby1_top_vby1tx_readback_10 {
    unsigned int lane_12_crc_result_ro                      :32;
};
#define tx_vby1_top_vby1tx_readback_10(val) ((rs_tx_vby1_top_vby1tx_readback_10*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_11                                   (HV_VBY1_TOP_BASE_ADDRESS + 0xC4)

#define TX_VBY1_TOP_VBY1TX_READBACK_11_struct                            rs_tx_vby1_top_vby1tx_readback_11

typedef struct _rs_tx_vby1_top_vby1tx_readback_11  rs_tx_vby1_top_vby1tx_readback_11;
struct _rs_tx_vby1_top_vby1tx_readback_11 {
    unsigned int lane_13_crc_result_ro                      :32;
};
#define tx_vby1_top_vby1tx_readback_11(val) ((rs_tx_vby1_top_vby1tx_readback_11*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_12                                   (HV_VBY1_TOP_BASE_ADDRESS + 0xC8)

#define TX_VBY1_TOP_VBY1TX_READBACK_12_struct                            rs_tx_vby1_top_vby1tx_readback_12

typedef struct _rs_tx_vby1_top_vby1tx_readback_12  rs_tx_vby1_top_vby1tx_readback_12;
struct _rs_tx_vby1_top_vby1tx_readback_12 {
    unsigned int lane_14_crc_result_ro                      :32;
};
#define tx_vby1_top_vby1tx_readback_12(val) ((rs_tx_vby1_top_vby1tx_readback_12*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_13                                   (HV_VBY1_TOP_BASE_ADDRESS + 0xCC)

#define TX_VBY1_TOP_VBY1TX_READBACK_13_struct                            rs_tx_vby1_top_vby1tx_readback_13

typedef struct _rs_tx_vby1_top_vby1tx_readback_13  rs_tx_vby1_top_vby1tx_readback_13;
struct _rs_tx_vby1_top_vby1tx_readback_13 {
    unsigned int lane_15_crc_result_ro                      :32;
};
#define tx_vby1_top_vby1tx_readback_13(val) ((rs_tx_vby1_top_vby1tx_readback_13*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_14                                   (HV_VBY1_TOP_BASE_ADDRESS + 0xD0)

#define TX_VBY1_TOP_VBY1TX_READBACK_14_struct                            rs_tx_vby1_top_vby1tx_readback_14

typedef struct _rs_tx_vby1_top_vby1tx_readback_14  rs_tx_vby1_top_vby1tx_readback_14;
struct _rs_tx_vby1_top_vby1tx_readback_14 {
    unsigned int capture_data_31_00_ro                      :32;
};
#define tx_vby1_top_vby1tx_readback_14(val) ((rs_tx_vby1_top_vby1tx_readback_14*)&(val))



#define TX_VBY1_TOP_VBY1TX_READBACK_15                                   (HV_VBY1_TOP_BASE_ADDRESS + 0xD4)

#define TX_VBY1_TOP_VBY1TX_READBACK_15_struct                            rs_tx_vby1_top_vby1tx_readback_15

typedef struct _rs_tx_vby1_top_vby1tx_readback_15  rs_tx_vby1_top_vby1tx_readback_15;
struct _rs_tx_vby1_top_vby1tx_readback_15 {
    unsigned int capture_data_39_32_ro                      : 8;
    unsigned int reserved                                   :24;
};
#define tx_vby1_top_vby1tx_readback_15(val) ((rs_tx_vby1_top_vby1tx_readback_15*)&(val))



#endif