#ifndef _HV_PAGE_HT7315_ISPTX_H_
#define _HV_PAGE_HT7315_ISPTX_H_

#ifndef HV_ISPTX_BASE_ADDRESS
    #define HV_ISPTX_BASE_ADDRESS                                         0x1105E700
#endif


#define TX_ISPTX_ISP_TX_REG_00                                           (HV_ISPTX_BASE_ADDRESS + 0x00)

#define TX_ISPTX_ISP_TX_REG_00_struct                                    rs_tx_isptx_isp_tx_reg_00

typedef struct _rs_tx_isptx_isp_tx_reg_00  rs_tx_isptx_isp_tx_reg_00;
struct _rs_tx_isptx_isp_tx_reg_00 {
    unsigned int reg_isp_pair_num                           : 1;
    unsigned int reg_isp_tx_en                              : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_isp_rgb_bit                            : 2;
    unsigned int reg_isp_sd_lock_type                       : 1;
    unsigned int reg_isp_scramb_en                          : 1;
    unsigned int reg_isp_scramb_sel                         : 1;
    unsigned int reg_sd_setting_length                      : 8;
    unsigned int reg_isp_vb_sd_set_en                       : 1;
    unsigned int reg_isp_vb_sd_set_frm                      : 8;
    unsigned int reg_isp_pre_scramb_en                      : 1;
    unsigned int reg_isp_scramb_key_type                    : 1;
    unsigned int reserved_1                                 : 3;
};
#define tx_isptx_isp_tx_reg_00(val) ((rs_tx_isptx_isp_tx_reg_00*)&(val))



#define TX_ISPTX_ISP_TX_REG_01                                           (HV_ISPTX_BASE_ADDRESS + 0x04)

#define TX_ISPTX_ISP_TX_REG_01_struct                                    rs_tx_isptx_isp_tx_reg_01

typedef struct _rs_tx_isptx_isp_tx_reg_01  rs_tx_isptx_isp_tx_reg_01;
struct _rs_tx_isptx_isp_tx_reg_01 {
    unsigned int reg_isp_set_aft_lock_en                    : 1;
    unsigned int reg_isp_set_aft_lock_sel                   : 1;
    unsigned int reg_isp_set_aft_lock_twice                 : 1;
    unsigned int reg_isp_bypass_sdlock                      : 1;
    unsigned int reg_isp_vblank_start                       :15;
    unsigned int reg_isp_set_aft_rst_once                   : 1;
    unsigned int reserved                                   :12;
};
#define tx_isptx_isp_tx_reg_01(val) ((rs_tx_isptx_isp_tx_reg_01*)&(val))



#define TX_ISPTX_ISP_TX_REG_02                                           (HV_ISPTX_BASE_ADDRESS + 0x08)

#define TX_ISPTX_ISP_TX_REG_02_struct                                    rs_tx_isptx_isp_tx_reg_02

typedef struct _rs_tx_isptx_isp_tx_reg_02  rs_tx_isptx_isp_tx_reg_02;
struct _rs_tx_isptx_isp_tx_reg_02 {
    unsigned int reg_isp_xstb_dh_sta                        :15;
    unsigned int reg_isp_xstb_width                         :15;
    unsigned int reserved                                   : 2;
};
#define tx_isptx_isp_tx_reg_02(val) ((rs_tx_isptx_isp_tx_reg_02*)&(val))



#define TX_ISPTX_ISP_TX_REG_03                                           (HV_ISPTX_BASE_ADDRESS + 0x0C)

#define TX_ISPTX_ISP_TX_REG_03_struct                                    rs_tx_isptx_isp_tx_reg_03

typedef struct _rs_tx_isptx_isp_tx_reg_03  rs_tx_isptx_isp_tx_reg_03;
struct _rs_tx_isptx_isp_tx_reg_03 {
    unsigned int reg_isp_tbk1                               : 9;
    unsigned int reg_isp_tbk2                               : 9;
    unsigned int reserved                                   :14;
};
#define tx_isptx_isp_tx_reg_03(val) ((rs_tx_isptx_isp_tx_reg_03*)&(val))



#define TX_ISPTX_ISP_TX_REG_04                                           (HV_ISPTX_BASE_ADDRESS + 0x10)

#define TX_ISPTX_ISP_TX_REG_04_struct                                    rs_tx_isptx_isp_tx_reg_04

typedef struct _rs_tx_isptx_isp_tx_reg_04  rs_tx_isptx_isp_tx_reg_04;
struct _rs_tx_isptx_isp_tx_reg_04 {
    unsigned int reg_isp_pol_p                              : 9;
    unsigned int reg_isp_pol_n                              : 9;
    unsigned int reserved                                   :14;
};
#define tx_isptx_isp_tx_reg_04(val) ((rs_tx_isptx_isp_tx_reg_04*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE0                              (HV_ISPTX_BASE_ADDRESS + 0x14)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE0_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane0

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane0  rs_tx_isptx_isptx_sd_setting_reg_lane0;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane0 {
    unsigned int reg_isp_sd_set_reg_0_0                     : 8;
    unsigned int reg_isp_sd_set_reg_1_0                     : 8;
    unsigned int reg_isp_sd_set_reg_2_0                     : 8;
    unsigned int reg_isp_sd_set_reg_3_0                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane0(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane0*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE1                              (HV_ISPTX_BASE_ADDRESS + 0x18)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE1_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane1

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane1  rs_tx_isptx_isptx_sd_setting_reg_lane1;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane1 {
    unsigned int reg_isp_sd_set_reg_0_1                     : 8;
    unsigned int reg_isp_sd_set_reg_1_1                     : 8;
    unsigned int reg_isp_sd_set_reg_2_1                     : 8;
    unsigned int reg_isp_sd_set_reg_3_1                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane1(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane1*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE2                              (HV_ISPTX_BASE_ADDRESS + 0x1C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE2_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane2

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane2  rs_tx_isptx_isptx_sd_setting_reg_lane2;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane2 {
    unsigned int reg_isp_sd_set_reg_0_2                     : 8;
    unsigned int reg_isp_sd_set_reg_1_2                     : 8;
    unsigned int reg_isp_sd_set_reg_2_2                     : 8;
    unsigned int reg_isp_sd_set_reg_3_2                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane2(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane2*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE3                              (HV_ISPTX_BASE_ADDRESS + 0x20)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE3_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane3

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane3  rs_tx_isptx_isptx_sd_setting_reg_lane3;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane3 {
    unsigned int reg_isp_sd_set_reg_0_3                     : 8;
    unsigned int reg_isp_sd_set_reg_1_3                     : 8;
    unsigned int reg_isp_sd_set_reg_2_3                     : 8;
    unsigned int reg_isp_sd_set_reg_3_3                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane3(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane3*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE4                              (HV_ISPTX_BASE_ADDRESS + 0x24)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE4_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane4

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane4  rs_tx_isptx_isptx_sd_setting_reg_lane4;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane4 {
    unsigned int reg_isp_sd_set_reg_0_4                     : 8;
    unsigned int reg_isp_sd_set_reg_1_4                     : 8;
    unsigned int reg_isp_sd_set_reg_2_4                     : 8;
    unsigned int reg_isp_sd_set_reg_3_4                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane4(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane4*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE5                              (HV_ISPTX_BASE_ADDRESS + 0x28)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE5_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane5

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane5  rs_tx_isptx_isptx_sd_setting_reg_lane5;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane5 {
    unsigned int reg_isp_sd_set_reg_0_5                     : 8;
    unsigned int reg_isp_sd_set_reg_1_5                     : 8;
    unsigned int reg_isp_sd_set_reg_2_5                     : 8;
    unsigned int reg_isp_sd_set_reg_3_5                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane5(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane5*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE6                              (HV_ISPTX_BASE_ADDRESS + 0x2C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE6_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane6

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane6  rs_tx_isptx_isptx_sd_setting_reg_lane6;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane6 {
    unsigned int reg_isp_sd_set_reg_0_6                     : 8;
    unsigned int reg_isp_sd_set_reg_1_6                     : 8;
    unsigned int reg_isp_sd_set_reg_2_6                     : 8;
    unsigned int reg_isp_sd_set_reg_3_6                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane6(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane6*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE7                              (HV_ISPTX_BASE_ADDRESS + 0x30)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE7_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane7

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane7  rs_tx_isptx_isptx_sd_setting_reg_lane7;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane7 {
    unsigned int reg_isp_sd_set_reg_0_7                     : 8;
    unsigned int reg_isp_sd_set_reg_1_7                     : 8;
    unsigned int reg_isp_sd_set_reg_2_7                     : 8;
    unsigned int reg_isp_sd_set_reg_3_7                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane7(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane7*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE8                              (HV_ISPTX_BASE_ADDRESS + 0x34)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE8_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane8

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane8  rs_tx_isptx_isptx_sd_setting_reg_lane8;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane8 {
    unsigned int reg_isp_sd_set_reg_0_8                     : 8;
    unsigned int reg_isp_sd_set_reg_1_8                     : 8;
    unsigned int reg_isp_sd_set_reg_2_8                     : 8;
    unsigned int reg_isp_sd_set_reg_3_8                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane8(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane8*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE9                              (HV_ISPTX_BASE_ADDRESS + 0x38)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE9_struct                       rs_tx_isptx_isptx_sd_setting_reg_lane9

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane9  rs_tx_isptx_isptx_sd_setting_reg_lane9;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane9 {
    unsigned int reg_isp_sd_set_reg_0_9                     : 8;
    unsigned int reg_isp_sd_set_reg_1_9                     : 8;
    unsigned int reg_isp_sd_set_reg_2_9                     : 8;
    unsigned int reg_isp_sd_set_reg_3_9                     : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane9(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane9*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE10                             (HV_ISPTX_BASE_ADDRESS + 0x3C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE10_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane10

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane10  rs_tx_isptx_isptx_sd_setting_reg_lane10;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane10 {
    unsigned int reg_isp_sd_set_reg_0_10                    : 8;
    unsigned int reg_isp_sd_set_reg_1_10                    : 8;
    unsigned int reg_isp_sd_set_reg_2_10                    : 8;
    unsigned int reg_isp_sd_set_reg_3_10                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane10(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane10*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE11                             (HV_ISPTX_BASE_ADDRESS + 0x40)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE11_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane11

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane11  rs_tx_isptx_isptx_sd_setting_reg_lane11;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane11 {
    unsigned int reg_isp_sd_set_reg_0_11                    : 8;
    unsigned int reg_isp_sd_set_reg_1_11                    : 8;
    unsigned int reg_isp_sd_set_reg_2_11                    : 8;
    unsigned int reg_isp_sd_set_reg_3_11                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane11(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane11*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE12                             (HV_ISPTX_BASE_ADDRESS + 0x44)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE12_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane12

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane12  rs_tx_isptx_isptx_sd_setting_reg_lane12;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane12 {
    unsigned int reg_isp_sd_set_reg_0_12                    : 8;
    unsigned int reg_isp_sd_set_reg_1_12                    : 8;
    unsigned int reg_isp_sd_set_reg_2_12                    : 8;
    unsigned int reg_isp_sd_set_reg_3_12                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane12(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane12*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE13                             (HV_ISPTX_BASE_ADDRESS + 0x48)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE13_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane13

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane13  rs_tx_isptx_isptx_sd_setting_reg_lane13;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane13 {
    unsigned int reg_isp_sd_set_reg_0_13                    : 8;
    unsigned int reg_isp_sd_set_reg_1_13                    : 8;
    unsigned int reg_isp_sd_set_reg_2_13                    : 8;
    unsigned int reg_isp_sd_set_reg_3_13                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane13(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane13*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE14                             (HV_ISPTX_BASE_ADDRESS + 0x4C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE14_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane14

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane14  rs_tx_isptx_isptx_sd_setting_reg_lane14;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane14 {
    unsigned int reg_isp_sd_set_reg_0_14                    : 8;
    unsigned int reg_isp_sd_set_reg_1_14                    : 8;
    unsigned int reg_isp_sd_set_reg_2_14                    : 8;
    unsigned int reg_isp_sd_set_reg_3_14                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane14(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane14*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE15                             (HV_ISPTX_BASE_ADDRESS + 0x50)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE15_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane15

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane15  rs_tx_isptx_isptx_sd_setting_reg_lane15;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane15 {
    unsigned int reg_isp_sd_set_reg_0_15                    : 8;
    unsigned int reg_isp_sd_set_reg_1_15                    : 8;
    unsigned int reg_isp_sd_set_reg_2_15                    : 8;
    unsigned int reg_isp_sd_set_reg_3_15                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane15(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane15*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE16                             (HV_ISPTX_BASE_ADDRESS + 0x54)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE16_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane16

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane16  rs_tx_isptx_isptx_sd_setting_reg_lane16;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane16 {
    unsigned int reg_isp_sd_set_reg_0_16                    : 8;
    unsigned int reg_isp_sd_set_reg_1_16                    : 8;
    unsigned int reg_isp_sd_set_reg_2_16                    : 8;
    unsigned int reg_isp_sd_set_reg_3_16                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane16(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane16*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE17                             (HV_ISPTX_BASE_ADDRESS + 0x58)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE17_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane17

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane17  rs_tx_isptx_isptx_sd_setting_reg_lane17;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane17 {
    unsigned int reg_isp_sd_set_reg_0_17                    : 8;
    unsigned int reg_isp_sd_set_reg_1_17                    : 8;
    unsigned int reg_isp_sd_set_reg_2_17                    : 8;
    unsigned int reg_isp_sd_set_reg_3_17                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane17(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane17*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE18                             (HV_ISPTX_BASE_ADDRESS + 0x5C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE18_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane18

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane18  rs_tx_isptx_isptx_sd_setting_reg_lane18;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane18 {
    unsigned int reg_isp_sd_set_reg_0_18                    : 8;
    unsigned int reg_isp_sd_set_reg_1_18                    : 8;
    unsigned int reg_isp_sd_set_reg_2_18                    : 8;
    unsigned int reg_isp_sd_set_reg_3_18                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane18(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane18*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE19                             (HV_ISPTX_BASE_ADDRESS + 0x60)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE19_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane19

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane19  rs_tx_isptx_isptx_sd_setting_reg_lane19;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane19 {
    unsigned int reg_isp_sd_set_reg_0_19                    : 8;
    unsigned int reg_isp_sd_set_reg_1_19                    : 8;
    unsigned int reg_isp_sd_set_reg_2_19                    : 8;
    unsigned int reg_isp_sd_set_reg_3_19                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane19(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane19*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE20                             (HV_ISPTX_BASE_ADDRESS + 0x64)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE20_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane20

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane20  rs_tx_isptx_isptx_sd_setting_reg_lane20;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane20 {
    unsigned int reg_isp_sd_set_reg_0_20                    : 8;
    unsigned int reg_isp_sd_set_reg_1_20                    : 8;
    unsigned int reg_isp_sd_set_reg_2_20                    : 8;
    unsigned int reg_isp_sd_set_reg_3_20                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane20(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane20*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE21                             (HV_ISPTX_BASE_ADDRESS + 0x68)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE21_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane21

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane21  rs_tx_isptx_isptx_sd_setting_reg_lane21;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane21 {
    unsigned int reg_isp_sd_set_reg_0_21                    : 8;
    unsigned int reg_isp_sd_set_reg_1_21                    : 8;
    unsigned int reg_isp_sd_set_reg_2_21                    : 8;
    unsigned int reg_isp_sd_set_reg_3_21                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane21(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane21*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE22                             (HV_ISPTX_BASE_ADDRESS + 0x6C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE22_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane22

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane22  rs_tx_isptx_isptx_sd_setting_reg_lane22;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane22 {
    unsigned int reg_isp_sd_set_reg_0_22                    : 8;
    unsigned int reg_isp_sd_set_reg_1_22                    : 8;
    unsigned int reg_isp_sd_set_reg_2_22                    : 8;
    unsigned int reg_isp_sd_set_reg_3_22                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane22(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane22*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE23                             (HV_ISPTX_BASE_ADDRESS + 0x70)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_LANE23_struct                      rs_tx_isptx_isptx_sd_setting_reg_lane23

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_lane23  rs_tx_isptx_isptx_sd_setting_reg_lane23;
struct _rs_tx_isptx_isptx_sd_setting_reg_lane23 {
    unsigned int reg_isp_sd_set_reg_0_23                    : 8;
    unsigned int reg_isp_sd_set_reg_1_23                    : 8;
    unsigned int reg_isp_sd_set_reg_2_23                    : 8;
    unsigned int reg_isp_sd_set_reg_3_23                    : 8;
};
#define tx_isptx_isptx_sd_setting_reg_lane23(val) ((rs_tx_isptx_isptx_sd_setting_reg_lane23*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_4                                  (HV_ISPTX_BASE_ADDRESS + 0x74)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_4_struct                           rs_tx_isptx_isptx_sd_setting_reg_4

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_4  rs_tx_isptx_isptx_sd_setting_reg_4;
struct _rs_tx_isptx_isptx_sd_setting_reg_4 {
    unsigned int reg_isp_sd_set_reg_4                       : 8;
    unsigned int reg_isp_sd_set_reg_5                       : 8;
    unsigned int reg_isp_sd_set_reg_6                       : 8;
    unsigned int reg_isp_sd_set_reg_7                       : 8;
};
#define tx_isptx_isptx_sd_setting_reg_4(val) ((rs_tx_isptx_isptx_sd_setting_reg_4*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_8                                  (HV_ISPTX_BASE_ADDRESS + 0x78)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_8_struct                           rs_tx_isptx_isptx_sd_setting_reg_8

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_8  rs_tx_isptx_isptx_sd_setting_reg_8;
struct _rs_tx_isptx_isptx_sd_setting_reg_8 {
    unsigned int reg_isp_sd_set_reg_8                       : 8;
    unsigned int reg_isp_sd_set_reg_9                       : 8;
    unsigned int reg_isp_sd_set_reg_10                      : 8;
    unsigned int reg_isp_sd_set_reg_11                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_8(val) ((rs_tx_isptx_isptx_sd_setting_reg_8*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_12                                 (HV_ISPTX_BASE_ADDRESS + 0x7C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_12_struct                          rs_tx_isptx_isptx_sd_setting_reg_12

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_12  rs_tx_isptx_isptx_sd_setting_reg_12;
struct _rs_tx_isptx_isptx_sd_setting_reg_12 {
    unsigned int reg_isp_sd_set_reg_12                      : 8;
    unsigned int reg_isp_sd_set_reg_13                      : 8;
    unsigned int reg_isp_sd_set_reg_14                      : 8;
    unsigned int reg_isp_sd_set_reg_15                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_12(val) ((rs_tx_isptx_isptx_sd_setting_reg_12*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_16                                 (HV_ISPTX_BASE_ADDRESS + 0x80)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_16_struct                          rs_tx_isptx_isptx_sd_setting_reg_16

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_16  rs_tx_isptx_isptx_sd_setting_reg_16;
struct _rs_tx_isptx_isptx_sd_setting_reg_16 {
    unsigned int reg_isp_sd_set_reg_16                      : 8;
    unsigned int reg_isp_sd_set_reg_17                      : 8;
    unsigned int reg_isp_sd_set_reg_18                      : 8;
    unsigned int reg_isp_sd_set_reg_19                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_16(val) ((rs_tx_isptx_isptx_sd_setting_reg_16*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_20                                 (HV_ISPTX_BASE_ADDRESS + 0x84)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_20_struct                          rs_tx_isptx_isptx_sd_setting_reg_20

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_20  rs_tx_isptx_isptx_sd_setting_reg_20;
struct _rs_tx_isptx_isptx_sd_setting_reg_20 {
    unsigned int reg_isp_sd_set_reg_20                      : 8;
    unsigned int reg_isp_sd_set_reg_21                      : 8;
    unsigned int reg_isp_sd_set_reg_22                      : 8;
    unsigned int reg_isp_sd_set_reg_23                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_20(val) ((rs_tx_isptx_isptx_sd_setting_reg_20*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_24                                 (HV_ISPTX_BASE_ADDRESS + 0x88)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_24_struct                          rs_tx_isptx_isptx_sd_setting_reg_24

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_24  rs_tx_isptx_isptx_sd_setting_reg_24;
struct _rs_tx_isptx_isptx_sd_setting_reg_24 {
    unsigned int reg_isp_sd_set_reg_24                      : 8;
    unsigned int reg_isp_sd_set_reg_25                      : 8;
    unsigned int reg_isp_sd_set_reg_26                      : 8;
    unsigned int reg_isp_sd_set_reg_27                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_24(val) ((rs_tx_isptx_isptx_sd_setting_reg_24*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_28                                 (HV_ISPTX_BASE_ADDRESS + 0x8C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_28_struct                          rs_tx_isptx_isptx_sd_setting_reg_28

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_28  rs_tx_isptx_isptx_sd_setting_reg_28;
struct _rs_tx_isptx_isptx_sd_setting_reg_28 {
    unsigned int reg_isp_sd_set_reg_28                      : 8;
    unsigned int reg_isp_sd_set_reg_29                      : 8;
    unsigned int reg_isp_sd_set_reg_30                      : 8;
    unsigned int reg_isp_sd_set_reg_31                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_28(val) ((rs_tx_isptx_isptx_sd_setting_reg_28*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_32                                 (HV_ISPTX_BASE_ADDRESS + 0x90)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_32_struct                          rs_tx_isptx_isptx_sd_setting_reg_32

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_32  rs_tx_isptx_isptx_sd_setting_reg_32;
struct _rs_tx_isptx_isptx_sd_setting_reg_32 {
    unsigned int reg_isp_sd_set_reg_32                      : 8;
    unsigned int reg_isp_sd_set_reg_33                      : 8;
    unsigned int reg_isp_sd_set_reg_34                      : 8;
    unsigned int reg_isp_sd_set_reg_35                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_32(val) ((rs_tx_isptx_isptx_sd_setting_reg_32*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_36                                 (HV_ISPTX_BASE_ADDRESS + 0x94)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_36_struct                          rs_tx_isptx_isptx_sd_setting_reg_36

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_36  rs_tx_isptx_isptx_sd_setting_reg_36;
struct _rs_tx_isptx_isptx_sd_setting_reg_36 {
    unsigned int reg_isp_sd_set_reg_36                      : 8;
    unsigned int reg_isp_sd_set_reg_37                      : 8;
    unsigned int reg_isp_sd_set_reg_38                      : 8;
    unsigned int reg_isp_sd_set_reg_39                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_36(val) ((rs_tx_isptx_isptx_sd_setting_reg_36*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_40                                 (HV_ISPTX_BASE_ADDRESS + 0x98)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_40_struct                          rs_tx_isptx_isptx_sd_setting_reg_40

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_40  rs_tx_isptx_isptx_sd_setting_reg_40;
struct _rs_tx_isptx_isptx_sd_setting_reg_40 {
    unsigned int reg_isp_sd_set_reg_40                      : 8;
    unsigned int reg_isp_sd_set_reg_41                      : 8;
    unsigned int reg_isp_sd_set_reg_42                      : 8;
    unsigned int reg_isp_sd_set_reg_43                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_40(val) ((rs_tx_isptx_isptx_sd_setting_reg_40*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_44                                 (HV_ISPTX_BASE_ADDRESS + 0x9C)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_44_struct                          rs_tx_isptx_isptx_sd_setting_reg_44

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_44  rs_tx_isptx_isptx_sd_setting_reg_44;
struct _rs_tx_isptx_isptx_sd_setting_reg_44 {
    unsigned int reg_isp_sd_set_reg_44                      : 8;
    unsigned int reg_isp_sd_set_reg_45                      : 8;
    unsigned int reg_isp_sd_set_reg_46                      : 8;
    unsigned int reg_isp_sd_set_reg_47                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_44(val) ((rs_tx_isptx_isptx_sd_setting_reg_44*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_48                                 (HV_ISPTX_BASE_ADDRESS + 0xA0)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_48_struct                          rs_tx_isptx_isptx_sd_setting_reg_48

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_48  rs_tx_isptx_isptx_sd_setting_reg_48;
struct _rs_tx_isptx_isptx_sd_setting_reg_48 {
    unsigned int reg_isp_sd_set_reg_48                      : 8;
    unsigned int reg_isp_sd_set_reg_49                      : 8;
    unsigned int reg_isp_sd_set_reg_50                      : 8;
    unsigned int reg_isp_sd_set_reg_51                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_48(val) ((rs_tx_isptx_isptx_sd_setting_reg_48*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_52                                 (HV_ISPTX_BASE_ADDRESS + 0xA4)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_52_struct                          rs_tx_isptx_isptx_sd_setting_reg_52

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_52  rs_tx_isptx_isptx_sd_setting_reg_52;
struct _rs_tx_isptx_isptx_sd_setting_reg_52 {
    unsigned int reg_isp_sd_set_reg_52                      : 8;
    unsigned int reg_isp_sd_set_reg_53                      : 8;
    unsigned int reg_isp_sd_set_reg_54                      : 8;
    unsigned int reg_isp_sd_set_reg_55                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_52(val) ((rs_tx_isptx_isptx_sd_setting_reg_52*)&(val))



#define TX_ISPTX_ISPTX_SD_SETTING_REG_56                                 (HV_ISPTX_BASE_ADDRESS + 0xA8)

#define TX_ISPTX_ISPTX_SD_SETTING_REG_56_struct                          rs_tx_isptx_isptx_sd_setting_reg_56

typedef struct _rs_tx_isptx_isptx_sd_setting_reg_56  rs_tx_isptx_isptx_sd_setting_reg_56;
struct _rs_tx_isptx_isptx_sd_setting_reg_56 {
    unsigned int reg_isp_sd_set_reg_56                      : 8;
    unsigned int reg_isp_sd_set_reg_57                      : 8;
    unsigned int reg_isp_sd_set_reg_58                      : 8;
    unsigned int reg_isp_sd_set_reg_59                      : 8;
};
#define tx_isptx_isptx_sd_setting_reg_56(val) ((rs_tx_isptx_isptx_sd_setting_reg_56*)&(val))



#define TX_ISPTX_ISP_TX_DEBUG_REG_00                                     (HV_ISPTX_BASE_ADDRESS + 0xAC)

#define TX_ISPTX_ISP_TX_DEBUG_REG_00_struct                              rs_tx_isptx_isp_tx_debug_reg_00

typedef struct _rs_tx_isptx_isp_tx_debug_reg_00  rs_tx_isptx_isp_tx_debug_reg_00;
struct _rs_tx_isptx_isp_tx_debug_reg_00 {
    unsigned int reg_isp_sd_lock_debug_sel                  : 1;
    unsigned int reg_isp_sd_lock_debug_value                : 1;
    unsigned int reg_isp_sd_lock_polarity                   : 1;
    unsigned int reserved                                   :29;
};
#define tx_isptx_isp_tx_debug_reg_00(val) ((rs_tx_isptx_isp_tx_debug_reg_00*)&(val))



#define TX_ISPTX_ISP_TX_DEBUG_REG_01                                     (HV_ISPTX_BASE_ADDRESS + 0xB0)

#define TX_ISPTX_ISP_TX_DEBUG_REG_01_struct                              rs_tx_isptx_isp_tx_debug_reg_01

typedef struct _rs_tx_isptx_isp_tx_debug_reg_01  rs_tx_isptx_isp_tx_debug_reg_01;
struct _rs_tx_isptx_isp_tx_debug_reg_01 {
    unsigned int reg_isp_rgb_debug_sel                      : 1;
    unsigned int reg_isp_rgb_debug_value_r                  :10;
    unsigned int reg_isp_rgb_debug_value_g                  :10;
    unsigned int reg_isp_rgb_debug_value_b                  :10;
    unsigned int reg_isp_dummy_data_delay_en                : 1;
};
#define tx_isptx_isp_tx_debug_reg_01(val) ((rs_tx_isptx_isp_tx_debug_reg_01*)&(val))



#define TX_ISPTX_ISP_TX_DUMMY_DATA_REG                                   (HV_ISPTX_BASE_ADDRESS + 0xB4)

#define TX_ISPTX_ISP_TX_DUMMY_DATA_REG_struct                            rs_tx_isptx_isp_tx_dummy_data_reg

typedef struct _rs_tx_isptx_isp_tx_dummy_data_reg  rs_tx_isptx_isp_tx_dummy_data_reg;
struct _rs_tx_isptx_isp_tx_dummy_data_reg {
    unsigned int reg_isp_dummy_data_en                      : 1;
    unsigned int reg_isp_dummy_data_random                  : 1;
    unsigned int reg_isp_dummy_data_r                       :10;
    unsigned int reg_isp_dummy_data_g                       :10;
    unsigned int reg_isp_dummy_data_b                       :10;
};
#define tx_isptx_isp_tx_dummy_data_reg(val) ((rs_tx_isptx_isp_tx_dummy_data_reg*)&(val))



#define TX_ISPTX_ISP_TX_H_CLR_PROCESS_REG                                (HV_ISPTX_BASE_ADDRESS + 0xB8)

#define TX_ISPTX_ISP_TX_H_CLR_PROCESS_REG_struct                         rs_tx_isptx_isp_tx_h_clr_process_reg

typedef struct _rs_tx_isptx_isp_tx_h_clr_process_reg  rs_tx_isptx_isp_tx_h_clr_process_reg;
struct _rs_tx_isptx_isp_tx_h_clr_process_reg {
    unsigned int reg_isp_h_clr_jmp_to_idle_en               : 1;
    unsigned int reserved                                   :31;
};
#define tx_isptx_isp_tx_h_clr_process_reg(val) ((rs_tx_isptx_isp_tx_h_clr_process_reg*)&(val))



#endif