#ifndef _HV_PAGE_HT7315_HDMI21_RX_EDID_00_H_
#define _HV_PAGE_HT7315_HDMI21_RX_EDID_00_H_

#ifndef HV_HDMI21_RX_EDID_00_BASE_ADDRESS
    #define HV_HDMI21_RX_EDID_00_BASE_ADDRESS                                         0x11008600
#endif


#define STANDBY_HDMI21_RX_EDID_00_00                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x00)

#define STANDBY_HDMI21_RX_EDID_00_00_struct                              rs_standby_hdmi21_rx_edid_00_00

typedef struct _rs_standby_hdmi21_rx_edid_00_00  rs_standby_hdmi21_rx_edid_00_00;
struct _rs_standby_hdmi21_rx_edid_00_00 {
    unsigned int reg_00_edid_data_00                        : 8;
    unsigned int reg_00_edid_data_01                        : 8;
    unsigned int reg_00_edid_data_02                        : 8;
    unsigned int reg_00_edid_data_03                        : 8;
};
#define standby_hdmi21_rx_edid_00_00(val) ((rs_standby_hdmi21_rx_edid_00_00*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_04                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x04)

#define STANDBY_HDMI21_RX_EDID_00_04_struct                              rs_standby_hdmi21_rx_edid_00_04

typedef struct _rs_standby_hdmi21_rx_edid_00_04  rs_standby_hdmi21_rx_edid_00_04;
struct _rs_standby_hdmi21_rx_edid_00_04 {
    unsigned int reg_00_edid_data_04                        : 8;
    unsigned int reg_00_edid_data_05                        : 8;
    unsigned int reg_00_edid_data_06                        : 8;
    unsigned int reg_00_edid_data_07                        : 8;
};
#define standby_hdmi21_rx_edid_00_04(val) ((rs_standby_hdmi21_rx_edid_00_04*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_08                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x08)

#define STANDBY_HDMI21_RX_EDID_00_08_struct                              rs_standby_hdmi21_rx_edid_00_08

typedef struct _rs_standby_hdmi21_rx_edid_00_08  rs_standby_hdmi21_rx_edid_00_08;
struct _rs_standby_hdmi21_rx_edid_00_08 {
    unsigned int reg_00_edid_data_08                        : 8;
    unsigned int reg_00_edid_data_09                        : 8;
    unsigned int reg_00_edid_data_0A                        : 8;
    unsigned int reg_00_edid_data_0B                        : 8;
};
#define standby_hdmi21_rx_edid_00_08(val) ((rs_standby_hdmi21_rx_edid_00_08*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_0C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x0C)

#define STANDBY_HDMI21_RX_EDID_00_0C_struct                              rs_standby_hdmi21_rx_edid_00_0c

typedef struct _rs_standby_hdmi21_rx_edid_00_0c  rs_standby_hdmi21_rx_edid_00_0c;
struct _rs_standby_hdmi21_rx_edid_00_0c {
    unsigned int reg_00_edid_data_0C                        : 8;
    unsigned int reg_00_edid_data_0D                        : 8;
    unsigned int reg_00_edid_data_0E                        : 8;
    unsigned int reg_00_edid_data_0F                        : 8;
};
#define standby_hdmi21_rx_edid_00_0c(val) ((rs_standby_hdmi21_rx_edid_00_0c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_10                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x10)

#define STANDBY_HDMI21_RX_EDID_00_10_struct                              rs_standby_hdmi21_rx_edid_00_10

typedef struct _rs_standby_hdmi21_rx_edid_00_10  rs_standby_hdmi21_rx_edid_00_10;
struct _rs_standby_hdmi21_rx_edid_00_10 {
    unsigned int reg_00_edid_data_10                        : 8;
    unsigned int reg_00_edid_data_11                        : 8;
    unsigned int reg_00_edid_data_12                        : 8;
    unsigned int reg_00_edid_data_13                        : 8;
};
#define standby_hdmi21_rx_edid_00_10(val) ((rs_standby_hdmi21_rx_edid_00_10*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_14                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x14)

#define STANDBY_HDMI21_RX_EDID_00_14_struct                              rs_standby_hdmi21_rx_edid_00_14

typedef struct _rs_standby_hdmi21_rx_edid_00_14  rs_standby_hdmi21_rx_edid_00_14;
struct _rs_standby_hdmi21_rx_edid_00_14 {
    unsigned int reg_00_edid_data_14                        : 8;
    unsigned int reg_00_edid_data_15                        : 8;
    unsigned int reg_00_edid_data_16                        : 8;
    unsigned int reg_00_edid_data_17                        : 8;
};
#define standby_hdmi21_rx_edid_00_14(val) ((rs_standby_hdmi21_rx_edid_00_14*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_18                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x18)

#define STANDBY_HDMI21_RX_EDID_00_18_struct                              rs_standby_hdmi21_rx_edid_00_18

typedef struct _rs_standby_hdmi21_rx_edid_00_18  rs_standby_hdmi21_rx_edid_00_18;
struct _rs_standby_hdmi21_rx_edid_00_18 {
    unsigned int reg_00_edid_data_18                        : 8;
    unsigned int reg_00_edid_data_19                        : 8;
    unsigned int reg_00_edid_data_1A                        : 8;
    unsigned int reg_00_edid_data_1B                        : 8;
};
#define standby_hdmi21_rx_edid_00_18(val) ((rs_standby_hdmi21_rx_edid_00_18*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_1C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x1C)

#define STANDBY_HDMI21_RX_EDID_00_1C_struct                              rs_standby_hdmi21_rx_edid_00_1c

typedef struct _rs_standby_hdmi21_rx_edid_00_1c  rs_standby_hdmi21_rx_edid_00_1c;
struct _rs_standby_hdmi21_rx_edid_00_1c {
    unsigned int reg_00_edid_data_1C                        : 8;
    unsigned int reg_00_edid_data_1D                        : 8;
    unsigned int reg_00_edid_data_1E                        : 8;
    unsigned int reg_00_edid_data_1F                        : 8;
};
#define standby_hdmi21_rx_edid_00_1c(val) ((rs_standby_hdmi21_rx_edid_00_1c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_20                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x20)

#define STANDBY_HDMI21_RX_EDID_00_20_struct                              rs_standby_hdmi21_rx_edid_00_20

typedef struct _rs_standby_hdmi21_rx_edid_00_20  rs_standby_hdmi21_rx_edid_00_20;
struct _rs_standby_hdmi21_rx_edid_00_20 {
    unsigned int reg_00_edid_data_20                        : 8;
    unsigned int reg_00_edid_data_21                        : 8;
    unsigned int reg_00_edid_data_22                        : 8;
    unsigned int reg_00_edid_data_23                        : 8;
};
#define standby_hdmi21_rx_edid_00_20(val) ((rs_standby_hdmi21_rx_edid_00_20*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_24                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x24)

#define STANDBY_HDMI21_RX_EDID_00_24_struct                              rs_standby_hdmi21_rx_edid_00_24

typedef struct _rs_standby_hdmi21_rx_edid_00_24  rs_standby_hdmi21_rx_edid_00_24;
struct _rs_standby_hdmi21_rx_edid_00_24 {
    unsigned int reg_00_edid_data_24                        : 8;
    unsigned int reg_00_edid_data_25                        : 8;
    unsigned int reg_00_edid_data_26                        : 8;
    unsigned int reg_00_edid_data_27                        : 8;
};
#define standby_hdmi21_rx_edid_00_24(val) ((rs_standby_hdmi21_rx_edid_00_24*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_28                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x28)

#define STANDBY_HDMI21_RX_EDID_00_28_struct                              rs_standby_hdmi21_rx_edid_00_28

typedef struct _rs_standby_hdmi21_rx_edid_00_28  rs_standby_hdmi21_rx_edid_00_28;
struct _rs_standby_hdmi21_rx_edid_00_28 {
    unsigned int reg_00_edid_data_28                        : 8;
    unsigned int reg_00_edid_data_29                        : 8;
    unsigned int reg_00_edid_data_2A                        : 8;
    unsigned int reg_00_edid_data_2B                        : 8;
};
#define standby_hdmi21_rx_edid_00_28(val) ((rs_standby_hdmi21_rx_edid_00_28*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_2C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x2C)

#define STANDBY_HDMI21_RX_EDID_00_2C_struct                              rs_standby_hdmi21_rx_edid_00_2c

typedef struct _rs_standby_hdmi21_rx_edid_00_2c  rs_standby_hdmi21_rx_edid_00_2c;
struct _rs_standby_hdmi21_rx_edid_00_2c {
    unsigned int reg_00_edid_data_2C                        : 8;
    unsigned int reg_00_edid_data_2D                        : 8;
    unsigned int reg_00_edid_data_2E                        : 8;
    unsigned int reg_00_edid_data_2F                        : 8;
};
#define standby_hdmi21_rx_edid_00_2c(val) ((rs_standby_hdmi21_rx_edid_00_2c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_30                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x30)

#define STANDBY_HDMI21_RX_EDID_00_30_struct                              rs_standby_hdmi21_rx_edid_00_30

typedef struct _rs_standby_hdmi21_rx_edid_00_30  rs_standby_hdmi21_rx_edid_00_30;
struct _rs_standby_hdmi21_rx_edid_00_30 {
    unsigned int reg_00_edid_data_30                        : 8;
    unsigned int reg_00_edid_data_31                        : 8;
    unsigned int reg_00_edid_data_32                        : 8;
    unsigned int reg_00_edid_data_33                        : 8;
};
#define standby_hdmi21_rx_edid_00_30(val) ((rs_standby_hdmi21_rx_edid_00_30*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_34                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x34)

#define STANDBY_HDMI21_RX_EDID_00_34_struct                              rs_standby_hdmi21_rx_edid_00_34

typedef struct _rs_standby_hdmi21_rx_edid_00_34  rs_standby_hdmi21_rx_edid_00_34;
struct _rs_standby_hdmi21_rx_edid_00_34 {
    unsigned int reg_00_edid_data_34                        : 8;
    unsigned int reg_00_edid_data_35                        : 8;
    unsigned int reg_00_edid_data_36                        : 8;
    unsigned int reg_00_edid_data_37                        : 8;
};
#define standby_hdmi21_rx_edid_00_34(val) ((rs_standby_hdmi21_rx_edid_00_34*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_38                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x38)

#define STANDBY_HDMI21_RX_EDID_00_38_struct                              rs_standby_hdmi21_rx_edid_00_38

typedef struct _rs_standby_hdmi21_rx_edid_00_38  rs_standby_hdmi21_rx_edid_00_38;
struct _rs_standby_hdmi21_rx_edid_00_38 {
    unsigned int reg_00_edid_data_38                        : 8;
    unsigned int reg_00_edid_data_39                        : 8;
    unsigned int reg_00_edid_data_3A                        : 8;
    unsigned int reg_00_edid_data_3B                        : 8;
};
#define standby_hdmi21_rx_edid_00_38(val) ((rs_standby_hdmi21_rx_edid_00_38*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_3C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x3C)

#define STANDBY_HDMI21_RX_EDID_00_3C_struct                              rs_standby_hdmi21_rx_edid_00_3c

typedef struct _rs_standby_hdmi21_rx_edid_00_3c  rs_standby_hdmi21_rx_edid_00_3c;
struct _rs_standby_hdmi21_rx_edid_00_3c {
    unsigned int reg_00_edid_data_3C                        : 8;
    unsigned int reg_00_edid_data_3D                        : 8;
    unsigned int reg_00_edid_data_3E                        : 8;
    unsigned int reg_00_edid_data_3F                        : 8;
};
#define standby_hdmi21_rx_edid_00_3c(val) ((rs_standby_hdmi21_rx_edid_00_3c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_40                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x40)

#define STANDBY_HDMI21_RX_EDID_00_40_struct                              rs_standby_hdmi21_rx_edid_00_40

typedef struct _rs_standby_hdmi21_rx_edid_00_40  rs_standby_hdmi21_rx_edid_00_40;
struct _rs_standby_hdmi21_rx_edid_00_40 {
    unsigned int reg_00_edid_data_40                        : 8;
    unsigned int reg_00_edid_data_41                        : 8;
    unsigned int reg_00_edid_data_42                        : 8;
    unsigned int reg_00_edid_data_43                        : 8;
};
#define standby_hdmi21_rx_edid_00_40(val) ((rs_standby_hdmi21_rx_edid_00_40*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_44                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x44)

#define STANDBY_HDMI21_RX_EDID_00_44_struct                              rs_standby_hdmi21_rx_edid_00_44

typedef struct _rs_standby_hdmi21_rx_edid_00_44  rs_standby_hdmi21_rx_edid_00_44;
struct _rs_standby_hdmi21_rx_edid_00_44 {
    unsigned int reg_00_edid_data_44                        : 8;
    unsigned int reg_00_edid_data_45                        : 8;
    unsigned int reg_00_edid_data_46                        : 8;
    unsigned int reg_00_edid_data_47                        : 8;
};
#define standby_hdmi21_rx_edid_00_44(val) ((rs_standby_hdmi21_rx_edid_00_44*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_48                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x48)

#define STANDBY_HDMI21_RX_EDID_00_48_struct                              rs_standby_hdmi21_rx_edid_00_48

typedef struct _rs_standby_hdmi21_rx_edid_00_48  rs_standby_hdmi21_rx_edid_00_48;
struct _rs_standby_hdmi21_rx_edid_00_48 {
    unsigned int reg_00_edid_data_48                        : 8;
    unsigned int reg_00_edid_data_49                        : 8;
    unsigned int reg_00_edid_data_4A                        : 8;
    unsigned int reg_00_edid_data_4B                        : 8;
};
#define standby_hdmi21_rx_edid_00_48(val) ((rs_standby_hdmi21_rx_edid_00_48*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_4C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x4C)

#define STANDBY_HDMI21_RX_EDID_00_4C_struct                              rs_standby_hdmi21_rx_edid_00_4c

typedef struct _rs_standby_hdmi21_rx_edid_00_4c  rs_standby_hdmi21_rx_edid_00_4c;
struct _rs_standby_hdmi21_rx_edid_00_4c {
    unsigned int reg_00_edid_data_4C                        : 8;
    unsigned int reg_00_edid_data_4D                        : 8;
    unsigned int reg_00_edid_data_4E                        : 8;
    unsigned int reg_00_edid_data_4F                        : 8;
};
#define standby_hdmi21_rx_edid_00_4c(val) ((rs_standby_hdmi21_rx_edid_00_4c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_50                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x50)

#define STANDBY_HDMI21_RX_EDID_00_50_struct                              rs_standby_hdmi21_rx_edid_00_50

typedef struct _rs_standby_hdmi21_rx_edid_00_50  rs_standby_hdmi21_rx_edid_00_50;
struct _rs_standby_hdmi21_rx_edid_00_50 {
    unsigned int reg_00_edid_data_50                        : 8;
    unsigned int reg_00_edid_data_51                        : 8;
    unsigned int reg_00_edid_data_52                        : 8;
    unsigned int reg_00_edid_data_53                        : 8;
};
#define standby_hdmi21_rx_edid_00_50(val) ((rs_standby_hdmi21_rx_edid_00_50*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_54                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x54)

#define STANDBY_HDMI21_RX_EDID_00_54_struct                              rs_standby_hdmi21_rx_edid_00_54

typedef struct _rs_standby_hdmi21_rx_edid_00_54  rs_standby_hdmi21_rx_edid_00_54;
struct _rs_standby_hdmi21_rx_edid_00_54 {
    unsigned int reg_00_edid_data_54                        : 8;
    unsigned int reg_00_edid_data_55                        : 8;
    unsigned int reg_00_edid_data_56                        : 8;
    unsigned int reg_00_edid_data_57                        : 8;
};
#define standby_hdmi21_rx_edid_00_54(val) ((rs_standby_hdmi21_rx_edid_00_54*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_58                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x58)

#define STANDBY_HDMI21_RX_EDID_00_58_struct                              rs_standby_hdmi21_rx_edid_00_58

typedef struct _rs_standby_hdmi21_rx_edid_00_58  rs_standby_hdmi21_rx_edid_00_58;
struct _rs_standby_hdmi21_rx_edid_00_58 {
    unsigned int reg_00_edid_data_58                        : 8;
    unsigned int reg_00_edid_data_59                        : 8;
    unsigned int reg_00_edid_data_5A                        : 8;
    unsigned int reg_00_edid_data_5B                        : 8;
};
#define standby_hdmi21_rx_edid_00_58(val) ((rs_standby_hdmi21_rx_edid_00_58*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_5C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x5C)

#define STANDBY_HDMI21_RX_EDID_00_5C_struct                              rs_standby_hdmi21_rx_edid_00_5c

typedef struct _rs_standby_hdmi21_rx_edid_00_5c  rs_standby_hdmi21_rx_edid_00_5c;
struct _rs_standby_hdmi21_rx_edid_00_5c {
    unsigned int reg_00_edid_data_5C                        : 8;
    unsigned int reg_00_edid_data_5D                        : 8;
    unsigned int reg_00_edid_data_5E                        : 8;
    unsigned int reg_00_edid_data_5F                        : 8;
};
#define standby_hdmi21_rx_edid_00_5c(val) ((rs_standby_hdmi21_rx_edid_00_5c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_60                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x60)

#define STANDBY_HDMI21_RX_EDID_00_60_struct                              rs_standby_hdmi21_rx_edid_00_60

typedef struct _rs_standby_hdmi21_rx_edid_00_60  rs_standby_hdmi21_rx_edid_00_60;
struct _rs_standby_hdmi21_rx_edid_00_60 {
    unsigned int reg_00_edid_data_60                        : 8;
    unsigned int reg_00_edid_data_61                        : 8;
    unsigned int reg_00_edid_data_62                        : 8;
    unsigned int reg_00_edid_data_63                        : 8;
};
#define standby_hdmi21_rx_edid_00_60(val) ((rs_standby_hdmi21_rx_edid_00_60*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_64                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x64)

#define STANDBY_HDMI21_RX_EDID_00_64_struct                              rs_standby_hdmi21_rx_edid_00_64

typedef struct _rs_standby_hdmi21_rx_edid_00_64  rs_standby_hdmi21_rx_edid_00_64;
struct _rs_standby_hdmi21_rx_edid_00_64 {
    unsigned int reg_00_edid_data_64                        : 8;
    unsigned int reg_00_edid_data_65                        : 8;
    unsigned int reg_00_edid_data_66                        : 8;
    unsigned int reg_00_edid_data_67                        : 8;
};
#define standby_hdmi21_rx_edid_00_64(val) ((rs_standby_hdmi21_rx_edid_00_64*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_68                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x68)

#define STANDBY_HDMI21_RX_EDID_00_68_struct                              rs_standby_hdmi21_rx_edid_00_68

typedef struct _rs_standby_hdmi21_rx_edid_00_68  rs_standby_hdmi21_rx_edid_00_68;
struct _rs_standby_hdmi21_rx_edid_00_68 {
    unsigned int reg_00_edid_data_68                        : 8;
    unsigned int reg_00_edid_data_69                        : 8;
    unsigned int reg_00_edid_data_6A                        : 8;
    unsigned int reg_00_edid_data_6B                        : 8;
};
#define standby_hdmi21_rx_edid_00_68(val) ((rs_standby_hdmi21_rx_edid_00_68*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_6C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x6C)

#define STANDBY_HDMI21_RX_EDID_00_6C_struct                              rs_standby_hdmi21_rx_edid_00_6c

typedef struct _rs_standby_hdmi21_rx_edid_00_6c  rs_standby_hdmi21_rx_edid_00_6c;
struct _rs_standby_hdmi21_rx_edid_00_6c {
    unsigned int reg_00_edid_data_6C                        : 8;
    unsigned int reg_00_edid_data_6D                        : 8;
    unsigned int reg_00_edid_data_6E                        : 8;
    unsigned int reg_00_edid_data_6F                        : 8;
};
#define standby_hdmi21_rx_edid_00_6c(val) ((rs_standby_hdmi21_rx_edid_00_6c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_70                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x70)

#define STANDBY_HDMI21_RX_EDID_00_70_struct                              rs_standby_hdmi21_rx_edid_00_70

typedef struct _rs_standby_hdmi21_rx_edid_00_70  rs_standby_hdmi21_rx_edid_00_70;
struct _rs_standby_hdmi21_rx_edid_00_70 {
    unsigned int reg_00_edid_data_70                        : 8;
    unsigned int reg_00_edid_data_71                        : 8;
    unsigned int reg_00_edid_data_72                        : 8;
    unsigned int reg_00_edid_data_73                        : 8;
};
#define standby_hdmi21_rx_edid_00_70(val) ((rs_standby_hdmi21_rx_edid_00_70*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_74                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x74)

#define STANDBY_HDMI21_RX_EDID_00_74_struct                              rs_standby_hdmi21_rx_edid_00_74

typedef struct _rs_standby_hdmi21_rx_edid_00_74  rs_standby_hdmi21_rx_edid_00_74;
struct _rs_standby_hdmi21_rx_edid_00_74 {
    unsigned int reg_00_edid_data_74                        : 8;
    unsigned int reg_00_edid_data_75                        : 8;
    unsigned int reg_00_edid_data_76                        : 8;
    unsigned int reg_00_edid_data_77                        : 8;
};
#define standby_hdmi21_rx_edid_00_74(val) ((rs_standby_hdmi21_rx_edid_00_74*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_78                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x78)

#define STANDBY_HDMI21_RX_EDID_00_78_struct                              rs_standby_hdmi21_rx_edid_00_78

typedef struct _rs_standby_hdmi21_rx_edid_00_78  rs_standby_hdmi21_rx_edid_00_78;
struct _rs_standby_hdmi21_rx_edid_00_78 {
    unsigned int reg_00_edid_data_78                        : 8;
    unsigned int reg_00_edid_data_79                        : 8;
    unsigned int reg_00_edid_data_7A                        : 8;
    unsigned int reg_00_edid_data_7B                        : 8;
};
#define standby_hdmi21_rx_edid_00_78(val) ((rs_standby_hdmi21_rx_edid_00_78*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_7C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x7C)

#define STANDBY_HDMI21_RX_EDID_00_7C_struct                              rs_standby_hdmi21_rx_edid_00_7c

typedef struct _rs_standby_hdmi21_rx_edid_00_7c  rs_standby_hdmi21_rx_edid_00_7c;
struct _rs_standby_hdmi21_rx_edid_00_7c {
    unsigned int reg_00_edid_data_7C                        : 8;
    unsigned int reg_00_edid_data_7D                        : 8;
    unsigned int reg_00_edid_data_7E                        : 8;
    unsigned int reg_00_edid_data_7F                        : 8;
};
#define standby_hdmi21_rx_edid_00_7c(val) ((rs_standby_hdmi21_rx_edid_00_7c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_80                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x80)

#define STANDBY_HDMI21_RX_EDID_00_80_struct                              rs_standby_hdmi21_rx_edid_00_80

typedef struct _rs_standby_hdmi21_rx_edid_00_80  rs_standby_hdmi21_rx_edid_00_80;
struct _rs_standby_hdmi21_rx_edid_00_80 {
    unsigned int reg_00_edid_data_80                        : 8;
    unsigned int reg_00_edid_data_81                        : 8;
    unsigned int reg_00_edid_data_82                        : 8;
    unsigned int reg_00_edid_data_83                        : 8;
};
#define standby_hdmi21_rx_edid_00_80(val) ((rs_standby_hdmi21_rx_edid_00_80*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_84                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x84)

#define STANDBY_HDMI21_RX_EDID_00_84_struct                              rs_standby_hdmi21_rx_edid_00_84

typedef struct _rs_standby_hdmi21_rx_edid_00_84  rs_standby_hdmi21_rx_edid_00_84;
struct _rs_standby_hdmi21_rx_edid_00_84 {
    unsigned int reg_00_edid_data_84                        : 8;
    unsigned int reg_00_edid_data_85                        : 8;
    unsigned int reg_00_edid_data_86                        : 8;
    unsigned int reg_00_edid_data_87                        : 8;
};
#define standby_hdmi21_rx_edid_00_84(val) ((rs_standby_hdmi21_rx_edid_00_84*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_88                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x88)

#define STANDBY_HDMI21_RX_EDID_00_88_struct                              rs_standby_hdmi21_rx_edid_00_88

typedef struct _rs_standby_hdmi21_rx_edid_00_88  rs_standby_hdmi21_rx_edid_00_88;
struct _rs_standby_hdmi21_rx_edid_00_88 {
    unsigned int reg_00_edid_data_88                        : 8;
    unsigned int reg_00_edid_data_89                        : 8;
    unsigned int reg_00_edid_data_8A                        : 8;
    unsigned int reg_00_edid_data_8B                        : 8;
};
#define standby_hdmi21_rx_edid_00_88(val) ((rs_standby_hdmi21_rx_edid_00_88*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_8C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x8C)

#define STANDBY_HDMI21_RX_EDID_00_8C_struct                              rs_standby_hdmi21_rx_edid_00_8c

typedef struct _rs_standby_hdmi21_rx_edid_00_8c  rs_standby_hdmi21_rx_edid_00_8c;
struct _rs_standby_hdmi21_rx_edid_00_8c {
    unsigned int reg_00_edid_data_8C                        : 8;
    unsigned int reg_00_edid_data_8D                        : 8;
    unsigned int reg_00_edid_data_8E                        : 8;
    unsigned int reg_00_edid_data_8F                        : 8;
};
#define standby_hdmi21_rx_edid_00_8c(val) ((rs_standby_hdmi21_rx_edid_00_8c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_90                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x90)

#define STANDBY_HDMI21_RX_EDID_00_90_struct                              rs_standby_hdmi21_rx_edid_00_90

typedef struct _rs_standby_hdmi21_rx_edid_00_90  rs_standby_hdmi21_rx_edid_00_90;
struct _rs_standby_hdmi21_rx_edid_00_90 {
    unsigned int reg_00_edid_data_90                        : 8;
    unsigned int reg_00_edid_data_91                        : 8;
    unsigned int reg_00_edid_data_92                        : 8;
    unsigned int reg_00_edid_data_93                        : 8;
};
#define standby_hdmi21_rx_edid_00_90(val) ((rs_standby_hdmi21_rx_edid_00_90*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_94                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x94)

#define STANDBY_HDMI21_RX_EDID_00_94_struct                              rs_standby_hdmi21_rx_edid_00_94

typedef struct _rs_standby_hdmi21_rx_edid_00_94  rs_standby_hdmi21_rx_edid_00_94;
struct _rs_standby_hdmi21_rx_edid_00_94 {
    unsigned int reg_00_edid_data_94                        : 8;
    unsigned int reg_00_edid_data_95                        : 8;
    unsigned int reg_00_edid_data_96                        : 8;
    unsigned int reg_00_edid_data_97                        : 8;
};
#define standby_hdmi21_rx_edid_00_94(val) ((rs_standby_hdmi21_rx_edid_00_94*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_98                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x98)

#define STANDBY_HDMI21_RX_EDID_00_98_struct                              rs_standby_hdmi21_rx_edid_00_98

typedef struct _rs_standby_hdmi21_rx_edid_00_98  rs_standby_hdmi21_rx_edid_00_98;
struct _rs_standby_hdmi21_rx_edid_00_98 {
    unsigned int reg_00_edid_data_98                        : 8;
    unsigned int reg_00_edid_data_99                        : 8;
    unsigned int reg_00_edid_data_9A                        : 8;
    unsigned int reg_00_edid_data_9B                        : 8;
};
#define standby_hdmi21_rx_edid_00_98(val) ((rs_standby_hdmi21_rx_edid_00_98*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_9C                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0x9C)

#define STANDBY_HDMI21_RX_EDID_00_9C_struct                              rs_standby_hdmi21_rx_edid_00_9c

typedef struct _rs_standby_hdmi21_rx_edid_00_9c  rs_standby_hdmi21_rx_edid_00_9c;
struct _rs_standby_hdmi21_rx_edid_00_9c {
    unsigned int reg_00_edid_data_9C                        : 8;
    unsigned int reg_00_edid_data_9D                        : 8;
    unsigned int reg_00_edid_data_9E                        : 8;
    unsigned int reg_00_edid_data_9F                        : 8;
};
#define standby_hdmi21_rx_edid_00_9c(val) ((rs_standby_hdmi21_rx_edid_00_9c*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_A0                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xA0)

#define STANDBY_HDMI21_RX_EDID_00_A0_struct                              rs_standby_hdmi21_rx_edid_00_a0

typedef struct _rs_standby_hdmi21_rx_edid_00_a0  rs_standby_hdmi21_rx_edid_00_a0;
struct _rs_standby_hdmi21_rx_edid_00_a0 {
    unsigned int reg_00_edid_data_A0                        : 8;
    unsigned int reg_00_edid_data_A1                        : 8;
    unsigned int reg_00_edid_data_A2                        : 8;
    unsigned int reg_00_edid_data_A3                        : 8;
};
#define standby_hdmi21_rx_edid_00_a0(val) ((rs_standby_hdmi21_rx_edid_00_a0*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_A4                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xA4)

#define STANDBY_HDMI21_RX_EDID_00_A4_struct                              rs_standby_hdmi21_rx_edid_00_a4

typedef struct _rs_standby_hdmi21_rx_edid_00_a4  rs_standby_hdmi21_rx_edid_00_a4;
struct _rs_standby_hdmi21_rx_edid_00_a4 {
    unsigned int reg_00_edid_data_A4                        : 8;
    unsigned int reg_00_edid_data_A5                        : 8;
    unsigned int reg_00_edid_data_A6                        : 8;
    unsigned int reg_00_edid_data_A7                        : 8;
};
#define standby_hdmi21_rx_edid_00_a4(val) ((rs_standby_hdmi21_rx_edid_00_a4*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_A8                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xA8)

#define STANDBY_HDMI21_RX_EDID_00_A8_struct                              rs_standby_hdmi21_rx_edid_00_a8

typedef struct _rs_standby_hdmi21_rx_edid_00_a8  rs_standby_hdmi21_rx_edid_00_a8;
struct _rs_standby_hdmi21_rx_edid_00_a8 {
    unsigned int reg_00_edid_data_A8                        : 8;
    unsigned int reg_00_edid_data_A9                        : 8;
    unsigned int reg_00_edid_data_AA                        : 8;
    unsigned int reg_00_edid_data_AB                        : 8;
};
#define standby_hdmi21_rx_edid_00_a8(val) ((rs_standby_hdmi21_rx_edid_00_a8*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_AC                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xAC)

#define STANDBY_HDMI21_RX_EDID_00_AC_struct                              rs_standby_hdmi21_rx_edid_00_ac

typedef struct _rs_standby_hdmi21_rx_edid_00_ac  rs_standby_hdmi21_rx_edid_00_ac;
struct _rs_standby_hdmi21_rx_edid_00_ac {
    unsigned int reg_00_edid_data_AC                        : 8;
    unsigned int reg_00_edid_data_AD                        : 8;
    unsigned int reg_00_edid_data_AE                        : 8;
    unsigned int reg_00_edid_data_AF                        : 8;
};
#define standby_hdmi21_rx_edid_00_ac(val) ((rs_standby_hdmi21_rx_edid_00_ac*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_B0                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xB0)

#define STANDBY_HDMI21_RX_EDID_00_B0_struct                              rs_standby_hdmi21_rx_edid_00_b0

typedef struct _rs_standby_hdmi21_rx_edid_00_b0  rs_standby_hdmi21_rx_edid_00_b0;
struct _rs_standby_hdmi21_rx_edid_00_b0 {
    unsigned int reg_00_edid_data_B0                        : 8;
    unsigned int reg_00_edid_data_B1                        : 8;
    unsigned int reg_00_edid_data_B2                        : 8;
    unsigned int reg_00_edid_data_B3                        : 8;
};
#define standby_hdmi21_rx_edid_00_b0(val) ((rs_standby_hdmi21_rx_edid_00_b0*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_B4                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xB4)

#define STANDBY_HDMI21_RX_EDID_00_B4_struct                              rs_standby_hdmi21_rx_edid_00_b4

typedef struct _rs_standby_hdmi21_rx_edid_00_b4  rs_standby_hdmi21_rx_edid_00_b4;
struct _rs_standby_hdmi21_rx_edid_00_b4 {
    unsigned int reg_00_edid_data_B4                        : 8;
    unsigned int reg_00_edid_data_B5                        : 8;
    unsigned int reg_00_edid_data_B6                        : 8;
    unsigned int reg_00_edid_data_B7                        : 8;
};
#define standby_hdmi21_rx_edid_00_b4(val) ((rs_standby_hdmi21_rx_edid_00_b4*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_B8                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xB8)

#define STANDBY_HDMI21_RX_EDID_00_B8_struct                              rs_standby_hdmi21_rx_edid_00_b8

typedef struct _rs_standby_hdmi21_rx_edid_00_b8  rs_standby_hdmi21_rx_edid_00_b8;
struct _rs_standby_hdmi21_rx_edid_00_b8 {
    unsigned int reg_00_edid_data_B8                        : 8;
    unsigned int reg_00_edid_data_B9                        : 8;
    unsigned int reg_00_edid_data_BA                        : 8;
    unsigned int reg_00_edid_data_BB                        : 8;
};
#define standby_hdmi21_rx_edid_00_b8(val) ((rs_standby_hdmi21_rx_edid_00_b8*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_BC                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xBC)

#define STANDBY_HDMI21_RX_EDID_00_BC_struct                              rs_standby_hdmi21_rx_edid_00_bc

typedef struct _rs_standby_hdmi21_rx_edid_00_bc  rs_standby_hdmi21_rx_edid_00_bc;
struct _rs_standby_hdmi21_rx_edid_00_bc {
    unsigned int reg_00_edid_data_BC                        : 8;
    unsigned int reg_00_edid_data_BD                        : 8;
    unsigned int reg_00_edid_data_BE                        : 8;
    unsigned int reg_00_edid_data_BF                        : 8;
};
#define standby_hdmi21_rx_edid_00_bc(val) ((rs_standby_hdmi21_rx_edid_00_bc*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_C0                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xC0)

#define STANDBY_HDMI21_RX_EDID_00_C0_struct                              rs_standby_hdmi21_rx_edid_00_c0

typedef struct _rs_standby_hdmi21_rx_edid_00_c0  rs_standby_hdmi21_rx_edid_00_c0;
struct _rs_standby_hdmi21_rx_edid_00_c0 {
    unsigned int reg_00_edid_data_C0                        : 8;
    unsigned int reg_00_edid_data_C1                        : 8;
    unsigned int reg_00_edid_data_C2                        : 8;
    unsigned int reg_00_edid_data_C3                        : 8;
};
#define standby_hdmi21_rx_edid_00_c0(val) ((rs_standby_hdmi21_rx_edid_00_c0*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_C4                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xC4)

#define STANDBY_HDMI21_RX_EDID_00_C4_struct                              rs_standby_hdmi21_rx_edid_00_c4

typedef struct _rs_standby_hdmi21_rx_edid_00_c4  rs_standby_hdmi21_rx_edid_00_c4;
struct _rs_standby_hdmi21_rx_edid_00_c4 {
    unsigned int reg_00_edid_data_C4                        : 8;
    unsigned int reg_00_edid_data_C5                        : 8;
    unsigned int reg_00_edid_data_C6                        : 8;
    unsigned int reg_00_edid_data_C7                        : 8;
};
#define standby_hdmi21_rx_edid_00_c4(val) ((rs_standby_hdmi21_rx_edid_00_c4*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_C8                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xC8)

#define STANDBY_HDMI21_RX_EDID_00_C8_struct                              rs_standby_hdmi21_rx_edid_00_c8

typedef struct _rs_standby_hdmi21_rx_edid_00_c8  rs_standby_hdmi21_rx_edid_00_c8;
struct _rs_standby_hdmi21_rx_edid_00_c8 {
    unsigned int reg_00_edid_data_C8                        : 8;
    unsigned int reg_00_edid_data_C9                        : 8;
    unsigned int reg_00_edid_data_CA                        : 8;
    unsigned int reg_00_edid_data_CB                        : 8;
};
#define standby_hdmi21_rx_edid_00_c8(val) ((rs_standby_hdmi21_rx_edid_00_c8*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_CC                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xCC)

#define STANDBY_HDMI21_RX_EDID_00_CC_struct                              rs_standby_hdmi21_rx_edid_00_cc

typedef struct _rs_standby_hdmi21_rx_edid_00_cc  rs_standby_hdmi21_rx_edid_00_cc;
struct _rs_standby_hdmi21_rx_edid_00_cc {
    unsigned int reg_00_edid_data_CC                        : 8;
    unsigned int reg_00_edid_data_CD                        : 8;
    unsigned int reg_00_edid_data_CE                        : 8;
    unsigned int reg_00_edid_data_CF                        : 8;
};
#define standby_hdmi21_rx_edid_00_cc(val) ((rs_standby_hdmi21_rx_edid_00_cc*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_D0                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xD0)

#define STANDBY_HDMI21_RX_EDID_00_D0_struct                              rs_standby_hdmi21_rx_edid_00_d0

typedef struct _rs_standby_hdmi21_rx_edid_00_d0  rs_standby_hdmi21_rx_edid_00_d0;
struct _rs_standby_hdmi21_rx_edid_00_d0 {
    unsigned int reg_00_edid_data_D0                        : 8;
    unsigned int reg_00_edid_data_D1                        : 8;
    unsigned int reg_00_edid_data_D2                        : 8;
    unsigned int reg_00_edid_data_D3                        : 8;
};
#define standby_hdmi21_rx_edid_00_d0(val) ((rs_standby_hdmi21_rx_edid_00_d0*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_D4                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xD4)

#define STANDBY_HDMI21_RX_EDID_00_D4_struct                              rs_standby_hdmi21_rx_edid_00_d4

typedef struct _rs_standby_hdmi21_rx_edid_00_d4  rs_standby_hdmi21_rx_edid_00_d4;
struct _rs_standby_hdmi21_rx_edid_00_d4 {
    unsigned int reg_00_edid_data_D4                        : 8;
    unsigned int reg_00_edid_data_D5                        : 8;
    unsigned int reg_00_edid_data_D6                        : 8;
    unsigned int reg_00_edid_data_D7                        : 8;
};
#define standby_hdmi21_rx_edid_00_d4(val) ((rs_standby_hdmi21_rx_edid_00_d4*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_D8                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xD8)

#define STANDBY_HDMI21_RX_EDID_00_D8_struct                              rs_standby_hdmi21_rx_edid_00_d8

typedef struct _rs_standby_hdmi21_rx_edid_00_d8  rs_standby_hdmi21_rx_edid_00_d8;
struct _rs_standby_hdmi21_rx_edid_00_d8 {
    unsigned int reg_00_edid_data_D8                        : 8;
    unsigned int reg_00_edid_data_D9                        : 8;
    unsigned int reg_00_edid_data_DA                        : 8;
    unsigned int reg_00_edid_data_DB                        : 8;
};
#define standby_hdmi21_rx_edid_00_d8(val) ((rs_standby_hdmi21_rx_edid_00_d8*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_DC                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xDC)

#define STANDBY_HDMI21_RX_EDID_00_DC_struct                              rs_standby_hdmi21_rx_edid_00_dc

typedef struct _rs_standby_hdmi21_rx_edid_00_dc  rs_standby_hdmi21_rx_edid_00_dc;
struct _rs_standby_hdmi21_rx_edid_00_dc {
    unsigned int reg_00_edid_data_DC                        : 8;
    unsigned int reg_00_edid_data_DD                        : 8;
    unsigned int reg_00_edid_data_DE                        : 8;
    unsigned int reg_00_edid_data_DF                        : 8;
};
#define standby_hdmi21_rx_edid_00_dc(val) ((rs_standby_hdmi21_rx_edid_00_dc*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_E0                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xE0)

#define STANDBY_HDMI21_RX_EDID_00_E0_struct                              rs_standby_hdmi21_rx_edid_00_e0

typedef struct _rs_standby_hdmi21_rx_edid_00_e0  rs_standby_hdmi21_rx_edid_00_e0;
struct _rs_standby_hdmi21_rx_edid_00_e0 {
    unsigned int reg_00_edid_data_E0                        : 8;
    unsigned int reg_00_edid_data_E1                        : 8;
    unsigned int reg_00_edid_data_E2                        : 8;
    unsigned int reg_00_edid_data_E3                        : 8;
};
#define standby_hdmi21_rx_edid_00_e0(val) ((rs_standby_hdmi21_rx_edid_00_e0*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_E4                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xE4)

#define STANDBY_HDMI21_RX_EDID_00_E4_struct                              rs_standby_hdmi21_rx_edid_00_e4

typedef struct _rs_standby_hdmi21_rx_edid_00_e4  rs_standby_hdmi21_rx_edid_00_e4;
struct _rs_standby_hdmi21_rx_edid_00_e4 {
    unsigned int reg_00_edid_data_E4                        : 8;
    unsigned int reg_00_edid_data_E5                        : 8;
    unsigned int reg_00_edid_data_E6                        : 8;
    unsigned int reg_00_edid_data_E7                        : 8;
};
#define standby_hdmi21_rx_edid_00_e4(val) ((rs_standby_hdmi21_rx_edid_00_e4*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_E8                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xE8)

#define STANDBY_HDMI21_RX_EDID_00_E8_struct                              rs_standby_hdmi21_rx_edid_00_e8

typedef struct _rs_standby_hdmi21_rx_edid_00_e8  rs_standby_hdmi21_rx_edid_00_e8;
struct _rs_standby_hdmi21_rx_edid_00_e8 {
    unsigned int reg_00_edid_data_E8                        : 8;
    unsigned int reg_00_edid_data_E9                        : 8;
    unsigned int reg_00_edid_data_EA                        : 8;
    unsigned int reg_00_edid_data_EB                        : 8;
};
#define standby_hdmi21_rx_edid_00_e8(val) ((rs_standby_hdmi21_rx_edid_00_e8*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_EC                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xEC)

#define STANDBY_HDMI21_RX_EDID_00_EC_struct                              rs_standby_hdmi21_rx_edid_00_ec

typedef struct _rs_standby_hdmi21_rx_edid_00_ec  rs_standby_hdmi21_rx_edid_00_ec;
struct _rs_standby_hdmi21_rx_edid_00_ec {
    unsigned int reg_00_edid_data_EC                        : 8;
    unsigned int reg_00_edid_data_ED                        : 8;
    unsigned int reg_00_edid_data_EE                        : 8;
    unsigned int reg_00_edid_data_EF                        : 8;
};
#define standby_hdmi21_rx_edid_00_ec(val) ((rs_standby_hdmi21_rx_edid_00_ec*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_F0                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xF0)

#define STANDBY_HDMI21_RX_EDID_00_F0_struct                              rs_standby_hdmi21_rx_edid_00_f0

typedef struct _rs_standby_hdmi21_rx_edid_00_f0  rs_standby_hdmi21_rx_edid_00_f0;
struct _rs_standby_hdmi21_rx_edid_00_f0 {
    unsigned int reg_00_edid_data_F0                        : 8;
    unsigned int reg_00_edid_data_F1                        : 8;
    unsigned int reg_00_edid_data_F2                        : 8;
    unsigned int reg_00_edid_data_F3                        : 8;
};
#define standby_hdmi21_rx_edid_00_f0(val) ((rs_standby_hdmi21_rx_edid_00_f0*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_F4                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xF4)

#define STANDBY_HDMI21_RX_EDID_00_F4_struct                              rs_standby_hdmi21_rx_edid_00_f4

typedef struct _rs_standby_hdmi21_rx_edid_00_f4  rs_standby_hdmi21_rx_edid_00_f4;
struct _rs_standby_hdmi21_rx_edid_00_f4 {
    unsigned int reg_00_edid_data_F4                        : 8;
    unsigned int reg_00_edid_data_F5                        : 8;
    unsigned int reg_00_edid_data_F6                        : 8;
    unsigned int reg_00_edid_data_F7                        : 8;
};
#define standby_hdmi21_rx_edid_00_f4(val) ((rs_standby_hdmi21_rx_edid_00_f4*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_F8                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xF8)

#define STANDBY_HDMI21_RX_EDID_00_F8_struct                              rs_standby_hdmi21_rx_edid_00_f8

typedef struct _rs_standby_hdmi21_rx_edid_00_f8  rs_standby_hdmi21_rx_edid_00_f8;
struct _rs_standby_hdmi21_rx_edid_00_f8 {
    unsigned int reg_00_edid_data_F8                        : 8;
    unsigned int reg_00_edid_data_F9                        : 8;
    unsigned int reg_00_edid_data_FA                        : 8;
    unsigned int reg_00_edid_data_FB                        : 8;
};
#define standby_hdmi21_rx_edid_00_f8(val) ((rs_standby_hdmi21_rx_edid_00_f8*)&(val))



#define STANDBY_HDMI21_RX_EDID_00_FC                                     (HV_HDMI21_RX_EDID_00_BASE_ADDRESS + 0xFC)

#define STANDBY_HDMI21_RX_EDID_00_FC_struct                              rs_standby_hdmi21_rx_edid_00_fc

typedef struct _rs_standby_hdmi21_rx_edid_00_fc  rs_standby_hdmi21_rx_edid_00_fc;
struct _rs_standby_hdmi21_rx_edid_00_fc {
    unsigned int reg_00_edid_data_FC                        : 8;
    unsigned int reg_00_edid_data_FD                        : 8;
    unsigned int reg_00_edid_data_FE                        : 8;
    unsigned int reg_00_edid_data_FF                        : 8;
};
#define standby_hdmi21_rx_edid_00_fc(val) ((rs_standby_hdmi21_rx_edid_00_fc*)&(val))



#endif