/**
 * @file hv_chip_memory.h
 * @brief define ddr/sram memmap
 * @details anyware
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-09-05
 * @copyright 版权信息
*/

#ifndef _HV_CHIP_MEMORY_H
#define _HV_CHIP_MEMORY_H

/*************************************************
   DDR Option
*************************************************/

#define HV_MEMORY_CONFIG_DDR_SIZE                          0x4000000
#define HV_MEMORY_CONFIG_DDR_PHY                           16
#define HV_MEMORY_CONFIG_DDR2_FREQ                          1066
#define HV_MEMORY_CONFIG_DDR2_UTILIZATION_RATIO             0.7
#define HV_MEMORY_CONFIG_DDR3_FREQ                          2133
#define HV_MEMORY_CONFIG_DDR3_UTILIZATION_RATIO             0.75

#define HV_MEMORY_CONFIG_RISC_DDR_SIZE                      0x800000
/*
total 32k.
8k:userdata+factorydata+systemdta
4K:hdcp
4k:gamma
...
4k:err log.
*/
#define HV_MEMORY_CONFIG_MONITOR_CONFIG_DATA_SIZE           0x8000
#define HV_MEMORY_CONFIG_PQ_DATA_SIZE                       0x80000
#define HV_MEMORY_CONFIG_AUDIO_DDR_SIZE                     0xC0000
#define HV_MEMORY_CONFIG_OSD_DDR_SIZE                       0x100000
#define HV_MEMORY_CONFIG_STATIC_DDR_SIZE                    (HV_MEMORY_CONFIG_RISC_DDR_SIZE+HV_MEMORY_CONFIG_MONITOR_CONFIG_DATA_SIZE+HV_MEMORY_CONFIG_PQ_DATA_SIZE+HV_MEMORY_CONFIG_AUDIO_DDR_SIZE+HV_MEMORY_CONFIG_OSD_DDR_SIZE)

#define HV_MEMORY_CONFIG_RISC_DDR_START                     PHY_TO_VDM(0x00000000)
#define HV_MEMORY_CONFIG_MONITOR_CONFIG_DATA_START          (HV_MEMORY_CONFIG_RISC_DDR_START+HV_MEMORY_CONFIG_RISC_DDR_SIZE)
#define HV_LOG_BUF_SAVE    4096
#define HV_MEMORY_CONFIG_MONITOR_LOG_START                  HV_MEMORY_CONFIG_MONITOR_CONFIG_DATA_START
#define HV_HOT_FIX_SIZE    4096
#define HV_MEMORY_CONFIG_MONITOR_HOTFIX_START               HV_MEMORY_CONFIG_MONITOR_CONFIG_DATA_START+HV_LOG_BUF_SAVE

#define HV_MEMORY_CONFIG_PQ_DATA_START                      (HV_MEMORY_CONFIG_MONITOR_CONFIG_DATA_START+HV_MEMORY_CONFIG_MONITOR_CONFIG_DATA_SIZE)
#define HV_MEMORY_CONFIG_AUDIO_DDR_START                    (HV_MEMORY_CONFIG_PQ_DATA_START+HV_MEMORY_CONFIG_PQ_DATA_SIZE)
#define HV_MEMORY_CONFIG_AUDIO_DMA_DDR_START                VIRT_TO_PHY(HV_MEMORY_CONFIG_AUDIO_DDR_START)
#define HV_MEMORY_CONFIG_OSD_DDR_START                      (HV_MEMORY_CONFIG_AUDIO_DDR_START+HV_MEMORY_CONFIG_AUDIO_DDR_SIZE)
#define HV_MEMORY_CONFIG_OSD_DMA_DDR_START                  VIRT_TO_PHY(HV_MEMORY_CONFIG_OSD_DDR_START)
/*
 * Logo ddr start within 1M address space of osd ddr, located as below:
 *
 * ------------------------     <- HV_MEMORY_CONFIG_OSD_DDR_START
 *  Middle ware structures      <- 64KB reserved. first 16KB used for jpg decompress
 * ------------------------
 *  Driver data structures      <- 32KB
 * ------------------------
 *  Palette data                <- 8KB
 * ------------------------
 *  Index data                  <- 16KB
 * ------------------------
 *  Resource data               <- 64KB
 * ------------------------     <- HV_MEMORY_CONFIG_OSD_DMA_DDR_START
 *  Logo data
 * ------------------------     <- 1M end
 */
#define HV_MEMORY_CONFIG_OSD_LOGO_DDR_START                 (HV_MEMORY_CONFIG_OSD_DDR_START + 0x2e000)


/*************************************************
******************DDR Bandwidth option************
**************************************************/
/* (600/10*4*8) */
#define HV_MEMORY_CONFIG_RISC_DDR_BANDWIDTH                1920
/* (768*8*2*2/1024) */
#define HV_MEMORY_CONFIG_AUDIO_DDR_BANDWIDTH               24
/* (80*80*8*16*2*165/1024/1024) */
#define HV_MEMORY_CONFIG_LD_DDR_BANDWIDTH                  384
#define HV_MEMORY_CONFIG_STATIC_DDR_BANDWIDTH              (HV_MEMORY_CONFIG_RISC_DDR_BANDWIDTH+HV_MEMORY_CONFIG_AUDIO_DDR_BANDWIDTH+HV_MEMORY_CONFIG_LD_DDR_BANDWIDTH)


/**
 * @brief address conversion. \n
 * @details interface for physical address to vitrual address,or virtral address to physical address. \n
 */

#define PHY_TO_VIRT(addr)     ((addr) | 0xA0000000)
#define VIRT_TO_PHY(addr)     ((addr) & 0x1FFFFFFF)
#define PHY_TO_VDM(addr)      ((addr) | 0x80000000)

/**
 * @brief ddr start address and ddr size for risc0 \n
 * @details ddr start address and ddr size for risc0 \n
 */


/**
 * @brief sram start address and sram size for mips0 \n
 * @details sram start address and sram size for mips0 \n
 */
#define BOARD_SRAM_ADDR         PHY_TO_VDM(0x10000000)
#define BOARD_SRAM_SIZE         0x10000

#endif
