#ifndef _HV_PAGE_HT7315_DPU_WVDM_01_H_
#define _HV_PAGE_HT7315_DPU_WVDM_01_H_

#ifndef HV_DPU_WVDM_01_BASE_ADDRESS
    #define HV_DPU_WVDM_01_BASE_ADDRESS                                         0x11022B00
#endif


#define DISP_TOP_DPU_WVDM_01_00                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_WVDM_01_00_struct                                   rs_disp_top_dpu_wvdm_01_00

typedef struct _rs_disp_top_dpu_wvdm_01_00  rs_disp_top_dpu_wvdm_01_00;
struct _rs_disp_top_dpu_wvdm_01_00 {
    unsigned int reg_01_en                                  : 1;
    unsigned int reg_01_en_no_latch                         : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_wvdm_01_00(val) ((rs_disp_top_dpu_wvdm_01_00*)&(val))



#define DISP_TOP_DPU_WVDM_01_04                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_WVDM_01_04_struct                                   rs_disp_top_dpu_wvdm_01_04

typedef struct _rs_disp_top_dpu_wvdm_01_04  rs_disp_top_dpu_wvdm_01_04;
struct _rs_disp_top_dpu_wvdm_01_04 {
    unsigned int reg_01_dm_wr_buf_size                      :10;
    unsigned int reserved                                   :22;
};
#define disp_top_dpu_wvdm_01_04(val) ((rs_disp_top_dpu_wvdm_01_04*)&(val))



#define DISP_TOP_DPU_WVDM_01_08                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_WVDM_01_08_struct                                   rs_disp_top_dpu_wvdm_01_08

typedef struct _rs_disp_top_dpu_wvdm_01_08  rs_disp_top_dpu_wvdm_01_08;
struct _rs_disp_top_dpu_wvdm_01_08 {
    unsigned int reg_01_dm_wr_4k_bound_en                   : 1;
    unsigned int reserved_l1                                : 1;
    unsigned int reg_01_dm_wr_burst_len                     : 8;
    unsigned int reg_01_dm_wr_burst_rmd                     : 8;
    unsigned int reg_01_dm_wr_col_step_dir                  : 1;
    unsigned int reg_01_dm_wr_db_en                         : 1;
    unsigned int reg_01_dm_wr_enable                        : 1;
    unsigned int reg_01_dm_wr_line_step_dir                 : 1;
    unsigned int reg_01_dm_wr_outstanding                   : 4;
    unsigned int reg_01_dm_wr_ovflow_clr                    : 1;
    unsigned int reg_01_dm_wr_udflow_clr                    : 1;
    unsigned int reg_01_dm_start_addr_sw_enable             : 1;
    unsigned int reserved                                   : 3;
};
#define disp_top_dpu_wvdm_01_08(val) ((rs_disp_top_dpu_wvdm_01_08*)&(val))



#define DISP_TOP_DPU_WVDM_01_0C                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_WVDM_01_0C_struct                                   rs_disp_top_dpu_wvdm_01_0c

typedef struct _rs_disp_top_dpu_wvdm_01_0c  rs_disp_top_dpu_wvdm_01_0c;
struct _rs_disp_top_dpu_wvdm_01_0c {
    unsigned int reg_01_dm_wr_burst_num                     :32;
};
#define disp_top_dpu_wvdm_01_0c(val) ((rs_disp_top_dpu_wvdm_01_0c*)&(val))



#define DISP_TOP_DPU_WVDM_01_10                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_WVDM_01_10_struct                                   rs_disp_top_dpu_wvdm_01_10

typedef struct _rs_disp_top_dpu_wvdm_01_10  rs_disp_top_dpu_wvdm_01_10;
struct _rs_disp_top_dpu_wvdm_01_10 {
    unsigned int reg_01_dm_wr_col_step                      :32;
};
#define disp_top_dpu_wvdm_01_10(val) ((rs_disp_top_dpu_wvdm_01_10*)&(val))



#define DISP_TOP_DPU_WVDM_01_14                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_WVDM_01_14_struct                                   rs_disp_top_dpu_wvdm_01_14

typedef struct _rs_disp_top_dpu_wvdm_01_14  rs_disp_top_dpu_wvdm_01_14;
struct _rs_disp_top_dpu_wvdm_01_14 {
    unsigned int reg_01_dm_wr_line_step                     :32;
};
#define disp_top_dpu_wvdm_01_14(val) ((rs_disp_top_dpu_wvdm_01_14*)&(val))



#define DISP_TOP_DPU_WVDM_01_18                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x18)

#define DISP_TOP_DPU_WVDM_01_18_struct                                   rs_disp_top_dpu_wvdm_01_18

typedef struct _rs_disp_top_dpu_wvdm_01_18  rs_disp_top_dpu_wvdm_01_18;
struct _rs_disp_top_dpu_wvdm_01_18 {
    unsigned int reg_01_dm_wr_start_adr                     :32;
};
#define disp_top_dpu_wvdm_01_18(val) ((rs_disp_top_dpu_wvdm_01_18*)&(val))



#define DISP_TOP_DPU_WVDM_01_1C                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x1C)

#define DISP_TOP_DPU_WVDM_01_1C_struct                                   rs_disp_top_dpu_wvdm_01_1c

typedef struct _rs_disp_top_dpu_wvdm_01_1c  rs_disp_top_dpu_wvdm_01_1c;
struct _rs_disp_top_dpu_wvdm_01_1c {
    unsigned int reg_01_dm_wr_total_col_num                 :16;
    unsigned int reg_01_dm_wr_total_line_num                :16;
};
#define disp_top_dpu_wvdm_01_1c(val) ((rs_disp_top_dpu_wvdm_01_1c*)&(val))



#define DISP_TOP_DPU_WVDM_01_20                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x20)

#define DISP_TOP_DPU_WVDM_01_20_struct                                   rs_disp_top_dpu_wvdm_01_20

typedef struct _rs_disp_top_dpu_wvdm_01_20  rs_disp_top_dpu_wvdm_01_20;
struct _rs_disp_top_dpu_wvdm_01_20 {
    unsigned int reg_01_dm_wr_wdata_index                   :32;
};
#define disp_top_dpu_wvdm_01_20(val) ((rs_disp_top_dpu_wvdm_01_20*)&(val))



#define DISP_TOP_DPU_WVDM_01_24                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x24)

#define DISP_TOP_DPU_WVDM_01_24_struct                                   rs_disp_top_dpu_wvdm_01_24

typedef struct _rs_disp_top_dpu_wvdm_01_24  rs_disp_top_dpu_wvdm_01_24;
struct _rs_disp_top_dpu_wvdm_01_24 {
    unsigned int reg_01_dm_start_adr0                       :32;
};
#define disp_top_dpu_wvdm_01_24(val) ((rs_disp_top_dpu_wvdm_01_24*)&(val))



#define DISP_TOP_DPU_WVDM_01_28                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x28)

#define DISP_TOP_DPU_WVDM_01_28_struct                                   rs_disp_top_dpu_wvdm_01_28

typedef struct _rs_disp_top_dpu_wvdm_01_28  rs_disp_top_dpu_wvdm_01_28;
struct _rs_disp_top_dpu_wvdm_01_28 {
    unsigned int reg_01_dm_start_adr1                       :32;
};
#define disp_top_dpu_wvdm_01_28(val) ((rs_disp_top_dpu_wvdm_01_28*)&(val))



#define DISP_TOP_DPU_WVDM_01_2C                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x2C)

#define DISP_TOP_DPU_WVDM_01_2C_struct                                   rs_disp_top_dpu_wvdm_01_2c

typedef struct _rs_disp_top_dpu_wvdm_01_2c  rs_disp_top_dpu_wvdm_01_2c;
struct _rs_disp_top_dpu_wvdm_01_2c {
    unsigned int reg_01_dm_start_adr2                       :32;
};
#define disp_top_dpu_wvdm_01_2c(val) ((rs_disp_top_dpu_wvdm_01_2c*)&(val))



#define DISP_TOP_DPU_WVDM_01_30                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x30)

#define DISP_TOP_DPU_WVDM_01_30_struct                                   rs_disp_top_dpu_wvdm_01_30

typedef struct _rs_disp_top_dpu_wvdm_01_30  rs_disp_top_dpu_wvdm_01_30;
struct _rs_disp_top_dpu_wvdm_01_30 {
    unsigned int reg_01_dm_start_adr3                       :32;
};
#define disp_top_dpu_wvdm_01_30(val) ((rs_disp_top_dpu_wvdm_01_30*)&(val))



#define DISP_TOP_DPU_WVDM_01_34                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x34)

#define DISP_TOP_DPU_WVDM_01_34_struct                                   rs_disp_top_dpu_wvdm_01_34

typedef struct _rs_disp_top_dpu_wvdm_01_34  rs_disp_top_dpu_wvdm_01_34;
struct _rs_disp_top_dpu_wvdm_01_34 {
    unsigned int reg_01_dm_start_adr4                       :32;
};
#define disp_top_dpu_wvdm_01_34(val) ((rs_disp_top_dpu_wvdm_01_34*)&(val))



#define DISP_TOP_DPU_WVDM_01_38                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x38)

#define DISP_TOP_DPU_WVDM_01_38_struct                                   rs_disp_top_dpu_wvdm_01_38

typedef struct _rs_disp_top_dpu_wvdm_01_38  rs_disp_top_dpu_wvdm_01_38;
struct _rs_disp_top_dpu_wvdm_01_38 {
    unsigned int reg_01_dm_start_adr5                       :32;
};
#define disp_top_dpu_wvdm_01_38(val) ((rs_disp_top_dpu_wvdm_01_38*)&(val))



#define DISP_TOP_DPU_WVDM_01_3C                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x3C)

#define DISP_TOP_DPU_WVDM_01_3C_struct                                   rs_disp_top_dpu_wvdm_01_3c

typedef struct _rs_disp_top_dpu_wvdm_01_3c  rs_disp_top_dpu_wvdm_01_3c;
struct _rs_disp_top_dpu_wvdm_01_3c {
    unsigned int reg_01_dm_start_adr6                       :32;
};
#define disp_top_dpu_wvdm_01_3c(val) ((rs_disp_top_dpu_wvdm_01_3c*)&(val))



#define DISP_TOP_DPU_WVDM_01_40                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x40)

#define DISP_TOP_DPU_WVDM_01_40_struct                                   rs_disp_top_dpu_wvdm_01_40

typedef struct _rs_disp_top_dpu_wvdm_01_40  rs_disp_top_dpu_wvdm_01_40;
struct _rs_disp_top_dpu_wvdm_01_40 {
    unsigned int reg_01_dm_start_adr7                       :32;
};
#define disp_top_dpu_wvdm_01_40(val) ((rs_disp_top_dpu_wvdm_01_40*)&(val))



#define DISP_TOP_DPU_WVDM_01_44                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x44)

#define DISP_TOP_DPU_WVDM_01_44_struct                                   rs_disp_top_dpu_wvdm_01_44

typedef struct _rs_disp_top_dpu_wvdm_01_44  rs_disp_top_dpu_wvdm_01_44;
struct _rs_disp_top_dpu_wvdm_01_44 {
    unsigned int mem_reg_01                                 : 8;
    unsigned int reg_01_mem_ema                             :16;
    unsigned int reserved                                   : 8;
};
#define disp_top_dpu_wvdm_01_44(val) ((rs_disp_top_dpu_wvdm_01_44*)&(val))



#define DISP_TOP_DPU_WVDM_01_80                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x80)

#define DISP_TOP_DPU_WVDM_01_80_struct                                   rs_disp_top_dpu_wvdm_01_80

typedef struct _rs_disp_top_dpu_wvdm_01_80  rs_disp_top_dpu_wvdm_01_80;
struct _rs_disp_top_dpu_wvdm_01_80 {
    unsigned int reg_01_pq_dynamic_crc_enable               : 1;
    unsigned int reserved                                   :31;
};
#define disp_top_dpu_wvdm_01_80(val) ((rs_disp_top_dpu_wvdm_01_80*)&(val))



#define DISP_TOP_DPU_WVDM_01_84                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x84)

#define DISP_TOP_DPU_WVDM_01_84_struct                                   rs_disp_top_dpu_wvdm_01_84

typedef struct _rs_disp_top_dpu_wvdm_01_84  rs_disp_top_dpu_wvdm_01_84;
struct _rs_disp_top_dpu_wvdm_01_84 {
    unsigned int regr_01_dynamic_crc_out0                   :32;
};
#define disp_top_dpu_wvdm_01_84(val) ((rs_disp_top_dpu_wvdm_01_84*)&(val))



#define DISP_TOP_DPU_WVDM_01_88                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0x88)

#define DISP_TOP_DPU_WVDM_01_88_struct                                   rs_disp_top_dpu_wvdm_01_88

typedef struct _rs_disp_top_dpu_wvdm_01_88  rs_disp_top_dpu_wvdm_01_88;
struct _rs_disp_top_dpu_wvdm_01_88 {
    unsigned int regr_01_dynamic_crc_out1                   :32;
};
#define disp_top_dpu_wvdm_01_88(val) ((rs_disp_top_dpu_wvdm_01_88*)&(val))



#define DISP_TOP_DPU_WVDM_01_E4                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0xE4)

#define DISP_TOP_DPU_WVDM_01_E4_struct                                   rs_disp_top_dpu_wvdm_01_e4

typedef struct _rs_disp_top_dpu_wvdm_01_e4  rs_disp_top_dpu_wvdm_01_e4;
struct _rs_disp_top_dpu_wvdm_01_e4 {
    unsigned int reg_01_mem_ro                              : 4;
    unsigned int reserved                                   :28;
};
#define disp_top_dpu_wvdm_01_e4(val) ((rs_disp_top_dpu_wvdm_01_e4*)&(val))



#define DISP_TOP_DPU_WVDM_01_E8                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0xE8)

#define DISP_TOP_DPU_WVDM_01_E8_struct                                   rs_disp_top_dpu_wvdm_01_e8

typedef struct _rs_disp_top_dpu_wvdm_01_e8  rs_disp_top_dpu_wvdm_01_e8;
struct _rs_disp_top_dpu_wvdm_01_e8 {
    unsigned int regr_01_dm_wr_afifo_ovflow                 : 1;
    unsigned int regr_01_dm_wr_afifo_udflow                 : 1;
    unsigned int regr_01_dm_wr_block_num                    :16;
    unsigned int regr_01_dm_wr_buf_ovflow                   : 1;
    unsigned int regr_01_dm_wr_buf_udflow                   : 1;
    unsigned int regr_01_dm_wr_bus_idle                     : 1;
    unsigned int regr_01_dm_wr_cmd_sent                     : 4;
    unsigned int reserved                                   : 7;
};
#define disp_top_dpu_wvdm_01_e8(val) ((rs_disp_top_dpu_wvdm_01_e8*)&(val))



#define DISP_TOP_DPU_WVDM_01_EC                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0xEC)

#define DISP_TOP_DPU_WVDM_01_EC_struct                                   rs_disp_top_dpu_wvdm_01_ec

typedef struct _rs_disp_top_dpu_wvdm_01_ec  rs_disp_top_dpu_wvdm_01_ec;
struct _rs_disp_top_dpu_wvdm_01_ec {
    unsigned int regr_01_dm_wr_dat_need                     :12;
    unsigned int regr_01_dm_wr_line_num                     :16;
    unsigned int regr_01_dm_wr_st                           : 4;
};
#define disp_top_dpu_wvdm_01_ec(val) ((rs_disp_top_dpu_wvdm_01_ec*)&(val))



#define DISP_TOP_DPU_WVDM_01_F0                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0xF0)

#define DISP_TOP_DPU_WVDM_01_F0_struct                                   rs_disp_top_dpu_wvdm_01_f0

typedef struct _rs_disp_top_dpu_wvdm_01_f0  rs_disp_top_dpu_wvdm_01_f0;
struct _rs_disp_top_dpu_wvdm_01_f0 {
    unsigned int regr_01_dm_wr_wdata_0                      :32;
};
#define disp_top_dpu_wvdm_01_f0(val) ((rs_disp_top_dpu_wvdm_01_f0*)&(val))



#define DISP_TOP_DPU_WVDM_01_F4                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0xF4)

#define DISP_TOP_DPU_WVDM_01_F4_struct                                   rs_disp_top_dpu_wvdm_01_f4

typedef struct _rs_disp_top_dpu_wvdm_01_f4  rs_disp_top_dpu_wvdm_01_f4;
struct _rs_disp_top_dpu_wvdm_01_f4 {
    unsigned int regr_01_dm_wr_wdata_1                      :32;
};
#define disp_top_dpu_wvdm_01_f4(val) ((rs_disp_top_dpu_wvdm_01_f4*)&(val))



#define DISP_TOP_DPU_WVDM_01_F8                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0xF8)

#define DISP_TOP_DPU_WVDM_01_F8_struct                                   rs_disp_top_dpu_wvdm_01_f8

typedef struct _rs_disp_top_dpu_wvdm_01_f8  rs_disp_top_dpu_wvdm_01_f8;
struct _rs_disp_top_dpu_wvdm_01_f8 {
    unsigned int regr_01_dm_wr_wdata_2                      :32;
};
#define disp_top_dpu_wvdm_01_f8(val) ((rs_disp_top_dpu_wvdm_01_f8*)&(val))



#define DISP_TOP_DPU_WVDM_01_FC                                          (HV_DPU_WVDM_01_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_WVDM_01_FC_struct                                   rs_disp_top_dpu_wvdm_01_fc

typedef struct _rs_disp_top_dpu_wvdm_01_fc  rs_disp_top_dpu_wvdm_01_fc;
struct _rs_disp_top_dpu_wvdm_01_fc {
    unsigned int regr_01_dm_wr_wdata_3                      :32;
};
#define disp_top_dpu_wvdm_01_fc(val) ((rs_disp_top_dpu_wvdm_01_fc*)&(val))



#endif