#ifndef _HV_PAGE_HT7315_DPU_CA_DPC_01_H_
#define _HV_PAGE_HT7315_DPU_CA_DPC_01_H_

#ifndef HV_DPU_CA_DPC_01_BASE_ADDRESS
    #define HV_DPU_CA_DPC_01_BASE_ADDRESS                                         0x11022700
#endif


#define DISP_TOP_DPU_CA_DPC_01_00                                        (HV_DPU_CA_DPC_01_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_CA_DPC_01_00_struct                                 rs_disp_top_dpu_ca_dpc_01_00

typedef struct _rs_disp_top_dpu_ca_dpc_01_00  rs_disp_top_dpu_ca_dpc_01_00;
struct _rs_disp_top_dpu_ca_dpc_01_00 {
    unsigned int reg_01_en                                  : 1;
    unsigned int reg_01_en_no_latch                         : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_ca_dpc_01_00(val) ((rs_disp_top_dpu_ca_dpc_01_00*)&(val))



#define DISP_TOP_DPU_CA_DPC_01_04                                        (HV_DPU_CA_DPC_01_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_CA_DPC_01_04_struct                                 rs_disp_top_dpu_ca_dpc_01_04

typedef struct _rs_disp_top_dpu_ca_dpc_01_04  rs_disp_top_dpu_ca_dpc_01_04;
struct _rs_disp_top_dpu_ca_dpc_01_04 {
    unsigned int reg_01_ca_enc_clk_en                       : 1;
    unsigned int reg_01_ca_data_mode                        : 2;
    unsigned int reg_01_ca_data_bitwidth                    : 4;
    unsigned int reg_01_ca_enc_pack_work                    : 2;
    unsigned int reserved                                   :23;
};
#define disp_top_dpu_ca_dpc_01_04(val) ((rs_disp_top_dpu_ca_dpc_01_04*)&(val))



#define DISP_TOP_DPU_CA_DPC_01_20                                        (HV_DPU_CA_DPC_01_BASE_ADDRESS + 0x20)

#define DISP_TOP_DPU_CA_DPC_01_20_struct                                 rs_disp_top_dpu_ca_dpc_01_20

typedef struct _rs_disp_top_dpu_ca_dpc_01_20  rs_disp_top_dpu_ca_dpc_01_20;
struct _rs_disp_top_dpu_ca_dpc_01_20 {
    unsigned int reg_01_mem_reg                             : 8;
    unsigned int reg_01_mem_ema0                            :16;
    unsigned int reserved                                   : 8;
};
#define disp_top_dpu_ca_dpc_01_20(val) ((rs_disp_top_dpu_ca_dpc_01_20*)&(val))



#define DISP_TOP_DPU_CA_DPC_01_24                                        (HV_DPU_CA_DPC_01_BASE_ADDRESS + 0x24)

#define DISP_TOP_DPU_CA_DPC_01_24_struct                                 rs_disp_top_dpu_ca_dpc_01_24

typedef struct _rs_disp_top_dpu_ca_dpc_01_24  rs_disp_top_dpu_ca_dpc_01_24;
struct _rs_disp_top_dpu_ca_dpc_01_24 {
    unsigned int reg_01_mem_ema1                            :16;
    unsigned int reg_01_mem_ema2                            :16;
};
#define disp_top_dpu_ca_dpc_01_24(val) ((rs_disp_top_dpu_ca_dpc_01_24*)&(val))



#define DISP_TOP_DPU_CA_DPC_01_28                                        (HV_DPU_CA_DPC_01_BASE_ADDRESS + 0x28)

#define DISP_TOP_DPU_CA_DPC_01_28_struct                                 rs_disp_top_dpu_ca_dpc_01_28

typedef struct _rs_disp_top_dpu_ca_dpc_01_28  rs_disp_top_dpu_ca_dpc_01_28;
struct _rs_disp_top_dpu_ca_dpc_01_28 {
    unsigned int reg_01_mem_ema3                            :16;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_ca_dpc_01_28(val) ((rs_disp_top_dpu_ca_dpc_01_28*)&(val))



#define DISP_TOP_DPU_CA_DPC_01_FC                                        (HV_DPU_CA_DPC_01_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_CA_DPC_01_FC_struct                                 rs_disp_top_dpu_ca_dpc_01_fc

typedef struct _rs_disp_top_dpu_ca_dpc_01_fc  rs_disp_top_dpu_ca_dpc_01_fc;
struct _rs_disp_top_dpu_ca_dpc_01_fc {
    unsigned int regr_01_mem_ro0                            : 4;
    unsigned int regr_01_mem_ro1                            : 4;
    unsigned int regr_01_mem_ro2                            : 4;
    unsigned int regr_01_mem_ro3                            : 4;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_ca_dpc_01_fc(val) ((rs_disp_top_dpu_ca_dpc_01_fc*)&(val))



#endif