#ifndef _HV_PAGE_HT7315_DPU_CA_SYNC_01_H_
#define _HV_PAGE_HT7315_DPU_CA_SYNC_01_H_

#ifndef HV_DPU_CA_SYNC_01_BASE_ADDRESS
    #define HV_DPU_CA_SYNC_01_BASE_ADDRESS                                         0x11022D00
#endif


#define DISP_TOP_DPU_CA_SYNC_01_00                                       (HV_DPU_CA_SYNC_01_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_CA_SYNC_01_00_struct                                rs_disp_top_dpu_ca_sync_01_00

typedef struct _rs_disp_top_dpu_ca_sync_01_00  rs_disp_top_dpu_ca_sync_01_00;
struct _rs_disp_top_dpu_ca_sync_01_00 {
    unsigned int reg_01_en                                  : 1;
    unsigned int reg_01_en_no_latch                         : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_ca_sync_01_00(val) ((rs_disp_top_dpu_ca_sync_01_00*)&(val))



#define DISP_TOP_DPU_CA_SYNC_01_04                                       (HV_DPU_CA_SYNC_01_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_CA_SYNC_01_04_struct                                rs_disp_top_dpu_ca_sync_01_04

typedef struct _rs_disp_top_dpu_ca_sync_01_04  rs_disp_top_dpu_ca_sync_01_04;
struct _rs_disp_top_dpu_ca_sync_01_04 {
    unsigned int reg_01_ca_htotal                           :14;
    unsigned int reg_01_ca_vact                             :14;
    unsigned int reg_01_ca_sw_tbl_go                        : 1;
    unsigned int reg_01_ca_sw_tbl_go_en                     : 1;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_ca_sync_01_04(val) ((rs_disp_top_dpu_ca_sync_01_04*)&(val))



#define DISP_TOP_DPU_CA_SYNC_01_08                                       (HV_DPU_CA_SYNC_01_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_CA_SYNC_01_08_struct                                rs_disp_top_dpu_ca_sync_01_08

typedef struct _rs_disp_top_dpu_ca_sync_01_08  rs_disp_top_dpu_ca_sync_01_08;
struct _rs_disp_top_dpu_ca_sync_01_08 {
    unsigned int reg_01_ca_sync_frc_trig_vdly               :14;
    unsigned int reg_01_ca_sync_frc_trig_hdly               :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_sync_01_08(val) ((rs_disp_top_dpu_ca_sync_01_08*)&(val))



#define DISP_TOP_DPU_CA_SYNC_01_0C                                       (HV_DPU_CA_SYNC_01_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_CA_SYNC_01_0C_struct                                rs_disp_top_dpu_ca_sync_01_0c

typedef struct _rs_disp_top_dpu_ca_sync_01_0c  rs_disp_top_dpu_ca_sync_01_0c;
struct _rs_disp_top_dpu_ca_sync_01_0c {
    unsigned int reg_01_ca_sync_data_trig_vdly              :14;
    unsigned int reg_01_ca_sync_data_trig_hdly              :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_sync_01_0c(val) ((rs_disp_top_dpu_ca_sync_01_0c*)&(val))



#define DISP_TOP_DPU_CA_SYNC_01_10                                       (HV_DPU_CA_SYNC_01_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_CA_SYNC_01_10_struct                                rs_disp_top_dpu_ca_sync_01_10

typedef struct _rs_disp_top_dpu_ca_sync_01_10  rs_disp_top_dpu_ca_sync_01_10;
struct _rs_disp_top_dpu_ca_sync_01_10 {
    unsigned int reg_01_ca_sync_tbl_trig_vdly               :14;
    unsigned int reg_01_ca_sync_tbl_trig_hdly               :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_sync_01_10(val) ((rs_disp_top_dpu_ca_sync_01_10*)&(val))



#endif