#ifndef _HV_PAGE_HT7315_HDMI21_RX_CEC_01_H_
#define _HV_PAGE_HT7315_HDMI21_RX_CEC_01_H_

#ifndef HV_HDMI21_RX_CEC_01_BASE_ADDRESS
    #define HV_HDMI21_RX_CEC_01_BASE_ADDRESS                                         0x11008800
#endif


#define STANDBY_HDMI21_RX_CEC_01_00                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x00)

#define STANDBY_HDMI21_RX_CEC_01_00_struct                               rs_standby_hdmi21_rx_cec_01_00

typedef struct _rs_standby_hdmi21_rx_cec_01_00  rs_standby_hdmi21_rx_cec_01_00;
struct _rs_standby_hdmi21_rx_cec_01_00 {
    unsigned int reg_01_HPD                                 : 1;
    unsigned int reserved                                   :31;
};
#define standby_hdmi21_rx_cec_01_00(val) ((rs_standby_hdmi21_rx_cec_01_00*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_08                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x08)

#define STANDBY_HDMI21_RX_CEC_01_08_struct                               rs_standby_hdmi21_rx_cec_01_08

typedef struct _rs_standby_hdmi21_rx_cec_01_08  rs_standby_hdmi21_rx_cec_01_08;
struct _rs_standby_hdmi21_rx_cec_01_08 {
    unsigned int reg_01_HDMIRX_REVISION_ID                  :32;
};
#define standby_hdmi21_rx_cec_01_08(val) ((rs_standby_hdmi21_rx_cec_01_08*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_10                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x10)

#define STANDBY_HDMI21_RX_CEC_01_10_struct                               rs_standby_hdmi21_rx_cec_01_10

typedef struct _rs_standby_hdmi21_rx_cec_01_10  rs_standby_hdmi21_rx_cec_01_10;
struct _rs_standby_hdmi21_rx_cec_01_10 {
    unsigned int reg_01_SEND                                : 1;
    unsigned int reg_01_FRAME_TYP                           : 2;
    unsigned int reg_01_BC_NACK                             : 1;
    unsigned int reg_01_STANDBY                             : 1;
    unsigned int reserved                                   :27;
};
#define standby_hdmi21_rx_cec_01_10(val) ((rs_standby_hdmi21_rx_cec_01_10*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_14                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x14)

#define STANDBY_HDMI21_RX_CEC_01_14_struct                               rs_standby_hdmi21_rx_cec_01_14

typedef struct _rs_standby_hdmi21_rx_cec_01_14  rs_standby_hdmi21_rx_cec_01_14;
struct _rs_standby_hdmi21_rx_cec_01_14 {
    unsigned int reg_01_DONE_mask                           : 1;
    unsigned int reg_01_EOM_mask                            : 1;
    unsigned int reg_01_NACK_mask                           : 1;
    unsigned int reg_01_ARB_LOST_mask                       : 1;
    unsigned int reg_01_ERROR_INITIATOR_mask                : 1;
    unsigned int reg_01_ERROR_FLOW_mask                     : 1;
    unsigned int reg_01_WAKEUP_mask                         : 1;
    unsigned int reserved                                   :25;
};
#define standby_hdmi21_rx_cec_01_14(val) ((rs_standby_hdmi21_rx_cec_01_14*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_18                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x18)

#define STANDBY_HDMI21_RX_CEC_01_18_struct                               rs_standby_hdmi21_rx_cec_01_18

typedef struct _rs_standby_hdmi21_rx_cec_01_18  rs_standby_hdmi21_rx_cec_01_18;
struct _rs_standby_hdmi21_rx_cec_01_18 {
    unsigned int reg_01_CEC_ADDR_L                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_18(val) ((rs_standby_hdmi21_rx_cec_01_18*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_1C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x1C)

#define STANDBY_HDMI21_RX_CEC_01_1C_struct                               rs_standby_hdmi21_rx_cec_01_1c

typedef struct _rs_standby_hdmi21_rx_cec_01_1c  rs_standby_hdmi21_rx_cec_01_1c;
struct _rs_standby_hdmi21_rx_cec_01_1c {
    unsigned int reg_01_CEC_ADDR_H                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_1c(val) ((rs_standby_hdmi21_rx_cec_01_1c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_20                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x20)

#define STANDBY_HDMI21_RX_CEC_01_20_struct                               rs_standby_hdmi21_rx_cec_01_20

typedef struct _rs_standby_hdmi21_rx_cec_01_20  rs_standby_hdmi21_rx_cec_01_20;
struct _rs_standby_hdmi21_rx_cec_01_20 {
    unsigned int reg_01_CEC_TX_CNT                          : 5;
    unsigned int reserved                                   :27;
};
#define standby_hdmi21_rx_cec_01_20(val) ((rs_standby_hdmi21_rx_cec_01_20*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_24                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x24)

#define STANDBY_HDMI21_RX_CEC_01_24_struct                               rs_standby_hdmi21_rx_cec_01_24

typedef struct _rs_standby_hdmi21_rx_cec_01_24  rs_standby_hdmi21_rx_cec_01_24;
struct _rs_standby_hdmi21_rx_cec_01_24 {
    unsigned int regr_01_CEC_RX_CNT                         : 5;
    unsigned int regr_01_wtx_state                          : 3;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_24(val) ((rs_standby_hdmi21_rx_cec_01_24*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_28                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x28)

#define STANDBY_HDMI21_RX_CEC_01_28_struct                               rs_standby_hdmi21_rx_cec_01_28

typedef struct _rs_standby_hdmi21_rx_cec_01_28  rs_standby_hdmi21_rx_cec_01_28;
struct _rs_standby_hdmi21_rx_cec_01_28 {
    unsigned int reg_01_DATABYTE0                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_28(val) ((rs_standby_hdmi21_rx_cec_01_28*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_2C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x2C)

#define STANDBY_HDMI21_RX_CEC_01_2C_struct                               rs_standby_hdmi21_rx_cec_01_2c

typedef struct _rs_standby_hdmi21_rx_cec_01_2c  rs_standby_hdmi21_rx_cec_01_2c;
struct _rs_standby_hdmi21_rx_cec_01_2c {
    unsigned int reg_01_DATABYTE1                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_2c(val) ((rs_standby_hdmi21_rx_cec_01_2c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_30                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x30)

#define STANDBY_HDMI21_RX_CEC_01_30_struct                               rs_standby_hdmi21_rx_cec_01_30

typedef struct _rs_standby_hdmi21_rx_cec_01_30  rs_standby_hdmi21_rx_cec_01_30;
struct _rs_standby_hdmi21_rx_cec_01_30 {
    unsigned int reg_01_DATABYTE2                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_30(val) ((rs_standby_hdmi21_rx_cec_01_30*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_34                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x34)

#define STANDBY_HDMI21_RX_CEC_01_34_struct                               rs_standby_hdmi21_rx_cec_01_34

typedef struct _rs_standby_hdmi21_rx_cec_01_34  rs_standby_hdmi21_rx_cec_01_34;
struct _rs_standby_hdmi21_rx_cec_01_34 {
    unsigned int reg_01_DATABYTE3                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_34(val) ((rs_standby_hdmi21_rx_cec_01_34*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_38                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x38)

#define STANDBY_HDMI21_RX_CEC_01_38_struct                               rs_standby_hdmi21_rx_cec_01_38

typedef struct _rs_standby_hdmi21_rx_cec_01_38  rs_standby_hdmi21_rx_cec_01_38;
struct _rs_standby_hdmi21_rx_cec_01_38 {
    unsigned int reg_01_DATABYTE4                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_38(val) ((rs_standby_hdmi21_rx_cec_01_38*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_3C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x3C)

#define STANDBY_HDMI21_RX_CEC_01_3C_struct                               rs_standby_hdmi21_rx_cec_01_3c

typedef struct _rs_standby_hdmi21_rx_cec_01_3c  rs_standby_hdmi21_rx_cec_01_3c;
struct _rs_standby_hdmi21_rx_cec_01_3c {
    unsigned int reg_01_DATABYTE5                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_3c(val) ((rs_standby_hdmi21_rx_cec_01_3c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_40                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x40)

#define STANDBY_HDMI21_RX_CEC_01_40_struct                               rs_standby_hdmi21_rx_cec_01_40

typedef struct _rs_standby_hdmi21_rx_cec_01_40  rs_standby_hdmi21_rx_cec_01_40;
struct _rs_standby_hdmi21_rx_cec_01_40 {
    unsigned int reg_01_DATABYTE6                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_40(val) ((rs_standby_hdmi21_rx_cec_01_40*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_44                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x44)

#define STANDBY_HDMI21_RX_CEC_01_44_struct                               rs_standby_hdmi21_rx_cec_01_44

typedef struct _rs_standby_hdmi21_rx_cec_01_44  rs_standby_hdmi21_rx_cec_01_44;
struct _rs_standby_hdmi21_rx_cec_01_44 {
    unsigned int reg_01_DATABYTE7                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_44(val) ((rs_standby_hdmi21_rx_cec_01_44*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_48                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x48)

#define STANDBY_HDMI21_RX_CEC_01_48_struct                               rs_standby_hdmi21_rx_cec_01_48

typedef struct _rs_standby_hdmi21_rx_cec_01_48  rs_standby_hdmi21_rx_cec_01_48;
struct _rs_standby_hdmi21_rx_cec_01_48 {
    unsigned int reg_01_DATABYTE8                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_48(val) ((rs_standby_hdmi21_rx_cec_01_48*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_4C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x4C)

#define STANDBY_HDMI21_RX_CEC_01_4C_struct                               rs_standby_hdmi21_rx_cec_01_4c

typedef struct _rs_standby_hdmi21_rx_cec_01_4c  rs_standby_hdmi21_rx_cec_01_4c;
struct _rs_standby_hdmi21_rx_cec_01_4c {
    unsigned int reg_01_DATABYTE9                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_4c(val) ((rs_standby_hdmi21_rx_cec_01_4c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_50                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x50)

#define STANDBY_HDMI21_RX_CEC_01_50_struct                               rs_standby_hdmi21_rx_cec_01_50

typedef struct _rs_standby_hdmi21_rx_cec_01_50  rs_standby_hdmi21_rx_cec_01_50;
struct _rs_standby_hdmi21_rx_cec_01_50 {
    unsigned int reg_01_DATABYTE10                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_50(val) ((rs_standby_hdmi21_rx_cec_01_50*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_54                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x54)

#define STANDBY_HDMI21_RX_CEC_01_54_struct                               rs_standby_hdmi21_rx_cec_01_54

typedef struct _rs_standby_hdmi21_rx_cec_01_54  rs_standby_hdmi21_rx_cec_01_54;
struct _rs_standby_hdmi21_rx_cec_01_54 {
    unsigned int reg_01_DATABYTE11                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_54(val) ((rs_standby_hdmi21_rx_cec_01_54*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_58                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x58)

#define STANDBY_HDMI21_RX_CEC_01_58_struct                               rs_standby_hdmi21_rx_cec_01_58

typedef struct _rs_standby_hdmi21_rx_cec_01_58  rs_standby_hdmi21_rx_cec_01_58;
struct _rs_standby_hdmi21_rx_cec_01_58 {
    unsigned int reg_01_DATABYTE12                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_58(val) ((rs_standby_hdmi21_rx_cec_01_58*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_5C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x5C)

#define STANDBY_HDMI21_RX_CEC_01_5C_struct                               rs_standby_hdmi21_rx_cec_01_5c

typedef struct _rs_standby_hdmi21_rx_cec_01_5c  rs_standby_hdmi21_rx_cec_01_5c;
struct _rs_standby_hdmi21_rx_cec_01_5c {
    unsigned int reg_01_DATABYTE13                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_5c(val) ((rs_standby_hdmi21_rx_cec_01_5c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_60                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x60)

#define STANDBY_HDMI21_RX_CEC_01_60_struct                               rs_standby_hdmi21_rx_cec_01_60

typedef struct _rs_standby_hdmi21_rx_cec_01_60  rs_standby_hdmi21_rx_cec_01_60;
struct _rs_standby_hdmi21_rx_cec_01_60 {
    unsigned int reg_01_DATABYTE14                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_60(val) ((rs_standby_hdmi21_rx_cec_01_60*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_64                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x64)

#define STANDBY_HDMI21_RX_CEC_01_64_struct                               rs_standby_hdmi21_rx_cec_01_64

typedef struct _rs_standby_hdmi21_rx_cec_01_64  rs_standby_hdmi21_rx_cec_01_64;
struct _rs_standby_hdmi21_rx_cec_01_64 {
    unsigned int reg_01_DATABYTE15                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_64(val) ((rs_standby_hdmi21_rx_cec_01_64*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_68                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x68)

#define STANDBY_HDMI21_RX_CEC_01_68_struct                               rs_standby_hdmi21_rx_cec_01_68

typedef struct _rs_standby_hdmi21_rx_cec_01_68  rs_standby_hdmi21_rx_cec_01_68;
struct _rs_standby_hdmi21_rx_cec_01_68 {
    unsigned int regr_01_DATABYTE0                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_68(val) ((rs_standby_hdmi21_rx_cec_01_68*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_6C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x6C)

#define STANDBY_HDMI21_RX_CEC_01_6C_struct                               rs_standby_hdmi21_rx_cec_01_6c

typedef struct _rs_standby_hdmi21_rx_cec_01_6c  rs_standby_hdmi21_rx_cec_01_6c;
struct _rs_standby_hdmi21_rx_cec_01_6c {
    unsigned int regr_01_DATABYTE1                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_6c(val) ((rs_standby_hdmi21_rx_cec_01_6c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_70                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x70)

#define STANDBY_HDMI21_RX_CEC_01_70_struct                               rs_standby_hdmi21_rx_cec_01_70

typedef struct _rs_standby_hdmi21_rx_cec_01_70  rs_standby_hdmi21_rx_cec_01_70;
struct _rs_standby_hdmi21_rx_cec_01_70 {
    unsigned int regr_01_DATABYTE2                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_70(val) ((rs_standby_hdmi21_rx_cec_01_70*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_74                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x74)

#define STANDBY_HDMI21_RX_CEC_01_74_struct                               rs_standby_hdmi21_rx_cec_01_74

typedef struct _rs_standby_hdmi21_rx_cec_01_74  rs_standby_hdmi21_rx_cec_01_74;
struct _rs_standby_hdmi21_rx_cec_01_74 {
    unsigned int regr_01_DATABYTE3                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_74(val) ((rs_standby_hdmi21_rx_cec_01_74*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_78                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x78)

#define STANDBY_HDMI21_RX_CEC_01_78_struct                               rs_standby_hdmi21_rx_cec_01_78

typedef struct _rs_standby_hdmi21_rx_cec_01_78  rs_standby_hdmi21_rx_cec_01_78;
struct _rs_standby_hdmi21_rx_cec_01_78 {
    unsigned int regr_01_DATABYTE4                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_78(val) ((rs_standby_hdmi21_rx_cec_01_78*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_7C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x7C)

#define STANDBY_HDMI21_RX_CEC_01_7C_struct                               rs_standby_hdmi21_rx_cec_01_7c

typedef struct _rs_standby_hdmi21_rx_cec_01_7c  rs_standby_hdmi21_rx_cec_01_7c;
struct _rs_standby_hdmi21_rx_cec_01_7c {
    unsigned int regr_01_DATABYTE5                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_7c(val) ((rs_standby_hdmi21_rx_cec_01_7c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_80                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x80)

#define STANDBY_HDMI21_RX_CEC_01_80_struct                               rs_standby_hdmi21_rx_cec_01_80

typedef struct _rs_standby_hdmi21_rx_cec_01_80  rs_standby_hdmi21_rx_cec_01_80;
struct _rs_standby_hdmi21_rx_cec_01_80 {
    unsigned int regr_01_DATABYTE6                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_80(val) ((rs_standby_hdmi21_rx_cec_01_80*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_84                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x84)

#define STANDBY_HDMI21_RX_CEC_01_84_struct                               rs_standby_hdmi21_rx_cec_01_84

typedef struct _rs_standby_hdmi21_rx_cec_01_84  rs_standby_hdmi21_rx_cec_01_84;
struct _rs_standby_hdmi21_rx_cec_01_84 {
    unsigned int regr_01_DATABYTE7                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_84(val) ((rs_standby_hdmi21_rx_cec_01_84*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_88                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x88)

#define STANDBY_HDMI21_RX_CEC_01_88_struct                               rs_standby_hdmi21_rx_cec_01_88

typedef struct _rs_standby_hdmi21_rx_cec_01_88  rs_standby_hdmi21_rx_cec_01_88;
struct _rs_standby_hdmi21_rx_cec_01_88 {
    unsigned int regr_01_DATABYTE8                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_88(val) ((rs_standby_hdmi21_rx_cec_01_88*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_8C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x8C)

#define STANDBY_HDMI21_RX_CEC_01_8C_struct                               rs_standby_hdmi21_rx_cec_01_8c

typedef struct _rs_standby_hdmi21_rx_cec_01_8c  rs_standby_hdmi21_rx_cec_01_8c;
struct _rs_standby_hdmi21_rx_cec_01_8c {
    unsigned int regr_01_DATABYTE9                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_8c(val) ((rs_standby_hdmi21_rx_cec_01_8c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_90                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x90)

#define STANDBY_HDMI21_RX_CEC_01_90_struct                               rs_standby_hdmi21_rx_cec_01_90

typedef struct _rs_standby_hdmi21_rx_cec_01_90  rs_standby_hdmi21_rx_cec_01_90;
struct _rs_standby_hdmi21_rx_cec_01_90 {
    unsigned int regr_01_DATABYTE10                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_90(val) ((rs_standby_hdmi21_rx_cec_01_90*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_94                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x94)

#define STANDBY_HDMI21_RX_CEC_01_94_struct                               rs_standby_hdmi21_rx_cec_01_94

typedef struct _rs_standby_hdmi21_rx_cec_01_94  rs_standby_hdmi21_rx_cec_01_94;
struct _rs_standby_hdmi21_rx_cec_01_94 {
    unsigned int regr_01_DATABYTE11                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_94(val) ((rs_standby_hdmi21_rx_cec_01_94*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_98                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x98)

#define STANDBY_HDMI21_RX_CEC_01_98_struct                               rs_standby_hdmi21_rx_cec_01_98

typedef struct _rs_standby_hdmi21_rx_cec_01_98  rs_standby_hdmi21_rx_cec_01_98;
struct _rs_standby_hdmi21_rx_cec_01_98 {
    unsigned int regr_01_DATABYTE12                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_98(val) ((rs_standby_hdmi21_rx_cec_01_98*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_9C                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0x9C)

#define STANDBY_HDMI21_RX_CEC_01_9C_struct                               rs_standby_hdmi21_rx_cec_01_9c

typedef struct _rs_standby_hdmi21_rx_cec_01_9c  rs_standby_hdmi21_rx_cec_01_9c;
struct _rs_standby_hdmi21_rx_cec_01_9c {
    unsigned int regr_01_DATABYTE13                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_9c(val) ((rs_standby_hdmi21_rx_cec_01_9c*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_A0                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0xA0)

#define STANDBY_HDMI21_RX_CEC_01_A0_struct                               rs_standby_hdmi21_rx_cec_01_a0

typedef struct _rs_standby_hdmi21_rx_cec_01_a0  rs_standby_hdmi21_rx_cec_01_a0;
struct _rs_standby_hdmi21_rx_cec_01_a0 {
    unsigned int regr_01_DATABYTE14                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_01_a0(val) ((rs_standby_hdmi21_rx_cec_01_a0*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_A4                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0xA4)

#define STANDBY_HDMI21_RX_CEC_01_A4_struct                               rs_standby_hdmi21_rx_cec_01_a4

typedef struct _rs_standby_hdmi21_rx_cec_01_a4  rs_standby_hdmi21_rx_cec_01_a4;
struct _rs_standby_hdmi21_rx_cec_01_a4 {
    unsigned int regr_01_DATABYTE15                         : 8;
    unsigned int regr_01_wake_ctrl_status                   : 8;
    unsigned int reserved                                   :16;
};
#define standby_hdmi21_rx_cec_01_a4(val) ((rs_standby_hdmi21_rx_cec_01_a4*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_A8                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0xA8)

#define STANDBY_HDMI21_RX_CEC_01_A8_struct                               rs_standby_hdmi21_rx_cec_01_a8

typedef struct _rs_standby_hdmi21_rx_cec_01_a8  rs_standby_hdmi21_rx_cec_01_a8;
struct _rs_standby_hdmi21_rx_cec_01_a8 {
    unsigned int reg_01_LOCKED_BUFFER                       : 1;
    unsigned int reserved                                   :31;
};
#define standby_hdmi21_rx_cec_01_a8(val) ((rs_standby_hdmi21_rx_cec_01_a8*)&(val))



#define STANDBY_HDMI21_RX_CEC_01_AC                                      (HV_HDMI21_RX_CEC_01_BASE_ADDRESS + 0xAC)

#define STANDBY_HDMI21_RX_CEC_01_AC_struct                               rs_standby_hdmi21_rx_cec_01_ac

typedef struct _rs_standby_hdmi21_rx_cec_01_ac  rs_standby_hdmi21_rx_cec_01_ac;
struct _rs_standby_hdmi21_rx_cec_01_ac {
    unsigned int reg_01_OPCODE0X04EN                        : 1;
    unsigned int reg_01_OPCODE0X0DEN                        : 1;
    unsigned int reg_01_OPCODE0X41EN                        : 1;
    unsigned int reg_01_OPCODE0X42EN                        : 1;
    unsigned int reg_01_OPCODE0X44EN                        : 1;
    unsigned int reg_01_OPCODE0X70EN                        : 1;
    unsigned int reg_01_OPCODE0X82EN                        : 1;
    unsigned int reg_01_OPCODE0X86EN                        : 1;
    unsigned int reg_01_hd_rcv_clr                          : 1;
    unsigned int reg_01_hd_locked_clr                       : 1;
    unsigned int reserved                                   :22;
};
#define standby_hdmi21_rx_cec_01_ac(val) ((rs_standby_hdmi21_rx_cec_01_ac*)&(val))



#endif