#ifndef _HV_PAGE_HT7315_HDMI21_RX_EDDC_01_H_
#define _HV_PAGE_HT7315_HDMI21_RX_EDDC_01_H_

#ifndef HV_HDMI21_RX_EDDC_01_BASE_ADDRESS
    #define HV_HDMI21_RX_EDDC_01_BASE_ADDRESS                                         0x11008A00
#endif


#define STANDBY_HDMI21_RX_EDDC_01_00                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x00)

#define STANDBY_HDMI21_RX_EDDC_01_00_struct                              rs_standby_hdmi21_rx_eddc_01_00

typedef struct _rs_standby_hdmi21_rx_eddc_01_00  rs_standby_hdmi21_rx_eddc_01_00;
struct _rs_standby_hdmi21_rx_eddc_01_00 {
    unsigned int reg_01_slv_en_edid                         : 1;
    unsigned int reg_01_slv_en_segment                      : 1;
    unsigned int reg_01_slv_en_ddcci                        : 1;
    unsigned int reg_01_slv_en_usr0                         : 1;
    unsigned int reg_01_slv_en_usr1                         : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_edid_segment_clr                    : 1;
    unsigned int reg_01_edid_segment_clr_auto               : 1;
    unsigned int reserved_1                                 :14;
    unsigned int reg_01_slv_addr_edid                       : 8;
};
#define standby_hdmi21_rx_eddc_01_00(val) ((rs_standby_hdmi21_rx_eddc_01_00*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_04                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x04)

#define STANDBY_HDMI21_RX_EDDC_01_04_struct                              rs_standby_hdmi21_rx_eddc_01_04

typedef struct _rs_standby_hdmi21_rx_eddc_01_04  rs_standby_hdmi21_rx_eddc_01_04;
struct _rs_standby_hdmi21_rx_eddc_01_04 {
    unsigned int reg_01_slv_addr_segment                    : 8;
    unsigned int reg_01_slv_addr_ddcci                      : 8;
    unsigned int reg_01_slv_addr_usr0                       : 8;
    unsigned int reg_01_slv_addr_usr1                       : 8;
};
#define standby_hdmi21_rx_eddc_01_04(val) ((rs_standby_hdmi21_rx_eddc_01_04*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_08                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x08)

#define STANDBY_HDMI21_RX_EDDC_01_08_struct                              rs_standby_hdmi21_rx_eddc_01_08

typedef struct _rs_standby_hdmi21_rx_eddc_01_08  rs_standby_hdmi21_rx_eddc_01_08;
struct _rs_standby_hdmi21_rx_eddc_01_08 {
    unsigned int reg_01_ddc_i2c_slv_edid_hw_read_en         : 1;
    unsigned int reg_01_ddc_i2c_slv_edid_sw_read_en         : 1;
    unsigned int reg_01_ddc_i2c_slv_segment_sw_read_en      : 1;
    unsigned int reg_01_ddc_i2c_slv_ddcci_sw_read_en        : 1;
    unsigned int reg_01_ddc_i2c_slv_usr0_sw_read_en         : 1;
    unsigned int reg_01_ddc_i2c_slv_usr1_sw_read_en         : 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_01_ddc_i2c_slv_edid_sw_write_en        : 1;
    unsigned int reg_01_ddc_i2c_slv_segment_sw_write_en     : 1;
    unsigned int reg_01_ddc_i2c_slv_ddcci_sw_write_en       : 1;
    unsigned int reg_01_ddc_i2c_slv_usr0_sw_write_en        : 1;
    unsigned int reg_01_ddc_i2c_slv_usr1_sw_write_en        : 1;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_01_ddc_i2c_wr_valid_th                 : 5;
    unsigned int reserved_2                                 : 3;
    unsigned int reg_01_ddc_i2c_rd_req_th                   : 5;
    unsigned int reserved_3                                 : 3;
};
#define standby_hdmi21_rx_eddc_01_08(val) ((rs_standby_hdmi21_rx_eddc_01_08*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_0C                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x0C)

#define STANDBY_HDMI21_RX_EDDC_01_0C_struct                              rs_standby_hdmi21_rx_eddc_01_0c

typedef struct _rs_standby_hdmi21_rx_eddc_01_0c  rs_standby_hdmi21_rx_eddc_01_0c;
struct _rs_standby_hdmi21_rx_eddc_01_0c {
    unsigned int reg_01_ddc_i2cspikesuppr                   : 2;
    unsigned int reg_01_ddc_i2ctimouten                     : 1;
    unsigned int reg_01_ddc_i2ctimoutcnt                    :20;
    unsigned int reg_01_ddc_i2c_standby_only                : 1;
    unsigned int reserved                                   : 8;
};
#define standby_hdmi21_rx_eddc_01_0c(val) ((rs_standby_hdmi21_rx_eddc_01_0c*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_10                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x10)

#define STANDBY_HDMI21_RX_EDDC_01_10_struct                              rs_standby_hdmi21_rx_eddc_01_10

typedef struct _rs_standby_hdmi21_rx_eddc_01_10  rs_standby_hdmi21_rx_eddc_01_10;
struct _rs_standby_hdmi21_rx_eddc_01_10 {
    unsigned int reg_01_int_en_start_pulse                  : 1;
    unsigned int reg_01_int_en_restart_pulse                : 1;
    unsigned int reg_01_int_en_stop_pulse                   : 1;
    unsigned int reg_01_int_en_slv_addr_valid               : 1;
    unsigned int reg_01_int_en_wr_data_valid                : 1;
    unsigned int reg_01_int_en_rd_data_req                  : 1;
    unsigned int reg_01_int_en_edid_segment_update          : 1;
    unsigned int reserved                                   : 9;
    unsigned int reg_01_int_clr_start_pulse                 : 1;
    unsigned int reg_01_int_clr_restart_pulse               : 1;
    unsigned int reg_01_int_clr_stop_pulse                  : 1;
    unsigned int reg_01_int_clr_slv_addr_valid              : 1;
    unsigned int reg_01_int_clr_wr_data_valid               : 1;
    unsigned int reg_01_int_clr_rd_data_req                 : 1;
    unsigned int reg_01_int_clr_edid_segment_update         : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_01_ddc_i2c_wr_data_clr                 : 1;
    unsigned int reg_01_ddc_i2c_wr_cnt_clr                  : 1;
    unsigned int reg_01_ddc_i2c_wr_valid_clr                : 1;
    unsigned int reserved_2                                 : 1;
    unsigned int reg_01_ddc_i2c_rd_cnt_clr                  : 1;
    unsigned int reg_01_ddc_i2c_rd_req_clr                  : 1;
    unsigned int reserved_3                                 : 2;
};
#define standby_hdmi21_rx_eddc_01_10(val) ((rs_standby_hdmi21_rx_eddc_01_10*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_14                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x14)

#define STANDBY_HDMI21_RX_EDDC_01_14_struct                              rs_standby_hdmi21_rx_eddc_01_14

typedef struct _rs_standby_hdmi21_rx_eddc_01_14  rs_standby_hdmi21_rx_eddc_01_14;
struct _rs_standby_hdmi21_rx_eddc_01_14 {
    unsigned int reg_01_int_en_cec_arblst                   : 1;
    unsigned int reg_01_int_en_cec_eom                      : 1;
    unsigned int reg_01_int_en_cec_error_foll               : 1;
    unsigned int reg_01_int_en_cec_error_init               : 1;
    unsigned int reg_01_int_en_cec_int_done                 : 1;
    unsigned int reg_01_int_en_cec_nack                     : 1;
    unsigned int reg_01_int_en_cec_wakeupctrl               : 1;
    unsigned int reserved                                   : 9;
    unsigned int reg_01_int_clr_cec_arblst                  : 1;
    unsigned int reg_01_int_clr_cec_eom                     : 1;
    unsigned int reg_01_int_clr_cec_error_foll              : 1;
    unsigned int reg_01_int_clr_cec_error_init              : 1;
    unsigned int reg_01_int_clr_cec_int_done                : 1;
    unsigned int reg_01_int_clr_cec_nack                    : 1;
    unsigned int reg_01_int_clr_cec_wakeupctrl              : 1;
    unsigned int reserved_1                                 : 9;
};
#define standby_hdmi21_rx_eddc_01_14(val) ((rs_standby_hdmi21_rx_eddc_01_14*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_20                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x20)

#define STANDBY_HDMI21_RX_EDDC_01_20_struct                              rs_standby_hdmi21_rx_eddc_01_20

typedef struct _rs_standby_hdmi21_rx_eddc_01_20  rs_standby_hdmi21_rx_eddc_01_20;
struct _rs_standby_hdmi21_rx_eddc_01_20 {
    unsigned int reg_01_ddc_i2c_rd_data_00                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_01                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_02                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_03                  : 8;
};
#define standby_hdmi21_rx_eddc_01_20(val) ((rs_standby_hdmi21_rx_eddc_01_20*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_24                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x24)

#define STANDBY_HDMI21_RX_EDDC_01_24_struct                              rs_standby_hdmi21_rx_eddc_01_24

typedef struct _rs_standby_hdmi21_rx_eddc_01_24  rs_standby_hdmi21_rx_eddc_01_24;
struct _rs_standby_hdmi21_rx_eddc_01_24 {
    unsigned int reg_01_ddc_i2c_rd_data_04                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_05                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_06                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_07                  : 8;
};
#define standby_hdmi21_rx_eddc_01_24(val) ((rs_standby_hdmi21_rx_eddc_01_24*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_28                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x28)

#define STANDBY_HDMI21_RX_EDDC_01_28_struct                              rs_standby_hdmi21_rx_eddc_01_28

typedef struct _rs_standby_hdmi21_rx_eddc_01_28  rs_standby_hdmi21_rx_eddc_01_28;
struct _rs_standby_hdmi21_rx_eddc_01_28 {
    unsigned int reg_01_ddc_i2c_rd_data_08                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_09                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_10                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_11                  : 8;
};
#define standby_hdmi21_rx_eddc_01_28(val) ((rs_standby_hdmi21_rx_eddc_01_28*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_2C                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x2C)

#define STANDBY_HDMI21_RX_EDDC_01_2C_struct                              rs_standby_hdmi21_rx_eddc_01_2c

typedef struct _rs_standby_hdmi21_rx_eddc_01_2c  rs_standby_hdmi21_rx_eddc_01_2c;
struct _rs_standby_hdmi21_rx_eddc_01_2c {
    unsigned int reg_01_ddc_i2c_rd_data_12                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_13                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_14                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_15                  : 8;
};
#define standby_hdmi21_rx_eddc_01_2c(val) ((rs_standby_hdmi21_rx_eddc_01_2c*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_30                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x30)

#define STANDBY_HDMI21_RX_EDDC_01_30_struct                              rs_standby_hdmi21_rx_eddc_01_30

typedef struct _rs_standby_hdmi21_rx_eddc_01_30  rs_standby_hdmi21_rx_eddc_01_30;
struct _rs_standby_hdmi21_rx_eddc_01_30 {
    unsigned int reg_01_ddc_i2c_rd_data_16                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_17                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_18                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_19                  : 8;
};
#define standby_hdmi21_rx_eddc_01_30(val) ((rs_standby_hdmi21_rx_eddc_01_30*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_34                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x34)

#define STANDBY_HDMI21_RX_EDDC_01_34_struct                              rs_standby_hdmi21_rx_eddc_01_34

typedef struct _rs_standby_hdmi21_rx_eddc_01_34  rs_standby_hdmi21_rx_eddc_01_34;
struct _rs_standby_hdmi21_rx_eddc_01_34 {
    unsigned int reg_01_ddc_i2c_rd_data_20                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_21                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_22                  : 8;
    unsigned int reg_01_ddc_i2c_rd_data_23                  : 8;
};
#define standby_hdmi21_rx_eddc_01_34(val) ((rs_standby_hdmi21_rx_eddc_01_34*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_38                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x38)

#define STANDBY_HDMI21_RX_EDDC_01_38_struct                              rs_standby_hdmi21_rx_eddc_01_38

typedef struct _rs_standby_hdmi21_rx_eddc_01_38  rs_standby_hdmi21_rx_eddc_01_38;
struct _rs_standby_hdmi21_rx_eddc_01_38 {
    unsigned int reg_01_int_mon_sel                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_eddc_01_38(val) ((rs_standby_hdmi21_rx_eddc_01_38*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_3C                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x3C)

#define STANDBY_HDMI21_RX_EDDC_01_3C_struct                              rs_standby_hdmi21_rx_eddc_01_3c

typedef struct _rs_standby_hdmi21_rx_eddc_01_3c  rs_standby_hdmi21_rx_eddc_01_3c;
struct _rs_standby_hdmi21_rx_eddc_01_3c {
    unsigned int regr_01_int_mon_cnt                        : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_eddc_01_3c(val) ((rs_standby_hdmi21_rx_eddc_01_3c*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_40                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x40)

#define STANDBY_HDMI21_RX_EDDC_01_40_struct                              rs_standby_hdmi21_rx_eddc_01_40

typedef struct _rs_standby_hdmi21_rx_eddc_01_40  rs_standby_hdmi21_rx_eddc_01_40;
struct _rs_standby_hdmi21_rx_eddc_01_40 {
    unsigned int regr_01_int_pending_start_pulse            : 1;
    unsigned int regr_01_int_pending_restart_pulse          : 1;
    unsigned int regr_01_int_pending_stop_pulse             : 1;
    unsigned int regr_01_int_pending_slv_addr_valid         : 1;
    unsigned int regr_01_int_pending_wr_data_valid          : 1;
    unsigned int regr_01_int_pending_rd_data_req            : 1;
    unsigned int regr_01_int_pending_edid_segment_update    : 1;
    unsigned int regr_01_int_pending_cec_arblst             : 1;
    unsigned int regr_01_int_pending_cec_eom                : 1;
    unsigned int regr_01_int_pending_cec_error_foll         : 1;
    unsigned int regr_01_int_pending_cec_error_init         : 1;
    unsigned int regr_01_int_pending_cec_int_done           : 1;
    unsigned int regr_01_int_pending_cec_nack               : 1;
    unsigned int regr_01_int_pending_cec_wakeupctrl         : 1;
    unsigned int reserved                                   : 2;
    unsigned int regr_01_edid_segment                       : 8;
    unsigned int regr_01_ddc_rcurstate                      : 4;
    unsigned int reserved_1                                 : 4;
};
#define standby_hdmi21_rx_eddc_01_40(val) ((rs_standby_hdmi21_rx_eddc_01_40*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_44                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x44)

#define STANDBY_HDMI21_RX_EDDC_01_44_struct                              rs_standby_hdmi21_rx_eddc_01_44

typedef struct _rs_standby_hdmi21_rx_eddc_01_44  rs_standby_hdmi21_rx_eddc_01_44;
struct _rs_standby_hdmi21_rx_eddc_01_44 {
    unsigned int regr_01_sel_slv_edid                       : 1;
    unsigned int regr_01_sel_slv_segment                    : 1;
    unsigned int regr_01_sel_slv_ddcci                      : 1;
    unsigned int regr_01_sel_slv_usr0                       : 1;
    unsigned int regr_01_sel_slv_usr1                       : 1;
    unsigned int reserved                                   : 1;
    unsigned int regr_01_ddc_i2c_wr_valid                   : 1;
    unsigned int regr_01_ddc_i2c_rd_req                     : 1;
    unsigned int regr_01_ddc_i2c_wr_valid_num               : 5;
    unsigned int regr_01_ddc_i2c_wr_cnt                     : 5;
    unsigned int regr_01_ddc_i2c_rd_cnt                     : 5;
    unsigned int reserved_1                                 : 1;
    unsigned int regr_01_ddc_i2c_slave_addr                 : 8;
};
#define standby_hdmi21_rx_eddc_01_44(val) ((rs_standby_hdmi21_rx_eddc_01_44*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_48                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x48)

#define STANDBY_HDMI21_RX_EDDC_01_48_struct                              rs_standby_hdmi21_rx_eddc_01_48

typedef struct _rs_standby_hdmi21_rx_eddc_01_48  rs_standby_hdmi21_rx_eddc_01_48;
struct _rs_standby_hdmi21_rx_eddc_01_48 {
    unsigned int regr_01_ddc_i2c_wr_data_00                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_01                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_02                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_03                 : 8;
};
#define standby_hdmi21_rx_eddc_01_48(val) ((rs_standby_hdmi21_rx_eddc_01_48*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_4C                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x4C)

#define STANDBY_HDMI21_RX_EDDC_01_4C_struct                              rs_standby_hdmi21_rx_eddc_01_4c

typedef struct _rs_standby_hdmi21_rx_eddc_01_4c  rs_standby_hdmi21_rx_eddc_01_4c;
struct _rs_standby_hdmi21_rx_eddc_01_4c {
    unsigned int regr_01_ddc_i2c_wr_data_04                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_05                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_06                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_07                 : 8;
};
#define standby_hdmi21_rx_eddc_01_4c(val) ((rs_standby_hdmi21_rx_eddc_01_4c*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_50                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x50)

#define STANDBY_HDMI21_RX_EDDC_01_50_struct                              rs_standby_hdmi21_rx_eddc_01_50

typedef struct _rs_standby_hdmi21_rx_eddc_01_50  rs_standby_hdmi21_rx_eddc_01_50;
struct _rs_standby_hdmi21_rx_eddc_01_50 {
    unsigned int regr_01_ddc_i2c_wr_data_08                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_09                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_10                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_11                 : 8;
};
#define standby_hdmi21_rx_eddc_01_50(val) ((rs_standby_hdmi21_rx_eddc_01_50*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_54                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x54)

#define STANDBY_HDMI21_RX_EDDC_01_54_struct                              rs_standby_hdmi21_rx_eddc_01_54

typedef struct _rs_standby_hdmi21_rx_eddc_01_54  rs_standby_hdmi21_rx_eddc_01_54;
struct _rs_standby_hdmi21_rx_eddc_01_54 {
    unsigned int regr_01_ddc_i2c_wr_data_12                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_13                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_14                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_15                 : 8;
};
#define standby_hdmi21_rx_eddc_01_54(val) ((rs_standby_hdmi21_rx_eddc_01_54*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_58                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x58)

#define STANDBY_HDMI21_RX_EDDC_01_58_struct                              rs_standby_hdmi21_rx_eddc_01_58

typedef struct _rs_standby_hdmi21_rx_eddc_01_58  rs_standby_hdmi21_rx_eddc_01_58;
struct _rs_standby_hdmi21_rx_eddc_01_58 {
    unsigned int regr_01_ddc_i2c_wr_data_16                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_17                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_18                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_19                 : 8;
};
#define standby_hdmi21_rx_eddc_01_58(val) ((rs_standby_hdmi21_rx_eddc_01_58*)&(val))



#define STANDBY_HDMI21_RX_EDDC_01_5C                                     (HV_HDMI21_RX_EDDC_01_BASE_ADDRESS + 0x5C)

#define STANDBY_HDMI21_RX_EDDC_01_5C_struct                              rs_standby_hdmi21_rx_eddc_01_5c

typedef struct _rs_standby_hdmi21_rx_eddc_01_5c  rs_standby_hdmi21_rx_eddc_01_5c;
struct _rs_standby_hdmi21_rx_eddc_01_5c {
    unsigned int regr_01_ddc_i2c_wr_data_20                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_21                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_22                 : 8;
    unsigned int regr_01_ddc_i2c_wr_data_23                 : 8;
};
#define standby_hdmi21_rx_eddc_01_5c(val) ((rs_standby_hdmi21_rx_eddc_01_5c*)&(val))



#endif