/**
 * @file hv_cal_Physical.c
 * @brief PHY 模块提供的驱动层
 * @details 该模块接口提供给driver处理INPUTPORT相关接口。
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20220822
 * @copyright Copyright(c),2022-8, Hiview Software. All rights reserved.
 * @par History: 
 * <table>
 * <tr><th>作者                         <th>日期              <th>描述
 * <tr><td>HiView SoC Software Team   <td>20220822        <td>Create and first Version.
 * </table>
**/
#include "hv_comm_Assert.h"
#include "hv_comm_Define.h"
#include "hv_vos_Comm.h"
#include "hv_chip_Config.h"

#include "hv_cal_Physical.h"

#define HV_INPUTPORT_HSRX_STEP          0x0200

static void Hv_Cal_Phy_TempSensorSetting(void)
{
    HV_W32_FIELD(SYS_SH06_TOP_50, reg_temps_sel_clk, 3);
    HV_W32_FIELD(SYS_SH06_TOP_50, reg_temps_sel_mode_ts, 1);
    HV_W32_FIELD(SYS_SH06_TOP_50, reg_temps_cali_ts, 0);
    HV_W32_FIELD(SYS_SH06_TOP_50, reg_temps_dctest_en, 0);

    return;
}

static VOID Hv_Cal_Phy_RxEqInit(UCHAR8 ucPortId)
{
    UINT32 uiAddrOffset = ucPortId * 0x100;

    /* EQ lowe power mode */
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_28, uiAddrOffset, reg_00_rx_phy_eq_bnd_sel, 0x3);

    /* EQ settings */
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_6C, uiAddrOffset, reg_00_rx_phy_eq_00, 0x00);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_6C, uiAddrOffset, reg_00_rx_phy_eq_01, 0x18);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_70, uiAddrOffset, reg_00_rx_phy_eq_02, 0x28);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_70, uiAddrOffset, reg_00_rx_phy_eq_03, 0x38);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_74, uiAddrOffset, reg_00_rx_phy_eq_04, 0x78);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_74, uiAddrOffset, reg_00_rx_phy_eq_05, 0xA8);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_78, uiAddrOffset, reg_00_rx_phy_eq_06, 0xF0);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_78, uiAddrOffset, reg_00_rx_phy_eq_07, 0x138);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_7C, uiAddrOffset, reg_00_rx_phy_eq_08, 0x178);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_7C, uiAddrOffset, reg_00_rx_phy_eq_09, 0x1B8);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_80, uiAddrOffset, reg_00_rx_phy_eq_10, 0x1F8);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_80, uiAddrOffset, reg_00_rx_phy_eq_11, 0x1FA);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_84, uiAddrOffset, reg_00_rx_phy_eq_12, 0x1FC);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_84, uiAddrOffset, reg_00_rx_phy_eq_13, 0x1FD);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_88, uiAddrOffset, reg_00_rx_phy_eq_14, 0x1FE);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_88, uiAddrOffset, reg_00_rx_phy_eq_15, 0x1FF);

    /* DC gain in manual mode */
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane0_rz, 0x0);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane1_rz, 0x0);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane2_rz, 0x0);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane3_rz, 0x0);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane0_cz, 0x7);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane1_cz, 0x7);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane2_cz, 0x7);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_1C, uiAddrOffset, reg_00_rx_phy_eq_lane3_cz, 0x7);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_20, uiAddrOffset, reg_00_rx_phy_eq_lane0_xcap, 0x3);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_20, uiAddrOffset, reg_00_rx_phy_eq_lane1_xcap, 0x2);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_20, uiAddrOffset, reg_00_rx_phy_eq_lane2_xcap, 0x3);
    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_20, uiAddrOffset, reg_00_rx_phy_eq_lane3_xcap, 0x3);

    return;
}

static VOID Hv_Cal_Phy_RxMacInit(UCHAR8 ucPortId)
{
    UINT32 uiAddrOffset = ucPortId * 0x100;

    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_04, uiAddrOffset, reg_00_rx_phy_sw_rst_n, 0x1);


    HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_14, uiAddrOffset, reg_00_rx_phy_cr_done_cnt, 0xAA);

    /* phy cr-done lock cycle */
    if (ucPortId < 2)
    {
        /* 4 lane power up */
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_10, uiAddrOffset, reg_00_rx_phy_lane_pd, 0x0);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_10, uiAddrOffset, reg_00_rx_phy_lane_rstn, 0xF);

        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_04, uiAddrOffset, reg_00_rx_phy_vos_sw_en, 0x1);

        /* valid for DP no link training */
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_14, uiAddrOffset, reg_00_rx_phy_ckref_sel, 0x1);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_10, uiAddrOffset, reg_00_rx_phy_lane_ckref_sel, 0xF);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_24, uiAddrOffset, reg_00_rx_phy_fast_lock_rlpf, 0x6);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_24, uiAddrOffset, reg_00_rx_phy_fine_lock_rlpf, 0x3);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_24, uiAddrOffset, reg_00_rx_phy_cdr_rlpf, 0x8);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_24, uiAddrOffset, reg_00_rx_phy_fast_lock_icp, 0x4);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_24, uiAddrOffset, reg_00_rx_phy_fine_lock_icp, 0xC);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_24, uiAddrOffset, reg_00_rx_phy_cdr_icp, 0x3);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_28, uiAddrOffset, reg_00_rx_phy_cr_prediv, 0x1);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_28, uiAddrOffset, reg_00_rx_phy_cr_fbdiv, 0x32);

        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_4C, uiAddrOffset, reg_00_rx_phy_eq_lp_mode_bw0, 0x0);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_4C, uiAddrOffset, reg_00_rx_phy_eq_lp_mode_bw1, 0x0);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_4C, uiAddrOffset, reg_00_rx_phy_cr_prediv_bw0, 0x1);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_4C, uiAddrOffset, reg_00_rx_phy_cr_prediv_bw1, 0x1);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_50, uiAddrOffset, reg_00_rx_phy_cr_prediv_bw2, 0x1);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_50, uiAddrOffset, reg_00_rx_phy_cr_prediv_bw3, 0x1);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_50, uiAddrOffset, reg_00_rx_phy_cr_fbdiv_bw0, 0xF);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_50, uiAddrOffset, reg_00_rx_phy_cr_fbdiv_bw1, 0x19);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_54, uiAddrOffset, reg_00_rx_phy_cr_fbdiv_bw2, 0x32);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_54, uiAddrOffset, reg_00_rx_phy_cr_fbdiv_bw3, 0x4B);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_5C, uiAddrOffset, reg_00_rx_phy_bw_set_en, 0x0);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_5C, uiAddrOffset, reg_00_rx_phy_bw_set, 0xF);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_5C, uiAddrOffset, reg_00_rx_phy_lane_vld_bw_en, 0x0);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_60, uiAddrOffset, reg_00_rx_phy_eq_bnd_sel_bw0, 0x1);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_60, uiAddrOffset, reg_00_rx_phy_eq_bnd_sel_bw1, 0x2);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_60, uiAddrOffset, reg_00_rx_phy_eq_bnd_sel_bw2, 0x3);
        HV_W32_FIELD_EX(RX_RX_PHY_T22_NOLINK_00_60, uiAddrOffset, reg_00_rx_phy_eq_bnd_sel_bw3, 0x3);


        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_00, uiAddrOffset, reg_00_rx_phy_ctl_enable, 0x1);

        /* auto eq wait for permit signal */
        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_0C, uiAddrOffset, reg_00_rx_phy_ctl_hold_mode, 0x3);

        /* 20us reset time for DP, count by OSC */
        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_10, uiAddrOffset, reg_00_rx_phy_ctl_rst_timer, 540);

        /* disable DFE */
        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_14, uiAddrOffset, reg_00_rx_phy_dfe_en, 0x7);
        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_14, uiAddrOffset, reg_00_rx_phy_dfe_win_sel, 0x2);

        /* disable 01 pattern check for auto eq */
        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_14, uiAddrOffset, reg_00_rx_phy_dfe_rand_det, 0x0);

        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_14, uiAddrOffset, reg_00_rx_phy_ctl_trn_mode_sw_en, 0x3);

        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_10, uiAddrOffset, reg_00_rx_phy_ctl_eq_init_val, 0x4);

        /* EQ loop */
        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_14, uiAddrOffset, reg_00_rx_phy_eq_loop_cnt, 0x5);

        /* disable VOS */
        HV_W32_FIELD_EX(RX_RX_PHY_DFE_00_64, uiAddrOffset, reg_00_rx_phy_vos_enable, 0x0);
    }

    return;
}

static VOID Hv_Cal_Phy_RxDpllInit(UCHAR8 ucPortId)
{
    UINT32 uiAddrOffset = ucPortId * 0x100;

    /* RxDpll enable */
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_en, 0x1);

    /* compensation DAC enable */
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_dac_en, 0x1);

    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_rstn, 0x1);

    /* fractional mode */
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_div_mode, 0x1);

    /* phase error estimation rounding mode */
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_rnd_mode, 0x0);

    /* test mode will ignore rx phy, close it */
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_test_mode, 0x0);

    /* vco freerun */
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_free_run, 0x0);

    /* pll overflow auto reset enable */
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_overflow_rst_en, 0x0);

    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_lock_force, 0x0);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_lock_cnt_sel, 0x0);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_lock_wd_sel, 0x1);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_ana_test_sel, 0x0);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_00, uiAddrOffset, reg_00_rx_dpll_dummy, 0x0);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_dly_ctrl, 0x4);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_icp_bias_tune, 0x4);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_icp_ctrl1, 0x8);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_icp_ctrl2, 0x1);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_ib5u_sel, 0x0);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_lpf_ctrl, 0x4);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_stb_en, 0x0);
    HV_W32_FIELD_EX(RX_RX_DPLL_00_04, uiAddrOffset, reg_00_rx_dpll_kvco_ctrl, 0x26);

    return;
}

Status Hv_Cal_Phy_HsrxInit(UCHAR8 ucPortIndex)
{
    HV_W32_FIELD(RX_SH08_TOP_RX_CTRL_4, reg_aging_in_in_sel, 2);

    return HV_SUCCESS;
}

Status Hv_Cal_Phy_DigitalInit( )
{
    Hv_Cal_Phy_RxMacInit(0);
    Hv_Cal_Phy_RxMacInit(1);
    Hv_Cal_Phy_RxMacInit(2);
    Hv_Cal_Phy_RxMacInit(3);
    /* PHY 各自控制，该处只打开Comm */
    HV_W32_MASK(SYS_SH06_TOP_08, BIT_31, BIT_31);

    /* HDMI0 0x0F00 & HDMI1 0xF000 & DP0 0x000F & DP1 0x00F0 reg_rx_phy_lane_vld */
    HV_W32(RX_RX_PHY_00, 0xFFFF);

    /* valid for DP no link training */
    HV_W32(RX_RX_PHY_04, 0x5);

    /* Not Use Now */
    //HV_W32_FIELD(RX_RX_PHY_0C, reg_phy_sw_rstn, 0x1F);

    /* HDMI0 0x0F00 & HDMI1 0xF000 & DP0 0x000F & DP1 0x00F0 reg_lane_clk_1x_inv_en 
     * 这个不需要打开： 保持默认值即可
     */
    //HV_W32(RX_RX_PHY_10, 0xFFFF);

    /* HDMI0 0x0F00 & HDMI1 0xF000 & DP0 0x000F & DP1 0x00F0 reg_lane_clk_1x_eq_en */
    HV_W32(RX_RX_PHY_14, 0xFFFF);

    /* HDMI0 0x0F00 & HDMI1 0xF000 & DP0 0x000F & DP1 0x00F0 reg_lane_clk_1x_phy_en */
    HV_W32(RX_RX_PHY_18, 0xFFFF);

    /* HDMI1: BIT6 BIT7 
       HDMI0: BIT4 BIT5
       DP1  : BIT2 BIT3
       DP0  : BIT0 BIT1
       All Used Lane0 
       reg_lane_clk_mac_src_sel*/

    /* DP lane0 refer to phy lane3 , HDMI Refer to Lane1*/
    HV_W32(RX_RX_PHY_1C, 0x5F);

    //HV_W32_FIELD(RX_RX_PHY_20, reg_lane_clk_1x_mac_en, 0xF);
    /* MAC 配置对应的 DIV */
    //HV_W32_MASK(RX_RX_PHY_20, 0xC0000, 0xC0000);
    HV_W32(RX_RX_PHY_20, 0xC000F);

    /* 关闭 mon */
    HV_W32_FIELD(RX_RX_PHY_28, reg_lane_clk_1x_mon_en, 0x0);

    /* 配置 FRL TMDS   CLOCK reg_lane_clk_1x_mac_frl_en */
    /* 配置 TMDS TMDS   CLOCK reg_lane_clk_1x_mac_tmds_en */
    HV_W32_MASK(RX_RX_PHY_28, 0x0FF00000, 0x0FF00000);

    /* Audio Lane clk select 这个需要Audio 根据 Lan 配置 */
    //HV_W32_FIELD(RX_RX_PHY_2C, reg_lane_clk_src_aud_sel, 0x32);

    /*
     * rxdpll rstn sel
     * [0] rxdpll0 rstn
     * [1] rxdpll1 rstn
     */
    HV_W32_FIELD(RX_RX_PHY_30, reg_rx_dpll_sw_rstn, 0x3);

    /*
     * rxdpll clk mac sel
     * [3:0] rxdpll clk for dp0
     *         4'd0 rxdpll0 pg0_0
     *         4'd1 rxdpll1 pg0_0
     *         4'd2 pix_glb_clk
     *         4'd3 pix_glb_clk
     * [7:4] rxdpll clk for dp1
     *         ?
     * [11:8] rxdpll clk for hdmi21_0
     *         ?
     * [15:12] rxdpll clk for hdmi21_1
     * [19:16] rxdpll clk for mute0
     * [23:20] rxdpll clk for mute1
     */
    /* Mute0 ==> Main 时钟采用RxDpll0 */
    //HV_W32_MASK(RX_RX_PHY_34, 0xF0000, 0);
    /* Mute1 ==> Sub 时钟采用RxDpll1 */
    //HV_W32_MASK(RX_RX_PHY_34, 0xF00000, 100000);
    HV_W32_MASK(RX_RX_PHY_34, 0xFF0000, 0x100000);

    /*
     * rxdpll clk mac en
     * [0] rxdpll clk for vbo
     * [1] rxdpll clk for dp0 
     * [2] rxdpll clk for dp0 mst
     * [3] rxdpll clk for hdmi21
     * [4] rxdpll clk for mute0
     * [5] rxdpll clk for mute1
     */
    HV_W32_FIELD(RX_RX_PHY_38, reg_rx_dpll_clk_mac_en, 0x0030);

    /* HDMI0 USED the BIT 8 - 11 */
    /* HDMI1 USED the BIT 12 - 15 */
    HV_W32_MASK(RX_RX_PHY_40, 0xFF00, 0x2200);

    /* reg_rx_mac_clkdet_en, USED FOR DP0 Lane0 to detect */
    HV_W32(RX_RX_PHY_50, 0x0);

    /* USED FOR DP0 Lane0 to detect */
    HV_W32_FIELD(RX_RX_PHY_54, reg_rx_mac_clkdet_lane_sel, 0x0);

    /*
     * ip0 clk src sel ==> Main
     * ip clk src sel
     * [3:0]
     * 8'd0 : pg0_0_rxdpll[0]
     * 8'd1 : pg0_0_rxdpll[1]
     * 8'd2 : pg2_rxdpll[0]
     * 8'd3 : pg2_rxdpll[1]
     * [7:4]
     * 8'd0 : pg0_0_rxdpll[0]
     * 8'd1 : pg0_0_rxdpll[1]
     * 8'd2 : pg2_rxdpll[0]
     * 8'd3 : pg2_rxdpll[1]
     */
    HV_W32_FIELD(RX_RX_PHY_54, reg_rx_dpll_ip_clk_sel, 0x10);

    /*
     * Main Video Path IP Clock Source Selection:
     * 2'h0: clock comes from dpll_pg1_src
     * 2'h1: clock comes from rxdpll_pg2_src
     */
    HV_W32_FIELD(SYS_SH06_TOP_10, reg_ip0_clk_src_sel, 0x1);

    /*
     * Sub Video Path IP Clock Source Selection:
     * 2'h0: clock comes from dpll_pg2_src
     * 2'h1: clock comes from rxdpll_pg2_src
     */
    HV_W32_FIELD(SYS_SH06_TOP_10, reg_ip1_clk_src_sel, 0x1);

    /*TMP ADD for Bring Up*/
    HV_W32_FIELD(STANDBY_STANDBY_MCU_REG_74, reg_rx_short_clk_en, 0x1);
    HV_W32_FIELD(STANDBY_STANDBY_MCU_REG_RX_SHORT0, reg_rxphy_short_det_enb, 0xF);

    return HV_SUCCESS;
}

Status Hv_Cal_Phy_SetRxMapping(UCHAR8 ucPortIndex, UINT32 uiValue)
{
    HV_W32_FIELD_EX(RX_HSRX_CH_00_30, ucPortIndex * HV_INPUTPORT_HSRX_STEP, reg_00_hsrx_mapping_en, 1);
    HV_W32_FIELD_EX(RX_HSRX_CH_00_30, ucPortIndex * HV_INPUTPORT_HSRX_STEP, reg_00_hsrx_mapping_pair, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_Phy_DisableRxMapping(UCHAR8 ucPortIndex)
{
    HV_W32_FIELD_EX(RX_HSRX_CH_00_30, ucPortIndex * HV_INPUTPORT_HSRX_STEP, reg_00_hsrx_mapping_en, 0);
    return HV_SUCCESS;
}

static void Hv_Cal_Phy_PDAnaInit(VOID)
{
    HV_W32_FIELD(SYS_SH06_TOP_5C,       reg_ptcdpll_ssc_en, 0);
    HV_W32_FIELD(RX_HSRX_TOP_08,        reg_hsrx_ce_oscclk_window_length, 0x3E8);
    HV_W32_FIELD(RX_HSRX_TOP_08,        reg_hsrx_ce_prc_det_mode,         0x0  );
    HV_W32_FIELD(RX_HSRX_TOP_08,        reg_hsrx_ce_prc_det_clkgate_en,   0x1  );
    HV_W32_FIELD(SYS_SH06_TOP_14,       reg_b3_oscclk_window_length,      0x3E8);
    HV_W32_FIELD(SYS_SH06_TOP_14,       reg_b3_prc_det_mode,              0x0  );
    HV_W32_FIELD(SYS_SH06_TOP_14,       reg_b3_prc_det_clkgate_en,        0x1  );
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_00,  reg_blk2_pd_oscclk_window_length, 0x3E8);
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_00,  reg_blk2_pd_prc_det_mode,         0x0  );
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_00,  reg_blk2_pd_prc_det_clkgate_en,   0x1  );
}

static void Hv_Cal_Phy_TypecAnaInit(VOID)
{
#ifdef CONFIG_USER_TYPE_C_ON
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_adc_brige,     0x8);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_adcib_comp,    0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_adcpulse_mode, 0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_atestsel,      0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_ccrxvrefh,     0x7F);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_ccrxvrefl,     0x21);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_divsel,        0x2);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_pd,            0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_radc_en,       0x1);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_00, reg_00_ccphy_rd_deten,      0x1);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_keep,          0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_rdtrim,        0x8);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_rdtrim_sel,    0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_rptrim,        0x20);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_slpsel,        0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_v1p1_adj,      0x4);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_v1p02_adj,     0x3);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_04, reg_00_ccphy_v1p8_adj,      0x4);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_10, reg_00_din_rdtrim_start,    0x1);
    Hv_Vos_MSleep(1);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_00_10, reg_00_din_rdtrim_start,    0x0);
#if (HV_BOARD_CONFIG_MAX_TYPEC_PORT_NUM > 1)
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_adc_brige,     0x8);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_adcib_comp,    0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_adcpulse_mode, 0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_atestsel,      0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_ccrxvrefh,     0x7F);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_ccrxvrefl,     0x21);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_divsel,        0x2);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_pd,            0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_radc_en,       0x1);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_00, reg_01_ccphy_rd_deten,      0x1);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_keep,          0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_rdtrim,        0x8);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_rdtrim_sel,    0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_rptrim,        0x20);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_slpsel,        0x0);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_v1p1_adj,      0x4);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_v1p02_adj,     0x3);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_04, reg_01_ccphy_v1p8_adj,      0x4);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_10, reg_01_din_rdtrim_start,    0x1);
    Hv_Vos_MSleep(1);
    HV_W32_FIELD(STANDBY_USB_TYPEC_PHY_TOP_01_10, reg_01_din_rdtrim_start,    0x0);
#endif
#endif
}

/*
* 该setting仅仅针对DP/VBO点屏用的setting
* reg_txphy_*_swing_main_*   用于调swing
* reg_txphy_*_swing_tapi_*   用于调pre-emphasis
* reg_txphy_*_vcm_adj        用于调共模
* reg_txphy_*_res_diff       用于调输出阻抗
*/
static VOID Hv_Cal_Phy_ComboTxPhyAnaInit(VOID)
{
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_pd, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_p2s_rstn, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_drv_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_mlvds_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_pmos_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_nmos_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_ckvco_test_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_ck_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_res_diff, 10);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_res_pg, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_clk_rd_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_pll_right_left_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_04, reg_txphy_00_dctest_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_20, reg_txphy_00_pre_emphasis_en, 15);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_24, reg_txphy_00_swing_main_0, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_24, reg_txphy_00_swing_main_1, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_24, reg_txphy_00_swing_main_2, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_24, reg_txphy_00_swing_main_3, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapi_0, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapi_1, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapi_2, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapi_3, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapii_0, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapii_1, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapii_2, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_swing_tapii_3, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_tapi_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_28, reg_txphy_00_tapii_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_dcd_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_dcd_adj, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_pn_sw, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_duty_up, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_duty_down, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_ib_source_adj, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_vcm_adj, 11);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_clklink_a_inv, 0);
    //HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_pulldn_b, 15);  /*正常流程下需要在RX、TX数字电路正常工作后才能设F*/
    HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_dcd_fb_sel, 1);

    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_pd, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_p2s_rstn, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_drv_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_mlvds_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_pmos_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_nmos_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_ckvco_test_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_ck_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_res_diff, 10);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_res_pg, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_clk_rd_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_pll_right_left_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_44, reg_txphy_01_dctest_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_60, reg_txphy_01_pre_emphasis_en, 15);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_64, reg_txphy_01_swing_main_0, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_64, reg_txphy_01_swing_main_1, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_64, reg_txphy_01_swing_main_2, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_64, reg_txphy_01_swing_main_3, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapi_0, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapi_1, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapi_2, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapi_3, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapii_0, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapii_1, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapii_2, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_swing_tapii_3, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_tapi_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_68, reg_txphy_01_tapii_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_dcd_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_dcd_adj, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_pn_sw, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_duty_up, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_duty_down, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_ib_source_adj, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_vcm_adj, 11);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_clklink_a_inv, 0);
    //HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_pulldn_b, 15);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_dcd_fb_sel, 1);

    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_pd, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_p2s_rstn, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_drv_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_mlvds_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_pmos_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_nmos_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_ckvco_test_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_ck_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_res_diff, 10);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_res_pg, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_clk_rd_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_pll_right_left_sel, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_84, reg_txphy_02_dctest_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A0, reg_txphy_02_pre_emphasis_en, 15);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A4, reg_txphy_02_swing_main_0, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A4, reg_txphy_02_swing_main_1, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A4, reg_txphy_02_swing_main_2, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A4, reg_txphy_02_swing_main_3, 20);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapi_0, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapi_1, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapi_2, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapi_3, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapii_0, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapii_1, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapii_2, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_swing_tapii_3, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_tapi_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_A8, reg_txphy_02_tapii_inv, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_dcd_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_dcd_adj, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_pn_sw, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_duty_up, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_duty_down, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_ib_source_adj, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_vcm_adj, 11);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_clklink_a_inv, 0);
    //HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_pulldn_b, 15);
    HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_dcd_fb_sel, 1);
    return;
}

static VOID Hv_Cal_Phy_ComboTxPhyPllAnaInit(VOID)
{
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_en, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_stb_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_rstn, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_div_mode, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_ib5u_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_test_mode, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_free_run, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_overflow_rst_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_lock_force, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_lock_cnt_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_lock_wd_sel, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_ana_test_sel, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_dummy, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_rnd_mode, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_dac_en, 0);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_dly_ctrl, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_icp_bias_tune, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_icp_ctrl1, 8);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_icp_ctrl2, 1);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_lpf_ctrl, 4);
    HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_kvco_ctrl, 38);
    return;
}

static VOID Hv_Cal_Ptcd_PtcdPllAnaInit(VOID)
{
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_en, 1);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_stb_en, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_rstn, 1);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_div_mode, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_ib5u_sel, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_test_mode, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_free_run, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_overflow_rst_en, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_lock_force, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_lock_cnt_sel, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_lock_wd_sel, 1);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_ana_test_sel, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_dummy, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_rnd_mode, 0);
    HV_W32_FIELD(SYS_SH06_TOP_3C, reg_ptcdpll_dac_en, 0);
    HV_W32_FIELD(SYS_SH06_TOP_40, reg_ptcdpll_dly_ctrl, 4);
    HV_W32_FIELD(SYS_SH06_TOP_40, reg_ptcdpll_icp_bias_tune, 4);
    HV_W32_FIELD(SYS_SH06_TOP_40, reg_ptcdpll_icp_ctrl1, 8);
    HV_W32_FIELD(SYS_SH06_TOP_40, reg_ptcdpll_icp_ctrl2, 1);
    HV_W32_FIELD(SYS_SH06_TOP_40, reg_ptcdpll_lpf_ctrl, 4);
    HV_W32_FIELD(SYS_SH06_TOP_40, reg_ptcdpll_kvco_ctrl, 38);

    /*ldg top*/
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_04, mem_ema1, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_04, mem_ema2, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_08, mem_ema3, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_08, mem_ema4, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_0C, mem_ema5, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_0C, mem_ema6, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_10, mem_ema7, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_10, mem_ema8, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_14, mem_ema9, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_14, mem_ema10, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_18, mem_ema11, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_18, mem_ema12, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_1C, mem_ema13, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_1C, mem_ema14, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_20, mem_ema15, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_20, mem_ema16, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_24, mem_ema17, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_24, mem_ema18, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_28, mem_ema19, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_28, mem_ema20, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_2C, mem_ema21, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_2C, mem_ema22, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_30, mem_ema23, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_30, mem_ema24, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_34, mem_ema25, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_34, mem_ema26, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_38, mem_ema27, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_38, mem_ema28, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_3C, mem_ema29, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_3C, mem_ema30, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_40, mem_ema31, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_40, mem_ema32, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_44, mem_ema33, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_44, mem_ema34, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_48, mem_ema35, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_48, mem_ema36, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_4C, mem_ema37, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_4C, mem_ema38, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_50, mem_ema39, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_50, mem_ema40, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_54, mem_ema41, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_54, mem_ema42, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_58, mem_ema43, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_58, mem_ema44, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_5C, mem_ema45, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_5C, mem_ema46, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_60, mem_ema47, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_60, mem_ema48, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_64, mem_ema49, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_64, mem_ema50, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_68, mem_ema51, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_68, mem_ema52, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_6C, mem_ema53, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_6C, mem_ema54, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_70, mem_ema55, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_70, mem_ema56, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_74, mem_ema57, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_74, mem_ema58, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_78, mem_ema59, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_78, mem_ema60, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_7C, mem_ema61, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_7C, mem_ema62, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_80, mem_ema63, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_80, mem_ema64, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_84, mem_ema65, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_84, mem_ema66, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_88, mem_ema67, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_88, mem_ema68, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_8C, mem_ema69, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_8C, mem_ema70, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_90, mem_ema71, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_90, mem_ema72, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_94, mem_ema73, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_94, mem_ema74, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_98, mem_ema75, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_98, mem_ema76, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_9C, mem_ema77, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_9C, mem_ema78, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_A0, mem_ema79, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_A0, mem_ema80, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_A4, mem_ema81, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_A4, mem_ema82, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_A8, mem_ema83, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_A8, mem_ema84, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_AC, mem_ema85, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_AC, mem_ema86, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_B0, mem_ema87, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_B0, mem_ema88, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_B4, mem_ema89, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_B4, mem_ema90, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_B8, mem_ema91, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_B8, mem_ema92, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_BC, mem_ema93, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_BC, mem_ema94, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_C0, mem_ema95, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_C0, mem_ema96, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_C4, mem_ema97, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_C4, mem_ema98, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_C8, mem_ema99, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_C8, mem_ema100, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_CC, mem_ema101, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_CC, mem_ema102, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_D0, mem_ema103, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_D0, mem_ema104, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_D4, mem_ema105, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_D4, mem_ema106, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_D8, mem_ema107, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_D8, mem_ema108, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_DC, mem_ema109, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_DC, mem_ema110, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_E0, mem_ema111, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_E0, mem_ema112, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_E4, mem_ema113, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_E4, mem_ema114, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_E8, mem_ema115, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_E8, mem_ema116, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_EC, mem_ema117, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_EC, mem_ema118, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_F0, mem_ema119, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_F0, mem_ema120, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_F4, mem_ema121, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_F4, mem_ema122, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_F8, mem_ema123, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_F8, mem_ema124, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_FC, mem_ema125, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE1_FC, mem_ema126, 19);

    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_00, mem_ema127, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_00, mem_ema128, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_04, mem_ema129, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_04, mem_ema130, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_08, mem_ema131, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_08, mem_ema132, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_0C, mem_ema133, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_0C, mem_ema134, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_10, mem_ema135, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_10, mem_ema136, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_14, mem_ema137, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_14, mem_ema138, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_18, mem_ema139, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_18, mem_ema140, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_1C, mem_ema141, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_1C, mem_ema142, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_20, mem_ema143, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_20, mem_ema144, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_24, mem_ema145, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_24, mem_ema146, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_28, mem_ema147, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_28, mem_ema148, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_2C, mem_ema149, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_2C, mem_ema150, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_30, mem_ema151, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_30, mem_ema152, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_34, mem_ema153, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_34, mem_ema154, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_38, mem_ema155, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_38, mem_ema156, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_3C, mem_ema157, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_3C, mem_ema158, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_40, mem_ema159, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_40, mem_ema160, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_44, mem_ema161, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_44, mem_ema162, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_48, mem_ema163, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_48, mem_ema164, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_4C, mem_ema165, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_4C, mem_ema166, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_50, mem_ema167, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_50, mem_ema168, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_54, mem_ema169, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_54, mem_ema170, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_58, mem_ema171, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_58, mem_ema172, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_5C, mem_ema173, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_5C, mem_ema174, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_60, mem_ema175, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_60, mem_ema176, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_64, mem_ema177, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_64, mem_ema178, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_68, mem_ema179, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_68, mem_ema180, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_6C, mem_ema181, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_6C, mem_ema182, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_70, mem_ema183, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_70, mem_ema184, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_74, mem_ema185, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_74, mem_ema186, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_78, mem_ema187, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_78, mem_ema188, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_7C, mem_ema189, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_7C, mem_ema190, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_80, mem_ema191, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_80, mem_ema192, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_84, mem_ema193, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_84, mem_ema194, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_88, mem_ema195, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_88, mem_ema196, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_8C, mem_ema197, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_8C, mem_ema198, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_90, mem_ema199, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_90, mem_ema200, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_94, mem_ema201, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_94, mem_ema202, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_98, mem_ema203, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_98, mem_ema204, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_9C, mem_ema205, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_9C, mem_ema206, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_A0, mem_ema207, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_A0, mem_ema208, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_A4, mem_ema209, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_A4, mem_ema210, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_A8, mem_ema211, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_A8, mem_ema212, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_AC, mem_ema213, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_AC, mem_ema214, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_B0, mem_ema215, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_B0, mem_ema216, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_B4, mem_ema217, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_B4, mem_ema218, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_B8, mem_ema219, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_B8, mem_ema220, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_BC, mem_ema221, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_BC, mem_ema222, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_C0, mem_ema223, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_C0, mem_ema224, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_C4, mem_ema225, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_C4, mem_ema226, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_C8, mem_ema227, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_C8, mem_ema228, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_CC, mem_ema229, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_CC, mem_ema230, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_D0, mem_ema231, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_D0, mem_ema232, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_D4, mem_ema233, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_D4, mem_ema234, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_D8, mem_ema235, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_D8, mem_ema236, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_DC, mem_ema237, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_DC, mem_ema238, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_E0, mem_ema239, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_E0, mem_ema240, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_E4, mem_ema241, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_E4, mem_ema242, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_E8, mem_ema243, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_E8, mem_ema244, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_EC, mem_ema245, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_EC, mem_ema246, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_F0, mem_ema247, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_F0, mem_ema248, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_F4, mem_ema249, 19);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_MEM_PAGE2_F4, mem_ema250, 19);

    /*main cap c02*/
    HV_W32_FIELD(DISP_TOP_C420_422_00_38, reg_00_mem_ema0, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_38, reg_00_mem_ema1, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_3C, reg_00_mem_ema2, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_3C, reg_00_mem_ema3, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_40, reg_00_mem_ema4, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_40, reg_00_mem_ema5, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_44, reg_00_mem_ema6, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_44, reg_00_mem_ema7, 19);
    HV_W32_FIELD(DISP_TOP_C420_422_00_48, reg_00_mem_ema8, 19);

    /*hsrx*/
    HV_W32_FIELD(RX_HSRX_TOP_70, reg_hsrx_mem_ema_0, 19);
    HV_W32_FIELD(RX_HSRX_TOP_74, reg_hsrx_mem_ema_1, 19);
    HV_W32_FIELD(RX_HSRX_TOP_78, reg_hsrx_mem_ema_2, 19);
    HV_W32_FIELD(RX_HSRX_TOP_7C, reg_hsrx_mem_ema_3, 19);
    HV_W32_FIELD(RX_HSRX_TOP_80, reg_hsrx_mem_ema_4, 19);
    HV_W32_FIELD(RX_HSRX_TOP_84, reg_hsrx_mem_ema_5, 19);
    HV_W32_FIELD(RX_HSRX_TOP_88, reg_hsrx_mem_ema_6, 19);
    HV_W32_FIELD(RX_HSRX_TOP_8C, reg_hsrx_mem_ema_7, 19);
    HV_W32_FIELD(RX_HSRX_TOP_90, reg_hsrx_mem_ema_8, 19);
    HV_W32_FIELD(RX_HSRX_TOP_94, reg_hsrx_mem_ema_9, 19);
    HV_W32_FIELD(RX_HSRX_TOP_98, reg_hsrx_mem_ema_10, 19);
    HV_W32_FIELD(RX_HSRX_TOP_9C, reg_hsrx_mem_ema_11, 19);
    HV_W32_FIELD(RX_HSRX_TOP_A0, reg_hsrx_mem_ema_12, 19);
    HV_W32_FIELD(RX_HSRX_TOP_A4, reg_hsrx_mem_ema_13, 19);
    HV_W32_FIELD(RX_HSRX_TOP_A8, reg_hsrx_mem_ema_14, 19);
    HV_W32_FIELD(RX_HSRX_TOP_AC, reg_hsrx_mem_ema_15, 19);
    return;
}

static VOID Hv_Cal_EdpTx_EdpTxAuxAnaInit(VOID)
{
    HV_W32_FIELD(TX_HSTX_TOP_10, reg_edptx_ana_aux_0_pwd, 0);
    HV_W32_FIELD(TX_HSTX_TOP_10, reg_edptx_ana_aux_0_pn_swap, 0);
    HV_W32_FIELD(TX_HSTX_TOP_10, reg_edptx_ana_aux_0_hys, 2);
    HV_W32_FIELD(TX_HSTX_TOP_10, reg_edptx_ana_aux_0_drv, 8);
    HV_W32_FIELD(TX_HSTX_TOP_10, reg_edptx_ana_aux_0_res, 10);
    HV_W32_FIELD(TX_HSTX_TOP_14, reg_edptx_ana_aux_1_pwd, 0);
    HV_W32_FIELD(TX_HSTX_TOP_14, reg_edptx_ana_aux_1_pn_swap, 0);
    HV_W32_FIELD(TX_HSTX_TOP_14, reg_edptx_ana_aux_1_hys, 2);
    HV_W32_FIELD(TX_HSTX_TOP_14, reg_edptx_ana_aux_1_drv, 8);
    HV_W32_FIELD(TX_HSTX_TOP_14, reg_edptx_ana_aux_1_res, 10);
    return;
}


Status Hv_Cal_Phy_AnalogInit(VOID)
{
    Hv_Cal_Phy_PDAnaInit();
    Hv_Cal_Phy_TypecAnaInit();
    Hv_Cal_Phy_TempSensorSetting();
    Hv_Cal_Phy_ComboTxPhyAnaInit();
    Hv_Cal_Phy_ComboTxPhyPllAnaInit();
    Hv_Cal_Ptcd_PtcdPllAnaInit();
    Hv_Cal_EdpTx_EdpTxAuxAnaInit();

    Hv_Cal_Phy_RxEqInit(0);
    Hv_Cal_Phy_RxEqInit(1);
    //Hv_Cal_Phy_RxEqInit(2);
    //Hv_Cal_Phy_RxEqInit(3);
    Hv_Cal_Phy_RxDpllInit(0);
    Hv_Cal_Phy_RxDpllInit(1);

    return HV_SUCCESS;
}
