#ifndef _HV_PAGE_HT7315_EPI_TOP0_H_
#define _HV_PAGE_HT7315_EPI_TOP0_H_

#ifndef HV_EPI_TOP0_BASE_ADDRESS
    #define HV_EPI_TOP0_BASE_ADDRESS                                         0x1105E700
#endif


#define TX_EPI_TOP0_EPI_TOP0_SET_0                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x00)

#define TX_EPI_TOP0_EPI_TOP0_SET_0_struct                                rs_tx_epi_top0_epi_top0_set_0

typedef struct _rs_tx_epi_top0_epi_top0_set_0  rs_tx_epi_top0_epi_top0_set_0;
struct _rs_tx_epi_top0_epi_top0_set_0 {
    unsigned int reg_epi_enable                             : 1;
    unsigned int reg_epi_bit_mode                           : 2;
    unsigned int reg_epi_ctr_start_en                       : 1;
    unsigned int reg_epi_ctr3_en                            : 1;
    unsigned int reg_epi_data_start_en                      : 1;
    unsigned int reg_epi_ctr_start_sel                      : 1;
    unsigned int reg_epi_ctr_soe_sel                        : 1;
    unsigned int reg_epi_fw_lock                            : 1;
    unsigned int reg_epi_lock_fw_mode                       : 1;
    unsigned int reg_epi_data_debug                         : 1;
    unsigned int reg_epi_den_end_mode                       : 1;
    unsigned int reg_epi_scramble_en                        : 1;
    unsigned int reg_epi_scramble_mode                      : 1;
    unsigned int reg_epi_prbs_half_mode                     : 1;
    unsigned int reg_epi_back_dummy_value                   : 2;
    unsigned int reg_epi_front_ck_value                     : 2;
    unsigned int reg_epi_pair_mode                          : 1;
    unsigned int reg_epi_lock_pol                           : 1;
    unsigned int reg_epi_soe_line_patt_en                   : 1;
    unsigned int reg_epi_clk_edge_scramble_en               : 1;
    unsigned int reg_epi_hbp_scramble_en                    : 1;
    unsigned int reg_epi_hbp_lfsr_shift_mode                : 1;
    unsigned int reg_epi_v2dot_shift_en                     : 1;
    unsigned int reg_epi_scramble_abnormal_rst              : 1;
    unsigned int reg_epi_soe_sdic_mode                      : 1;
    unsigned int reg_epi_scr_en_mode                        : 1;
    unsigned int reg_epi_scr_rst_mode                       : 2;
    unsigned int reserved                                   : 1;
};
#define tx_epi_top0_epi_top0_set_0(val) ((rs_tx_epi_top0_epi_top0_set_0*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_1                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x04)

#define TX_EPI_TOP0_EPI_TOP0_SET_1_struct                                rs_tx_epi_top0_epi_top0_set_1

typedef struct _rs_tx_epi_top0_epi_top0_set_1  rs_tx_epi_top0_epi_top0_set_1;
struct _rs_tx_epi_top0_epi_top0_set_1 {
    unsigned int reg_epi_phase1_preamble_num                :16;
    unsigned int reg_epi_phase2_preamble_num                :16;
};
#define tx_epi_top0_epi_top0_set_1(val) ((rs_tx_epi_top0_epi_top0_set_1*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_2                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x08)

#define TX_EPI_TOP0_EPI_TOP0_SET_2_struct                                rs_tx_epi_top0_epi_top0_set_2

typedef struct _rs_tx_epi_top0_epi_top0_set_2  rs_tx_epi_top0_epi_top0_set_2;
struct _rs_tx_epi_top0_epi_top0_set_2 {
    unsigned int reg_epi_data_start                         : 6;
    unsigned int reg_epi_data_start_cfg                     :24;
    unsigned int reg_epi_ctr1_28s_en                        : 1;
    unsigned int reg_epi_ctr2_28s_en                        : 1;
};
#define tx_epi_top0_epi_top0_set_2(val) ((rs_tx_epi_top0_epi_top0_set_2*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_3                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x0C)

#define TX_EPI_TOP0_EPI_TOP0_SET_3_struct                                rs_tx_epi_top0_epi_top0_set_3

typedef struct _rs_tx_epi_top0_epi_top0_set_3  rs_tx_epi_top0_epi_top0_set_3;
struct _rs_tx_epi_top0_epi_top0_set_3 {
    unsigned int reg_epi_pre_de_num                         : 8;
    unsigned int reg_epi_post_de_num                        : 8;
    unsigned int reg_epi_ctr_start                          : 6;
    unsigned int reg_epi_a10_rd_mode                        : 2;
    unsigned int reserved                                   : 8;
};
#define tx_epi_top0_epi_top0_set_3(val) ((rs_tx_epi_top0_epi_top0_set_3*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_4                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x10)

#define TX_EPI_TOP0_EPI_TOP0_SET_4_struct                                rs_tx_epi_top0_epi_top0_set_4

typedef struct _rs_tx_epi_top0_epi_top0_set_4  rs_tx_epi_top0_epi_top0_set_4;
struct _rs_tx_epi_top0_epi_top0_set_4 {
    unsigned int reg_epi_dv_scr_en_sta                      :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_epi_dv_scr_en_end                      :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_epi_top0_epi_top0_set_4(val) ((rs_tx_epi_top0_epi_top0_set_4*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_5                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x14)

#define TX_EPI_TOP0_EPI_TOP0_SET_5_struct                                rs_tx_epi_top0_epi_top0_set_5

typedef struct _rs_tx_epi_top0_epi_top0_set_5  rs_tx_epi_top0_epi_top0_set_5;
struct _rs_tx_epi_top0_epi_top0_set_5 {
    unsigned int reg_epi_dv_scr_rst_pos                     :15;
    unsigned int reg_epi_monitor_soe_ctrl                   : 2;
    unsigned int reserved                                   :15;
};
#define tx_epi_top0_epi_top0_set_5(val) ((rs_tx_epi_top0_epi_top0_set_5*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_6                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x18)

#define TX_EPI_TOP0_EPI_TOP0_SET_6_struct                                rs_tx_epi_top0_epi_top0_set_6

typedef struct _rs_tx_epi_top0_epi_top0_set_6  rs_tx_epi_top0_epi_top0_set_6;
struct _rs_tx_epi_top0_epi_top0_set_6 {
    unsigned int reg_epi_ctr_start_c11_sel                  : 2;
    unsigned int reg_epi_ctr_start_c12_sel                  : 2;
    unsigned int reg_epi_ctr_start_c13_sel                  : 2;
    unsigned int reg_epi_ctr_start_c14_sel                  : 2;
    unsigned int reserved                                   :24;
};
#define tx_epi_top0_epi_top0_set_6(val) ((rs_tx_epi_top0_epi_top0_set_6*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_7                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x1C)

#define TX_EPI_TOP0_EPI_TOP0_SET_7_struct                                rs_tx_epi_top0_epi_top0_set_7

typedef struct _rs_tx_epi_top0_epi_top0_set_7  rs_tx_epi_top0_epi_top0_set_7;
struct _rs_tx_epi_top0_epi_top0_set_7 {
    unsigned int reg_epi_ctr1_c2_sel                        : 2;
    unsigned int reg_epi_ctr1_c3_sel                        : 2;
    unsigned int reg_epi_ctr1_c4_sel                        : 2;
    unsigned int reg_epi_ctr1_c5_sel                        : 2;
    unsigned int reg_epi_ctr1_c6_sel                        : 2;
    unsigned int reg_epi_ctr1_c7_sel                        : 2;
    unsigned int reg_epi_ctr1_c8_sel                        : 2;
    unsigned int reg_epi_ctr1_c9_sel                        : 2;
    unsigned int reg_epi_ctr1_c10_sel                       : 2;
    unsigned int reg_epi_ctr1_c11_sel                       : 2;
    unsigned int reg_epi_ctr1_c12_sel                       : 2;
    unsigned int reg_epi_ctr1_c13_sel                       : 2;
    unsigned int reg_epi_ctr1_c14_sel                       : 2;
    unsigned int reg_epi_ctr1_c15_sel                       : 2;
    unsigned int reg_epi_ctr1_c16_sel                       : 2;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_7(val) ((rs_tx_epi_top0_epi_top0_set_7*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_8                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x20)

#define TX_EPI_TOP0_EPI_TOP0_SET_8_struct                                rs_tx_epi_top0_epi_top0_set_8

typedef struct _rs_tx_epi_top0_epi_top0_set_8  rs_tx_epi_top0_epi_top0_set_8;
struct _rs_tx_epi_top0_epi_top0_set_8 {
    unsigned int reg_epi_ctr1_c17_sel                       : 2;
    unsigned int reg_epi_ctr1_c18_sel                       : 2;
    unsigned int reg_epi_ctr1_c19_sel                       : 2;
    unsigned int reg_epi_ctr1_c20_sel                       : 2;
    unsigned int reg_epi_ctr1_c21_sel                       : 2;
    unsigned int reg_epi_ctr1_c22_sel                       : 2;
    unsigned int reg_epi_ctr1_c23_sel                       : 2;
    unsigned int reg_epi_ctr1_c24_sel                       : 2;
    unsigned int reg_epi_ctr1_c25_sel                       : 2;
    unsigned int reg_epi_ctr1_c26_sel                       : 2;
    unsigned int reg_epi_ctr1_c27_sel                       : 2;
    unsigned int reg_epi_ctr1_c28_sel                       : 2;
    unsigned int reg_epi_ctr1_c29_sel                       : 2;
    unsigned int reg_epi_ctr1_c30_sel                       : 2;
    unsigned int reg_epi_ctr1_c31_sel                       : 2;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_8(val) ((rs_tx_epi_top0_epi_top0_set_8*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_9                                       (HV_EPI_TOP0_BASE_ADDRESS + 0x24)

#define TX_EPI_TOP0_EPI_TOP0_SET_9_struct                                rs_tx_epi_top0_epi_top0_set_9

typedef struct _rs_tx_epi_top0_epi_top0_set_9  rs_tx_epi_top0_epi_top0_set_9;
struct _rs_tx_epi_top0_epi_top0_set_9 {
    unsigned int reg_epi_ctr2_c2_sel                        : 2;
    unsigned int reg_epi_ctr2_c3_sel                        : 2;
    unsigned int reg_epi_ctr2_c4_sel                        : 2;
    unsigned int reg_epi_ctr2_c5_sel                        : 2;
    unsigned int reg_epi_ctr2_c6_sel                        : 2;
    unsigned int reg_epi_ctr2_c7_sel                        : 2;
    unsigned int reg_epi_ctr2_c8_sel                        : 2;
    unsigned int reg_epi_ctr2_c9_sel                        : 2;
    unsigned int reg_epi_ctr2_c10_sel                       : 2;
    unsigned int reg_epi_ctr2_c11_sel                       : 2;
    unsigned int reg_epi_ctr2_c12_sel                       : 2;
    unsigned int reg_epi_ctr2_c13_sel                       : 2;
    unsigned int reg_epi_ctr2_c14_sel                       : 2;
    unsigned int reg_epi_ctr2_c15_sel                       : 2;
    unsigned int reg_epi_ctr2_c16_sel                       : 2;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_9(val) ((rs_tx_epi_top0_epi_top0_set_9*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_10                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x28)

#define TX_EPI_TOP0_EPI_TOP0_SET_10_struct                               rs_tx_epi_top0_epi_top0_set_10

typedef struct _rs_tx_epi_top0_epi_top0_set_10  rs_tx_epi_top0_epi_top0_set_10;
struct _rs_tx_epi_top0_epi_top0_set_10 {
    unsigned int reg_epi_ctr2_c17_sel                       : 2;
    unsigned int reg_epi_ctr2_c18_sel                       : 2;
    unsigned int reg_epi_ctr2_c19_sel                       : 2;
    unsigned int reg_epi_ctr2_c20_sel                       : 2;
    unsigned int reg_epi_ctr2_c21_sel                       : 2;
    unsigned int reg_epi_ctr2_c22_sel                       : 2;
    unsigned int reg_epi_ctr2_c23_sel                       : 2;
    unsigned int reg_epi_ctr2_c24_sel                       : 2;
    unsigned int reg_epi_ctr2_c25_sel                       : 2;
    unsigned int reg_epi_ctr2_c26_sel                       : 2;
    unsigned int reg_epi_ctr2_c27_sel                       : 2;
    unsigned int reg_epi_ctr2_c28_sel                       : 2;
    unsigned int reg_epi_ctr2_c29_sel                       : 2;
    unsigned int reg_epi_ctr2_c30_sel                       : 2;
    unsigned int reg_epi_ctr2_c31_sel                       : 2;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_10(val) ((rs_tx_epi_top0_epi_top0_set_10*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_11                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x2C)

#define TX_EPI_TOP0_EPI_TOP0_SET_11_struct                               rs_tx_epi_top0_epi_top0_set_11

typedef struct _rs_tx_epi_top0_epi_top0_set_11  rs_tx_epi_top0_epi_top0_set_11;
struct _rs_tx_epi_top0_epi_top0_set_11 {
    unsigned int reg_epi_ctr3_c2_sel                        : 2;
    unsigned int reg_epi_ctr3_c3_sel                        : 2;
    unsigned int reg_epi_ctr3_c4_sel                        : 2;
    unsigned int reg_epi_ctr3_c5_sel                        : 2;
    unsigned int reg_epi_ctr3_c6_sel                        : 2;
    unsigned int reg_epi_ctr3_c7_sel                        : 2;
    unsigned int reg_epi_ctr3_c16_sel                       : 2;
    unsigned int reg_epi_ctr3_c17_sel                       : 2;
    unsigned int reg_epi_ctr3_c18_sel                       : 2;
    unsigned int reg_epi_ctr3_c19_sel                       : 2;
    unsigned int reg_epi_ctr3_c20_sel                       : 2;
    unsigned int reg_epi_ctr3_c21_sel                       : 2;
    unsigned int reserved                                   : 8;
};
#define tx_epi_top0_epi_top0_set_11(val) ((rs_tx_epi_top0_epi_top0_set_11*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_12                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x30)

#define TX_EPI_TOP0_EPI_TOP0_SET_12_struct                               rs_tx_epi_top0_epi_top0_set_12

typedef struct _rs_tx_epi_top0_epi_top0_set_12  rs_tx_epi_top0_epi_top0_set_12;
struct _rs_tx_epi_top0_epi_top0_set_12 {
    unsigned int reg_epi_ctr1_disp_ctrl_c2_sel              : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c3_sel              : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c4_sel              : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c5_sel              : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c6_sel              : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c7_sel              : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_12(val) ((rs_tx_epi_top0_epi_top0_set_12*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_13                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x34)

#define TX_EPI_TOP0_EPI_TOP0_SET_13_struct                               rs_tx_epi_top0_epi_top0_set_13

typedef struct _rs_tx_epi_top0_epi_top0_set_13  rs_tx_epi_top0_epi_top0_set_13;
struct _rs_tx_epi_top0_epi_top0_set_13 {
    unsigned int reg_epi_ctr1_disp_ctrl_c8_sel              : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c9_sel              : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c10_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c11_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c12_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c13_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_13(val) ((rs_tx_epi_top0_epi_top0_set_13*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_14                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x38)

#define TX_EPI_TOP0_EPI_TOP0_SET_14_struct                               rs_tx_epi_top0_epi_top0_set_14

typedef struct _rs_tx_epi_top0_epi_top0_set_14  rs_tx_epi_top0_epi_top0_set_14;
struct _rs_tx_epi_top0_epi_top0_set_14 {
    unsigned int reg_epi_ctr1_disp_ctrl_c14_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c15_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c16_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c17_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c18_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c19_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_14(val) ((rs_tx_epi_top0_epi_top0_set_14*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_15                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x3C)

#define TX_EPI_TOP0_EPI_TOP0_SET_15_struct                               rs_tx_epi_top0_epi_top0_set_15

typedef struct _rs_tx_epi_top0_epi_top0_set_15  rs_tx_epi_top0_epi_top0_set_15;
struct _rs_tx_epi_top0_epi_top0_set_15 {
    unsigned int reg_epi_ctr1_disp_ctrl_c20_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c21_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c22_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c23_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c24_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c25_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_15(val) ((rs_tx_epi_top0_epi_top0_set_15*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_16                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x40)

#define TX_EPI_TOP0_EPI_TOP0_SET_16_struct                               rs_tx_epi_top0_epi_top0_set_16

typedef struct _rs_tx_epi_top0_epi_top0_set_16  rs_tx_epi_top0_epi_top0_set_16;
struct _rs_tx_epi_top0_epi_top0_set_16 {
    unsigned int reg_epi_ctr1_disp_ctrl_c26_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c27_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c28_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c29_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c30_sel             : 5;
    unsigned int reg_epi_ctr1_disp_ctrl_c31_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_16(val) ((rs_tx_epi_top0_epi_top0_set_16*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_17                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x44)

#define TX_EPI_TOP0_EPI_TOP0_SET_17_struct                               rs_tx_epi_top0_epi_top0_set_17

typedef struct _rs_tx_epi_top0_epi_top0_set_17  rs_tx_epi_top0_epi_top0_set_17;
struct _rs_tx_epi_top0_epi_top0_set_17 {
    unsigned int reg_epi_ctr2_disp_ctrl_c2_sel              : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c3_sel              : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c4_sel              : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c5_sel              : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c6_sel              : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c7_sel              : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_17(val) ((rs_tx_epi_top0_epi_top0_set_17*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_18                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x48)

#define TX_EPI_TOP0_EPI_TOP0_SET_18_struct                               rs_tx_epi_top0_epi_top0_set_18

typedef struct _rs_tx_epi_top0_epi_top0_set_18  rs_tx_epi_top0_epi_top0_set_18;
struct _rs_tx_epi_top0_epi_top0_set_18 {
    unsigned int reg_epi_ctr2_disp_ctrl_c8_sel              : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c9_sel              : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c10_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c11_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c12_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c13_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_18(val) ((rs_tx_epi_top0_epi_top0_set_18*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_19                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x4C)

#define TX_EPI_TOP0_EPI_TOP0_SET_19_struct                               rs_tx_epi_top0_epi_top0_set_19

typedef struct _rs_tx_epi_top0_epi_top0_set_19  rs_tx_epi_top0_epi_top0_set_19;
struct _rs_tx_epi_top0_epi_top0_set_19 {
    unsigned int reg_epi_ctr2_disp_ctrl_c14_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c15_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c16_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c17_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c18_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c19_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_19(val) ((rs_tx_epi_top0_epi_top0_set_19*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_20                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x50)

#define TX_EPI_TOP0_EPI_TOP0_SET_20_struct                               rs_tx_epi_top0_epi_top0_set_20

typedef struct _rs_tx_epi_top0_epi_top0_set_20  rs_tx_epi_top0_epi_top0_set_20;
struct _rs_tx_epi_top0_epi_top0_set_20 {
    unsigned int reg_epi_ctr2_disp_ctrl_c20_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c21_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c22_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c23_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c24_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c25_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_20(val) ((rs_tx_epi_top0_epi_top0_set_20*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_21                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x54)

#define TX_EPI_TOP0_EPI_TOP0_SET_21_struct                               rs_tx_epi_top0_epi_top0_set_21

typedef struct _rs_tx_epi_top0_epi_top0_set_21  rs_tx_epi_top0_epi_top0_set_21;
struct _rs_tx_epi_top0_epi_top0_set_21 {
    unsigned int reg_epi_ctr2_disp_ctrl_c26_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c27_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c28_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c29_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c30_sel             : 5;
    unsigned int reg_epi_ctr2_disp_ctrl_c31_sel             : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_21(val) ((rs_tx_epi_top0_epi_top0_set_21*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_22                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x58)

#define TX_EPI_TOP0_EPI_TOP0_SET_22_struct                               rs_tx_epi_top0_epi_top0_set_22

typedef struct _rs_tx_epi_top0_epi_top0_set_22  rs_tx_epi_top0_epi_top0_set_22;
struct _rs_tx_epi_top0_epi_top0_set_22 {
    unsigned int reg_epi_ctr3_disp_ctrl_c2_sel              : 5;
    unsigned int reg_epi_ctr3_disp_ctrl_c3_sel              : 5;
    unsigned int reg_epi_ctr3_disp_ctrl_c4_sel              : 5;
    unsigned int reg_epi_ctr3_disp_ctrl_c5_sel              : 5;
    unsigned int reg_epi_ctr3_disp_ctrl_c6_sel              : 5;
    unsigned int reg_epi_ctr3_disp_ctrl_c7_sel              : 5;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_22(val) ((rs_tx_epi_top0_epi_top0_set_22*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_23                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x5C)

#define TX_EPI_TOP0_EPI_TOP0_SET_23_struct                               rs_tx_epi_top0_epi_top0_set_23

typedef struct _rs_tx_epi_top0_epi_top0_set_23  rs_tx_epi_top0_epi_top0_set_23;
struct _rs_tx_epi_top0_epi_top0_set_23 {
    unsigned int reg_epi_inv_line_0                         : 4;
    unsigned int reg_epi_inv_line_1                         : 4;
    unsigned int reg_epi_inv_line_2                         : 4;
    unsigned int reg_epi_inv_line_3                         : 4;
    unsigned int reg_epi_inv_line_4                         : 4;
    unsigned int reg_epi_inv_line_5                         : 4;
    unsigned int reg_epi_inv_line_6                         : 4;
    unsigned int reg_epi_inv_line_7                         : 4;
};
#define tx_epi_top0_epi_top0_set_23(val) ((rs_tx_epi_top0_epi_top0_set_23*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_24                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x60)

#define TX_EPI_TOP0_EPI_TOP0_SET_24_struct                               rs_tx_epi_top0_epi_top0_set_24

typedef struct _rs_tx_epi_top0_epi_top0_set_24  rs_tx_epi_top0_epi_top0_set_24;
struct _rs_tx_epi_top0_epi_top0_set_24 {
    unsigned int reg_epi_inv_line_8                         : 4;
    unsigned int reg_epi_inv_line_9                         : 4;
    unsigned int reg_epi_inv_line_10                        : 4;
    unsigned int reg_epi_inv_line_11                        : 4;
    unsigned int reg_epi_inv_line_12                        : 4;
    unsigned int reg_epi_inv_line_13                        : 4;
    unsigned int reg_epi_inv_line_14                        : 4;
    unsigned int reg_epi_inv_line_15                        : 4;
};
#define tx_epi_top0_epi_top0_set_24(val) ((rs_tx_epi_top0_epi_top0_set_24*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_25                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x64)

#define TX_EPI_TOP0_EPI_TOP0_SET_25_struct                               rs_tx_epi_top0_epi_top0_set_25

typedef struct _rs_tx_epi_top0_epi_top0_set_25  rs_tx_epi_top0_epi_top0_set_25;
struct _rs_tx_epi_top0_epi_top0_set_25 {
    unsigned int reg_epi_ctr_start_cfg                      :24;
    unsigned int reserved                                   : 8;
};
#define tx_epi_top0_epi_top0_set_25(val) ((rs_tx_epi_top0_epi_top0_set_25*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_26                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x68)

#define TX_EPI_TOP0_EPI_TOP0_SET_26_struct                               rs_tx_epi_top0_epi_top0_set_26

typedef struct _rs_tx_epi_top0_epi_top0_set_26  rs_tx_epi_top0_epi_top0_set_26;
struct _rs_tx_epi_top0_epi_top0_set_26 {
    unsigned int reg_epi_ctr3_cfg                           :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_26(val) ((rs_tx_epi_top0_epi_top0_set_26*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_27                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x6C)

#define TX_EPI_TOP0_EPI_TOP0_SET_27_struct                               rs_tx_epi_top0_epi_top0_set_27

typedef struct _rs_tx_epi_top0_epi_top0_set_27  rs_tx_epi_top0_epi_top0_set_27;
struct _rs_tx_epi_top0_epi_top0_set_27 {
    unsigned int reg_epi_p00_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_27(val) ((rs_tx_epi_top0_epi_top0_set_27*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_28                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x70)

#define TX_EPI_TOP0_EPI_TOP0_SET_28_struct                               rs_tx_epi_top0_epi_top0_set_28

typedef struct _rs_tx_epi_top0_epi_top0_set_28  rs_tx_epi_top0_epi_top0_set_28;
struct _rs_tx_epi_top0_epi_top0_set_28 {
    unsigned int reg_epi_p01_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_28(val) ((rs_tx_epi_top0_epi_top0_set_28*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_29                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x74)

#define TX_EPI_TOP0_EPI_TOP0_SET_29_struct                               rs_tx_epi_top0_epi_top0_set_29

typedef struct _rs_tx_epi_top0_epi_top0_set_29  rs_tx_epi_top0_epi_top0_set_29;
struct _rs_tx_epi_top0_epi_top0_set_29 {
    unsigned int reg_epi_p02_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_29(val) ((rs_tx_epi_top0_epi_top0_set_29*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_30                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x78)

#define TX_EPI_TOP0_EPI_TOP0_SET_30_struct                               rs_tx_epi_top0_epi_top0_set_30

typedef struct _rs_tx_epi_top0_epi_top0_set_30  rs_tx_epi_top0_epi_top0_set_30;
struct _rs_tx_epi_top0_epi_top0_set_30 {
    unsigned int reg_epi_p03_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_30(val) ((rs_tx_epi_top0_epi_top0_set_30*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_31                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x7C)

#define TX_EPI_TOP0_EPI_TOP0_SET_31_struct                               rs_tx_epi_top0_epi_top0_set_31

typedef struct _rs_tx_epi_top0_epi_top0_set_31  rs_tx_epi_top0_epi_top0_set_31;
struct _rs_tx_epi_top0_epi_top0_set_31 {
    unsigned int reg_epi_p04_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_31(val) ((rs_tx_epi_top0_epi_top0_set_31*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_32                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x80)

#define TX_EPI_TOP0_EPI_TOP0_SET_32_struct                               rs_tx_epi_top0_epi_top0_set_32

typedef struct _rs_tx_epi_top0_epi_top0_set_32  rs_tx_epi_top0_epi_top0_set_32;
struct _rs_tx_epi_top0_epi_top0_set_32 {
    unsigned int reg_epi_p05_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_32(val) ((rs_tx_epi_top0_epi_top0_set_32*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_33                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x84)

#define TX_EPI_TOP0_EPI_TOP0_SET_33_struct                               rs_tx_epi_top0_epi_top0_set_33

typedef struct _rs_tx_epi_top0_epi_top0_set_33  rs_tx_epi_top0_epi_top0_set_33;
struct _rs_tx_epi_top0_epi_top0_set_33 {
    unsigned int reg_epi_p06_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_33(val) ((rs_tx_epi_top0_epi_top0_set_33*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_34                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x88)

#define TX_EPI_TOP0_EPI_TOP0_SET_34_struct                               rs_tx_epi_top0_epi_top0_set_34

typedef struct _rs_tx_epi_top0_epi_top0_set_34  rs_tx_epi_top0_epi_top0_set_34;
struct _rs_tx_epi_top0_epi_top0_set_34 {
    unsigned int reg_epi_p07_ctr1_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_34(val) ((rs_tx_epi_top0_epi_top0_set_34*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_35                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x8C)

#define TX_EPI_TOP0_EPI_TOP0_SET_35_struct                               rs_tx_epi_top0_epi_top0_set_35

typedef struct _rs_tx_epi_top0_epi_top0_set_35  rs_tx_epi_top0_epi_top0_set_35;
struct _rs_tx_epi_top0_epi_top0_set_35 {
    unsigned int reg_epi_p00_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_35(val) ((rs_tx_epi_top0_epi_top0_set_35*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_36                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x90)

#define TX_EPI_TOP0_EPI_TOP0_SET_36_struct                               rs_tx_epi_top0_epi_top0_set_36

typedef struct _rs_tx_epi_top0_epi_top0_set_36  rs_tx_epi_top0_epi_top0_set_36;
struct _rs_tx_epi_top0_epi_top0_set_36 {
    unsigned int reg_epi_p01_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_36(val) ((rs_tx_epi_top0_epi_top0_set_36*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_37                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x94)

#define TX_EPI_TOP0_EPI_TOP0_SET_37_struct                               rs_tx_epi_top0_epi_top0_set_37

typedef struct _rs_tx_epi_top0_epi_top0_set_37  rs_tx_epi_top0_epi_top0_set_37;
struct _rs_tx_epi_top0_epi_top0_set_37 {
    unsigned int reg_epi_p02_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_37(val) ((rs_tx_epi_top0_epi_top0_set_37*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_38                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x98)

#define TX_EPI_TOP0_EPI_TOP0_SET_38_struct                               rs_tx_epi_top0_epi_top0_set_38

typedef struct _rs_tx_epi_top0_epi_top0_set_38  rs_tx_epi_top0_epi_top0_set_38;
struct _rs_tx_epi_top0_epi_top0_set_38 {
    unsigned int reg_epi_p03_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_38(val) ((rs_tx_epi_top0_epi_top0_set_38*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_39                                      (HV_EPI_TOP0_BASE_ADDRESS + 0x9C)

#define TX_EPI_TOP0_EPI_TOP0_SET_39_struct                               rs_tx_epi_top0_epi_top0_set_39

typedef struct _rs_tx_epi_top0_epi_top0_set_39  rs_tx_epi_top0_epi_top0_set_39;
struct _rs_tx_epi_top0_epi_top0_set_39 {
    unsigned int reg_epi_p04_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_39(val) ((rs_tx_epi_top0_epi_top0_set_39*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_40                                      (HV_EPI_TOP0_BASE_ADDRESS + 0xA0)

#define TX_EPI_TOP0_EPI_TOP0_SET_40_struct                               rs_tx_epi_top0_epi_top0_set_40

typedef struct _rs_tx_epi_top0_epi_top0_set_40  rs_tx_epi_top0_epi_top0_set_40;
struct _rs_tx_epi_top0_epi_top0_set_40 {
    unsigned int reg_epi_p05_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_40(val) ((rs_tx_epi_top0_epi_top0_set_40*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_41                                      (HV_EPI_TOP0_BASE_ADDRESS + 0xA4)

#define TX_EPI_TOP0_EPI_TOP0_SET_41_struct                               rs_tx_epi_top0_epi_top0_set_41

typedef struct _rs_tx_epi_top0_epi_top0_set_41  rs_tx_epi_top0_epi_top0_set_41;
struct _rs_tx_epi_top0_epi_top0_set_41 {
    unsigned int reg_epi_p06_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_41(val) ((rs_tx_epi_top0_epi_top0_set_41*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_42                                      (HV_EPI_TOP0_BASE_ADDRESS + 0xA8)

#define TX_EPI_TOP0_EPI_TOP0_SET_42_struct                               rs_tx_epi_top0_epi_top0_set_42

typedef struct _rs_tx_epi_top0_epi_top0_set_42  rs_tx_epi_top0_epi_top0_set_42;
struct _rs_tx_epi_top0_epi_top0_set_42 {
    unsigned int reg_epi_p07_ctr2_cfg                       :30;
    unsigned int reserved                                   : 2;
};
#define tx_epi_top0_epi_top0_set_42(val) ((rs_tx_epi_top0_epi_top0_set_42*)&(val))



#define TX_EPI_TOP0_EPI_TOP0_SET_57                                      (HV_EPI_TOP0_BASE_ADDRESS + 0xE4)

#define TX_EPI_TOP0_EPI_TOP0_SET_57_struct                               rs_tx_epi_top0_epi_top0_set_57

typedef struct _rs_tx_epi_top0_epi_top0_set_57  rs_tx_epi_top0_epi_top0_set_57;
struct _rs_tx_epi_top0_epi_top0_set_57 {
    unsigned int reg_epi_den_end_sub_00                     : 2;
    unsigned int reg_epi_den_end_sub_01                     : 2;
    unsigned int reg_epi_den_end_sub_02                     : 2;
    unsigned int reg_epi_den_end_sub_03                     : 2;
    unsigned int reg_epi_den_end_sub_04                     : 2;
    unsigned int reg_epi_den_end_sub_05                     : 2;
    unsigned int reg_epi_den_end_sub_06                     : 2;
    unsigned int reg_epi_den_end_sub_07                     : 2;
    unsigned int reg_epi_den_end_sub_08                     : 2;
    unsigned int reg_epi_den_end_sub_09                     : 2;
    unsigned int reg_epi_den_end_sub_10                     : 2;
    unsigned int reg_epi_den_end_sub_11                     : 2;
    unsigned int reg_epi_den_end_sub_12                     : 2;
    unsigned int reg_epi_den_end_sub_13                     : 2;
    unsigned int reg_epi_den_end_sub_14                     : 2;
    unsigned int reg_epi_den_end_sub_15                     : 2;
};
#define tx_epi_top0_epi_top0_set_57(val) ((rs_tx_epi_top0_epi_top0_set_57*)&(val))



#define TX_EPI_TOP0_X                                                    (HV_EPI_TOP0_BASE_ADDRESS + 0xE8)

#define TX_EPI_TOP0_X_struct                                             rs_tx_epi_top0_x

typedef struct _rs_tx_epi_top0_x  rs_tx_epi_top0_x;
struct _rs_tx_epi_top0_x {
    unsigned int reg_epi_den_end_sub_16                     : 2;
    unsigned int reg_epi_den_end_sub_17                     : 2;
    unsigned int reg_epi_den_end_sub_18                     : 2;
    unsigned int reg_epi_den_end_sub_19                     : 2;
    unsigned int reg_epi_den_end_sub_20                     : 2;
    unsigned int reg_epi_den_end_sub_21                     : 2;
    unsigned int reg_epi_den_end_sub_22                     : 2;
    unsigned int reg_epi_den_end_sub_23                     : 2;
    unsigned int reserved                                   :16;
};
#define tx_epi_top0_x(val) ((rs_tx_epi_top0_x*)&(val))



#endif