/**
 * @file hv_cal_Ktx.c
 * @brief KTX CAL module driver
 * @details This module provide interfaces for DRV level.
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20220903
 * @copyright Copyright(c),2022-9, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date             <th>Details
 * <tr><td>HiView SoC Software Team   <td>20220903       <td>Create and first Version.
 * </table>
 **/

#include "hv_cal_Ktx.h"
#include "hv_vos_Comm.h"
#include "HV_REGS_HT7315.h"
#include "PanelConfig.h"
#include "hv_comm_Log.h"
#include "hv_comm_Define.h"
#include "hv_cal_Gpio.h"

VOID Hv_Cal_Ktx_ComboTxPhyMuxSel(UCHAR8 ucPhyIdx, const PanelParam *pstPanelParam)
{
    switch (ucPhyIdx)
    {
        case 0:
        {
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_0_mux_sel, pstPanelParam->ucPanelPhy0Lane0MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_1_mux_sel, pstPanelParam->ucPanelPhy0Lane1MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_2_mux_sel, pstPanelParam->ucPanelPhy0Lane2MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_3_mux_sel, pstPanelParam->ucPanelPhy0Lane3MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_pn_swap_lane0, pstPanelParam->bPanelPhy0Lane0PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_pn_swap_lane1, pstPanelParam->bPanelPhy0Lane1PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_pn_swap_lane2, pstPanelParam->bPanelPhy0Lane2PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX00_MUX_CTRL, reg_txphy_00_pn_swap_lane3, pstPanelParam->bPanelPhy0Lane3PnSwap);
            break;
        }

        case 1:
        {
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_0_mux_sel, pstPanelParam->ucPanelPhy1Lane0MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_1_mux_sel, pstPanelParam->ucPanelPhy1Lane1MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_2_mux_sel, pstPanelParam->ucPanelPhy1Lane2MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_3_mux_sel, pstPanelParam->ucPanelPhy1Lane3MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_pn_swap_lane0, pstPanelParam->bPanelPhy1Lane0PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_pn_swap_lane1, pstPanelParam->bPanelPhy1Lane1PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_pn_swap_lane2, pstPanelParam->bPanelPhy1Lane2PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX01_MUX_CTRL, reg_txphy_01_pn_swap_lane3, pstPanelParam->bPanelPhy1Lane3PnSwap);
            break;
        }

        case 2:
        {
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_0_mux_sel, pstPanelParam->ucPanelPhy2Lane0MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_1_mux_sel, pstPanelParam->ucPanelPhy2Lane1MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_2_mux_sel, pstPanelParam->ucPanelPhy2Lane2MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_3_mux_sel, pstPanelParam->ucPanelPhy2Lane3MuxSel);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_pn_swap_lane0, pstPanelParam->bPanelPhy2Lane0PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_pn_swap_lane1, pstPanelParam->bPanelPhy2Lane1PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_pn_swap_lane2, pstPanelParam->bPanelPhy2Lane2PnSwap);
            HV_W32_FIELD(TX_COMBOTX_PHY_3_TX02_MUX_CTRL, reg_txphy_02_pn_swap_lane3, pstPanelParam->bPanelPhy2Lane3PnSwap);
            break;
        }

        default:
        {
            break;
        }
    }
}

VOID HV_Cal_Ktx_ComboTxPhyEn(UCHAR8 ucPhy, BOOL bEn)
{
    HV_LOG_DEBUG(PANEL, "HV_Cal_Ktx_ComboTxPhyEn ucPhy:%d bEn:%d ", ucPhy, bEn);
    if (ucPhy == 0)
    {
        HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_drv_en, bEn ? 0xF : 0);
        HV_W32_FIELD(TX_COMBOTX_PHY_1_00, reg_txphy_00_pd, bEn ? 0 : 1);
        HV_W32_FIELD(TX_COMBOTX_PHY_1_34, reg_txphy_00_pulldn_b, bEn ? 0xF : 0);
    }
    else if (ucPhy == 1)
    {
        HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_drv_en, bEn ? 0xF : 0);
        HV_W32_FIELD(TX_COMBOTX_PHY_1_40, reg_txphy_01_pd, bEn ? 0 : 1);
        HV_W32_FIELD(TX_COMBOTX_PHY_1_74, reg_txphy_01_pulldn_b, bEn ? 0xF : 0);
    }
    else if (ucPhy == 2)
    {
        HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_drv_en, bEn ? 0xF : 0);
        HV_W32_FIELD(TX_COMBOTX_PHY_1_80, reg_txphy_02_pd, bEn ? 0 : 1);
        HV_W32_FIELD(TX_COMBOTX_PHY_1_B4, reg_txphy_02_pulldn_b, bEn ? 0xF : 0);
    }
    else
    {
        HV_LOG_DEBUG(PANEL, "############## HV_Cal_No matching bPhy %d K, bPhy ##############");
    }
    return;
}


BOOL Hv_Cal_Ktx_GetTxPhyAfifoFlag(VOID)
{
    HV_R32_DECL_VAR();
    UINT32 uiFlow = HV_R32_FIELD(TX_COMBOTX_PHY_3_TX_AFIFO_RO_0, regr_txphy_00_afifo_overflow);
    uiFlow += HV_R32_FIELD(TX_COMBOTX_PHY_3_TX_AFIFO_RO_1, regr_txphy_00_afifo_underflow);
    uiFlow += HV_R32_FIELD(TX_COMBOTX_PHY_3_TX_AFIFO_RO_0, regr_txphy_01_afifo_overflow);
    uiFlow += HV_R32_FIELD(TX_COMBOTX_PHY_3_TX_AFIFO_RO_1, regr_txphy_01_afifo_underflow);
    uiFlow += HV_R32_FIELD(TX_COMBOTX_PHY_3_TX_AFIFO_RO_0, regr_txphy_02_afifo_overflow);
    uiFlow += HV_R32_FIELD(TX_COMBOTX_PHY_3_TX_AFIFO_RO_1, regr_txphy_02_afifo_underflow);
    return uiFlow == 0 ? 0: 1;
}

VOID Hv_Cal_Ktx_TxPhyAfifoFlagClear(VOID)
{
    HV_W32_FIELD(TX_COMBOTX_PHY_3_B0, reg_tx_afifo_readback_clear, 1);
    Hv_Vos_Delayus(10);
    HV_W32_FIELD(TX_COMBOTX_PHY_3_B0, reg_tx_afifo_readback_clear, 0);
    return;
}

BOOL Hv_Cal_Ktx_GetKtxPostFifoFlag(VOID)
{
    BOOL bFifoFlag = 0;
    HV_R32_DECL_VAR();
    bFifoFlag = HV_R32_FIELD(TX_KTX_POST_TOP_E0, regr_ktx_fifo_underflow) == 0 ? 0 : 1;
    bFifoFlag = bFifoFlag || (HV_R32_FIELD(TX_KTX_POST_TOP_E4, regr_ktx_fifo_overflow) == 0 ? 0 : 1);
    return bFifoFlag;
}

VOID Hv_Cal_Ktx_KtxPostFifoFlagClear(VOID)
{
    HV_W32_FIELD(TX_KTX_POST_TOP_04, reg_ktx_fifo_flag_clear, 1);
    Hv_Vos_Delayus(10);
    HV_W32_FIELD(TX_KTX_POST_TOP_04, reg_ktx_fifo_flag_clear, 0);
    return;
}

BOOL Hv_Cal_Ktx_GetKtxPifAfifoFlag(VOID)
{
    BOOL bFifoFlag = 0;
    HV_R32_DECL_VAR();
    bFifoFlag = HV_R32_FIELD(TX_PIF_TX_TOP_A10_FIFO_READBACK_0, regr_pif_afifo_flag_underflow) == 0 ? 0 : 1;
    bFifoFlag = bFifoFlag || (HV_R32_FIELD(TX_PIF_TX_TOP_A10_FIFO_READBACK_1, regr_pif_afifo_flag_overflow) == 0 ? 0 : 1);
    return bFifoFlag;
}

VOID Hv_Cal_Ktx_KtxPifAfifoFlagClear(VOID)
{
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_DEBUG_REG_0, reg_pif_afifo_flag_clear, 1);
    Hv_Vos_Delayus(10);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_DEBUG_REG_0, reg_pif_afifo_flag_clear, 0);
    return;
}

VOID Hv_Cal_Ktx_SetPostTopParam(HvKtxPostTopCfgParam *pstKtxTostTopParam)
{
#ifdef HV_SCALER_DEBUG_VERSION
    HV_LOG_DEBUG(PANEL, "############## Hv_Cal_Ktx_SetPostTopParam ##############");
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucPortNum: %d", pstKtxTostTopParam->ucPortNum);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucPairNum: %d", pstKtxTostTopParam->ucPairNum);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDoublescanEn: %d", pstKtxTostTopParam->ucDoublescanEn);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDegenUseInPreDe: %d", pstKtxTostTopParam->ucDegenUseInPreDe);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDualgateEn: %d", pstKtxTostTopParam->ucDualgateEn);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucTrigateEn: %d", pstKtxTostTopParam->ucTrigateEn);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDegenUse1stLine: %d", pstKtxTostTopParam->ucDegenUse1stLine);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDePreNum: %d", pstKtxTostTopParam->ucDePreNum);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDeOutDly: %d", pstKtxTostTopParam->ucDeOutDly);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucMppHBackPorch: %d", pstKtxTostTopParam->ucMppHBackPorch);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDePreDummyMode: %d", pstKtxTostTopParam->ucDePreDummyMode);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDePostDummyMode: %d", pstKtxTostTopParam->ucDePostDummyMode);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDePreDummyNum: %d", pstKtxTostTopParam->ucDePreDummyNum);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usDePostDummyNum: %d", pstKtxTostTopParam->usDePostDummyNum);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucRamEnable: %d", pstKtxTostTopParam->ucRamEnable);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usMppHAct: %d", pstKtxTostTopParam->usMppHAct);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usMppVAct: %d", pstKtxTostTopParam->usMppVAct);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usWram1rdStartAddr: %d", pstKtxTostTopParam->usWram1stStartAddr);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usWram2rdStartAddr: %d", pstKtxTostTopParam->usWram2ndStartAddr);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usWram3rdStartAddr: %d", pstKtxTostTopParam->usWram3rdStartAddr);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucDsMapEn: %d", pstKtxTostTopParam->ucDsMapEn);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->uiLnPixelSwap: %d", pstKtxTostTopParam->uiLnPixelSwap);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usInVAct: %d", pstKtxTostTopParam->usInVAct);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->ucOutDataMode: %d", pstKtxTostTopParam->ucOutDataMode);
    HV_LOG_DEBUG(PANEL, "pstKtxTostTopParam->usHsFilter: %d", pstKtxTostTopParam->usHsFilter);
#endif
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_port_num, pstKtxTostTopParam->ucPortNum);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_pair_num, pstKtxTostTopParam->ucPairNum);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_doublescan_en, pstKtxTostTopParam->ucDoublescanEn);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_degen_use_in_pre_de, pstKtxTostTopParam->ucDegenUseInPreDe);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_post_dualgate_en, pstKtxTostTopParam->ucDualgateEn);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_post_trigate_en, pstKtxTostTopParam->ucTrigateEn);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_degen_use_1st_line, pstKtxTostTopParam->ucDegenUse1stLine);
    HV_W32_FIELD(TX_KTX_POST_TOP_04, reg_ktx_de_pre_num, pstKtxTostTopParam->ucDePreNum);
    HV_W32_FIELD(TX_KTX_POST_TOP_04, reg_ktx_ctl_de_out_dly, pstKtxTostTopParam->ucDeOutDly);
    HV_W32_FIELD(TX_KTX_POST_TOP_04, reg_ktx_mpp_hbackporch, pstKtxTostTopParam->ucMppHBackPorch);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_de_pre_dummy_mode, pstKtxTostTopParam->ucDePreDummyMode);
    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_de_post_dummy_mode, pstKtxTostTopParam->ucDePostDummyMode);
    HV_W32_FIELD(TX_KTX_POST_TOP_0C, reg_ktx_de_pre_dummy_num, pstKtxTostTopParam->ucDePreDummyNum);
    HV_W32_FIELD(TX_KTX_POST_TOP_0C, reg_ktx_de_post_dummy_num, pstKtxTostTopParam->usDePostDummyNum);
    HV_W32_FIELD(TX_KTX_POST_TOP_04, reg_ktx_ram_enable, pstKtxTostTopParam->ucRamEnable);
    HV_W32_FIELD(TX_KTX_POST_TOP_08, reg_ktx_mpp_hact, pstKtxTostTopParam->usMppHAct);
    HV_W32_FIELD(TX_KTX_POST_TOP_08, reg_ktx_mpp_vact, pstKtxTostTopParam->usMppVAct);
    HV_W32_FIELD(TX_KTX_POST_TOP_0C, reg_ktx_wram_1st_start_addr, pstKtxTostTopParam->usWram1stStartAddr);
    HV_W32_FIELD(TX_KTX_POST_TOP_10, reg_ktx_wram_2nd_start_addr, pstKtxTostTopParam->usWram2ndStartAddr);
    HV_W32_FIELD(TX_KTX_POST_TOP_10, reg_ktx_wram_3rd_start_addr, pstKtxTostTopParam->usWram3rdStartAddr);
    HV_W32_FIELD(TX_KTX_POST_TOP_18, reg_ktx_ds_map_en, pstKtxTostTopParam->ucDsMapEn);
    HV_W32_FIELD(TX_KTX_POST_TOP_60, reg_ktx_ln_pixel_swap, pstKtxTostTopParam->uiLnPixelSwap);
    HV_W32_FIELD(TX_KTX_POST_TOP_80, reg_ktx_in_vact, pstKtxTostTopParam->usInVAct);

    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p00_addr_shift, pstKtxTostTopParam->usRRamAddrShift[0]);
    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p01_addr_shift, pstKtxTostTopParam->usRRamAddrShift[1]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p02_addr_shift, pstKtxTostTopParam->usRRamAddrShift[2]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p03_addr_shift, pstKtxTostTopParam->usRRamAddrShift[3]);
    HV_W32_FIELD(TX_KTX_POST_TOP_48, reg_ktx_rram_p04_addr_shift, pstKtxTostTopParam->usRRamAddrShift[4]);
    HV_W32_FIELD(TX_KTX_POST_TOP_48, reg_ktx_rram_p05_addr_shift, pstKtxTostTopParam->usRRamAddrShift[5]);
    HV_W32_FIELD(TX_KTX_POST_TOP_4C, reg_ktx_rram_p06_addr_shift, pstKtxTostTopParam->usRRamAddrShift[6]);
    HV_W32_FIELD(TX_KTX_POST_TOP_4C, reg_ktx_rram_p07_addr_shift, pstKtxTostTopParam->usRRamAddrShift[7]);
    HV_W32_FIELD(TX_KTX_POST_TOP_50, reg_ktx_rram_p08_addr_shift, pstKtxTostTopParam->usRRamAddrShift[8]);
    HV_W32_FIELD(TX_KTX_POST_TOP_50, reg_ktx_rram_p09_addr_shift, pstKtxTostTopParam->usRRamAddrShift[9]);
    HV_W32_FIELD(TX_KTX_POST_TOP_54, reg_ktx_rram_p10_addr_shift, pstKtxTostTopParam->usRRamAddrShift[10]);
    HV_W32_FIELD(TX_KTX_POST_TOP_54, reg_ktx_rram_p11_addr_shift, pstKtxTostTopParam->usRRamAddrShift[11]);
    HV_W32_FIELD(TX_KTX_POST_TOP_58, reg_ktx_rram_p12_addr_shift, pstKtxTostTopParam->usRRamAddrShift[12]);
    HV_W32_FIELD(TX_KTX_POST_TOP_58, reg_ktx_rram_p13_addr_shift, pstKtxTostTopParam->usRRamAddrShift[13]);
    HV_W32_FIELD(TX_KTX_POST_TOP_5C, reg_ktx_rram_p14_addr_shift, pstKtxTostTopParam->usRRamAddrShift[14]);
    HV_W32_FIELD(TX_KTX_POST_TOP_5C, reg_ktx_rram_p15_addr_shift, pstKtxTostTopParam->usRRamAddrShift[15]);
    HV_W32_FIELD(TX_KTX_POST_TOP_70, reg_ktx_rram_p16_addr_shift, pstKtxTostTopParam->usRRamAddrShift[16]);
    HV_W32_FIELD(TX_KTX_POST_TOP_70, reg_ktx_rram_p17_addr_shift, pstKtxTostTopParam->usRRamAddrShift[17]);
    HV_W32_FIELD(TX_KTX_POST_TOP_74, reg_ktx_rram_p18_addr_shift, pstKtxTostTopParam->usRRamAddrShift[18]);
    HV_W32_FIELD(TX_KTX_POST_TOP_74, reg_ktx_rram_p19_addr_shift, pstKtxTostTopParam->usRRamAddrShift[19]);
    HV_W32_FIELD(TX_KTX_POST_TOP_78, reg_ktx_rram_p20_addr_shift, pstKtxTostTopParam->usRRamAddrShift[20]);
    HV_W32_FIELD(TX_KTX_POST_TOP_78, reg_ktx_rram_p21_addr_shift, pstKtxTostTopParam->usRRamAddrShift[21]);
    HV_W32_FIELD(TX_KTX_POST_TOP_7C, reg_ktx_rram_p22_addr_shift, pstKtxTostTopParam->usRRamAddrShift[22]);
    HV_W32_FIELD(TX_KTX_POST_TOP_7C, reg_ktx_rram_p23_addr_shift, pstKtxTostTopParam->usRRamAddrShift[23]);
    HV_W32_FIELD(TX_KTX_POST_TOP_9C, reg_ktx_rram_p24_addr_shift, pstKtxTostTopParam->usRRamAddrShift[24]);
    HV_W32_FIELD(TX_KTX_POST_TOP_9C, reg_ktx_rram_p25_addr_shift, pstKtxTostTopParam->usRRamAddrShift[25]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A0, reg_ktx_rram_p26_addr_shift, pstKtxTostTopParam->usRRamAddrShift[26]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A0, reg_ktx_rram_p27_addr_shift, pstKtxTostTopParam->usRRamAddrShift[27]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A4, reg_ktx_rram_p28_addr_shift, pstKtxTostTopParam->usRRamAddrShift[28]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A4, reg_ktx_rram_p29_addr_shift, pstKtxTostTopParam->usRRamAddrShift[29]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A8, reg_ktx_rram_p30_addr_shift, pstKtxTostTopParam->usRRamAddrShift[30]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A8, reg_ktx_rram_p31_addr_shift, pstKtxTostTopParam->usRRamAddrShift[31]);

    HV_W32_FIELD(TX_KTX_POST_TOP_20, reg_ktx_lane00_index, pstKtxTostTopParam->ucLaneIndex[0]);
    HV_W32_FIELD(TX_KTX_POST_TOP_20, reg_ktx_lane01_index, pstKtxTostTopParam->ucLaneIndex[1]);
    HV_W32_FIELD(TX_KTX_POST_TOP_20, reg_ktx_lane02_index, pstKtxTostTopParam->ucLaneIndex[2]);
    HV_W32_FIELD(TX_KTX_POST_TOP_20, reg_ktx_lane03_index, pstKtxTostTopParam->ucLaneIndex[3]);
    HV_W32_FIELD(TX_KTX_POST_TOP_24, reg_ktx_lane04_index, pstKtxTostTopParam->ucLaneIndex[4]);
    HV_W32_FIELD(TX_KTX_POST_TOP_24, reg_ktx_lane05_index, pstKtxTostTopParam->ucLaneIndex[5]);
    HV_W32_FIELD(TX_KTX_POST_TOP_24, reg_ktx_lane06_index, pstKtxTostTopParam->ucLaneIndex[6]);
    HV_W32_FIELD(TX_KTX_POST_TOP_24, reg_ktx_lane07_index, pstKtxTostTopParam->ucLaneIndex[7]);
    HV_W32_FIELD(TX_KTX_POST_TOP_28, reg_ktx_lane08_index, pstKtxTostTopParam->ucLaneIndex[8]);
    HV_W32_FIELD(TX_KTX_POST_TOP_28, reg_ktx_lane09_index, pstKtxTostTopParam->ucLaneIndex[9]);
    HV_W32_FIELD(TX_KTX_POST_TOP_28, reg_ktx_lane10_index, pstKtxTostTopParam->ucLaneIndex[10]);
    HV_W32_FIELD(TX_KTX_POST_TOP_28, reg_ktx_lane11_index, pstKtxTostTopParam->ucLaneIndex[11]);
    HV_W32_FIELD(TX_KTX_POST_TOP_2C, reg_ktx_lane12_index, pstKtxTostTopParam->ucLaneIndex[12]);
    HV_W32_FIELD(TX_KTX_POST_TOP_2C, reg_ktx_lane13_index, pstKtxTostTopParam->ucLaneIndex[13]);
    HV_W32_FIELD(TX_KTX_POST_TOP_2C, reg_ktx_lane14_index, pstKtxTostTopParam->ucLaneIndex[14]);
    HV_W32_FIELD(TX_KTX_POST_TOP_2C, reg_ktx_lane15_index, pstKtxTostTopParam->ucLaneIndex[15]);
    HV_W32_FIELD(TX_KTX_POST_TOP_30, reg_ktx_lane16_index, pstKtxTostTopParam->ucLaneIndex[16]);
    HV_W32_FIELD(TX_KTX_POST_TOP_30, reg_ktx_lane17_index, pstKtxTostTopParam->ucLaneIndex[17]);
    HV_W32_FIELD(TX_KTX_POST_TOP_30, reg_ktx_lane18_index, pstKtxTostTopParam->ucLaneIndex[18]);
    HV_W32_FIELD(TX_KTX_POST_TOP_30, reg_ktx_lane19_index, pstKtxTostTopParam->ucLaneIndex[19]);
    HV_W32_FIELD(TX_KTX_POST_TOP_34, reg_ktx_lane20_index, pstKtxTostTopParam->ucLaneIndex[20]);
    HV_W32_FIELD(TX_KTX_POST_TOP_34, reg_ktx_lane21_index, pstKtxTostTopParam->ucLaneIndex[21]);
    HV_W32_FIELD(TX_KTX_POST_TOP_34, reg_ktx_lane22_index, pstKtxTostTopParam->ucLaneIndex[22]);
    HV_W32_FIELD(TX_KTX_POST_TOP_34, reg_ktx_lane23_index, pstKtxTostTopParam->ucLaneIndex[23]);
    HV_W32_FIELD(TX_KTX_POST_TOP_38, reg_ktx_lane24_index, pstKtxTostTopParam->ucLaneIndex[24]);
    HV_W32_FIELD(TX_KTX_POST_TOP_38, reg_ktx_lane25_index, pstKtxTostTopParam->ucLaneIndex[25]);
    HV_W32_FIELD(TX_KTX_POST_TOP_38, reg_ktx_lane26_index, pstKtxTostTopParam->ucLaneIndex[26]);
    HV_W32_FIELD(TX_KTX_POST_TOP_38, reg_ktx_lane27_index, pstKtxTostTopParam->ucLaneIndex[27]);
    HV_W32_FIELD(TX_KTX_POST_TOP_3C, reg_ktx_lane28_index, pstKtxTostTopParam->ucLaneIndex[28]);
    HV_W32_FIELD(TX_KTX_POST_TOP_3C, reg_ktx_lane29_index, pstKtxTostTopParam->ucLaneIndex[29]);
    HV_W32_FIELD(TX_KTX_POST_TOP_3C, reg_ktx_lane30_index, pstKtxTostTopParam->ucLaneIndex[30]);
    HV_W32_FIELD(TX_KTX_POST_TOP_3C, reg_ktx_lane31_index, pstKtxTostTopParam->ucLaneIndex[31]);

    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p00_reverse, pstKtxTostTopParam->ucRamReverse[0]);
    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p01_reverse, pstKtxTostTopParam->ucRamReverse[1]);
    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p02_reverse, pstKtxTostTopParam->ucRamReverse[2]);
    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p03_reverse, pstKtxTostTopParam->ucRamReverse[3]);
    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p04_reverse, pstKtxTostTopParam->ucRamReverse[4]);
    HV_W32_FIELD(TX_KTX_POST_TOP_40, reg_ktx_rram_p05_reverse, pstKtxTostTopParam->ucRamReverse[5]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p06_reverse, pstKtxTostTopParam->ucRamReverse[6]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p07_reverse, pstKtxTostTopParam->ucRamReverse[7]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p08_reverse, pstKtxTostTopParam->ucRamReverse[8]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p09_reverse, pstKtxTostTopParam->ucRamReverse[9]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p10_reverse, pstKtxTostTopParam->ucRamReverse[10]);
    HV_W32_FIELD(TX_KTX_POST_TOP_44, reg_ktx_rram_p11_reverse, pstKtxTostTopParam->ucRamReverse[11]);
    HV_W32_FIELD(TX_KTX_POST_TOP_48, reg_ktx_rram_p12_reverse, pstKtxTostTopParam->ucRamReverse[12]);
    HV_W32_FIELD(TX_KTX_POST_TOP_48, reg_ktx_rram_p13_reverse, pstKtxTostTopParam->ucRamReverse[13]);
    HV_W32_FIELD(TX_KTX_POST_TOP_48, reg_ktx_rram_p14_reverse, pstKtxTostTopParam->ucRamReverse[14]);
    HV_W32_FIELD(TX_KTX_POST_TOP_48, reg_ktx_rram_p15_reverse, pstKtxTostTopParam->ucRamReverse[15]);
    HV_W32_FIELD(TX_KTX_POST_TOP_70, reg_ktx_rram_p16_reverse, pstKtxTostTopParam->ucRamReverse[16]);
    HV_W32_FIELD(TX_KTX_POST_TOP_70, reg_ktx_rram_p17_reverse, pstKtxTostTopParam->ucRamReverse[17]);
    HV_W32_FIELD(TX_KTX_POST_TOP_70, reg_ktx_rram_p18_reverse, pstKtxTostTopParam->ucRamReverse[18]);
    HV_W32_FIELD(TX_KTX_POST_TOP_70, reg_ktx_rram_p19_reverse, pstKtxTostTopParam->ucRamReverse[19]);
    HV_W32_FIELD(TX_KTX_POST_TOP_74, reg_ktx_rram_p20_reverse, pstKtxTostTopParam->ucRamReverse[20]);
    HV_W32_FIELD(TX_KTX_POST_TOP_74, reg_ktx_rram_p21_reverse, pstKtxTostTopParam->ucRamReverse[21]);
    HV_W32_FIELD(TX_KTX_POST_TOP_74, reg_ktx_rram_p22_reverse, pstKtxTostTopParam->ucRamReverse[22]);
    HV_W32_FIELD(TX_KTX_POST_TOP_74, reg_ktx_rram_p23_reverse, pstKtxTostTopParam->ucRamReverse[23]);
    HV_W32_FIELD(TX_KTX_POST_TOP_9C, reg_ktx_rram_p24_reverse, pstKtxTostTopParam->ucRamReverse[24]);
    HV_W32_FIELD(TX_KTX_POST_TOP_9C, reg_ktx_rram_p25_reverse, pstKtxTostTopParam->ucRamReverse[25]);
    HV_W32_FIELD(TX_KTX_POST_TOP_9C, reg_ktx_rram_p26_reverse, pstKtxTostTopParam->ucRamReverse[26]);
    HV_W32_FIELD(TX_KTX_POST_TOP_9C, reg_ktx_rram_p27_reverse, pstKtxTostTopParam->ucRamReverse[27]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A0, reg_ktx_rram_p28_reverse, pstKtxTostTopParam->ucRamReverse[28]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A0, reg_ktx_rram_p29_reverse, pstKtxTostTopParam->ucRamReverse[29]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A0, reg_ktx_rram_p30_reverse, pstKtxTostTopParam->ucRamReverse[30]);
    HV_W32_FIELD(TX_KTX_POST_TOP_A0, reg_ktx_rram_p31_reverse, pstKtxTostTopParam->ucRamReverse[31]);

    HV_W32_FIELD(TX_KTX_POST_TOP_00, reg_ktx_out_data_mode, pstKtxTostTopParam->ucOutDataMode);
    HV_W32_FIELD(TX_KTX_POST_TOP_80, reg_ktx_hs_filter, pstKtxTostTopParam->usHsFilter);
    return;
}

VOID Hv_Cal_Ktx_SetPifParam(HvKtxPIFCfgParam *pstKtxPIFParam)
{
    HV_LOG_DEBUG(PANEL, "############## Hv_Cal_Ktx_SetPifParam ##############");
#ifdef HV_SCALER_DEBUG_VERSION
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->uiPtgHsDly: %d", pstKtxPIFParam->uiPtgHsDly);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->ucPifInAfifoSizeMode: %d", pstKtxPIFParam->ucPifInAfifoSizeMode);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->ucTxgrp0PhyModeSel: %d", pstKtxPIFParam->ucTxgrp0PhyModeSel);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->usPifTg0PacketDhDenSta: %d", pstKtxPIFParam->usPifTg0PacketDhDenSta);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->usPifTg0PacketDhDenEnd: %d", pstKtxPIFParam->usPifTg0PacketDhDenEnd);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->usPifTg0PacketDvDenSta: %d", pstKtxPIFParam->usPifTg0PacketDvDenSta);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->usPifTg0PacketDvDenEnd: %d", pstKtxPIFParam->usPifTg0PacketDvDenEnd);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->ucTxgrp00PifConvMode: %d", pstKtxPIFParam->ucTxgrp00PifConvMode);
    HV_LOG_DEBUG(PANEL, "pstKtxPIFParam->ucTxgrp00PifTxW2rDly: %d", pstKtxPIFParam->ucTxgrp00PifTxW2rDly);
#endif
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_DEBUG_REG_0, reg_ptg_hs_dly, pstKtxPIFParam->uiPtgHsDly);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_3, reg_pif_in_afifo_size_mode, pstKtxPIFParam->ucPifInAfifoSizeMode);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_2, reg_txgrp_0_phy_mode_sel, pstKtxPIFParam->ucTxgrp0PhyModeSel);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_0, reg_pif_tg_0_packet_dh_den_sta, pstKtxPIFParam->usPifTg0PacketDhDenSta);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_0, reg_pif_tg_0_packet_dh_den_end, pstKtxPIFParam->usPifTg0PacketDhDenEnd);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_1, reg_pif_tg_0_packet_dv_den_sta, pstKtxPIFParam->usPifTg0PacketDvDenSta);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_1, reg_pif_tg_0_packet_dv_den_end, pstKtxPIFParam->usPifTg0PacketDvDenEnd);
    HV_W32_FIELD(TX_COMBOTX_PHY_3_TX_CTRL, reg_txgrp_00_pif_conv_mode, pstKtxPIFParam->ucTxgrp00PifConvMode);
    HV_W32_FIELD(TX_COMBOTX_PHY_3_TX_CTRL, reg_txgrp_00_pif_tx_w2r_dly, pstKtxPIFParam->ucTxgrp00PifTxW2rDly);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_3, reg_pif_tg_0_pkt_double_buffer_timer, pstKtxPIFParam->uiPifTg0PktDoubleBufferTimer);
    HV_W32_FIELD(TX_PIF_TX_TOP_18, reg_txgrp_00_dclk_div_num, pstKtxPIFParam->ucTxgrp00DclkDivNum);

    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_2, reg_txgrp_1_phy_mode_sel, pstKtxPIFParam->ucTxgrp0PhyModeSel);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_3, reg_pif_tg_1_pkt_double_buffer_timer, pstKtxPIFParam->uiPifTg0PktDoubleBufferTimer);

    return;
}

VOID Hv_Cal_Ktx_PifRst(BOOL bRst)
{
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_pif_0_rst_n, bRst);
    return;
}

VOID Hv_Cal_Ktx_TxMacRst(BOOL bRst)
{
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_rx_vbo_rst_n, bRst);
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_pif_edp_rst_n, bRst ? 3 : 0);
    return;
}

extern VOID Hv_Cal_Ktx_TxInit(USHORT16 usHval, USHORT16 usVval, UCHAR8 ucFrame);

VOID Hv_Cal_Ktx_BasicInit(const PanelParam *pstPanelParam)
{

    /* 10 - SH06_TOP */
    Hv_Cal_Ktx_PifRst(1);
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_ctrl_kcpr_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_ctrl_kod_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_rx_vbo_rst_n, 1);

    /* KTX_PRE_DBG */
    HV_W32_FIELD(TX_DISP_CTRL_TOP_00, reg_ktx_patt_pix_gate_en, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_00, reg_cursor_pix_gate_en, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_00, reg_frm_rate_det_pix_gate_en, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_00, reg_kcpr_apb_clk_en, 1);

    Hv_Cal_Ktx_TxInit(pstPanelParam->usPanelHactive, pstPanelParam->usPanelVactive, pstPanelParam->usPanelFrameRateMax);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_94, reg_ktx_top_patt_htotal, pstPanelParam->usPanelHtotalType);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_94, reg_ktx_top_patt_vtotal, pstPanelParam->usPanelVtotalType);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_98, reg_ktx_top_patt_hact, pstPanelParam->usPanelHactive);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_98, reg_ktx_top_patt_vact, pstPanelParam->usPanelVactive);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_9C, reg_ktx_top_patt_hs_width, pstPanelParam->ucPanelHsyncWidth);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_9C, reg_ktx_top_patt_vs_width, pstPanelParam->ucPanelVsyncWidth);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_A0, reg_ktx_top_patt_pre_de_vs_bporch, 0);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_9C, reg_ktx_top_patt_hs_bporch, pstPanelParam->ucPanelHsyncBackPorch);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_9C, reg_ktx_top_patt_vs_bporch, pstPanelParam->ucPanelVsyncBackPorch);

    /* 2D - tcon_top_1 */
    // HV_W32_FIELD(TX_DISP_CTRL_TOP_1_00, reg_ktx_pre_insert_pixel_swap, 0);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_14, reg_disp_ctrl_vs_mode, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_14, reg_disp_ctrl_vs_pos, 15);
    /* PIF_TX_TOP */
    HV_W32_FIELD(TX_PIF_TX_TOP_18, reg_txgrp_00_dclk_sel, TX_GRP_00_DCLK_SEL);
    // HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_TOP_REG_3, reg_pif_tg_0_pkt_double_buffer_en, 1);
    // HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_3, reg_pif_tg_1_pkt_double_buffer_en, 1);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_DEBUG_REG_0, reg_pif_afifo_wclr_disable, 1);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_DEBUG_REG_0, reg_pif_afifo_rclr_disable, 1);

    /* KTX_POST_TOP */
    HV_W32_FIELD(TX_KTX_POST_TOP_14, reg_ktx_vx1_hs_width, 8);

    /* display_ctrl top */
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_ktx_pre_proc_lod_bypass, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux0_sel, 0);
#if defined CONFIG_USER_DISPCTRL_DEMURA_ON
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux1_sel, 0);
#else
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux1_sel, 2);
#endif
#if defined CONFIG_USER_DISPCTRL_GAMMA_ON && defined CONFIG_USER_DISPCTRL_OD_ON
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux2_sel, 0);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux3_sel, 0);
#endif
#if defined CONFIG_USER_DISPCTRL_GAMMA_ON && !defined CONFIG_USER_DISPCTRL_OD_ON
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux2_sel, 0);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux3_sel, 1);
#endif
#if !defined CONFIG_USER_DISPCTRL_GAMMA_ON && defined CONFIG_USER_DISPCTRL_OD_ON
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux2_sel, 3);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux3_sel, 0);
#endif
#if !defined CONFIG_USER_DISPCTRL_GAMMA_ON && !defined CONFIG_USER_DISPCTRL_OD_ON
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux2_sel, 3);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux3_sel, 3);
#endif
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux4_sel, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux6_sel, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux7_sel, 3);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux5_sel, 1);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_mux8_sel, 1);
    /* reg_disp_ctrl_src_sel 0:DPU, 1:RX */
    HV_W32_FIELD(TX_DISP_CTRL_TOP_04, reg_disp_ctrl_src_sel, 0);

    HV_W32_FIELD(TX_DISP_CTRL_TOP_0C, reg_disp_ctrl_dummy_htotal, pstPanelParam->usPanelHtotalType);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_10, reg_disp_ctrl_vact, pstPanelParam->usPanelVactive);
    HV_W32_FIELD(TX_DISP_CTRL_TOP_10, reg_disp_ctrl_hact, pstPanelParam->usPanelHactive >> (TX_PPC - 1));
    HV_W32_FIELD(TX_DISP_CTRL_TOP_14, reg_disp_ctrl_vs_pos, 10);

    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_30, reg_ktx_in_hact, pstPanelParam->usPanelHactive >> (TX_PPC - 1));

    /* F0 - COMBOTX_PHY_0 */
    HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_ckref_sel, 1);
    return;
}

VOID Hv_Cal_Ktx_PifStart(BOOL bStart)
{
    HV_W32_FIELD(TX_COMBOTX_PHY_3_TX_CTRL, reg_txgrp_00_pif_tx_start, bStart);
    return;
}

VOID Hv_Cal_Ktx_SetPllParam(UINT32 uiIdx, HvKtxPllCfgParam *pstKtxPllParam)
{
    if (uiIdx == 0)
    {
        HV_W32_FIELD(TX_COMBOTX_PHY_0_04, reg_txpll_0_prediv, pstKtxPllParam->ucTxPllPreDiv);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_08, reg_txpll_0_fbdiv_int, pstKtxPllParam->usTxPllFbdivInt);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_0C, reg_txpll_0_postdiv0, pstKtxPllParam->usTxPllPostDiv0);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_10, reg_txpll_0_postdiv0_div2, pstKtxPllParam->ucTxPllPostDiv0Div2);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_0C, reg_txpll_0_postdiv1, pstKtxPllParam->usTxPllPostDiv1);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_10, reg_txpll_0_postdiv_lvds, pstKtxPllParam->ucTxPllPostDivLvds);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_10, reg_txpll_0_cklvds_en, pstKtxPllParam->ucTxPllClklvdsEn);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_10, reg_txpll_0_pif_div, pstKtxPllParam->ucTxPllPifDiv);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_10, reg_txpll_0_rd_div, pstKtxPllParam->ucTxPllRdDiv);
        HV_W32_FIELD(TX_COMBOTX_PHY_0_0C, reg_txpll_0_postdiv2, pstKtxPllParam->usTxPllPostDiv2);
    }
    else
    {
        HV_LOG_DEBUG(PANEL, "Hv_Cal_Ktx_SetPllParam uiIdx %d not adapter", uiIdx);
    }
    return;
}

VOID Hv_Cal_Ktx_PllReset(BOOL bRst)
{
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_rstn, !bRst);
    return;
}

VOID Hv_Cal_Ktx_PllEn(BOOL bEn)
{
    HV_W32_FIELD(TX_COMBOTX_PHY_0_00, reg_txpll_0_en, bEn);
    return;
}

VOID Hv_Cal_Ktx_TxPhyRdClkEn(USHORT16 usEn)
{
    HV_W32_FIELD(TX_PIF_TX_TOP_2C, reg_txphy_rd_clk_en, usEn ? 0xFFFF : 0);
    return;
}

VOID Hv_Cal_Ktx_PifLaneClkEn(BOOL bEn)
{
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_CLKGEN1, reg_pif_lane_clk_en, bEn ? 0x3F : 0);
    return;
}

VOID Hv_Cal_Ktx_PifPreClkEn(BOOL bEn)
{
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_CLKGEN1, reg_pif_pre_clk_en, bEn);
    return;
}

UCHAR8 Hv_Cal_Ktx_PllLockStatus(VOID)
{
    UCHAR8 ucVal = 0;
    HV_R32_DECL_VAR();
    ucVal = HV_R32_FIELD(TX_COMBOTX_PHY_0_D0, regr_txpll_0_lock_flag);

    return ucVal == 1 ? 1 : 0;
}

Status Hv_Cal_Ktx_SetKtxPatt(UCHAR8 ucKtxPattSwitch, UCHAR8 ucPatternMode)
{
    if (HV_TRUE == ucKtxPattSwitch)
    {
        HV_W32_FIELD(TX_DISP_CTRL_TOP_1_90, reg_ktx_top_patt_enable, 1);
        HV_W32_FIELD(TX_DISP_CTRL_TOP_1_90, reg_ktx_top_patt_slf_gen, 1);
    }
    else
    {
        HV_W32_FIELD(TX_DISP_CTRL_TOP_1_90, reg_ktx_top_patt_enable, 0);
        HV_W32_FIELD(TX_DISP_CTRL_TOP_1_90, reg_ktx_top_patt_slf_gen, 0);
    }
    
    HV_W32_FIELD(TX_DISP_CTRL_TOP_1_90, reg_ktx_top_patt_mode, ucPatternMode);
    return HV_SUCCESS;
}

static UINT32 KtxBitConvert(UCHAR8 ucValue)
{
    UINT32 uiNewVale = ucValue / 0xFF * 0x3FF;
    return uiNewVale;
}

Status Hv_Cal_Ktx_SetInpPattColor(UCHAR8 ucR, UCHAR8 ucG, UCHAR8 ucB)
{
    UINT32 uiInpColor = 0;
    UINT32 uiR = KtxBitConvert(ucR);
    UINT32 uiG = KtxBitConvert(ucG);
    UINT32 uiB = KtxBitConvert(ucB);

    // 判断是否超过0x3FF，如果超过则等于0x3FF
    uiR = (uiR > 0x3FF) ? 0x3FF : uiR;
    uiG = (uiG > 0x3FF) ? 0x3FF : uiG;
    uiB = (uiB > 0x3FF) ? 0x3FF : uiB;

    // 将各个部分的位赋给uiInpColor
    uiInpColor |= (uiR & 0xFF) << 0;        // 将uiR的0到7bit位赋给uiInpColor的0到7bit位
    uiInpColor |= ((uiR >> 8) & 0x3) << 24; // 将uiR的8到9bit赋值给uiInpColor的24到25bit位
    uiInpColor |= (uiG & 0xFF) << 8;        // 将uiG的0到7bit位赋给uiInpColor的8到15bit位
    uiInpColor |= ((uiG >> 8) & 0x3) << 26; // 将uiG的8到9bit赋值给uiInpColor的26到27bit位
    uiInpColor |= (uiB & 0xFF) << 16;       // 将uiB的0到7bit位赋给uiInpColor的16到23bit位
    uiInpColor |= ((uiB >> 8) & 0x3) << 28; // 将uiB的8到9bit赋值给uiInpColor的28到29bit位

    HV_W32_FIELD(RX_PTC_INP_PATT_TOP_00_00, reg_00_ptc_inp_patt_enable, 1);
    HV_W32_FIELD(RX_PTC_INP_PATT_TOP_00_04, reg_00_ptc_inp_patt_type_0, 0);     //raster
    HV_W32_FIELD(RX_PTC_INP_PATT_TOP_00_38, reg_00_ptc_inp_patt_loop_stop, 1);
    HV_W32_FIELD(RX_PTC_INP_PATT_TOP_00_38, reg_00_ptc_inp_patt_type0_clk_en, 1);
    HV_W32_FIELD(RX_PTC_INP_PATT_TOP_00_38, reg_00_ptc_inp_patt_type_new_clk_en, 1);
    HV_W32_FIELD(RX_PTC_INP_PATT_TOP_00_38, reg_00_ptc_inp_patt_loop_clk_en, 1);
    HV_W32_FIELD(RX_PTC_INP_PATT_TOP_00_08, reg_00_ptc_inp_patt_para_0, uiInpColor);
    return HV_SUCCESS;
}

VOID Hv_Cal_Ktx_SetTxPostCursroParam(UINT32 uiHpost, UINT32 uiVpost,UINT32 uiR, UINT32 uiG, UINT32 uiB)
{
    HV_W32_FIELD(TX_KTX_POST_TOP_84, reg_ktx_cursor_en, 1);
    HV_W32_FIELD(TX_KTX_POST_TOP_84, reg_ktx_cursor_h, uiHpost);
    HV_W32_FIELD(TX_KTX_POST_TOP_84, reg_ktx_cursor_v, uiVpost);
    HV_W32_FIELD(TX_KTX_POST_TOP_88, reg_ktx_cursor_color_r, uiR);
    HV_W32_FIELD(TX_KTX_POST_TOP_88, reg_ktx_cursor_color_g, uiG);
    HV_W32_FIELD(TX_KTX_POST_TOP_88, reg_ktx_cursor_color_b, uiB);
    return;
}

VOID Hv_Cal_Ktx_SetPanelState(USHORT16 usState)
{
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_1, reg_pif_tg_1_packet_dv_den_sta, usState);
    return;
}

VOID Hv_Cal_Ktx_SetPowerState(USHORT16 usState)
{
    HV_R32_DECL_VAR();
    /*bit0到bit3表示power状态，bit4到bit7表示开机原因*/
    USHORT16 usPowerState = HV_R32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_1, reg_pif_tg_1_packet_dv_den_end);
    usState = (usPowerState & 0xf0) | usState;
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_1, reg_pif_tg_1_packet_dv_den_end, usState);
    return;
}

VOID Hv_Cal_Ktx_SetPowerOnReason(USHORT16 usReason)
{
    HV_R32_DECL_VAR();
    USHORT16 usState = HV_R32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_1, reg_pif_tg_1_packet_dv_den_end);
    usReason = (usState & 0xf) | (usReason << 4);
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_1, reg_pif_tg_1_packet_dv_den_end, usReason);
    return;
}
