#ifndef _HV_PAGE_HT7315_DPU_DEC_VDM_TOP_00_H_
#define _HV_PAGE_HT7315_DPU_DEC_VDM_TOP_00_H_

#ifndef HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS
    #define HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS                                         0x11024100
#endif


#define DISP_TOP_DPU_DEC_VDM_TOP_00_00                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_00_struct                            rs_disp_top_dpu_dec_vdm_top_00_00

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_00  rs_disp_top_dpu_dec_vdm_top_00_00;
struct _rs_disp_top_dpu_dec_vdm_top_00_00 {
    unsigned int reg_00_dec_start_address0                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_00(val) ((rs_disp_top_dpu_dec_vdm_top_00_00*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_04                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_04_struct                            rs_disp_top_dpu_dec_vdm_top_00_04

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_04  rs_disp_top_dpu_dec_vdm_top_00_04;
struct _rs_disp_top_dpu_dec_vdm_top_00_04 {
    unsigned int reg_00_dec_start_address1                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_04(val) ((rs_disp_top_dpu_dec_vdm_top_00_04*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_08                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_08_struct                            rs_disp_top_dpu_dec_vdm_top_00_08

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_08  rs_disp_top_dpu_dec_vdm_top_00_08;
struct _rs_disp_top_dpu_dec_vdm_top_00_08 {
    unsigned int reg_00_dec_start_address2                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_08(val) ((rs_disp_top_dpu_dec_vdm_top_00_08*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_0C                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_0C_struct                            rs_disp_top_dpu_dec_vdm_top_00_0c

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_0c  rs_disp_top_dpu_dec_vdm_top_00_0c;
struct _rs_disp_top_dpu_dec_vdm_top_00_0c {
    unsigned int reg_00_dec_start_address3                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_0c(val) ((rs_disp_top_dpu_dec_vdm_top_00_0c*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_10                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_10_struct                            rs_disp_top_dpu_dec_vdm_top_00_10

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_10  rs_disp_top_dpu_dec_vdm_top_00_10;
struct _rs_disp_top_dpu_dec_vdm_top_00_10 {
    unsigned int reg_00_dec_start_address4                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_10(val) ((rs_disp_top_dpu_dec_vdm_top_00_10*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_14                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_14_struct                            rs_disp_top_dpu_dec_vdm_top_00_14

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_14  rs_disp_top_dpu_dec_vdm_top_00_14;
struct _rs_disp_top_dpu_dec_vdm_top_00_14 {
    unsigned int reg_00_dec_start_address5                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_14(val) ((rs_disp_top_dpu_dec_vdm_top_00_14*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_18                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x18)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_18_struct                            rs_disp_top_dpu_dec_vdm_top_00_18

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_18  rs_disp_top_dpu_dec_vdm_top_00_18;
struct _rs_disp_top_dpu_dec_vdm_top_00_18 {
    unsigned int reg_00_dec_start_address6                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_18(val) ((rs_disp_top_dpu_dec_vdm_top_00_18*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_1C                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x1C)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_1C_struct                            rs_disp_top_dpu_dec_vdm_top_00_1c

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_1c  rs_disp_top_dpu_dec_vdm_top_00_1c;
struct _rs_disp_top_dpu_dec_vdm_top_00_1c {
    unsigned int reg_00_dec_start_address7                  :32;
};
#define disp_top_dpu_dec_vdm_top_00_1c(val) ((rs_disp_top_dpu_dec_vdm_top_00_1c*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_20                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x20)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_20_struct                            rs_disp_top_dpu_dec_vdm_top_00_20

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_20  rs_disp_top_dpu_dec_vdm_top_00_20;
struct _rs_disp_top_dpu_dec_vdm_top_00_20 {
    unsigned int reg_00_dec_end_address0                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_20(val) ((rs_disp_top_dpu_dec_vdm_top_00_20*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_24                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x24)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_24_struct                            rs_disp_top_dpu_dec_vdm_top_00_24

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_24  rs_disp_top_dpu_dec_vdm_top_00_24;
struct _rs_disp_top_dpu_dec_vdm_top_00_24 {
    unsigned int reg_00_dec_end_address1                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_24(val) ((rs_disp_top_dpu_dec_vdm_top_00_24*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_28                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x28)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_28_struct                            rs_disp_top_dpu_dec_vdm_top_00_28

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_28  rs_disp_top_dpu_dec_vdm_top_00_28;
struct _rs_disp_top_dpu_dec_vdm_top_00_28 {
    unsigned int reg_00_dec_end_address2                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_28(val) ((rs_disp_top_dpu_dec_vdm_top_00_28*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_2C                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x2C)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_2C_struct                            rs_disp_top_dpu_dec_vdm_top_00_2c

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_2c  rs_disp_top_dpu_dec_vdm_top_00_2c;
struct _rs_disp_top_dpu_dec_vdm_top_00_2c {
    unsigned int reg_00_dec_end_address3                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_2c(val) ((rs_disp_top_dpu_dec_vdm_top_00_2c*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_30                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x30)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_30_struct                            rs_disp_top_dpu_dec_vdm_top_00_30

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_30  rs_disp_top_dpu_dec_vdm_top_00_30;
struct _rs_disp_top_dpu_dec_vdm_top_00_30 {
    unsigned int reg_00_dec_end_address4                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_30(val) ((rs_disp_top_dpu_dec_vdm_top_00_30*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_34                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x34)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_34_struct                            rs_disp_top_dpu_dec_vdm_top_00_34

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_34  rs_disp_top_dpu_dec_vdm_top_00_34;
struct _rs_disp_top_dpu_dec_vdm_top_00_34 {
    unsigned int reg_00_dec_end_address5                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_34(val) ((rs_disp_top_dpu_dec_vdm_top_00_34*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_38                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x38)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_38_struct                            rs_disp_top_dpu_dec_vdm_top_00_38

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_38  rs_disp_top_dpu_dec_vdm_top_00_38;
struct _rs_disp_top_dpu_dec_vdm_top_00_38 {
    unsigned int reg_00_dec_end_address6                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_38(val) ((rs_disp_top_dpu_dec_vdm_top_00_38*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_3C                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x3C)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_3C_struct                            rs_disp_top_dpu_dec_vdm_top_00_3c

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_3c  rs_disp_top_dpu_dec_vdm_top_00_3c;
struct _rs_disp_top_dpu_dec_vdm_top_00_3c {
    unsigned int reg_00_dec_end_address7                    :32;
};
#define disp_top_dpu_dec_vdm_top_00_3c(val) ((rs_disp_top_dpu_dec_vdm_top_00_3c*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_40                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x40)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_40_struct                            rs_disp_top_dpu_dec_vdm_top_00_40

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_40  rs_disp_top_dpu_dec_vdm_top_00_40;
struct _rs_disp_top_dpu_dec_vdm_top_00_40 {
    unsigned int reg_00_dec_line_offset_addr                :32;
};
#define disp_top_dpu_dec_vdm_top_00_40(val) ((rs_disp_top_dpu_dec_vdm_top_00_40*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_44                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x44)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_44_struct                            rs_disp_top_dpu_dec_vdm_top_00_44

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_44  rs_disp_top_dpu_dec_vdm_top_00_44;
struct _rs_disp_top_dpu_dec_vdm_top_00_44 {
    unsigned int reg_00_dec_alen                            : 8;
    unsigned int reg_00_dec_qos                             : 8;
    unsigned int reg_00_dec_cmdlen                          : 4;
    unsigned int reg_00_dec_read_enable                     : 1;
    unsigned int reg_00_dec_mode                            : 1;
    unsigned int reg_00_dec_disable_frame_hold              : 1;
    unsigned int reg_00_dec_read_err_clr                    : 1;
    unsigned int reg_00_en                                  : 1;
    unsigned int reg_00_en_no_latch                         : 1;
    unsigned int reg_00_dec_dynamic_crc_enable              : 1;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_dec_vdm_top_00_44(val) ((rs_disp_top_dpu_dec_vdm_top_00_44*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_48                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x48)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_48_struct                            rs_disp_top_dpu_dec_vdm_top_00_48

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_48  rs_disp_top_dpu_dec_vdm_top_00_48;
struct _rs_disp_top_dpu_dec_vdm_top_00_48 {
    unsigned int reg_00_dec_threshold_m                     : 9;
    unsigned int reg_00_dec_threshold_n                     : 9;
    unsigned int reserved                                   :14;
};
#define disp_top_dpu_dec_vdm_top_00_48(val) ((rs_disp_top_dpu_dec_vdm_top_00_48*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_4C                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x4C)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_4C_struct                            rs_disp_top_dpu_dec_vdm_top_00_4c

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_4c  rs_disp_top_dpu_dec_vdm_top_00_4c;
struct _rs_disp_top_dpu_dec_vdm_top_00_4c {
    unsigned int reg_00_dec_vtotal                          :12;
    unsigned int reg_00_dec_vflip_enable                    : 1;
    unsigned int reg_00_dec_mode422_enable                  : 1;
    unsigned int reg_00_dec_4k_proc_enable                  : 1;
    unsigned int reg_00_dec_cmdlength_enable                : 1;
    unsigned int reg_00_dec_sram_ls_en                      : 1;
    unsigned int reg_00_dec_sram_ls_value                   : 1;
    unsigned int reserved                                   :14;
};
#define disp_top_dpu_dec_vdm_top_00_4c(val) ((rs_disp_top_dpu_dec_vdm_top_00_4c*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_50                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x50)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_50_struct                            rs_disp_top_dpu_dec_vdm_top_00_50

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_50  rs_disp_top_dpu_dec_vdm_top_00_50;
struct _rs_disp_top_dpu_dec_vdm_top_00_50 {
    unsigned int reg_00_dec_dm_frmbuf_num                   : 4;
    unsigned int reg_00_dec_dm_frmbuf_gap                   : 4;
    unsigned int reg_00_dec_dm_frmbuf_mode                  : 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dec_dm_frmbuf_hold_en               : 1;
    unsigned int reg_00_dec_dm_frmbuf_hold_idx              : 3;
    unsigned int reserved_1                                 :12;
};
#define disp_top_dpu_dec_vdm_top_00_50(val) ((rs_disp_top_dpu_dec_vdm_top_00_50*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_54                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x54)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_54_struct                            rs_disp_top_dpu_dec_vdm_top_00_54

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_54  rs_disp_top_dpu_dec_vdm_top_00_54;
struct _rs_disp_top_dpu_dec_vdm_top_00_54 {
    unsigned int mem_reg_00_0                               : 8;
    unsigned int mem_reg_00_1                               : 8;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_dec_vdm_top_00_54(val) ((rs_disp_top_dpu_dec_vdm_top_00_54*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_58                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0x58)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_58_struct                            rs_disp_top_dpu_dec_vdm_top_00_58

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_58  rs_disp_top_dpu_dec_vdm_top_00_58;
struct _rs_disp_top_dpu_dec_vdm_top_00_58 {
    unsigned int reg_00_mem_ema_0                           :16;
    unsigned int reg_00_mem_ema_1                           :16;
};
#define disp_top_dpu_dec_vdm_top_00_58(val) ((rs_disp_top_dpu_dec_vdm_top_00_58*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_F0                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0xF0)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_F0_struct                            rs_disp_top_dpu_dec_vdm_top_00_f0

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_f0  rs_disp_top_dpu_dec_vdm_top_00_f0;
struct _rs_disp_top_dpu_dec_vdm_top_00_f0 {
    unsigned int reg_00_mem_ro_0                            : 4;
    unsigned int reg_00_mem_ro_1                            : 4;
    unsigned int reserved                                   :24;
};
#define disp_top_dpu_dec_vdm_top_00_f0(val) ((rs_disp_top_dpu_dec_vdm_top_00_f0*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_F4                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0xF4)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_F4_struct                            rs_disp_top_dpu_dec_vdm_top_00_f4

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_f4  rs_disp_top_dpu_dec_vdm_top_00_f4;
struct _rs_disp_top_dpu_dec_vdm_top_00_f4 {
    unsigned int reg_00_dec_dynamic_crc_out_h               :32;
};
#define disp_top_dpu_dec_vdm_top_00_f4(val) ((rs_disp_top_dpu_dec_vdm_top_00_f4*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_F8                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0xF8)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_F8_struct                            rs_disp_top_dpu_dec_vdm_top_00_f8

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_f8  rs_disp_top_dpu_dec_vdm_top_00_f8;
struct _rs_disp_top_dpu_dec_vdm_top_00_f8 {
    unsigned int reg_00_dec_dynamic_crc_out_l               :32;
};
#define disp_top_dpu_dec_vdm_top_00_f8(val) ((rs_disp_top_dpu_dec_vdm_top_00_f8*)&(val))



#define DISP_TOP_DPU_DEC_VDM_TOP_00_FC                                   (HV_DPU_DEC_VDM_TOP_00_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_DEC_VDM_TOP_00_FC_struct                            rs_disp_top_dpu_dec_vdm_top_00_fc

typedef struct _rs_disp_top_dpu_dec_vdm_top_00_fc  rs_disp_top_dpu_dec_vdm_top_00_fc;
struct _rs_disp_top_dpu_dec_vdm_top_00_fc {
    unsigned int regr_00_dec_dm_headerfail                  : 1;
    unsigned int regr_00_dec_dm_fail                        : 1;
    unsigned int regr_00_dec_dm_dec_fetch_err               : 6;
    unsigned int reg_00_dec_dynamic_crc_fail                : 1;
    unsigned int reserved                                   :23;
};
#define disp_top_dpu_dec_vdm_top_00_fc(val) ((rs_disp_top_dpu_dec_vdm_top_00_fc*)&(val))



#endif