#ifndef _HV_PAGE_HT7315_HDMI21_RX_SCDC_01_H_
#define _HV_PAGE_HT7315_HDMI21_RX_SCDC_01_H_

#ifndef HV_HDMI21_RX_SCDC_01_BASE_ADDRESS
    #define HV_HDMI21_RX_SCDC_01_BASE_ADDRESS                                         0x1104E000
#endif


#define RX_HDMI21_RX_SCDC_01_00                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX_SCDC_01_00_struct                                   rs_rx_hdmi21_rx_scdc_01_00

typedef struct _rs_rx_hdmi21_rx_scdc_01_00  rs_rx_hdmi21_rx_scdc_01_00;
struct _rs_rx_hdmi21_rx_scdc_01_00 {
    unsigned int reg_01_SCRAMBEN_SEL                        : 2;
    unsigned int reserved                                   : 2;
    unsigned int reg_01_SCDC_ENABLE                         : 1;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_01_CTRLCHECKEN                         : 1;
    unsigned int reg_01_PREAMBCHECKEN                       : 1;
    unsigned int reg_01_GBCHECKEN                           : 1;
    unsigned int reg_01_DATAISCHECKEN                       : 1;
    unsigned int reg_01_VIDDATACHECKEN                      : 1;
    unsigned int reg_01_hd21rx_check_vld_sel                : 1;
    unsigned int reserved_2                                 :18;
};
#define rx_hdmi21_rx_scdc_01_00(val) ((rs_rx_hdmi21_rx_scdc_01_00*)&(val))



#define RX_HDMI21_RX_SCDC_01_04                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX_SCDC_01_04_struct                                   rs_rx_hdmi21_rx_scdc_01_04

typedef struct _rs_rx_hdmi21_rx_scdc_01_04  rs_rx_hdmi21_rx_scdc_01_04;
struct _rs_rx_hdmi21_rx_scdc_01_04 {
    unsigned int reg_01_I2CTIMOUTCNT                        :20;
    unsigned int reg_01_2CTIMOUTEN                          : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_I2CSPIKESUPPR                       : 2;
    unsigned int reserved_1                                 : 6;
};
#define rx_hdmi21_rx_scdc_01_04(val) ((rs_rx_hdmi21_rx_scdc_01_04*)&(val))



#define RX_HDMI21_RX_SCDC_01_08                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX_SCDC_01_08_struct                                   rs_rx_hdmi21_rx_scdc_01_08

typedef struct _rs_rx_hdmi21_rx_scdc_01_08  rs_rx_hdmi21_rx_scdc_01_08;
struct _rs_rx_hdmi21_rx_scdc_01_08 {
    unsigned int reg_01_POWERPROVIDED                       : 1;
    unsigned int reg_01_HPDLOW                              : 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_01_RR_IFFLAGS_ALREADYSET               : 1;
    unsigned int reserved_1                                 :27;
};
#define rx_hdmi21_rx_scdc_01_08(val) ((rs_rx_hdmi21_rx_scdc_01_08*)&(val))



#define RX_HDMI21_RX_SCDC_01_0C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x0C)

#define RX_HDMI21_RX_SCDC_01_0C_struct                                   rs_rx_hdmi21_rx_scdc_01_0c

typedef struct _rs_rx_hdmi21_rx_scdc_01_0c  rs_rx_hdmi21_rx_scdc_01_0c;
struct _rs_rx_hdmi21_rx_scdc_01_0c {
    unsigned int reg_01_MILISECTIMERLIMIT                   :16;
    unsigned int reg_01_hd_rx_scdc_errdet_clr               : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_CHLOCKMAXER                         :10;
    unsigned int reserved_1                                 : 2;
};
#define rx_hdmi21_rx_scdc_01_0c(val) ((rs_rx_hdmi21_rx_scdc_01_0c*)&(val))



#define RX_HDMI21_RX_SCDC_01_10                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x10)

#define RX_HDMI21_RX_SCDC_01_10_struct                                   rs_rx_hdmi21_rx_scdc_01_10

typedef struct _rs_rx_hdmi21_rx_scdc_01_10  rs_rx_hdmi21_rx_scdc_01_10;
struct _rs_rx_hdmi21_rx_scdc_01_10 {
    unsigned int regr_01_SCDC_SOURCEREVISION                : 8;
    unsigned int regr_01_SCDC_STATUSUPDATE                  : 1;
    unsigned int regr_01_SCDC_CEDUPDATE                     : 1;
    unsigned int regr_01_SCDC_RRTEST                        : 1;
    unsigned int regr_01_scdc_source_test_update            : 1;
    unsigned int regr_01_scdc_frl_start                     : 1;
    unsigned int regr_01_scdc_flt_update                    : 1;
    unsigned int regr_01_scdc_rsed_update                   : 1;
    unsigned int reserved                                   : 1;
    unsigned int regr_01_SCDC_SCRAMBEN                      : 1;
    unsigned int regr_01_SCDC_TMDSBITCLKRATIO               : 1;
    unsigned int reserved_1                                 : 6;
    unsigned int regr_01_SCDC_SCRAMBSTATUS                  : 1;
    unsigned int reserved_2                                 : 7;
};
#define rx_hdmi21_rx_scdc_01_10(val) ((rs_rx_hdmi21_rx_scdc_01_10*)&(val))



#define RX_HDMI21_RX_SCDC_01_14                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x14)

#define RX_HDMI21_RX_SCDC_01_14_struct                                   rs_rx_hdmi21_rx_scdc_01_14

typedef struct _rs_rx_hdmi21_rx_scdc_01_14  rs_rx_hdmi21_rx_scdc_01_14;
struct _rs_rx_hdmi21_rx_scdc_01_14 {
    unsigned int regr_01_SCDC_RRENABLE                      : 1;
    unsigned int regr_01_hd21rx_flt_no_retrain              : 1;
    unsigned int regr_01_scdc_frl_rate                      : 4;
    unsigned int regr_01_scdc_ffe_levels                    : 4;
    unsigned int regr_01_SCDC_CLOCKDETECTED                 : 1;
    unsigned int regr_01_SCDC_CH0LOCKED                     : 1;
    unsigned int regr_01_SCDC_CH1LOCKED                     : 1;
    unsigned int regr_01_SCDC_CH2LOCKED                     : 1;
    unsigned int reserved                                   : 2;
    unsigned int regr_01_SCDC_ERRDET0                       :15;
    unsigned int regr_01_SCDC_ERRDET0_VALID                 : 1;
};
#define rx_hdmi21_rx_scdc_01_14(val) ((rs_rx_hdmi21_rx_scdc_01_14*)&(val))



#define RX_HDMI21_RX_SCDC_01_18                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX_SCDC_01_18_struct                                   rs_rx_hdmi21_rx_scdc_01_18

typedef struct _rs_rx_hdmi21_rx_scdc_01_18  rs_rx_hdmi21_rx_scdc_01_18;
struct _rs_rx_hdmi21_rx_scdc_01_18 {
    unsigned int regr_01_SCDC_ERRDET1                       :15;
    unsigned int regr_01_SCDC_ERRDET1_VALID                 : 1;
    unsigned int regr_01_SCDC_ERRDET2                       :15;
    unsigned int regr_01_SCDC_ERRDET2_VALID                 : 1;
};
#define rx_hdmi21_rx_scdc_01_18(val) ((rs_rx_hdmi21_rx_scdc_01_18*)&(val))



#define RX_HDMI21_RX_SCDC_01_1C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX_SCDC_01_1C_struct                                   rs_rx_hdmi21_rx_scdc_01_1c

typedef struct _rs_rx_hdmi21_rx_scdc_01_1c  rs_rx_hdmi21_rx_scdc_01_1c;
struct _rs_rx_hdmi21_rx_scdc_01_1c {
    unsigned int regr_01_SCDC_ERRDET3                       :15;
    unsigned int regr_01_SCDC_ERRDET3_VALID                 : 1;
    unsigned int regr_01_SCDC_RS_ERRCNT                     :15;
    unsigned int regr_01_SCDC_RS_VALID                      : 1;
};
#define rx_hdmi21_rx_scdc_01_1c(val) ((rs_rx_hdmi21_rx_scdc_01_1c*)&(val))



#define RX_HDMI21_RX_SCDC_01_20                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x20)

#define RX_HDMI21_RX_SCDC_01_20_struct                                   rs_rx_hdmi21_rx_scdc_01_20

typedef struct _rs_rx_hdmi21_rx_scdc_01_20  rs_rx_hdmi21_rx_scdc_01_20;
struct _rs_rx_hdmi21_rx_scdc_01_20 {
    unsigned int regr_01_MANUFACTURSPECIFICWR0              :32;
};
#define rx_hdmi21_rx_scdc_01_20(val) ((rs_rx_hdmi21_rx_scdc_01_20*)&(val))



#define RX_HDMI21_RX_SCDC_01_24                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x24)

#define RX_HDMI21_RX_SCDC_01_24_struct                                   rs_rx_hdmi21_rx_scdc_01_24

typedef struct _rs_rx_hdmi21_rx_scdc_01_24  rs_rx_hdmi21_rx_scdc_01_24;
struct _rs_rx_hdmi21_rx_scdc_01_24 {
    unsigned int regr_01_MANUFACTURSPECIFICWR1              :32;
};
#define rx_hdmi21_rx_scdc_01_24(val) ((rs_rx_hdmi21_rx_scdc_01_24*)&(val))



#define RX_HDMI21_RX_SCDC_01_28                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x28)

#define RX_HDMI21_RX_SCDC_01_28_struct                                   rs_rx_hdmi21_rx_scdc_01_28

typedef struct _rs_rx_hdmi21_rx_scdc_01_28  rs_rx_hdmi21_rx_scdc_01_28;
struct _rs_rx_hdmi21_rx_scdc_01_28 {
    unsigned int regr_01_MANUFACTURSPECIFICWR2              :32;
};
#define rx_hdmi21_rx_scdc_01_28(val) ((rs_rx_hdmi21_rx_scdc_01_28*)&(val))



#define RX_HDMI21_RX_SCDC_01_2C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x2C)

#define RX_HDMI21_RX_SCDC_01_2C_struct                                   rs_rx_hdmi21_rx_scdc_01_2c

typedef struct _rs_rx_hdmi21_rx_scdc_01_2c  rs_rx_hdmi21_rx_scdc_01_2c;
struct _rs_rx_hdmi21_rx_scdc_01_2c {
    unsigned int regr_01_MANUFACTURSPECIFICWR3              :32;
};
#define rx_hdmi21_rx_scdc_01_2c(val) ((rs_rx_hdmi21_rx_scdc_01_2c*)&(val))



#define RX_HDMI21_RX_SCDC_01_30                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x30)

#define RX_HDMI21_RX_SCDC_01_30_struct                                   rs_rx_hdmi21_rx_scdc_01_30

typedef struct _rs_rx_hdmi21_rx_scdc_01_30  rs_rx_hdmi21_rx_scdc_01_30;
struct _rs_rx_hdmi21_rx_scdc_01_30 {
    unsigned int regr_01_MANUFACTURSPECIFICWR4              :16;
    unsigned int regr_01_SCDC_TESTREADREQDELAY              : 7;
    unsigned int regr_01_SCDC_TESTREADREQ                   : 1;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_scdc_01_30(val) ((rs_rx_hdmi21_rx_scdc_01_30*)&(val))



#define RX_HDMI21_RX_SCDC_01_34                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX_SCDC_01_34_struct                                   rs_rx_hdmi21_rx_scdc_01_34

typedef struct _rs_rx_hdmi21_rx_scdc_01_34  rs_rx_hdmi21_rx_scdc_01_34;
struct _rs_rx_hdmi21_rx_scdc_01_34 {
    unsigned int reg_01_SINKVERSION                         : 8;
    unsigned int reg_01_MANUFACTUREROUI                     :24;
};
#define rx_hdmi21_rx_scdc_01_34(val) ((rs_rx_hdmi21_rx_scdc_01_34*)&(val))



#define RX_HDMI21_RX_SCDC_01_38                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX_SCDC_01_38_struct                                   rs_rx_hdmi21_rx_scdc_01_38

typedef struct _rs_rx_hdmi21_rx_scdc_01_38  rs_rx_hdmi21_rx_scdc_01_38;
struct _rs_rx_hdmi21_rx_scdc_01_38 {
    unsigned int reg_01_DEVICEID_STRING0                    :32;
};
#define rx_hdmi21_rx_scdc_01_38(val) ((rs_rx_hdmi21_rx_scdc_01_38*)&(val))



#define RX_HDMI21_RX_SCDC_01_3C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX_SCDC_01_3C_struct                                   rs_rx_hdmi21_rx_scdc_01_3c

typedef struct _rs_rx_hdmi21_rx_scdc_01_3c  rs_rx_hdmi21_rx_scdc_01_3c;
struct _rs_rx_hdmi21_rx_scdc_01_3c {
    unsigned int reg_01_DEVICEID_STRING1                    :32;
};
#define rx_hdmi21_rx_scdc_01_3c(val) ((rs_rx_hdmi21_rx_scdc_01_3c*)&(val))



#define RX_HDMI21_RX_SCDC_01_40                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x40)

#define RX_HDMI21_RX_SCDC_01_40_struct                                   rs_rx_hdmi21_rx_scdc_01_40

typedef struct _rs_rx_hdmi21_rx_scdc_01_40  rs_rx_hdmi21_rx_scdc_01_40;
struct _rs_rx_hdmi21_rx_scdc_01_40 {
    unsigned int reg_01_DEVICEID_MINORREV                   : 4;
    unsigned int reg_01_DEVICEID_MAJORREV                   : 4;
    unsigned int reg_01_DEVICEID_SWMAJORREV                 : 8;
    unsigned int reg_01_DEVICEID_SWMINORREV                 : 8;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_scdc_01_40(val) ((rs_rx_hdmi21_rx_scdc_01_40*)&(val))



#define RX_HDMI21_RX_SCDC_01_44                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x44)

#define RX_HDMI21_RX_SCDC_01_44_struct                                   rs_rx_hdmi21_rx_scdc_01_44

typedef struct _rs_rx_hdmi21_rx_scdc_01_44  rs_rx_hdmi21_rx_scdc_01_44;
struct _rs_rx_hdmi21_rx_scdc_01_44 {
    unsigned int reg_01_MANUFACTURSPECIFIC0                 :32;
};
#define rx_hdmi21_rx_scdc_01_44(val) ((rs_rx_hdmi21_rx_scdc_01_44*)&(val))



#define RX_HDMI21_RX_SCDC_01_48                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x48)

#define RX_HDMI21_RX_SCDC_01_48_struct                                   rs_rx_hdmi21_rx_scdc_01_48

typedef struct _rs_rx_hdmi21_rx_scdc_01_48  rs_rx_hdmi21_rx_scdc_01_48;
struct _rs_rx_hdmi21_rx_scdc_01_48 {
    unsigned int reg_01_MANUFACTURSPECIFIC1                 :32;
};
#define rx_hdmi21_rx_scdc_01_48(val) ((rs_rx_hdmi21_rx_scdc_01_48*)&(val))



#define RX_HDMI21_RX_SCDC_01_4C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x4C)

#define RX_HDMI21_RX_SCDC_01_4C_struct                                   rs_rx_hdmi21_rx_scdc_01_4c

typedef struct _rs_rx_hdmi21_rx_scdc_01_4c  rs_rx_hdmi21_rx_scdc_01_4c;
struct _rs_rx_hdmi21_rx_scdc_01_4c {
    unsigned int reg_01_MANUFACTURSPECIFIC2                 :32;
};
#define rx_hdmi21_rx_scdc_01_4c(val) ((rs_rx_hdmi21_rx_scdc_01_4c*)&(val))



#define RX_HDMI21_RX_SCDC_01_50                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x50)

#define RX_HDMI21_RX_SCDC_01_50_struct                                   rs_rx_hdmi21_rx_scdc_01_50

typedef struct _rs_rx_hdmi21_rx_scdc_01_50  rs_rx_hdmi21_rx_scdc_01_50;
struct _rs_rx_hdmi21_rx_scdc_01_50 {
    unsigned int reg_01_MANUFACTURSPECIFIC3                 :32;
};
#define rx_hdmi21_rx_scdc_01_50(val) ((rs_rx_hdmi21_rx_scdc_01_50*)&(val))



#define RX_HDMI21_RX_SCDC_01_54                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x54)

#define RX_HDMI21_RX_SCDC_01_54_struct                                   rs_rx_hdmi21_rx_scdc_01_54

typedef struct _rs_rx_hdmi21_rx_scdc_01_54  rs_rx_hdmi21_rx_scdc_01_54;
struct _rs_rx_hdmi21_rx_scdc_01_54 {
    unsigned int regr_01_SCRAMBDET                          : 1;
    unsigned int reserved                                   :31;
};
#define rx_hdmi21_rx_scdc_01_54(val) ((rs_rx_hdmi21_rx_scdc_01_54*)&(val))



#define RX_HDMI21_RX_SCDC_01_58                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x58)

#define RX_HDMI21_RX_SCDC_01_58_struct                                   rs_rx_hdmi21_rx_scdc_01_58

typedef struct _rs_rx_hdmi21_rx_scdc_01_58  rs_rx_hdmi21_rx_scdc_01_58;
struct _rs_rx_hdmi21_rx_scdc_01_58 {
    unsigned int reserved                                   : 2;
    unsigned int reg_01_hd21rx_ffe_pre_shoot_only           : 1;
    unsigned int reg_01_hd21rx_ffe_de_emphasis_only         : 1;
    unsigned int reg_01_hd21rx_ffe_no_ffe                   : 1;
    unsigned int reg_01_hd21rx_flt_no_timeout               : 1;
    unsigned int reg_01_hd21rx_dsc_frl_max                  : 1;
    unsigned int reg_01_hd21rx_frl_max                      : 1;
    unsigned int reg_01_hd21rx_frl_mode_on                  : 1;
    unsigned int reg_01_hd21rx_flt_ready                    : 1;
    unsigned int reg_01_hd21rx_flt_update_swset             : 1;
    unsigned int reg_01_hd21rx_frl_start_swset              : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int regr_01_hd21rx_daisy_err                   : 1;
    unsigned int regr_01_hd21rx_mono_dir_on                 : 1;
    unsigned int regr_01_hd21rx_mono_dir_err                : 1;
    unsigned int regr_01_hd21rx_ca_pwr_err                  : 1;
    unsigned int reg_01_hd21rx_cable_status                 : 1;
    unsigned int reserved_2                                 :14;
};
#define rx_hdmi21_rx_scdc_01_58(val) ((rs_rx_hdmi21_rx_scdc_01_58*)&(val))



#define RX_HDMI21_RX_SCDC_01_5C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x5C)

#define RX_HDMI21_RX_SCDC_01_5C_struct                                   rs_rx_hdmi21_rx_scdc_01_5c

typedef struct _rs_rx_hdmi21_rx_scdc_01_5c  rs_rx_hdmi21_rx_scdc_01_5c;
struct _rs_rx_hdmi21_rx_scdc_01_5c {
    unsigned int regr_01_hd21rx_scdc_offset10               : 8;
    unsigned int regr_01_hd21rx_scdc_offset31               : 8;
    unsigned int regr_01_hd21rx_scdc_offset40               : 8;
    unsigned int regr_01_hd21rx_scdc_offset41               : 8;
};
#define rx_hdmi21_rx_scdc_01_5c(val) ((rs_rx_hdmi21_rx_scdc_01_5c*)&(val))



#define RX_HDMI21_RX_SCDC_01_60                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x60)

#define RX_HDMI21_RX_SCDC_01_60_struct                                   rs_rx_hdmi21_rx_scdc_01_60

typedef struct _rs_rx_hdmi21_rx_scdc_01_60  rs_rx_hdmi21_rx_scdc_01_60;
struct _rs_rx_hdmi21_rx_scdc_01_60 {
    unsigned int regr_01_hd21rx_scdc_offset42               : 8;
    unsigned int regr_01_i2c_h2_h14_sel                     : 1;
    unsigned int regr_01_i2c_short_upd_rd                   : 1;
    unsigned int regr_01_ddc_rcurstate                      : 4;
    unsigned int reserved                                   :18;
};
#define rx_hdmi21_rx_scdc_01_60(val) ((rs_rx_hdmi21_rx_scdc_01_60*)&(val))



#define RX_HDMI21_RX_SCDC_01_6C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x6C)

#define RX_HDMI21_RX_SCDC_01_6C_struct                                   rs_rx_hdmi21_rx_scdc_01_6c

typedef struct _rs_rx_hdmi21_rx_scdc_01_6c  rs_rx_hdmi21_rx_scdc_01_6c;
struct _rs_rx_hdmi21_rx_scdc_01_6c {
    unsigned int reg_01_frl_start_time_th                   :16;
    unsigned int reg_01_frl_start_chk_gap                   : 1;
    unsigned int reg_01_frl_start_chk_blk                   : 1;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx_scdc_01_6c(val) ((rs_rx_hdmi21_rx_scdc_01_6c*)&(val))



#define RX_HDMI21_RX_SCDC_01_70                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x70)

#define RX_HDMI21_RX_SCDC_01_70_struct                                   rs_rx_hdmi21_rx_scdc_01_70

typedef struct _rs_rx_hdmi21_rx_scdc_01_70  rs_rx_hdmi21_rx_scdc_01_70;
struct _rs_rx_hdmi21_rx_scdc_01_70 {
    unsigned int reg_01_ED_MILISECTIMERLIMIT                :19;
    unsigned int reserved                                   :13;
};
#define rx_hdmi21_rx_scdc_01_70(val) ((rs_rx_hdmi21_rx_scdc_01_70*)&(val))



#define RX_HDMI21_RX_SCDC_01_74                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x74)

#define RX_HDMI21_RX_SCDC_01_74_struct                                   rs_rx_hdmi21_rx_scdc_01_74

typedef struct _rs_rx_hdmi21_rx_scdc_01_74  rs_rx_hdmi21_rx_scdc_01_74;
struct _rs_rx_hdmi21_rx_scdc_01_74 {
    unsigned int reg_01_err_cnt_update_mode                 : 1;
    unsigned int reg_01_err_cnt_sw_mode                     : 1;
    unsigned int reg_01_cedupd_sw                           : 1;
    unsigned int reg_01_rsedupd_sw                          : 1;
    unsigned int reg_01_err0_cnt_sw                         :16;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_scdc_01_74(val) ((rs_rx_hdmi21_rx_scdc_01_74*)&(val))



#define RX_HDMI21_RX_SCDC_01_78                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x78)

#define RX_HDMI21_RX_SCDC_01_78_struct                                   rs_rx_hdmi21_rx_scdc_01_78

typedef struct _rs_rx_hdmi21_rx_scdc_01_78  rs_rx_hdmi21_rx_scdc_01_78;
struct _rs_rx_hdmi21_rx_scdc_01_78 {
    unsigned int reg_01_err1_cnt_sw                         :16;
    unsigned int reg_01_err2_cnt_sw                         :16;
};
#define rx_hdmi21_rx_scdc_01_78(val) ((rs_rx_hdmi21_rx_scdc_01_78*)&(val))



#define RX_HDMI21_RX_SCDC_01_7C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x7C)

#define RX_HDMI21_RX_SCDC_01_7C_struct                                   rs_rx_hdmi21_rx_scdc_01_7c

typedef struct _rs_rx_hdmi21_rx_scdc_01_7c  rs_rx_hdmi21_rx_scdc_01_7c;
struct _rs_rx_hdmi21_rx_scdc_01_7c {
    unsigned int reg_01_err3_cnt_sw                         :16;
    unsigned int reg_01_rserr_cnt_sw                        :16;
};
#define rx_hdmi21_rx_scdc_01_7c(val) ((rs_rx_hdmi21_rx_scdc_01_7c*)&(val))



#define RX_HDMI21_RX_SCDC_01_80                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x80)

#define RX_HDMI21_RX_SCDC_01_80_struct                                   rs_rx_hdmi21_rx_scdc_01_80

typedef struct _rs_rx_hdmi21_rx_scdc_01_80  rs_rx_hdmi21_rx_scdc_01_80;
struct _rs_rx_hdmi21_rx_scdc_01_80 {
    unsigned int reg_01_rstatus_sw_mode                     : 1;
    unsigned int reg_01_ln0_locked_sw                       : 1;
    unsigned int reg_01_ln1_locked_sw                       : 1;
    unsigned int reg_01_ln2_locked_sw                       : 1;
    unsigned int reg_01_ln3_locked_sw                       : 1;
    unsigned int reg_01_clock_det_sw                        : 1;
    unsigned int reg_01_dsc_decoderfail_sw                  : 1;
    unsigned int reg_01_rstatus12_sw_mode                   : 1;
    unsigned int reg_01_ln0_ltp_req_sw                      : 4;
    unsigned int reg_01_ln1_ltp_req_sw                      : 4;
    unsigned int reg_01_ln2_ltp_req_sw                      : 4;
    unsigned int reg_01_ln3_ltp_req_sw                      : 4;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_scdc_01_80(val) ((rs_rx_hdmi21_rx_scdc_01_80*)&(val))



#define RX_HDMI21_RX_SCDC_01_88                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x88)

#define RX_HDMI21_RX_SCDC_01_88_struct                                   rs_rx_hdmi21_rx_scdc_01_88

typedef struct _rs_rx_hdmi21_rx_scdc_01_88  rs_rx_hdmi21_rx_scdc_01_88;
struct _rs_rx_hdmi21_rx_scdc_01_88 {
    unsigned int reg_01_errcnt_rd_timer_cnt                 :18;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx_scdc_01_88(val) ((rs_rx_hdmi21_rx_scdc_01_88*)&(val))



#define RX_HDMI21_RX_SCDC_01_8C                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0x8C)

#define RX_HDMI21_RX_SCDC_01_8C_struct                                   rs_rx_hdmi21_rx_scdc_01_8c

typedef struct _rs_rx_hdmi21_rx_scdc_01_8c  rs_rx_hdmi21_rx_scdc_01_8c;
struct _rs_rx_hdmi21_rx_scdc_01_8c {
    unsigned int reg_01_flt_update_hwset_cnt_clr            : 1;
    unsigned int reserved                                   : 3;
    unsigned int regr_01_flt_update_hwset_cnt               : 4;
    unsigned int reserved_1                                 :24;
};
#define rx_hdmi21_rx_scdc_01_8c(val) ((rs_rx_hdmi21_rx_scdc_01_8c*)&(val))



#define RX_HDMI21_RX_SCDC_01_A0                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0xA0)

#define RX_HDMI21_RX_SCDC_01_A0_struct                                   rs_rx_hdmi21_rx_scdc_01_a0

typedef struct _rs_rx_hdmi21_rx_scdc_01_a0  rs_rx_hdmi21_rx_scdc_01_a0;
struct _rs_rx_hdmi21_rx_scdc_01_a0 {
    unsigned int reserved                                   : 1;
    unsigned int reg_01_MODET_SWRESET                       : 1;
    unsigned int reg_01_HDMI_SWRESET                        : 1;
    unsigned int reg_01_BUS_SWRESET                         : 1;
    unsigned int reg_01_AUD_SWRESET                         : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_01_PIXEL_SWRESET                       : 1;
    unsigned int reg_01_VID_SWRESET                         : 1;
    unsigned int reg_01_SCDC_SWRESET                        : 1;
    unsigned int reg_01_CFG_SWRESET                         : 1;
    unsigned int reg_01_LTP_SWRESET                         : 1;
    unsigned int reserved_2                                 : 5;
    unsigned int reg_01_TMDS_SWRESET                        : 1;
    unsigned int reg_01_hd_mac_dbg_mux                      : 4;
    unsigned int reserved_3                                 :11;
};
#define rx_hdmi21_rx_scdc_01_a0(val) ((rs_rx_hdmi21_rx_scdc_01_a0*)&(val))



#define RX_HDMI21_RX_SCDC_01_A4                                          (HV_HDMI21_RX_SCDC_01_BASE_ADDRESS + 0xA4)

#define RX_HDMI21_RX_SCDC_01_A4_struct                                   rs_rx_hdmi21_rx_scdc_01_a4

typedef struct _rs_rx_hdmi21_rx_scdc_01_a4  rs_rx_hdmi21_rx_scdc_01_a4;
struct _rs_rx_hdmi21_rx_scdc_01_a4 {
    unsigned int reg_01_hd_rx_auto_rst_mac                  : 1;
    unsigned int reg_01_5v_det_sw_sel                       : 1;
    unsigned int reg_01_5v_det_sw_value                     : 1;
    unsigned int reg_01_HPD_to_eARC                         : 1;
    unsigned int reg_01_hdcp_ddc_enable                     : 1;
    unsigned int reserved                                   :27;
};
#define rx_hdmi21_rx_scdc_01_a4(val) ((rs_rx_hdmi21_rx_scdc_01_a4*)&(val))



#endif