#ifndef _HV_PAGE_HT7315_PIF_TX_TOP_H_
#define _HV_PAGE_HT7315_PIF_TX_TOP_H_

#ifndef HV_PIF_TX_TOP_BASE_ADDRESS
    #define HV_PIF_TX_TOP_BASE_ADDRESS                                         0x1105E000
#endif


#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_0                                   (HV_PIF_TX_TOP_BASE_ADDRESS + 0x00)

#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_0_struct                            rs_tx_pif_tx_top_pif_tx_top_reg_0

typedef struct _rs_tx_pif_tx_top_pif_tx_top_reg_0  rs_tx_pif_tx_top_pif_tx_top_reg_0;
struct _rs_tx_pif_tx_top_pif_tx_top_reg_0 {
    unsigned int reg_pif_tg_0_packet_dh_den_sta             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_pif_tg_0_packet_dh_den_end             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_pif_tx_top_pif_tx_top_reg_0(val) ((rs_tx_pif_tx_top_pif_tx_top_reg_0*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_1                                   (HV_PIF_TX_TOP_BASE_ADDRESS + 0x04)

#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_1_struct                            rs_tx_pif_tx_top_pif_tx_top_reg_1

typedef struct _rs_tx_pif_tx_top_pif_tx_top_reg_1  rs_tx_pif_tx_top_pif_tx_top_reg_1;
struct _rs_tx_pif_tx_top_pif_tx_top_reg_1 {
    unsigned int reg_pif_tg_0_packet_dv_den_sta             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_pif_tg_0_packet_dv_den_end             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_pif_tx_top_pif_tx_top_reg_1(val) ((rs_tx_pif_tx_top_pif_tx_top_reg_1*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_2                                   (HV_PIF_TX_TOP_BASE_ADDRESS + 0x08)

#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_2_struct                            rs_tx_pif_tx_top_pif_tx_top_reg_2

typedef struct _rs_tx_pif_tx_top_pif_tx_top_reg_2  rs_tx_pif_tx_top_pif_tx_top_reg_2;
struct _rs_tx_pif_tx_top_pif_tx_top_reg_2 {
    unsigned int reg_txgrp_0_phy_mode_sel                   : 4;
    unsigned int reg_pif_tg_0_mode                          : 1;
    unsigned int reg_pif_tg_0_vs_mode                       : 1;
    unsigned int reg_pif_tg_0_hs_mode                       : 1;
    unsigned int reserved                                   :10;
    unsigned int reg_ptg_db_seamless_en                     : 1;
    unsigned int reserved_1                                 :10;
    unsigned int reg_txgrp_1_phy_mode_sel                   : 4;
};
#define tx_pif_tx_top_pif_tx_top_reg_2(val) ((rs_tx_pif_tx_top_pif_tx_top_reg_2*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_3                                   (HV_PIF_TX_TOP_BASE_ADDRESS + 0x0C)

#define TX_PIF_TX_TOP_PIF_TX_TOP_REG_3_struct                            rs_tx_pif_tx_top_pif_tx_top_reg_3

typedef struct _rs_tx_pif_tx_top_pif_tx_top_reg_3  rs_tx_pif_tx_top_pif_tx_top_reg_3;
struct _rs_tx_pif_tx_top_pif_tx_top_reg_3 {
    unsigned int reserved                                   : 5;
    unsigned int reg_ptg_timer_en                           : 1;
    unsigned int reg_pif_in_afifo_size_mode                 : 2;
    unsigned int reserved_1                                 : 7;
    unsigned int reg_ptg_unit_clk_force_on                  : 1;
    unsigned int reg_ptg_mute_en_mux                        : 1;
    unsigned int reg_ptg_mute_en_soft_value                 : 1;
    unsigned int reg_pif_tg_0_pkt_double_buffer_en          : 1;
    unsigned int reg_pif_tg_0_pkt_double_buffer_timer       : 6;
    unsigned int reserved_2                                 : 7;
};
#define tx_pif_tx_top_pif_tx_top_reg_3(val) ((rs_tx_pif_tx_top_pif_tx_top_reg_3*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_CLKGEN0                                     (HV_PIF_TX_TOP_BASE_ADDRESS + 0x10)

#define TX_PIF_TX_TOP_PIF_TX_CLKGEN0_struct                              rs_tx_pif_tx_top_pif_tx_clkgen0

typedef struct _rs_tx_pif_tx_top_pif_tx_clkgen0  rs_tx_pif_tx_top_pif_tx_clkgen0;
struct _rs_tx_pif_tx_top_pif_tx_clkgen0 {
    unsigned int reg_pif_cmpi_clk_en                        : 1;
    unsigned int reg_pif_boe_clk_en                         : 1;
    unsigned int reg_pif_epi_clk_en                         : 1;
    unsigned int reg_pif_isp_clk_en                         : 1;
    unsigned int reg_pif_usit_clk_en                        : 1;
    unsigned int reg_pif_vby1_clk_en                        : 1;
    unsigned int reg_pif_mlvds_clk_en                       : 1;
    unsigned int reg_pif_edp_clk_en                         : 2;
    unsigned int reg_pif_hdtx_clk_en                        : 1;
    unsigned int reserved                                   : 6;
    unsigned int reg_pif_ptg_clk_en                         : 1;
    unsigned int reg_pif_ptg_clk_sel                        : 2;
    unsigned int reserved_1                                 :13;
};
#define tx_pif_tx_top_pif_tx_clkgen0(val) ((rs_tx_pif_tx_top_pif_tx_clkgen0*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_CLKGEN1                                     (HV_PIF_TX_TOP_BASE_ADDRESS + 0x14)

#define TX_PIF_TX_TOP_PIF_TX_CLKGEN1_struct                              rs_tx_pif_tx_top_pif_tx_clkgen1

typedef struct _rs_tx_pif_tx_top_pif_tx_clkgen1  rs_tx_pif_tx_top_pif_tx_clkgen1;
struct _rs_tx_pif_tx_top_pif_tx_clkgen1 {
    unsigned int reg_pif_pre_clk_en                         : 1;
    unsigned int reserved                                   :15;
    unsigned int reg_pif_lane_clk_en                        : 6;
    unsigned int reserved_1                                 :10;
};
#define tx_pif_tx_top_pif_tx_clkgen1(val) ((rs_tx_pif_tx_top_pif_tx_clkgen1*)&(val))



#define TX_PIF_TX_TOP_18                                                 (HV_PIF_TX_TOP_BASE_ADDRESS + 0x18)

#define TX_PIF_TX_TOP_18_struct                                          rs_tx_pif_tx_top_18

typedef struct _rs_tx_pif_tx_top_18  rs_tx_pif_tx_top_18;
struct _rs_tx_pif_tx_top_18 {
    unsigned int reg_txgrp_00_dclk_sel                      : 1;
    unsigned int reg_txgrp_00_dclk_div_num                  : 4;
    unsigned int reg_txgrp_00_pif_clk_div_num               : 2;
    unsigned int reg_txgrp_00_pif_clk_src_sel               : 2;
    unsigned int reg_txgrp_00_pif_latch_clk_div_num         : 3;
    unsigned int reserved                                   : 4;
    unsigned int reg_txgrp_01_dclk_sel                      : 1;
    unsigned int reg_txgrp_01_dclk_div_num                  : 4;
    unsigned int reg_txgrp_01_pif_clk_div_num               : 2;
    unsigned int reg_txgrp_01_pif_clk_src_sel               : 2;
    unsigned int reg_txgrp_01_pif_latch_clk_div_num         : 3;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_txphy_ext_rd_clk_sel                   : 3;
};
#define tx_pif_tx_top_18(val) ((rs_tx_pif_tx_top_18*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_UNIT_INITIAL                                (HV_PIF_TX_TOP_BASE_ADDRESS + 0x1C)

#define TX_PIF_TX_TOP_PIF_TX_UNIT_INITIAL_struct                         rs_tx_pif_tx_top_pif_tx_unit_initial

typedef struct _rs_tx_pif_tx_top_pif_tx_unit_initial  rs_tx_pif_tx_top_pif_tx_unit_initial;
struct _rs_tx_pif_tx_top_pif_tx_unit_initial {
    unsigned int reg_ptg_unit_initial                       :24;
    unsigned int reserved                                   : 8;
};
#define tx_pif_tx_top_pif_tx_unit_initial(val) ((rs_tx_pif_tx_top_pif_tx_unit_initial*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_DEBUG_REG_0                                 (HV_PIF_TX_TOP_BASE_ADDRESS + 0x20)

#define TX_PIF_TX_TOP_PIF_TX_DEBUG_REG_0_struct                          rs_tx_pif_tx_top_pif_tx_debug_reg_0

typedef struct _rs_tx_pif_tx_top_pif_tx_debug_reg_0  rs_tx_pif_tx_top_pif_tx_debug_reg_0;
struct _rs_tx_pif_tx_top_pif_tx_debug_reg_0 {
    unsigned int reg_pif_afifo_wclr_disable                 : 1;
    unsigned int reg_pif_afifo_rclr_disable                 : 1;
    unsigned int reg_ptg_hs_dly                             :11;
    unsigned int reserved                                   : 1;
    unsigned int reg_pif_afifo_flag_clear                   : 1;
    unsigned int reg_tx_lock_int_polarity_inv               : 1;
    unsigned int reserved_1                                 : 5;
    unsigned int reg_ktx_post_pre_de_mux_sel                : 1;
    unsigned int reserved_2                                 : 7;
    unsigned int reg_pif_edp_rd_ctl_sel                     : 2;
    unsigned int reg_pif_ktx_clk_en                         : 1;
};
#define tx_pif_tx_top_pif_tx_debug_reg_0(val) ((rs_tx_pif_tx_top_pif_tx_debug_reg_0*)&(val))



#define TX_PIF_TX_TOP_PTG_DOUBLE_BUFFER_TIMER                            (HV_PIF_TX_TOP_BASE_ADDRESS + 0x24)

#define TX_PIF_TX_TOP_PTG_DOUBLE_BUFFER_TIMER_struct                     rs_tx_pif_tx_top_ptg_double_buffer_timer

typedef struct _rs_tx_pif_tx_top_ptg_double_buffer_timer  rs_tx_pif_tx_top_ptg_double_buffer_timer;
struct _rs_tx_pif_tx_top_ptg_double_buffer_timer {
    unsigned int reg_ptg_timer0                             : 8;
    unsigned int reg_ptg_timer1                             : 8;
    unsigned int reg_ptg_timer2                             : 8;
    unsigned int reg_ptg_timer3                             : 8;
};
#define tx_pif_tx_top_ptg_double_buffer_timer(val) ((rs_tx_pif_tx_top_ptg_double_buffer_timer*)&(val))



#define TX_PIF_TX_TOP_PIF_TG_SETTINS                                     (HV_PIF_TX_TOP_BASE_ADDRESS + 0x28)

#define TX_PIF_TX_TOP_PIF_TG_SETTINS_struct                              rs_tx_pif_tx_top_pif_tg_settins

typedef struct _rs_tx_pif_tx_top_pif_tg_settins  rs_tx_pif_tx_top_pif_tg_settins;
struct _rs_tx_pif_tx_top_pif_tg_settins {
    unsigned int reg_pif_tg_0_den_hcnt_min_th               :15;
    unsigned int reserved                                   :17;
};
#define tx_pif_tx_top_pif_tg_settins(val) ((rs_tx_pif_tx_top_pif_tg_settins*)&(val))



#define TX_PIF_TX_TOP_2C                                                 (HV_PIF_TX_TOP_BASE_ADDRESS + 0x2C)

#define TX_PIF_TX_TOP_2C_struct                                          rs_tx_pif_tx_top_2c

typedef struct _rs_tx_pif_tx_top_2c  rs_tx_pif_tx_top_2c;
struct _rs_tx_pif_tx_top_2c {
    unsigned int reg_txphy_rd_clk_en                        :16;
    unsigned int reg_txphy_rd_clk_inv_sel                   :16;
};
#define tx_pif_tx_top_2c(val) ((rs_tx_pif_tx_top_2c*)&(val))



#define TX_PIF_TX_TOP_PTG_POL_SEL_0                                      (HV_PIF_TX_TOP_BASE_ADDRESS + 0x40)

#define TX_PIF_TX_TOP_PTG_POL_SEL_0_struct                               rs_tx_pif_tx_top_ptg_pol_sel_0

typedef struct _rs_tx_pif_tx_top_ptg_pol_sel_0  rs_tx_pif_tx_top_ptg_pol_sel_0;
struct _rs_tx_pif_tx_top_ptg_pol_sel_0 {
    unsigned int reg_ptg_pol0_sel                           : 5;
    unsigned int reg_ptg_pol1_sel                           : 5;
    unsigned int reg_ptg_pol2_sel                           : 5;
    unsigned int reg_ptg_pol3_sel                           : 5;
    unsigned int reg_ptg_pol4_sel                           : 5;
    unsigned int reg_ptg_pol5_sel                           : 5;
    unsigned int reserved                                   : 2;
};
#define tx_pif_tx_top_ptg_pol_sel_0(val) ((rs_tx_pif_tx_top_ptg_pol_sel_0*)&(val))



#define TX_PIF_TX_TOP_PTG_POL_SEL_1                                      (HV_PIF_TX_TOP_BASE_ADDRESS + 0x44)

#define TX_PIF_TX_TOP_PTG_POL_SEL_1_struct                               rs_tx_pif_tx_top_ptg_pol_sel_1

typedef struct _rs_tx_pif_tx_top_ptg_pol_sel_1  rs_tx_pif_tx_top_ptg_pol_sel_1;
struct _rs_tx_pif_tx_top_ptg_pol_sel_1 {
    unsigned int reg_ptg_pol6_sel                           : 5;
    unsigned int reg_ptg_pol7_sel                           : 5;
    unsigned int reserved                                   :21;
    unsigned int reg_mprt_timing_sel                        : 1;
};
#define tx_pif_tx_top_ptg_pol_sel_1(val) ((rs_tx_pif_tx_top_ptg_pol_sel_1*)&(val))



#define TX_PIF_TX_TOP_P2P_28S_SOE_SET_0                                  (HV_PIF_TX_TOP_BASE_ADDRESS + 0x64)

#define TX_PIF_TX_TOP_P2P_28S_SOE_SET_0_struct                           rs_tx_pif_tx_top_p2p_28s_soe_set_0

typedef struct _rs_tx_pif_tx_top_p2p_28s_soe_set_0  rs_tx_pif_tx_top_p2p_28s_soe_set_0;
struct _rs_tx_pif_tx_top_p2p_28s_soe_set_0 {
    unsigned int reg_p2p_28s_1st_soe_sta                    :10;
    unsigned int reg_p2p_28s_1st_soe_end                    : 8;
    unsigned int reserved                                   :14;
};
#define tx_pif_tx_top_p2p_28s_soe_set_0(val) ((rs_tx_pif_tx_top_p2p_28s_soe_set_0*)&(val))



#define TX_PIF_TX_TOP_P2P_28S_SOE_SET_1                                  (HV_PIF_TX_TOP_BASE_ADDRESS + 0x68)

#define TX_PIF_TX_TOP_P2P_28S_SOE_SET_1_struct                           rs_tx_pif_tx_top_p2p_28s_soe_set_1

typedef struct _rs_tx_pif_tx_top_p2p_28s_soe_set_1  rs_tx_pif_tx_top_p2p_28s_soe_set_1;
struct _rs_tx_pif_tx_top_p2p_28s_soe_set_1 {
    unsigned int reg_p2p_28s_2nd_soe_sta                    :10;
    unsigned int reg_p2p_28s_2nd_soe_end                    : 8;
    unsigned int reserved                                   :14;
};
#define tx_pif_tx_top_p2p_28s_soe_set_1(val) ((rs_tx_pif_tx_top_p2p_28s_soe_set_1*)&(val))



#define TX_PIF_TX_TOP_P2P_28S_SOE_SET_2                                  (HV_PIF_TX_TOP_BASE_ADDRESS + 0x6C)

#define TX_PIF_TX_TOP_P2P_28S_SOE_SET_2_struct                           rs_tx_pif_tx_top_p2p_28s_soe_set_2

typedef struct _rs_tx_pif_tx_top_p2p_28s_soe_set_2  rs_tx_pif_tx_top_p2p_28s_soe_set_2;
struct _rs_tx_pif_tx_top_p2p_28s_soe_set_2 {
    unsigned int reg_p2p_28s_frm_flag_1st_sel               : 5;
    unsigned int reg_p2p_28s_frm_flag_2nd_sel               : 5;
    unsigned int reg_p2p_28s_frm_flag_1st_en                : 1;
    unsigned int reg_p2p_28s_frm_flag_2nd_en                : 1;
    unsigned int reg_p2p_28s_cs_mode                        : 2;
    unsigned int reserved                                   :18;
};
#define tx_pif_tx_top_p2p_28s_soe_set_2(val) ((rs_tx_pif_tx_top_p2p_28s_soe_set_2*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_0                                 (HV_PIF_TX_TOP_BASE_ADDRESS + 0x80)

#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_0_struct                          rs_tx_pif_tx_top_pif_tx_grp_1_reg_0

typedef struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_0  rs_tx_pif_tx_top_pif_tx_grp_1_reg_0;
struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_0 {
    unsigned int reg_pif_tg_1_packet_dh_den_sta             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_pif_tg_1_packet_dh_den_end             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_pif_tx_top_pif_tx_grp_1_reg_0(val) ((rs_tx_pif_tx_top_pif_tx_grp_1_reg_0*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_1                                 (HV_PIF_TX_TOP_BASE_ADDRESS + 0x84)

#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_1_struct                          rs_tx_pif_tx_top_pif_tx_grp_1_reg_1

typedef struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_1  rs_tx_pif_tx_top_pif_tx_grp_1_reg_1;
struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_1 {
    unsigned int reg_pif_tg_1_packet_dv_den_sta             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_pif_tg_1_packet_dv_den_end             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_pif_tx_top_pif_tx_grp_1_reg_1(val) ((rs_tx_pif_tx_top_pif_tx_grp_1_reg_1*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_2                                 (HV_PIF_TX_TOP_BASE_ADDRESS + 0x88)

#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_2_struct                          rs_tx_pif_tx_top_pif_tx_grp_1_reg_2

typedef struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_2  rs_tx_pif_tx_top_pif_tx_grp_1_reg_2;
struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_2 {
    unsigned int reserved                                   : 4;
    unsigned int reg_pif_tg_1_mode                          : 1;
    unsigned int reg_pif_tg_1_vs_mode                       : 1;
    unsigned int reg_pif_tg_1_hs_mode                       : 1;
    unsigned int reserved_1                                 :25;
};
#define tx_pif_tx_top_pif_tx_grp_1_reg_2(val) ((rs_tx_pif_tx_top_pif_tx_grp_1_reg_2*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_3                                 (HV_PIF_TX_TOP_BASE_ADDRESS + 0x8C)

#define TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_3_struct                          rs_tx_pif_tx_top_pif_tx_grp_1_reg_3

typedef struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_3  rs_tx_pif_tx_top_pif_tx_grp_1_reg_3;
struct _rs_tx_pif_tx_top_pif_tx_grp_1_reg_3 {
    unsigned int reserved                                   :18;
    unsigned int reg_pif_tg_1_pkt_double_buffer_en          : 1;
    unsigned int reg_pif_tg_1_pkt_double_buffer_timer       : 6;
    unsigned int reserved_1                                 : 7;
};
#define tx_pif_tx_top_pif_tx_grp_1_reg_3(val) ((rs_tx_pif_tx_top_pif_tx_grp_1_reg_3*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_GRP_1_SETTINS                               (HV_PIF_TX_TOP_BASE_ADDRESS + 0x90)

#define TX_PIF_TX_TOP_PIF_TX_GRP_1_SETTINS_struct                        rs_tx_pif_tx_top_pif_tx_grp_1_settins

typedef struct _rs_tx_pif_tx_top_pif_tx_grp_1_settins  rs_tx_pif_tx_top_pif_tx_grp_1_settins;
struct _rs_tx_pif_tx_top_pif_tx_grp_1_settins {
    unsigned int reg_pif_tg_1_den_hcnt_min_th               :15;
    unsigned int reserved                                   :17;
};
#define tx_pif_tx_top_pif_tx_grp_1_settins(val) ((rs_tx_pif_tx_top_pif_tx_grp_1_settins*)&(val))



#define TX_PIF_TX_TOP_PIF_TX_GRP_1_BRG_CFG                               (HV_PIF_TX_TOP_BASE_ADDRESS + 0x94)

#define TX_PIF_TX_TOP_PIF_TX_GRP_1_BRG_CFG_struct                        rs_tx_pif_tx_top_pif_tx_grp_1_brg_cfg

typedef struct _rs_tx_pif_tx_top_pif_tx_grp_1_brg_cfg  rs_tx_pif_tx_top_pif_tx_grp_1_brg_cfg;
struct _rs_tx_pif_tx_top_pif_tx_grp_1_brg_cfg {
    unsigned int reg_pif_txgrp_1_brg_init_en                : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_pif_txgrp_1_brg_init_mode              : 4;
    unsigned int reg_pif_txgrp_1_brg_port_num               : 4;
    unsigned int reg_pif_txgrp_1_brg_dept_thr               : 4;
    unsigned int reg_pif_txgrp_1_brg_src_sel                : 1;
    unsigned int reserved_1                                 :15;
};
#define tx_pif_tx_top_pif_tx_grp_1_brg_cfg(val) ((rs_tx_pif_tx_top_pif_tx_grp_1_brg_cfg*)&(val))



#define TX_PIF_TX_TOP_PIF_TG_0_READBACK                                  (HV_PIF_TX_TOP_BASE_ADDRESS + 0xF0)

#define TX_PIF_TX_TOP_PIF_TG_0_READBACK_struct                           rs_tx_pif_tx_top_pif_tg_0_readback

typedef struct _rs_tx_pif_tx_top_pif_tg_0_readback  rs_tx_pif_tx_top_pif_tg_0_readback;
struct _rs_tx_pif_tx_top_pif_tg_0_readback {
    unsigned int regr_pif_tg_0_den_hcnt_total               :15;
    unsigned int regr_pif_tg_0_den_vcnt_total               :15;
    unsigned int reserved                                   : 2;
};
#define tx_pif_tx_top_pif_tg_0_readback(val) ((rs_tx_pif_tx_top_pif_tg_0_readback*)&(val))



#define TX_PIF_TX_TOP_PIF_TG_1_READBACK                                  (HV_PIF_TX_TOP_BASE_ADDRESS + 0xF4)

#define TX_PIF_TX_TOP_PIF_TG_1_READBACK_struct                           rs_tx_pif_tx_top_pif_tg_1_readback

typedef struct _rs_tx_pif_tx_top_pif_tg_1_readback  rs_tx_pif_tx_top_pif_tg_1_readback;
struct _rs_tx_pif_tx_top_pif_tg_1_readback {
    unsigned int regr_pif_tg_1_den_hcnt_total               :15;
    unsigned int regr_pif_tg_1_den_vcnt_total               :15;
    unsigned int regr_pif_txgrp_1_brg_overflow              : 2;
};
#define tx_pif_tx_top_pif_tg_1_readback(val) ((rs_tx_pif_tx_top_pif_tg_1_readback*)&(val))



#define TX_PIF_TX_TOP_A10_FIFO_READBACK_0                                (HV_PIF_TX_TOP_BASE_ADDRESS + 0xF8)

#define TX_PIF_TX_TOP_A10_FIFO_READBACK_0_struct                         rs_tx_pif_tx_top_a10_fifo_readback_0

typedef struct _rs_tx_pif_tx_top_a10_fifo_readback_0  rs_tx_pif_tx_top_a10_fifo_readback_0;
struct _rs_tx_pif_tx_top_a10_fifo_readback_0 {
    unsigned int regr_ptg_tg_0_hcnt_total                   :15;
    unsigned int regr_ptg_tg_0_vcnt_total                   :15;
    unsigned int regr_pif_afifo_flag_underflow              : 2;
};
#define tx_pif_tx_top_a10_fifo_readback_0(val) ((rs_tx_pif_tx_top_a10_fifo_readback_0*)&(val))



#define TX_PIF_TX_TOP_A10_FIFO_READBACK_1                                (HV_PIF_TX_TOP_BASE_ADDRESS + 0xFC)

#define TX_PIF_TX_TOP_A10_FIFO_READBACK_1_struct                         rs_tx_pif_tx_top_a10_fifo_readback_1

typedef struct _rs_tx_pif_tx_top_a10_fifo_readback_1  rs_tx_pif_tx_top_a10_fifo_readback_1;
struct _rs_tx_pif_tx_top_a10_fifo_readback_1 {
    unsigned int regr_pif_afifo_flag_overflow               : 2;
    unsigned int reserved                                   :30;
};
#define tx_pif_tx_top_a10_fifo_readback_1(val) ((rs_tx_pif_tx_top_a10_fifo_readback_1*)&(val))



#endif