#ifndef _HV_PAGE_HT7315_EDP_RX_MAC_RO_REG_01_H_
#define _HV_PAGE_HT7315_EDP_RX_MAC_RO_REG_01_H_

#ifndef HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS
    #define HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS                                         0x1104A800
#endif


#define RX_EDP_RX_MAC_RO_REG_01_04                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_MAC_RO_REG_01_04_struct                                rs_rx_edp_rx_mac_ro_reg_01_04

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_04  rs_rx_edp_rx_mac_ro_reg_01_04;
struct _rs_rx_edp_rx_mac_ro_reg_01_04 {
    unsigned int regr_01_dprx_sb_lock                       : 4;
    unsigned int regr_01_dprx_cr_done                       : 4;
    unsigned int regr_01_dprx_phy_cr_done                   : 4;
    unsigned int regr_01_dprx_eq_lock                       : 4;
    unsigned int regr_01_dprx_phy_eq_lock                   : 4;
    unsigned int regr_01_dprx_cr_done_all                   : 1;
    unsigned int regr_01_dprx_eq_lock_all                   : 1;
    unsigned int regr_01_dprx_sb_lock_all                   : 1;
    unsigned int regr_01_dprx_aln_done                      : 1;
    unsigned int regr_01_dprx_front_st                      : 4;
    unsigned int regr_01_dprx_pm_fsm_status                 : 4;
};
#define rx_edp_rx_mac_ro_reg_01_04(val) ((rs_rx_edp_rx_mac_ro_reg_01_04*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_08                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_MAC_RO_REG_01_08_struct                                rs_rx_edp_rx_mac_ro_reg_01_08

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_08  rs_rx_edp_rx_mac_ro_reg_01_08;
struct _rs_rx_edp_rx_mac_ro_reg_01_08 {
    unsigned int regr_01_dprx_symbol_lock_pos               :32;
};
#define rx_edp_rx_mac_ro_reg_01_08(val) ((rs_rx_edp_rx_mac_ro_reg_01_08*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_0C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x0C)

#define RX_EDP_RX_MAC_RO_REG_01_0C_struct                                rs_rx_edp_rx_mac_ro_reg_01_0c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_0c  rs_rx_edp_rx_mac_ro_reg_01_0c;
struct _rs_rx_edp_rx_mac_ro_reg_01_0c {
    unsigned int regr_01_dprx_lane0_err_cnt                 :32;
};
#define rx_edp_rx_mac_ro_reg_01_0c(val) ((rs_rx_edp_rx_mac_ro_reg_01_0c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_10                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x10)

#define RX_EDP_RX_MAC_RO_REG_01_10_struct                                rs_rx_edp_rx_mac_ro_reg_01_10

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_10  rs_rx_edp_rx_mac_ro_reg_01_10;
struct _rs_rx_edp_rx_mac_ro_reg_01_10 {
    unsigned int regr_01_dprx_lane1_err_cnt                 :32;
};
#define rx_edp_rx_mac_ro_reg_01_10(val) ((rs_rx_edp_rx_mac_ro_reg_01_10*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_14                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x14)

#define RX_EDP_RX_MAC_RO_REG_01_14_struct                                rs_rx_edp_rx_mac_ro_reg_01_14

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_14  rs_rx_edp_rx_mac_ro_reg_01_14;
struct _rs_rx_edp_rx_mac_ro_reg_01_14 {
    unsigned int regr_01_dprx_lane2_err_cnt                 :32;
};
#define rx_edp_rx_mac_ro_reg_01_14(val) ((rs_rx_edp_rx_mac_ro_reg_01_14*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_18                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x18)

#define RX_EDP_RX_MAC_RO_REG_01_18_struct                                rs_rx_edp_rx_mac_ro_reg_01_18

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_18  rs_rx_edp_rx_mac_ro_reg_01_18;
struct _rs_rx_edp_rx_mac_ro_reg_01_18 {
    unsigned int regr_01_dprx_lane3_err_cnt                 :32;
};
#define rx_edp_rx_mac_ro_reg_01_18(val) ((rs_rx_edp_rx_mac_ro_reg_01_18*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_1C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x1C)

#define RX_EDP_RX_MAC_RO_REG_01_1C_struct                                rs_rx_edp_rx_mac_ro_reg_01_1c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_1c  rs_rx_edp_rx_mac_ro_reg_01_1c;
struct _rs_rx_edp_rx_mac_ro_reg_01_1c {
    unsigned int regr_01_dprx_hpd_abn_l1                    : 8;
    unsigned int regr_01_dprx_irq_l1                        : 8;
    unsigned int reserved                                   : 8;
    unsigned int regr_01_dprx_sr_flag                       : 8;
};
#define rx_edp_rx_mac_ro_reg_01_1c(val) ((rs_rx_edp_rx_mac_ro_reg_01_1c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_20                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_MAC_RO_REG_01_20_struct                                rs_rx_edp_rx_mac_ro_reg_01_20

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_20  rs_rx_edp_rx_mac_ro_reg_01_20;
struct _rs_rx_edp_rx_mac_ro_reg_01_20 {
    unsigned int regr_01_dprx_lane0_err_cnt_tr              :16;
    unsigned int regr_01_dprx_lane1_err_cnt_tr              :16;
};
#define rx_edp_rx_mac_ro_reg_01_20(val) ((rs_rx_edp_rx_mac_ro_reg_01_20*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_24                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_MAC_RO_REG_01_24_struct                                rs_rx_edp_rx_mac_ro_reg_01_24

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_24  rs_rx_edp_rx_mac_ro_reg_01_24;
struct _rs_rx_edp_rx_mac_ro_reg_01_24 {
    unsigned int regr_01_dprx_lane2_err_cnt_tr              :16;
    unsigned int regr_01_dprx_lane3_err_cnt_tr              :16;
};
#define rx_edp_rx_mac_ro_reg_01_24(val) ((rs_rx_edp_rx_mac_ro_reg_01_24*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_2C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x2C)

#define RX_EDP_RX_MAC_RO_REG_01_2C_struct                                rs_rx_edp_rx_mac_ro_reg_01_2c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_2c  rs_rx_edp_rx_mac_ro_reg_01_2c;
struct _rs_rx_edp_rx_mac_ro_reg_01_2c {
    unsigned int regr_01_dprx_deskew_cnt_lane0              : 8;
    unsigned int regr_01_dprx_deskew_cnt_lane1              : 8;
    unsigned int regr_01_dprx_deskew_cnt_lane2              : 8;
    unsigned int regr_01_dprx_deskew_cnt_lane3              : 8;
};
#define rx_edp_rx_mac_ro_reg_01_2c(val) ((rs_rx_edp_rx_mac_ro_reg_01_2c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_30                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x30)

#define RX_EDP_RX_MAC_RO_REG_01_30_struct                                rs_rx_edp_rx_mac_ro_reg_01_30

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_30  rs_rx_edp_rx_mac_ro_reg_01_30;
struct _rs_rx_edp_rx_mac_ro_reg_01_30 {
    unsigned int regr_01_dprx_irq_l                         :32;
};
#define rx_edp_rx_mac_ro_reg_01_30(val) ((rs_rx_edp_rx_mac_ro_reg_01_30*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_34                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x34)

#define RX_EDP_RX_MAC_RO_REG_01_34_struct                                rs_rx_edp_rx_mac_ro_reg_01_34

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_34  rs_rx_edp_rx_mac_ro_reg_01_34;
struct _rs_rx_edp_rx_mac_ro_reg_01_34 {
    unsigned int regr_01_dprx_irq_h                         :32;
};
#define rx_edp_rx_mac_ro_reg_01_34(val) ((rs_rx_edp_rx_mac_ro_reg_01_34*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_38                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x38)

#define RX_EDP_RX_MAC_RO_REG_01_38_struct                                rs_rx_edp_rx_mac_ro_reg_01_38

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_38  rs_rx_edp_rx_mac_ro_reg_01_38;
struct _rs_rx_edp_rx_mac_ro_reg_01_38 {
    unsigned int regr_01_dprx_hpd_abn_l                     :32;
};
#define rx_edp_rx_mac_ro_reg_01_38(val) ((rs_rx_edp_rx_mac_ro_reg_01_38*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_3C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x3C)

#define RX_EDP_RX_MAC_RO_REG_01_3C_struct                                rs_rx_edp_rx_mac_ro_reg_01_3c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_3c  rs_rx_edp_rx_mac_ro_reg_01_3c;
struct _rs_rx_edp_rx_mac_ro_reg_01_3c {
    unsigned int regr_01_dprx_hpd_abn_h                     :32;
};
#define rx_edp_rx_mac_ro_reg_01_3c(val) ((rs_rx_edp_rx_mac_ro_reg_01_3c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_40                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_MAC_RO_REG_01_40_struct                                rs_rx_edp_rx_mac_ro_reg_01_40

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_40  rs_rx_edp_rx_mac_ro_reg_01_40;
struct _rs_rx_edp_rx_mac_ro_reg_01_40 {
    unsigned int regr_01_dprx_ft_dbg_dat0                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_40(val) ((rs_rx_edp_rx_mac_ro_reg_01_40*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_44                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_MAC_RO_REG_01_44_struct                                rs_rx_edp_rx_mac_ro_reg_01_44

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_44  rs_rx_edp_rx_mac_ro_reg_01_44;
struct _rs_rx_edp_rx_mac_ro_reg_01_44 {
    unsigned int regr_01_dprx_ft_dbg_dat1                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_44(val) ((rs_rx_edp_rx_mac_ro_reg_01_44*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_48                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_MAC_RO_REG_01_48_struct                                rs_rx_edp_rx_mac_ro_reg_01_48

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_48  rs_rx_edp_rx_mac_ro_reg_01_48;
struct _rs_rx_edp_rx_mac_ro_reg_01_48 {
    unsigned int regr_01_dprx_ft_dbg_dat2                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_48(val) ((rs_rx_edp_rx_mac_ro_reg_01_48*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_4C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x4C)

#define RX_EDP_RX_MAC_RO_REG_01_4C_struct                                rs_rx_edp_rx_mac_ro_reg_01_4c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_4c  rs_rx_edp_rx_mac_ro_reg_01_4c;
struct _rs_rx_edp_rx_mac_ro_reg_01_4c {
    unsigned int regr_01_dprx_ft_dbg_dat3                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_4c(val) ((rs_rx_edp_rx_mac_ro_reg_01_4c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_50                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x50)

#define RX_EDP_RX_MAC_RO_REG_01_50_struct                                rs_rx_edp_rx_mac_ro_reg_01_50

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_50  rs_rx_edp_rx_mac_ro_reg_01_50;
struct _rs_rx_edp_rx_mac_ro_reg_01_50 {
    unsigned int regr_01_dprx_bw_set                        : 4;
    unsigned int regr_01_dprx_lnum_set                      : 4;
    unsigned int reserved                                   :24;
};
#define rx_edp_rx_mac_ro_reg_01_50(val) ((rs_rx_edp_rx_mac_ro_reg_01_50*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_54                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x54)

#define RX_EDP_RX_MAC_RO_REG_01_54_struct                                rs_rx_edp_rx_mac_ro_reg_01_54

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_54  rs_rx_edp_rx_mac_ro_reg_01_54;
struct _rs_rx_edp_rx_mac_ro_reg_01_54 {
    unsigned int regr_01_dprx_mac_clkdet_freq_cnt           :32;
};
#define rx_edp_rx_mac_ro_reg_01_54(val) ((rs_rx_edp_rx_mac_ro_reg_01_54*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_58                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x58)

#define RX_EDP_RX_MAC_RO_REG_01_58_struct                                rs_rx_edp_rx_mac_ro_reg_01_58

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_58  rs_rx_edp_rx_mac_ro_reg_01_58;
struct _rs_rx_edp_rx_mac_ro_reg_01_58 {
    unsigned int regr_01_dprx_mac_clkdet_abn_nck            : 4;
    unsigned int regr_01_dprx_mac_clkdet_abn_low            : 4;
    unsigned int regr_01_dprx_mac_clkdet_abn_high           : 4;
    unsigned int regr_01_dprx_mac_clkdet_abn_nstb           : 4;
    unsigned int reserved                                   :16;
};
#define rx_edp_rx_mac_ro_reg_01_58(val) ((rs_rx_edp_rx_mac_ro_reg_01_58*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_60                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_MAC_RO_REG_01_60_struct                                rs_rx_edp_rx_mac_ro_reg_01_60

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_60  rs_rx_edp_rx_mac_ro_reg_01_60;
struct _rs_rx_edp_rx_mac_ro_reg_01_60 {
    unsigned int regr_01_dprx_aux_commd                     : 4;
    unsigned int regr_01_dprx_aux_addr                      :20;
    unsigned int regr_01_dprx_aux_len                       : 8;
};
#define rx_edp_rx_mac_ro_reg_01_60(val) ((rs_rx_edp_rx_mac_ro_reg_01_60*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_64                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x64)

#define RX_EDP_RX_MAC_RO_REG_01_64_struct                                rs_rx_edp_rx_mac_ro_reg_01_64

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_64  rs_rx_edp_rx_mac_ro_reg_01_64;
struct _rs_rx_edp_rx_mac_ro_reg_01_64 {
    unsigned int regr_01_dprx_aux_wdata_0                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_64(val) ((rs_rx_edp_rx_mac_ro_reg_01_64*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_68                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x68)

#define RX_EDP_RX_MAC_RO_REG_01_68_struct                                rs_rx_edp_rx_mac_ro_reg_01_68

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_68  rs_rx_edp_rx_mac_ro_reg_01_68;
struct _rs_rx_edp_rx_mac_ro_reg_01_68 {
    unsigned int regr_01_dprx_aux_wdata_1                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_68(val) ((rs_rx_edp_rx_mac_ro_reg_01_68*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_6C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x6C)

#define RX_EDP_RX_MAC_RO_REG_01_6C_struct                                rs_rx_edp_rx_mac_ro_reg_01_6c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_6c  rs_rx_edp_rx_mac_ro_reg_01_6c;
struct _rs_rx_edp_rx_mac_ro_reg_01_6c {
    unsigned int regr_01_dprx_aux_wdata_2                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_6c(val) ((rs_rx_edp_rx_mac_ro_reg_01_6c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_70                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x70)

#define RX_EDP_RX_MAC_RO_REG_01_70_struct                                rs_rx_edp_rx_mac_ro_reg_01_70

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_70  rs_rx_edp_rx_mac_ro_reg_01_70;
struct _rs_rx_edp_rx_mac_ro_reg_01_70 {
    unsigned int regr_01_dprx_aux_wdata_3                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_70(val) ((rs_rx_edp_rx_mac_ro_reg_01_70*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_74                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x74)

#define RX_EDP_RX_MAC_RO_REG_01_74_struct                                rs_rx_edp_rx_mac_ro_reg_01_74

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_74  rs_rx_edp_rx_mac_ro_reg_01_74;
struct _rs_rx_edp_rx_mac_ro_reg_01_74 {
    unsigned int regr_01_dprx_aux_wdata_4                   :32;
};
#define rx_edp_rx_mac_ro_reg_01_74(val) ((rs_rx_edp_rx_mac_ro_reg_01_74*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_80                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x80)

#define RX_EDP_RX_MAC_RO_REG_01_80_struct                                rs_rx_edp_rx_mac_ro_reg_01_80

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_80  rs_rx_edp_rx_mac_ro_reg_01_80;
struct _rs_rx_edp_rx_mac_ro_reg_01_80 {
    unsigned int regr_01_dprx_aux_rx_time_out               : 1;
    unsigned int regr_01_dprx_aux_rx_time_out_evt           : 1;
    unsigned int reserved                                   : 2;
    unsigned int regr_01_dprx_aux_tx_state                  : 4;
    unsigned int regr_01_dprx_aux_state                     : 4;
    unsigned int regr_01_dprx_aux_wdata_cnt                 : 8;
    unsigned int regr_01_dprx_fec_en_cnt                    : 4;
    unsigned int regr_01_dprx_fec_dis_cnt                   : 4;
    unsigned int regr_01_dprx_fec_pm_cnt                    : 4;
};
#define rx_edp_rx_mac_ro_reg_01_80(val) ((rs_rx_edp_rx_mac_ro_reg_01_80*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_84                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x84)

#define RX_EDP_RX_MAC_RO_REG_01_84_struct                                rs_rx_edp_rx_mac_ro_reg_01_84

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_84  rs_rx_edp_rx_mac_ro_reg_01_84;
struct _rs_rx_edp_rx_mac_ro_reg_01_84 {
    unsigned int regr_01_dprx_aux_freq_cnt                  :16;
    unsigned int regr_01_dprx_aux_dbg_cmd_cnt               :16;
};
#define rx_edp_rx_mac_ro_reg_01_84(val) ((rs_rx_edp_rx_mac_ro_reg_01_84*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_88                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x88)

#define RX_EDP_RX_MAC_RO_REG_01_88_struct                                rs_rx_edp_rx_mac_ro_reg_01_88

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_88  rs_rx_edp_rx_mac_ro_reg_01_88;
struct _rs_rx_edp_rx_mac_ro_reg_01_88 {
    unsigned int regr_01_dprx_aux_debug_cmddata             :32;
};
#define rx_edp_rx_mac_ro_reg_01_88(val) ((rs_rx_edp_rx_mac_ro_reg_01_88*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_8C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x8C)

#define RX_EDP_RX_MAC_RO_REG_01_8C_struct                                rs_rx_edp_rx_mac_ro_reg_01_8c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_8c  rs_rx_edp_rx_mac_ro_reg_01_8c;
struct _rs_rx_edp_rx_mac_ro_reg_01_8c {
    unsigned int regr_01_dprx_aux_debug_wdata               :28;
    unsigned int reserved                                   : 4;
};
#define rx_edp_rx_mac_ro_reg_01_8c(val) ((rs_rx_edp_rx_mac_ro_reg_01_8c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_90                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x90)

#define RX_EDP_RX_MAC_RO_REG_01_90_struct                                rs_rx_edp_rx_mac_ro_reg_01_90

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_90  rs_rx_edp_rx_mac_ro_reg_01_90;
struct _rs_rx_edp_rx_mac_ro_reg_01_90 {
    unsigned int regr_01_dprx_aux_debug_rdata               :28;
    unsigned int regr_01_dprx_psr_crc_error                 : 1;
    unsigned int regr_01_dprx_psr_fsm_status                : 3;
};
#define rx_edp_rx_mac_ro_reg_01_90(val) ((rs_rx_edp_rx_mac_ro_reg_01_90*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_94                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x94)

#define RX_EDP_RX_MAC_RO_REG_01_94_struct                                rs_rx_edp_rx_mac_ro_reg_01_94

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_94  rs_rx_edp_rx_mac_ro_reg_01_94;
struct _rs_rx_edp_rx_mac_ro_reg_01_94 {
    unsigned int regr_01_dprx_sr_bs_cnt                     :16;
    unsigned int regr_01_dprx_psr_fsm_abn                   :16;
};
#define rx_edp_rx_mac_ro_reg_01_94(val) ((rs_rx_edp_rx_mac_ro_reg_01_94*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_9C                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0x9C)

#define RX_EDP_RX_MAC_RO_REG_01_9C_struct                                rs_rx_edp_rx_mac_ro_reg_01_9c

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_9c  rs_rx_edp_rx_mac_ro_reg_01_9c;
struct _rs_rx_edp_rx_mac_ro_reg_01_9c {
    unsigned int regr_01_dprx_phy_data_lane0                :20;
    unsigned int reserved                                   :12;
};
#define rx_edp_rx_mac_ro_reg_01_9c(val) ((rs_rx_edp_rx_mac_ro_reg_01_9c*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_A0                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xA0)

#define RX_EDP_RX_MAC_RO_REG_01_A0_struct                                rs_rx_edp_rx_mac_ro_reg_01_a0

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_a0  rs_rx_edp_rx_mac_ro_reg_01_a0;
struct _rs_rx_edp_rx_mac_ro_reg_01_a0 {
    unsigned int regr_01_dprx_phy_data_lane1                :20;
    unsigned int reserved                                   :12;
};
#define rx_edp_rx_mac_ro_reg_01_a0(val) ((rs_rx_edp_rx_mac_ro_reg_01_a0*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_A4                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xA4)

#define RX_EDP_RX_MAC_RO_REG_01_A4_struct                                rs_rx_edp_rx_mac_ro_reg_01_a4

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_a4  rs_rx_edp_rx_mac_ro_reg_01_a4;
struct _rs_rx_edp_rx_mac_ro_reg_01_a4 {
    unsigned int regr_01_dprx_phy_data_lane2                :20;
    unsigned int reserved                                   :12;
};
#define rx_edp_rx_mac_ro_reg_01_a4(val) ((rs_rx_edp_rx_mac_ro_reg_01_a4*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_A8                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xA8)

#define RX_EDP_RX_MAC_RO_REG_01_A8_struct                                rs_rx_edp_rx_mac_ro_reg_01_a8

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_a8  rs_rx_edp_rx_mac_ro_reg_01_a8;
struct _rs_rx_edp_rx_mac_ro_reg_01_a8 {
    unsigned int regr_01_dprx_phy_data_lane3                :20;
    unsigned int regr_01_dprx_fec_rs_cnt                    : 8;
    unsigned int regr_01_dprx_alpm_fw_stb_flag              : 1;
    unsigned int regr_01_dprx_alpm_fw_slp_flag              : 1;
    unsigned int regr_01_dprx_alpm_aux_wake_flag            : 1;
    unsigned int regr_01_dprx_alpm_aux_wake_alpm_flag       : 1;
};
#define rx_edp_rx_mac_ro_reg_01_a8(val) ((rs_rx_edp_rx_mac_ro_reg_01_a8*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_AC                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xAC)

#define RX_EDP_RX_MAC_RO_REG_01_AC_struct                                rs_rx_edp_rx_mac_ro_reg_01_ac

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_ac  rs_rx_edp_rx_mac_ro_reg_01_ac;
struct _rs_rx_edp_rx_mac_ro_reg_01_ac {
    unsigned int regr_01_dprx_cdr_time_cnt                  : 8;
    unsigned int regr_01_dprx_aln_time_cnt                  :16;
    unsigned int regr_01_dprx_ft_abn                        : 8;
};
#define rx_edp_rx_mac_ro_reg_01_ac(val) ((rs_rx_edp_rx_mac_ro_reg_01_ac*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_B0                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xB0)

#define RX_EDP_RX_MAC_RO_REG_01_B0_struct                                rs_rx_edp_rx_mac_ro_reg_01_b0

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_b0  rs_rx_edp_rx_mac_ro_reg_01_b0;
struct _rs_rx_edp_rx_mac_ro_reg_01_b0 {
    unsigned int regr_01_dprx_front_st_buf0                 :32;
};
#define rx_edp_rx_mac_ro_reg_01_b0(val) ((rs_rx_edp_rx_mac_ro_reg_01_b0*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_B4                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xB4)

#define RX_EDP_RX_MAC_RO_REG_01_B4_struct                                rs_rx_edp_rx_mac_ro_reg_01_b4

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_b4  rs_rx_edp_rx_mac_ro_reg_01_b4;
struct _rs_rx_edp_rx_mac_ro_reg_01_b4 {
    unsigned int regr_01_dprx_front_st_buf1                 :32;
};
#define rx_edp_rx_mac_ro_reg_01_b4(val) ((rs_rx_edp_rx_mac_ro_reg_01_b4*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_C4                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xC4)

#define RX_EDP_RX_MAC_RO_REG_01_C4_struct                                rs_rx_edp_rx_mac_ro_reg_01_c4

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_c4  rs_rx_edp_rx_mac_ro_reg_01_c4;
struct _rs_rx_edp_rx_mac_ro_reg_01_c4 {
    unsigned int regr_01_dprx_rx_gtc_delta                  :32;
};
#define rx_edp_rx_mac_ro_reg_01_c4(val) ((rs_rx_edp_rx_mac_ro_reg_01_c4*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_C8                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xC8)

#define RX_EDP_RX_MAC_RO_REG_01_C8_struct                                rs_rx_edp_rx_mac_ro_reg_01_c8

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_c8  rs_rx_edp_rx_mac_ro_reg_01_c8;
struct _rs_rx_edp_rx_mac_ro_reg_01_c8 {
    unsigned int regr_01_dprx_tx_gtc_delta                  :32;
};
#define rx_edp_rx_mac_ro_reg_01_c8(val) ((rs_rx_edp_rx_mac_ro_reg_01_c8*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_CC                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xCC)

#define RX_EDP_RX_MAC_RO_REG_01_CC_struct                                rs_rx_edp_rx_mac_ro_reg_01_cc

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_cc  rs_rx_edp_rx_mac_ro_reg_01_cc;
struct _rs_rx_edp_rx_mac_ro_reg_01_cc {
    unsigned int regr_01_dprx_frame_sync_delta              :32;
};
#define rx_edp_rx_mac_ro_reg_01_cc(val) ((rs_rx_edp_rx_mac_ro_reg_01_cc*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_D0                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xD0)

#define RX_EDP_RX_MAC_RO_REG_01_D0_struct                                rs_rx_edp_rx_mac_ro_reg_01_d0

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_d0  rs_rx_edp_rx_mac_ro_reg_01_d0;
struct _rs_rx_edp_rx_mac_ro_reg_01_d0 {
    unsigned int regr_01_dprx_lock_cnt                      :16;
    unsigned int regr_01_dprx_unlock_cnt                    :16;
};
#define rx_edp_rx_mac_ro_reg_01_d0(val) ((rs_rx_edp_rx_mac_ro_reg_01_d0*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_D4                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xD4)

#define RX_EDP_RX_MAC_RO_REG_01_D4_struct                                rs_rx_edp_rx_mac_ro_reg_01_d4

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_d4  rs_rx_edp_rx_mac_ro_reg_01_d4;
struct _rs_rx_edp_rx_mac_ro_reg_01_d4 {
    unsigned int regr_01_dprx_ft_af_of                      : 4;
    unsigned int regr_01_dprx_ft_af_uf                      : 4;
    unsigned int regr_01_dprx_aux_100_wdata                 : 8;
    unsigned int regr_01_dprx_aux_101_wdata                 : 8;
    unsigned int regr_01_dprx_qual_patt_flag                : 8;
};
#define rx_edp_rx_mac_ro_reg_01_d4(val) ((rs_rx_edp_rx_mac_ro_reg_01_d4*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_D8                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xD8)

#define RX_EDP_RX_MAC_RO_REG_01_D8_struct                                rs_rx_edp_rx_mac_ro_reg_01_d8

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_d8  rs_rx_edp_rx_mac_ro_reg_01_d8;
struct _rs_rx_edp_rx_mac_ro_reg_01_d8 {
    unsigned int regr_01_dprx_qual_patt_cnt                 :32;
};
#define rx_edp_rx_mac_ro_reg_01_d8(val) ((rs_rx_edp_rx_mac_ro_reg_01_d8*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_E0                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xE0)

#define RX_EDP_RX_MAC_RO_REG_01_E0_struct                                rs_rx_edp_rx_mac_ro_reg_01_e0

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_e0  rs_rx_edp_rx_mac_ro_reg_01_e0;
struct _rs_rx_edp_rx_mac_ro_reg_01_e0 {
    unsigned int regr_01_dprx_psr_fsm_buf0                  :32;
};
#define rx_edp_rx_mac_ro_reg_01_e0(val) ((rs_rx_edp_rx_mac_ro_reg_01_e0*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_E4                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xE4)

#define RX_EDP_RX_MAC_RO_REG_01_E4_struct                                rs_rx_edp_rx_mac_ro_reg_01_e4

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_e4  rs_rx_edp_rx_mac_ro_reg_01_e4;
struct _rs_rx_edp_rx_mac_ro_reg_01_e4 {
    unsigned int regr_01_dprx_psr_fsm_buf1                  :32;
};
#define rx_edp_rx_mac_ro_reg_01_e4(val) ((rs_rx_edp_rx_mac_ro_reg_01_e4*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_E8                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xE8)

#define RX_EDP_RX_MAC_RO_REG_01_E8_struct                                rs_rx_edp_rx_mac_ro_reg_01_e8

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_e8  rs_rx_edp_rx_mac_ro_reg_01_e8;
struct _rs_rx_edp_rx_mac_ro_reg_01_e8 {
    unsigned int regr_01_dprx_psr_dbg_rdata0                :32;
};
#define rx_edp_rx_mac_ro_reg_01_e8(val) ((rs_rx_edp_rx_mac_ro_reg_01_e8*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_EC                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xEC)

#define RX_EDP_RX_MAC_RO_REG_01_EC_struct                                rs_rx_edp_rx_mac_ro_reg_01_ec

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_ec  rs_rx_edp_rx_mac_ro_reg_01_ec;
struct _rs_rx_edp_rx_mac_ro_reg_01_ec {
    unsigned int regr_01_dprx_psr_dbg_rdata1                :32;
};
#define rx_edp_rx_mac_ro_reg_01_ec(val) ((rs_rx_edp_rx_mac_ro_reg_01_ec*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_F0                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xF0)

#define RX_EDP_RX_MAC_RO_REG_01_F0_struct                                rs_rx_edp_rx_mac_ro_reg_01_f0

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_f0  rs_rx_edp_rx_mac_ro_reg_01_f0;
struct _rs_rx_edp_rx_mac_ro_reg_01_f0 {
    unsigned int regr_01_dprx_psr_dbg_rdata2                :32;
};
#define rx_edp_rx_mac_ro_reg_01_f0(val) ((rs_rx_edp_rx_mac_ro_reg_01_f0*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_F4                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xF4)

#define RX_EDP_RX_MAC_RO_REG_01_F4_struct                                rs_rx_edp_rx_mac_ro_reg_01_f4

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_f4  rs_rx_edp_rx_mac_ro_reg_01_f4;
struct _rs_rx_edp_rx_mac_ro_reg_01_f4 {
    unsigned int regr_01_dprx_psr_crc_val_buf0              :32;
};
#define rx_edp_rx_mac_ro_reg_01_f4(val) ((rs_rx_edp_rx_mac_ro_reg_01_f4*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_F8                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xF8)

#define RX_EDP_RX_MAC_RO_REG_01_F8_struct                                rs_rx_edp_rx_mac_ro_reg_01_f8

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_f8  rs_rx_edp_rx_mac_ro_reg_01_f8;
struct _rs_rx_edp_rx_mac_ro_reg_01_f8 {
    unsigned int regr_01_dprx_psr_crc_val_buf1              :32;
};
#define rx_edp_rx_mac_ro_reg_01_f8(val) ((rs_rx_edp_rx_mac_ro_reg_01_f8*)&(val))



#define RX_EDP_RX_MAC_RO_REG_01_FC                                       (HV_EDP_RX_MAC_RO_REG_01_BASE_ADDRESS + 0xFC)

#define RX_EDP_RX_MAC_RO_REG_01_FC_struct                                rs_rx_edp_rx_mac_ro_reg_01_fc

typedef struct _rs_rx_edp_rx_mac_ro_reg_01_fc  rs_rx_edp_rx_mac_ro_reg_01_fc;
struct _rs_rx_edp_rx_mac_ro_reg_01_fc {
    unsigned int regr_01_dprx_psr_crc_val_buf2              :32;
};
#define rx_edp_rx_mac_ro_reg_01_fc(val) ((rs_rx_edp_rx_mac_ro_reg_01_fc*)&(val))



#endif