/**
 * @file  hv_drv_TypecDrpBootConfig.h
 * @brief  Power Delivery DRP Configurable globals Header File
 *       This header file contains user configurable globals and function prototypes.
 * @details This file provides the following functions: \n
 *          (1) \n
 *          (2) \n
 *          (3) \n
 *
 * @bug 1.bug1 \n
 * @todo 1.todo1 \n
 * 
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-25
 * @copyright Copyright(c),2022-8, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date         <th>Change Description
 * <tr><td>Hiview SoC Software Team       <td>2022-08-25   <td>init
 * </table>
*/


#ifndef _HV_DRV_TYPECDRPBOOTCONFIG_H    /* Guard against multiple inclusion */
#define _HV_DRV_TYPECDRPBOOTCONFIG_H

/*********************************Common Configuration*****************************************/
#define CFG_PRODUCT_ID              0x0350U
#define CFG_VENDOR_ID               0x380CU
#define CFG_HW_VERSION              0x00U
#define CFG_SILICON_VERSION         0x00U

/*Length of Manufacturer string should be within the range of 0 to 21.
 Default length of Manufacturer string is 20*/
#define CFG_MANUFACTURER_STR_LEN    20U

/*Number of characters in Manufacturer string should be less than or equal to
 the value in CFG_MANUFACTURER_STR_LEN. Default manufacturer string is 
 "Hiview Technology" */
#define CFG_MANUFACTURER_STR        "Hiview Technology"


/*******************Power Throttling configuration**********************/
/* Note: By default, PT is disabled for the system since support for 
   PPS + PT coexistence is planned for future phases. If PT needs to 
   be enabled, change the value of CFG_PT_ENABLE macro to 1U. */
#define CFG_PT_ENABLE                         0U 
/*Bank A - 0, Bank B - 1, Bank C - 2, Shutdown mode - 3*/
#define CFG_PT_POWER_THROTTLE_BANK_SEL        0U /*Bank A selected*/

/**************************Power Balancing configuration******************* */
/* Note: By default, PB is disabled for the system since support for 
   PPS + PB coexistence is planned for future phases. If PB needs to be 
   enabled, change the value of CFG_PB_ENABLE macro to 0x10U and 
   CFG_PORT_x_PB_ENABLE to 0x01U. This will enable PB 
   with FCFS as Selection Algorithm. */
#define CFG_PB_ENABLE                         0x00U 

#define CFG_PORT_0_PB_ENABLE                  0x00U
#define CFG_PORT_1_PB_ENABLE                  0x00U

#define CFG_EPR_ENABLE                         0

/* Default Total System Power Bank A is 120W */
#define CFG_PB_TOT_SYS_POWER_BANKA_IN_250mW            0x01E0U 
/* Guaranteed Minimum Power for Bank A is 15W */
#define CFG_PB_MIN_POWER_BANKA_IN_250mW                0x003CU
/* Default Total System Power Bank B is 120W */
#define CFG_PB_TOT_SYS_POWER_BANKB_IN_250mW            0x01E0U
/* Guaranteed Minimum Power for Bank A is 15W */
#define CFG_PB_MIN_POWER_BANKB_IN_250mW                0x003CU
/* Default Total System Power Bank C is 120W */
#define CFG_PB_TOT_SYS_POWER_BANKC_IN_250mW            0x01E0U
/* Guaranteed Minimum Power for Bank A is 15W */
#define CFG_PB_MIN_POWER_BANKC_IN_250mW                0x003CU

/* Default Max Port Power for Bank A is 60W */
#define CFG_PB_MAX_PORT_0_POWER_BANKA_IN_250mW           0x00F0U
/* Default Max Port Power for Bank B is 60W */
#define CFG_PB_MAX_PORT_0_POWER_BANKB_IN_250mW           0x00F0U
/* Default Max Port Power for Bank C is 60W */
#define CFG_PB_MAX_PORT_0_POWER_BANKC_IN_250mW           0x00F0U

#define CFG_PB_MAX_PORT_1_POWER_BANKA_IN_250mW           0x00F0U
/* Default Max Port Power for Bank B is 60W */
#define CFG_PB_MAX_PORT_1_POWER_BANKB_IN_250mW           0x00F0U
/* Default Max Port Power for Bank C is 60W */
#define CFG_PB_MAX_PORT_1_POWER_BANKC_IN_250mW           0x00F0U

/***********************************Port Specific configuration***********************/    
/*Configuration value for u32CfgData*/
/*Power Role values: 0 - Sink, 1 - Source, 2 - DRP*/
#define CFG_PORT_0_POWER_ROLE                2
#define CFG_PORT_1_POWER_ROLE                2

/*Data Role supported values: 0 - Dual Role Data Not supported, 1 - Dual Role Date Supported */
#define CFG_PORT_0_DUAL_ROLE_DATA_SUPPORT    (1U << 2)
#define CFG_PORT_1_DUAL_ROLE_DATA_SUPPORT    (1U << 2)

/*Rp Value: 0 - Rd(Sink), 1 - Default USB Rp, 2 - 1.5A Rp, 3 - 3.0A Rp */
#define CFG_PORT_0_RP_CURRENT_VALUE          (3U << 3)
#define CFG_PORT_1_RP_CURRENT_VALUE          (3U << 3)

/*Port Enable: 0 - Port Disable; 1 - Port Enable*/
#define CFG_PORT_0_ENABLE                    (1U << 5)
#define CFG_PORT_1_ENABLE                    (1U << 5)

/*VCONN OCS Enable: 0 - Disable, 1 - Enable*/
#define CFG_PORT_0_VCONN_OCS_ENABLE          (0U << 9)
#define CFG_PORT_1_VCONN_OCS_ENABLE          (0U << 9)  

/********************************PIO Specific configuration******************************/
#define CFG_PORT_0_UPD_FAULT_IN_PIO_NO       0        //not support
#define CFG_PORT_1_UPD_FAULT_IN_PIO_NO       0

#define CFG_PORT_0_UPD_FAULT_IN_MODE         eINPUT_ACTIVE_LOW
#define CFG_PORT_1_UPD_FAULT_IN_MODE         eINPUT_ACTIVE_LOW

#define CFG_PORT_0_UPD_EN_VBUS               0
#define CFG_PORT_1_UPD_EN_VBUS               0
#define CFG_PORT_0_UPD_EN_VBUS_PIO_MODE      ePUSH_PULL_ACTIVE_HIGH
#define CFG_PORT_1_UPD_EN_VBUS_PIO_MODE      ePUSH_PULL_ACTIVE_HIGH

#define CFG_PORT_0_UPD_EN_SNK                0
#define CFG_PORT_1_UPD_EN_SNK                0
#define CFG_PORT_0_UPD_EN_SNK_PIO_MODE       ePUSH_PULL_ACTIVE_HIGH
#define CFG_PORT_1_UPD_EN_SNK_PIO_MODE       ePUSH_PULL_ACTIVE_HIGH

/* Note: UPD PIO9 is shared between HPD and VSEL2 pin functionalities. 
   Hence, INCLUDE_UPD_HPD is disabled by default. If user application
   wishes to use HPD feature, then VSEL2 functionality has to be mapped
   with any MCU pin since HPD pin can only be an UPD PIO */
#define CFG_PORT_0_HPD_IO                    0
#define CFG_PORT_1_HPD_IO                    0

/**********************Fault Related configuration**************************/
#define CFG_OVER_VOLTAGE_FACTOR              115U
#define CFG_UNDER_VOLTAGE_FACTOR             85U
#define CFG_FAULT_IN_OCS_DEBOUNCE_MS         5U
#define CFG_VCONN_OCS_DEBOUNCE_IN_MS         2U
#define CFG_MAX_VBUS_POWER_FAULT_COUNT       3U
#define CFG_MAX_VCONN_FAULT_COUNT            3U
#define CFG_POWER_GOOD_TIMER_MS              10000U
#define CFG_MAX_PORT_CURRENT_IN_10mA         300U 

/*********************************************************************************/
/*********************************PDO Configuration ******************************/
/**********************************************************************************/

/********************************************************************************/
/**********************************Port 0****************************************/
/*********************************************************************************/
/*Port 0 common PDO configuration for Source and Sink*/
#define CFG_PORT_0_DUAL_ROLE_POWER           1U 
#define CFG_PORT_0_DUAL_ROLE_DATA            1U

/*Port - 0 Source PDO Configuration***/
#ifndef CFG_PORT_0_SOURCE_NUM_OF_PDOS
#define CFG_PORT_0_SOURCE_NUM_OF_PDOS        2U
#endif

#ifndef CFG_PORT_5V_CURRENT
#define CFG_PORT_5V_CURRENT                   3000U
#endif

#define CFG_PORT_0_SOURCE_USB_SUSP           0U
#define CFG_PORT_0_SOURCE_UNCONSTARINED_PWR  1U
#define CFG_PORT_0_SOURCE_USB_COMM           0U
#define CFG_PORT_0_SOURCE_PDO_1     CFG_FORM_SOURCE_FIXED_PDO1(5000U, CFG_PORT_5V_CURRENT,\
                                    CFG_PORT_0_DUAL_ROLE_DATA, \
                                    CFG_PORT_0_SOURCE_USB_COMM, \
                                    CFG_PORT_0_SOURCE_USB_SUSP,  \
                                    CFG_PORT_0_SOURCE_UNCONSTARINED_PWR, \
                                    CFG_PORT_0_DUAL_ROLE_POWER);
#define CFG_PORT_0_SOURCE_PDO_2     CFG_FORM_FIXED_PDOx(9000U, 3000U)
#define CFG_PORT_0_SOURCE_PDO_3     CFG_FORM_FIXED_PDOx(12000U, 3000U)
#define CFG_PORT_0_SOURCE_PDO_4     CFG_FORM_FIXED_PDOx(15000U, 3000U)
#define CFG_PORT_0_SOURCE_PDO_5     CFG_FORM_FIXED_PDOx(20000U, 3250U)
#define CFG_PORT_0_SOURCE_PDO_6     CFG_FORM_FIXED_PDOx(0,0)
#define CFG_PORT_0_SOURCE_PDO_7     CFG_FORM_FIXED_PDOx(0,0)   

/*Port - 0 EPR Source PDO Configuration***/
#define CFG_PORT_0_SOURCE_PDO_8     CFG_FORM_FIXED_PDOx(28000U,5000U)
#define CFG_PORT_0_SOURCE_PDO_9     CFG_FORM_EPR_APDO(15000U, 28000U, 0, 140U)
#define CFG_PORT_0_SOURCE_PDO_10    CFG_FORM_EPR_APDO(0, 0, 0, 0)
#define CFG_PORT_0_SOURCE_PDO_11    CFG_FORM_EPR_APDO(0, 0, 0, 0)

/*Port - 0 Sink PDO configuration*/
#define CFG_PORT_0_SINK_NUM_OF_PDOS          1U
#define CFG_PORT_0_SINK_HIGHER_CAPABILITY    1U
#define CFG_PORT_0_SINK_UNCONSTRAINED_PWR    1U 
#define CFG_PORT_0_SINK_USB_COMM             1U
#define CFG_PORT_0_SINK_FRS_CURRENT          0U

#define CFG_PORT_0_SINK_PDO_1     CFG_FORM_SINK_FIXED_PDO1(5000U, 3000U, \
                                    CFG_PORT_0_SINK_FRS_CURRENT, \
                                    CFG_PORT_0_DUAL_ROLE_DATA, \
                                    CFG_PORT_0_SINK_USB_COMM, \
                                    CFG_PORT_0_SINK_UNCONSTRAINED_PWR, \
                                    CFG_PORT_0_SINK_HIGHER_CAPABILITY, \
                                    CFG_PORT_0_DUAL_ROLE_POWER);
#define CFG_PORT_0_SINK_PDO_2     CFG_FORM_FIXED_PDOx(0,0)   
#define CFG_PORT_0_SINK_PDO_3     CFG_FORM_FIXED_PDOx(0,0)   
#define CFG_PORT_0_SINK_PDO_4     CFG_FORM_FIXED_PDOx(0,0)
#define CFG_PORT_0_SINK_PDO_5     CFG_FORM_FIXED_PDOx(0,0)   
#define CFG_PORT_0_SINK_PDO_6     CFG_FORM_FIXED_PDOx(0,0)
#define CFG_PORT_0_SINK_PDO_7     CFG_FORM_FIXED_PDOx(0,0) 

/********************************************************************************/
/**********************************Port 1****************************************/
/*********************************************************************************/
/*Port 1 Dock common PDO configuration for Source and Sink*/
#define CFG_PORT_1_DUAL_ROLE_POWER           1U 
#define CFG_PORT_1_DUAL_ROLE_DATA            1U

/*Port - 1 Dock Source PDO Configuration***/
#define CFG_PORT_1_SOURCE_NUM_OF_PDOS        4U
#define CFG_PORT_1_SOURCE_USB_SUSP           0U
#define CFG_PORT_1_SOURCE_UNCONSTARINED_PWR  1U
#define CFG_PORT_1_SOURCE_USB_COMM           0U
/* Source APDO defines */
#define CFG_PORT_1_SOURCE_APDO_5_MIN_VOLTAGE    3300U
#define CFG_PORT_1_SOURCE_APDO_5_MAX_VOLTAGE    21000U
#define CFG_PORT_1_SOURCE_APDO_5_MAX_CURRENT    3000U
#define CFG_PORT_1_SOURCE_APDO_5_PPS_PWR_LTD    0U

#define CFG_PORT_1_SOURCE_PDO_1     CFG_FORM_SOURCE_FIXED_PDO1(5000U, 3000U, \
                                    CFG_PORT_1_DUAL_ROLE_DATA, \
                                    CFG_PORT_1_SOURCE_USB_COMM, \
                                    CFG_PORT_1_SOURCE_USB_SUSP,  \
                                    CFG_PORT_1_SOURCE_UNCONSTARINED_PWR, \
                                    CFG_PORT_1_DUAL_ROLE_POWER);
#define CFG_PORT_1_SOURCE_PDO_2     CFG_FORM_FIXED_PDOx(9000U,3000U)    
#define CFG_PORT_1_SOURCE_PDO_3     CFG_FORM_FIXED_PDOx(15000U,3000U)   
#define CFG_PORT_1_SOURCE_PDO_4     CFG_FORM_FIXED_PDOx(20000U,3000U)
#define CFG_PORT_1_SOURCE_PDO_5     CFG_FORM_FIXED_PDOx(0,0)   
#define CFG_PORT_1_SOURCE_PDO_6     CFG_FORM_FIXED_PDOx(0,0)
#define CFG_PORT_1_SOURCE_PDO_7     CFG_FORM_FIXED_PDOx(0,0)

/*Port - 1 Dock Sink PDO configuration*/
#define CFG_PORT_1_SINK_NUM_OF_PDOS          1U
#define CFG_PORT_1_SINK_HIGHER_CAPABILITY    1U
#define CFG_PORT_1_SINK_UNCONSTRAINED_PWR    1U 
#define CFG_PORT_1_SINK_USB_COMM             0U
#define CFG_PORT_1_SINK_FRS_CURRENT          0U

#define CFG_PORT_1_SINK_PDO_1     CFG_FORM_SINK_FIXED_PDO1(5000U, 0,\
                                    CFG_PORT_1_SINK_FRS_CURRENT, \
                                    CFG_PORT_1_DUAL_ROLE_DATA, \
                                    CFG_PORT_1_SINK_USB_COMM, \
                                    CFG_PORT_1_SINK_UNCONSTRAINED_PWR, \
                                    CFG_PORT_1_SINK_HIGHER_CAPABILITY, \
                                    CFG_PORT_1_DUAL_ROLE_POWER); 
#define CFG_PORT_1_SINK_PDO_2     CFG_FORM_FIXED_PDOx(0,0)    
#define CFG_PORT_1_SINK_PDO_3     CFG_FORM_FIXED_PDOx(0,0)   
#define CFG_PORT_1_SINK_PDO_4     CFG_FORM_FIXED_PDOx(0,0)
#define CFG_PORT_1_SINK_PDO_5     CFG_FORM_FIXED_PDOx(0,0)   
#define CFG_PORT_1_SINK_PDO_6     CFG_FORM_FIXED_PDOx(0,0)
#define CFG_PORT_1_SINK_PDO_7     CFG_FORM_FIXED_PDOx(0,0) 


/********************************Sink Specific Configuration********************************/
/*u8SinkConfigSel configuration*/
/*Sink Mode A - 0x00, Mode B - 0x01*/
#define CFG_PORT_0_SINK_MODE            0x00
#define CFG_PORT_1_SINK_MODE            0x00
/*Sink Give Back Flag - 0 - Disabled, 1 - Enabled*/
#define CFG_PORT_0_SINK_GIVE_BACK_FLAG      (0U << 2)
#define CFG_PORT_1_SINK_GIVE_BACK_FLAG      (0U << 2)
/*Sink USB Suspend support - 0- Disabled, 1-Enabled*/
#define CFG_PORT_0_SINK_USB_SUSP            (0U << 3)
#define CFG_PORT_1_SINK_USB_SUSP            (0U << 3)

#define CFG_PORT_0_SINK_MIN_OPERATING_CURRENT_InmA             1000U
#define CFG_PORT_0_SINK_MAX_OPERATING_CURRENT_InmA             3000U
#define CFG_PORT_1_SINK_MIN_OPERATING_CURRENT_InmA             0U
#define CFG_PORT_1_SINK_MAX_OPERATING_CURRENT_InmA             0U

#define CFG_PORT_0_SINK_PDO_1_PREFERRED_MIN_CURRENT 2000U
#define CFG_PORT_0_SINK_PDO_2_PREFERRED_MIN_CURRENT 2000U
#define CFG_PORT_0_SINK_PDO_3_PREFERRED_MIN_CURRENT 2000U
#define CFG_PORT_0_SINK_PDO_4_PREFERRED_MIN_CURRENT 2000U
#define CFG_PORT_0_SINK_PDO_5_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_0_SINK_PDO_6_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_0_SINK_PDO_7_PREFERRED_MIN_CURRENT 0U

#define CFG_PORT_1_SINK_PDO_1_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_1_SINK_PDO_2_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_1_SINK_PDO_3_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_1_SINK_PDO_4_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_1_SINK_PDO_5_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_1_SINK_PDO_6_PREFERRED_MIN_CURRENT 0U
#define CFG_PORT_1_SINK_PDO_7_PREFERRED_MIN_CURRENT 0U

/*********************DAC_I defines******************/
#define CFG_PORT_0_SINK_DAC_I_MAX_OP_VOLTAGE             2500U
#define CFG_PORT_0_SINK_DAC_I_MIN_OP_VOLTAGE             0U
#define CFG_PORT_0_SINK_DAC_I_CUR_INDICATION_MAX         5000U
/*Configuration value for u8DAC_I_Direction*/
/*0 - High amperage = Max Voltage, 1- High amperage = Min Voltage*/
#define CFG_PORT_0_SINK_DAC_I_DIR      0U

/**************************Sink Caps Extd defines*****************************/
/*Sink Capabilities Extended Data Block (From Table 6-60 of USB PD Spec 3.0) 
  Offset  Field               Size 
    0     VID                 2
    2     PID                 2
    4     XID                 4
    8     FW Version          1 
    9     HW Version          1 
    10    SKEDB Version       1 
    11    Load Step           1 
    12    Sink Load           2
          Characteristics
    14    Compliance          1 
    15    Touch Temp          1
    16    Battery Info        1 
    17    Sink Modes          1 
    18    Sink Minimum PDP    1
    19    Sink Operational    1 
          PDP
    20    Sink Maximum PDP    1
  */
#define CFG_PORT_0_SINK_CAPS_EXTD_VID                       CFG_VENDOR_ID
#define CFG_PORT_0_SINK_CAPS_EXTD_PID                       CFG_PRODUCT_ID
#define CFG_PORT_0_SINK_CAPS_EXTD_XID                       0U
#define CFG_PORT_0_SINK_CAPS_EXTD_FW_VERSION                0U
#define CFG_PORT_0_SINK_CAPS_EXTD_HW_VERSION                CFG_HW_VERSION
#define CFG_PORT_0_SINK_CAPS_EXTD_SKEDB_VERSION             1U
#define CFG_PORT_0_SINK_CAPS_EXTD_LOAD_STEP                 0U
#define CFG_PORT_0_SINK_CAPS_EXTD_LOAD_CHARACTERISTICS      0U
#define CFG_PORT_0_SINK_CAPS_EXTD_COMPLIANCE                0U
#define CFG_PORT_0_SINK_CAPS_EXTD_TOUCH_TEMP                0U
#define CFG_PORT_0_SINK_CAPS_EXTD_BATTERY_INFO              0U
#define CFG_PORT_0_SINK_CAPS_EXTD_SINK_MODES                4U
#define CFG_PORT_0_SINK_CAPS_EXTD_MIN_PDP_In_WATT           5U
#define CFG_PORT_0_SINK_CAPS_EXTD_OPERATIONAL_PDP_In_WATT   60U
#define CFG_PORT_0_SINK_CAPS_EXTD_MAX_PDP_In_WATT           60U 

#define CFG_PORT_1_SINK_CAPS_EXTD_VID                       CFG_VENDOR_ID
#define CFG_PORT_1_SINK_CAPS_EXTD_PID                       CFG_PRODUCT_ID
#define CFG_PORT_1_SINK_CAPS_EXTD_XID                       0U
#define CFG_PORT_1_SINK_CAPS_EXTD_FW_VERSION                0U
#define CFG_PORT_1_SINK_CAPS_EXTD_HW_VERSION                CFG_HW_VERSION
#define CFG_PORT_1_SINK_CAPS_EXTD_SKEDB_VERSION             1U
#define CFG_PORT_1_SINK_CAPS_EXTD_LOAD_STEP                 0U
#define CFG_PORT_1_SINK_CAPS_EXTD_LOAD_CHARACTERISTICS      0U
#define CFG_PORT_1_SINK_CAPS_EXTD_COMPLIANCE                0U
#define CFG_PORT_1_SINK_CAPS_EXTD_TOUCH_TEMP                0U
#define CFG_PORT_1_SINK_CAPS_EXTD_BATTERY_INFO              0U
#define CFG_PORT_1_SINK_CAPS_EXTD_SINK_MODES                4U
#define CFG_PORT_1_SINK_CAPS_EXTD_MIN_PDP_In_WATT           0U
#define CFG_PORT_1_SINK_CAPS_EXTD_OPERATIONAL_PDP_In_WATT   0U
#define CFG_PORT_1_SINK_CAPS_EXTD_MAX_PDP_In_WATT           0U 

/**************************Role Swap Policy defines*****************************/
#define CFG_PORT_0_AS_DFP_REQUEST_DR_SWAP             1 
#define CFG_PORT_0_AS_UFP_REQUEST_DR_SWAP             0
#define CFG_PORT_0_AS_DFP_ACCEPT_DR_SWAP              1 
#define CFG_PORT_0_AS_UFP_ACCEPT_DR_SWAP              0 
#define CFG_PORT_0_AS_SRC_REQUEST_PR_SWAP             0
#define CFG_PORT_0_AS_SNK_REQUEST_PR_SWAP             0
#define CFG_PORT_0_AS_SRC_ACCEPT_PR_SWAP              1
#define CFG_PORT_0_AS_SNK_ACCEPT_PR_SWAP              1
#define CFG_PORT_0_AS_VCONN_SRC_REQ_VCONN_SWAP        0
#define CFG_PORT_0_AS_NOT_VCONN_SRC_REQ_VCONN_SWAP    0
#define CFG_PORT_0_AS_VCONN_SRC_ACCEPT_VCONN_SWAP     0
#define CFG_PORT_0_AS_NOT_VCONN_SRC_ACCEPT_VCONN_SWAP 0

#define CFG_PORT_1_AS_DFP_REQUEST_DR_SWAP             1
#define CFG_PORT_1_AS_UFP_REQUEST_DR_SWAP             0
#define CFG_PORT_1_AS_DFP_ACCEPT_DR_SWAP              1
#define CFG_PORT_1_AS_UFP_ACCEPT_DR_SWAP              0
#define CFG_PORT_1_AS_SRC_REQUEST_PR_SWAP             0
#define CFG_PORT_1_AS_SNK_REQUEST_PR_SWAP             1
#define CFG_PORT_1_AS_SRC_ACCEPT_PR_SWAP              0
#define CFG_PORT_1_AS_SNK_ACCEPT_PR_SWAP              1
#define CFG_PORT_1_AS_VCONN_SRC_REQ_VCONN_SWAP        1
#define CFG_PORT_1_AS_NOT_VCONN_SRC_REQ_VCONN_SWAP    0
#define CFG_PORT_1_AS_VCONN_SRC_ACCEPT_VCONN_SWAP     1
#define CFG_PORT_1_AS_NOT_VCONN_SRC_ACCEPT_VCONN_SWAP 0

/*********************** Feature Select Defines *************************************/
#define CFG_PORT_0_ENABLE_VDM_SUPPORT                 (INCLUDE_PD_VDM << 1)
#define CFG_PORT_1_ENABLE_VDM_SUPPORT                 (0U << 1)

#ifdef CONFIG_USER_USB_BILLBOARD_ON
#define CFG_PORT_0_ENABLE_AME_MONITORING              (1U << 2)
#else
#define CFG_PORT_0_ENABLE_AME_MONITORING              (0U << 2)
#endif
#define CFG_PORT_1_ENABLE_AME_MONITORING              (0U << 2)

/* Note: VDM defines are set to 0 by default. Users shall input necessary
   data relevant to their application. Refer section 6.4.4.3.1 of USB
   Power Delivery Specification v3.0 for detailed information on
   Discover Identity */
/******************* PD Identity Count Defines **************************/
#define CFG_PORT_0_PD_IDENTITY_COUNT                   4U
#define CFG_PORT_1_PD_IDENTITY_COUNT                   0U

/**************** ID Header VDO Defines *********************************/
#define CFG_PORT_0_ID_HEADER_VDO_USB_HOST_CAPABLE         0U
#define CFG_PORT_0_ID_HEADER_VDO_USB_DEVICE_CAPABLE       1U
#define CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_UFP            2U
#define CFG_PORT_0_ID_HEADER_VDO_MODAL_OPR_SUPPORTED      1U
#define CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_DFP            0U
#define CFG_PORT_0_ID_HEADER_VDO_CONNECTOR_TYPE           2U
#define CFG_PORT_0_ID_HEADER_VDO_USB_VENDOR_ID            0x380CU /* hisense=0x380C dell=0x413C lenovo=0x17EF*/

#define CFG_NS_ID_HEADER_VDO_USB_VENDOR_ID                0x057EU // ns device

#define CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_UFP_PD2        5U /* PD2.0=5(AMA) */
#define CFG_PORT_0_ID_HEADER_VDO_CONNECTOR_TYPE_PD2       0U /* PD2.0=0 */
#define CFG_PORT_1_ID_HEADER_VDO_USB_HOST_CAPABLE         0U
#define CFG_PORT_1_ID_HEADER_VDO_USB_DEVICE_CAPABLE       0U
#define CFG_PORT_1_ID_HEADER_VDO_PROD_TYPE_UFP            0U
#define CFG_PORT_1_ID_HEADER_VDO_MODAL_OPR_SUPPORTED      0U
#define CFG_PORT_1_ID_HEADER_VDO_PROD_TYPE_DFP            0U
#define CFG_PORT_1_ID_HEADER_VDO_CONNECTOR_TYPE           0U
#define CFG_PORT_1_ID_HEADER_VDO_USB_VENDOR_ID            0U 

/**************** Cert Stat VDO Defines *********************************/
#define CFG_PORT_0_CERT_STAT_VDO_XID                  0U

#define CFG_PORT_1_CERT_STAT_VDO_XID                  0U

/******************* Product VDO Defines *********************************/
#define CFG_PORT_0_PROD_VDO_USB_PRODUCT_ID            0xB076U
#define CFG_PORT_0_PROD_VDO_BCD_DEVICE                0x0712U 

#define CFG_PORT_1_PROD_VDO_USB_PRODUCT_ID            0U
#define CFG_PORT_1_PROD_VDO_BCD_DEVICE                0U 

/******************* Product Type VDO Defines ****************************/
                /*************** UFP VDO 1 *************/
#define CFG_PORT_0_UFP_VDO_1_UFP_VDO_VERSION          0U
#define CFG_PORT_0_UFP_VDO_1_DEVICE_CAPABILITY        0U
#define CFG_PORT_0_UFP_VDO_1_CONNECTOR_TYPE           0U
#define CFG_PORT_0_UFP_VDO_1_ALTERNATE_MODES          0U
#define CFG_PORT_0_UFP_VDO_1_USB_HIGHEST_SPEED        0U 

#define CFG_PORT_1_UFP_VDO_1_UFP_VDO_VERSION          0U
#define CFG_PORT_1_UFP_VDO_1_DEVICE_CAPABILITY        0U
#define CFG_PORT_1_UFP_VDO_1_CONNECTOR_TYPE           0U
#define CFG_PORT_1_UFP_VDO_1_ALTERNATE_MODES          0U
#define CFG_PORT_1_UFP_VDO_1_USB_HIGHEST_SPEED        0U 

                /*************** UFP VDO 2 *************/
#define CFG_PORT_0_UFP_VDO_2_USB4_MIN_PWR             0U
#define CFG_PORT_0_UFP_VDO_2_USB4_MAX_PWR             0U
#define CFG_PORT_0_UFP_VDO_2_USB3_MIN_PWR             0U
#define CFG_PORT_0_UFP_VDO_2_USB3_MAX_PWR             0U

#define CFG_PORT_1_UFP_VDO_2_USB4_MIN_PWR             0U
#define CFG_PORT_1_UFP_VDO_2_USB4_MAX_PWR             0U
#define CFG_PORT_1_UFP_VDO_2_USB3_MIN_PWR             0U
#define CFG_PORT_1_UFP_VDO_2_USB3_MAX_PWR             0U

                /*************** DFP VDO ***************/
#define CFG_PORT_0_DFP_VDO_DFP_VDO_VERSION            0U
#define CFG_PORT_0_DFP_VDO_DFP_HOST_CAPABILITY        0U
#define CFG_PORT_0_DFP_VDO_DFP_CONNECTOR_TYPE         0U
#define CFG_PORT_0_DFP_VDO_DFP_PORT_NUMBER            0U

#define CFG_PORT_1_DFP_VDO_DFP_VDO_VERSION            0U
#define CFG_PORT_1_DFP_VDO_DFP_HOST_CAPABILITY        0U
#define CFG_PORT_1_DFP_VDO_DFP_CONNECTOR_TYPE         0U
#define CFG_PORT_1_DFP_VDO_DFP_PORT_NUMBER            0U

/*************************** SVID Defines ****************************/
                /*************** SVIDs ***************/
#define CFG_PORT_0_SVID_0                             0xFF01U
#define CFG_PORT_0_SVID_1                             0x380CU

#define CFG_PORT_1_SVID_0                             0U
#define CFG_PORT_1_SVID_1                             0U

                /************* SVIDs Count ***********/
#define CFG_PORT_0_SVID_COUNT                         2U
#define CFG_PORT_1_SVID_COUNT                         0U

/*************************** Mode Defines ****************************/
                /*************** Modes ***************/
#define CFG_PORT_0_SVID_0_MODE_0                      0x00140045U
#define CFG_PORT_0_SVID_0_MODE_1                      0U

#define CFG_PORT_0_SVID_1_MODE_0                      0U
#define CFG_PORT_0_SVID_1_MODE_1                      0U

#define CFG_PORT_1_SVID_0_MODE_0                      0U
#define CFG_PORT_1_SVID_0_MODE_1                      0U
#define CFG_PORT_1_SVID_1_MODE_0                      0U
#define CFG_PORT_1_SVID_1_MODE_1                      0U

                /*************** Modes Count ***************/
#define CFG_PORT_0_SVID_0_MODES_COUNT                 1U
#define CFG_PORT_0_SVID_1_MODES_COUNT                 0U

#define CFG_PORT_1_SVID_0_MODES_COUNT                 1U
#define CFG_PORT_1_SVID_1_MODES_COUNT                 0U

                /************ Start Mode Index **************/
#define CFG_PORT_0_SVID_0_START_MODE_INDEX            (0U << 3)
#define CFG_PORT_0_SVID_1_START_MODE_INDEX            (0U << 3)

#define CFG_PORT_1_SVID_0_START_MODE_INDEX            (0U << 3)
#define CFG_PORT_1_SVID_1_START_MODE_INDEX            (0U << 3) 

/*****************Defines to form PDOs ****************************************/
/* Macro used to form Fixed PDO 1 */
/*Source PDO 
  B31-B30   - Supply Type
  B29       - Dual Power role
  B28       - USB Suspend supported
  B27       - UnConstrained Power
  B26       - USB Communication capable
  B25       - Dual-Role Data
  B24       - Unchunked extended message
  B23       - EPR Mode Capable
  B22       - Reserved
  B21-B20   - Peak Current
  B19-B10   - Voltage in 50mV units
  B9-B0     - Maximum current in 10mA units */
#define CFG_FORM_SOURCE_FIXED_PDO1(voltage,current,DualRoleData,usbCommn,usbSusp,unconstrainedPwr,isDrp) \
    (((isDrp) << 29) | \
    ((usbSusp) << 28) | \
    ((unconstrainedPwr) << 27) | \
    ((usbCommn) << 26) | \
    ((DualRoleData) << 25) |\
    ((CFG_EPR_ENABLE) << 23) |\
    (((voltage)/50) << 10) | \
    ((current)/10))            

/*Sink PDO 
  B31-B30   - Supply Type
  B29       - Dual Power role
  B28       - Higher Capability
  B27       - UnConstrained Power
  B26       - USB Communication capable
  B25       - Dual-Role Data
  B24-B23   - Fast Role Swap required USB Type-C current
  B22-B20   - Reserved
  B19-B10   - Voltage in 50mV units
  B9-B0     - Maximum current in 10mA units */
/* Macro used to form Sink Fixed PDO 1 */
#define CFG_FORM_SINK_FIXED_PDO1(voltage,current,FRSCurrent,DualRoleData,usbCommn,unconstrainedPwr,HigherCapability,isDrp)  \
    (((isDrp) << 29) | \
    (((HigherCapability) << 28)) | \
    ((unconstrainedPwr) << 27) | \
    ((usbCommn) << 26) | \
    ((DualRoleData) << 25) |\
    ((FRSCurrent) << 23) |\
    (((voltage)/50) << 10) | \
    ((current)/10))  

/* Macro used to form Fixed PDOs 2 to 7 */
#define CFG_FORM_FIXED_PDOx(voltage,current)   ((((voltage)/50) << 10) | ((current)/10))

/*APDO Source
  B31-30    -11b Augmented Power Data Object
  B29-28    - 00b Programmable Power Supply
  B27       - PPS Power Limited
  B26-25    - Reserved
  B24-17    - Maximum voltage in 100mV increment 
  B16       - Reserved
  B15-8     - Minimum voltage in 100mV increment 
  B7        - Reserved
  B6-0      - Maximum current in 50mA increment */
/* Macro used to form PPS APDO */
#define CFG_FORM_PPS_APDO(minVolt,maxVolt,maxCurrent,pwrLtd)\
    (((0x3U) << 30U) |\
    ((pwrLtd) << 27U) | \
    (((maxVolt) / 100U) << 17U) | \
    (((minVolt) / 100U) << 8U) | \
    ((maxCurrent) / 50U)) 

/*EPR AVS APDO Source
  B31-30    -11b Augmented Power Data Object
  B29-28    - 01b EPR AVS
  B27-B26   - Peak Current
  B25-17    - Maximum voltage in 100mV increment
  B16       - Reserved
  B15-8     - Minimum voltage in 100mV increment
  B7-0      - PDP in 1W increments */
/* Macro used to form PPS APDO */
#define CFG_FORM_EPR_APDO(minVolt,maxVolt,peakCurrent,pwrLtd)\
    (((0x3U) << 30U) |\
    ((0x01) << 28U) | \
    (peakCurrent << 26U) | \
    (((maxVolt) / 100U) << 17U) | \
    (((minVolt) / 100U) << 8U) | \
    (pwrLtd)) 

/***********************Defines to form role swap policy************************/
#define CFG_PORT_0_ROLE_SWAP_POLICY  CFG_FORM_ROLE_SWAP_POLICY(CFG_PORT_0_AS_DFP_REQUEST_DR_SWAP, \
 CFG_PORT_0_AS_UFP_REQUEST_DR_SWAP, CFG_PORT_0_AS_DFP_ACCEPT_DR_SWAP, CFG_PORT_0_AS_UFP_ACCEPT_DR_SWAP,\
 CFG_PORT_0_AS_SRC_REQUEST_PR_SWAP, CFG_PORT_0_AS_SNK_REQUEST_PR_SWAP, CFG_PORT_0_AS_SRC_ACCEPT_PR_SWAP,\
 CFG_PORT_0_AS_SNK_ACCEPT_PR_SWAP, CFG_PORT_0_AS_VCONN_SRC_REQ_VCONN_SWAP, CFG_PORT_0_AS_NOT_VCONN_SRC_REQ_VCONN_SWAP,\
 CFG_PORT_0_AS_VCONN_SRC_ACCEPT_VCONN_SWAP, CFG_PORT_0_AS_NOT_VCONN_SRC_ACCEPT_VCONN_SWAP);

#define CFG_PORT_1_ROLE_SWAP_POLICY CFG_FORM_ROLE_SWAP_POLICY(CFG_PORT_1_AS_DFP_REQUEST_DR_SWAP, \
 CFG_PORT_1_AS_UFP_REQUEST_DR_SWAP, CFG_PORT_1_AS_DFP_ACCEPT_DR_SWAP, CFG_PORT_1_AS_UFP_ACCEPT_DR_SWAP,\
 CFG_PORT_1_AS_SRC_REQUEST_PR_SWAP, CFG_PORT_1_AS_SNK_REQUEST_PR_SWAP, CFG_PORT_1_AS_SRC_ACCEPT_PR_SWAP,\
 CFG_PORT_1_AS_SNK_ACCEPT_PR_SWAP, CFG_PORT_1_AS_VCONN_SRC_REQ_VCONN_SWAP, CFG_PORT_1_AS_NOT_VCONN_SRC_REQ_VCONN_SWAP,\
 CFG_PORT_1_AS_VCONN_SRC_ACCEPT_VCONN_SWAP, CFG_PORT_1_AS_NOT_VCONN_SRC_ACCEPT_VCONN_SWAP);

#define CFG_FORM_ROLE_SWAP_POLICY(AsDfp_Request_DRSwap, AsUfp_Request_DRSwap, \
 AsDfp_Accept_DRSwap, AsUfp_Accept_DRSwap, AsSrc_Request_PRSwap, AsSnk_Request_PRSwap,\
 AsSrc_Accept_PRSwap, AsSnk_Accept_PRSwap, AsVCONNSrc_Req_VCONNSwap, AsNotVCONNSrc_Req_VCONNSwap,\
 AsVCONNSrc_Accept_VCONNSwap, AsNotVCONNSrc_Accept_VCONNSwap) ( (AsDfp_Request_DRSwap << 0) | \
 (AsUfp_Request_DRSwap << 1) | (AsDfp_Accept_DRSwap << 2) | (AsUfp_Accept_DRSwap << 3) \
 | (AsSrc_Request_PRSwap << 4) | (AsSnk_Request_PRSwap << 5) | (AsSrc_Accept_PRSwap << 6) \
 | (AsSnk_Accept_PRSwap << 7) | (AsVCONNSrc_Req_VCONNSwap << 8) | (AsNotVCONNSrc_Req_VCONNSwap << 9)\
 | (AsVCONNSrc_Accept_VCONNSwap << 10) | (AsNotVCONNSrc_Accept_VCONNSwap << 11))


/*Defines for getting default power role configured to a port from 
 * gasCfgStatusData.sPerPortData[u8PortNum].u32CfgData variable*/
/*CFG_GET_CONFIGURED_POWER_ROLE(u8PortNum) will return one of the following values
    - 0 (Sink)
    - 1 (Source)
    - 2 (DRP) */
#define CFG_GET_CONFIGURED_POWER_ROLE(u8PortNum)  \
    (gasCfgStatusData.sPerPortData[u8PortNum].u32CfgData & (BIT(0)|BIT(1)))

/***********************Defines to form VDM Header************************/
/* VDM Header (From Table 6-25 Structured VDM Header of PD 3.0 Spec)
   B31-16  - Standard or Vendor ID (SVID) 
   B15     - VDM Type 
   B14-13  - Structured VDM Version
   B12-11  - Reserved 
   B10-8   - Object Position 
   B7-6    - Command Type 
   B5      - Reserved 
   B4-0    - Command */

#define CFG_FORM_VDM_HEADER(svid,vdmType,svdmVersion,objPos,cmdType,cmd) \
    (((svid) << 16) | \
    ((vdmType) << 15) | \
    ((svdmVersion) << 13) | \
    ((objPos) << 8) | \
    ((cmdType) << 6) | \
    (cmd))

/****************** Defines to configure Discover Identity ****************/
/***************************** ID HEADER VDO*************************/
/* ID Header VDO (From Table 6-29 ID Header VDO of PD 3.0 Spec)
   B31     - USB Commn Capable as USB Host
   B30     - USB Commn Capable as USB Device 
   B29-27  - Product Type (UFP/Cable Plug)
   B26     - Modal Operation Supported
   B25-23  - Product Type (DFP)
   B22-21  - Connector Type 
   B20-16  - Reserved 
   B15-0   - USB Vendor ID */

#define CFG_FORM_ID_HEADER_VDO(host,device,prodTypeUFP,modalOpr,prodTypeDFP,connectorType,vendorID) \
    (((host) << 31) | \
    ((device) << 30) | \
    ((prodTypeUFP) << 27) | \
    ((modalOpr) << 26) | \
    ((prodTypeDFP) << 23) | \
    ((connectorType) << 21) | \
    (vendorID))

#define CFG_PORT_0_ID_HEADER_VDO   CFG_FORM_ID_HEADER_VDO(CFG_PORT_0_ID_HEADER_VDO_USB_HOST_CAPABLE, \
        CFG_PORT_0_ID_HEADER_VDO_USB_DEVICE_CAPABLE, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_UFP, \
        CFG_PORT_0_ID_HEADER_VDO_MODAL_OPR_SUPPORTED, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_DFP, \
        CFG_PORT_0_ID_HEADER_VDO_CONNECTOR_TYPE, CFG_PORT_0_ID_HEADER_VDO_USB_VENDOR_ID)

#define CFG_PORT_0_ID_HEADER_VDO_PD2   CFG_FORM_ID_HEADER_VDO(CFG_PORT_0_ID_HEADER_VDO_USB_HOST_CAPABLE, \
                CFG_PORT_0_ID_HEADER_VDO_USB_DEVICE_CAPABLE, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_UFP_PD2, \
                CFG_PORT_0_ID_HEADER_VDO_MODAL_OPR_SUPPORTED, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_DFP, \
                CFG_PORT_0_ID_HEADER_VDO_CONNECTOR_TYPE_PD2, CFG_PORT_0_ID_HEADER_VDO_USB_VENDOR_ID)
#define CFG_PORT_1_ID_HEADER_VDO   CFG_FORM_ID_HEADER_VDO(CFG_PORT_1_ID_HEADER_VDO_USB_HOST_CAPABLE, \
        CFG_PORT_1_ID_HEADER_VDO_USB_DEVICE_CAPABLE, CFG_PORT_1_ID_HEADER_VDO_PROD_TYPE_UFP, \
        CFG_PORT_1_ID_HEADER_VDO_MODAL_OPR_SUPPORTED, CFG_PORT_1_ID_HEADER_VDO_PROD_TYPE_DFP, \
        CFG_PORT_1_ID_HEADER_VDO_CONNECTOR_TYPE, CFG_PORT_1_ID_HEADER_VDO_USB_VENDOR_ID)
        
#define CFG_PORT_1_ID_HEADER_VDO_PD2   CFG_FORM_ID_HEADER_VDO(CFG_PORT_1_ID_HEADER_VDO_USB_HOST_CAPABLE, \
                CFG_PORT_1_ID_HEADER_VDO_USB_DEVICE_CAPABLE, CFG_PORT_1_ID_HEADER_VDO_PROD_TYPE_UFP_PD2, \
                CFG_PORT_1_ID_HEADER_VDO_MODAL_OPR_SUPPORTED, CFG_PORT_1_ID_HEADER_VDO_PROD_TYPE_DFP, \
                CFG_PORT_1_ID_HEADER_VDO_CONNECTOR_TYPE_PD2, CFG_PORT_1_ID_HEADER_VDO_USB_VENDOR_ID)

#define CFG_PORT_NS_ID_HEADER_VDO   CFG_FORM_ID_HEADER_VDO(CFG_PORT_0_ID_HEADER_VDO_USB_HOST_CAPABLE, \
        CFG_PORT_0_ID_HEADER_VDO_USB_DEVICE_CAPABLE, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_UFP, \
        CFG_PORT_0_ID_HEADER_VDO_MODAL_OPR_SUPPORTED, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_DFP, \
        CFG_PORT_0_ID_HEADER_VDO_CONNECTOR_TYPE, CFG_NS_ID_HEADER_VDO_USB_VENDOR_ID)

#define CFG_PORT_NS_ID_HEADER_VDO_PD2   CFG_FORM_ID_HEADER_VDO(CFG_PORT_0_ID_HEADER_VDO_USB_HOST_CAPABLE, \
                CFG_PORT_0_ID_HEADER_VDO_USB_DEVICE_CAPABLE, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_UFP_PD2, \
                CFG_PORT_0_ID_HEADER_VDO_MODAL_OPR_SUPPORTED, CFG_PORT_0_ID_HEADER_VDO_PROD_TYPE_DFP, \
                CFG_PORT_0_ID_HEADER_VDO_CONNECTOR_TYPE_PD2, CFG_NS_ID_HEADER_VDO_USB_VENDOR_ID)
/***************************** PRODUCT VDO*************************/
/* Product VDO (From Table 6-34 ID Product VDO of PD 3.0 Spec)
   B31-16     - USB Product ID
   B15-0      - bcd Device */

#define CFG_FORM_PRODUCT_VDO(productID,bcdDevice) \
    (((productID) << 16) | \
    (bcdDevice))

#define CFG_PORT_0_PRODUCT_VDO   CFG_FORM_PRODUCT_VDO(CFG_PORT_0_PROD_VDO_USB_PRODUCT_ID, \
                                 CFG_PORT_0_PROD_VDO_BCD_DEVICE)

#define CFG_PORT_1_PRODUCT_VDO   CFG_FORM_PRODUCT_VDO(CFG_PORT_1_PROD_VDO_USB_PRODUCT_ID, \
                                 CFG_PORT_1_PROD_VDO_BCD_DEVICE)

/******************* PRODUCT TYPE VDO - AMA VDO *********************/
/* AMA VDO (From Table 6-37 AMA VDO of PD 3.0 Spec)
   B31-28   - HW Version
   B27-24   - Firmware Version
   B23-21   - VDO Verison
   B20-8    - Reserved
   B7-5     - Vconn power
   B4       - Vconn required
   B3       - Vbus required
   B2-0     - USB SuperSpeed Signaling Support
   */
#define CFG_FORM_AMA_VDO(hdVersion,firmwareVersion,vdoVersion,vconnPwr,vconnRequire,vbusRequire,signalingSupport)   \
    ((hdVersion << 28)          | \
    (firmwareVersion << 24)     | \
    (vdoVersion << 21)     | \
    (vconnPwr << 8)     | \
    (vconnRequire << 5)     | \
    (vbusRequire << 4)     | \
    (signalingSupport))

/*fiexd */
#define CFG_PORT_0_AMA_VDO       CFG_FORM_AMA_VDO(0,0,0,0,0,0,1)

/******************* PRODUCT TYPE VDO - UFP VDO 1 *********************/
/* UFP VDO 1 (From Table 6-35 UFP VDO 1 of PD 3.0 Spec)
   B31-29  - UFP VDO Version 
   B28     - Reserved 
   B27-24  - Device Capability 
   B23-22  - Connector Type 
   B21-6   - Reserved  
   B5-3    - Alternate Modes
   B2-0    - USB Highest Speed */

#define CFG_FORM_UFP_VDO_1(vdoVer,devCapability,connectorType,altModes,usbSpeed) \
    (((vdoVer) << 29) | \
    ((devCapability) << 24) | \
    ((connectorType) << 22) | \
    ((altModes) << 3) | \
    (usbSpeed))

#define CFG_PORT_0_UFP_VDO_1    CFG_FORM_UFP_VDO_1(CFG_PORT_0_UFP_VDO_1_UFP_VDO_VERSION, \
        CFG_PORT_0_UFP_VDO_1_DEVICE_CAPABILITY, CFG_PORT_0_UFP_VDO_1_CONNECTOR_TYPE, \
        CFG_PORT_0_UFP_VDO_1_ALTERNATE_MODES, CFG_PORT_0_UFP_VDO_1_USB_HIGHEST_SPEED)

#define CFG_PORT_1_UFP_VDO_1    CFG_FORM_UFP_VDO_1(CFG_PORT_1_UFP_VDO_1_UFP_VDO_VERSION, \
        CFG_PORT_1_UFP_VDO_1_DEVICE_CAPABILITY, CFG_PORT_1_UFP_VDO_1_CONNECTOR_TYPE, \
        CFG_PORT_1_UFP_VDO_1_ALTERNATE_MODES, CFG_PORT_1_UFP_VDO_1_USB_HIGHEST_SPEED)

/******************* PRODUCT TYPE VDO - UFP VDO 2 *********************/
/* UFP VDO 2 (From Table 6-36 UFP VDO 2 of PD 3.0 Spec)
   B31-30  - Reserved
   B29-23  - USB4 Min Power
   B22-16  - USB4 Max Power 
   B15-14  - Reserved
   B13-7   - USB3 Min Power
   B6-0    - USB3 Max Power */

#define CFG_FORM_UFP_VDO_2(usb4MinPwr,usb4MaxPwr,usb3MinPwr,usb3MaxPwr) \
    (((usb4MinPwr) << 23) | \
    ((usb4MaxPwr) << 16) | \
    ((usb3MinPwr) << 7) | \
    (usb3MaxPwr))

#define CFG_PORT_0_UFP_VDO_2    CFG_FORM_UFP_VDO_2(CFG_PORT_0_UFP_VDO_2_USB4_MIN_PWR, \
        CFG_PORT_0_UFP_VDO_2_USB4_MAX_PWR, CFG_PORT_0_UFP_VDO_2_USB3_MIN_PWR, \
        CFG_PORT_0_UFP_VDO_2_USB3_MAX_PWR)

#define CFG_PORT_1_UFP_VDO_2    CFG_FORM_UFP_VDO_2(CFG_PORT_1_UFP_VDO_2_USB4_MIN_PWR, \
        CFG_PORT_1_UFP_VDO_2_USB4_MAX_PWR, CFG_PORT_1_UFP_VDO_2_USB3_MIN_PWR, \
        CFG_PORT_1_UFP_VDO_2_USB3_MAX_PWR)

/******************* PRODUCT TYPE VDO - DFP VDO *********************/
/* DFP VDO (From Table 6-37 DFP VDO of PD 3.0 Spec)
   B31-29  - DFP VDO Version
   B28-27  - Reserved
   B26-24  - Host Capability
   B23-22  - Connector Type
   B21-5   - Reserved
   B4-0    - Port Number */

#define CFG_FORM_DFP_VDO(vdoVersion,hostCapability,connectorType,portNum) \
    (((vdoVersion) << 29) | \
    ((hostCapability) << 24) | \
    ((connectorType) << 22) | \
    (portNum))

#define CFG_PORT_0_DFP_VDO    CFG_FORM_DFP_VDO(CFG_PORT_0_DFP_VDO_DFP_VDO_VERSION, \
        CFG_PORT_0_DFP_VDO_DFP_HOST_CAPABILITY, CFG_PORT_0_DFP_VDO_DFP_CONNECTOR_TYPE, \
        CFG_PORT_0_DFP_VDO_DFP_PORT_NUMBER)

#define CFG_PORT_1_DFP_VDO    CFG_FORM_DFP_VDO(CFG_PORT_1_DFP_VDO_DFP_VDO_VERSION, \
        CFG_PORT_1_DFP_VDO_DFP_HOST_CAPABILITY, CFG_PORT_1_DFP_VDO_DFP_CONNECTOR_TYPE, \
        CFG_PORT_1_DFP_VDO_DFP_PORT_NUMBER)

void PSF_LoadConfig(GLOBAL_CFG_STATUS_DATA *pasCfgStatusData); 
#ifdef HV_TYPEC_SUPPORT_NS_DEVICE
void PSF_SetNSConfig (UINT8 u8PortNum, GLOBAL_CFG_STATUS_DATA *pasCfgStatusData);
void PSF_ClrNSConfig (UINT8 u8PortNum, GLOBAL_CFG_STATUS_DATA *pasCfgStatusData);
#endif

#endif /* _PSFDRP_BOOTCFG_H */

/* *****************************************************************************
 End of File
 */
