#ifndef _HV_PAGE_HT7315_ISPTX1_H_
#define _HV_PAGE_HT7315_ISPTX1_H_

#ifndef HV_ISPTX1_BASE_ADDRESS
    #define HV_ISPTX1_BASE_ADDRESS                                         0x1105E800
#endif


#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE24                            (HV_ISPTX1_BASE_ADDRESS + 0x00)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE24_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane24

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane24  rs_tx_isptx1_isptx_sd_setting_reg_lane24;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane24 {
    unsigned int reg_isp_sd_set_reg_0_24                    : 8;
    unsigned int reg_isp_sd_set_reg_1_24                    : 8;
    unsigned int reg_isp_sd_set_reg_2_24                    : 8;
    unsigned int reg_isp_sd_set_reg_3_24                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane24(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane24*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE25                            (HV_ISPTX1_BASE_ADDRESS + 0x04)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE25_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane25

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane25  rs_tx_isptx1_isptx_sd_setting_reg_lane25;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane25 {
    unsigned int reg_isp_sd_set_reg_0_25                    : 8;
    unsigned int reg_isp_sd_set_reg_1_25                    : 8;
    unsigned int reg_isp_sd_set_reg_2_25                    : 8;
    unsigned int reg_isp_sd_set_reg_3_25                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane25(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane25*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE26                            (HV_ISPTX1_BASE_ADDRESS + 0x08)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE26_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane26

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane26  rs_tx_isptx1_isptx_sd_setting_reg_lane26;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane26 {
    unsigned int reg_isp_sd_set_reg_0_26                    : 8;
    unsigned int reg_isp_sd_set_reg_1_26                    : 8;
    unsigned int reg_isp_sd_set_reg_2_26                    : 8;
    unsigned int reg_isp_sd_set_reg_3_26                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane26(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane26*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE27                            (HV_ISPTX1_BASE_ADDRESS + 0x0C)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE27_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane27

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane27  rs_tx_isptx1_isptx_sd_setting_reg_lane27;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane27 {
    unsigned int reg_isp_sd_set_reg_0_27                    : 8;
    unsigned int reg_isp_sd_set_reg_1_27                    : 8;
    unsigned int reg_isp_sd_set_reg_2_27                    : 8;
    unsigned int reg_isp_sd_set_reg_3_27                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane27(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane27*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE28                            (HV_ISPTX1_BASE_ADDRESS + 0x10)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE28_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane28

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane28  rs_tx_isptx1_isptx_sd_setting_reg_lane28;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane28 {
    unsigned int reg_isp_sd_set_reg_0_28                    : 8;
    unsigned int reg_isp_sd_set_reg_1_28                    : 8;
    unsigned int reg_isp_sd_set_reg_2_28                    : 8;
    unsigned int reg_isp_sd_set_reg_3_28                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane28(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane28*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE29                            (HV_ISPTX1_BASE_ADDRESS + 0x14)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE29_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane29

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane29  rs_tx_isptx1_isptx_sd_setting_reg_lane29;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane29 {
    unsigned int reg_isp_sd_set_reg_0_29                    : 8;
    unsigned int reg_isp_sd_set_reg_1_29                    : 8;
    unsigned int reg_isp_sd_set_reg_2_29                    : 8;
    unsigned int reg_isp_sd_set_reg_3_29                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane29(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane29*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE30                            (HV_ISPTX1_BASE_ADDRESS + 0x18)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE30_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane30

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane30  rs_tx_isptx1_isptx_sd_setting_reg_lane30;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane30 {
    unsigned int reg_isp_sd_set_reg_0_30                    : 8;
    unsigned int reg_isp_sd_set_reg_1_30                    : 8;
    unsigned int reg_isp_sd_set_reg_2_30                    : 8;
    unsigned int reg_isp_sd_set_reg_3_30                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane30(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane30*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE31                            (HV_ISPTX1_BASE_ADDRESS + 0x1C)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE31_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane31

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane31  rs_tx_isptx1_isptx_sd_setting_reg_lane31;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane31 {
    unsigned int reg_isp_sd_set_reg_0_31                    : 8;
    unsigned int reg_isp_sd_set_reg_1_31                    : 8;
    unsigned int reg_isp_sd_set_reg_2_31                    : 8;
    unsigned int reg_isp_sd_set_reg_3_31                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane31(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane31*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE32                            (HV_ISPTX1_BASE_ADDRESS + 0x20)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE32_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane32

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane32  rs_tx_isptx1_isptx_sd_setting_reg_lane32;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane32 {
    unsigned int reg_isp_sd_set_reg_0_32                    : 8;
    unsigned int reg_isp_sd_set_reg_1_32                    : 8;
    unsigned int reg_isp_sd_set_reg_2_32                    : 8;
    unsigned int reg_isp_sd_set_reg_3_32                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane32(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane32*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE33                            (HV_ISPTX1_BASE_ADDRESS + 0x24)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE33_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane33

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane33  rs_tx_isptx1_isptx_sd_setting_reg_lane33;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane33 {
    unsigned int reg_isp_sd_set_reg_0_33                    : 8;
    unsigned int reg_isp_sd_set_reg_1_33                    : 8;
    unsigned int reg_isp_sd_set_reg_2_33                    : 8;
    unsigned int reg_isp_sd_set_reg_3_33                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane33(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane33*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE34                            (HV_ISPTX1_BASE_ADDRESS + 0x28)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE34_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane34

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane34  rs_tx_isptx1_isptx_sd_setting_reg_lane34;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane34 {
    unsigned int reg_isp_sd_set_reg_0_34                    : 8;
    unsigned int reg_isp_sd_set_reg_1_34                    : 8;
    unsigned int reg_isp_sd_set_reg_2_34                    : 8;
    unsigned int reg_isp_sd_set_reg_3_34                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane34(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane34*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE35                            (HV_ISPTX1_BASE_ADDRESS + 0x2C)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE35_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane35

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane35  rs_tx_isptx1_isptx_sd_setting_reg_lane35;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane35 {
    unsigned int reg_isp_sd_set_reg_0_35                    : 8;
    unsigned int reg_isp_sd_set_reg_1_35                    : 8;
    unsigned int reg_isp_sd_set_reg_2_35                    : 8;
    unsigned int reg_isp_sd_set_reg_3_35                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane35(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane35*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE36                            (HV_ISPTX1_BASE_ADDRESS + 0x30)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE36_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane36

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane36  rs_tx_isptx1_isptx_sd_setting_reg_lane36;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane36 {
    unsigned int reg_isp_sd_set_reg_0_36                    : 8;
    unsigned int reg_isp_sd_set_reg_1_36                    : 8;
    unsigned int reg_isp_sd_set_reg_2_36                    : 8;
    unsigned int reg_isp_sd_set_reg_3_36                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane36(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane36*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE37                            (HV_ISPTX1_BASE_ADDRESS + 0x34)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE37_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane37

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane37  rs_tx_isptx1_isptx_sd_setting_reg_lane37;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane37 {
    unsigned int reg_isp_sd_set_reg_0_37                    : 8;
    unsigned int reg_isp_sd_set_reg_1_37                    : 8;
    unsigned int reg_isp_sd_set_reg_2_37                    : 8;
    unsigned int reg_isp_sd_set_reg_3_37                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane37(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane37*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE38                            (HV_ISPTX1_BASE_ADDRESS + 0x38)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE38_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane38

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane38  rs_tx_isptx1_isptx_sd_setting_reg_lane38;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane38 {
    unsigned int reg_isp_sd_set_reg_0_38                    : 8;
    unsigned int reg_isp_sd_set_reg_1_38                    : 8;
    unsigned int reg_isp_sd_set_reg_2_38                    : 8;
    unsigned int reg_isp_sd_set_reg_3_38                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane38(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane38*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE39                            (HV_ISPTX1_BASE_ADDRESS + 0x3C)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE39_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane39

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane39  rs_tx_isptx1_isptx_sd_setting_reg_lane39;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane39 {
    unsigned int reg_isp_sd_set_reg_0_39                    : 8;
    unsigned int reg_isp_sd_set_reg_1_39                    : 8;
    unsigned int reg_isp_sd_set_reg_2_39                    : 8;
    unsigned int reg_isp_sd_set_reg_3_39                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane39(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane39*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE40                            (HV_ISPTX1_BASE_ADDRESS + 0x40)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE40_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane40

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane40  rs_tx_isptx1_isptx_sd_setting_reg_lane40;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane40 {
    unsigned int reg_isp_sd_set_reg_0_40                    : 8;
    unsigned int reg_isp_sd_set_reg_1_40                    : 8;
    unsigned int reg_isp_sd_set_reg_2_40                    : 8;
    unsigned int reg_isp_sd_set_reg_3_40                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane40(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane40*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE41                            (HV_ISPTX1_BASE_ADDRESS + 0x44)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE41_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane41

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane41  rs_tx_isptx1_isptx_sd_setting_reg_lane41;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane41 {
    unsigned int reg_isp_sd_set_reg_0_41                    : 8;
    unsigned int reg_isp_sd_set_reg_1_41                    : 8;
    unsigned int reg_isp_sd_set_reg_2_41                    : 8;
    unsigned int reg_isp_sd_set_reg_3_41                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane41(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane41*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE42                            (HV_ISPTX1_BASE_ADDRESS + 0x48)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE42_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane42

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane42  rs_tx_isptx1_isptx_sd_setting_reg_lane42;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane42 {
    unsigned int reg_isp_sd_set_reg_0_42                    : 8;
    unsigned int reg_isp_sd_set_reg_1_42                    : 8;
    unsigned int reg_isp_sd_set_reg_2_42                    : 8;
    unsigned int reg_isp_sd_set_reg_3_42                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane42(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane42*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE43                            (HV_ISPTX1_BASE_ADDRESS + 0x4C)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE43_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane43

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane43  rs_tx_isptx1_isptx_sd_setting_reg_lane43;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane43 {
    unsigned int reg_isp_sd_set_reg_0_43                    : 8;
    unsigned int reg_isp_sd_set_reg_1_43                    : 8;
    unsigned int reg_isp_sd_set_reg_2_43                    : 8;
    unsigned int reg_isp_sd_set_reg_3_43                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane43(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane43*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE44                            (HV_ISPTX1_BASE_ADDRESS + 0x50)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE44_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane44

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane44  rs_tx_isptx1_isptx_sd_setting_reg_lane44;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane44 {
    unsigned int reg_isp_sd_set_reg_0_44                    : 8;
    unsigned int reg_isp_sd_set_reg_1_44                    : 8;
    unsigned int reg_isp_sd_set_reg_2_44                    : 8;
    unsigned int reg_isp_sd_set_reg_3_44                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane44(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane44*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE45                            (HV_ISPTX1_BASE_ADDRESS + 0x54)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE45_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane45

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane45  rs_tx_isptx1_isptx_sd_setting_reg_lane45;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane45 {
    unsigned int reg_isp_sd_set_reg_0_45                    : 8;
    unsigned int reg_isp_sd_set_reg_1_45                    : 8;
    unsigned int reg_isp_sd_set_reg_2_45                    : 8;
    unsigned int reg_isp_sd_set_reg_3_45                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane45(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane45*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE46                            (HV_ISPTX1_BASE_ADDRESS + 0x58)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE46_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane46

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane46  rs_tx_isptx1_isptx_sd_setting_reg_lane46;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane46 {
    unsigned int reg_isp_sd_set_reg_0_46                    : 8;
    unsigned int reg_isp_sd_set_reg_1_46                    : 8;
    unsigned int reg_isp_sd_set_reg_2_46                    : 8;
    unsigned int reg_isp_sd_set_reg_3_46                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane46(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane46*)&(val))



#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE47                            (HV_ISPTX1_BASE_ADDRESS + 0x5C)

#define TX_ISPTX1_ISPTX_SD_SETTING_REG_LANE47_struct                     rs_tx_isptx1_isptx_sd_setting_reg_lane47

typedef struct _rs_tx_isptx1_isptx_sd_setting_reg_lane47  rs_tx_isptx1_isptx_sd_setting_reg_lane47;
struct _rs_tx_isptx1_isptx_sd_setting_reg_lane47 {
    unsigned int reg_isp_sd_set_reg_0_47                    : 8;
    unsigned int reg_isp_sd_set_reg_1_47                    : 8;
    unsigned int reg_isp_sd_set_reg_2_47                    : 8;
    unsigned int reg_isp_sd_set_reg_3_47                    : 8;
};
#define tx_isptx1_isptx_sd_setting_reg_lane47(val) ((rs_tx_isptx1_isptx_sd_setting_reg_lane47*)&(val))



#define TX_ISPTX1_CSPI_AEQ_00                                            (HV_ISPTX1_BASE_ADDRESS + 0x60)

#define TX_ISPTX1_CSPI_AEQ_00_struct                                     rs_tx_isptx1_cspi_aeq_00

typedef struct _rs_tx_isptx1_cspi_aeq_00  rs_tx_isptx1_cspi_aeq_00;
struct _rs_tx_isptx1_cspi_aeq_00 {
    unsigned int reg_cspi_aeq_prbs7_init                    : 7;
    unsigned int reg_cspi_aeq_prbs7_mode                    : 1;
    unsigned int reg_cspi_aeq_prbs7_mode1_phase             : 4;
    unsigned int reg_cspi_aeq_random_en                     : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_cspi_aeq_lane_sel_47to32               :16;
};
#define tx_isptx1_cspi_aeq_00(val) ((rs_tx_isptx1_cspi_aeq_00*)&(val))



#define TX_ISPTX1_CSPI_AEQ_01                                            (HV_ISPTX1_BASE_ADDRESS + 0x64)

#define TX_ISPTX1_CSPI_AEQ_01_struct                                     rs_tx_isptx1_cspi_aeq_01

typedef struct _rs_tx_isptx1_cspi_aeq_01  rs_tx_isptx1_cspi_aeq_01;
struct _rs_tx_isptx1_cspi_aeq_01 {
    unsigned int reg_cspi_aeq_lane_sel_31to00               :32;
};
#define tx_isptx1_cspi_aeq_01(val) ((rs_tx_isptx1_cspi_aeq_01*)&(val))



#define TX_ISPTX1_CSPI_AEQ_02                                            (HV_ISPTX1_BASE_ADDRESS + 0x68)

#define TX_ISPTX1_CSPI_AEQ_02_struct                                     rs_tx_isptx1_cspi_aeq_02

typedef struct _rs_tx_isptx1_cspi_aeq_02  rs_tx_isptx1_cspi_aeq_02;
struct _rs_tx_isptx1_cspi_aeq_02 {
    unsigned int reg_cspi_aeq_en_47to32                     :16;
    unsigned int reg_cspi_aeq_done_47to32                   :16;
};
#define tx_isptx1_cspi_aeq_02(val) ((rs_tx_isptx1_cspi_aeq_02*)&(val))



#define TX_ISPTX1_CSPI_AEQ_03                                            (HV_ISPTX1_BASE_ADDRESS + 0x6C)

#define TX_ISPTX1_CSPI_AEQ_03_struct                                     rs_tx_isptx1_cspi_aeq_03

typedef struct _rs_tx_isptx1_cspi_aeq_03  rs_tx_isptx1_cspi_aeq_03;
struct _rs_tx_isptx1_cspi_aeq_03 {
    unsigned int reg_cspi_aeq_en_31to00                     :32;
};
#define tx_isptx1_cspi_aeq_03(val) ((rs_tx_isptx1_cspi_aeq_03*)&(val))



#define TX_ISPTX1_CSPI_AEQ_04                                            (HV_ISPTX1_BASE_ADDRESS + 0x70)

#define TX_ISPTX1_CSPI_AEQ_04_struct                                     rs_tx_isptx1_cspi_aeq_04

typedef struct _rs_tx_isptx1_cspi_aeq_04  rs_tx_isptx1_cspi_aeq_04;
struct _rs_tx_isptx1_cspi_aeq_04 {
    unsigned int reg_cspi_aeq_done_31to00                   :32;
};
#define tx_isptx1_cspi_aeq_04(val) ((rs_tx_isptx1_cspi_aeq_04*)&(val))



#define TX_ISPTX1_CSPI_AEQ_05                                            (HV_ISPTX1_BASE_ADDRESS + 0x74)

#define TX_ISPTX1_CSPI_AEQ_05_struct                                     rs_tx_isptx1_cspi_aeq_05

typedef struct _rs_tx_isptx1_cspi_aeq_05  rs_tx_isptx1_cspi_aeq_05;
struct _rs_tx_isptx1_cspi_aeq_05 {
    unsigned int reg_cspi_aeq_fbd_link_en                   : 1;
    unsigned int reg_cspi_aeq_fbd_filter_num                : 8;
    unsigned int reg_cspi_aeq_fbd_start_num                 : 4;
    unsigned int reg_cspi_aeq_fbd_header_num                : 4;
    unsigned int reg_cspi_aeq_fbd_header_mode               : 1;
    unsigned int reg_cspi_aeq_fbd_data_num                  : 6;
    unsigned int reserved                                   : 8;
};
#define tx_isptx1_cspi_aeq_05(val) ((rs_tx_isptx1_cspi_aeq_05*)&(val))



#define TX_ISPTX1_CSPI_AEQ_06                                            (HV_ISPTX1_BASE_ADDRESS + 0x78)

#define TX_ISPTX1_CSPI_AEQ_06_struct                                     rs_tx_isptx1_cspi_aeq_06

typedef struct _rs_tx_isptx1_cspi_aeq_06  rs_tx_isptx1_cspi_aeq_06;
struct _rs_tx_isptx1_cspi_aeq_06 {
    unsigned int reg_cspi_aeq_fbd_clk_scale                 :10;
    unsigned int reserved                                   :22;
};
#define tx_isptx1_cspi_aeq_06(val) ((rs_tx_isptx1_cspi_aeq_06*)&(val))



#define TX_ISPTX1_CSPI_AEQ_07                                            (HV_ISPTX1_BASE_ADDRESS + 0x7C)

#define TX_ISPTX1_CSPI_AEQ_07_struct                                     rs_tx_isptx1_cspi_aeq_07

typedef struct _rs_tx_isptx1_cspi_aeq_07  rs_tx_isptx1_cspi_aeq_07;
struct _rs_tx_isptx1_cspi_aeq_07 {
    unsigned int reg_cspi_aeq_cmd_t                         : 9;
    unsigned int reg_cspi_aeq_cmd_s                         : 9;
    unsigned int reg_cspi_aeq_cmd_e                         : 9;
    unsigned int reserved                                   : 5;
};
#define tx_isptx1_cspi_aeq_07(val) ((rs_tx_isptx1_cspi_aeq_07*)&(val))



#define TX_ISPTX1_CSPI_AEQ_08                                            (HV_ISPTX1_BASE_ADDRESS + 0x80)

#define TX_ISPTX1_CSPI_AEQ_08_struct                                     rs_tx_isptx1_cspi_aeq_08

typedef struct _rs_tx_isptx1_cspi_aeq_08  rs_tx_isptx1_cspi_aeq_08;
struct _rs_tx_isptx1_cspi_aeq_08 {
    unsigned int reg_cspi_aeq_force_lock_47to32             :16;
    unsigned int reserved                                   :16;
};
#define tx_isptx1_cspi_aeq_08(val) ((rs_tx_isptx1_cspi_aeq_08*)&(val))



#define TX_ISPTX1_CSPI_AEQ_09                                            (HV_ISPTX1_BASE_ADDRESS + 0x8C)

#define TX_ISPTX1_CSPI_AEQ_09_struct                                     rs_tx_isptx1_cspi_aeq_09

typedef struct _rs_tx_isptx1_cspi_aeq_09  rs_tx_isptx1_cspi_aeq_09;
struct _rs_tx_isptx1_cspi_aeq_09 {
    unsigned int reg_cspi_aeq_force_lock_31to00             :32;
};
#define tx_isptx1_cspi_aeq_09(val) ((rs_tx_isptx1_cspi_aeq_09*)&(val))



#endif