/**
 * @file hv_pm51_driver_Interrupt.c
 * @brief interrupt implement
 * @details
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20230301
 * @copyright Copyright(c),2023-3, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>author                     <th>date           <th>description
 * <tr><td>HiView SoC Software Team   <td>20230301       <td>Create and first Version.
 * </table>
**/

#include <reg51.h>
#include "HS_PAGE_HT7315_8051_reg.h"
#include "hv_pm51_Base.h"
#include "hv_pm51_Setting.h"
#include "hv_pm51_Reg.h"
#include "hv_pm51_driver_Reg.h"
#include "hv_pm51_driver_ADC.h"

#include "hv_pm51_driver_Interrupt.h"
#include "hv_pm51_driver_UART.h"
#include "hv_pm51_driver_WDG.h"
#if TIMER_ENABLE
#include "hv_pm51_driver_Timer.h"
#endif
#if GPIO_ENABLE
#include "hv_pm51_driver_GPIO.h"
#endif
#if WATCHDOG_ENABLE
#include "hv_pm51_driver_WDG.h"
#endif
#include "hv_pm51_app_Sys.h"
#include "hv_pm51_app_PM.h"
#include "hv_pm51_app_Key.h"
#include "hv_pm51_app_Mailbox.h"
#include "hv_pm51_app_IR.h"
#include "BoardConfig.h"
#include "ProjectConfig.h"
extern xdata BOOL s_bIsKeyWork;
extern xULONG32 g_ulTimer0Cnt;
extern UCHAR8 ucPowerState;

volatile IntFlags g_unIntFlag;
volatile WakeupIntFlags g_unWakeupIntFlag;
volatile EventIntFlags g_unEventIntFlag;
volatile MiscIntFlags g_unMiscIntFlag;

UCHAR8 ucPmFixMode = 0xff;
UCHAR8 ucPmCurMainChannel = 0xff;
UCHAR8 ucPmCurSubChannel = 0xff;

#if (HV_PROJECT_CONFIG_ESEGMENT_PM51 == HV_CONFIG_ON)
static const xUCHAR8 s_ucHdmiEdidData[] = {
#include "hv_edidi_Hdmi14_2560X1440@60.h"
};
#endif

void Hv_PM51_Int_Init(void)
{
    /* DP RX Cable deglitch,pol inv,io_ctrl */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_dp_filter_num_ADDR,
                      HS_Standby__standby_mcu_reg__reg_dp_filter_num_BITSTART,
                      HS_Standby__standby_mcu_reg__reg_dp_filter_num_BITEND, IO_DEGLITCH_NUM);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_dp_pol_ADDR,
                      HS_Standby__standby_mcu_reg__reg_dp_pol_BITSTART,
                      HS_Standby__standby_mcu_reg__reg_dp_pol_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_dp0_cable_in_sel_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_dp0_cable_in_sel_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_dp0_cable_in_sel_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_dp1_cable_in_sel_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_dp1_cable_in_sel_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_dp1_cable_in_sel_BITEND, 0x0);

    /* HDMI RX Cable deglitch,pol inv */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_hdmi_filter_num_ADDR,
                      HS_Standby__standby_mcu_reg__reg_hdmi_filter_num_BITSTART,
                      HS_Standby__standby_mcu_reg__reg_hdmi_filter_num_BITEND, IO_DEGLITCH_NUM);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_hdmi_pol_ADDR,
                      HS_Standby__standby_mcu_reg__reg_hdmi_pol_BITSTART,
                      HS_Standby__standby_mcu_reg__reg_hdmi_pol_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_hdmi0_rx_cable_det_in_sel_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi0_rx_cable_det_in_sel_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi0_rx_cable_det_in_sel_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_hdmi1_rx_cable_det_in_sel_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi1_rx_cable_det_in_sel_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi1_rx_cable_det_in_sel_BITEND, 0x0);

    /* pwr key intr pol inv */
    Hv_PM51_Reg_WriteMask(HS_Standby__AON_REG__reg_pmu_pk_filter_num_ADDR,
                      HS_Standby__AON_REG__reg_pmu_pk_filter_num_BITSTART,
                      HS_Standby__AON_REG__reg_pmu_pk_filter_num_BITEND, IO_DEGLITCH_NUM);
    Hv_PM51_Reg_WriteMask(HS_Standby__AON_REG__reg_pmu_pk_pol_ADDR,
                      HS_Standby__AON_REG__reg_pmu_pk_pol_BITSTART,
                      HS_Standby__AON_REG__reg_pmu_pk_pol_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__AON_REG__reg_pmu_reg_en_ADDR,
                      HS_Standby__AON_REG__reg_pmu_reg_en_BITSTART,
                      HS_Standby__AON_REG__reg_pmu_reg_en_BITEND, 0x1);

    Hv_PM51_Sys_DelayMs(1);

    /* clear fake intr */
    /* Hv_PM51_Int_ClearIntState(STATE_INTR_PWR_KEY); */
    /* Hv_PM51_Int_ClearIntState(STATE_INTR_DP_CABLE_0); */
    /* Hv_PM51_Int_ClearIntState(STATE_INTR_AUX); */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_off_int_clr_ADDR,
                      HS_Standby__standby_mcu_reg__reg_off_int_clr_BITSTART,
                      HS_Standby__standby_mcu_reg__reg_off_int_clr_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_off_int_clr_ADDR,
                      HS_Standby__standby_mcu_reg__reg_off_int_clr_BITSTART,
                      HS_Standby__standby_mcu_reg__reg_off_int_clr_BITEND, 0x0);

    /*  enable all intr */

    /* priority setting ,all set lowest */
    IP=0x00;
    IP1=0x00;
    /* IPH=0x00; */
    IPH1=0x00;

    /**
     * IE.7 EA Enable or disable all interrupt bits.
     * IE.6 Not implemented. Returns zero when read.
     * IE.5 ET2 Enable Timer 2 overflow interrupt (or Extended Interrupt 5 if Timer 2 is not included).
     * IE.4 ES Enable Serial Port interrupt (or Extended Interrupt 4 if the UART is not included).
     * IE.3 ET1 Enable Timer 1 overflow interrupt (or Extended Interrupt 3 if no timers are included).
     * IE.2 EX1 Enable External Interrupt 1 (or Extended Interrupt 2 if no timers are included).
     * IE.1 ET0 Enable Timer 0 overflow interrupt (or Extended Interrupt 1 if no timers are included).
     * IE.0 EX0 Enable External Interrupt 0 (or Extended Interrupt 0 if no timers are included).
    **/
    IE=INTR_IE_ENABLE_ALL;

    /**
     * Different name from doc (IE1 -> EI1)
     * EI1.7 EI13 Enable Extended Interrupt 13.
     * EI1.6 EI12 Enable Extended Interrupt 12.
     * EI1.5 EI11 Enable Extended Interrupt 11.
     * EI1.4 EI10 Enable Extended Interrupt 10.
     * EI1.3 EI9 Enable Extended Interrupt 9.
     * EI1.2 EI8 Enable Extended Interrupt 8.
     * EI1.1 EI7 Enable Extended Interrupt 7.
     * EI1.0 EI6 Enable Extended Interrupt 6.
    **/
    EI1=INTR_EI1_ENABLE_ALL;

    /* Intr_1 = Intr_CBDefault; */
    /* flag = 0x0; */
}

void Hv_PM51_Int_EnableAll(void)
{
    IE=INTR_IE_ENABLE_ALL;
    EI1=INTR_EI1_ENABLE_ALL;
}
void Hv_PM51_Int_DisableAll(void)
{
    IE=INTR_IE_DISABLE_ALL;
    EI1=INTR_EI1_DISABLE_ALL;
}

static void PM51_Int_ClearPowerKeyIntState(void)
{
    xULONG32 ulTempData;

    ulTempData = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_off_int_clr_ADDR);

    ulTempData |= BIT_0;
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_off_int_clr_ADDR, ulTempData);

    ulTempData = ulTempData & ~(BIT_0);
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_off_int_clr_ADDR, ulTempData);
}

static void PM51_Int_ClearMipsIntState(void)
{
    xULONG32 ulTempData;

    ulTempData = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_stby_int_clr_ADDR);

    ulTempData |= BIT_7;
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stby_int_clr_ADDR, ulTempData);

    ulTempData = ulTempData & ~(BIT_7);
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stby_int_clr_ADDR, ulTempData);
}

static void PM51_Int_SaveWakeupIntState(void)
{
    xUCHAR8 ucTempData0;
    xUCHAR8 ucTempData1;

    ucTempData0 = Hv_PM51_Reg_ReadByte(HS_Standby__standby_mcu_reg__regr_wake_int_stat_ADDR);
    ucTempData1 = Hv_PM51_Reg_ReadByte(HS_Standby__standby_mcu_reg__regr_wake_int_stat_ADDR+1);

    g_unWakeupIntFlag.All = ((USHORT16)ucTempData0 | (((USHORT16)ucTempData1) << 8));
}

static void PM51_Int_ClearWakeupIntState(void)
{
    xULONG32 ulTempData0;
    xULONG32 ulTempData1;

    ulTempData0 = Hv_PM51_Reg_Read(HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_wakeupctrl_ADDR);
    ulTempData0 &= (BIT_13);
    if(ulTempData0)
    {
        ulTempData0 = Hv_PM51_Reg_Read(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_ADDR);
        ulTempData0 |= (BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_ADDR, ulTempData0);
        ulTempData0 &= ~(BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_ADDR, ulTempData0);
    }

    ulTempData0 = Hv_PM51_Reg_Read(HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_wakeupctrl_ADDR);
    ulTempData0 &= (BIT_13);
    if(ulTempData0)
    {
        ulTempData0 = Hv_PM51_Reg_Read(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_ADDR);
        ulTempData0 |= (BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_ADDR, ulTempData0);
        ulTempData0 &= ~(BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_ADDR, ulTempData0);
    }

    ulTempData0 = Hv_PM51_Reg_Read(0x1100806C);
    ulTempData1 = Hv_PM51_Reg_Read(0x11008060);

    ulTempData0 |= ulTempData1;
    Hv_PM51_Reg_Write(0x11008060, ulTempData0);
}

static void PM51_Int_SaveEventIntState(void)
{
    xULONG32 ulTempData;

    ulTempData = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_event_int_stat_ADDR);
    ulTempData &= 0xffffU;
    g_unEventIntFlag.All = (USHORT16)ulTempData;
}

static void PM51_Int_ClearEventIntState(void)
{
    xULONG32 ulTempData;

    ulTempData = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_event_int_clr_ADDR);

    ulTempData |= 0xffffU;
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_event_int_clr_ADDR, ulTempData);
}

static void PM51_Int_EnterNormal(void) reentrant
{
#if 0
    USHORT16 usCounts;
    USHORT16 usMs;
    ULONG32 ulRData32;

    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_power_on_ADDR);
    ulRData32 = ulRData32 | (BIT_2);  /* power_on = 1 */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_power_on_ADDR, ulRData32);

    /* wait for DCDC work */
    usMs = 5;
    for(;usMs > 0;usMs--)
    {
        for(usCounts = 1650;usCounts > 0;usCounts--); /* 1650 = magic num */
    }

    ulRData32 = ulRData32 & ~(BIT_1);  /* stby_iso = 0 */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR, ulRData32);

    usMs = 1;
    for(;usMs > 0;usMs--)
    {
        for(usCounts = 1650;usCounts > 0;usCounts--); /* 1650 = magic num */
    }

    ulRData32 = ulRData32 | (BIT_0);  /* stb_sw_rst release */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR, ulRData32);
#else
    return;
#endif
}

#if TIMER_ENABLE
void Hv_PM51_Int_Timer0(void)                    interrupt 1
{
    g_unIntFlag.Bits.stIntFlagInnerTimer0 = 1;
    Hv_PM51_Timer_Clear(INNERTIMER0);

#if IR_ENABLE
    g_ulTimer0Cnt++;
    if(g_ulTimer0Cnt < 5)
    {
        Hv_PM51_Timer_Set(INNERTIMER0, 0x0);
    }
    else
    {
        g_ulTimer0Cnt = 0;
    }
#endif

    return;
}
#endif

void Hv_PM51_Int_Reserved0(void)                interrupt 2
{
    return;
}

#if TIMER_ENABLE
void Hv_PM51_Int_Timer1(void)                    interrupt 3
{
    g_unIntFlag.Bits.stIntFlagInnerTimer1 = 1;
    Hv_PM51_Timer_Clear(INNERTIMER1);

    return;
}
#endif

void Hv_PM51_Int_UART(void)                      interrupt 4
{
    g_unIntFlag.Bits.stIntFlagUart = 1;
    return;
}

void Hv_PM51_Int_Reserved1(void)                 interrupt 5
{
    return;
}

void Hv_PM51_Int_Reserved2(void)                  interrupt 6
{
    return;
}

#if TIMER_ENABLE
void Hv_PM51_Int_ExTimer0(void)                    interrupt 7
{
    g_unIntFlag.Bits.stIntFlagExTimer0 = 1;
    Hv_PM51_Timer_Clear(EXTIMER0);

    return;
}
#endif

#if TIMER_ENABLE
void Hv_PM51_Int_ExTimer1(void)                     interrupt 8
{
    g_unIntFlag.Bits.stIntFlagExTimer1 = 1;
    Hv_PM51_Timer_Clear(EXTIMER1);

    return;
}
#endif

void Hv_PM51_Int_PMU(void)                           interrupt 9
{
    g_unIntFlag.Bits.stIntFlagPwrKey = 1;
    PM51_Int_ClearPowerKeyIntState();

    return;
}

void Hv_PM51_Int_MIPS(void)                          interrupt 10
{
    g_unIntFlag.Bits.stIntFlagMips = 1;
    PM51_Int_ClearMipsIntState();

    return;
}

void Hv_PM51_Clear_DDC(void)
{
    xUCHAR8 ucRData8;

    /* hdmi0 wr_data_clr wr_cnt_clr wr_valid_clr bit24-26 */
    ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_ADDR+3);
    ucRData8 |= 7;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_ADDR+3, ucRData8);
    ucRData8 &= 0xf8;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_ADDR+3, ucRData8);

    /* clr_slv_addr_valid bit19 */
    ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_ADDR+2);
    ucRData8 |= 8;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_ADDR+2, ucRData8);
    ucRData8 &= 0xf7;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_ADDR+2, ucRData8);

    /* hdmi1 wr_data_clr wr_cnt_clr wr_valid_clr bit24-26 */
    ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_ADDR+3);
    ucRData8 |= 7;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_ADDR+3, ucRData8);
    ucRData8 &= 0xf8;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_ADDR+3, ucRData8);

    /* clr_slv_addr_valid bit19 */
    ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_ADDR+2);
    ucRData8 |= 8;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_ADDR+2, ucRData8);
    ucRData8 &= 0xf7;
    Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_ADDR+2, ucRData8);

    return;
}

void Hv_PM51_Int_WakeUp(void)                        interrupt 11
{
    xUCHAR8 ucRData8;
    xULONG32 ulRData32;
#if ( (HV_PROJECT_CONFIG_HDMI0_DDC_WAKEUP_ENABLE == HV_CONFIG_ON) || (HV_PROJECT_CONFIG_HDMI1_DDC_WAKEUP_ENABLE == HV_CONFIG_ON) )
    xUCHAR8 aucRData8[6];
#endif
    g_unIntFlag.Bits.stIntFlagWakeup = 1;
    ulRData32 = 0;
#if (HV_PROJECT_CONFIG_ESEGMENT_PM51 == HV_CONFIG_ON)
    /* HDMI0 */
    ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_edid_segment_update_ADDR);
    ucRData8 &= (BIT_6);
    if(ucRData8)
    {
        Hv_PM51_Sys_UpdateHdmiEdidData(0, 512, s_ucHdmiEdidData);

        ulRData32 = Hv_PM51_Reg_Read(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_ADDR);
        ulRData32 |= (BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_ADDR, ulRData32);
        ulRData32 &= ~(BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_ADDR, ulRData32);

        g_unMiscIntFlag.Bits.stMiscIntHdmi0EdidSeg = 1;
    }
    /* HDMI1 */
    ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_edid_segment_update_ADDR);
    ucRData8 &= (BIT_6);
    if(ucRData8)
    {
        Hv_PM51_Sys_UpdateHdmiEdidData(1, 512, s_ucHdmiEdidData);

        ulRData32 = Hv_PM51_Reg_Read(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_ADDR);
        ulRData32 |= (BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_ADDR, ulRData32);
        ulRData32 &= ~(BIT_22);
        Hv_PM51_Reg_Write(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_ADDR, ulRData32);

        g_unMiscIntFlag.Bits.stMiscIntHdmi1EdidSeg = 1;
    }
#endif

    PM51_Int_SaveWakeupIntState();
    PM51_Int_ClearWakeupIntState();

    if((g_unWakeupIntFlag.Bits.stWakeupIntFlagHdmiCec0) && !(g_unWakeupIntFlag.Bits.stWakeupIntFlagTmds0))
    {
        ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_slave_addr_ADDR+3);
        if((ucRData8 != 0xA8) && (ucRData8 != 0xA9) && (ucRData8 != 0x60) && (ucRData8 != 0x61)
#if (HV_PROJECT_CONFIG_HDMI0_DDC_WAKEUP_ENABLE == HV_CONFIG_ON)
            && (ucRData8 != 0x6E)
#endif
          )
        {
            g_unIntFlag.Bits.stIntFlagWakeup = 0;
            g_unWakeupIntFlag.All = 0;
            Hv_PM51_Clear_DDC();
            return;
        }
#if (HV_PROJECT_CONFIG_HDMI0_DDC_WAKEUP_ENABLE == HV_CONFIG_ON)
        if (ucRData8 == 0x6E)
        {
            /* wait for data ready */
            Hv_PM51_Sys_DelayMs(150);

            ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_valid_num_ADDR);
            aucRData8[0] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_ADDR);
            aucRData8[1] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_ADDR+1);
            aucRData8[2] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_ADDR+2);
            aucRData8[3] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_ADDR+3);
            aucRData8[4] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_ADDR+4);
            aucRData8[5] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_ADDR+5);
            Hv_PM51_Clear_DDC();
            if (
                 (0x51 == aucRData8[0]) && (0x84 == aucRData8[1]) && (0x03 == aucRData8[2])
                 && (0xFB == aucRData8[3]) && (0xA0 == aucRData8[4]) && (0x01 == aucRData8[5])
               )
            {
                aucRData8[0] = 0x6E;
                aucRData8[1] = 0x83;
                aucRData8[2] = 0x02;
                aucRData8[3] = 0xA0;
                aucRData8[4] = 0x01;
                aucRData8[5] = 0x1E;
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_ADDR, aucRData8[0]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_ADDR+1, aucRData8[1]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_ADDR+2, aucRData8[2]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_ADDR+3, aucRData8[3]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_ADDR+4, aucRData8[4]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_ADDR+5, aucRData8[5]);

                /* hdmi0 i2c_rd_req_th bit24-28, 29-31 reserved */
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_req_th_ADDR+3, 6);
            }
            else
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
#endif
    }
    if((g_unWakeupIntFlag.Bits.stWakeupIntFlagHdmiCec1) && !(g_unWakeupIntFlag.Bits.stWakeupIntFlagTmds1))
    {
        ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_slave_addr_ADDR+3);
        if((ucRData8 != 0xA8) && (ucRData8 != 0xA9) && (ucRData8 != 0x60) && (ucRData8 != 0x61)
#if (HV_PROJECT_CONFIG_HDMI1_DDC_WAKEUP_ENABLE == HV_CONFIG_ON)
            && (ucRData8 != 0x6E)
#endif
          )
        {
            Hv_PM51_Clear_DDC();
            g_unIntFlag.Bits.stIntFlagWakeup = 0;
            g_unWakeupIntFlag.All = 0;
            return;
        }
#if (HV_PROJECT_CONFIG_HDMI1_DDC_WAKEUP_ENABLE == HV_CONFIG_ON)
        if (ucRData8 == 0x6E)
        {
            /* wait for data ready */
            Hv_PM51_Sys_DelayMs(150);

            ucRData8 = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_valid_num_ADDR);
            aucRData8[0] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_ADDR);
            aucRData8[1] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_ADDR+1);
            aucRData8[2] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_ADDR+2);
            aucRData8[3] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_ADDR+3);
            aucRData8[4] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_ADDR+4);
            aucRData8[5] = Hv_PM51_Reg_ReadByte(HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_ADDR+5);
            Hv_PM51_Clear_DDC();
            if (
                 (0x51 == aucRData8[0]) && (0x84 == aucRData8[1]) && (0x03 == aucRData8[2])
                 && (0xFB == aucRData8[3]) && (0xA0 == aucRData8[4]) && (0x01 == aucRData8[5])
               )
            {
                aucRData8[0] = 0x6E;
                aucRData8[1] = 0x83;
                aucRData8[2] = 0x02;
                aucRData8[3] = 0xA0;
                aucRData8[4] = 0x01;
                aucRData8[5] = 0x1E;
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_ADDR, aucRData8[0]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_ADDR+1, aucRData8[1]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_ADDR+2, aucRData8[2]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_ADDR+3, aucRData8[3]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_ADDR+4, aucRData8[4]);
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_ADDR+5, aucRData8[5]);

                /* hdmi1 i2c_rd_req_th bit24-28, 29-31 reserved */
                Hv_PM51_Reg_WriteByte(HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_req_th_ADDR+3, 6);
            }
            else
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
#endif
    }

#if DPMS_FIX_MODE_ENABLE
    if(ucPmFixMode == 1)
    {
        if(g_unWakeupIntFlag.Bits.stWakeupIntFlagHdmiCable0
            || g_unWakeupIntFlag.Bits.stWakeupIntFlagTmds0
            || g_unWakeupIntFlag.Bits.stWakeupIntFlagHdmiCec0)
        {
            if((ucPmCurMainChannel != CUR_CHANNEL_HDMI0) && (ucPmCurSubChannel != CUR_CHANNEL_HDMI0))
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
        if(g_unWakeupIntFlag.Bits.stWakeupIntFlagHdmiCable1
            || g_unWakeupIntFlag.Bits.stWakeupIntFlagTmds1
            || g_unWakeupIntFlag.Bits.stWakeupIntFlagHdmiCec1)
        {
            if((ucPmCurMainChannel != CUR_CHANNEL_HDMI1) && (ucPmCurSubChannel != CUR_CHANNEL_HDMI1))
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
#if (HV_BOARD_CONFIG_DP0_TYPE == DP_PORT_ALTMODE)
        if(g_unWakeupIntFlag.Bits.stWakeupIntFlagTypec0)
        {
            if((ucPmCurMainChannel != CUR_CHANNEL_DP0) && (ucPmCurSubChannel != CUR_CHANNEL_DP0))
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
#else
        if(g_unWakeupIntFlag.Bits.stWakeupIntFlagDpCable0
            || g_unWakeupIntFlag.Bits.stWakeupIntFlagAux0)
        {
            if((ucPmCurMainChannel != CUR_CHANNEL_DP0) && (ucPmCurSubChannel != CUR_CHANNEL_DP0))
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
#endif
#if (HV_BOARD_CONFIG_DP1_TYPE == DP_PORT_ALTMODE)
        if(g_unWakeupIntFlag.Bits.stWakeupIntFlagTypec0)
        {
            if((ucPmCurMainChannel != CUR_CHANNEL_DP1) && (ucPmCurSubChannel != CUR_CHANNEL_DP1))
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
#else
        if(g_unWakeupIntFlag.Bits.stWakeupIntFlagDpCable1
            || g_unWakeupIntFlag.Bits.stWakeupIntFlagAux1)
        {
            if((ucPmCurMainChannel != CUR_CHANNEL_DP1) && (ucPmCurSubChannel != CUR_CHANNEL_DP1))
            {
                g_unIntFlag.Bits.stIntFlagWakeup = 0;
                g_unWakeupIntFlag.All = 0;
                return;
            }
        }
#endif
    }
#endif

    if((g_unWakeupIntFlag.Bits.stWakeupIntFlagAdc0) || (g_unWakeupIntFlag.Bits.stWakeupIntFlagAdc1))
    {
        /* do nothing */
    }
    else
    {
        PM51_Int_EnterNormal();
    }

    return;
}

void Hv_PM51_Int_Event(void)                         interrupt 12
{
    xULONG32 ulRData32;

    g_unIntFlag.Bits.stIntFlagEvent = 1;

    PM51_Int_SaveEventIntState();
    PM51_Int_ClearEventIntState();
#if (GPIO_ENABLE && IR_ENABLE)
    if((g_unEventIntFlag.All & (BIT_0<<HV_PROJECT_CONFIG_PM51_IR_USE_GPIO)) > 0)
    {
        if(s_bIsKeyWork)
        {
            Hv_PM51_IR_RecvHandler();
        }
    }
#endif
#if DPMS_DP0_GPIO_ENABLE
    if((g_unEventIntFlag.All & (1 << DPMS_DP0_GPIO)) > 0)
    {
        ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_power_on_ADDR);
        ulRData32 &= (BIT_2);
        if(ulRData32 == 0)
        {
#if DPMS_FIX_MODE_ENABLE
            if((ucPmFixMode == 1) && (ucPmCurMainChannel != CUR_CHANNEL_DP0) \
                && (ucPmCurSubChannel != CUR_CHANNEL_DP0))
            {
                g_unEventIntFlag.All &= ~(1 << DPMS_DP0_GPIO);
            }
            else
#endif
            {
                PM51_Int_EnterNormal();
            }
        }
        else
        {
            g_unEventIntFlag.All |= (1 << DPMS_DP0_GPIO);
        }
    }
#endif

#if DPMS_DP1_GPIO_ENABLE
    if((g_unEventIntFlag.All & (1 << DPMS_DP1_GPIO)) > 0)
    {
        ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_power_on_ADDR);
        ulRData32 &= (BIT_2);
        if(ulRData32 == 0)
        {
#if DPMS_FIX_MODE_ENABLE
            if((ucPmFixMode == 1) && (ucPmCurMainChannel != CUR_CHANNEL_DP1) \
                && (ucPmCurSubChannel != CUR_CHANNEL_DP1))
            {
                g_unEventIntFlag.All &= ~(1 << DPMS_DP1_GPIO);
            }
            else
#endif
            {
                PM51_Int_EnterNormal();
            }
        }
        else
        {
            g_unEventIntFlag.All |= (1 << DPMS_DP1_GPIO);
        }
    }
#endif

#if HV_BOARD_CONFIG_HDMI_HPD_5V
    /* HDMI0 */
    if((g_unEventIntFlag.All & BIT_6) > 0)
    {
        ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_power_on_ADDR);
        ulRData32 &= (BIT_2);

        if(ulRData32)
        {
            Hv_PM51_Reg_Write(HS_Standby__standby_comm_reg__sw1_intr_set_ADDR, 0x1);
        }
    }
    /* HDMI1 */
    if((g_unEventIntFlag.All & BIT_7) > 0)
    {
        ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_power_on_ADDR);
        ulRData32 &= (BIT_2);

        if(ulRData32)
        {
            Hv_PM51_Reg_Write(HS_Standby__standby_comm_reg__sw1_intr_set_ADDR, 0x2);
        }
    }
#endif
    return;
}

#if WATCHDOG_ENABLE
void Hv_PM51_Int_WDG(void)                         interrupt 13
{
    g_unIntFlag.Bits.stIntFlagWdg = 1;
    Hv_PM51_Wdg_Feed();

    return;
}
#endif

