/*
 * @file hv_cal_Dma.h
 * @brief Header file of misc module.
 *
 * @verbatim
 * ==============================================================================
 *                        ##### How to use #####
 * ==============================================================================
 * (+) Use ()
 * @endverbatim
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2023-06-07
 */

#ifndef _Hv_Cal_Dma_H
#define _Hv_Cal_Dma_H

typedef enum _DmaDirection
{
    /*!< Transfer type is Memory to Memory and Flow Controller is DW_ahb_dmac.                   */
    DMA_M_TO_M_DMAC = 0,
    /*!< Transfer type is Memory to Peripheral and Flow Controller is DW_ahb_dmac.               */
    DMA_M_TO_P_DMAC,
    /*!< Transfer type is Peripheral to Memory and Flow Controller is DW_ahb_dmac.               */
    DMA_P_TO_M_DMAC,
    /*!< Transfer type is Peripheral to Peripheral and Flow Controller is DW_ahb_dmac.           */
    DMA_P_TO_P_DMAC,
    /*!< Transfer type is Peripheral to Memory and Flow Controller is Peripheral.                */
    DMA_P_TO_M_PERIP,
    /*!< Transfer type is Peripheral to Peripheral and Flow Controller is Source Peripheral.     */
    DMA_P_TO_P_SPERIP,
    /*!< Transfer type is Memory to Peripheral and Flow Controller is Peripheral.                */
    DMA_M_TO_P_PERIP,
    /*!< Transfer type is Peripheral to Peripheral and Flow Controller is Destination Peripheral.*/
    DMA_P_TO_P_DPERIP
} DmaDirection;

typedef enum _DmaInterfaceMux
{
  DMA_MUX_INTERFACE0 = 0x0001,
  DMA_MUX_INTERFACE1 = 0x0002,
  DMA_MUX_INTERFACE2 = 0x0004,
  DMA_MUX_INTERFACE3 = 0x0008,
  DMA_MUX_INTERFACE4 = 0x0010,
  DMA_MUX_INTERFACE5 = 0x0020,
  DMA_MUX_INTERFACE6 = 0x0040,
  DMA_MUX_INTERFACE7 = 0x0080,
  DMA_MUX_INTERFACE8 = 0x0100,
  DMA_MUX_INTERFACE9 = 0x0200,
  DMA_MUX_INTERFACE10 = 0x0400,
  DMA_MUX_INTERFACE11 = 0x0800,
  DMA_MUX_INTERFACE12 = 0x1000,
  DMA_MUX_INTERFACE13 = 0x2000,
  DMA_MUX_INTERFACE14 = 0x4000,
  DMA_MUX_INTERFACE15 = 0x8000,
} DmaInterfaceMux;

typedef enum  _DmaPort
{
    DMA_PORT_0 = 0,
    DMA_PORT_1,
    DMA_PORT_MAX
} DmaPort;

typedef enum _DmaPortChannel
{
    /*!< DMA0 Channel 0 */
    DMA_PORT0_CHANNEL0 = 0,
    /*!< DMA0 Channel 1 */
    DMA_PORT0_CHANNEL1,
    /*!< DMA0 Channel 2 */
    DMA_PORT0_CHANNEL2,
    /*!< DMA0 Channel 3 */
    DMA_PORT0_CHANNEL3,
    /*!< DMA0 Channel 4 */
    DMA_PORT0_CHANNEL4,
    /*!< DMA0 Channel 5 */
    DMA_PORT0_CHANNEL5,
    /*!< DMA0 Channel 6 */
    DMA_PORT0_CHANNEL6,
    /*!< DMA0 Channel 7 */
    DMA_PORT0_CHANNEL7,
    /*!< DMA1 Channel 0 */
    DMA_PORT1_CHANNEL0,
    /*!< DMA1 Channel 1 */
    DMA_PORT1_CHANNEL1,
    /*!< DMA1 Channel 2 */
    DMA_PORT1_CHANNEL2,
    /*!< DMA1 Channel 3 */
    DMA_PORT1_CHANNEL3,
    /*!< DMA1 Channel 4 */
    DMA_PORT1_CHANNEL4,
    /*!< DMA1 Channel 5 */
    DMA_PORT1_CHANNEL5,
    /*!< DMA1 Channel 6 */
    DMA_PORT1_CHANNEL6,
    /*!< DMA1 Channel 7 */
    DMA_PORT1_CHANNEL7,
    /*!< DMA Channel max is 16 */
    DMA_CHANNEL_COUNT,
} DmaPortChannel;


typedef enum _DmaDataSize
{
    /*!< Transfer data size is 8bits.           */
    DMA_DATA_SIZE_8Bits = 0,
    /*!< Transfer data size is 16bits.          */
    DMA_DATA_SIZE_16Bits,
    /*!< Transfer data size is 32bits.          */
    DMA_DATA_SIZE_32Bits,
    /*!< Transfer data size is 64bits.          */
    DMA_DATA_SIZE_64Bits,
    /*!< Transfer data size is 128bits.         */
    DMA_DATA_SIZE_128Bits,
    /*!< Transfer data size is 256bits.         */
    DMA_DATA_SIZE_256Bits,
} DmaDataSize;


typedef enum _DmaBurstSize
{
    /*!< Transfer data number is 1 of a burst.  */
    DMA_DATA_BURST_SIZE_1 = 0,
    /*!< Transfer data number is 4 of a burst.  */
    DMA_DATA_BURST_SIZE_4,
    /*!< Transfer data number is 8 of a burst.  */
    DMA_DATA_BURST_SIZE_8,
    /*!< Transfer data number is 16 of a burst. */
    DMA_DATA_BURST_SIZE_16,
    /*!< Transfer data number is 32 of a burst. */
    DMA_DATA_BURST_SIZE_32,
    /*!< Transfer data number is 64 of a burst. */
    DMA_DATA_BURST_SIZE_64,
    /*!< Transfer data number is 128 of a burst.*/
    DMA_DATA_BURST_SIZE_128,
    /*!< Transfer data number is 256 of a burst.*/
    DMA_DATA_BURST_SIZE_256,
} DmaBurstSize;


typedef enum _DmaSink
{
    /*!< Transfer data number is 1 of a burst.*/
    DMA_SINK_INCREASE = 0,
    /*!< Transfer data number is 4 of a burst.*/
    DMA_SINK_DECREASE,
    /*!< Transfer data number is 8 of a burst.*/
    DMA_SINK_NO_CHANGE
} DmaSink;

typedef enum _DmaDink
{
    /*!< Transfer data number is 1 of a burst.*/
    DMA_DINK_INCREASE = 0,
    /*!< Transfer data number is 4 of a burst.*/
    DMA_DINK_DECREASE,
    /*!< Transfer data number is 8 of a burst.*/
    DMA_DINK_NO_CHANGE
} DmaDink;

typedef enum _DmaMasterMode
{
    DMA_MASTER_MODE_SINGLE = 0,
    DMA_MASTER_MODE_DUAL,
    DMA_MASTER_MODE_ISPRAM_READ,
    DMA_MASTER_MODE_ISPRAM_WRITE,
    DMA_MASTER_MODE_DSPRAM_READ,
    DMA_MASTER_MODE_DSPRAM_WRITE,
} DmaMasterMode;

typedef enum _DmaAhbSelect
{
    /*!< Device is accessed from AHB master 1.*/
    DMA_AHB_MASTER_1 = 0,
    /*!< Device is accessed from AHB master 2.*/
    DMA_AHB_MASTER_2,
    /*!< Device is accessed from AHB master 3.*/
    DMA_AHB_MASTER_3,
    /*!< Device is accessed from AHB master 4.*/
    DMA_AHB_MASTER_4,
} DmaAhbSelect;

typedef enum _DmaConfigSelect
{
    DMA_SRC_CONFIF = 0,
    DMA_DST_CONFIF,
    DMA_BOTH_CONFIF,
} DmaConfigSelect;

typedef enum _DmaStatsu
{
    DMA_CLOSE = 0,
    DMA_IDLE,
    DMA_WORKING,
} DmaStatsu;

typedef enum _DmaChannelStatus
{
    DMA_CHANNEL_IDLE = 0,
    DMA_CHANNEL_BUSY,
} DmaChannelStatus;

typedef enum _DmaIntStatus
{
    DMA_INT_DISABLE = 0,
    DMA_INT_ENABLE,
} DmaIntStatus;

typedef enum _DmaLinklistStatus
{
    DMA_LINKED_LIST_DIS = 0,
    DMA_LINKED_LIST_EN,
} DmaLinklistStatus;

typedef enum _DmaAutoreloadStatus
{
    DMA_AUTO_RELOAD_DIS = 0,
    DMA_AUTO_RELOAD_EN,
} DmaAutoreloadStatus;

typedef enum _DmaGatherStatus
{
    DMA_SRC_GATHER_DIS = 0,
    DMA_SRC_GATHER_EN,
} DmaGatherStatus;

typedef enum _DmaScatterStatus
{
    DMA_DST_SCATTER_DIS = 0,
    DMA_DST_SCATTER_EN,
} DmaScatterStatus;

typedef enum _DmaFifoMode
{
    DMA_FIFOMODE_SINGLE = 0,
    DMA_FIFOMODE_HALF,
} DmaFifoMode;

typedef enum _DmaChannelPriority
{
    /*!< DMA Channel priority is 0. */
    DMA_CHANNEL_PRIORITY_0 = 0,
    /*!< DMA Channel priority is 1. */
    DMA_CHANNEL_PRIORITY_1,
    /*!< DMA Channel priority is 2. */
    DMA_CHANNEL_PRIORITY_2,
    /*!< DMA Channel priority is 3. */
    DMA_CHANNEL_PRIORITY_3,
    /*!< DMA Channel priority is 4. */
    DMA_CHANNEL_PRIORITY_4,
    /*!< DMA Channel priority is 5. */
    DMA_CHANNEL_PRIORITY_5,
    /*!< DMA Channel priority is 6. */
    DMA_CHANNEL_PRIORITY_6,
    /*!< DMA Channel priority is 7. */
    DMA_CHANNEL_PRIORITY_7
} DmaChannelPriority;

typedef enum _DmaHwinterface
{
    /*!< DMA Hardware Interface 0.*/
    DMA_CHANNEL_HW_INTERF_0 = 0,
    /*!< DMA Hardware Interface 1.*/
    DMA_CHANNEL_HW_INTERF_1,
    /*!< DMA Hardware Interface 2.*/
    DMA_CHANNEL_HW_INTERF_2,
    /*!< DMA Hardware Interface 3.*/
    DMA_CHANNEL_HW_INTERF_3,
    /*!< DMA Hardware Interface 4.*/
    DMA_CHANNEL_HW_INTERF_4,
    /*!< DMA Hardware Interface 5.*/
    DMA_CHANNEL_HW_INTERF_5,
    /*!< DMA Hardware Interface 6.*/
    DMA_CHANNEL_HW_INTERF_6,
    /*!< DMA Hardware Interface 7.*/
    DMA_CHANNEL_HW_INTERF_7,
    /*!< DMA Hardware Interface 8.*/
    DMA_CHANNEL_HW_INTERF_8,
    /*!< DMA Hardware Interface 9.*/
    DMA_CHANNEL_HW_INTERF_9,
    /*!< DMA Hardware Interface 10.*/
    DMA_CHANNEL_HW_INTERF_10,
    /*!< DMA Hardware Interface 11.*/
    DMA_CHANNEL_HW_INTERF_11,
    /*!< DMA Hardware Interface 12.*/
    DMA_CHANNEL_HW_INTERF_12,
    /*!< DMA Hardware Interface 13.*/
    DMA_CHANNEL_HW_INTERF_13,
    /*!< DMA Hardware Interface 14.*/
    DMA_CHANNEL_HW_INTERF_14,
    /*!< DMA Hardware Interface 15.*/
    DMA_CHANNEL_HW_INTERF_15,
} DmaHwinterface;

typedef enum DmaTranstype
{
    DMA_TYPE_SINGLE                = 0x00,
    DMA_TYPE_GATHER_SCATTER        = 0x01,
    DMA_TYPE_LINKEDLIST            = 0x02,
    DMA_TYPE_LINKEDLIST_CONTIGU    = 0x04,
    DMA_TYPE_CONTIGU_LINKEDLIST    = 0x08,
    DMA_TYPE_AUTORELOAD            = 0x10,
    DMA_TYPE_LINKEDLIST_AUTORELOAD = 0x11,
    DMA_TYPE_AUTORELOAD_LINKEDLIST = 0x12,
    DMA_TYPE_AUTORELOAD_CONTIGU    = 0x14,
    DMA_TYPE_CONTIGU_AUTORELOAD    = 0x18,
    DMA_TYPE_AUTORELOAD_MASK       = 0x10,
} DmaTranstype ;

typedef enum _DmaTransComplete
{
    DMA_TRANS_IN_PROCESS = 0,
    DMA_TRANS_END,
} DmaTransComplete;

typedef enum _DmaApplication
{
    DMA_APPLI_MEM                  = 0x600,
    DMA_APPLI_I2C0_TX              = 0x001,
    DMA_APPLI_I2C1_TX              = 0x002,
    DMA_APPLI_UART0_TX             = 0x003,
    DMA_APPLI_UART1_TX             = 0x004,
    DMA_APPLI_UART2_TX             = 0x005,
    DMA_APPLI_UART3_TX             = 0x006,
    DMA_APPLI_RS232_RS485_HBS_0_TX = 0x007,
    DMA_APPLI_RS232_RS485_HBS_1_TX = 0x008,
    DMA_APPLI_CRC_TX               = 0x009,

    DMA_APPLI_AUDIO_TX             = 0x411,
    DMA_APPLI_SPI0_TX              = 0x420,
    DMA_APPLI_SPI1_TX              = 0x421,
    DMA_APPLI_QSPI0_TX             = 0x422,
    DMA_APPLI_QSPI1_TX             = 0x423,

    DMA_APPLI_CAN_TX               = 0x624,

    DMA_APPLI_I2C0_RX              = 0x830,
    DMA_APPLI_I2C1_RX              = 0x831,
    DMA_APPLI_UART0_RX             = 0x832,
    DMA_APPLI_UART1_RX             = 0x833,
    DMA_APPLI_UART2_RX             = 0x834,
    DMA_APPLI_UART3_RX             = 0x835,
    DMA_APPLI_RS232_RS485_HBS_0_RX = 0x836,
    DMA_APPLI_RS232_RS485_HBS_1_RX = 0x837,

    DMA_APPLI_SPI0_RX              = 0xc50,
    DMA_APPLI_SPI1_RX              = 0xc51,
    DMA_APPLI_QSPI0_RX             = 0xc52,
    DMA_APPLI_QSPI1_RX             = 0xc53,

    DMA_APPLI_AUDIO1_RX_L          = 0xe54,
    DMA_APPLI_AUDIO1_RX_R          = 0xe55,
    DMA_APPLI_VAD_RX_L             = 0xe56,
    DMA_APPLI_VAD_RX_R             = 0xe57,
    DMA_APPLI_CAN_RX              = 0xe58,

}DmaApplication;

#define DMA_APPLI_PERIPHERAL_TO_MEM_MASK      0x800
#define DMA_APPLI_DATAWIDTH32_MASK            0x400
#define DMA_APPLI_HIGH_SPEED_MASK             0x200
#define DMA_APPLI_MIDDLE_SPEED_MASK           0x100

typedef enum _DmaStatusChannel
{
    DMA_STATUS_CHANNEL0 = 0x01,
    DMA_STATUS_CHANNEL1 = 0x02,
    DMA_STATUS_CHANNEL2 = 0x04,
    DMA_STATUS_CHANNEL3 = 0x08,
    DMA_STATUS_CHANNEL4 = 0x10,
    DMA_STATUS_CHANNEL5 = 0x20,
    DMA_STATUS_CHANNEL6 = 0x40,
    DMA_STATUS_CHANNEL7 = 0x80,
} DmaStatusChannel;

typedef enum _DmaIntStatusFlag
{
    DMA_FLAG_TFR      = 0x01,
    DMA_FLAG_BLOCK    = 0x02,
    DMA_FLAG_SRCTRAN  = 0x04,
    DMA_FLAG_DESTTRAN = 0x08,
    DMA_FLAG_ERR      = 0x10,
    DMA_FLAG_MASK     = 0x1f,
} DmaIntStatusFlag;

typedef struct _DmaSrcGather
{
    DmaGatherStatus   SrcGatherEn;
    UINT32   SrcGatherInterval;
    UINT32   SrcGatherCount;
} DmaSrcGather ;

typedef struct _DmaDstScatter
{
    DmaScatterStatus   DstScatterEn;
    UINT32   DstScatterInterval;
    UINT32   DstScatterCount;
} DmaDstScatter ;

typedef struct _DmaLinkedList
{
    UINT32   SrcAddr;
    UINT32   DstAddr;
    UINT32   NextLinkedListAddr;
    UINT32   CtrlVal_L;
    UINT32   CtrlVal_H;
    UINT32   SrcState;
    UINT32   DstState;
    UINT32   tmp;
} DmaLinkedList ;

typedef Status (*XferCpltCallbackType)(void *arg);
typedef Status (*XferErrorCallbackType)(void *arg);

typedef struct _DmaInitParam
{
    /*!< The channel is  belong to which dma.                    */
    DmaPortChannel      PortChannelNum;
    DmaTranstype        transType;
    DmaApplication      Application;
    UINT32              BlockNum;
    /*!< Source Address.                                        */
    UINT32              SrcAddr;
    /*!< Destination Address.                                   */
    UINT32              DstAddr;
    /*!< A block numbers of datas.                              */
    UINT32              BlockDataNum;
    /*!< Transfer direction and Flow Controller.                */
    DmaDirection        Direction;
    /*!< Source address increase.                               */
    DmaSink             Sink;
    /*!< Destination address increase.                          */
    DmaDink             Dink;
    /*!< Source size of a data.                                 */
    DmaDataSize         SrcDataSize;
    /*!< Destination size of a data.                            */
    DmaDataSize         DstDataSize;
    /*!< 7 is the channel highest priority, and 0 is the lowest.*/
    DmaChannelPriority  ChPriority;
    DmaHwinterface      SrcInterface;
    DmaHwinterface      DstInterface;
    DmaBurstSize        SrcBurstSize;
    DmaBurstSize        DstBurstSize;
    DmaMasterMode       masterMode;

    DmaLinklistStatus       SrcLinkedListEn;
    DmaLinklistStatus       DstLinkedListEn;
    DmaAutoreloadStatus     SrcAutoReloadEn;
    DmaAutoreloadStatus     DstAutoReloadEn;
    /*!< DMA transfer complete callback                         */
    XferCpltCallbackType    XferCpltCallback;
    /*!< DMA transfer error callback                            */
    XferErrorCallbackType   XferErrorCallback;
} DmaInitParam;

typedef struct _DmaSelf
{
    DmaInitParam            InitParam;
    INT32                   portOffset;
    DmaTransComplete        TransCompleteFlag;
    void*                   parent;
}DmaSelf;

#define  DMA_PORT_BITS_MASK                             3
#define  DMA_CHANNEL_MASK                               0x07
#define  DMA_ONE_PORT_CHANNEL_COUNT                     8
#define  DMA_CHANNEL_REG_LENGTH                         0x58

#define  DMA_TIMEOUT                                    100
#define  DMA_ALL_CHANNEL_BUSY                           0x08
#define  DMA_WORK_LOOP                                  0xFFFFFFFF

/* pdma block ts 2048, width 32bit */
#define DMA_MEM_BLOCK_SIZE 8192

/** @brief 当多个src拼接到一个dst时，每个src和dst均是连续的。创建到一个LLC，启动一次dma传输。最后一个src的最后一个block结束传输。
 *  @param linkedListStem linklist to setup.
 *  @param SrcAddr srcaddr to move
 *  @param DstAddr DstAddr to move
 *  @param SrcSize total size to move
 *  @param uiLast whether the last src to transfer
 */
Status Hv_Cal_Dma_LLIbuild_BothContinous(DmaLinkedList* linkedListStem, UINT32 SrcAddr, UINT32 DstAddr, UINT32 SrcSize, UINT32 uiLast);
DmaPortChannel Hv_Cal_Dma_GetPortChannelNum(DmaSelf* self);

void Hv_Cal_Dma_SetParent(DmaSelf* self,void* parent);

void* Hv_Cal_Dma_GetParent(DmaSelf* self);


Status Hv_Cal_Dma_WaitTfrFlag(DmaSelf* self);

/** @brief Set the frame data transfer size of source
 *  @self channelparam no.
 *  @param FrameVal transfer data size
 */
void Hv_Cal_Dma_SetSrcFrameSize(DmaSelf* self, DmaDataSize FrameVal);

/** @brief Set the frame data transfer size of destination
 *  @self channelparam no.
 *  @param FrameVal transfer data size
 */
void Hv_Cal_Dma_SetDstFrameSize(DmaSelf* self, DmaDataSize FrameVal);

/** @brief Set the dma source address
 *  @self channelparam no.
 *  @param SrcAddr source address
 */
void Hv_Cal_Dma_SetSrcAddr(DmaSelf* self, UINT32 SrcAddr);

/** @brief Set the dma destination address
 *  @self channelparam no.
 *  @param DstAddr destination address
 */
void Hv_Cal_Dma_SetDstAddr(DmaSelf* self,UINT32 DstAddr);

/** @brief Set the dma block transfer size
 *  @self channelparam no.
 *  @param BlockSize size of block
 */
void Hv_Cal_Dma_SetBlockSize(DmaSelf* self,UINT32 BlockSize);

/** @brief Set the source address increment mode
 *  @self channelparam no.
 *  @param AddrChangeMode increment mode
 */
void Hv_Cal_Dma_SetSrcAddrMode(DmaSelf* self,DmaSink AddrChangeMode);

/** @brief Set the destination address increment mode
 *  @self channelparam no.
 *  @param AddrChangeMode increment mode
 */
void Hv_Cal_Dma_SetDstAddrMode(DmaSelf* self,DmaDink AddrChangeMode);

/** @brief Set the source burst transaction length
 *  @self channelparam no.
 *  @param BurstSize burst size
 */
void Hv_Cal_Dma_SetSrcBurstSize(DmaSelf* self,DmaBurstSize BurstSize);

/** @brief Set the destination burst transaction length
 *  @self channelparam no.
 *  @param BurstSize burst size
 */
void Hv_Cal_Dma_SetDstBurstSize(DmaSelf* self,DmaBurstSize BurstSize);

/** @brief Set the source master select
 *  @self channelparam no.
 *  @param AHBLayer sms selection, such as AHB master 1/2/3/4
 */
void Hv_Cal_Dma_SetSrcLayer(DmaSelf* self,DmaAhbSelect AHBLayer);

/** @brief Set the destination master select
 *  @self channelparam no.
 *  @param AHBLayer sms selection, such as AHB master 1/2/3/4
 */
void Hv_Cal_Dma_SetDstLayer(DmaSelf* self,DmaAhbSelect AHBLayer);

/** @brief Set the FIFO mode select
 *  @self channelparam no.
 *  @param FifoMode 0x0(FIFO_MODE_0), 0x1(FIFO_MODE_1)
 */
void Hv_Cal_Dma_SetFifoMode(DmaSelf* self,DmaFifoMode FifoMode);

/** @brief Set the address of next linked list item
 *  @self channelparam no.
 *  @param LinkedListStemAddr starting address in memory of next Link List Item if block chaining is enabled
 */
void Hv_Cal_Dma_SetLinkedListAddr(DmaSelf* self, DmaLinkedList* LinkedListStemAddr);

/** @brief Set the source gather parameters, includes en, interval, count
 *  @self channelparam no.
 *  @param pGather pointer to source gather structure
 */
void Hv_Cal_Dma_SetSrcGatherParam(DmaSelf* self,DmaSrcGather* pGather);

/** @brief Set the destination scatter parameters, includes en, interval, count
 *  @self channelparam no.
 *  @param pScatter pointer to destination scatter structure
 */
void Hv_Cal_Dma_SetDstScatterParam(DmaSelf* self,DmaDstScatter* pScatter);

/** @brief Bond the memory move complete callback
 *  @self channelparam no.
 *  @param CallbackFunc user defined callback fn.
 */
void Hv_Cal_Dma_XferCallbackBond(DmaSelf* self,void* CallbackFunc);

/** @brief Unbond the transfer complete callback
 *  @self channelparam no.
 *  @param CallbackFunc user defined callback fn.
 */
void Hv_Cal_Dma_XferCallbackUnBond(DmaSelf* self);

/** Configure the designated DMA channel
 *  @param  chCfgParam pointer to channel configuration parameters
 *  @param  isMemToMem is or not mem to mem
 *  @retval worked channel number
 */
DmaSelf* Hv_Cal_Dma_ChannelInit(DmaInitParam* InitParam);

/** De-initializes the DMA module.
 *  @param  self dma handler
 */
void Hv_Cal_Dma_CleanUp(DmaSelf* self);

/** Enable the designated DMA channel
 *  @param  PortChannelNum channel number
 */
void Hv_Cal_Dma_ChannelEn(DmaSelf* self);

/** Disable the designated DMA channel
 *  @param  PortChannelNum channel number
 */
void Hv_Cal_Dma_ChannelDis(DmaSelf* self);

/** Start the dma memory move
 *  @self channelparam number
 *  @param  SrcAddr source address
 *  @param  DstAddr destination address
 *  @param  blockSize block size
 */
void Hv_Cal_Dma_MemMove(DmaSelf* self, UINT32 SrcAddr, UINT32 DstAddr, UINT32 dataSize);

/** dma is complete or not
 *  @self channelparam number
 */
BOOL Hv_Cal_Dma_TransferIsComplete(DmaSelf *self);

/** dma just for testcase
 *  @linkedListStem
 */
BOOL Hv_Cal_Dma_Port1LinkedListStemBuild(DmaLinkedList* linkedListStem,UINT32 SrcAddr,UINT32 DstAddr, UINT32 SrcAddrOffset, UINT32 DstAddrOffset, UINT32 ConfigType, UINT32 BlockNum, UINT32 OneBlockSize,UINT32 LastBlockSize);

#endif




