#ifndef _HV_PAGE_HT7315_EDP_RX_DPCD_1_REG_00_H_
#define _HV_PAGE_HT7315_EDP_RX_DPCD_1_REG_00_H_

#ifndef HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS
    #define HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS                                         0x11048100
#endif


#define RX_EDP_RX_DPCD_1_REG_00_00                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_DPCD_1_REG_00_00_struct                                rs_rx_edp_rx_dpcd_1_reg_00_00

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_00  rs_rx_edp_rx_dpcd_1_reg_00_00;
struct _rs_rx_edp_rx_dpcd_1_reg_00_00 {
    unsigned int reg_00_dprx_dpcd_link_bw_set               : 8;
    unsigned int reg_00_dprx_dpcd_lane_count_set            : 5;
    unsigned int reg_00_dprx_dpcd_post_lt_adj_req_granted   : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dpcd_enhanced_frame_en         : 1;
    unsigned int reg_00_dprx_dpcd_training_pattern_select   : 4;
    unsigned int reg_00_dprx_dpcd_recovered_clock_out_en    : 1;
    unsigned int reg_00_dprx_dpcd_scrambling_disable        : 1;
    unsigned int reg_00_dprx_dpcd_symbol_error_count_sel    : 2;
    unsigned int reg_00_dprx_dpcd_lane0_voltage_swing_set   : 2;
    unsigned int reg_00_dprx_dpcd_lane0_max_swing_reached   : 1;
    unsigned int reg_00_dprx_dpcd_lane0_pre_emphasis_set    : 2;
    unsigned int reg_00_dprx_dpcd_lane0_max_pre_emphasis_reached: 1;
    unsigned int reserved_1                                 : 2;
};
#define rx_edp_rx_dpcd_1_reg_00_00(val) ((rs_rx_edp_rx_dpcd_1_reg_00_00*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_04                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_DPCD_1_REG_00_04_struct                                rs_rx_edp_rx_dpcd_1_reg_00_04

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_04  rs_rx_edp_rx_dpcd_1_reg_00_04;
struct _rs_rx_edp_rx_dpcd_1_reg_00_04 {
    unsigned int reg_00_dprx_dpcd_lane1_voltage_swing_set   : 2;
    unsigned int reg_00_dprx_dpcd_lane1_max_swing_reached   : 1;
    unsigned int reg_00_dprx_dpcd_lane1_pre_emphasis_set    : 2;
    unsigned int reg_00_dprx_dpcd_lane1_max_pre_emphasis_reached: 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_dprx_dpcd_lane2_voltage_swing_set   : 2;
    unsigned int reg_00_dprx_dpcd_lane2_max_swing_reached   : 1;
    unsigned int reg_00_dprx_dpcd_lane2_pre_emphasis_set    : 2;
    unsigned int reg_00_dprx_dpcd_lane2_max_pre_emphasis_reached: 1;
    unsigned int reserved_1                                 : 2;
    unsigned int reg_00_dprx_dpcd_lane3_voltage_swing_set   : 2;
    unsigned int reg_00_dprx_dpcd_lane3_max_swing_reached   : 1;
    unsigned int reg_00_dprx_dpcd_lane3_pre_emphasis_set    : 2;
    unsigned int reg_00_dprx_dpcd_lane3_max_pre_emphasis_reached: 1;
    unsigned int reserved_2                                 : 6;
    unsigned int reg_00_dprx_dpcd_downspread_ctrl_spread_amp: 1;
    unsigned int reserved_3                                 : 1;
    unsigned int reg_00_dprx_adaptive_sync_sdp_en           : 1;
    unsigned int reg_00_dprx_dpcd_downspread_msa_timing_par_ignore_en: 1;
};
#define rx_edp_rx_dpcd_1_reg_00_04(val) ((rs_rx_edp_rx_dpcd_1_reg_00_04*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_08                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_DPCD_1_REG_00_08_struct                                rs_rx_edp_rx_dpcd_1_reg_00_08

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_08  rs_rx_edp_rx_dpcd_1_reg_00_08;
struct _rs_rx_edp_rx_dpcd_1_reg_00_08 {
    unsigned int reg_00_dprx_dpcd_set_ansi_8b10b            : 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_dpcd_i2c_speed_ctrl            : 8;
    unsigned int reg_00_dprx_dpcd_alternate_scrambler_reset_enable: 1;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_00_dprx_dpcd_panel_self_test_enable    : 1;
    unsigned int reg_00_dprx_dpcd_lane0_link_qual_pattern_set: 3;
    unsigned int reserved_2                                 : 5;
};
#define rx_edp_rx_dpcd_1_reg_00_08(val) ((rs_rx_edp_rx_dpcd_1_reg_00_08*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_0C                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x0C)

#define RX_EDP_RX_DPCD_1_REG_00_0C_struct                                rs_rx_edp_rx_dpcd_1_reg_00_0c

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_0c  rs_rx_edp_rx_dpcd_1_reg_00_0c;
struct _rs_rx_edp_rx_dpcd_1_reg_00_0c {
    unsigned int reg_00_dprx_dpcd_lane1_link_qual_pattern_set: 3;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_lane2_link_qual_pattern_set: 3;
    unsigned int reserved_1                                 : 5;
    unsigned int reg_00_dprx_dpcd_lane3_link_qual_pattern_set: 3;
    unsigned int reserved_2                                 :13;
};
#define rx_edp_rx_dpcd_1_reg_00_0c(val) ((rs_rx_edp_rx_dpcd_1_reg_00_0c*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_10                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x10)

#define RX_EDP_RX_DPCD_1_REG_00_10_struct                                rs_rx_edp_rx_dpcd_1_reg_00_10

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_10  rs_rx_edp_rx_dpcd_1_reg_00_10;
struct _rs_rx_edp_rx_dpcd_1_reg_00_10 {
    unsigned int reg_00_dprx_dpcd_reserved_0x10             : 8;
    unsigned int reg_00_dprx_dpcd_mst_en                    : 1;
    unsigned int reg_00_dprx_dpcd_up_req_en                 : 1;
    unsigned int reg_00_dprx_dpcd_upstream_is_src           : 1;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_audio_delay0              :16;
};
#define rx_edp_rx_dpcd_1_reg_00_10(val) ((rs_rx_edp_rx_dpcd_1_reg_00_10*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_14                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x14)

#define RX_EDP_RX_DPCD_1_REG_00_14_struct                                rs_rx_edp_rx_dpcd_1_reg_00_14

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_14  rs_rx_edp_rx_dpcd_1_reg_00_14;
struct _rs_rx_edp_rx_dpcd_1_reg_00_14 {
    unsigned int reg_00_dprx_dpcd_audio_delay1              : 8;
    unsigned int reg_00_dprx_dpcd_link_rate_set             : 3;
    unsigned int reg_00_dprx_dpcd_tx_gtc_cap                : 1;
    unsigned int reg_00_dprx_dpcd_tx_gtc_slave_cap          : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_00_dprx_dpcd_alpm_enable               : 1;
    unsigned int reg_00_dprx_dpcd_alpm_lock_error_irq_hpd_enable: 1;
    unsigned int reg_00_dprx_dpcd_alpm_mode_selected        : 1;
    unsigned int reg_00_dprx_dpcd_alpm_period_of_cds_phase  : 1;
    unsigned int reserved_1                                 : 4;
    unsigned int reg_00_dprx_dpcd_aux_frame_sync_enable     : 1;
    unsigned int reg_00_dprx_dpcd_aux_frame_sync_irq_hpd_enable: 1;
    unsigned int reserved_2                                 : 6;
};
#define rx_edp_rx_dpcd_1_reg_00_14(val) ((rs_rx_edp_rx_dpcd_1_reg_00_14*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_18                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x18)

#define RX_EDP_RX_DPCD_1_REG_00_18_struct                                rs_rx_edp_rx_dpcd_1_reg_00_18

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_18  rs_rx_edp_rx_dpcd_1_reg_00_18;
struct _rs_rx_edp_rx_dpcd_1_reg_00_18 {
    unsigned int reg_00_dprx_dpcd_dp_pwr_not_needed_by_upstream_device: 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_dpcd_ext_dprx_sleep_wake_timeout_grant: 1;
    unsigned int reserved_1                                 :13;
    unsigned int reg_00_dprx_dpcd_source_adaptive_sync_sdp_t2_setup_enable: 1;
    unsigned int reg_00_dprx_dpcd_adaptive_sync_sdp_t2_set_for_all_pr_active_states: 1;
    unsigned int reserved_2                                 : 7;
    unsigned int reg_00_dprx_dpcd_as_sdp_one_line_earlier_enable: 1;
};
#define rx_edp_rx_dpcd_1_reg_00_18(val) ((rs_rx_edp_rx_dpcd_1_reg_00_18*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_20                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_DPCD_1_REG_00_20_struct                                rs_rx_edp_rx_dpcd_1_reg_00_20

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_20  rs_rx_edp_rx_dpcd_1_reg_00_20;
struct _rs_rx_edp_rx_dpcd_1_reg_00_20 {
    unsigned int reg_00_dprx_dpcd_fec_ready                 : 1;
    unsigned int reg_00_dprx_dpcd_fec_error_count_sel       : 3;
    unsigned int reg_00_dprx_dpcd_fec_lane_select           : 2;
    unsigned int reserved                                   :26;
};
#define rx_edp_rx_dpcd_1_reg_00_20(val) ((rs_rx_edp_rx_dpcd_1_reg_00_20*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_54                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x54)

#define RX_EDP_RX_DPCD_1_REG_00_54_struct                                rs_rx_edp_rx_dpcd_1_reg_00_54

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_54  rs_rx_edp_rx_dpcd_1_reg_00_54;
struct _rs_rx_edp_rx_dpcd_1_reg_00_54 {
    unsigned int reg_00_dprx_dpcd_tx_gtc_value              :32;
};
#define rx_edp_rx_dpcd_1_reg_00_54(val) ((rs_rx_edp_rx_dpcd_1_reg_00_54*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_58                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x58)

#define RX_EDP_RX_DPCD_1_REG_00_58_struct                                rs_rx_edp_rx_dpcd_1_reg_00_58

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_58  rs_rx_edp_rx_dpcd_1_reg_00_58;
struct _rs_rx_edp_rx_dpcd_1_reg_00_58 {
    unsigned int reg_00_dprx_dpcd_rx_gtc_value_phase_skew_en: 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_dpcd_tx_gtc_freq_lock_done     : 1;
    unsigned int reserved_1                                 : 7;
    unsigned int reg_00_dprx_dpcd_tx_gtc_phase_skew_offset  :16;
};
#define rx_edp_rx_dpcd_1_reg_00_58(val) ((rs_rx_edp_rx_dpcd_1_reg_00_58*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_5C                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x5C)

#define RX_EDP_RX_DPCD_1_REG_00_5C_struct                                rs_rx_edp_rx_dpcd_1_reg_00_5c

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_5c  rs_rx_edp_rx_dpcd_1_reg_00_5c;
struct _rs_rx_edp_rx_dpcd_1_reg_00_5c {
    unsigned int reg_00_dprx_dpcd_aux_frame_sync_valid      : 1;
    unsigned int reg_00_dprx_dpcd_aux_frame_sync_tx_vbe_master_value:31;
};
#define rx_edp_rx_dpcd_1_reg_00_5c(val) ((rs_rx_edp_rx_dpcd_1_reg_00_5c*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_60                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_DPCD_1_REG_00_60_struct                                rs_rx_edp_rx_dpcd_1_reg_00_60

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_60  rs_rx_edp_rx_dpcd_1_reg_00_60;
struct _rs_rx_edp_rx_dpcd_1_reg_00_60 {
    unsigned int reg_00_dprx_dpcd_dsc_en                    : 1;
    unsigned int reserved                                   :31;
};
#define rx_edp_rx_dpcd_1_reg_00_60(val) ((rs_rx_edp_rx_dpcd_1_reg_00_60*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_70                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0x70)

#define RX_EDP_RX_DPCD_1_REG_00_70_struct                                rs_rx_edp_rx_dpcd_1_reg_00_70

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_70  rs_rx_edp_rx_dpcd_1_reg_00_70;
struct _rs_rx_edp_rx_dpcd_1_reg_00_70 {
    unsigned int reg_00_dprx_dpcd_psr_source_device_enable_psr_in_sink_device: 1;
    unsigned int reg_00_dprx_dpcd_psr_source_device_transmitter_state_in_psr_active: 1;
    unsigned int reg_00_dprx_dpcd_psr_crc_verification_in_psr_active: 1;
    unsigned int reg_00_dprx_dpcd_psr_frame_capture_indication: 1;
    unsigned int reg_00_dprx_dpcd_psr_select_update_region_scan_line_capture_indication: 1;
    unsigned int reg_00_dprx_dpcd_psr_irq_hpd_with_link_crc_errors: 1;
    unsigned int reg_00_dprx_dpcd_enable_psr2_protocol      : 1;
    unsigned int reg_00_dprx_dpcd_psr_su_region_early_transport_enable: 1;
    unsigned int reserved                                   :24;
};
#define rx_edp_rx_dpcd_1_reg_00_70(val) ((rs_rx_edp_rx_dpcd_1_reg_00_70*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_A0                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0xA0)

#define RX_EDP_RX_DPCD_1_REG_00_A0_struct                                rs_rx_edp_rx_dpcd_1_reg_00_a0

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_a0  rs_rx_edp_rx_dpcd_1_reg_00_a0;
struct _rs_rx_edp_rx_dpcd_1_reg_00_a0 {
    unsigned int reg_00_dprx_dpcd_force_load_sense          : 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_dpcd_hpd_event_notiffication_type: 1;
    unsigned int reserved_1                                 :23;
};
#define rx_edp_rx_dpcd_1_reg_00_a0(val) ((rs_rx_edp_rx_dpcd_1_reg_00_a0*)&(val))



#define RX_EDP_RX_DPCD_1_REG_00_C0                                       (HV_EDP_RX_DPCD_1_REG_00_BASE_ADDRESS + 0xC0)

#define RX_EDP_RX_DPCD_1_REG_00_C0_struct                                rs_rx_edp_rx_dpcd_1_reg_00_c0

typedef struct _rs_rx_edp_rx_dpcd_1_reg_00_c0  rs_rx_edp_rx_dpcd_1_reg_00_c0;
struct _rs_rx_edp_rx_dpcd_1_reg_00_c0 {
    unsigned int reg_00_dprx_dpcd_vc_payload_id_to_be_allocated: 7;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dpcd_payload_allocate_start_time_slot: 6;
    unsigned int reserved_1                                 : 2;
    unsigned int reg_00_dprx_dpcd_payload_allocate_time_slot_count: 6;
    unsigned int reserved_2                                 :10;
};
#define rx_edp_rx_dpcd_1_reg_00_c0(val) ((rs_rx_edp_rx_dpcd_1_reg_00_c0*)&(val))



#endif