/**
 * @file HS_PAGE_HT7315_8051_reg.h
 * @brief This header file defines register address/mask.
 * @date 2023/4/26
 * @version V90
 * @svn svn6534
 * @author PCTool
 * @par Register Define  - Copyright (C) 2014 Kiwi-Image Co. LTD
 * @par History:
*/

/* This file is auto generated. Do not edit. Date: 2023/4/26 19:49:08 */

#ifndef _REG_HT7315_HEADER_
#define _REG_HT7315_HEADER_


#define KIWI_REG(name) name##_ADDR,name##_BITSTART,name##_BITEND


#define HS_Standby__standby_mcu_reg__reg_dma_xdata_addr_15_0_ADDR 0x11008000
#define HS_Standby__standby_mcu_reg__reg_dma_xdata_addr_15_0_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_dma_xdata_addr_15_0_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_length_cnt_15_0_ADDR 0x11008000
#define HS_Standby__standby_mcu_reg__reg_length_cnt_15_0_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_length_cnt_15_0_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_length_cnt_22_16_ADDR 0x11008004
#define HS_Standby__standby_mcu_reg__reg_length_cnt_22_16_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_length_cnt_22_16_BITEND 6

#define HS_Standby__standby_mcu_reg__reg_length_cnt_flag_ADDR 0x11008004
#define HS_Standby__standby_mcu_reg__reg_length_cnt_flag_BITSTART 7
#define HS_Standby__standby_mcu_reg__reg_length_cnt_flag_BITEND 7

#define HS_Standby__standby_mcu_reg__reg_code_spi_addr_ADDR 0x11008004
#define HS_Standby__standby_mcu_reg__reg_code_spi_addr_BITSTART 8
#define HS_Standby__standby_mcu_reg__reg_code_spi_addr_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_dma_xdata_addr_19_16_ADDR 0x11008008
#define HS_Standby__standby_mcu_reg__reg_dma_xdata_addr_19_16_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_dma_xdata_addr_19_16_BITEND 3

#define HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_BITEND 0

#define HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_stby_iso_BITSTART 1
#define HS_Standby__standby_mcu_reg__reg_stby_iso_BITEND 1

#define HS_Standby__standby_mcu_reg__reg_power_on_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_power_on_BITSTART 2
#define HS_Standby__standby_mcu_reg__reg_power_on_BITEND 2

#define HS_Standby__standby_mcu_reg__reg_mcu_spi_dis_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_mcu_spi_dis_BITSTART 3
#define HS_Standby__standby_mcu_reg__reg_mcu_spi_dis_BITEND 3

#define HS_Standby__standby_mcu_reg__reg_apb_clk_sel_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_apb_clk_sel_BITSTART 4
#define HS_Standby__standby_mcu_reg__reg_apb_clk_sel_BITEND 4

#define HS_Standby__standby_mcu_reg__reg_cpu_rom_addr_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_cpu_rom_addr_BITSTART 5
#define HS_Standby__standby_mcu_reg__reg_cpu_rom_addr_BITEND 20

#define HS_Standby__standby_mcu_reg__reg_spi_cpol_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_spi_cpol_BITSTART 21
#define HS_Standby__standby_mcu_reg__reg_spi_cpol_BITEND 21

#define HS_Standby__standby_mcu_reg__reg_spi_cpha_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_spi_cpha_BITSTART 22
#define HS_Standby__standby_mcu_reg__reg_spi_cpha_BITEND 22

#define HS_Standby__standby_mcu_reg__reg_spi_speed_ADDR 0x11008010
#define HS_Standby__standby_mcu_reg__reg_spi_speed_BITSTART 23
#define HS_Standby__standby_mcu_reg__reg_spi_speed_BITEND 25

#define HS_Standby__standby_mcu_reg__reg_xram_mem_reg_ADDR 0x11008014
#define HS_Standby__standby_mcu_reg__reg_xram_mem_reg_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_xram_mem_reg_BITEND 7

#define HS_Standby__standby_mcu_reg__reg_xram_mem_ema_ADDR 0x11008014
#define HS_Standby__standby_mcu_reg__reg_xram_mem_ema_BITSTART 8
#define HS_Standby__standby_mcu_reg__reg_xram_mem_ema_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_xram_mem_ls_ADDR 0x11008014
#define HS_Standby__standby_mcu_reg__reg_xram_mem_ls_BITSTART 24
#define HS_Standby__standby_mcu_reg__reg_xram_mem_ls_BITEND 24

#define HS_Standby__standby_mcu_reg__regr_xram_mem_ro_ADDR 0x11008014
#define HS_Standby__standby_mcu_reg__regr_xram_mem_ro_BITSTART 25
#define HS_Standby__standby_mcu_reg__regr_xram_mem_ro_BITEND 28

#define HS_Standby__standby_mcu_reg__reg_xram_mem_sleep_en_ADDR 0x11008014
#define HS_Standby__standby_mcu_reg__reg_xram_mem_sleep_en_BITSTART 29
#define HS_Standby__standby_mcu_reg__reg_xram_mem_sleep_en_BITEND 29

#define HS_Standby__standby_mcu_reg__reg_xram_mem_cs_ADDR 0x11008014
#define HS_Standby__standby_mcu_reg__reg_xram_mem_cs_BITSTART 30
#define HS_Standby__standby_mcu_reg__reg_xram_mem_cs_BITEND 30

#define HS_Standby__standby_mcu_reg__reg_xram_mem_mbist_ADDR 0x11008014
#define HS_Standby__standby_mcu_reg__reg_xram_mem_mbist_BITSTART 31
#define HS_Standby__standby_mcu_reg__reg_xram_mem_mbist_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_host_scl_filter_ADDR 0x11008018
#define HS_Standby__standby_mcu_reg__reg_host_scl_filter_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_host_scl_filter_BITEND 7

#define HS_Standby__standby_mcu_reg__reg_host_sda_filter_ADDR 0x11008018
#define HS_Standby__standby_mcu_reg__reg_host_sda_filter_BITSTART 8
#define HS_Standby__standby_mcu_reg__reg_host_sda_filter_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_stby_reg0_ADDR 0x1100801C
#define HS_Standby__standby_mcu_reg__reg_stby_reg0_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg0_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg1_ADDR 0x11008020
#define HS_Standby__standby_mcu_reg__reg_stby_reg1_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg1_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg2_ADDR 0x11008024
#define HS_Standby__standby_mcu_reg__reg_stby_reg2_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg2_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg3_ADDR 0x11008028
#define HS_Standby__standby_mcu_reg__reg_stby_reg3_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg3_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg4_ADDR 0x1100802C
#define HS_Standby__standby_mcu_reg__reg_stby_reg4_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg4_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg5_ADDR 0x11008030
#define HS_Standby__standby_mcu_reg__reg_stby_reg5_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg5_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg6_ADDR 0x11008034
#define HS_Standby__standby_mcu_reg__reg_stby_reg6_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg6_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg7_ADDR 0x11008038
#define HS_Standby__standby_mcu_reg__reg_stby_reg7_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg7_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_off_int_clr_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_off_int_clr_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_off_int_clr_BITEND 0

#define HS_Standby__standby_mcu_reg__reg_off_int_en_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_off_int_en_BITSTART 1
#define HS_Standby__standby_mcu_reg__reg_off_int_en_BITEND 1

#define HS_Standby__standby_mcu_reg__reg_off_int_level_p_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_off_int_level_p_BITSTART 2
#define HS_Standby__standby_mcu_reg__reg_off_int_level_p_BITEND 2

#define HS_Standby__standby_mcu_reg__reg_off_int_level_n_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_off_int_level_n_BITSTART 3
#define HS_Standby__standby_mcu_reg__reg_off_int_level_n_BITEND 3

#define HS_Standby__standby_mcu_reg__reg_off_int_edge_p_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_off_int_edge_p_BITSTART 4
#define HS_Standby__standby_mcu_reg__reg_off_int_edge_p_BITEND 4

#define HS_Standby__standby_mcu_reg__reg_off_int_edge_n_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_off_int_edge_n_BITSTART 5
#define HS_Standby__standby_mcu_reg__reg_off_int_edge_n_BITEND 5

#define HS_Standby__standby_mcu_reg__regr_off_int_stat_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__regr_off_int_stat_BITSTART 6
#define HS_Standby__standby_mcu_reg__regr_off_int_stat_BITEND 6

#define HS_Standby__standby_mcu_reg__reg_stby_int_clr_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_stby_int_clr_BITSTART 7
#define HS_Standby__standby_mcu_reg__reg_stby_int_clr_BITEND 7

#define HS_Standby__standby_mcu_reg__reg_stby_int_en_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_stby_int_en_BITSTART 8
#define HS_Standby__standby_mcu_reg__reg_stby_int_en_BITEND 8

#define HS_Standby__standby_mcu_reg__reg_stby_int_level_p_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_stby_int_level_p_BITSTART 9
#define HS_Standby__standby_mcu_reg__reg_stby_int_level_p_BITEND 9

#define HS_Standby__standby_mcu_reg__reg_stby_int_level_n_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_stby_int_level_n_BITSTART 10
#define HS_Standby__standby_mcu_reg__reg_stby_int_level_n_BITEND 10

#define HS_Standby__standby_mcu_reg__reg_stby_int_edge_p_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_stby_int_edge_p_BITSTART 11
#define HS_Standby__standby_mcu_reg__reg_stby_int_edge_p_BITEND 11

#define HS_Standby__standby_mcu_reg__reg_stby_int_edge_n_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__reg_stby_int_edge_n_BITSTART 12
#define HS_Standby__standby_mcu_reg__reg_stby_int_edge_n_BITEND 12

#define HS_Standby__standby_mcu_reg__regr_stby_int_stat_ADDR 0x1100803C
#define HS_Standby__standby_mcu_reg__regr_stby_int_stat_BITSTART 13
#define HS_Standby__standby_mcu_reg__regr_stby_int_stat_BITEND 13

#define HS_Standby__standby_mcu_reg__reg_act_to_stby_ADDR 0x11008040
#define HS_Standby__standby_mcu_reg__reg_act_to_stby_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_act_to_stby_BITEND 0

#define HS_Standby__standby_mcu_reg__reg_dp_filter_num_ADDR 0x11008044
#define HS_Standby__standby_mcu_reg__reg_dp_filter_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_dp_filter_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_dp_pol_ADDR 0x11008044
#define HS_Standby__standby_mcu_reg__reg_dp_pol_BITSTART 24
#define HS_Standby__standby_mcu_reg__reg_dp_pol_BITEND 24

#define HS_Standby__standby_mcu_reg__reg_apb_clk_div_num_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_apb_clk_div_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_apb_clk_div_num_BITEND 1

#define HS_Standby__standby_mcu_reg__reg_apb_clk_en_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_apb_clk_en_BITSTART 2
#define HS_Standby__standby_mcu_reg__reg_apb_clk_en_BITEND 2

#define HS_Standby__standby_mcu_reg__reg_aux0_rst_n_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_aux0_rst_n_BITSTART 3
#define HS_Standby__standby_mcu_reg__reg_aux0_rst_n_BITEND 3

#define HS_Standby__standby_mcu_reg__reg_i2c_rst_n_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_i2c_rst_n_BITSTART 4
#define HS_Standby__standby_mcu_reg__reg_i2c_rst_n_BITEND 4

#define HS_Standby__standby_mcu_reg__reg_gpio_rst_n_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_gpio_rst_n_BITSTART 5
#define HS_Standby__standby_mcu_reg__reg_gpio_rst_n_BITEND 5

#define HS_Standby__standby_mcu_reg__reg_i2c_spi_mcu_rst_n_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_i2c_spi_mcu_rst_n_BITSTART 6
#define HS_Standby__standby_mcu_reg__reg_i2c_spi_mcu_rst_n_BITEND 6

#define HS_Standby__standby_mcu_reg__reg_mcu_sw_rst_n_delay_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_mcu_sw_rst_n_delay_BITSTART 7
#define HS_Standby__standby_mcu_reg__reg_mcu_sw_rst_n_delay_BITEND 22

#define HS_Standby__standby_mcu_reg__reg_src_clk_en_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_src_clk_en_BITSTART 23
#define HS_Standby__standby_mcu_reg__reg_src_clk_en_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_osc_0_div_num_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_osc_0_div_num_BITSTART 24
#define HS_Standby__standby_mcu_reg__reg_osc_0_div_num_BITEND 26

#define HS_Standby__standby_mcu_reg__reg_mcu_clk_div_num_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_mcu_clk_div_num_BITSTART 27
#define HS_Standby__standby_mcu_reg__reg_mcu_clk_div_num_BITEND 28

#define HS_Standby__standby_mcu_reg__reg_mcu_clk_sel_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_mcu_clk_sel_BITSTART 29
#define HS_Standby__standby_mcu_reg__reg_mcu_clk_sel_BITEND 29

#define HS_Standby__standby_mcu_reg__reg_mcu_clk_en_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_mcu_clk_en_BITSTART 30
#define HS_Standby__standby_mcu_reg__reg_mcu_clk_en_BITEND 30

#define HS_Standby__standby_mcu_reg__reg_aux1_rst_n_ADDR 0x11008048
#define HS_Standby__standby_mcu_reg__reg_aux1_rst_n_BITSTART 31
#define HS_Standby__standby_mcu_reg__reg_aux1_rst_n_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_mcu_sw_rst_ADDR 0x1100804C
#define HS_Standby__standby_mcu_reg__reg_mcu_sw_rst_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_mcu_sw_rst_BITEND 0

#define HS_Standby__standby_mcu_reg__regr_stb_sw_rst_n_ADDR 0x11008050
#define HS_Standby__standby_mcu_reg__regr_stb_sw_rst_n_BITSTART 0
#define HS_Standby__standby_mcu_reg__regr_stb_sw_rst_n_BITEND 0

#define HS_Standby__standby_mcu_reg__regr_stby_iso_ADDR 0x11008050
#define HS_Standby__standby_mcu_reg__regr_stby_iso_BITSTART 1
#define HS_Standby__standby_mcu_reg__regr_stby_iso_BITEND 1

#define HS_Standby__standby_mcu_reg__regr_power_on_ADDR 0x11008050
#define HS_Standby__standby_mcu_reg__regr_power_on_BITSTART 2
#define HS_Standby__standby_mcu_reg__regr_power_on_BITEND 2

#define HS_Standby__standby_mcu_reg__reg_power_on_cnt_ADDR 0x11008050
#define HS_Standby__standby_mcu_reg__reg_power_on_cnt_BITSTART 3
#define HS_Standby__standby_mcu_reg__reg_power_on_cnt_BITEND 10

#define HS_Standby__standby_mcu_reg__reg_stby_iso_cnt_ADDR 0x11008050
#define HS_Standby__standby_mcu_reg__reg_stby_iso_cnt_BITSTART 11
#define HS_Standby__standby_mcu_reg__reg_stby_iso_cnt_BITEND 18

#define HS_Standby__standby_mcu_reg__reg_stb_rst_n_cnt_ADDR 0x11008050
#define HS_Standby__standby_mcu_reg__reg_stb_rst_n_cnt_BITSTART 19
#define HS_Standby__standby_mcu_reg__reg_stb_rst_n_cnt_BITEND 26

#define HS_Standby__standby_mcu_reg__regr_stb_pwr_on_ADDR 0x11008050
#define HS_Standby__standby_mcu_reg__regr_stb_pwr_on_BITSTART 27
#define HS_Standby__standby_mcu_reg__regr_stb_pwr_on_BITEND 27

#define HS_Standby__standby_mcu_reg__reg_dbg_sel_ADDR 0x11008054
#define HS_Standby__standby_mcu_reg__reg_dbg_sel_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_dbg_sel_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_wake_int_clr_ADDR 0x11008060
#define HS_Standby__standby_mcu_reg__reg_wake_int_clr_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_wake_int_clr_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR 0x11008060
#define HS_Standby__standby_mcu_reg__reg_wake_int_en_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_wake_int_en_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_wake_int_level_p_ADDR 0x11008064
#define HS_Standby__standby_mcu_reg__reg_wake_int_level_p_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_wake_int_level_p_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_wake_int_level_n_ADDR 0x11008064
#define HS_Standby__standby_mcu_reg__reg_wake_int_level_n_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_wake_int_level_n_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR 0x11008068
#define HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_wake_int_edge_n_ADDR 0x11008068
#define HS_Standby__standby_mcu_reg__reg_wake_int_edge_n_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_wake_int_edge_n_BITEND 31

#define HS_Standby__standby_mcu_reg__regr_wake_int_stat_ADDR 0x1100806C
#define HS_Standby__standby_mcu_reg__regr_wake_int_stat_BITSTART 0
#define HS_Standby__standby_mcu_reg__regr_wake_int_stat_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_hdmi_filter_num_ADDR 0x11008070
#define HS_Standby__standby_mcu_reg__reg_hdmi_filter_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_hdmi_filter_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_hdmi_pol_ADDR 0x11008070
#define HS_Standby__standby_mcu_reg__reg_hdmi_pol_BITSTART 24
#define HS_Standby__standby_mcu_reg__reg_hdmi_pol_BITEND 24

#define HS_Standby__standby_mcu_reg__reg_osc_1_div_num_ADDR 0x11008070
#define HS_Standby__standby_mcu_reg__reg_osc_1_div_num_BITSTART 29
#define HS_Standby__standby_mcu_reg__reg_osc_1_div_num_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_aux0_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_aux0_clk_en_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_aux0_clk_en_BITEND 0

#define HS_Standby__standby_mcu_reg__reg_gpio_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_gpio_clk_en_BITSTART 1
#define HS_Standby__standby_mcu_reg__reg_gpio_clk_en_BITEND 1

#define HS_Standby__standby_mcu_reg__reg_adc0_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_adc0_clk_en_BITSTART 2
#define HS_Standby__standby_mcu_reg__reg_adc0_clk_en_BITEND 2

#define HS_Standby__standby_mcu_reg__reg_pwm_pclk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_pwm_pclk_en_BITSTART 3
#define HS_Standby__standby_mcu_reg__reg_pwm_pclk_en_BITEND 3

#define HS_Standby__standby_mcu_reg__reg_adc0_rst_n_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_adc0_rst_n_BITSTART 4
#define HS_Standby__standby_mcu_reg__reg_adc0_rst_n_BITEND 4

#define HS_Standby__standby_mcu_reg__reg_pwm_presetn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_pwm_presetn_BITSTART 5
#define HS_Standby__standby_mcu_reg__reg_pwm_presetn_BITEND 5

#define HS_Standby__standby_mcu_reg__reg_aux1_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_aux1_clk_en_BITSTART 6
#define HS_Standby__standby_mcu_reg__reg_aux1_clk_en_BITEND 6

#define HS_Standby__standby_mcu_reg__reg_rx_cec0_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_rx_cec0_clk_en_BITSTART 7
#define HS_Standby__standby_mcu_reg__reg_rx_cec0_clk_en_BITEND 7

#define HS_Standby__standby_mcu_reg__reg_rx_cec1_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_rx_cec1_clk_en_BITSTART 8
#define HS_Standby__standby_mcu_reg__reg_rx_cec1_clk_en_BITEND 8

#define HS_Standby__standby_mcu_reg__reg_hdmi0_osc_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi0_osc_clk_en_BITSTART 9
#define HS_Standby__standby_mcu_reg__reg_hdmi0_osc_clk_en_BITEND 9

#define HS_Standby__standby_mcu_reg__reg_hdmi1_osc_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi1_osc_clk_en_BITSTART 10
#define HS_Standby__standby_mcu_reg__reg_hdmi1_osc_clk_en_BITEND 10

#define HS_Standby__standby_mcu_reg__reg_hdmi0_pclk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi0_pclk_en_BITSTART 11
#define HS_Standby__standby_mcu_reg__reg_hdmi0_pclk_en_BITEND 11

#define HS_Standby__standby_mcu_reg__reg_hdmi1_pclk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi1_pclk_en_BITSTART 12
#define HS_Standby__standby_mcu_reg__reg_hdmi1_pclk_en_BITEND 12

#define HS_Standby__standby_mcu_reg__reg_cec0_rstn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_cec0_rstn_BITSTART 13
#define HS_Standby__standby_mcu_reg__reg_cec0_rstn_BITEND 13

#define HS_Standby__standby_mcu_reg__reg_cec1_rstn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_cec1_rstn_BITSTART 14
#define HS_Standby__standby_mcu_reg__reg_cec1_rstn_BITEND 14

#define HS_Standby__standby_mcu_reg__reg_hdmi0_osc_rstn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi0_osc_rstn_BITSTART 15
#define HS_Standby__standby_mcu_reg__reg_hdmi0_osc_rstn_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_hdmi1_osc_rstn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi1_osc_rstn_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_hdmi1_osc_rstn_BITEND 16

#define HS_Standby__standby_mcu_reg__reg_hdmi0_presetn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi0_presetn_BITSTART 17
#define HS_Standby__standby_mcu_reg__reg_hdmi0_presetn_BITEND 17

#define HS_Standby__standby_mcu_reg__reg_hdmi1_presetn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_hdmi1_presetn_BITSTART 18
#define HS_Standby__standby_mcu_reg__reg_hdmi1_presetn_BITEND 18

#define HS_Standby__standby_mcu_reg__reg_typec0_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec0_clk_en_BITSTART 19
#define HS_Standby__standby_mcu_reg__reg_typec0_clk_en_BITEND 19

#define HS_Standby__standby_mcu_reg__reg_typec1_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec1_clk_en_BITSTART 20
#define HS_Standby__standby_mcu_reg__reg_typec1_clk_en_BITEND 20

#define HS_Standby__standby_mcu_reg__reg_typec0_pclk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec0_pclk_en_BITSTART 21
#define HS_Standby__standby_mcu_reg__reg_typec0_pclk_en_BITEND 21

#define HS_Standby__standby_mcu_reg__reg_typec1_pclk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec1_pclk_en_BITSTART 22
#define HS_Standby__standby_mcu_reg__reg_typec1_pclk_en_BITEND 22

#define HS_Standby__standby_mcu_reg__reg_typec0_rstn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec0_rstn_BITSTART 23
#define HS_Standby__standby_mcu_reg__reg_typec0_rstn_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_typec1_rstn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec1_rstn_BITSTART 24
#define HS_Standby__standby_mcu_reg__reg_typec1_rstn_BITEND 24

#define HS_Standby__standby_mcu_reg__reg_typec0_presetn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec0_presetn_BITSTART 25
#define HS_Standby__standby_mcu_reg__reg_typec0_presetn_BITEND 25

#define HS_Standby__standby_mcu_reg__reg_typec1_presetn_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_typec1_presetn_BITSTART 26
#define HS_Standby__standby_mcu_reg__reg_typec1_presetn_BITEND 26

#define HS_Standby__standby_mcu_reg__reg_adc1_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_adc1_clk_en_BITSTART 27
#define HS_Standby__standby_mcu_reg__reg_adc1_clk_en_BITEND 27

#define HS_Standby__standby_mcu_reg__reg_adc1_rst_n_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_adc1_rst_n_BITSTART 28
#define HS_Standby__standby_mcu_reg__reg_adc1_rst_n_BITEND 28

#define HS_Standby__standby_mcu_reg__reg_rx_short_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_rx_short_clk_en_BITSTART 29
#define HS_Standby__standby_mcu_reg__reg_rx_short_clk_en_BITEND 29

#define HS_Standby__standby_mcu_reg__reg_rx_short_rst_n_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_rx_short_rst_n_BITSTART 30
#define HS_Standby__standby_mcu_reg__reg_rx_short_rst_n_BITEND 30

#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_clk_en_ADDR 0x11008074
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_clk_en_BITSTART 31
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_clk_en_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_rx_cec_clk_div_num_ADDR 0x11008078
#define HS_Standby__standby_mcu_reg__reg_rx_cec_clk_div_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rx_cec_clk_div_num_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_event_int_clr_ADDR 0x11008080
#define HS_Standby__standby_mcu_reg__reg_event_int_clr_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_event_int_clr_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_event_int_en_ADDR 0x11008080
#define HS_Standby__standby_mcu_reg__reg_event_int_en_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_event_int_en_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_event_int_level_p_ADDR 0x11008084
#define HS_Standby__standby_mcu_reg__reg_event_int_level_p_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_event_int_level_p_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_event_int_level_n_ADDR 0x11008084
#define HS_Standby__standby_mcu_reg__reg_event_int_level_n_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_event_int_level_n_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_event_int_edge_p_ADDR 0x11008088
#define HS_Standby__standby_mcu_reg__reg_event_int_edge_p_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_event_int_edge_p_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_event_int_edge_n_ADDR 0x11008088
#define HS_Standby__standby_mcu_reg__reg_event_int_edge_n_BITSTART 16
#define HS_Standby__standby_mcu_reg__reg_event_int_edge_n_BITEND 31

#define HS_Standby__standby_mcu_reg__regr_event_int_stat_ADDR 0x1100808C
#define HS_Standby__standby_mcu_reg__regr_event_int_stat_BITSTART 0
#define HS_Standby__standby_mcu_reg__regr_event_int_stat_BITEND 15

#define HS_Standby__standby_mcu_reg__reg_rx_det_filter_num_ADDR 0x11008090
#define HS_Standby__standby_mcu_reg__reg_rx_det_filter_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rx_det_filter_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_stby_reg8_ADDR 0x110080A0
#define HS_Standby__standby_mcu_reg__reg_stby_reg8_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg8_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_reg9_ADDR 0x110080A4
#define HS_Standby__standby_mcu_reg__reg_stby_reg9_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_reg9_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_rega_ADDR 0x110080A8
#define HS_Standby__standby_mcu_reg__reg_stby_rega_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_rega_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_regb_ADDR 0x110080AC
#define HS_Standby__standby_mcu_reg__reg_stby_regb_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_regb_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_regc_ADDR 0x110080B0
#define HS_Standby__standby_mcu_reg__reg_stby_regc_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_regc_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_regd_ADDR 0x110080B4
#define HS_Standby__standby_mcu_reg__reg_stby_regd_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_regd_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_rege_ADDR 0x110080B8
#define HS_Standby__standby_mcu_reg__reg_stby_rege_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_rege_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_stby_regf_ADDR 0x110080BC
#define HS_Standby__standby_mcu_reg__reg_stby_regf_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_stby_regf_BITEND 31

#define HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_ADDR 0x110080C0
#define HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_BITEND 3

#define HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_ADDR 0x110080C0
#define HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITSTART 4
#define HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITEND 7

#define HS_Standby__standby_mcu_reg__regr_rxphy_short_flag_ADDR 0x110080C0
#define HS_Standby__standby_mcu_reg__regr_rxphy_short_flag_BITSTART 8
#define HS_Standby__standby_mcu_reg__regr_rxphy_short_flag_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy0_short_det_pwm_l_num_ADDR 0x110080C4
#define HS_Standby__standby_mcu_reg__reg_rxphy0_short_det_pwm_l_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy0_short_det_pwm_l_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy0_short_det_pwm_h_num_ADDR 0x110080C8
#define HS_Standby__standby_mcu_reg__reg_rxphy0_short_det_pwm_h_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy0_short_det_pwm_h_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy1_short_det_pwm_l_num_ADDR 0x110080CC
#define HS_Standby__standby_mcu_reg__reg_rxphy1_short_det_pwm_l_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy1_short_det_pwm_l_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy1_short_det_pwm_h_num_ADDR 0x110080D0
#define HS_Standby__standby_mcu_reg__reg_rxphy1_short_det_pwm_h_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy1_short_det_pwm_h_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_ADDR 0x110080D4
#define HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_ADDR 0x110080D8
#define HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_ADDR 0x110080DC
#define HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_ADDR 0x110080E0
#define HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_BITEND 23

#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_en_ADDR 0x110080E4
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_en_BITSTART 0
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_en_BITEND 0

#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_set_ADDR 0x110080E4
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_set_BITSTART 4
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_set_BITEND 7

#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_hold_ADDR 0x110080E4
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_hold_BITSTART 8
#define HS_Standby__standby_mcu_reg__reg_bg33_res_measure_hold_BITEND 23

#define HS_Standby__standby_mcu_reg__regr_bg33_res_measure_set_ADDR 0x110080E4
#define HS_Standby__standby_mcu_reg__regr_bg33_res_measure_set_BITSTART 24
#define HS_Standby__standby_mcu_reg__regr_bg33_res_measure_set_BITEND 27

#define HS_Standby__standby_mcu_reg__regr_bg33_res_measure_done_ADDR 0x110080E4
#define HS_Standby__standby_mcu_reg__regr_bg33_res_measure_done_BITSTART 28
#define HS_Standby__standby_mcu_reg__regr_bg33_res_measure_done_BITEND 28

#define HS_Standby__standby_mcu_reg__regr_proga_ADDR 0x110080F0
#define HS_Standby__standby_mcu_reg__regr_proga_BITSTART 0
#define HS_Standby__standby_mcu_reg__regr_proga_BITEND 19

#define HS_Standby__standby_mcu_reg__regr_proga_en_ADDR 0x110080F0
#define HS_Standby__standby_mcu_reg__regr_proga_en_BITSTART 20
#define HS_Standby__standby_mcu_reg__regr_proga_en_BITEND 20

#define HS_Standby__standby_mcu_reg__regr_aux_wake_irq_ADDR 0x110080F0
#define HS_Standby__standby_mcu_reg__regr_aux_wake_irq_BITSTART 21
#define HS_Standby__standby_mcu_reg__regr_aux_wake_irq_BITEND 22

#define HS_Standby__standby_mcu_reg__regr_progdi_ADDR 0x110080F0
#define HS_Standby__standby_mcu_reg__regr_progdi_BITSTART 24
#define HS_Standby__standby_mcu_reg__regr_progdi_BITEND 31

#define HS_Standby__standby_mcu_reg__regr_xramdi_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_xramdi_BITSTART 0
#define HS_Standby__standby_mcu_reg__regr_xramdi_BITEND 7

#define HS_Standby__standby_mcu_reg__regr_xramdo_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_xramdo_BITSTART 8
#define HS_Standby__standby_mcu_reg__regr_xramdo_BITEND 15

#define HS_Standby__standby_mcu_reg__regr_nxramr_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_nxramr_BITSTART 16
#define HS_Standby__standby_mcu_reg__regr_nxramr_BITEND 16

#define HS_Standby__standby_mcu_reg__regr_nxramw_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_nxramw_BITSTART 17
#define HS_Standby__standby_mcu_reg__regr_nxramw_BITEND 17

#define HS_Standby__standby_mcu_reg__regr_xrama_en_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_xrama_en_BITSTART 18
#define HS_Standby__standby_mcu_reg__regr_xrama_en_BITEND 18

#define HS_Standby__standby_mcu_reg__regr_mwait_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_mwait_BITSTART 19
#define HS_Standby__standby_mcu_reg__regr_mwait_BITEND 19

#define HS_Standby__standby_mcu_reg__regr_mcu_idle_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_mcu_idle_BITSTART 20
#define HS_Standby__standby_mcu_reg__regr_mcu_idle_BITEND 20

#define HS_Standby__standby_mcu_reg__regr_act_to_stby_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_act_to_stby_BITSTART 21
#define HS_Standby__standby_mcu_reg__regr_act_to_stby_BITEND 21

#define HS_Standby__standby_mcu_reg__regr_pmu_off_irq_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_pmu_off_irq_BITSTART 29
#define HS_Standby__standby_mcu_reg__regr_pmu_off_irq_BITEND 29

#define HS_Standby__standby_mcu_reg__regr_adc0_irq_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_adc0_irq_BITSTART 30
#define HS_Standby__standby_mcu_reg__regr_adc0_irq_BITEND 30

#define HS_Standby__standby_mcu_reg__regr_adc1_irq_ADDR 0x110080F4
#define HS_Standby__standby_mcu_reg__regr_adc1_irq_BITSTART 31
#define HS_Standby__standby_mcu_reg__regr_adc1_irq_BITEND 31

#define HS_Standby__standby_mcu_reg__regr_dp0_cable_ADDR 0x110080F8
#define HS_Standby__standby_mcu_reg__regr_dp0_cable_BITSTART 0
#define HS_Standby__standby_mcu_reg__regr_dp0_cable_BITEND 0

#define HS_Standby__standby_mcu_reg__regr_dp1_cable_ADDR 0x110080F8
#define HS_Standby__standby_mcu_reg__regr_dp1_cable_BITSTART 1
#define HS_Standby__standby_mcu_reg__regr_dp1_cable_BITEND 1

#define HS_Standby__standby_mcu_reg__regr_hdmi0_cable_ADDR 0x110080F8
#define HS_Standby__standby_mcu_reg__regr_hdmi0_cable_BITSTART 2
#define HS_Standby__standby_mcu_reg__regr_hdmi0_cable_BITEND 2

#define HS_Standby__standby_mcu_reg__regr_hdmi1_cable_ADDR 0x110080F8
#define HS_Standby__standby_mcu_reg__regr_hdmi1_cable_BITSTART 3
#define HS_Standby__standby_mcu_reg__regr_hdmi1_cable_BITEND 3

#define HS_Standby__standby_mcu_reg__regr_gpio_in_ADDR 0x110080F8
#define HS_Standby__standby_mcu_reg__regr_gpio_in_BITSTART 4
#define HS_Standby__standby_mcu_reg__regr_gpio_in_BITEND 11

#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_drv_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_drv_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_drv_BITEND 3

#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_eng_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_eng_BITSTART 4
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_eng_BITEND 11

#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_hys_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_hys_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_hys_BITEND 13

#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_ie_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_ie_BITSTART 14
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_ie_BITEND 14

#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_pn_swap_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_pn_swap_BITSTART 15
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_pn_swap_BITEND 15

#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_pwd_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_pwd_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_pwd_BITEND 16

#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_res_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_res_BITSTART 17
#define HS_Standby__standby_peri_reg__reg_dprx0_ana_aux_res_BITEND 20

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_from_pin_ADDR 0x11008100
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_from_pin_BITSTART 21
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_from_pin_BITEND 22

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_actual_freq_th_ADDR 0x11008104
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_actual_freq_th_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_actual_freq_th_BITEND 3

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_corr_value_th_ADDR 0x11008104
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_corr_value_th_BITSTART 4
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_corr_value_th_BITEND 11

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_debug_clr_en_ADDR 0x11008104
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_debug_clr_en_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_debug_clr_en_BITEND 12

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_en_ADDR 0x11008104
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_en_BITSTART 13
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_en_BITEND 13

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_glitch_th_ADDR 0x11008104
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_glitch_th_BITSTART 14
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_glitch_th_BITEND 19

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_half_1us_thd_ADDR 0x11008104
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_half_1us_thd_BITSTART 20
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_half_1us_thd_BITEND 29

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_bypass_ADDR 0x11008104
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_bypass_BITSTART 30
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_bypass_BITEND 30

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_mask_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_mask_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_mask_BITEND 7

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_pat_sel_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_pat_sel_BITSTART 8
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_phase_sync_pat_sel_BITEND 9

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_pre_amble_num_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_pre_amble_num_BITSTART 10
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_pre_amble_num_BITEND 14

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_pre_charge_num_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_pre_charge_num_BITSTART 15
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_pre_charge_num_BITEND 19

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rdata_num_limit_en_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rdata_num_limit_en_BITSTART 20
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rdata_num_limit_en_BITEND 20

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rdback_clr_en_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rdback_clr_en_BITSTART 21
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rdback_clr_en_BITEND 21

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rx_inv_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rx_inv_BITSTART 22
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_rx_inv_BITEND 22

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_slp_sel_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_slp_sel_BITSTART 23
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_slp_sel_BITEND 24

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_start_patt1_en_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_start_patt1_en_BITSTART 25
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_start_patt1_en_BITEND 25

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_state_rst_en_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_state_rst_en_BITSTART 26
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_state_rst_en_BITEND 26

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_sw_sel_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_sw_sel_BITSTART 27
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_sw_sel_BITEND 28

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_time_out_clr_en_ADDR 0x11008108
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_time_out_clr_en_BITSTART 29
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_time_out_clr_en_BITEND 29

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_timeout_th_ADDR 0x1100810C
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_timeout_th_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_timeout_th_BITEND 15

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_dly_thro_ADDR 0x1100810C
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_dly_thro_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_dly_thro_BITEND 31

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_inv_ADDR 0x11008110
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_inv_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_inv_BITEND 0

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_phase_dly_en_ADDR 0x11008110
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_phase_dly_en_BITSTART 1
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_phase_dly_en_BITEND 1

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_precharge_on_ADDR 0x11008110
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_precharge_on_BITSTART 2
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_precharge_on_BITEND 2

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_wake_sel_ADDR 0x11008110
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_wake_sel_BITSTART 3
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_tx_wake_sel_BITEND 4

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_addr_ADDR 0x11008110
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_addr_BITSTART 5
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_addr_BITEND 24

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_sel_ADDR 0x11008114
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_sel_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_sel_BITEND 11

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_wdata_ADDR 0x11008114
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_wdata_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_wdata_BITEND 19

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_wr_ADDR 0x11008114
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_wr_BITSTART 20
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_wake_wr_BITEND 20

#define HS_Standby__standby_peri_reg__reg_dprx0_edid_addr0_ADDR 0x11008114
#define HS_Standby__standby_peri_reg__reg_dprx0_edid_addr0_BITSTART 21
#define HS_Standby__standby_peri_reg__reg_dprx0_edid_addr0_BITEND 28

#define HS_Standby__standby_peri_reg__reg_dprx0_edid_addr1_ADDR 0x11008118
#define HS_Standby__standby_peri_reg__reg_dprx0_edid_addr1_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx0_edid_addr1_BITEND 7

#define HS_Standby__standby_peri_reg__reg_dprx0_edid_seg_addr_ADDR 0x11008118
#define HS_Standby__standby_peri_reg__reg_dprx0_edid_seg_addr_BITSTART 8
#define HS_Standby__standby_peri_reg__reg_dprx0_edid_seg_addr_BITEND 15

#define HS_Standby__standby_peri_reg__reg_dprx0_aux_i2c_invalid_addr_en_ADDR 0x11008118
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_i2c_invalid_addr_en_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_dprx0_aux_i2c_invalid_addr_en_BITEND 16

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_addr_ADDR 0x1100811C
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_addr_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_addr_BITEND 19

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_commd_ADDR 0x1100811C
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_commd_BITSTART 20
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_commd_BITEND 23

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_dbg_cmd_cnt_ADDR 0x11008120
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_dbg_cmd_cnt_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_dbg_cmd_cnt_BITEND 15

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_freq_cnt_ADDR 0x11008120
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_freq_cnt_BITSTART 16
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_freq_cnt_BITEND 31

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_len_ADDR 0x11008124
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_len_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_len_BITEND 7

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_rx_time_out_ADDR 0x11008124
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_rx_time_out_BITSTART 8
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_rx_time_out_BITEND 8

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_state_ADDR 0x11008124
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_state_BITSTART 9
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_state_BITEND 12

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_100_wdata_ADDR 0x11008128
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_100_wdata_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_100_wdata_BITEND 7

#define HS_Standby__standby_peri_reg__regr_dprx0_aux_101_wdata_ADDR 0x11008128
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_101_wdata_BITSTART 8
#define HS_Standby__standby_peri_reg__regr_dprx0_aux_101_wdata_BITEND 15

#define HS_Standby__standby_peri_reg__reg_rx_standby_0p9_ADDR 0x11008140
#define HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITEND 3

#define HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_ADDR 0x11008140
#define HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_BITSTART 4
#define HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_BITEND 7

#define HS_Standby__standby_peri_reg__regr_rx_clk_flag_0p9_ADDR 0x11008140
#define HS_Standby__standby_peri_reg__regr_rx_clk_flag_0p9_BITSTART 8
#define HS_Standby__standby_peri_reg__regr_rx_clk_flag_0p9_BITEND 11

#define HS_Standby__standby_peri_reg__reg_rx_clk_mode_ADDR 0x11008140
#define HS_Standby__standby_peri_reg__reg_rx_clk_mode_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_rx_clk_mode_BITEND 15

#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_drv_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_drv_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_drv_BITEND 3

#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_eng_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_eng_BITSTART 4
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_eng_BITEND 11

#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_hys_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_hys_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_hys_BITEND 13

#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_ie_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_ie_BITSTART 14
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_ie_BITEND 14

#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_pn_swap_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_pn_swap_BITSTART 15
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_pn_swap_BITEND 15

#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_pwd_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_pwd_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_pwd_BITEND 16

#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_res_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_res_BITSTART 17
#define HS_Standby__standby_peri_reg__reg_dprx1_ana_aux_res_BITEND 20

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_from_pin_ADDR 0x11008150
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_from_pin_BITSTART 21
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_from_pin_BITEND 22

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_actual_freq_th_ADDR 0x11008154
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_actual_freq_th_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_actual_freq_th_BITEND 3

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_corr_value_th_ADDR 0x11008154
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_corr_value_th_BITSTART 4
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_corr_value_th_BITEND 11

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_debug_clr_en_ADDR 0x11008154
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_debug_clr_en_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_debug_clr_en_BITEND 12

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_en_ADDR 0x11008154
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_en_BITSTART 13
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_en_BITEND 13

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_glitch_th_ADDR 0x11008154
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_glitch_th_BITSTART 14
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_glitch_th_BITEND 19

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_half_1us_thd_ADDR 0x11008154
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_half_1us_thd_BITSTART 20
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_half_1us_thd_BITEND 29

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_bypass_ADDR 0x11008154
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_bypass_BITSTART 30
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_bypass_BITEND 30

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_mask_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_mask_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_mask_BITEND 7

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_pat_sel_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_pat_sel_BITSTART 8
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_phase_sync_pat_sel_BITEND 9

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_pre_amble_num_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_pre_amble_num_BITSTART 10
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_pre_amble_num_BITEND 14

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_pre_charge_num_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_pre_charge_num_BITSTART 15
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_pre_charge_num_BITEND 19

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rdata_num_limit_en_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rdata_num_limit_en_BITSTART 20
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rdata_num_limit_en_BITEND 20

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rdback_clr_en_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rdback_clr_en_BITSTART 21
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rdback_clr_en_BITEND 21

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rx_inv_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rx_inv_BITSTART 22
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_rx_inv_BITEND 22

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_slp_sel_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_slp_sel_BITSTART 23
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_slp_sel_BITEND 24

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_start_patt1_en_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_start_patt1_en_BITSTART 25
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_start_patt1_en_BITEND 25

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_state_rst_en_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_state_rst_en_BITSTART 26
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_state_rst_en_BITEND 26

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_sw_sel_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_sw_sel_BITSTART 27
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_sw_sel_BITEND 28

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_time_out_clr_en_ADDR 0x11008158
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_time_out_clr_en_BITSTART 29
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_time_out_clr_en_BITEND 29

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_timeout_th_ADDR 0x1100815C
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_timeout_th_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_timeout_th_BITEND 15

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_dly_thro_ADDR 0x1100815C
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_dly_thro_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_dly_thro_BITEND 31

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_inv_ADDR 0x11008160
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_inv_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_inv_BITEND 0

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_phase_dly_en_ADDR 0x11008160
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_phase_dly_en_BITSTART 1
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_phase_dly_en_BITEND 1

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_precharge_on_ADDR 0x11008160
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_precharge_on_BITSTART 2
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_precharge_on_BITEND 2

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_wake_sel_ADDR 0x11008160
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_wake_sel_BITSTART 3
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_tx_wake_sel_BITEND 4

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_addr_ADDR 0x11008160
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_addr_BITSTART 5
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_addr_BITEND 24

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_sel_ADDR 0x11008164
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_sel_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_sel_BITEND 11

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_wdata_ADDR 0x11008164
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_wdata_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_wdata_BITEND 19

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_wr_ADDR 0x11008164
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_wr_BITSTART 20
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_wake_wr_BITEND 20

#define HS_Standby__standby_peri_reg__reg_dprx1_edid_addr0_ADDR 0x11008164
#define HS_Standby__standby_peri_reg__reg_dprx1_edid_addr0_BITSTART 21
#define HS_Standby__standby_peri_reg__reg_dprx1_edid_addr0_BITEND 28

#define HS_Standby__standby_peri_reg__reg_dprx1_edid_addr1_ADDR 0x11008168
#define HS_Standby__standby_peri_reg__reg_dprx1_edid_addr1_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_dprx1_edid_addr1_BITEND 7

#define HS_Standby__standby_peri_reg__reg_dprx1_edid_seg_addr_ADDR 0x11008168
#define HS_Standby__standby_peri_reg__reg_dprx1_edid_seg_addr_BITSTART 8
#define HS_Standby__standby_peri_reg__reg_dprx1_edid_seg_addr_BITEND 15

#define HS_Standby__standby_peri_reg__reg_dprx1_aux_i2c_invalid_addr_en_ADDR 0x11008168
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_i2c_invalid_addr_en_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_dprx1_aux_i2c_invalid_addr_en_BITEND 16

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_addr_ADDR 0x1100816C
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_addr_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_addr_BITEND 19

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_commd_ADDR 0x1100816C
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_commd_BITSTART 20
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_commd_BITEND 23

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_dbg_cmd_cnt_ADDR 0x11008170
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_dbg_cmd_cnt_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_dbg_cmd_cnt_BITEND 15

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_freq_cnt_ADDR 0x11008170
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_freq_cnt_BITSTART 16
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_freq_cnt_BITEND 31

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_len_ADDR 0x11008174
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_len_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_len_BITEND 7

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_rx_time_out_ADDR 0x11008174
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_rx_time_out_BITSTART 8
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_rx_time_out_BITEND 8

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_state_ADDR 0x11008174
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_state_BITSTART 9
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_state_BITEND 12

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_100_wdata_ADDR 0x11008178
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_100_wdata_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_100_wdata_BITEND 7

#define HS_Standby__standby_peri_reg__regr_dprx1_aux_101_wdata_ADDR 0x11008178
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_101_wdata_BITSTART 8
#define HS_Standby__standby_peri_reg__regr_dprx1_aux_101_wdata_BITEND 15

#define HS_Standby__standby_peri_reg__reg_adc0_en_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_en_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_adc0_en_BITEND 0

#define HS_Standby__standby_peri_reg__reg_adc0_pd_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_pd_BITSTART 1
#define HS_Standby__standby_peri_reg__reg_adc0_pd_BITEND 1

#define HS_Standby__standby_peri_reg__reg_adc0_puls_mod_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_puls_mod_BITSTART 2
#define HS_Standby__standby_peri_reg__reg_adc0_puls_mod_BITEND 2

#define HS_Standby__standby_peri_reg__reg_adc0_bridge_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_bridge_BITSTART 3
#define HS_Standby__standby_peri_reg__reg_adc0_bridge_BITEND 6

#define HS_Standby__standby_peri_reg__reg_adc0_ib_comp_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_ib_comp_BITSTART 7
#define HS_Standby__standby_peri_reg__reg_adc0_ib_comp_BITEND 8

#define HS_Standby__standby_peri_reg__reg_adc0_odmode_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_odmode_BITSTART 9
#define HS_Standby__standby_peri_reg__reg_adc0_odmode_BITEND 9

#define HS_Standby__standby_peri_reg__reg_adc0_clk_div_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_clk_div_BITSTART 10
#define HS_Standby__standby_peri_reg__reg_adc0_clk_div_BITEND 11

#define HS_Standby__standby_peri_reg__reg_adc0_vref_sel_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc0_vref_sel_BITSTART 12
#define HS_Standby__standby_peri_reg__reg_adc0_vref_sel_BITEND 15

#define HS_Standby__standby_peri_reg__reg_adc1_en_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_en_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_adc1_en_BITEND 16

#define HS_Standby__standby_peri_reg__reg_adc1_pd_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_pd_BITSTART 17
#define HS_Standby__standby_peri_reg__reg_adc1_pd_BITEND 17

#define HS_Standby__standby_peri_reg__reg_adc1_puls_mod_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_puls_mod_BITSTART 18
#define HS_Standby__standby_peri_reg__reg_adc1_puls_mod_BITEND 18

#define HS_Standby__standby_peri_reg__reg_adc1_bridge_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_bridge_BITSTART 19
#define HS_Standby__standby_peri_reg__reg_adc1_bridge_BITEND 22

#define HS_Standby__standby_peri_reg__reg_adc1_ib_comp_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_ib_comp_BITSTART 23
#define HS_Standby__standby_peri_reg__reg_adc1_ib_comp_BITEND 24

#define HS_Standby__standby_peri_reg__reg_adc1_odmode_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_odmode_BITSTART 25
#define HS_Standby__standby_peri_reg__reg_adc1_odmode_BITEND 25

#define HS_Standby__standby_peri_reg__reg_adc1_clk_div_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_clk_div_BITSTART 26
#define HS_Standby__standby_peri_reg__reg_adc1_clk_div_BITEND 27

#define HS_Standby__standby_peri_reg__reg_adc1_vref_sel_ADDR 0x11008180
#define HS_Standby__standby_peri_reg__reg_adc1_vref_sel_BITSTART 28
#define HS_Standby__standby_peri_reg__reg_adc1_vref_sel_BITEND 31

#define HS_Standby__standby_peri_reg__reg_adc0_lth_ADDR 0x11008184
#define HS_Standby__standby_peri_reg__reg_adc0_lth_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_adc0_lth_BITEND 11

#define HS_Standby__standby_peri_reg__reg_adc0_hth_ADDR 0x11008184
#define HS_Standby__standby_peri_reg__reg_adc0_hth_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_adc0_hth_BITEND 27

#define HS_Standby__standby_peri_reg__reg_adc1_lth_ADDR 0x11008188
#define HS_Standby__standby_peri_reg__reg_adc1_lth_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_adc1_lth_BITEND 11

#define HS_Standby__standby_peri_reg__reg_adc1_hth_ADDR 0x11008188
#define HS_Standby__standby_peri_reg__reg_adc1_hth_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_adc1_hth_BITEND 27

#define HS_Standby__standby_peri_reg__regr_adc0_data_ADDR 0x1100818C
#define HS_Standby__standby_peri_reg__regr_adc0_data_BITSTART 0
#define HS_Standby__standby_peri_reg__regr_adc0_data_BITEND 11

#define HS_Standby__standby_peri_reg__regr_adc1_data_ADDR 0x1100818C
#define HS_Standby__standby_peri_reg__regr_adc1_data_BITSTART 16
#define HS_Standby__standby_peri_reg__regr_adc1_data_BITEND 27

#define HS_Standby__standby_peri_reg__reg_gpio_o_ADDR 0x11008190
#define HS_Standby__standby_peri_reg__reg_gpio_o_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gpio_o_BITEND 7

#define HS_Standby__standby_peri_reg__reg_gpio_oe_ADDR 0x11008190
#define HS_Standby__standby_peri_reg__reg_gpio_oe_BITSTART 8
#define HS_Standby__standby_peri_reg__reg_gpio_oe_BITEND 15

#define HS_Standby__standby_peri_reg__regr_gpio_i_ADDR 0x11008190
#define HS_Standby__standby_peri_reg__regr_gpio_i_BITSTART 16
#define HS_Standby__standby_peri_reg__regr_gpio_i_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gpio_pol_ADDR 0x11008190
#define HS_Standby__standby_peri_reg__reg_gpio_pol_BITSTART 24
#define HS_Standby__standby_peri_reg__reg_gpio_pol_BITEND 31

#define HS_Standby__standby_peri_reg__reg_gp0_filter_num_ADDR 0x11008194
#define HS_Standby__standby_peri_reg__reg_gp0_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp0_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gp1_filter_num_ADDR 0x11008198
#define HS_Standby__standby_peri_reg__reg_gp1_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp1_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gp2_filter_num_ADDR 0x1100819C
#define HS_Standby__standby_peri_reg__reg_gp2_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp2_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gp3_filter_num_ADDR 0x110081A0
#define HS_Standby__standby_peri_reg__reg_gp3_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp3_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gp4_filter_num_ADDR 0x110081A4
#define HS_Standby__standby_peri_reg__reg_gp4_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp4_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gp5_filter_num_ADDR 0x110081A8
#define HS_Standby__standby_peri_reg__reg_gp5_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp5_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gp6_filter_num_ADDR 0x110081AC
#define HS_Standby__standby_peri_reg__reg_gp6_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp6_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_gp7_filter_num_ADDR 0x110081B0
#define HS_Standby__standby_peri_reg__reg_gp7_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_gp7_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_adc0_filter_num_ADDR 0x110081B4
#define HS_Standby__standby_peri_reg__reg_adc0_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_adc0_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_adc1_filter_num_ADDR 0x110081B8
#define HS_Standby__standby_peri_reg__reg_adc1_filter_num_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_adc1_filter_num_BITEND 23

#define HS_Standby__standby_peri_reg__reg_pwm_ch_en_ADDR 0x110081C0
#define HS_Standby__standby_peri_reg__reg_pwm_ch_en_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_pwm_ch_en_BITEND 0

#define HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_ADDR 0x110081C0
#define HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_BITSTART 1
#define HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_BITEND 1

#define HS_Standby__standby_peri_reg__reg_pwm_output_mode_ADDR 0x110081C0
#define HS_Standby__standby_peri_reg__reg_pwm_output_mode_BITSTART 2
#define HS_Standby__standby_peri_reg__reg_pwm_output_mode_BITEND 2

#define HS_Standby__standby_peri_reg__reg_pwm_pol_ADDR 0x110081C0
#define HS_Standby__standby_peri_reg__reg_pwm_pol_BITSTART 3
#define HS_Standby__standby_peri_reg__reg_pwm_pol_BITEND 3

#define HS_Standby__standby_peri_reg__reg_pwm_prescaler_ADDR 0x110081C0
#define HS_Standby__standby_peri_reg__reg_pwm_prescaler_BITSTART 4
#define HS_Standby__standby_peri_reg__reg_pwm_prescaler_BITEND 7

#define HS_Standby__standby_peri_reg__reg_pwm_counter_top_ADDR 0x110081C0
#define HS_Standby__standby_peri_reg__reg_pwm_counter_top_BITSTART 8
#define HS_Standby__standby_peri_reg__reg_pwm_counter_top_BITEND 23

#define HS_Standby__standby_peri_reg__reg_pwm_cmp_start_val_ADDR 0x110081C4
#define HS_Standby__standby_peri_reg__reg_pwm_cmp_start_val_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_pwm_cmp_start_val_BITEND 15

#define HS_Standby__standby_peri_reg__reg_pwm_cmp_end_val_ADDR 0x110081C4
#define HS_Standby__standby_peri_reg__reg_pwm_cmp_end_val_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_pwm_cmp_end_val_BITEND 31

#define HS_Standby__standby_peri_reg__reg_pwm_cmp_step_val_ADDR 0x110081C8
#define HS_Standby__standby_peri_reg__reg_pwm_cmp_step_val_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_pwm_cmp_step_val_BITEND 15

#define HS_Standby__standby_peri_reg__reg_pwm_cycle_num_ADDR 0x110081C8
#define HS_Standby__standby_peri_reg__reg_pwm_cycle_num_BITSTART 16
#define HS_Standby__standby_peri_reg__reg_pwm_cycle_num_BITEND 31

#define HS_Standby__standby_peri_reg__reg_pwm_rep_ADDR 0x110081CC
#define HS_Standby__standby_peri_reg__reg_pwm_rep_BITSTART 0
#define HS_Standby__standby_peri_reg__reg_pwm_rep_BITEND 15

#define HS_Standby__standby_peri_reg__regr_pwm_cnt_val_ADDR 0x110081CC
#define HS_Standby__standby_peri_reg__regr_pwm_cnt_val_BITSTART 16
#define HS_Standby__standby_peri_reg__regr_pwm_cnt_val_BITEND 31

#define HS_Standby__AON_REG__reg_bg_pd_bias_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_pd_bias_BITSTART 0
#define HS_Standby__AON_REG__reg_bg_pd_bias_BITEND 0

#define HS_Standby__AON_REG__reg_bg_bias_trim_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_bias_trim_BITSTART 1
#define HS_Standby__AON_REG__reg_bg_bias_trim_BITEND 3

#define HS_Standby__AON_REG__reg_bg_vbg_test_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_vbg_test_BITSTART 4
#define HS_Standby__AON_REG__reg_bg_vbg_test_BITEND 4

#define HS_Standby__AON_REG__reg_bg_eng_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_eng_BITSTART 5
#define HS_Standby__AON_REG__reg_bg_eng_BITEND 12

#define HS_Standby__AON_REG__reg_bg_rext_rint_sel_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_rext_rint_sel_BITSTART 13
#define HS_Standby__AON_REG__reg_bg_rext_rint_sel_BITEND 13

#define HS_Standby__AON_REG__reg_bg_rint_adj_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_rint_adj_BITSTART 14
#define HS_Standby__AON_REG__reg_bg_rint_adj_BITEND 17

#define HS_Standby__AON_REG__reg_bg_res_mesure_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_res_mesure_BITSTART 18
#define HS_Standby__AON_REG__reg_bg_res_mesure_BITEND 21

#define HS_Standby__AON_REG__reg_bg_test_sel_ADDR 0x11008200
#define HS_Standby__AON_REG__reg_bg_test_sel_BITSTART 22
#define HS_Standby__AON_REG__reg_bg_test_sel_BITEND 24

#define HS_Standby__AON_REG__regr_bg_comp_flag_ADDR 0x11008200
#define HS_Standby__AON_REG__regr_bg_comp_flag_BITSTART 25
#define HS_Standby__AON_REG__regr_bg_comp_flag_BITEND 25

#define HS_Standby__AON_REG__reg_osc_keep_ADDR 0x11008204
#define HS_Standby__AON_REG__reg_osc_keep_BITSTART 0
#define HS_Standby__AON_REG__reg_osc_keep_BITEND 3

#define HS_Standby__AON_REG__reg_osc_adj_gain_ADDR 0x11008204
#define HS_Standby__AON_REG__reg_osc_adj_gain_BITSTART 4
#define HS_Standby__AON_REG__reg_osc_adj_gain_BITEND 6

#define HS_Standby__AON_REG__reg_osc_pd_ADDR 0x11008204
#define HS_Standby__AON_REG__reg_osc_pd_BITSTART 7
#define HS_Standby__AON_REG__reg_osc_pd_BITEND 7

#define HS_Standby__AON_REG__reg_ldo_ref_adj_ADDR 0x11008208
#define HS_Standby__AON_REG__reg_ldo_ref_adj_BITSTART 0
#define HS_Standby__AON_REG__reg_ldo_ref_adj_BITEND 2

#define HS_Standby__AON_REG__reg_ldo_ref_sel_ADDR 0x11008208
#define HS_Standby__AON_REG__reg_ldo_ref_sel_BITSTART 3
#define HS_Standby__AON_REG__reg_ldo_ref_sel_BITEND 3

#define HS_Standby__AON_REG__reg_ldo_bias_adj_ADDR 0x11008208
#define HS_Standby__AON_REG__reg_ldo_bias_adj_BITSTART 4
#define HS_Standby__AON_REG__reg_ldo_bias_adj_BITEND 6

#define HS_Standby__AON_REG__reg_ldo_eng_ADDR 0x11008208
#define HS_Standby__AON_REG__reg_ldo_eng_BITSTART 7
#define HS_Standby__AON_REG__reg_ldo_eng_BITEND 11

#define HS_Standby__AON_REG__reg_ldo1p8_ref_adj_ADDR 0x11008208
#define HS_Standby__AON_REG__reg_ldo1p8_ref_adj_BITSTART 12
#define HS_Standby__AON_REG__reg_ldo1p8_ref_adj_BITEND 14

#define HS_Standby__AON_REG__reg_ldo1p8_soft_start_enb_ADDR 0x11008208
#define HS_Standby__AON_REG__reg_ldo1p8_soft_start_enb_BITSTART 15
#define HS_Standby__AON_REG__reg_ldo1p8_soft_start_enb_BITEND 15

#define HS_Standby__AON_REG__reg_ldo1p8_eng_ADDR 0x11008208
#define HS_Standby__AON_REG__reg_ldo1p8_eng_BITSTART 16
#define HS_Standby__AON_REG__reg_ldo1p8_eng_BITEND 20

#define HS_Standby__AON_REG__regr_ldo1p8_rdy_ADDR 0x11008208
#define HS_Standby__AON_REG__regr_ldo1p8_rdy_BITSTART 21
#define HS_Standby__AON_REG__regr_ldo1p8_rdy_BITEND 21

#define HS_Standby__AON_REG__reg_ana_scan_setting_en_ADDR 0x1100820C
#define HS_Standby__AON_REG__reg_ana_scan_setting_en_BITSTART 0
#define HS_Standby__AON_REG__reg_ana_scan_setting_en_BITEND 0

#define HS_Standby__AON_REG__reg_osc_div_clk_num_ADDR 0x1100820C
#define HS_Standby__AON_REG__reg_osc_div_clk_num_BITSTART 1
#define HS_Standby__AON_REG__reg_osc_div_clk_num_BITEND 3

#define HS_Standby__AON_REG__reg_src_clk_en_ADDR 0x1100820C
#define HS_Standby__AON_REG__reg_src_clk_en_BITSTART 4
#define HS_Standby__AON_REG__reg_src_clk_en_BITEND 4

#define HS_Standby__AON_REG__reg_sw_rst_n_ADDR 0x1100820C
#define HS_Standby__AON_REG__reg_sw_rst_n_BITSTART 5
#define HS_Standby__AON_REG__reg_sw_rst_n_BITEND 5

#define HS_Standby__AON_REG__reg_pmu_pon_ini_cnt_val_ADDR 0x11008210
#define HS_Standby__AON_REG__reg_pmu_pon_ini_cnt_val_BITSTART 0
#define HS_Standby__AON_REG__reg_pmu_pon_ini_cnt_val_BITEND 15

#define HS_Standby__AON_REG__reg_pmu_pon_ini_cnt_div_ADDR 0x11008210
#define HS_Standby__AON_REG__reg_pmu_pon_ini_cnt_div_BITSTART 16
#define HS_Standby__AON_REG__reg_pmu_pon_ini_cnt_div_BITEND 23

#define HS_Standby__AON_REG__reg_pmu_psw_cnt_val_ADDR 0x11008210
#define HS_Standby__AON_REG__reg_pmu_psw_cnt_val_BITSTART 24
#define HS_Standby__AON_REG__reg_pmu_psw_cnt_val_BITEND 31

#define HS_Standby__AON_REG__reg_pmu_iso_cnt_val_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_iso_cnt_val_BITSTART 0
#define HS_Standby__AON_REG__reg_pmu_iso_cnt_val_BITEND 7

#define HS_Standby__AON_REG__reg_pmu_rst_cnt_val_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_rst_cnt_val_BITSTART 8
#define HS_Standby__AON_REG__reg_pmu_rst_cnt_val_BITEND 15

#define HS_Standby__AON_REG__reg_pmu_mcu_off_req_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_mcu_off_req_BITSTART 16
#define HS_Standby__AON_REG__reg_pmu_mcu_off_req_BITEND 16

#define HS_Standby__AON_REG__reg_pmu_psw_stby_men_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_psw_stby_men_BITSTART 17
#define HS_Standby__AON_REG__reg_pmu_psw_stby_men_BITEND 17

#define HS_Standby__AON_REG__reg_pmu_psw_stby_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_psw_stby_BITSTART 18
#define HS_Standby__AON_REG__reg_pmu_psw_stby_BITEND 18

#define HS_Standby__AON_REG__reg_pmu_aon_iso_men_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_aon_iso_men_BITSTART 19
#define HS_Standby__AON_REG__reg_pmu_aon_iso_men_BITEND 19

#define HS_Standby__AON_REG__reg_pmu_aon_iso_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_aon_iso_BITSTART 20
#define HS_Standby__AON_REG__reg_pmu_aon_iso_BITEND 20

#define HS_Standby__AON_REG__reg_pmu_fsm_clr_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_fsm_clr_BITSTART 21
#define HS_Standby__AON_REG__reg_pmu_fsm_clr_BITEND 21

#define HS_Standby__AON_REG__reg_pmu_reg_en_ADDR 0x11008214
#define HS_Standby__AON_REG__reg_pmu_reg_en_BITSTART 22
#define HS_Standby__AON_REG__reg_pmu_reg_en_BITEND 22

#define HS_Standby__AON_REG__reg_pmu_pk_filter_num_ADDR 0x11008218
#define HS_Standby__AON_REG__reg_pmu_pk_filter_num_BITSTART 0
#define HS_Standby__AON_REG__reg_pmu_pk_filter_num_BITEND 23

#define HS_Standby__AON_REG__reg_pmu_pk_pol_ADDR 0x11008218
#define HS_Standby__AON_REG__reg_pmu_pk_pol_BITSTART 24
#define HS_Standby__AON_REG__reg_pmu_pk_pol_BITEND 24

#define HS_Standby__AON_REG__reg_first_start_flag_ADDR 0x1100821C
#define HS_Standby__AON_REG__reg_first_start_flag_BITSTART 0
#define HS_Standby__AON_REG__reg_first_start_flag_BITEND 0

#define HS_Standby__AON_REG__reg_ver_sel_ADDR 0x1100821C
#define HS_Standby__AON_REG__reg_ver_sel_BITSTART 1
#define HS_Standby__AON_REG__reg_ver_sel_BITEND 1

#define HS_Standby__AON_REG__reg_pmu_pwr_off_state_ADDR 0x1100821C
#define HS_Standby__AON_REG__reg_pmu_pwr_off_state_BITSTART 2
#define HS_Standby__AON_REG__reg_pmu_pwr_off_state_BITEND 2

#define HS_Standby__AON_REG__regr_pmu_current_state_ADDR 0x11008230
#define HS_Standby__AON_REG__regr_pmu_current_state_BITSTART 0
#define HS_Standby__AON_REG__regr_pmu_current_state_BITEND 31

#define HS_Standby__AON_REG__regr_stb_pwr_on_ADDR 0x11008234
#define HS_Standby__AON_REG__regr_stb_pwr_on_BITSTART 0
#define HS_Standby__AON_REG__regr_stb_pwr_on_BITEND 0

#define HS_Standby__AON_REG__regr_aon_iso_ADDR 0x11008234
#define HS_Standby__AON_REG__regr_aon_iso_BITSTART 1
#define HS_Standby__AON_REG__regr_aon_iso_BITEND 1

#define HS_Standby__AON_REG__reg_ate_sel_ADDR 0x11008240
#define HS_Standby__AON_REG__reg_ate_sel_BITSTART 0
#define HS_Standby__AON_REG__reg_ate_sel_BITEND 1

#define HS_Standby__AON_REG__reg_keep_ADDR 0x11008244
#define HS_Standby__AON_REG__reg_keep_BITSTART 8
#define HS_Standby__AON_REG__reg_keep_BITEND 11

#define HS_Standby__AON_REG__reg_pw_aon_ADDR 0x11008248
#define HS_Standby__AON_REG__reg_pw_aon_BITSTART 0
#define HS_Standby__AON_REG__reg_pw_aon_BITEND 0

#define HS_Standby__AON_REG__reg_pw_stb_ADDR 0x11008248
#define HS_Standby__AON_REG__reg_pw_stb_BITSTART 1
#define HS_Standby__AON_REG__reg_pw_stb_BITEND 1

#define HS_Standby__AON_REG__reg_xram_mem_power_en_ADDR 0x1100824C
#define HS_Standby__AON_REG__reg_xram_mem_power_en_BITSTART 0
#define HS_Standby__AON_REG__reg_xram_mem_power_en_BITEND 0

#define HS_Standby__AON_REG__reg_aon_xram_mem_sleep_en_ADDR 0x1100824C
#define HS_Standby__AON_REG__reg_aon_xram_mem_sleep_en_BITSTART 1
#define HS_Standby__AON_REG__reg_aon_xram_mem_sleep_en_BITEND 1

#define HS_Standby__AON_REG__regr_pwr_ctrl_dis_di_ADDR 0x11008250
#define HS_Standby__AON_REG__regr_pwr_ctrl_dis_di_BITSTART 0
#define HS_Standby__AON_REG__regr_pwr_ctrl_dis_di_BITEND 0

#define HS_Standby__AON_REG__regr_pwr_key_di_ADDR 0x11008250
#define HS_Standby__AON_REG__regr_pwr_key_di_BITSTART 1
#define HS_Standby__AON_REG__regr_pwr_key_di_BITEND 1

#define HS_Standby__AON_REG__regr_pwr_state_di_ADDR 0x11008250
#define HS_Standby__AON_REG__regr_pwr_state_di_BITSTART 2
#define HS_Standby__AON_REG__regr_pwr_state_di_BITEND 2

#define HS_Standby__AON_REG__regr_rstn_di_ADDR 0x11008250
#define HS_Standby__AON_REG__regr_rstn_di_BITSTART 3
#define HS_Standby__AON_REG__regr_rstn_di_BITEND 3

#define HS_Standby__AON_REG__regr_pwr_on_di_ADDR 0x11008250
#define HS_Standby__AON_REG__regr_pwr_on_di_BITSTART 4
#define HS_Standby__AON_REG__regr_pwr_on_di_BITEND 4

#define HS_Standby__AON_REG__regr_test_di_ADDR 0x11008250
#define HS_Standby__AON_REG__regr_test_di_BITSTART 5
#define HS_Standby__AON_REG__regr_test_di_BITEND 5

#define HS_Standby__standby_comm_reg__sw0_intr_set_ADDR 0x11008300
#define HS_Standby__standby_comm_reg__sw0_intr_set_BITSTART 0
#define HS_Standby__standby_comm_reg__sw0_intr_set_BITEND 31

#define HS_Standby__standby_comm_reg__sw0_intr_clr_ADDR 0x11008304
#define HS_Standby__standby_comm_reg__sw0_intr_clr_BITSTART 0
#define HS_Standby__standby_comm_reg__sw0_intr_clr_BITEND 31

#define HS_Standby__standby_comm_reg__sw0_intr_sts_ADDR 0x11008308
#define HS_Standby__standby_comm_reg__sw0_intr_sts_BITSTART 0
#define HS_Standby__standby_comm_reg__sw0_intr_sts_BITEND 31

#define HS_Standby__standby_comm_reg__sw1_intr_set_ADDR 0x11008310
#define HS_Standby__standby_comm_reg__sw1_intr_set_BITSTART 0
#define HS_Standby__standby_comm_reg__sw1_intr_set_BITEND 31

#define HS_Standby__standby_comm_reg__sw1_intr_clr_ADDR 0x11008314
#define HS_Standby__standby_comm_reg__sw1_intr_clr_BITSTART 0
#define HS_Standby__standby_comm_reg__sw1_intr_clr_BITEND 31

#define HS_Standby__standby_comm_reg__sw1_intr_sts_ADDR 0x11008318
#define HS_Standby__standby_comm_reg__sw1_intr_sts_BITSTART 0
#define HS_Standby__standby_comm_reg__sw1_intr_sts_BITEND 31

#define HS_Standby__standby_comm_reg__rclr_spinlock00_ADDR 0x11008340
#define HS_Standby__standby_comm_reg__rclr_spinlock00_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock00_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock01_ADDR 0x11008344
#define HS_Standby__standby_comm_reg__rclr_spinlock01_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock01_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock02_ADDR 0x11008348
#define HS_Standby__standby_comm_reg__rclr_spinlock02_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock02_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock03_ADDR 0x1100834C
#define HS_Standby__standby_comm_reg__rclr_spinlock03_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock03_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock04_ADDR 0x11008350
#define HS_Standby__standby_comm_reg__rclr_spinlock04_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock04_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock05_ADDR 0x11008354
#define HS_Standby__standby_comm_reg__rclr_spinlock05_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock05_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock06_ADDR 0x11008358
#define HS_Standby__standby_comm_reg__rclr_spinlock06_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock06_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock07_ADDR 0x1100835C
#define HS_Standby__standby_comm_reg__rclr_spinlock07_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock07_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock08_ADDR 0x11008360
#define HS_Standby__standby_comm_reg__rclr_spinlock08_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock08_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock09_ADDR 0x11008364
#define HS_Standby__standby_comm_reg__rclr_spinlock09_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock09_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock10_ADDR 0x11008368
#define HS_Standby__standby_comm_reg__rclr_spinlock10_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock10_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock11_ADDR 0x1100836C
#define HS_Standby__standby_comm_reg__rclr_spinlock11_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock11_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock12_ADDR 0x11008370
#define HS_Standby__standby_comm_reg__rclr_spinlock12_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock12_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock13_ADDR 0x11008374
#define HS_Standby__standby_comm_reg__rclr_spinlock13_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock13_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock14_ADDR 0x11008378
#define HS_Standby__standby_comm_reg__rclr_spinlock14_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock14_BITEND 0

#define HS_Standby__standby_comm_reg__rclr_spinlock15_ADDR 0x1100837C
#define HS_Standby__standby_comm_reg__rclr_spinlock15_BITSTART 0
#define HS_Standby__standby_comm_reg__rclr_spinlock15_BITEND 0

#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_scl_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_scl_func_sel_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_scl_func_sel_BITEND 0

#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_sda_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_sda_func_sel_BITSTART 1
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_sda_func_sel_BITEND 1

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_cable_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_cable_func_sel_BITSTART 2
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_cable_func_sel_BITEND 2

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_hpd_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_hpd_func_sel_BITSTART 3
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_hpd_func_sel_BITEND 3

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_cable_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_cable_func_sel_BITSTART 4
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_cable_func_sel_BITEND 4

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp5_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp5_func_sel_BITSTART 5
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp5_func_sel_BITEND 5

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cable_det_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cable_det_func_sel_BITSTART 6
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cable_det_func_sel_BITEND 6

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_func_sel_BITSTART 7
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_func_sel_BITEND 8

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_func_sel_BITSTART 9
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_func_sel_BITEND 9

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cable_det_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cable_det_func_sel_BITSTART 10
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cable_det_func_sel_BITEND 10

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_func_sel_BITSTART 11
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_func_sel_BITEND 12

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_func_sel_BITSTART 13
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_func_sel_BITEND 13

#define HS_Standby__SH08_TOP_STBY__reg_mi2c_scl_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_scl_func_sel_BITSTART 14
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_scl_func_sel_BITEND 14

#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_func_sel_BITSTART 15
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_func_sel_BITEND 15

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_clk_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_clk_func_sel_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_clk_func_sel_BITEND 16

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_csn_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_csn_func_sel_BITSTART 17
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_csn_func_sel_BITEND 17

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_hold_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_hold_func_sel_BITSTART 18
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_hold_func_sel_BITEND 18

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_miso_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_miso_func_sel_BITSTART 19
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_miso_func_sel_BITEND 19

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_mosi_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_mosi_func_sel_BITSTART 20
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_mosi_func_sel_BITEND 20

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_wp_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_wp_func_sel_BITSTART 21
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_wp_func_sel_BITEND 21

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp0_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp0_func_sel_BITSTART 22
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp0_func_sel_BITEND 22

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp1_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp1_func_sel_BITSTART 23
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp1_func_sel_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp2_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp2_func_sel_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp2_func_sel_BITEND 24

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp3_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp3_func_sel_BITSTART 25
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp3_func_sel_BITEND 26

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp4_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp4_func_sel_BITSTART 27
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp4_func_sel_BITEND 27

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_BITSTART 28
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_BITEND 29

#define HS_Standby__SH08_TOP_STBY__reg_aux_dprx0_gpio_in_in_sel_ADDR 0x11008400
#define HS_Standby__SH08_TOP_STBY__reg_aux_dprx0_gpio_in_in_sel_BITSTART 30
#define HS_Standby__SH08_TOP_STBY__reg_aux_dprx0_gpio_in_in_sel_BITEND 31

#define HS_Standby__SH08_TOP_STBY__reg_dp0_cable_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_dp0_cable_in_sel_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_dp0_cable_in_sel_BITEND 1

#define HS_Standby__SH08_TOP_STBY__reg_dp1_cable_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_dp1_cable_in_sel_BITSTART 2
#define HS_Standby__SH08_TOP_STBY__reg_dp1_cable_in_sel_BITEND 3

#define HS_Standby__SH08_TOP_STBY__reg_hdmi0_rx_cable_det_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi0_rx_cable_det_in_sel_BITSTART 4
#define HS_Standby__SH08_TOP_STBY__reg_hdmi0_rx_cable_det_in_sel_BITEND 5

#define HS_Standby__SH08_TOP_STBY__reg_hdmi1_rx_cable_det_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi1_rx_cable_det_in_sel_BITSTART 6
#define HS_Standby__SH08_TOP_STBY__reg_hdmi1_rx_cable_det_in_sel_BITEND 7

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_in_in_sel_BITSTART 8
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_in_in_sel_BITEND 9

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_in_in_sel_BITSTART 10
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_in_in_sel_BITEND 11

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_in_in_sel_BITSTART 12
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_in_in_sel_BITEND 13

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_in_in_sel_BITSTART 14
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_in_in_sel_BITEND 15

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_in_in_sel_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_in_in_sel_BITEND 17

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_in_in_sel_BITSTART 18
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_in_in_sel_BITEND 19

#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_in_in_sel_BITSTART 20
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_in_in_sel_BITEND 21

#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_BITSTART 22
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_uart_rxd_i_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_uart_rxd_i_in_sel_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_uart_rxd_i_in_sel_BITEND 25

#define HS_Standby__SH08_TOP_STBY__reg_aux_dprx1_gpio_in_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_aux_dprx1_gpio_in_in_sel_BITSTART 26
#define HS_Standby__SH08_TOP_STBY__reg_aux_dprx1_gpio_in_in_sel_BITEND 27

#define HS_Standby__SH08_TOP_STBY__reg_uart0_sin_in_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_uart0_sin_in_sel_BITSTART 28
#define HS_Standby__SH08_TOP_STBY__reg_uart0_sin_in_sel_BITEND 29

#define HS_Standby__SH08_TOP_STBY__reg_other_pin_sel_ADDR 0x11008404
#define HS_Standby__SH08_TOP_STBY__reg_other_pin_sel_BITSTART 30
#define HS_Standby__SH08_TOP_STBY__reg_other_pin_sel_BITEND 31

#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_scl_io_ctrl_ADDR 0x11008408
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_scl_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_scl_io_ctrl_BITEND 7

#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_sda_io_ctrl_ADDR 0x11008408
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_sda_io_ctrl_BITSTART 8
#define HS_Standby__SH08_TOP_STBY__reg_dbgi2c_sda_io_ctrl_BITEND 15

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_cable_io_ctrl_ADDR 0x11008408
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_cable_io_ctrl_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_cable_io_ctrl_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_hpd_io_ctrl_ADDR 0x11008408
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_hpd_io_ctrl_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx0_hpd_io_ctrl_BITEND 31

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_cable_io_ctrl_ADDR 0x1100840C
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_cable_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_cable_io_ctrl_BITEND 7

#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_ADDR 0x1100840C
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_BITSTART 8
#define HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_BITEND 15

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cable_det_io_ctrl_ADDR 0x1100840C
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cable_det_io_ctrl_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cable_det_io_ctrl_BITEND 20

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_io_ctrl_ADDR 0x1100840C
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_io_ctrl_BITSTART 21
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_io_ctrl_BITEND 25

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_io_ctrl_ADDR 0x11008410
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc0_io_ctrl_BITEND 4

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_io_ctrl_ADDR 0x11008410
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_io_ctrl_BITSTART 5
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_io_ctrl_BITEND 9

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cable_det_io_ctrl_ADDR 0x11008410
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cable_det_io_ctrl_BITSTART 10
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cable_det_io_ctrl_BITEND 14

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_io_ctrl_ADDR 0x11008410
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_io_ctrl_BITSTART 15
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_io_ctrl_BITEND 19

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_io_ctrl_ADDR 0x11008414
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc0_io_ctrl_BITEND 4

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_io_ctrl_ADDR 0x11008414
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_io_ctrl_BITSTART 5
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_io_ctrl_BITEND 9

#define HS_Standby__SH08_TOP_STBY__reg_mi2c_scl_io_ctrl_ADDR 0x11008414
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_scl_io_ctrl_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_scl_io_ctrl_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_io_ctrl_ADDR 0x11008414
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_io_ctrl_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_mi2c_sda_io_ctrl_BITEND 31

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_clk_io_ctrl_ADDR 0x11008418
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_clk_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_clk_io_ctrl_BITEND 7

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_csn_io_ctrl_ADDR 0x11008418
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_csn_io_ctrl_BITSTART 8
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_csn_io_ctrl_BITEND 15

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_hold_io_ctrl_ADDR 0x11008418
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_hold_io_ctrl_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_hold_io_ctrl_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_miso_io_ctrl_ADDR 0x11008418
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_miso_io_ctrl_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_miso_io_ctrl_BITEND 31

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_mosi_io_ctrl_ADDR 0x1100841C
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_mosi_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_mosi_io_ctrl_BITEND 7

#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_wp_io_ctrl_ADDR 0x1100841C
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_wp_io_ctrl_BITSTART 8
#define HS_Standby__SH08_TOP_STBY__reg_prog_spi_wp_io_ctrl_BITEND 15

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp0_io_ctrl_ADDR 0x1100841C
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp0_io_ctrl_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp0_io_ctrl_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp1_io_ctrl_ADDR 0x1100841C
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp1_io_ctrl_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp1_io_ctrl_BITEND 28

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp2_io_ctrl_ADDR 0x11008420
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp2_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp2_io_ctrl_BITEND 4

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp3_io_ctrl_ADDR 0x11008420
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp3_io_ctrl_BITSTART 5
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp3_io_ctrl_BITEND 9

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp4_io_ctrl_ADDR 0x11008420
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp4_io_ctrl_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp4_io_ctrl_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp5_io_ctrl_ADDR 0x11008420
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp5_io_ctrl_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp5_io_ctrl_BITEND 31

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp6_io_ctrl_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp6_io_ctrl_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp6_io_ctrl_BITEND 4

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp7_io_ctrl_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp7_io_ctrl_BITSTART 5
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp7_io_ctrl_BITEND 9

#define HS_Standby__SH08_TOP_STBY__reg_uart_rxd_i_use_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_uart_rxd_i_use_sel_BITSTART 10
#define HS_Standby__SH08_TOP_STBY__reg_uart_rxd_i_use_sel_BITEND 11

#define HS_Standby__SH08_TOP_STBY__reg_uart0_sin_use_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_uart0_sin_use_sel_BITSTART 12
#define HS_Standby__SH08_TOP_STBY__reg_uart0_sin_use_sel_BITEND 12

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp6_func_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp6_func_sel_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp6_func_sel_BITEND 16

#define HS_Standby__SH08_TOP_STBY__reg_stby_gp7_func_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp7_func_sel_BITSTART 17
#define HS_Standby__SH08_TOP_STBY__reg_stby_gp7_func_sel_BITEND 17

#define HS_Standby__SH08_TOP_STBY__reg_io_user_mode_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_io_user_mode_BITSTART 18
#define HS_Standby__SH08_TOP_STBY__reg_io_user_mode_BITEND 18

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_func_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_func_sel_BITSTART 19
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_ddc1_func_sel_BITEND 20

#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_func_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_func_sel_BITSTART 21
#define HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_ddc1_func_sel_BITEND 22

#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i2_use_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i2_use_sel_BITSTART 23
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i2_use_sel_BITEND 23

#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i3_use_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i3_use_sel_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i3_use_sel_BITEND 24

#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_BITSTART 25
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_BITEND 25

#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i5_use_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i5_use_sel_BITSTART 26
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i5_use_sel_BITEND 26

#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i6_use_sel_ADDR 0x11008424
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i6_use_sel_BITSTART 27
#define HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i6_use_sel_BITEND 27

#define HS_Standby__SH08_TOP_STBY__regr_dbgi2c_scl_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_dbgi2c_scl_di_BITSTART 0
#define HS_Standby__SH08_TOP_STBY__regr_dbgi2c_scl_di_BITEND 0

#define HS_Standby__SH08_TOP_STBY__regr_dbgi2c_sda_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_dbgi2c_sda_di_BITSTART 1
#define HS_Standby__SH08_TOP_STBY__regr_dbgi2c_sda_di_BITEND 1

#define HS_Standby__SH08_TOP_STBY__regr_dp_rx0_cable_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx0_cable_di_BITSTART 2
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx0_cable_di_BITEND 2

#define HS_Standby__SH08_TOP_STBY__regr_dp_rx0_hpd_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx0_hpd_di_BITSTART 3
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx0_hpd_di_BITEND 3

#define HS_Standby__SH08_TOP_STBY__regr_dp_rx1_cable_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx1_cable_di_BITSTART 4
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx1_cable_di_BITEND 4

#define HS_Standby__SH08_TOP_STBY__regr_dp_rx1_hpd_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx1_hpd_di_BITSTART 5
#define HS_Standby__SH08_TOP_STBY__regr_dp_rx1_hpd_di_BITEND 5

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_cable_det_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_cable_det_di_BITSTART 6
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_cable_det_di_BITEND 6

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_cec_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_cec_di_BITSTART 7
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_cec_di_BITEND 7

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_ddc0_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_ddc0_di_BITSTART 8
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_ddc0_di_BITEND 8

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_ddc1_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_ddc1_di_BITSTART 9
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx0_ddc1_di_BITEND 9

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_cable_det_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_cable_det_di_BITSTART 10
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_cable_det_di_BITEND 10

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_cec_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_cec_di_BITSTART 11
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_cec_di_BITEND 11

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_ddc0_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_ddc0_di_BITSTART 12
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_ddc0_di_BITEND 12

#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_ddc1_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_ddc1_di_BITSTART 13
#define HS_Standby__SH08_TOP_STBY__regr_hdmi_rx1_ddc1_di_BITEND 13

#define HS_Standby__SH08_TOP_STBY__regr_mi2c_scl_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_mi2c_scl_di_BITSTART 14
#define HS_Standby__SH08_TOP_STBY__regr_mi2c_scl_di_BITEND 14

#define HS_Standby__SH08_TOP_STBY__regr_mi2c_sda_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_mi2c_sda_di_BITSTART 15
#define HS_Standby__SH08_TOP_STBY__regr_mi2c_sda_di_BITEND 15

#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_clk_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_clk_di_BITSTART 16
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_clk_di_BITEND 16

#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_csn_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_csn_di_BITSTART 17
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_csn_di_BITEND 17

#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_hold_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_hold_di_BITSTART 18
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_hold_di_BITEND 18

#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_miso_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_miso_di_BITSTART 19
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_miso_di_BITEND 19

#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_mosi_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_mosi_di_BITSTART 20
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_mosi_di_BITEND 20

#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_wp_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_wp_di_BITSTART 21
#define HS_Standby__SH08_TOP_STBY__regr_prog_spi_wp_di_BITEND 21

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp0_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp0_di_BITSTART 22
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp0_di_BITEND 22

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp1_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp1_di_BITSTART 23
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp1_di_BITEND 23

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp2_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp2_di_BITSTART 24
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp2_di_BITEND 24

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp3_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp3_di_BITSTART 25
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp3_di_BITEND 25

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp4_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp4_di_BITSTART 26
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp4_di_BITEND 26

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp5_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp5_di_BITSTART 27
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp5_di_BITEND 27

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp6_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp6_di_BITSTART 28
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp6_di_BITEND 28

#define HS_Standby__SH08_TOP_STBY__regr_stby_gp7_di_ADDR 0x110084D0
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp7_di_BITSTART 29
#define HS_Standby__SH08_TOP_STBY__regr_stby_gp7_di_BITEND 29

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_ADDR 0x11008500
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_HDMIRX_REVISION_ID_ADDR 0x11008508
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_HDMIRX_REVISION_ID_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_HDMIRX_REVISION_ID_BITEND 31

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_SEND_ADDR 0x11008510
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_SEND_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_SEND_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_FRAME_TYP_ADDR 0x11008510
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_FRAME_TYP_BITSTART 1
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_FRAME_TYP_BITEND 2

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_BC_NACK_ADDR 0x11008510
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_BC_NACK_BITSTART 3
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_BC_NACK_BITEND 3

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_STANDBY_ADDR 0x11008510
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_STANDBY_BITSTART 4
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_STANDBY_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DONE_mask_ADDR 0x11008514
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DONE_mask_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DONE_mask_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_EOM_mask_ADDR 0x11008514
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_EOM_mask_BITSTART 1
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_EOM_mask_BITEND 1

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_NACK_mask_ADDR 0x11008514
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_NACK_mask_BITSTART 2
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_NACK_mask_BITEND 2

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ARB_LOST_mask_ADDR 0x11008514
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ARB_LOST_mask_BITSTART 3
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ARB_LOST_mask_BITEND 3

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ERROR_INITIATOR_mask_ADDR 0x11008514
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ERROR_INITIATOR_mask_BITSTART 4
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ERROR_INITIATOR_mask_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ERROR_FLOW_mask_ADDR 0x11008514
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ERROR_FLOW_mask_BITSTART 5
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_ERROR_FLOW_mask_BITEND 5

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_WAKEUP_mask_ADDR 0x11008514
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_WAKEUP_mask_BITSTART 6
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_WAKEUP_mask_BITEND 6

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_ADDR_L_ADDR 0x11008518
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_ADDR_L_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_ADDR_L_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_ADDR_H_ADDR 0x1100851C
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_ADDR_H_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_ADDR_H_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_TX_CNT_ADDR 0x11008520
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_TX_CNT_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_CEC_TX_CNT_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_CEC_RX_CNT_ADDR 0x11008524
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_CEC_RX_CNT_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_CEC_RX_CNT_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_wtx_state_ADDR 0x11008524
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_wtx_state_BITSTART 5
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_wtx_state_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE0_ADDR 0x11008528
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE0_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE0_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE1_ADDR 0x1100852C
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE1_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE1_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE2_ADDR 0x11008530
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE2_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE2_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE3_ADDR 0x11008534
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE3_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE3_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE4_ADDR 0x11008538
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE4_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE4_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE5_ADDR 0x1100853C
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE5_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE5_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE6_ADDR 0x11008540
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE6_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE6_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE7_ADDR 0x11008544
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE7_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE7_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE8_ADDR 0x11008548
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE8_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE8_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE9_ADDR 0x1100854C
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE9_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE9_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE10_ADDR 0x11008550
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE10_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE10_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE11_ADDR 0x11008554
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE11_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE11_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE12_ADDR 0x11008558
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE12_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE12_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE13_ADDR 0x1100855C
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE13_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE13_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE14_ADDR 0x11008560
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE14_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE14_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE15_ADDR 0x11008564
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE15_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_DATABYTE15_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE0_ADDR 0x11008568
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE0_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE0_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE1_ADDR 0x1100856C
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE1_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE1_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE2_ADDR 0x11008570
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE2_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE2_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE3_ADDR 0x11008574
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE3_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE3_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE4_ADDR 0x11008578
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE4_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE4_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE5_ADDR 0x1100857C
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE5_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE5_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE6_ADDR 0x11008580
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE6_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE6_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE7_ADDR 0x11008584
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE7_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE7_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE8_ADDR 0x11008588
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE8_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE8_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE9_ADDR 0x1100858C
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE9_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE9_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE10_ADDR 0x11008590
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE10_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE10_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE11_ADDR 0x11008594
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE11_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE11_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE12_ADDR 0x11008598
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE12_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE12_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE13_ADDR 0x1100859C
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE13_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE13_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE14_ADDR 0x110085A0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE14_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE14_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE15_ADDR 0x110085A4
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE15_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_DATABYTE15_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__regr_00_wake_ctrl_status_ADDR 0x110085A4
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_wake_ctrl_status_BITSTART 8
#define HS_Standby__HDMI21_RX_CEC_00__regr_00_wake_ctrl_status_BITEND 15

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_LOCKED_BUFFER_ADDR 0x110085A8
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_LOCKED_BUFFER_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_LOCKED_BUFFER_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X04EN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X04EN_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X04EN_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X0DEN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X0DEN_BITSTART 1
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X0DEN_BITEND 1

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X41EN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X41EN_BITSTART 2
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X41EN_BITEND 2

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X42EN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X42EN_BITSTART 3
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X42EN_BITEND 3

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X44EN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X44EN_BITSTART 4
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X44EN_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X70EN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X70EN_BITSTART 5
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X70EN_BITEND 5

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X82EN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X82EN_BITSTART 6
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X82EN_BITEND 6

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X86EN_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X86EN_BITSTART 7
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_OPCODE0X86EN_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_BITSTART 8
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_BITEND 8

#define HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_ADDR 0x110085AC
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_BITSTART 9
#define HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_BITEND 9

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_00_ADDR 0x11008600
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_00_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_00_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_01_ADDR 0x11008600
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_01_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_01_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_02_ADDR 0x11008600
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_02_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_02_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_03_ADDR 0x11008600
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_03_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_03_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_04_ADDR 0x11008604
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_04_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_04_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_05_ADDR 0x11008604
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_05_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_05_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_06_ADDR 0x11008604
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_06_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_06_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_07_ADDR 0x11008604
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_07_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_07_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_08_ADDR 0x11008608
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_08_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_08_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_09_ADDR 0x11008608
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_09_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_09_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0A_ADDR 0x11008608
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0B_ADDR 0x11008608
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0C_ADDR 0x1100860C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0D_ADDR 0x1100860C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0E_ADDR 0x1100860C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0F_ADDR 0x1100860C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_0F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_10_ADDR 0x11008610
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_10_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_10_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_11_ADDR 0x11008610
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_11_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_11_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_12_ADDR 0x11008610
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_12_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_12_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_13_ADDR 0x11008610
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_13_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_13_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_14_ADDR 0x11008614
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_14_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_14_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_15_ADDR 0x11008614
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_15_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_15_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_16_ADDR 0x11008614
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_16_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_16_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_17_ADDR 0x11008614
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_17_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_17_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_18_ADDR 0x11008618
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_18_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_18_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_19_ADDR 0x11008618
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_19_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_19_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1A_ADDR 0x11008618
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1B_ADDR 0x11008618
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1C_ADDR 0x1100861C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1D_ADDR 0x1100861C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1E_ADDR 0x1100861C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1F_ADDR 0x1100861C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_1F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_20_ADDR 0x11008620
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_20_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_20_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_21_ADDR 0x11008620
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_21_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_21_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_22_ADDR 0x11008620
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_22_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_22_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_23_ADDR 0x11008620
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_23_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_23_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_24_ADDR 0x11008624
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_24_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_24_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_25_ADDR 0x11008624
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_25_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_25_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_26_ADDR 0x11008624
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_26_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_26_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_27_ADDR 0x11008624
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_27_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_27_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_28_ADDR 0x11008628
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_28_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_28_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_29_ADDR 0x11008628
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_29_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_29_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2A_ADDR 0x11008628
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2B_ADDR 0x11008628
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2C_ADDR 0x1100862C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2D_ADDR 0x1100862C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2E_ADDR 0x1100862C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2F_ADDR 0x1100862C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_2F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_30_ADDR 0x11008630
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_30_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_30_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_31_ADDR 0x11008630
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_31_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_31_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_32_ADDR 0x11008630
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_32_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_32_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_33_ADDR 0x11008630
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_33_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_33_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_34_ADDR 0x11008634
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_34_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_34_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_35_ADDR 0x11008634
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_35_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_35_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_36_ADDR 0x11008634
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_36_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_36_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_37_ADDR 0x11008634
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_37_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_37_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_38_ADDR 0x11008638
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_38_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_38_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_39_ADDR 0x11008638
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_39_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_39_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3A_ADDR 0x11008638
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3B_ADDR 0x11008638
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3C_ADDR 0x1100863C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3D_ADDR 0x1100863C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3E_ADDR 0x1100863C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3F_ADDR 0x1100863C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_3F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_40_ADDR 0x11008640
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_40_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_40_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_41_ADDR 0x11008640
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_41_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_41_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_42_ADDR 0x11008640
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_42_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_42_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_43_ADDR 0x11008640
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_43_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_43_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_44_ADDR 0x11008644
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_44_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_44_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_45_ADDR 0x11008644
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_45_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_45_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_46_ADDR 0x11008644
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_46_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_46_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_47_ADDR 0x11008644
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_47_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_47_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_48_ADDR 0x11008648
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_48_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_48_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_49_ADDR 0x11008648
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_49_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_49_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4A_ADDR 0x11008648
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4B_ADDR 0x11008648
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4C_ADDR 0x1100864C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4D_ADDR 0x1100864C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4E_ADDR 0x1100864C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4F_ADDR 0x1100864C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_4F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_50_ADDR 0x11008650
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_50_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_50_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_51_ADDR 0x11008650
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_51_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_51_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_52_ADDR 0x11008650
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_52_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_52_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_53_ADDR 0x11008650
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_53_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_53_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_54_ADDR 0x11008654
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_54_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_54_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_55_ADDR 0x11008654
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_55_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_55_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_56_ADDR 0x11008654
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_56_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_56_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_57_ADDR 0x11008654
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_57_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_57_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_58_ADDR 0x11008658
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_58_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_58_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_59_ADDR 0x11008658
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_59_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_59_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5A_ADDR 0x11008658
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5B_ADDR 0x11008658
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5C_ADDR 0x1100865C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5D_ADDR 0x1100865C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5E_ADDR 0x1100865C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5F_ADDR 0x1100865C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_5F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_60_ADDR 0x11008660
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_60_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_60_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_61_ADDR 0x11008660
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_61_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_61_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_62_ADDR 0x11008660
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_62_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_62_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_63_ADDR 0x11008660
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_63_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_63_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_64_ADDR 0x11008664
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_64_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_64_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_65_ADDR 0x11008664
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_65_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_65_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_66_ADDR 0x11008664
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_66_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_66_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_67_ADDR 0x11008664
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_67_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_67_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_68_ADDR 0x11008668
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_68_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_68_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_69_ADDR 0x11008668
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_69_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_69_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6A_ADDR 0x11008668
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6B_ADDR 0x11008668
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6C_ADDR 0x1100866C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6D_ADDR 0x1100866C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6E_ADDR 0x1100866C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6F_ADDR 0x1100866C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_6F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_70_ADDR 0x11008670
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_70_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_70_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_71_ADDR 0x11008670
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_71_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_71_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_72_ADDR 0x11008670
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_72_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_72_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_73_ADDR 0x11008670
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_73_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_73_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_74_ADDR 0x11008674
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_74_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_74_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_75_ADDR 0x11008674
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_75_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_75_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_76_ADDR 0x11008674
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_76_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_76_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_77_ADDR 0x11008674
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_77_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_77_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_78_ADDR 0x11008678
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_78_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_78_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_79_ADDR 0x11008678
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_79_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_79_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7A_ADDR 0x11008678
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7B_ADDR 0x11008678
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7C_ADDR 0x1100867C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7D_ADDR 0x1100867C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7E_ADDR 0x1100867C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7F_ADDR 0x1100867C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_7F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_80_ADDR 0x11008680
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_80_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_80_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_81_ADDR 0x11008680
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_81_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_81_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_82_ADDR 0x11008680
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_82_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_82_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_83_ADDR 0x11008680
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_83_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_83_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_84_ADDR 0x11008684
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_84_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_84_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_85_ADDR 0x11008684
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_85_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_85_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_86_ADDR 0x11008684
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_86_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_86_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_87_ADDR 0x11008684
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_87_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_87_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_88_ADDR 0x11008688
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_88_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_88_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_89_ADDR 0x11008688
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_89_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_89_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8A_ADDR 0x11008688
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8B_ADDR 0x11008688
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8C_ADDR 0x1100868C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8D_ADDR 0x1100868C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8E_ADDR 0x1100868C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8F_ADDR 0x1100868C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_8F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_90_ADDR 0x11008690
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_90_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_90_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_91_ADDR 0x11008690
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_91_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_91_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_92_ADDR 0x11008690
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_92_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_92_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_93_ADDR 0x11008690
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_93_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_93_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_94_ADDR 0x11008694
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_94_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_94_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_95_ADDR 0x11008694
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_95_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_95_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_96_ADDR 0x11008694
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_96_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_96_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_97_ADDR 0x11008694
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_97_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_97_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_98_ADDR 0x11008698
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_98_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_98_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_99_ADDR 0x11008698
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_99_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_99_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9A_ADDR 0x11008698
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9B_ADDR 0x11008698
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9C_ADDR 0x1100869C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9D_ADDR 0x1100869C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9E_ADDR 0x1100869C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9F_ADDR 0x1100869C
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_9F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A0_ADDR 0x110086A0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A1_ADDR 0x110086A0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A2_ADDR 0x110086A0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A3_ADDR 0x110086A0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A4_ADDR 0x110086A4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A5_ADDR 0x110086A4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A6_ADDR 0x110086A4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A7_ADDR 0x110086A4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A8_ADDR 0x110086A8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A9_ADDR 0x110086A8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_A9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AA_ADDR 0x110086A8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AB_ADDR 0x110086A8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AC_ADDR 0x110086AC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AD_ADDR 0x110086AC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AE_ADDR 0x110086AC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AF_ADDR 0x110086AC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_AF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B0_ADDR 0x110086B0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B1_ADDR 0x110086B0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B2_ADDR 0x110086B0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B3_ADDR 0x110086B0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B4_ADDR 0x110086B4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B5_ADDR 0x110086B4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B6_ADDR 0x110086B4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B7_ADDR 0x110086B4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B8_ADDR 0x110086B8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B9_ADDR 0x110086B8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_B9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BA_ADDR 0x110086B8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BB_ADDR 0x110086B8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BC_ADDR 0x110086BC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BD_ADDR 0x110086BC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BE_ADDR 0x110086BC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BF_ADDR 0x110086BC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_BF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C0_ADDR 0x110086C0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C1_ADDR 0x110086C0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C2_ADDR 0x110086C0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C3_ADDR 0x110086C0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C4_ADDR 0x110086C4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C5_ADDR 0x110086C4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C6_ADDR 0x110086C4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C7_ADDR 0x110086C4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C8_ADDR 0x110086C8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C9_ADDR 0x110086C8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_C9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CA_ADDR 0x110086C8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CB_ADDR 0x110086C8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CC_ADDR 0x110086CC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CD_ADDR 0x110086CC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CE_ADDR 0x110086CC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CF_ADDR 0x110086CC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_CF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D0_ADDR 0x110086D0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D1_ADDR 0x110086D0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D2_ADDR 0x110086D0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D3_ADDR 0x110086D0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D4_ADDR 0x110086D4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D5_ADDR 0x110086D4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D6_ADDR 0x110086D4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D7_ADDR 0x110086D4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D8_ADDR 0x110086D8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D9_ADDR 0x110086D8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_D9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DA_ADDR 0x110086D8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DB_ADDR 0x110086D8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DC_ADDR 0x110086DC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DD_ADDR 0x110086DC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DE_ADDR 0x110086DC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DF_ADDR 0x110086DC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_DF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E0_ADDR 0x110086E0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E1_ADDR 0x110086E0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E2_ADDR 0x110086E0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E3_ADDR 0x110086E0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E4_ADDR 0x110086E4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E5_ADDR 0x110086E4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E6_ADDR 0x110086E4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E7_ADDR 0x110086E4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E8_ADDR 0x110086E8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E9_ADDR 0x110086E8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_E9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EA_ADDR 0x110086E8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EB_ADDR 0x110086E8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EC_ADDR 0x110086EC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_ED_ADDR 0x110086EC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_ED_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_ED_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EE_ADDR 0x110086EC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EF_ADDR 0x110086EC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_EF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F0_ADDR 0x110086F0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F1_ADDR 0x110086F0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F2_ADDR 0x110086F0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F3_ADDR 0x110086F0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F4_ADDR 0x110086F4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F5_ADDR 0x110086F4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F6_ADDR 0x110086F4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F7_ADDR 0x110086F4
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F8_ADDR 0x110086F8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F9_ADDR 0x110086F8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_F9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FA_ADDR 0x110086F8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FB_ADDR 0x110086F8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FC_ADDR 0x110086FC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FD_ADDR 0x110086FC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FE_ADDR 0x110086FC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FF_ADDR 0x110086FC
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_00__reg_00_edid_data_FF_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_edid_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_edid_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_edid_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_segment_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_segment_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_segment_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_ddcci_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_ddcci_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_ddcci_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_usr0_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_usr0_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_usr0_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_usr1_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_usr1_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_usr1_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_edid_segment_clr_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_edid_segment_clr_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_edid_segment_clr_BITEND 8

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_edid_segment_clr_auto_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_edid_segment_clr_auto_BITSTART 9
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_edid_segment_clr_auto_BITEND 9

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_edid_ADDR 0x11008700
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_edid_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_edid_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_segment_ADDR 0x11008704
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_segment_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_segment_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_ddcci_ADDR 0x11008704
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_ddcci_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_ddcci_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_usr0_ADDR 0x11008704
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_usr0_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_usr0_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_usr1_ADDR 0x11008704
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_usr1_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_addr_usr1_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_hw_read_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_hw_read_en_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_hw_read_en_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_sw_read_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_sw_read_en_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_sw_read_en_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_segment_sw_read_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_segment_sw_read_en_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_segment_sw_read_en_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_ddcci_sw_read_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_ddcci_sw_read_en_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_ddcci_sw_read_en_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr0_sw_read_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr0_sw_read_en_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr0_sw_read_en_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr1_sw_read_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr1_sw_read_en_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr1_sw_read_en_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_sw_write_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_sw_write_en_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_edid_sw_write_en_BITEND 8

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_segment_sw_write_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_segment_sw_write_en_BITSTART 9
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_segment_sw_write_en_BITEND 9

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_ddcci_sw_write_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_ddcci_sw_write_en_BITSTART 10
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_ddcci_sw_write_en_BITEND 10

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr0_sw_write_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr0_sw_write_en_BITSTART 11
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr0_sw_write_en_BITEND 11

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr1_sw_write_en_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr1_sw_write_en_BITSTART 12
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_slv_usr1_sw_write_en_BITEND 12

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_th_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_th_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_th_BITEND 20

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_req_th_ADDR 0x11008708
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_req_th_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_req_th_BITEND 28

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2cspikesuppr_ADDR 0x1100870C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2cspikesuppr_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2cspikesuppr_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2ctimouten_ADDR 0x1100870C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2ctimouten_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2ctimouten_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2ctimoutcnt_ADDR 0x1100870C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2ctimoutcnt_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2ctimoutcnt_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_standby_only_ADDR 0x1100870C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_standby_only_BITSTART 23
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_standby_only_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_start_pulse_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_start_pulse_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_start_pulse_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_restart_pulse_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_restart_pulse_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_restart_pulse_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_stop_pulse_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_stop_pulse_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_stop_pulse_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_slv_addr_valid_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_slv_addr_valid_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_slv_addr_valid_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_wr_data_valid_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_wr_data_valid_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_wr_data_valid_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_rd_data_req_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_rd_data_req_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_rd_data_req_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_edid_segment_update_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_edid_segment_update_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_edid_segment_update_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_start_pulse_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_start_pulse_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_start_pulse_BITEND 16

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_restart_pulse_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_restart_pulse_BITSTART 17
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_restart_pulse_BITEND 17

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_stop_pulse_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_stop_pulse_BITSTART 18
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_stop_pulse_BITEND 18

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_slv_addr_valid_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_slv_addr_valid_BITSTART 19
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_slv_addr_valid_BITEND 19

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_wr_data_valid_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_wr_data_valid_BITSTART 20
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_wr_data_valid_BITEND 20

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_rd_data_req_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_rd_data_req_BITSTART 21
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_rd_data_req_BITEND 21

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_BITSTART 22
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_data_clr_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_data_clr_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_data_clr_BITEND 24

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_cnt_clr_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_cnt_clr_BITSTART 25
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_cnt_clr_BITEND 25

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_BITSTART 26
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_wr_valid_clr_BITEND 26

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_cnt_clr_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_cnt_clr_BITSTART 28
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_cnt_clr_BITEND 28

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_req_clr_ADDR 0x11008710
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_req_clr_BITSTART 29
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_req_clr_BITEND 29

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_arblst_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_arblst_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_arblst_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_eom_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_eom_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_eom_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_error_foll_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_error_foll_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_error_foll_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_error_init_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_error_init_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_error_init_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_int_done_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_int_done_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_int_done_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_nack_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_nack_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_nack_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_wakeupctrl_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_wakeupctrl_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_wakeupctrl_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_arblst_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_arblst_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_arblst_BITEND 16

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_eom_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_eom_BITSTART 17
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_eom_BITEND 17

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_error_foll_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_error_foll_BITSTART 18
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_error_foll_BITEND 18

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_error_init_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_error_init_BITSTART 19
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_error_init_BITEND 19

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_int_done_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_int_done_BITSTART 20
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_int_done_BITEND 20

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_nack_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_nack_BITSTART 21
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_nack_BITEND 21

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_ADDR 0x11008714
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_BITSTART 22
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_ADDR 0x11008720
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_00_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_01_ADDR 0x11008720
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_01_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_01_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_02_ADDR 0x11008720
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_02_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_02_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_03_ADDR 0x11008720
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_03_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_03_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_04_ADDR 0x11008724
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_04_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_04_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_05_ADDR 0x11008724
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_05_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_05_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_06_ADDR 0x11008724
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_06_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_06_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_07_ADDR 0x11008724
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_07_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_07_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_08_ADDR 0x11008728
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_08_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_08_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_09_ADDR 0x11008728
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_09_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_09_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_10_ADDR 0x11008728
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_10_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_10_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_11_ADDR 0x11008728
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_11_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_11_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_12_ADDR 0x1100872C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_12_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_12_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_13_ADDR 0x1100872C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_13_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_13_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_14_ADDR 0x1100872C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_14_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_14_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_15_ADDR 0x1100872C
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_15_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_15_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_16_ADDR 0x11008730
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_16_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_16_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_17_ADDR 0x11008730
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_17_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_17_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_18_ADDR 0x11008730
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_18_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_18_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_19_ADDR 0x11008730
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_19_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_19_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_20_ADDR 0x11008734
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_20_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_20_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_21_ADDR 0x11008734
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_21_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_21_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_22_ADDR 0x11008734
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_22_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_22_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_23_ADDR 0x11008734
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_23_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_ddc_i2c_rd_data_23_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_mon_sel_ADDR 0x11008738
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_mon_sel_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__reg_00_int_mon_sel_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_mon_cnt_ADDR 0x1100873C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_mon_cnt_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_mon_cnt_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_start_pulse_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_start_pulse_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_start_pulse_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_restart_pulse_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_restart_pulse_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_restart_pulse_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_stop_pulse_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_stop_pulse_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_stop_pulse_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_slv_addr_valid_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_slv_addr_valid_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_slv_addr_valid_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_wr_data_valid_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_wr_data_valid_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_wr_data_valid_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_rd_data_req_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_rd_data_req_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_rd_data_req_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_edid_segment_update_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_edid_segment_update_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_edid_segment_update_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_arblst_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_arblst_BITSTART 7
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_arblst_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_eom_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_eom_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_eom_BITEND 8

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_error_foll_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_error_foll_BITSTART 9
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_error_foll_BITEND 9

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_error_init_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_error_init_BITSTART 10
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_error_init_BITEND 10

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_int_done_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_int_done_BITSTART 11
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_int_done_BITEND 11

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_nack_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_nack_BITSTART 12
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_nack_BITEND 12

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_wakeupctrl_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_wakeupctrl_BITSTART 13
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_int_pending_cec_wakeupctrl_BITEND 13

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_edid_segment_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_edid_segment_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_edid_segment_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_rcurstate_ADDR 0x11008740
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_rcurstate_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_rcurstate_BITEND 27

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_edid_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_edid_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_edid_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_segment_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_segment_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_segment_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_ddcci_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_ddcci_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_ddcci_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_usr0_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_usr0_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_usr0_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_usr1_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_usr1_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_sel_slv_usr1_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_valid_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_valid_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_valid_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_rd_req_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_rd_req_BITSTART 7
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_rd_req_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_valid_num_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_valid_num_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_valid_num_BITEND 12

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_cnt_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_cnt_BITSTART 13
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_cnt_BITEND 17

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_rd_cnt_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_rd_cnt_BITSTART 18
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_rd_cnt_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_slave_addr_ADDR 0x11008744
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_slave_addr_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_slave_addr_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_ADDR 0x11008748
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_00_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_01_ADDR 0x11008748
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_01_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_01_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_02_ADDR 0x11008748
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_02_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_02_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_03_ADDR 0x11008748
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_03_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_03_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_04_ADDR 0x1100874C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_04_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_04_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_05_ADDR 0x1100874C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_05_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_05_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_06_ADDR 0x1100874C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_06_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_06_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_07_ADDR 0x1100874C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_07_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_07_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_08_ADDR 0x11008750
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_08_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_08_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_09_ADDR 0x11008750
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_09_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_09_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_10_ADDR 0x11008750
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_10_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_10_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_11_ADDR 0x11008750
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_11_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_11_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_12_ADDR 0x11008754
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_12_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_12_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_13_ADDR 0x11008754
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_13_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_13_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_14_ADDR 0x11008754
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_14_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_14_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_15_ADDR 0x11008754
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_15_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_15_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_16_ADDR 0x11008758
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_16_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_16_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_17_ADDR 0x11008758
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_17_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_17_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_18_ADDR 0x11008758
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_18_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_18_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_19_ADDR 0x11008758
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_19_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_19_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_20_ADDR 0x1100875C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_20_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_20_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_21_ADDR 0x1100875C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_21_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_21_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_22_ADDR 0x1100875C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_22_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_22_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_23_ADDR 0x1100875C
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_23_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_00__regr_00_ddc_i2c_wr_data_23_BITEND 31

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_ADDR 0x11008800
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_HDMIRX_REVISION_ID_ADDR 0x11008808
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_HDMIRX_REVISION_ID_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_HDMIRX_REVISION_ID_BITEND 31

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_SEND_ADDR 0x11008810
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_SEND_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_SEND_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_FRAME_TYP_ADDR 0x11008810
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_FRAME_TYP_BITSTART 1
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_FRAME_TYP_BITEND 2

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_BC_NACK_ADDR 0x11008810
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_BC_NACK_BITSTART 3
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_BC_NACK_BITEND 3

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_STANDBY_ADDR 0x11008810
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_STANDBY_BITSTART 4
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_STANDBY_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DONE_mask_ADDR 0x11008814
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DONE_mask_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DONE_mask_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_EOM_mask_ADDR 0x11008814
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_EOM_mask_BITSTART 1
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_EOM_mask_BITEND 1

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_NACK_mask_ADDR 0x11008814
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_NACK_mask_BITSTART 2
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_NACK_mask_BITEND 2

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ARB_LOST_mask_ADDR 0x11008814
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ARB_LOST_mask_BITSTART 3
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ARB_LOST_mask_BITEND 3

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ERROR_INITIATOR_mask_ADDR 0x11008814
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ERROR_INITIATOR_mask_BITSTART 4
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ERROR_INITIATOR_mask_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ERROR_FLOW_mask_ADDR 0x11008814
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ERROR_FLOW_mask_BITSTART 5
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_ERROR_FLOW_mask_BITEND 5

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_WAKEUP_mask_ADDR 0x11008814
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_WAKEUP_mask_BITSTART 6
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_WAKEUP_mask_BITEND 6

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_ADDR_L_ADDR 0x11008818
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_ADDR_L_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_ADDR_L_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_ADDR_H_ADDR 0x1100881C
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_ADDR_H_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_ADDR_H_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_TX_CNT_ADDR 0x11008820
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_TX_CNT_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_CEC_TX_CNT_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_CEC_RX_CNT_ADDR 0x11008824
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_CEC_RX_CNT_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_CEC_RX_CNT_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_wtx_state_ADDR 0x11008824
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_wtx_state_BITSTART 5
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_wtx_state_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE0_ADDR 0x11008828
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE0_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE0_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE1_ADDR 0x1100882C
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE1_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE1_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE2_ADDR 0x11008830
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE2_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE2_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE3_ADDR 0x11008834
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE3_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE3_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE4_ADDR 0x11008838
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE4_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE4_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE5_ADDR 0x1100883C
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE5_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE5_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE6_ADDR 0x11008840
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE6_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE6_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE7_ADDR 0x11008844
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE7_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE7_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE8_ADDR 0x11008848
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE8_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE8_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE9_ADDR 0x1100884C
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE9_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE9_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE10_ADDR 0x11008850
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE10_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE10_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE11_ADDR 0x11008854
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE11_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE11_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE12_ADDR 0x11008858
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE12_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE12_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE13_ADDR 0x1100885C
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE13_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE13_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE14_ADDR 0x11008860
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE14_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE14_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE15_ADDR 0x11008864
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE15_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_DATABYTE15_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE0_ADDR 0x11008868
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE0_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE0_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE1_ADDR 0x1100886C
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE1_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE1_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE2_ADDR 0x11008870
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE2_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE2_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE3_ADDR 0x11008874
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE3_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE3_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE4_ADDR 0x11008878
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE4_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE4_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE5_ADDR 0x1100887C
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE5_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE5_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE6_ADDR 0x11008880
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE6_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE6_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE7_ADDR 0x11008884
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE7_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE7_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE8_ADDR 0x11008888
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE8_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE8_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE9_ADDR 0x1100888C
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE9_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE9_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE10_ADDR 0x11008890
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE10_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE10_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE11_ADDR 0x11008894
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE11_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE11_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE12_ADDR 0x11008898
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE12_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE12_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE13_ADDR 0x1100889C
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE13_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE13_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE14_ADDR 0x110088A0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE14_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE14_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE15_ADDR 0x110088A4
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE15_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_DATABYTE15_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__regr_01_wake_ctrl_status_ADDR 0x110088A4
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_wake_ctrl_status_BITSTART 8
#define HS_Standby__HDMI21_RX_CEC_01__regr_01_wake_ctrl_status_BITEND 15

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_LOCKED_BUFFER_ADDR 0x110088A8
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_LOCKED_BUFFER_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_LOCKED_BUFFER_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X04EN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X04EN_BITSTART 0
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X04EN_BITEND 0

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X0DEN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X0DEN_BITSTART 1
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X0DEN_BITEND 1

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X41EN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X41EN_BITSTART 2
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X41EN_BITEND 2

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X42EN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X42EN_BITSTART 3
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X42EN_BITEND 3

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X44EN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X44EN_BITSTART 4
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X44EN_BITEND 4

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X70EN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X70EN_BITSTART 5
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X70EN_BITEND 5

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X82EN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X82EN_BITSTART 6
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X82EN_BITEND 6

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X86EN_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X86EN_BITSTART 7
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_OPCODE0X86EN_BITEND 7

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_BITSTART 8
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_BITEND 8

#define HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_ADDR 0x110088AC
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_BITSTART 9
#define HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_BITEND 9

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_00_ADDR 0x11008900
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_00_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_00_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_01_ADDR 0x11008900
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_01_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_01_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_02_ADDR 0x11008900
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_02_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_02_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_03_ADDR 0x11008900
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_03_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_03_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_04_ADDR 0x11008904
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_04_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_04_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_05_ADDR 0x11008904
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_05_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_05_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_06_ADDR 0x11008904
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_06_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_06_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_07_ADDR 0x11008904
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_07_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_07_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_08_ADDR 0x11008908
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_08_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_08_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_09_ADDR 0x11008908
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_09_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_09_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0A_ADDR 0x11008908
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0B_ADDR 0x11008908
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0C_ADDR 0x1100890C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0D_ADDR 0x1100890C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0E_ADDR 0x1100890C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0F_ADDR 0x1100890C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_0F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_10_ADDR 0x11008910
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_10_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_10_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_11_ADDR 0x11008910
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_11_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_11_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_12_ADDR 0x11008910
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_12_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_12_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_13_ADDR 0x11008910
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_13_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_13_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_14_ADDR 0x11008914
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_14_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_14_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_15_ADDR 0x11008914
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_15_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_15_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_16_ADDR 0x11008914
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_16_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_16_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_17_ADDR 0x11008914
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_17_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_17_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_18_ADDR 0x11008918
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_18_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_18_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_19_ADDR 0x11008918
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_19_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_19_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1A_ADDR 0x11008918
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1B_ADDR 0x11008918
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1C_ADDR 0x1100891C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1D_ADDR 0x1100891C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1E_ADDR 0x1100891C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1F_ADDR 0x1100891C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_1F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_20_ADDR 0x11008920
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_20_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_20_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_21_ADDR 0x11008920
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_21_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_21_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_22_ADDR 0x11008920
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_22_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_22_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_23_ADDR 0x11008920
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_23_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_23_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_24_ADDR 0x11008924
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_24_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_24_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_25_ADDR 0x11008924
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_25_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_25_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_26_ADDR 0x11008924
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_26_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_26_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_27_ADDR 0x11008924
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_27_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_27_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_28_ADDR 0x11008928
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_28_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_28_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_29_ADDR 0x11008928
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_29_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_29_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2A_ADDR 0x11008928
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2B_ADDR 0x11008928
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2C_ADDR 0x1100892C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2D_ADDR 0x1100892C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2E_ADDR 0x1100892C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2F_ADDR 0x1100892C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_2F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_30_ADDR 0x11008930
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_30_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_30_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_31_ADDR 0x11008930
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_31_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_31_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_32_ADDR 0x11008930
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_32_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_32_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_33_ADDR 0x11008930
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_33_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_33_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_34_ADDR 0x11008934
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_34_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_34_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_35_ADDR 0x11008934
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_35_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_35_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_36_ADDR 0x11008934
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_36_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_36_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_37_ADDR 0x11008934
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_37_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_37_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_38_ADDR 0x11008938
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_38_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_38_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_39_ADDR 0x11008938
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_39_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_39_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3A_ADDR 0x11008938
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3B_ADDR 0x11008938
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3C_ADDR 0x1100893C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3D_ADDR 0x1100893C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3E_ADDR 0x1100893C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3F_ADDR 0x1100893C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_3F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_40_ADDR 0x11008940
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_40_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_40_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_41_ADDR 0x11008940
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_41_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_41_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_42_ADDR 0x11008940
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_42_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_42_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_43_ADDR 0x11008940
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_43_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_43_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_44_ADDR 0x11008944
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_44_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_44_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_45_ADDR 0x11008944
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_45_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_45_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_46_ADDR 0x11008944
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_46_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_46_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_47_ADDR 0x11008944
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_47_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_47_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_48_ADDR 0x11008948
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_48_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_48_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_49_ADDR 0x11008948
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_49_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_49_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4A_ADDR 0x11008948
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4B_ADDR 0x11008948
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4C_ADDR 0x1100894C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4D_ADDR 0x1100894C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4E_ADDR 0x1100894C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4F_ADDR 0x1100894C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_4F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_50_ADDR 0x11008950
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_50_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_50_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_51_ADDR 0x11008950
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_51_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_51_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_52_ADDR 0x11008950
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_52_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_52_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_53_ADDR 0x11008950
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_53_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_53_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_54_ADDR 0x11008954
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_54_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_54_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_55_ADDR 0x11008954
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_55_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_55_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_56_ADDR 0x11008954
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_56_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_56_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_57_ADDR 0x11008954
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_57_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_57_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_58_ADDR 0x11008958
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_58_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_58_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_59_ADDR 0x11008958
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_59_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_59_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5A_ADDR 0x11008958
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5B_ADDR 0x11008958
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5C_ADDR 0x1100895C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5D_ADDR 0x1100895C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5E_ADDR 0x1100895C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5F_ADDR 0x1100895C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_5F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_60_ADDR 0x11008960
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_60_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_60_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_61_ADDR 0x11008960
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_61_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_61_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_62_ADDR 0x11008960
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_62_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_62_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_63_ADDR 0x11008960
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_63_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_63_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_64_ADDR 0x11008964
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_64_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_64_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_65_ADDR 0x11008964
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_65_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_65_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_66_ADDR 0x11008964
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_66_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_66_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_67_ADDR 0x11008964
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_67_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_67_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_68_ADDR 0x11008968
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_68_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_68_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_69_ADDR 0x11008968
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_69_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_69_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6A_ADDR 0x11008968
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6B_ADDR 0x11008968
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6C_ADDR 0x1100896C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6D_ADDR 0x1100896C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6E_ADDR 0x1100896C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6F_ADDR 0x1100896C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_6F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_70_ADDR 0x11008970
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_70_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_70_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_71_ADDR 0x11008970
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_71_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_71_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_72_ADDR 0x11008970
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_72_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_72_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_73_ADDR 0x11008970
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_73_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_73_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_74_ADDR 0x11008974
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_74_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_74_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_75_ADDR 0x11008974
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_75_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_75_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_76_ADDR 0x11008974
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_76_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_76_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_77_ADDR 0x11008974
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_77_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_77_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_78_ADDR 0x11008978
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_78_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_78_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_79_ADDR 0x11008978
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_79_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_79_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7A_ADDR 0x11008978
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7B_ADDR 0x11008978
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7C_ADDR 0x1100897C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7D_ADDR 0x1100897C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7E_ADDR 0x1100897C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7F_ADDR 0x1100897C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_7F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_80_ADDR 0x11008980
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_80_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_80_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_81_ADDR 0x11008980
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_81_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_81_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_82_ADDR 0x11008980
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_82_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_82_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_83_ADDR 0x11008980
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_83_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_83_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_84_ADDR 0x11008984
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_84_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_84_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_85_ADDR 0x11008984
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_85_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_85_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_86_ADDR 0x11008984
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_86_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_86_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_87_ADDR 0x11008984
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_87_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_87_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_88_ADDR 0x11008988
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_88_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_88_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_89_ADDR 0x11008988
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_89_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_89_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8A_ADDR 0x11008988
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8B_ADDR 0x11008988
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8C_ADDR 0x1100898C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8D_ADDR 0x1100898C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8E_ADDR 0x1100898C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8F_ADDR 0x1100898C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_8F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_90_ADDR 0x11008990
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_90_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_90_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_91_ADDR 0x11008990
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_91_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_91_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_92_ADDR 0x11008990
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_92_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_92_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_93_ADDR 0x11008990
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_93_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_93_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_94_ADDR 0x11008994
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_94_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_94_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_95_ADDR 0x11008994
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_95_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_95_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_96_ADDR 0x11008994
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_96_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_96_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_97_ADDR 0x11008994
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_97_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_97_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_98_ADDR 0x11008998
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_98_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_98_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_99_ADDR 0x11008998
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_99_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_99_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9A_ADDR 0x11008998
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9A_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9A_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9B_ADDR 0x11008998
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9B_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9B_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9C_ADDR 0x1100899C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9C_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9C_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9D_ADDR 0x1100899C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9D_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9D_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9E_ADDR 0x1100899C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9E_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9E_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9F_ADDR 0x1100899C
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9F_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_9F_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A0_ADDR 0x110089A0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A1_ADDR 0x110089A0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A2_ADDR 0x110089A0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A3_ADDR 0x110089A0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A4_ADDR 0x110089A4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A5_ADDR 0x110089A4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A6_ADDR 0x110089A4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A7_ADDR 0x110089A4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A8_ADDR 0x110089A8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A9_ADDR 0x110089A8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_A9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AA_ADDR 0x110089A8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AB_ADDR 0x110089A8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AC_ADDR 0x110089AC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AD_ADDR 0x110089AC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AE_ADDR 0x110089AC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AF_ADDR 0x110089AC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_AF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B0_ADDR 0x110089B0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B1_ADDR 0x110089B0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B2_ADDR 0x110089B0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B3_ADDR 0x110089B0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B4_ADDR 0x110089B4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B5_ADDR 0x110089B4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B6_ADDR 0x110089B4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B7_ADDR 0x110089B4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B8_ADDR 0x110089B8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B9_ADDR 0x110089B8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_B9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BA_ADDR 0x110089B8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BB_ADDR 0x110089B8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BC_ADDR 0x110089BC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BD_ADDR 0x110089BC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BE_ADDR 0x110089BC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BF_ADDR 0x110089BC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_BF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C0_ADDR 0x110089C0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C1_ADDR 0x110089C0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C2_ADDR 0x110089C0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C3_ADDR 0x110089C0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C4_ADDR 0x110089C4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C5_ADDR 0x110089C4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C6_ADDR 0x110089C4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C7_ADDR 0x110089C4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C8_ADDR 0x110089C8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C9_ADDR 0x110089C8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_C9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CA_ADDR 0x110089C8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CB_ADDR 0x110089C8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CC_ADDR 0x110089CC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CD_ADDR 0x110089CC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CE_ADDR 0x110089CC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CF_ADDR 0x110089CC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_CF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D0_ADDR 0x110089D0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D1_ADDR 0x110089D0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D2_ADDR 0x110089D0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D3_ADDR 0x110089D0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D4_ADDR 0x110089D4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D5_ADDR 0x110089D4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D6_ADDR 0x110089D4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D7_ADDR 0x110089D4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D8_ADDR 0x110089D8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D9_ADDR 0x110089D8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_D9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DA_ADDR 0x110089D8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DB_ADDR 0x110089D8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DC_ADDR 0x110089DC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DD_ADDR 0x110089DC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DE_ADDR 0x110089DC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DF_ADDR 0x110089DC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_DF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E0_ADDR 0x110089E0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E1_ADDR 0x110089E0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E2_ADDR 0x110089E0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E3_ADDR 0x110089E0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E4_ADDR 0x110089E4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E5_ADDR 0x110089E4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E6_ADDR 0x110089E4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E7_ADDR 0x110089E4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E8_ADDR 0x110089E8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E9_ADDR 0x110089E8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_E9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EA_ADDR 0x110089E8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EB_ADDR 0x110089E8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EC_ADDR 0x110089EC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_ED_ADDR 0x110089EC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_ED_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_ED_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EE_ADDR 0x110089EC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EF_ADDR 0x110089EC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_EF_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F0_ADDR 0x110089F0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F0_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F0_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F1_ADDR 0x110089F0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F1_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F1_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F2_ADDR 0x110089F0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F2_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F2_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F3_ADDR 0x110089F0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F3_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F3_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F4_ADDR 0x110089F4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F4_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F4_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F5_ADDR 0x110089F4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F5_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F5_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F6_ADDR 0x110089F4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F6_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F6_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F7_ADDR 0x110089F4
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F7_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F7_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F8_ADDR 0x110089F8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F8_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F8_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F9_ADDR 0x110089F8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F9_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_F9_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FA_ADDR 0x110089F8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FA_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FA_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FB_ADDR 0x110089F8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FB_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FB_BITEND 31

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FC_ADDR 0x110089FC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FC_BITSTART 0
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FC_BITEND 7

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FD_ADDR 0x110089FC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FD_BITSTART 8
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FD_BITEND 15

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FE_ADDR 0x110089FC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FE_BITSTART 16
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FE_BITEND 23

#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FF_ADDR 0x110089FC
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FF_BITSTART 24
#define HS_Standby__hdmi21_rx_edid_01__reg_01_edid_data_FF_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_edid_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_edid_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_edid_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_segment_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_segment_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_segment_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_ddcci_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_ddcci_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_ddcci_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_usr0_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_usr0_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_usr0_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_usr1_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_usr1_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_usr1_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_edid_segment_clr_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_edid_segment_clr_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_edid_segment_clr_BITEND 8

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_edid_segment_clr_auto_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_edid_segment_clr_auto_BITSTART 9
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_edid_segment_clr_auto_BITEND 9

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_edid_ADDR 0x11008A00
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_edid_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_edid_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_segment_ADDR 0x11008A04
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_segment_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_segment_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_ddcci_ADDR 0x11008A04
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_ddcci_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_ddcci_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_usr0_ADDR 0x11008A04
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_usr0_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_usr0_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_usr1_ADDR 0x11008A04
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_usr1_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_addr_usr1_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_hw_read_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_hw_read_en_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_hw_read_en_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_sw_read_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_sw_read_en_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_sw_read_en_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_segment_sw_read_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_segment_sw_read_en_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_segment_sw_read_en_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_ddcci_sw_read_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_ddcci_sw_read_en_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_ddcci_sw_read_en_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr0_sw_read_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr0_sw_read_en_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr0_sw_read_en_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr1_sw_read_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr1_sw_read_en_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr1_sw_read_en_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_sw_write_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_sw_write_en_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_edid_sw_write_en_BITEND 8

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_segment_sw_write_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_segment_sw_write_en_BITSTART 9
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_segment_sw_write_en_BITEND 9

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_ddcci_sw_write_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_ddcci_sw_write_en_BITSTART 10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_ddcci_sw_write_en_BITEND 10

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr0_sw_write_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr0_sw_write_en_BITSTART 11
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr0_sw_write_en_BITEND 11

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr1_sw_write_en_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr1_sw_write_en_BITSTART 12
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_slv_usr1_sw_write_en_BITEND 12

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_th_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_th_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_th_BITEND 20

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_req_th_ADDR 0x11008A08
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_req_th_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_req_th_BITEND 28

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2cspikesuppr_ADDR 0x11008A0C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2cspikesuppr_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2cspikesuppr_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2ctimouten_ADDR 0x11008A0C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2ctimouten_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2ctimouten_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2ctimoutcnt_ADDR 0x11008A0C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2ctimoutcnt_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2ctimoutcnt_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_standby_only_ADDR 0x11008A0C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_standby_only_BITSTART 23
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_standby_only_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_start_pulse_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_start_pulse_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_start_pulse_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_restart_pulse_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_restart_pulse_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_restart_pulse_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_stop_pulse_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_stop_pulse_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_stop_pulse_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_slv_addr_valid_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_slv_addr_valid_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_slv_addr_valid_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_wr_data_valid_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_wr_data_valid_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_wr_data_valid_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_rd_data_req_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_rd_data_req_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_rd_data_req_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_edid_segment_update_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_edid_segment_update_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_edid_segment_update_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_start_pulse_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_start_pulse_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_start_pulse_BITEND 16

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_restart_pulse_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_restart_pulse_BITSTART 17
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_restart_pulse_BITEND 17

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_stop_pulse_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_stop_pulse_BITSTART 18
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_stop_pulse_BITEND 18

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_slv_addr_valid_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_slv_addr_valid_BITSTART 19
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_slv_addr_valid_BITEND 19

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_wr_data_valid_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_wr_data_valid_BITSTART 20
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_wr_data_valid_BITEND 20

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_rd_data_req_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_rd_data_req_BITSTART 21
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_rd_data_req_BITEND 21

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_BITSTART 22
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_data_clr_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_data_clr_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_data_clr_BITEND 24

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_cnt_clr_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_cnt_clr_BITSTART 25
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_cnt_clr_BITEND 25

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_BITSTART 26
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_wr_valid_clr_BITEND 26

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_cnt_clr_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_cnt_clr_BITSTART 28
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_cnt_clr_BITEND 28

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_req_clr_ADDR 0x11008A10
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_req_clr_BITSTART 29
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_req_clr_BITEND 29

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_arblst_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_arblst_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_arblst_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_eom_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_eom_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_eom_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_error_foll_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_error_foll_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_error_foll_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_error_init_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_error_init_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_error_init_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_int_done_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_int_done_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_int_done_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_nack_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_nack_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_nack_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_wakeupctrl_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_wakeupctrl_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_wakeupctrl_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_arblst_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_arblst_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_arblst_BITEND 16

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_eom_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_eom_BITSTART 17
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_eom_BITEND 17

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_error_foll_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_error_foll_BITSTART 18
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_error_foll_BITEND 18

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_error_init_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_error_init_BITSTART 19
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_error_init_BITEND 19

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_int_done_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_int_done_BITSTART 20
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_int_done_BITEND 20

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_nack_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_nack_BITSTART 21
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_nack_BITEND 21

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_ADDR 0x11008A14
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_BITSTART 22
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_ADDR 0x11008A20
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_00_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_01_ADDR 0x11008A20
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_01_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_01_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_02_ADDR 0x11008A20
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_02_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_02_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_03_ADDR 0x11008A20
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_03_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_03_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_04_ADDR 0x11008A24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_04_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_04_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_05_ADDR 0x11008A24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_05_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_05_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_06_ADDR 0x11008A24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_06_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_06_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_07_ADDR 0x11008A24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_07_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_07_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_08_ADDR 0x11008A28
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_08_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_08_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_09_ADDR 0x11008A28
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_09_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_09_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_10_ADDR 0x11008A28
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_10_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_10_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_11_ADDR 0x11008A28
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_11_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_11_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_12_ADDR 0x11008A2C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_12_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_12_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_13_ADDR 0x11008A2C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_13_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_13_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_14_ADDR 0x11008A2C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_14_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_14_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_15_ADDR 0x11008A2C
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_15_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_15_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_16_ADDR 0x11008A30
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_16_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_16_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_17_ADDR 0x11008A30
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_17_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_17_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_18_ADDR 0x11008A30
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_18_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_18_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_19_ADDR 0x11008A30
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_19_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_19_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_20_ADDR 0x11008A34
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_20_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_20_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_21_ADDR 0x11008A34
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_21_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_21_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_22_ADDR 0x11008A34
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_22_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_22_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_23_ADDR 0x11008A34
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_23_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_ddc_i2c_rd_data_23_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_mon_sel_ADDR 0x11008A38
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_mon_sel_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__reg_01_int_mon_sel_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_mon_cnt_ADDR 0x11008A3C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_mon_cnt_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_mon_cnt_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_start_pulse_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_start_pulse_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_start_pulse_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_restart_pulse_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_restart_pulse_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_restart_pulse_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_stop_pulse_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_stop_pulse_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_stop_pulse_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_slv_addr_valid_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_slv_addr_valid_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_slv_addr_valid_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_wr_data_valid_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_wr_data_valid_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_wr_data_valid_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_rd_data_req_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_rd_data_req_BITSTART 5
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_rd_data_req_BITEND 5

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_edid_segment_update_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_edid_segment_update_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_edid_segment_update_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_arblst_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_arblst_BITSTART 7
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_arblst_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_eom_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_eom_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_eom_BITEND 8

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_error_foll_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_error_foll_BITSTART 9
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_error_foll_BITEND 9

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_error_init_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_error_init_BITSTART 10
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_error_init_BITEND 10

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_int_done_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_int_done_BITSTART 11
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_int_done_BITEND 11

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_nack_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_nack_BITSTART 12
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_nack_BITEND 12

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_wakeupctrl_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_wakeupctrl_BITSTART 13
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_int_pending_cec_wakeupctrl_BITEND 13

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_edid_segment_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_edid_segment_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_edid_segment_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_rcurstate_ADDR 0x11008A40
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_rcurstate_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_rcurstate_BITEND 27

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_edid_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_edid_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_edid_BITEND 0

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_segment_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_segment_BITSTART 1
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_segment_BITEND 1

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_ddcci_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_ddcci_BITSTART 2
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_ddcci_BITEND 2

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_usr0_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_usr0_BITSTART 3
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_usr0_BITEND 3

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_usr1_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_usr1_BITSTART 4
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_sel_slv_usr1_BITEND 4

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_valid_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_valid_BITSTART 6
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_valid_BITEND 6

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_rd_req_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_rd_req_BITSTART 7
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_rd_req_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_valid_num_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_valid_num_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_valid_num_BITEND 12

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_cnt_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_cnt_BITSTART 13
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_cnt_BITEND 17

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_rd_cnt_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_rd_cnt_BITSTART 18
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_rd_cnt_BITEND 22

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_slave_addr_ADDR 0x11008A44
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_slave_addr_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_slave_addr_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_ADDR 0x11008A48
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_00_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_01_ADDR 0x11008A48
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_01_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_01_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_02_ADDR 0x11008A48
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_02_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_02_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_03_ADDR 0x11008A48
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_03_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_03_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_04_ADDR 0x11008A4C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_04_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_04_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_05_ADDR 0x11008A4C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_05_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_05_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_06_ADDR 0x11008A4C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_06_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_06_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_07_ADDR 0x11008A4C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_07_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_07_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_08_ADDR 0x11008A50
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_08_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_08_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_09_ADDR 0x11008A50
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_09_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_09_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_10_ADDR 0x11008A50
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_10_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_10_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_11_ADDR 0x11008A50
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_11_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_11_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_12_ADDR 0x11008A54
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_12_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_12_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_13_ADDR 0x11008A54
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_13_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_13_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_14_ADDR 0x11008A54
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_14_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_14_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_15_ADDR 0x11008A54
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_15_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_15_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_16_ADDR 0x11008A58
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_16_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_16_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_17_ADDR 0x11008A58
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_17_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_17_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_18_ADDR 0x11008A58
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_18_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_18_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_19_ADDR 0x11008A58
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_19_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_19_BITEND 31

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_20_ADDR 0x11008A5C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_20_BITSTART 0
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_20_BITEND 7

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_21_ADDR 0x11008A5C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_21_BITSTART 8
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_21_BITEND 15

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_22_ADDR 0x11008A5C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_22_BITSTART 16
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_22_BITEND 23

#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_23_ADDR 0x11008A5C
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_23_BITSTART 24
#define HS_Standby__hdmi21_rx_eddc_01__regr_01_ddc_i2c_wr_data_23_BITEND 31

#define HS_Standby__standby_i2c_reg__reg_addr_ADDR 0x11009000
#define HS_Standby__standby_i2c_reg__reg_addr_BITSTART 0
#define HS_Standby__standby_i2c_reg__reg_addr_BITEND 15

#define HS_Standby__standby_i2c_reg__reg_slv_id_ADDR 0x11009000
#define HS_Standby__standby_i2c_reg__reg_slv_id_BITSTART 16
#define HS_Standby__standby_i2c_reg__reg_slv_id_BITEND 22

#define HS_Standby__standby_i2c_reg__reg_clk_en_ADDR 0x11009000
#define HS_Standby__standby_i2c_reg__reg_clk_en_BITSTART 23
#define HS_Standby__standby_i2c_reg__reg_clk_en_BITEND 23

#define HS_Standby__standby_i2c_reg__reg_start_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_start_BITSTART 0
#define HS_Standby__standby_i2c_reg__reg_start_BITEND 0

#define HS_Standby__standby_i2c_reg__reg_rw_sel_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_rw_sel_BITSTART 1
#define HS_Standby__standby_i2c_reg__reg_rw_sel_BITEND 1

#define HS_Standby__standby_i2c_reg__reg_curr_rd_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_curr_rd_BITSTART 2
#define HS_Standby__standby_i2c_reg__reg_curr_rd_BITEND 2

#define HS_Standby__standby_i2c_reg__reg_addr_length_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_addr_length_BITSTART 3
#define HS_Standby__standby_i2c_reg__reg_addr_length_BITEND 3

#define HS_Standby__standby_i2c_reg__reg_error_en_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_error_en_BITSTART 4
#define HS_Standby__standby_i2c_reg__reg_error_en_BITEND 4

#define HS_Standby__standby_i2c_reg__reg_fifo_empty_int_en_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_fifo_empty_int_en_BITSTART 5
#define HS_Standby__standby_i2c_reg__reg_fifo_empty_int_en_BITEND 5

#define HS_Standby__standby_i2c_reg__reg_fifo_full_int_en_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_fifo_full_int_en_BITSTART 6
#define HS_Standby__standby_i2c_reg__reg_fifo_full_int_en_BITEND 6

#define HS_Standby__standby_i2c_reg__reg_trans_done_int_en_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_trans_done_int_en_BITSTART 7
#define HS_Standby__standby_i2c_reg__reg_trans_done_int_en_BITEND 7

#define HS_Standby__standby_i2c_reg__reg_data_length_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_data_length_BITSTART 8
#define HS_Standby__standby_i2c_reg__reg_data_length_BITEND 15

#define HS_Standby__standby_i2c_reg__reg_busy_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_busy_BITSTART 16
#define HS_Standby__standby_i2c_reg__reg_busy_BITEND 16

#define HS_Standby__standby_i2c_reg__reg_done_out_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_done_out_BITSTART 17
#define HS_Standby__standby_i2c_reg__reg_done_out_BITEND 17

#define HS_Standby__standby_i2c_reg__reg_error_flag_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_error_flag_BITSTART 18
#define HS_Standby__standby_i2c_reg__reg_error_flag_BITEND 18

#define HS_Standby__standby_i2c_reg__reg_fifo_empty_flag_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_fifo_empty_flag_BITSTART 19
#define HS_Standby__standby_i2c_reg__reg_fifo_empty_flag_BITEND 19

#define HS_Standby__standby_i2c_reg__reg_fifo_full_flag_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_fifo_full_flag_BITSTART 20
#define HS_Standby__standby_i2c_reg__reg_fifo_full_flag_BITEND 20

#define HS_Standby__standby_i2c_reg__reg_trans_done_ADDR 0x11009004
#define HS_Standby__standby_i2c_reg__reg_trans_done_BITSTART 21
#define HS_Standby__standby_i2c_reg__reg_trans_done_BITEND 21

#define HS_Standby__standby_i2c_reg__reg_iic_txdata_ADDR 0x11009008
#define HS_Standby__standby_i2c_reg__reg_iic_txdata_BITSTART 0
#define HS_Standby__standby_i2c_reg__reg_iic_txdata_BITEND 31

#define HS_Standby__standby_i2c_reg__reg_iic_rxdata_ADDR 0x1100900C
#define HS_Standby__standby_i2c_reg__reg_iic_rxdata_BITSTART 0
#define HS_Standby__standby_i2c_reg__reg_iic_rxdata_BITEND 31

#define HS_Standby__standby_i2c_reg__reg_read_done_ADDR 0x11009010
#define HS_Standby__standby_i2c_reg__reg_read_done_BITSTART 0
#define HS_Standby__standby_i2c_reg__reg_read_done_BITEND 0

#define HS_Standby__standby_i2c_reg__reg_speed_ADDR 0x11009010
#define HS_Standby__standby_i2c_reg__reg_speed_BITSTART 8
#define HS_Standby__standby_i2c_reg__reg_speed_BITEND 19

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_ADDR 0x1100A000
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C02_TX_IRQFLAG_ADDR 0x1100A000
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C02_TX_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C02_TX_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C03_RXFSM_SOP_IRQFLAG_ADDR 0x1100A000
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C03_RXFSM_SOP_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C03_RXFSM_SOP_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_ADDR 0x1100A004
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C05_TXFSM_SOP_IRQFLAG_ADDR 0x1100A004
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C05_TXFSM_SOP_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C05_TXFSM_SOP_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C06_TXFSM_SOPP_IRQFLAG_ADDR 0x1100A004
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C06_TXFSM_SOPP_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C06_TXFSM_SOPP_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C07_RSTFSM_IRQFLAG_ADDR 0x1100A004
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C07_RSTFSM_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C07_RSTFSM_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_ADDR 0x1100A008
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C09_PE_TIMER_IRQFLAG_ADDR 0x1100A008
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C09_PE_TIMER_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C09_PE_TIMER_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0A_Reserved_for_PE_TIMER_IRQFLAG_ADDR 0x1100A008
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0A_Reserved_for_PE_TIMER_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0A_Reserved_for_PE_TIMER_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_ADDR 0x1100A008
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_ADDR 0x1100A00C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0D_IRQ_PWR_DET_ADDR 0x1100A00C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0D_IRQ_PWR_DET_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0D_IRQ_PWR_DET_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0E_IRQ_CCVOL_DET_ADDR 0x1100A00C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0E_IRQ_CCVOL_DET_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0E_IRQ_CCVOL_DET_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_ADDR 0x1100A00C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C10_Reserved_ADDR 0x1100A010
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C10_Reserved_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C10_Reserved_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C11_RX_RAW_IRQFLAG_ADDR 0x1100A010
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C11_RX_RAW_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C11_RX_RAW_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C12_TX_RAW_IRQFLAG_ADDR 0x1100A010
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C12_TX_RAW_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C12_TX_RAW_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C13_RXFSM_SOP_RAW_IRQFLAG_ADDR 0x1100A010
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C13_RXFSM_SOP_RAW_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C13_RXFSM_SOP_RAW_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C14_RXFSM_SOPP_RAW_IRQFLAG_ADDR 0x1100A014
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C14_RXFSM_SOPP_RAW_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C14_RXFSM_SOPP_RAW_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C15_TXFSM_SOP_RAW_IRQFLAG_ADDR 0x1100A014
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C15_TXFSM_SOP_RAW_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C15_TXFSM_SOP_RAW_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C16_TXFSM_SOPP_RAW_IRQFLAG_ADDR 0x1100A014
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C16_TXFSM_SOPP_RAW_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C16_TXFSM_SOPP_RAW_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C17_RSTFSM_RAW_IRQFLAG_ADDR 0x1100A014
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C17_RSTFSM_RAW_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C17_RSTFSM_RAW_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C18_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A018
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C18_PE_TIMER_RAW_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C18_PE_TIMER_RAW_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C19_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A018
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C19_PE_TIMER_RAW_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C19_PE_TIMER_RAW_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1A_Reserved_for_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A018
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1A_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1A_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1B_Reserved_for_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A018
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1B_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1B_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1C_PD_TOP_RAW_IRQFALG_ADDR 0x1100A01C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1C_PD_TOP_RAW_IRQFALG_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1C_PD_TOP_RAW_IRQFALG_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1D_IRQ_RAW_PWR_DET_ADDR 0x1100A01C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1D_IRQ_RAW_PWR_DET_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1D_IRQ_RAW_PWR_DET_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1E_IRQ_RAW_CCVOL_DET_ADDR 0x1100A01C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1E_IRQ_RAW_CCVOL_DET_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1E_IRQ_RAW_CCVOL_DET_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1F_IRQ_RAW_MISC_ADDR 0x1100A01C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1F_IRQ_RAW_MISC_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C1F_IRQ_RAW_MISC_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C3E_PD_RX_status_register_ADDR 0x1100A03C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C3E_PD_RX_status_register_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C3E_PD_RX_status_register_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C3F_PD_RX_received_SOP_type_ADDR 0x1100A03C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C3F_PD_RX_received_SOP_type_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C3F_PD_RX_received_SOP_type_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C40_PD_RX_status_register_ADDR 0x1100A040
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C40_PD_RX_status_register_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C40_PD_RX_status_register_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C41_PD_RX_Received_CRC_ADDR 0x1100A040
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C41_PD_RX_Received_CRC_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C41_PD_RX_Received_CRC_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C42_PD_RX_Received_CRC_ADDR 0x1100A040
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C42_PD_RX_Received_CRC_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C42_PD_RX_Received_CRC_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C43_PD_RX_Received_CRC_ADDR 0x1100A040
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C43_PD_RX_Received_CRC_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C43_PD_RX_Received_CRC_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C44_PD_RX_Received_CRC_ADDR 0x1100A044
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C44_PD_RX_Received_CRC_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C44_PD_RX_Received_CRC_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C45_Reserved_ADDR 0x1100A044
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C45_Reserved_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C45_Reserved_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C46_Reserved_ADDR 0x1100A044
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C46_Reserved_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C46_Reserved_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C47_Reserved_ADDR 0x1100A044
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C47_Reserved_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C47_Reserved_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C48_PD_RX_Received_MessageID_ADDR 0x1100A048
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C48_PD_RX_Received_MessageID_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C48_PD_RX_Received_MessageID_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C49_FSM_for_SOP_status_register_ADDR 0x1100A048
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C49_FSM_for_SOP_status_register_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C49_FSM_for_SOP_status_register_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4A_FSM_for_SOPP_status_register_ADDR 0x1100A048
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4A_FSM_for_SOPP_status_register_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4A_FSM_for_SOPP_status_register_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4B_TX_FSM_for_SOP_status_register_ADDR 0x1100A048
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4B_TX_FSM_for_SOP_status_register_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4B_TX_FSM_for_SOP_status_register_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4C_TX_FSM_for_SOPP_status_register_ADDR 0x1100A04C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4C_TX_FSM_for_SOPP_status_register_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4C_TX_FSM_for_SOPP_status_register_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4D_Hard_Reset_FSM_for_SOPs_state_ADDR 0x1100A04C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4D_Hard_Reset_FSM_for_SOPs_state_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4D_Hard_Reset_FSM_for_SOPs_state_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4E_PD_PHY_status_register_ADDR 0x1100A04C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4E_PD_PHY_status_register_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4E_PD_PHY_status_register_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4F_Resevered_ADDR 0x1100A04C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4F_Resevered_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C4F_Resevered_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C54_PD_TXPATH_status_register_ADDR 0x1100A054
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C54_PD_TXPATH_status_register_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C54_PD_TXPATH_status_register_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C55_PD_PHY_FSM_status_register_ADDR 0x1100A054
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C55_PD_PHY_FSM_status_register_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C55_PD_PHY_FSM_status_register_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C56_PD_TX_DATA_CRC_ADDR 0x1100A054
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C56_PD_TX_DATA_CRC_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C56_PD_TX_DATA_CRC_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C57_PD_TX_DATA_CRC_ADDR 0x1100A054
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C57_PD_TX_DATA_CRC_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C57_PD_TX_DATA_CRC_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C58_PD_TX_DATA_CRC_ADDR 0x1100A058
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C58_PD_TX_DATA_CRC_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C58_PD_TX_DATA_CRC_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C59_PD_TX_DATA_CRC_ADDR 0x1100A058
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C59_PD_TX_DATA_CRC_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C59_PD_TX_DATA_CRC_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5A_PD_TX_DATA_CRC_newc_ADDR 0x1100A058
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5A_PD_TX_DATA_CRC_newc_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5A_PD_TX_DATA_CRC_newc_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5B_PD_TX_DATA_CRC_newc_ADDR 0x1100A058
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5B_PD_TX_DATA_CRC_newc_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5B_PD_TX_DATA_CRC_newc_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5C_PE_TIMER_time_out_ADDR 0x1100A05C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5C_PE_TIMER_time_out_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5C_PE_TIMER_time_out_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5D_PE_TIMER_time_out_ADDR 0x1100A05C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5D_PE_TIMER_time_out_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5D_PE_TIMER_time_out_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5E_Reserved_ADDR 0x1100A05C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5E_Reserved_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5E_Reserved_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5F_Reserved_ADDR 0x1100A05C
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5F_Reserved_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C5F_Reserved_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_TRIM_CCSR_ADDR 0x1100A064
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_TRIM_CCSR_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_TRIM_CCSR_BITEND 4

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_CCTX_AUX_DONE_ADDR 0x1100A064
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_CCTX_AUX_DONE_BITSTART 5
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_CCTX_AUX_DONE_BITEND 5

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_SENSE_CC2A_ADDR 0x1100A064
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_SENSE_CC2A_BITSTART 6
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C64_SENSE_CC2A_BITEND 6

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C65_SENSE_PULSE_LEN_ADDR 0x1100A064
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C65_SENSE_PULSE_LEN_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C65_SENSE_PULSE_LEN_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C66_SENSE_CYCLE_NUM_ADDR 0x1100A064
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C66_SENSE_CYCLE_NUM_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C66_SENSE_CYCLE_NUM_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C67_reserved_ADDR 0x1100A064
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C67_reserved_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C67_reserved_BITEND 31

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C80_cc_power_detect_ADDR 0x1100A080
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C80_cc_power_detect_BITSTART 0
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C80_cc_power_detect_BITEND 7

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C81_cc_connection_detect_ADDR 0x1100A080
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C81_cc_connection_detect_BITSTART 8
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C81_cc_connection_detect_BITEND 15

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C82_cc_connection_detect_ADDR 0x1100A080
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C82_cc_connection_detect_BITSTART 16
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C82_cc_connection_detect_BITEND 23

#define HS_Standby__usb_typec_0_00__REG_00_RO_2C83_cc_plug_detect_ADDR 0x1100A080
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C83_cc_plug_detect_BITSTART 24
#define HS_Standby__usb_typec_0_00__REG_00_RO_2C83_cc_plug_detect_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_RX_clock_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_RX_clock_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_RX_clock_BITEND 8

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_SOP_FSM_clock_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_SOP_FSM_clock_BITSTART 9
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_SOP_FSM_clock_BITEND 9

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_SOPP_FSM_clock_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_SOPP_FSM_clock_BITSTART 10
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_SOPP_FSM_clock_BITEND 10

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_Reset_FSM_clock_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_Reset_FSM_clock_BITSTART 11
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_Reset_FSM_clock_BITEND 11

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_PE_Timer_clock_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_PE_Timer_clock_BITSTART 12
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_PE_Timer_clock_BITEND 12

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_CC_TX_Auxiliary_logic_clock_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_CC_TX_Auxiliary_logic_clock_BITSTART 13
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_CC_TX_Auxiliary_logic_clock_BITEND 13

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_TX_clock_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_TX_clock_BITSTART 14
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_TX_clock_BITEND 14

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_Clock_Gating_Control_for_PD_TX_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_Clock_Gating_Control_for_PD_TX_BITSTART 15
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D01_Clock_Gating_Control_for_PD_TX_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D02_RX_SOP_packet_type_setting_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D02_RX_SOP_packet_type_setting_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D02_RX_SOP_packet_type_setting_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D03_RXOS_MPAT1_ADDR 0x1100A100
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D03_RXOS_MPAT1_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D03_RXOS_MPAT1_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D04_RXOS_MPAT2_ADDR 0x1100A104
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D04_RXOS_MPAT2_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D04_RXOS_MPAT2_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D05_RXOS_MPAT3_ADDR 0x1100A104
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D05_RXOS_MPAT3_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D05_RXOS_MPAT3_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D06_RXOS_MPAT4_ADDR 0x1100A104
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D06_RXOS_MPAT4_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D06_RXOS_MPAT4_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D07_TX_SOP_packet_type_setting_ADDR 0x1100A104
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D07_TX_SOP_packet_type_setting_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D07_TX_SOP_packet_type_setting_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D08_TXOS_MPAT1_ADDR 0x1100A108
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D08_TXOS_MPAT1_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D08_TXOS_MPAT1_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D09_TXOS_MPAT2_ADDR 0x1100A108
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D09_TXOS_MPAT2_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D09_TXOS_MPAT2_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0A_TXOS_MPAT3_ADDR 0x1100A108
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0A_TXOS_MPAT3_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0A_TXOS_MPAT3_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0B_TXOS_MPAT4_ADDR 0x1100A108
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0B_TXOS_MPAT4_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0B_TXOS_MPAT4_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_IDLE_counter_length_bit_8_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_IDLE_counter_length_bit_8_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_IDLE_counter_length_bit_8_BITEND 0

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_IDLE_counter_clear_enable_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_IDLE_counter_clear_enable_BITSTART 1
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_IDLE_counter_clear_enable_BITEND 1

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_SOP_Search_Window_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_SOP_Search_Window_BITSTART 2
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0C_SOP_Search_Window_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0D_IDLE_counter_length_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0D_IDLE_counter_length_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0D_IDLE_counter_length_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0E_CC_Spike_Filter_counter_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0E_CC_Spike_Filter_counter_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0E_CC_Spike_Filter_counter_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_CRC_check_bypass_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_CRC_check_bypass_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_CRC_check_bypass_BITEND 24

#define HS_Standby__usb_typec_1_00__00_PREDISCTX_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__00_PREDISCTX_BITSTART 25
#define HS_Standby__usb_typec_1_00__00_PREDISCTX_BITEND 26

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_RX_FIFO_reset_control_by_HW_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_RX_FIFO_reset_control_by_HW_BITSTART 27
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_RX_FIFO_reset_control_by_HW_BITEND 27

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_BMC_UI_Average_Delay_count_ADDR 0x1100A10C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_BMC_UI_Average_Delay_count_BITSTART 28
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D0F_BMC_UI_Average_Delay_count_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D10_reserved_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D10_reserved_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D10_reserved_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_TXEN_enable_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_TXEN_enable_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_TXEN_enable_BITEND 8

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_RXEN_enable_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_RXEN_enable_BITSTART 9
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_RXEN_enable_BITEND 9

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_enable_control_mode_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_enable_control_mode_BITSTART 10
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_CC_enable_control_mode_BITEND 10

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_reserved_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_reserved_BITSTART 11
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_reserved_BITEND 13

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_Disable_TXHIZ_to_block_CCIN_RX_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_Disable_TXHIZ_to_block_CCIN_RX_BITSTART 14
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_Disable_TXHIZ_to_block_CCIN_RX_BITEND 14

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_all_K_code_are_same_flag_set_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_all_K_code_are_same_flag_set_BITSTART 15
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D11_all_K_code_are_same_flag_set_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D12_PD_TX_message_control_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D12_PD_TX_message_control_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D12_PD_TX_message_control_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D13_PD_RX_message_control_ADDR 0x1100A110
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D13_PD_RX_message_control_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D13_PD_RX_message_control_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D14_PD_TX_message_data_buffer_control_ADDR 0x1100A114
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D14_PD_TX_message_data_buffer_control_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D14_PD_TX_message_data_buffer_control_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D15_MSG_TX_BITRATE_ADDR 0x1100A114
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D15_MSG_TX_BITRATE_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D15_MSG_TX_BITRATE_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D16_MSG_TX_CRC_FW_ADDR 0x1100A114
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D16_MSG_TX_CRC_FW_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D16_MSG_TX_CRC_FW_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D17_MSG_TX_CRC_FW_ADDR 0x1100A114
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D17_MSG_TX_CRC_FW_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D17_MSG_TX_CRC_FW_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D18_MSG_TX_CRC_FW_ADDR 0x1100A118
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D18_MSG_TX_CRC_FW_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D18_MSG_TX_CRC_FW_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D19_MSG_TX_CRC_FW_ADDR 0x1100A118
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D19_MSG_TX_CRC_FW_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D19_MSG_TX_CRC_FW_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_CHEN_CTL_BPRX_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_CHEN_CTL_BPRX_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_CHEN_CTL_BPRX_BITEND 0

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_CHEN_CTL_BPTX_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_CHEN_CTL_BPTX_BITSTART 1
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_CHEN_CTL_BPTX_BITEND 1

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_TX_IRQ_MODE_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_TX_IRQ_MODE_BITSTART 2
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_TX_IRQ_MODE_BITEND 2

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_reserved_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_reserved_BITSTART 3
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3C_reserved_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_set_to_Cable_plug_mode_if_cable_plug_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_set_to_Cable_plug_mode_if_cable_plug_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_set_to_Cable_plug_mode_if_cable_plug_BITEND 8

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_Cable_plug_mode_for_SOP_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_Cable_plug_mode_for_SOP_BITSTART 9
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_Cable_plug_mode_for_SOP_BITEND 9

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_Cable_plug_mode_for_SOPP_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_Cable_plug_mode_for_SOPP_BITSTART 10
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_Cable_plug_mode_for_SOPP_BITEND 10

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_reserved_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_reserved_BITSTART 11
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_reserved_BITEND 11

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_TX_Retry_Counter_for_SOP_SOPP_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_TX_Retry_Counter_for_SOP_SOPP_BITSTART 12
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3D_TX_Retry_Counter_for_SOP_SOPP_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_register_control_for_SOP_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_register_control_for_SOP_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_register_control_for_SOP_BITEND 16

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_select_for_SOP_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_select_for_SOP_BITSTART 17
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_select_for_SOP_BITEND 17

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_register_control_for_SOPP_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_register_control_for_SOPP_BITSTART 18
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_register_control_for_SOPP_BITEND 18

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_select_for_SOPP_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_select_for_SOPP_BITSTART 19
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_MSGID_Reset_select_for_SOPP_BITEND 19

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_Reserved_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_Reserved_BITSTART 20
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3E_Reserved_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3F_set_if_MCU_finished_HardReset_ADDR 0x1100A13C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3F_set_if_MCU_finished_HardReset_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D3F_set_if_MCU_finished_HardReset_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D44_PE_TIMER_timer_enable_ADDR 0x1100A144
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D44_PE_TIMER_timer_enable_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D44_PE_TIMER_timer_enable_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D45_PE_TIMER_timer_enable_ADDR 0x1100A144
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D45_PE_TIMER_timer_enable_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D45_PE_TIMER_timer_enable_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D46_PE_TIMER_timer_enable_ADDR 0x1100A144
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D46_PE_TIMER_timer_enable_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D46_PE_TIMER_timer_enable_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D47_PE_TIMER_timer_enable_ADDR 0x1100A144
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D47_PE_TIMER_timer_enable_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D47_PE_TIMER_timer_enable_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D48_PE_TIMER_timer_start_ADDR 0x1100A148
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D48_PE_TIMER_timer_start_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D48_PE_TIMER_timer_start_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D49_PE_TIMER_timer_start_ADDR 0x1100A148
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D49_PE_TIMER_timer_start_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D49_PE_TIMER_timer_start_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4A_PE_TIMER_timer_start_ADDR 0x1100A148
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4A_PE_TIMER_timer_start_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4A_PE_TIMER_timer_start_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4B_PE_TIMER_timer_start_ADDR 0x1100A148
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4B_PE_TIMER_timer_start_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4B_PE_TIMER_timer_start_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4C_PE_TIMER_timer_stop_ADDR 0x1100A14C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4C_PE_TIMER_timer_stop_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4C_PE_TIMER_timer_stop_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4D_PE_TIMER_timer_stop_ADDR 0x1100A14C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4D_PE_TIMER_timer_stop_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4D_PE_TIMER_timer_stop_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4E_PE_TIMER_timer_stop_ADDR 0x1100A14C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4E_PE_TIMER_timer_stop_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4E_PE_TIMER_timer_stop_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4F_PE_TIMER_timer_stop_ADDR 0x1100A14C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4F_PE_TIMER_timer_stop_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D4F_PE_TIMER_timer_stop_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D50_PE_TIMER_timeout_value_ADDR 0x1100A150
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D50_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D50_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D51_PE_TIMER_timeout_value_ADDR 0x1100A150
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D51_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D51_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D52_PE_TIMER_timeout_value_ADDR 0x1100A150
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D52_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D52_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D53_PE_TIMER_timeout_value_ADDR 0x1100A150
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D53_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D53_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D54_PE_TIMER_timeout_value_ADDR 0x1100A154
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D54_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D54_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D55_PE_TIMER_timeout_value_ADDR 0x1100A154
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D55_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D55_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D56_PE_TIMER_timeout_value_ADDR 0x1100A154
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D56_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D56_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D57_PE_TIMER_timeout_value_ADDR 0x1100A154
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D57_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D57_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D58_PE_TIMER_timeout_value_ADDR 0x1100A158
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D58_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D58_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D59_PE_TIMER_timeout_value_ADDR 0x1100A158
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D59_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D59_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5A_PE_TIMER_timeout_value_ADDR 0x1100A158
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5A_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5A_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5B_PE_TIMER_timeout_value_ADDR 0x1100A158
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5B_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5B_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5C_PE_TIMER_timeout_value_ADDR 0x1100A15C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5C_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5C_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5D_PE_TIMER_timeout_value_ADDR 0x1100A15C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5D_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5D_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5E_PE_TIMER_timeout_value_ADDR 0x1100A15C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5E_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5E_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5F_PE_TIMER_timeout_value_ADDR 0x1100A15C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5F_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D5F_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D60_PE_TIMER_timeout_value_ADDR 0x1100A160
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D60_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D60_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D61_PE_TIMER_timeout_value_ADDR 0x1100A160
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D61_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D61_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D62_PE_TIMER_timeout_value_ADDR 0x1100A160
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D62_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D62_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D63_PE_TIMER_timeout_value_ADDR 0x1100A160
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D63_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D63_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D64_PE_TIMER_timeout_value_ADDR 0x1100A164
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D64_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D64_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D65_PE_TIMER_timeout_value_ADDR 0x1100A164
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D65_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D65_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D66_PE_TIMER_timeout_value_ADDR 0x1100A164
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D66_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D66_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D67_PE_TIMER_timeout_value_ADDR 0x1100A164
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D67_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D67_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D68_PE_TIMER_timeout_value_ADDR 0x1100A168
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D68_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D68_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D69_PE_TIMER_timeout_value_ADDR 0x1100A168
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D69_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D69_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D6A_PE_TIMER_timeout_value_ADDR 0x1100A168
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D6A_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D6A_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D6B_PE_TIMER_timeout_value_ADDR 0x1100A168
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D6B_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D6B_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D80_PE_TIMER_timeout_value_ADDR 0x1100A180
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D80_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D80_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_ADDR 0x1100A180
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D82_PD_TX_IRQ_Mask_ADDR 0x1100A180
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D82_PD_TX_IRQ_Mask_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D82_PD_TX_IRQ_Mask_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_ADDR 0x1100A180
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D84_PD_RX_FSM_SOPP_IRQ_Mask_ADDR 0x1100A184
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D84_PD_RX_FSM_SOPP_IRQ_Mask_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D84_PD_RX_FSM_SOPP_IRQ_Mask_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D85_PD_TX_FSM_SOP_IRQ_Mask_ADDR 0x1100A184
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D85_PD_TX_FSM_SOP_IRQ_Mask_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D85_PD_TX_FSM_SOP_IRQ_Mask_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D86_PD_TX_FSM_SOPP_IRQ_Mask_ADDR 0x1100A184
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D86_PD_TX_FSM_SOPP_IRQ_Mask_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D86_PD_TX_FSM_SOPP_IRQ_Mask_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D87_PD_Reset_FSM_IRQ_Mask_ADDR 0x1100A184
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D87_PD_Reset_FSM_IRQ_Mask_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D87_PD_Reset_FSM_IRQ_Mask_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D88_PE_TIMER_IRQ_Mask_ADDR 0x1100A188
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D88_PE_TIMER_IRQ_Mask_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D88_PE_TIMER_IRQ_Mask_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D89_PE_TIMER_IRQ_Mask_ADDR 0x1100A188
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D89_PE_TIMER_IRQ_Mask_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D89_PE_TIMER_IRQ_Mask_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8A_PE_TIMER_IRQ_Mask_ADDR 0x1100A188
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8A_PE_TIMER_IRQ_Mask_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8A_PE_TIMER_IRQ_Mask_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8B_PE_TIMER_IRQ_Mask_ADDR 0x1100A188
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8B_PE_TIMER_IRQ_Mask_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8B_PE_TIMER_IRQ_Mask_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8C_USBPD_MISC_IRQ_Mask_ADDR 0x1100A18C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8C_USBPD_MISC_IRQ_Mask_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8C_USBPD_MISC_IRQ_Mask_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8D_Reserved_ADDR 0x1100A18C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8D_Reserved_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8D_Reserved_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8E_Reserved_ADDR 0x1100A18C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8E_Reserved_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8E_Reserved_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8F_Reserved_ADDR 0x1100A18C
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8F_Reserved_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D8F_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_START_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_START_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_START_BITEND 0

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_STOP_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_STOP_BITSTART 1
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_STOP_BITEND 1

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_EN_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_EN_BITSTART 2
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_CCTX_AUX_EN_BITEND 2

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_Reserved_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_Reserved_BITSTART 3
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D90_Reserved_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D91_TRIM_INITIAL_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D91_TRIM_INITIAL_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D91_TRIM_INITIAL_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D92_TRIM_DOWN_LIMIT_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D92_TRIM_DOWN_LIMIT_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D92_TRIM_DOWN_LIMIT_BITEND 20

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D92_TRIM_WINDOW_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D92_TRIM_WINDOW_BITSTART 21
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D92_TRIM_WINDOW_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_TRIM_STEP_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_TRIM_STEP_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_TRIM_STEP_BITEND 26

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_ADJUST_DIR_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_ADJUST_DIR_BITSTART 27
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_ADJUST_DIR_BITEND 27

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_Reserved_ADDR 0x1100A190
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_Reserved_BITSTART 28
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D93_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D94_PD_START_DLY_ADDR 0x1100A194
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D94_PD_START_DLY_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D94_PD_START_DLY_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D95_PD_START_DLY_ADDR 0x1100A194
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D95_PD_START_DLY_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D95_PD_START_DLY_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D96_MAX_CYCLE_NUM_ADDR 0x1100A194
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D96_MAX_CYCLE_NUM_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D96_MAX_CYCLE_NUM_BITEND 20

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D96_MAX_CYCLE_EN_ADDR 0x1100A194
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D96_MAX_CYCLE_EN_BITSTART 21
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D96_MAX_CYCLE_EN_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2D97_Reserved_ADDR 0x1100A194
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D97_Reserved_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2D97_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_MISC_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_MISC_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_MISC_BITEND 0

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_UFP_FSM_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_UFP_FSM_BITSTART 1
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_UFP_FSM_BITEND 1

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_DRP_FSM_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_DRP_FSM_BITSTART 2
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_DRP_FSM_BITEND 2

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_TERM_DET_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_TERM_DET_BITSTART 3
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_CLK_TERM_DET_BITEND 3

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_Clock_Gating_Control_for_CC_Detect_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_Clock_Gating_Control_for_CC_Detect_BITSTART 4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA0_Clock_Gating_Control_for_CC_Detect_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA1_VBUS_or_VCONN_power_detection_configuration_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA1_VBUS_or_VCONN_power_detection_configuration_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA1_VBUS_or_VCONN_power_detection_configuration_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA2_VBUS_or_VCONN_IRQ_edge_setting_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA2_VBUS_or_VCONN_IRQ_edge_setting_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA2_VBUS_or_VCONN_IRQ_edge_setting_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_FW_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_FW_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_FW_BITEND 24

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_MODE_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_MODE_BITSTART 25
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_MODE_BITEND 25

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_INV_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_INV_BITSTART 26
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_CCSEL_ANA_INV_BITEND 26

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_Reserved_ADDR 0x1100A1A0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_Reserved_BITSTART 27
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA3_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_RD_GND_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_RD_GND_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_RD_GND_BITEND 1

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_RD_CON_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_RD_CON_BITSTART 2
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_RD_CON_BITEND 3

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SWAP_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SWAP_BITSTART 4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SWAP_BITEND 4

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SEL_FW_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SEL_FW_BITSTART 5
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SEL_FW_BITEND 5

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SEL_MODE_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SEL_MODE_BITSTART 6
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_CCVOL_SEL_MODE_BITEND 6

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_DBBP_CCVOL_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_DBBP_CCVOL_BITSTART 7
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA4_DBBP_CCVOL_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_OPEN_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_OPEN_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_OPEN_BITEND 9

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_RD_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_RD_BITSTART 10
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_RD_BITEND 11

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_RA_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_RA_BITSTART 12
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA5_CCVOL_RP_RA_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA7_STATE_DIRECT_TRIG_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA7_STATE_DIRECT_TRIG_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA7_STATE_DIRECT_TRIG_BITEND 24

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA7_STATE_DIRECT_ADDR 0x1100A1A4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA7_STATE_DIRECT_BITSTART 25
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA7_STATE_DIRECT_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA8_TERR_RECOV_ADDR 0x1100A1A8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA8_TERR_RECOV_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA8_TERR_RECOV_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA9_Reserved_ADDR 0x1100A1A8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA9_Reserved_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DA9_Reserved_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAA_Debounce_attach_for_tCCDebounce_ADDR 0x1100A1A8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAA_Debounce_attach_for_tCCDebounce_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAA_Debounce_attach_for_tCCDebounce_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAB_Debounce_detach_for_tPDDebounce_ADDR 0x1100A1A8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAB_Debounce_detach_for_tPDDebounce_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAB_Debounce_detach_for_tPDDebounce_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAC_Debounce_VBUS_ON_for_tVBUSON_ADDR 0x1100A1AC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAC_Debounce_VBUS_ON_for_tVBUSON_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAC_Debounce_VBUS_ON_for_tVBUSON_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAD_Debounce_VBUS_OFF_for_tVBUSOFF_ADDR 0x1100A1AC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAD_Debounce_VBUS_OFF_for_tVBUSOFF_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAD_Debounce_VBUS_OFF_for_tVBUSOFF_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAE_Debounce_VCONN_ON_for_tVCONNON_ADDR 0x1100A1AC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAE_Debounce_VCONN_ON_for_tVCONNON_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAE_Debounce_VCONN_ON_for_tVCONNON_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAF_Debounce_VCONN_OFF_for_tVCONNOFF_ADDR 0x1100A1AC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAF_Debounce_VCONN_OFF_for_tVCONNOFF_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DAF_Debounce_VCONN_OFF_for_tVCONNOFF_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB0_reg_cc_chg_cnt_ADDR 0x1100A1B0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB0_reg_cc_chg_cnt_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB0_reg_cc_chg_cnt_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB1_reg_cc_vol_chg_thd_ADDR 0x1100A1B0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB1_reg_cc_vol_chg_thd_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB1_reg_cc_vol_chg_thd_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB2_Reserved_ADDR 0x1100A1B0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB2_Reserved_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB2_Reserved_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB3_CCDET_test_signal_index_ADDR 0x1100A1B0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB3_CCDET_test_signal_index_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB3_CCDET_test_signal_index_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB4_DRP_PERIOD_ADDR 0x1100A1B4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB4_DRP_PERIOD_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB4_DRP_PERIOD_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB5_DRP_DUTY_ADDR 0x1100A1B4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB5_DRP_DUTY_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB5_DRP_DUTY_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB6_DRP_HOLD_ADDR 0x1100A1B4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB6_DRP_HOLD_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB6_DRP_HOLD_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB7_DRP_LOCK_ADDR 0x1100A1B4
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB7_DRP_LOCK_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DB7_DRP_LOCK_BITEND 31

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCC_Reserved_ADDR 0x1100A1CC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCC_Reserved_BITSTART 0
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCC_Reserved_BITEND 7

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_ADDR 0x1100A1CC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_BITSTART 8
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_BITEND 15

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_ADDR 0x1100A1CC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITSTART 16
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITEND 23

#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCF_IRQ_mask_for_connection_detection_FSM_ADDR 0x1100A1CC
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCF_IRQ_mask_for_connection_detection_FSM_BITSTART 24
#define HS_Standby__usb_typec_1_00__REG_00_RW_2DCF_IRQ_mask_for_connection_detection_FSM_BITEND 31

#define HS_Standby__usb_typec_top_00__00_rstn_peri_ADDR 0x1100A200
#define HS_Standby__usb_typec_top_00__00_rstn_peri_BITSTART 0
#define HS_Standby__usb_typec_top_00__00_rstn_peri_BITEND 0

#define HS_Standby__usb_typec_top_00__00_rstn_ccdet_ADDR 0x1100A200
#define HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITSTART 1
#define HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITEND 1

#define HS_Standby__usb_typec_top_00__00_rstn_usbpd_ADDR 0x1100A200
#define HS_Standby__usb_typec_top_00__00_rstn_usbpd_BITSTART 2
#define HS_Standby__usb_typec_top_00__00_rstn_usbpd_BITEND 2

#define HS_Standby__usb_typec_top_00__00_SENSE2A_SEL_ADDR 0x1100A200
#define HS_Standby__usb_typec_top_00__00_SENSE2A_SEL_BITSTART 26
#define HS_Standby__usb_typec_top_00__00_SENSE2A_SEL_BITEND 26

#define HS_Standby__usb_typec_top_00__00_SENSE2A_FW_ADDR 0x1100A200
#define HS_Standby__usb_typec_top_00__00_SENSE2A_FW_BITSTART 27
#define HS_Standby__usb_typec_top_00__00_SENSE2A_FW_BITEND 27

#define HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITEND 0

#define HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITSTART 1
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITEND 1

#define HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITSTART 2
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITEND 2

#define HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITSTART 3
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITEND 3

#define HS_Standby__usb_typec_top_00__reg_00_cc1_vconn_sel_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc1_vconn_sel_BITSTART 4
#define HS_Standby__usb_typec_top_00__reg_00_cc1_vconn_sel_BITEND 4

#define HS_Standby__usb_typec_top_00__reg_00_cc2_vconn_sel_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc2_vconn_sel_BITSTART 5
#define HS_Standby__usb_typec_top_00__reg_00_cc2_vconn_sel_BITEND 5

#define HS_Standby__usb_typec_top_00__reg_00_cc1_det_2bit_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc1_det_2bit_en_BITSTART 6
#define HS_Standby__usb_typec_top_00__reg_00_cc1_det_2bit_en_BITEND 6

#define HS_Standby__usb_typec_top_00__reg_00_cc2_det_2bit_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_cc2_det_2bit_en_BITSTART 7
#define HS_Standby__usb_typec_top_00__reg_00_cc2_det_2bit_en_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rd_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rd_en_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rd_en_BITEND 8

#define HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rp_en_ADDR 0x1100A204
#define HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rp_en_BITSTART 9
#define HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rp_en_BITEND 9

#define HS_Standby__usb_typec_top_00__reg_00_power_role_state_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITEND 1

#define HS_Standby__usb_typec_top_00__reg_00_drp_preference_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_drp_preference_BITSTART 2
#define HS_Standby__usb_typec_top_00__reg_00_drp_preference_BITEND 2

#define HS_Standby__usb_typec_top_00__reg_00_self_powered_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_self_powered_BITSTART 3
#define HS_Standby__usb_typec_top_00__reg_00_self_powered_BITEND 3

#define HS_Standby__usb_typec_top_00__reg_00_accessory_support_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_accessory_support_BITSTART 4
#define HS_Standby__usb_typec_top_00__reg_00_accessory_support_BITEND 4

#define HS_Standby__usb_typec_top_00__reg_00_audio_accessory_support_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_audio_accessory_support_BITSTART 5
#define HS_Standby__usb_typec_top_00__reg_00_audio_accessory_support_BITEND 5

#define HS_Standby__usb_typec_top_00__reg_00_debug_accessory_support_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_debug_accessory_support_BITSTART 6
#define HS_Standby__usb_typec_top_00__reg_00_debug_accessory_support_BITEND 6

#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_accessory_support_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_accessory_support_BITSTART 7
#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_accessory_support_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_pd_support_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_pd_support_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_pd_support_BITEND 8

#define HS_Standby__usb_typec_top_00__reg_00_try_src_support_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITSTART 9
#define HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITEND 9

#define HS_Standby__usb_typec_top_00__reg_00_try_snk_support_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_try_snk_support_BITSTART 10
#define HS_Standby__usb_typec_top_00__reg_00_try_snk_support_BITEND 10

#define HS_Standby__usb_typec_top_00__reg_00_vbus_operating_mode_ADDR 0x1100A208
#define HS_Standby__usb_typec_top_00__reg_00_vbus_operating_mode_BITSTART 11
#define HS_Standby__usb_typec_top_00__reg_00_vbus_operating_mode_BITEND 11

#define HS_Standby__usb_typec_top_00__reg_00_vbus_on_thd_ADDR 0x1100A210
#define HS_Standby__usb_typec_top_00__reg_00_vbus_on_thd_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_vbus_on_thd_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_vbus_off_thd_ADDR 0x1100A210
#define HS_Standby__usb_typec_top_00__reg_00_vbus_off_thd_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_vbus_off_thd_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_vconn_on_thd_ADDR 0x1100A214
#define HS_Standby__usb_typec_top_00__reg_00_vconn_on_thd_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_vconn_on_thd_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_vconn_off_thd_ADDR 0x1100A214
#define HS_Standby__usb_typec_top_00__reg_00_vconn_off_thd_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_vconn_off_thd_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_vsink_disconnect_vol_ADDR 0x1100A218
#define HS_Standby__usb_typec_top_00__reg_00_vsink_disconnect_vol_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_vsink_disconnect_vol_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_vsink_disconnect_pd_vol_ADDR 0x1100A218
#define HS_Standby__usb_typec_top_00__reg_00_vsink_disconnect_pd_vol_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_vsink_disconnect_pd_vol_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_vsafe0v_ADDR 0x1100A218
#define HS_Standby__usb_typec_top_00__reg_00_vsafe0v_BITSTART 16
#define HS_Standby__usb_typec_top_00__reg_00_vsafe0v_BITEND 23

#define HS_Standby__usb_typec_top_00__reg_00_vvconn_disconnect_vol_ADDR 0x1100A218
#define HS_Standby__usb_typec_top_00__reg_00_vvconn_disconnect_vol_BITSTART 24
#define HS_Standby__usb_typec_top_00__reg_00_vvconn_disconnect_vol_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_vvconn_discharge_vol_ADDR 0x1100A21C
#define HS_Standby__usb_typec_top_00__reg_00_vvconn_discharge_vol_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_vvconn_discharge_vol_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_vrd_usb_vol_ADDR 0x1100A21C
#define HS_Standby__usb_typec_top_00__reg_00_vrd_usb_vol_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_vrd_usb_vol_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_ra_threshold_ADDR 0x1100A220
#define HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_rd_threshold_ADDR 0x1100A220
#define HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_ADDR 0x1100A220
#define HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITSTART 16
#define HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITEND 23

#define HS_Standby__usb_typec_top_00__reg_00_cc_adc_in_db_ADDR 0x1100A220
#define HS_Standby__usb_typec_top_00__reg_00_cc_adc_in_db_BITSTART 24
#define HS_Standby__usb_typec_top_00__reg_00_cc_adc_in_db_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_delay_cnt_ADDR 0x1100A224
#define HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_typec_vbus_value_ADDR 0x1100A228
#define HS_Standby__usb_typec_top_00__reg_00_typec_vbus_value_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_typec_vbus_value_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_typec_vbus_sel_ADDR 0x1100A228
#define HS_Standby__usb_typec_top_00__reg_00_typec_vbus_sel_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_typec_vbus_sel_BITEND 8

#define HS_Standby__usb_typec_top_00__reg_00_clk_freq_ADDR 0x1100A230
#define HS_Standby__usb_typec_top_00__reg_00_clk_freq_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_clk_freq_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_terror_recovery_ADDR 0x1100A230
#define HS_Standby__usb_typec_top_00__reg_00_terror_recovery_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_terror_recovery_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_tccdebounce_ADDR 0x1100A230
#define HS_Standby__usb_typec_top_00__reg_00_tccdebounce_BITSTART 16
#define HS_Standby__usb_typec_top_00__reg_00_tccdebounce_BITEND 23

#define HS_Standby__usb_typec_top_00__reg_00_tpddebounce_ADDR 0x1100A230
#define HS_Standby__usb_typec_top_00__reg_00_tpddebounce_BITSTART 24
#define HS_Standby__usb_typec_top_00__reg_00_tpddebounce_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_ttryccdebounce_ADDR 0x1100A234
#define HS_Standby__usb_typec_top_00__reg_00_ttryccdebounce_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_ttryccdebounce_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_tdrp_ADDR 0x1100A234
#define HS_Standby__usb_typec_top_00__reg_00_tdrp_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_tdrp_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_dcsrc_drp_ADDR 0x1100A234
#define HS_Standby__usb_typec_top_00__reg_00_dcsrc_drp_BITSTART 16
#define HS_Standby__usb_typec_top_00__reg_00_dcsrc_drp_BITEND 23

#define HS_Standby__usb_typec_top_00__reg_00_tdrptry_ADDR 0x1100A234
#define HS_Standby__usb_typec_top_00__reg_00_tdrptry_BITSTART 24
#define HS_Standby__usb_typec_top_00__reg_00_tdrptry_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_tdrptrywait_ADDR 0x1100A238
#define HS_Standby__usb_typec_top_00__reg_00_tdrptrywait_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_tdrptrywait_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_ttrytimeout_ADDR 0x1100A238
#define HS_Standby__usb_typec_top_00__reg_00_ttrytimeout_BITSTART 16
#define HS_Standby__usb_typec_top_00__reg_00_ttrytimeout_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_cmd_direct_ADDR 0x1100A23C
#define HS_Standby__usb_typec_top_00__reg_00_cmd_direct_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_cmd_direct_BITEND 4

#define HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_ADDR 0x1100A23C
#define HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_BITSTART 5
#define HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_BITEND 6

#define HS_Standby__usb_typec_top_00__reg_00_source_vconn_supply_ADDR 0x1100A23C
#define HS_Standby__usb_typec_top_00__reg_00_source_vconn_supply_BITSTART 7
#define HS_Standby__usb_typec_top_00__reg_00_source_vconn_supply_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_oriention_required_ADDR 0x1100A23C
#define HS_Standby__usb_typec_top_00__reg_00_oriention_required_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_oriention_required_BITEND 8

#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_acc_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_acc_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_acc_BITEND 0

#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_dev_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_dev_BITSTART 1
#define HS_Standby__usb_typec_top_00__reg_00_vconn_powered_dev_BITEND 1

#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_inflow_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_inflow_BITSTART 2
#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_inflow_BITEND 2

#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_rdy_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_rdy_BITSTART 3
#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_rdy_BITEND 3

#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_accept_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_accept_BITSTART 4
#define HS_Standby__usb_typec_top_00__reg_00_pr_swap_accept_BITEND 4

#define HS_Standby__usb_typec_top_00__reg_00_drp_toggle_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_drp_toggle_BITSTART 5
#define HS_Standby__usb_typec_top_00__reg_00_drp_toggle_BITEND 5

#define HS_Standby__usb_typec_top_00__reg_00_attached_vconn_powered_acc_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_attached_vconn_powered_acc_BITSTART 6
#define HS_Standby__usb_typec_top_00__reg_00_attached_vconn_powered_acc_BITEND 6

#define HS_Standby__usb_typec_top_00__reg_00_attached_vconn_powered_dev_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_attached_vconn_powered_dev_BITSTART 7
#define HS_Standby__usb_typec_top_00__reg_00_attached_vconn_powered_dev_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_dev_enter_alternate_success_ADDR 0x1100A240
#define HS_Standby__usb_typec_top_00__reg_00_dev_enter_alternate_success_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_dev_enter_alternate_success_BITEND 8

#define HS_Standby__usb_typec_top_00__regr_00_vbus_value_ADDR 0x1100A244
#define HS_Standby__usb_typec_top_00__regr_00_vbus_value_BITSTART 0
#define HS_Standby__usb_typec_top_00__regr_00_vbus_value_BITEND 7

#define HS_Standby__usb_typec_top_00__regr_00_vconn_value_ADDR 0x1100A244
#define HS_Standby__usb_typec_top_00__regr_00_vconn_value_BITSTART 16
#define HS_Standby__usb_typec_top_00__regr_00_vconn_value_BITEND 27

#define HS_Standby__usb_typec_top_00__regr_00_cc1_adc_in_ADDR 0x1100A248
#define HS_Standby__usb_typec_top_00__regr_00_cc1_adc_in_BITSTART 0
#define HS_Standby__usb_typec_top_00__regr_00_cc1_adc_in_BITEND 11

#define HS_Standby__usb_typec_top_00__regr_00_cc2_adc_in_ADDR 0x1100A248
#define HS_Standby__usb_typec_top_00__regr_00_cc2_adc_in_BITSTART 16
#define HS_Standby__usb_typec_top_00__regr_00_cc2_adc_in_BITEND 27

#define HS_Standby__usb_typec_top_00__regr_00_state_c_ADDR 0x1100A24C
#define HS_Standby__usb_typec_top_00__regr_00_state_c_BITSTART 0
#define HS_Standby__usb_typec_top_00__regr_00_state_c_BITEND 4

#define HS_Standby__usb_typec_top_00__regr_00_cc_turn_on_vbus_ADDR 0x1100A24C
#define HS_Standby__usb_typec_top_00__regr_00_cc_turn_on_vbus_BITSTART 8
#define HS_Standby__usb_typec_top_00__regr_00_cc_turn_on_vbus_BITEND 8

#define HS_Standby__usb_typec_top_00__regr_00_cc1_turn_on_vconn_ADDR 0x1100A24C
#define HS_Standby__usb_typec_top_00__regr_00_cc1_turn_on_vconn_BITSTART 9
#define HS_Standby__usb_typec_top_00__regr_00_cc1_turn_on_vconn_BITEND 9

#define HS_Standby__usb_typec_top_00__regr_00_cc2_turn_on_vconn_ADDR 0x1100A24C
#define HS_Standby__usb_typec_top_00__regr_00_cc2_turn_on_vconn_BITSTART 10
#define HS_Standby__usb_typec_top_00__regr_00_cc2_turn_on_vconn_BITEND 10

#define HS_Standby__usb_typec_top_00__regr_00_cc1_resistance_ADDR 0x1100A24C
#define HS_Standby__usb_typec_top_00__regr_00_cc1_resistance_BITSTART 11
#define HS_Standby__usb_typec_top_00__regr_00_cc1_resistance_BITEND 13

#define HS_Standby__usb_typec_top_00__regr_00_cc2_resistance_ADDR 0x1100A24C
#define HS_Standby__usb_typec_top_00__regr_00_cc2_resistance_BITSTART 14
#define HS_Standby__usb_typec_top_00__regr_00_cc2_resistance_BITEND 16

#define HS_Standby__usb_typec_top_00__reg_00_res_en_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_res_en_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_res_en_BITEND 0

#define HS_Standby__usb_typec_top_00__reg_00_res_seta_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_res_seta_BITSTART 1
#define HS_Standby__usb_typec_top_00__reg_00_res_seta_BITEND 1

#define HS_Standby__usb_typec_top_00__reg_00_res_setb_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_res_setb_BITSTART 2
#define HS_Standby__usb_typec_top_00__reg_00_res_setb_BITEND 2

#define HS_Standby__usb_typec_top_00__reg_00_aux_pn_set_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_aux_pn_set_BITSTART 3
#define HS_Standby__usb_typec_top_00__reg_00_aux_pn_set_BITEND 3

#define HS_Standby__usb_typec_top_00__reg_00_cc1_rd_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rd_BITSTART 4
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rd_BITEND 4

#define HS_Standby__usb_typec_top_00__reg_00_cc2_rd_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rd_BITSTART 5
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rd_BITEND 5

#define HS_Standby__usb_typec_top_00__reg_00_cc1_von_sw_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc1_von_sw_BITSTART 6
#define HS_Standby__usb_typec_top_00__reg_00_cc1_von_sw_BITEND 6

#define HS_Standby__usb_typec_top_00__reg_00_cc2_von_sw_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc2_von_sw_BITSTART 7
#define HS_Standby__usb_typec_top_00__reg_00_cc2_von_sw_BITEND 7

#define HS_Standby__usb_typec_top_00__reg_00_discha_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_discha_BITSTART 8
#define HS_Standby__usb_typec_top_00__reg_00_discha_BITEND 8

#define HS_Standby__usb_typec_top_00__reg_00_vbus_pmu_en_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_vbus_pmu_en_BITSTART 9
#define HS_Standby__usb_typec_top_00__reg_00_vbus_pmu_en_BITEND 9

#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_BITSTART 10
#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_BITEND 10

#define HS_Standby__usb_typec_top_00__reg_00_cc1_disable_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc1_disable_BITSTART 11
#define HS_Standby__usb_typec_top_00__reg_00_cc1_disable_BITEND 12

#define HS_Standby__usb_typec_top_00__reg_00_cc2_disable_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc2_disable_BITSTART 13
#define HS_Standby__usb_typec_top_00__reg_00_cc2_disable_BITEND 14

#define HS_Standby__usb_typec_top_00__reg_00_cc1_tx_bmc_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc1_tx_bmc_BITSTART 15
#define HS_Standby__usb_typec_top_00__reg_00_cc1_tx_bmc_BITEND 16

#define HS_Standby__usb_typec_top_00__reg_00_cc2_tx_bmc_ADDR 0x1100A250
#define HS_Standby__usb_typec_top_00__reg_00_cc2_tx_bmc_BITSTART 17
#define HS_Standby__usb_typec_top_00__reg_00_cc2_tx_bmc_BITEND 18

#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_drp_noreal_chip_ADDR 0x1100A254
#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_drp_noreal_chip_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_drp_noreal_chip_BITEND 0

#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_drp_real_chip_ADDR 0x1100A254
#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_drp_real_chip_BITSTART 1
#define HS_Standby__usb_typec_top_00__reg_00_cc_rp_en_drp_real_chip_BITEND 1

#define HS_Standby__usb_typec_top_00__reg_00_pattern_en_ADDR 0x1100A260
#define HS_Standby__usb_typec_top_00__reg_00_pattern_en_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_pattern_en_BITEND 0

#define HS_Standby__usb_typec_top_00__reg_00_unuse0_ADDR 0x1100A2A0
#define HS_Standby__usb_typec_top_00__reg_00_unuse0_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_unuse0_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_unuse1_ADDR 0x1100A2A4
#define HS_Standby__usb_typec_top_00__reg_00_unuse1_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_unuse1_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_unuse2_ADDR 0x1100A2A8
#define HS_Standby__usb_typec_top_00__reg_00_unuse2_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_unuse2_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_pd_bg_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_pd_bg_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_pd_bg_BITEND 0

#define HS_Standby__usb_typec_top_00__reg_00_pd_bginr_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_pd_bginr_BITSTART 1
#define HS_Standby__usb_typec_top_00__reg_00_pd_bginr_BITEND 1

#define HS_Standby__usb_typec_top_00__reg_00_sw_datalen_en_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_sw_datalen_en_BITSTART 2
#define HS_Standby__usb_typec_top_00__reg_00_sw_datalen_en_BITEND 2

#define HS_Standby__usb_typec_top_00__reg_00_sw_datalen_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_sw_datalen_BITSTART 4
#define HS_Standby__usb_typec_top_00__reg_00_sw_datalen_BITEND 13

#define HS_Standby__usb_typec_top_00__reg_00_sw_ctr_extendmsg_en_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_sw_ctr_extendmsg_en_BITSTART 14
#define HS_Standby__usb_typec_top_00__reg_00_sw_ctr_extendmsg_en_BITEND 14

#define HS_Standby__usb_typec_top_00__reg_00_discard_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_discard_BITSTART 15
#define HS_Standby__usb_typec_top_00__reg_00_discard_BITEND 15

#define HS_Standby__usb_typec_top_00__reg_00_spikesize_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_spikesize_BITSTART 16
#define HS_Standby__usb_typec_top_00__reg_00_spikesize_BITEND 20

#define HS_Standby__usb_typec_top_00__reg_00_delta_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_delta_BITSTART 24
#define HS_Standby__usb_typec_top_00__reg_00_delta_BITEND 28

#define HS_Standby__usb_typec_top_00__reg_00_cc1_rprd_keep_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rprd_keep_BITSTART 29
#define HS_Standby__usb_typec_top_00__reg_00_cc1_rprd_keep_BITEND 29

#define HS_Standby__usb_typec_top_00__reg_00_cc2_rprd_keep_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rprd_keep_BITSTART 30
#define HS_Standby__usb_typec_top_00__reg_00_cc2_rprd_keep_BITEND 30

#define HS_Standby__usb_typec_top_00__reg_00_cc_state_keep_ADDR 0x1100A2AC
#define HS_Standby__usb_typec_top_00__reg_00_cc_state_keep_BITSTART 31
#define HS_Standby__usb_typec_top_00__reg_00_cc_state_keep_BITEND 31

#define HS_Standby__usb_typec_top_00__reg_00_msg_recv_irq_fake_ADDR 0x1100A2B0
#define HS_Standby__usb_typec_top_00__reg_00_msg_recv_irq_fake_BITSTART 0
#define HS_Standby__usb_typec_top_00__reg_00_msg_recv_irq_fake_BITEND 0

#define HS_Standby__usb_typec_top_00__reg_00_channel_busy_irq_fake_ADDR 0x1100A2B0
#define HS_Standby__usb_typec_top_00__reg_00_channel_busy_irq_fake_BITSTART 1
#define HS_Standby__usb_typec_top_00__reg_00_channel_busy_irq_fake_BITEND 1

#define HS_Standby__usb_typec_top_00__reg_00_preamble_det_irq_fake_ADDR 0x1100A2B0
#define HS_Standby__usb_typec_top_00__reg_00_preamble_det_irq_fake_BITSTART 2
#define HS_Standby__usb_typec_top_00__reg_00_preamble_det_irq_fake_BITEND 2

#define HS_Standby__usb_typec_top_00__reg_00_dfp_attach_chg_irq_fake_ADDR 0x1100A2B0
#define HS_Standby__usb_typec_top_00__reg_00_dfp_attach_chg_irq_fake_BITSTART 3
#define HS_Standby__usb_typec_top_00__reg_00_dfp_attach_chg_irq_fake_BITEND 3

#define HS_Standby__usb_typec_top_00__reg_00_ufp_attach_chg_irq_fake_ADDR 0x1100A2B0
#define HS_Standby__usb_typec_top_00__reg_00_ufp_attach_chg_irq_fake_BITSTART 4
#define HS_Standby__usb_typec_top_00__reg_00_ufp_attach_chg_irq_fake_BITEND 4

#define HS_Standby__usb_typec_top_00__reg_00_ufp_attach_irq_fake_ADDR 0x1100A2B0
#define HS_Standby__usb_typec_top_00__reg_00_ufp_attach_irq_fake_BITSTART 5
#define HS_Standby__usb_typec_top_00__reg_00_ufp_attach_irq_fake_BITEND 5

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_en_ADDR 0x1100A300
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_en_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_en_BITEND 0

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_pat_sel_ADDR 0x1100A300
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_pat_sel_BITSTART 1
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_pat_sel_BITEND 4

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_precoder_en_ADDR 0x1100A300
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_precoder_en_BITSTART 5
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_precoder_en_BITEND 5

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_gray_coding_value_ADDR 0x1100A300
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_gray_coding_value_BITSTART 6
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_gray_coding_value_BITEND 13

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_0_ADDR 0x1100A304
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_0_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_0_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_1_ADDR 0x1100A308
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_1_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_1_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_2_ADDR 0x1100A30C
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_2_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_2_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_3_ADDR 0x1100A310
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_3_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_3_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_4_ADDR 0x1100A314
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_4_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data0_4_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_0_ADDR 0x1100A318
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_0_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_0_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_1_ADDR 0x1100A31C
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_1_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_1_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_2_ADDR 0x1100A320
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_2_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_2_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_3_ADDR 0x1100A324
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_3_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_3_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_4_ADDR 0x1100A328
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_4_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data1_4_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_0_ADDR 0x1100A32C
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_0_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_0_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_1_ADDR 0x1100A330
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_1_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_1_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_2_ADDR 0x1100A334
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_2_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_2_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_3_ADDR 0x1100A338
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_3_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_3_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_4_ADDR 0x1100A33C
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_4_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_tx_prbs_data2_4_BITEND 31

#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_en_ADDR 0x1100A350
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_en_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_en_BITEND 0

#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_mon_sel_ADDR 0x1100A350
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_mon_sel_BITSTART 8
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_mon_sel_BITEND 9

#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_pat_sel_ADDR 0x1100A354
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_pat_sel_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_pat_sel_BITEND 3

#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_ucnt_time_ADDR 0x1100A354
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_ucnt_time_BITSTART 8
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_ucnt_time_BITEND 17

#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_mcnt_time_ADDR 0x1100A354
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_mcnt_time_BITSTART 18
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_mcnt_time_BITEND 27

#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_match_sel_ADDR 0x1100A354
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_match_sel_BITSTART 28
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_match_sel_BITEND 29

#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_match_thd_ADDR 0x1100A358
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_match_thd_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__reg_00_rx_prbs_20b_match_thd_BITEND 5

#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_1us_ADDR 0x1100A35C
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_1us_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_1us_BITEND 14

#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_locked_ADDR 0x1100A35C
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_locked_BITSTART 16
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_locked_BITEND 16

#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_alllane_ADDR 0x1100A35C
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_alllane_BITSTART 17
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_alllane_BITEND 20

#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_1ms_ADDR 0x1100A360
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_1ms_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_1ms_BITEND 24

#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_total_ADDR 0x1100A364
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_total_BITSTART 0
#define HS_Standby__typec_prbs_pattern_00__regr_00_rx_prbs_20b_error_total_BITEND 31

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adc_brige_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adc_brige_BITSTART 0
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adc_brige_BITEND 3

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adcib_comp_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adcib_comp_BITSTART 4
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adcib_comp_BITEND 5

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adcpulse_mode_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adcpulse_mode_BITSTART 6
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_adcpulse_mode_BITEND 6

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_atestsel_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_atestsel_BITSTART 7
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_atestsel_BITEND 10

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_ccrxvrefh_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_ccrxvrefh_BITSTART 11
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_ccrxvrefh_BITEND 18

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_ccrxvrefl_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_ccrxvrefl_BITSTART 19
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_ccrxvrefl_BITEND 26

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_divsel_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_divsel_BITSTART 27
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_divsel_BITEND 28

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_pd_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_pd_BITSTART 29
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_pd_BITEND 29

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_radc_en_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_radc_en_BITSTART 30
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_radc_en_BITEND 30

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rd_deten_ADDR 0x1100A400
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rd_deten_BITSTART 31
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rd_deten_BITEND 31

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_keep_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_keep_BITSTART 0
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_keep_BITEND 7

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rdtrim_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rdtrim_BITSTART 8
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rdtrim_BITEND 11

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rdtrim_sel_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rdtrim_sel_BITSTART 12
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rdtrim_sel_BITEND 12

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rptrim_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rptrim_BITSTART 13
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rptrim_BITEND 18

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_slpsel_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_slpsel_BITSTART 19
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_slpsel_BITEND 19

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p1_adj_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p1_adj_BITSTART 20
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p1_adj_BITEND 22

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p02_adj_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p02_adj_BITSTART 23
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p02_adj_BITEND 25

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p8_adj_ADDR 0x1100A404
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p8_adj_BITSTART 26
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_v1p8_adj_BITEND 28

#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rdtrim_ADDR 0x1100A408
#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rdtrim_BITSTART 0
#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rdtrim_BITEND 3

#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rd_cmpout_ADDR 0x1100A408
#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rd_cmpout_BITSTART 4
#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rd_cmpout_BITEND 4

#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rdtrim_done_ADDR 0x1100A408
#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rdtrim_done_BITSTART 5
#define HS_Standby__usb_typec_phy_top_00__regr_00_ccphy_rdtrim_done_BITEND 5

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rstn_cc_ADDR 0x1100A410
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rstn_cc_BITSTART 0
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rstn_cc_BITEND 0

#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rstn_adc_ADDR 0x1100A410
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rstn_adc_BITSTART 1
#define HS_Standby__usb_typec_phy_top_00__reg_00_ccphy_rstn_adc_BITEND 1

#define HS_Standby__usb_typec_phy_top_00__reg_00_din_rdtrim_start_ADDR 0x1100A410
#define HS_Standby__usb_typec_phy_top_00__reg_00_din_rdtrim_start_BITSTART 2
#define HS_Standby__usb_typec_phy_top_00__reg_00_din_rdtrim_start_BITEND 2

#define HS_Standby__usb_typec_phy_top_00__reg_00_din_sleepmode_ADDR 0x1100A410
#define HS_Standby__usb_typec_phy_top_00__reg_00_din_sleepmode_BITSTART 3
#define HS_Standby__usb_typec_phy_top_00__reg_00_din_sleepmode_BITEND 3

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_header_0_ADDR 0x1100A500
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_header_0_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_header_0_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_header_1_ADDR 0x1100A500
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_header_1_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_header_1_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_0_ADDR 0x1100A500
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_1_ADDR 0x1100A500
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_2_ADDR 0x1100A504
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_3_ADDR 0x1100A504
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_0_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_0_ADDR 0x1100A504
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_1_ADDR 0x1100A504
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_2_ADDR 0x1100A508
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_3_ADDR 0x1100A508
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_1_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_0_ADDR 0x1100A508
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_1_ADDR 0x1100A508
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_2_ADDR 0x1100A50C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_3_ADDR 0x1100A50C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_2_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_0_ADDR 0x1100A50C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_1_ADDR 0x1100A50C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_2_ADDR 0x1100A510
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_3_ADDR 0x1100A510
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_3_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_0_ADDR 0x1100A510
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_1_ADDR 0x1100A510
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_2_ADDR 0x1100A514
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_3_ADDR 0x1100A514
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_4_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_0_ADDR 0x1100A514
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_1_ADDR 0x1100A514
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_2_ADDR 0x1100A518
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_3_ADDR 0x1100A518
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_5_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_0_ADDR 0x1100A518
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_1_ADDR 0x1100A518
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_2_ADDR 0x1100A51C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_3_ADDR 0x1100A51C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_6_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_0_ADDR 0x1100A51C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_1_ADDR 0x1100A51C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_2_ADDR 0x1100A520
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_3_ADDR 0x1100A520
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_7_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_0_ADDR 0x1100A520
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_1_ADDR 0x1100A520
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_2_ADDR 0x1100A524
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_3_ADDR 0x1100A524
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_8_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_0_ADDR 0x1100A524
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_1_ADDR 0x1100A524
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_2_ADDR 0x1100A528
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_3_ADDR 0x1100A528
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_9_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_0_ADDR 0x1100A528
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_1_ADDR 0x1100A528
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_2_ADDR 0x1100A52C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_3_ADDR 0x1100A52C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_10_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_0_ADDR 0x1100A52C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_1_ADDR 0x1100A52C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_2_ADDR 0x1100A530
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_3_ADDR 0x1100A530
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_11_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_0_ADDR 0x1100A530
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_1_ADDR 0x1100A530
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_2_ADDR 0x1100A534
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_3_ADDR 0x1100A534
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_12_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_0_ADDR 0x1100A534
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_1_ADDR 0x1100A534
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_2_ADDR 0x1100A538
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_3_ADDR 0x1100A538
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_13_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_0_ADDR 0x1100A538
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_1_ADDR 0x1100A538
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_2_ADDR 0x1100A53C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_3_ADDR 0x1100A53C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_14_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_0_ADDR 0x1100A53C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_1_ADDR 0x1100A53C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_2_ADDR 0x1100A540
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_3_ADDR 0x1100A540
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_15_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_0_ADDR 0x1100A540
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_1_ADDR 0x1100A540
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_2_ADDR 0x1100A544
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_3_ADDR 0x1100A544
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_16_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_0_ADDR 0x1100A544
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_1_ADDR 0x1100A544
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_2_ADDR 0x1100A548
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_3_ADDR 0x1100A548
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_17_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_0_ADDR 0x1100A548
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_1_ADDR 0x1100A548
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_2_ADDR 0x1100A54C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_3_ADDR 0x1100A54C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_18_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_0_ADDR 0x1100A54C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_1_ADDR 0x1100A54C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_2_ADDR 0x1100A550
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_3_ADDR 0x1100A550
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_19_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_0_ADDR 0x1100A550
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_1_ADDR 0x1100A550
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_2_ADDR 0x1100A554
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_3_ADDR 0x1100A554
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_20_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_0_ADDR 0x1100A554
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_1_ADDR 0x1100A554
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_2_ADDR 0x1100A558
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_3_ADDR 0x1100A558
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_21_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_0_ADDR 0x1100A558
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_1_ADDR 0x1100A558
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_2_ADDR 0x1100A55C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_3_ADDR 0x1100A55C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_22_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_0_ADDR 0x1100A55C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_1_ADDR 0x1100A55C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_2_ADDR 0x1100A560
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_3_ADDR 0x1100A560
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_23_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_0_ADDR 0x1100A560
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_1_ADDR 0x1100A560
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_2_ADDR 0x1100A564
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_3_ADDR 0x1100A564
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_24_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_0_ADDR 0x1100A564
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_1_ADDR 0x1100A564
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_2_ADDR 0x1100A568
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_3_ADDR 0x1100A568
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_25_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_0_ADDR 0x1100A568
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_1_ADDR 0x1100A568
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_2_ADDR 0x1100A56C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_3_ADDR 0x1100A56C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_26_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_0_ADDR 0x1100A56C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_1_ADDR 0x1100A56C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_2_ADDR 0x1100A570
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_3_ADDR 0x1100A570
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_27_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_0_ADDR 0x1100A570
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_1_ADDR 0x1100A570
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_2_ADDR 0x1100A574
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_3_ADDR 0x1100A574
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_28_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_0_ADDR 0x1100A574
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_1_ADDR 0x1100A574
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_2_ADDR 0x1100A578
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_3_ADDR 0x1100A578
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_29_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_0_ADDR 0x1100A578
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_1_ADDR 0x1100A578
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_2_ADDR 0x1100A57C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_3_ADDR 0x1100A57C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_30_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_0_ADDR 0x1100A57C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_1_ADDR 0x1100A57C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_2_ADDR 0x1100A580
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_3_ADDR 0x1100A580
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_31_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_0_ADDR 0x1100A580
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_1_ADDR 0x1100A580
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_2_ADDR 0x1100A584
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_3_ADDR 0x1100A584
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_32_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_0_ADDR 0x1100A584
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_1_ADDR 0x1100A584
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_2_ADDR 0x1100A588
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_3_ADDR 0x1100A588
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_33_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_0_ADDR 0x1100A588
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_1_ADDR 0x1100A588
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_2_ADDR 0x1100A58C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_3_ADDR 0x1100A58C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_34_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_0_ADDR 0x1100A58C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_1_ADDR 0x1100A58C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_2_ADDR 0x1100A590
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_3_ADDR 0x1100A590
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_35_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_0_ADDR 0x1100A590
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_1_ADDR 0x1100A590
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_2_ADDR 0x1100A594
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_3_ADDR 0x1100A594
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_36_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_0_ADDR 0x1100A594
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_1_ADDR 0x1100A594
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_2_ADDR 0x1100A598
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_3_ADDR 0x1100A598
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_37_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_0_ADDR 0x1100A598
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_1_ADDR 0x1100A598
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_2_ADDR 0x1100A59C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_3_ADDR 0x1100A59C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_38_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_0_ADDR 0x1100A59C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_1_ADDR 0x1100A59C
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_2_ADDR 0x1100A5A0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_3_ADDR 0x1100A5A0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_39_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_0_ADDR 0x1100A5A0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_1_ADDR 0x1100A5A0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_2_ADDR 0x1100A5A4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_3_ADDR 0x1100A5A4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_40_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_0_ADDR 0x1100A5A4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_1_ADDR 0x1100A5A4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_2_ADDR 0x1100A5A8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_3_ADDR 0x1100A5A8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_41_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_0_ADDR 0x1100A5A8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_1_ADDR 0x1100A5A8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_2_ADDR 0x1100A5AC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_3_ADDR 0x1100A5AC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_42_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_0_ADDR 0x1100A5AC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_1_ADDR 0x1100A5AC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_2_ADDR 0x1100A5B0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_3_ADDR 0x1100A5B0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_43_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_0_ADDR 0x1100A5B0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_1_ADDR 0x1100A5B0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_2_ADDR 0x1100A5B4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_3_ADDR 0x1100A5B4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_44_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_0_ADDR 0x1100A5B4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_1_ADDR 0x1100A5B4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_2_ADDR 0x1100A5B8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_3_ADDR 0x1100A5B8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_45_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_0_ADDR 0x1100A5B8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_1_ADDR 0x1100A5B8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_2_ADDR 0x1100A5BC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_3_ADDR 0x1100A5BC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_46_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_0_ADDR 0x1100A5BC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_1_ADDR 0x1100A5BC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_2_ADDR 0x1100A5C0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_3_ADDR 0x1100A5C0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_47_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_0_ADDR 0x1100A5C0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_1_ADDR 0x1100A5C0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_2_ADDR 0x1100A5C4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_3_ADDR 0x1100A5C4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_48_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_0_ADDR 0x1100A5C4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_1_ADDR 0x1100A5C4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_2_ADDR 0x1100A5C8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_3_ADDR 0x1100A5C8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_49_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_0_ADDR 0x1100A5C8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_1_ADDR 0x1100A5C8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_2_ADDR 0x1100A5CC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_3_ADDR 0x1100A5CC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_50_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_0_ADDR 0x1100A5CC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_1_ADDR 0x1100A5CC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_2_ADDR 0x1100A5D0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_3_ADDR 0x1100A5D0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_51_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_0_ADDR 0x1100A5D0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_1_ADDR 0x1100A5D0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_2_ADDR 0x1100A5D4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_3_ADDR 0x1100A5D4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_52_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_0_ADDR 0x1100A5D4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_1_ADDR 0x1100A5D4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_2_ADDR 0x1100A5D8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_3_ADDR 0x1100A5D8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_53_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_0_ADDR 0x1100A5D8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_1_ADDR 0x1100A5D8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_2_ADDR 0x1100A5DC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_3_ADDR 0x1100A5DC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_54_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_0_ADDR 0x1100A5DC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_1_ADDR 0x1100A5DC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_2_ADDR 0x1100A5E0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_3_ADDR 0x1100A5E0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_55_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_0_ADDR 0x1100A5E0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_1_ADDR 0x1100A5E0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_2_ADDR 0x1100A5E4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_3_ADDR 0x1100A5E4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_56_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_0_ADDR 0x1100A5E4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_1_ADDR 0x1100A5E4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_2_ADDR 0x1100A5E8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_3_ADDR 0x1100A5E8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_57_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_0_ADDR 0x1100A5E8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_1_ADDR 0x1100A5E8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_2_ADDR 0x1100A5EC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_3_ADDR 0x1100A5EC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_58_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_0_ADDR 0x1100A5EC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_1_ADDR 0x1100A5EC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_2_ADDR 0x1100A5F0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_3_ADDR 0x1100A5F0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_59_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_0_ADDR 0x1100A5F0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_1_ADDR 0x1100A5F0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_2_ADDR 0x1100A5F4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_3_ADDR 0x1100A5F4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_60_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_0_ADDR 0x1100A5F4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_1_ADDR 0x1100A5F4
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_2_ADDR 0x1100A5F8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_3_ADDR 0x1100A5F8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_61_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_0_ADDR 0x1100A5F8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_1_ADDR 0x1100A5F8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_2_ADDR 0x1100A5FC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_3_ADDR 0x1100A5FC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_62_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_63_0_ADDR 0x1100A5FC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_63_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_63_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_63_1_ADDR 0x1100A5FC
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_63_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_00__reg_00_tx_msg_data_object_63_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_63_2_ADDR 0x1100A600
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_63_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_63_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_63_3_ADDR 0x1100A600
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_63_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_63_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_0_ADDR 0x1100A600
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_1_ADDR 0x1100A600
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_2_ADDR 0x1100A604
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_3_ADDR 0x1100A604
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_64_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_0_ADDR 0x1100A604
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_1_ADDR 0x1100A604
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_2_ADDR 0x1100A608
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_3_ADDR 0x1100A608
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_65_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_0_ADDR 0x1100A608
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_1_ADDR 0x1100A608
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_2_ADDR 0x1100A60C
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_3_ADDR 0x1100A60C
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_66_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_0_ADDR 0x1100A60C
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_1_ADDR 0x1100A60C
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_2_ADDR 0x1100A610
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_3_ADDR 0x1100A610
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_67_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_0_ADDR 0x1100A610
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_1_ADDR 0x1100A610
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_2_ADDR 0x1100A614
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_3_ADDR 0x1100A614
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_68_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_69_0_ADDR 0x1100A614
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_69_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_69_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_69_1_ADDR 0x1100A614
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_69_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_00__reg_00_tx_msg_data_object_69_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_header_0_ADDR 0x1100A700
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_header_0_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_header_0_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_header_1_ADDR 0x1100A700
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_header_1_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_header_1_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_0_ADDR 0x1100A700
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_1_ADDR 0x1100A700
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_2_ADDR 0x1100A704
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_3_ADDR 0x1100A704
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_0_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_0_ADDR 0x1100A704
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_1_ADDR 0x1100A704
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_2_ADDR 0x1100A708
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_3_ADDR 0x1100A708
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_1_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_0_ADDR 0x1100A708
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_1_ADDR 0x1100A708
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_2_ADDR 0x1100A70C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_3_ADDR 0x1100A70C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_2_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_0_ADDR 0x1100A70C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_1_ADDR 0x1100A70C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_2_ADDR 0x1100A710
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_3_ADDR 0x1100A710
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_3_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_0_ADDR 0x1100A710
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_1_ADDR 0x1100A710
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_2_ADDR 0x1100A714
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_3_ADDR 0x1100A714
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_4_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_0_ADDR 0x1100A714
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_1_ADDR 0x1100A714
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_2_ADDR 0x1100A718
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_3_ADDR 0x1100A718
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_5_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_0_ADDR 0x1100A718
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_1_ADDR 0x1100A718
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_2_ADDR 0x1100A71C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_3_ADDR 0x1100A71C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_6_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_0_ADDR 0x1100A71C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_1_ADDR 0x1100A71C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_2_ADDR 0x1100A720
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_3_ADDR 0x1100A720
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_7_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_0_ADDR 0x1100A720
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_1_ADDR 0x1100A720
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_2_ADDR 0x1100A724
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_3_ADDR 0x1100A724
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_8_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_0_ADDR 0x1100A724
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_1_ADDR 0x1100A724
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_2_ADDR 0x1100A728
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_3_ADDR 0x1100A728
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_9_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_0_ADDR 0x1100A728
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_1_ADDR 0x1100A728
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_2_ADDR 0x1100A72C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_3_ADDR 0x1100A72C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_10_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_0_ADDR 0x1100A72C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_1_ADDR 0x1100A72C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_2_ADDR 0x1100A730
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_3_ADDR 0x1100A730
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_11_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_0_ADDR 0x1100A730
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_1_ADDR 0x1100A730
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_2_ADDR 0x1100A734
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_3_ADDR 0x1100A734
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_12_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_0_ADDR 0x1100A734
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_1_ADDR 0x1100A734
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_2_ADDR 0x1100A738
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_3_ADDR 0x1100A738
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_13_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_0_ADDR 0x1100A738
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_1_ADDR 0x1100A738
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_2_ADDR 0x1100A73C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_3_ADDR 0x1100A73C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_14_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_0_ADDR 0x1100A73C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_1_ADDR 0x1100A73C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_2_ADDR 0x1100A740
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_3_ADDR 0x1100A740
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_15_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_0_ADDR 0x1100A740
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_1_ADDR 0x1100A740
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_2_ADDR 0x1100A744
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_3_ADDR 0x1100A744
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_16_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_0_ADDR 0x1100A744
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_1_ADDR 0x1100A744
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_2_ADDR 0x1100A748
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_3_ADDR 0x1100A748
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_17_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_0_ADDR 0x1100A748
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_1_ADDR 0x1100A748
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_2_ADDR 0x1100A74C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_3_ADDR 0x1100A74C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_18_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_0_ADDR 0x1100A74C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_1_ADDR 0x1100A74C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_2_ADDR 0x1100A750
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_3_ADDR 0x1100A750
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_19_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_0_ADDR 0x1100A750
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_1_ADDR 0x1100A750
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_2_ADDR 0x1100A754
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_3_ADDR 0x1100A754
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_20_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_0_ADDR 0x1100A754
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_1_ADDR 0x1100A754
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_2_ADDR 0x1100A758
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_3_ADDR 0x1100A758
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_21_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_0_ADDR 0x1100A758
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_1_ADDR 0x1100A758
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_2_ADDR 0x1100A75C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_3_ADDR 0x1100A75C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_22_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_0_ADDR 0x1100A75C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_1_ADDR 0x1100A75C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_2_ADDR 0x1100A760
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_3_ADDR 0x1100A760
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_23_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_0_ADDR 0x1100A760
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_1_ADDR 0x1100A760
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_2_ADDR 0x1100A764
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_3_ADDR 0x1100A764
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_24_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_0_ADDR 0x1100A764
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_1_ADDR 0x1100A764
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_2_ADDR 0x1100A768
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_3_ADDR 0x1100A768
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_25_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_0_ADDR 0x1100A768
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_1_ADDR 0x1100A768
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_2_ADDR 0x1100A76C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_3_ADDR 0x1100A76C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_26_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_0_ADDR 0x1100A76C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_1_ADDR 0x1100A76C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_2_ADDR 0x1100A770
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_3_ADDR 0x1100A770
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_27_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_0_ADDR 0x1100A770
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_1_ADDR 0x1100A770
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_2_ADDR 0x1100A774
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_3_ADDR 0x1100A774
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_28_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_0_ADDR 0x1100A774
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_1_ADDR 0x1100A774
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_2_ADDR 0x1100A778
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_3_ADDR 0x1100A778
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_29_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_0_ADDR 0x1100A778
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_1_ADDR 0x1100A778
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_2_ADDR 0x1100A77C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_3_ADDR 0x1100A77C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_30_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_0_ADDR 0x1100A77C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_1_ADDR 0x1100A77C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_2_ADDR 0x1100A780
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_3_ADDR 0x1100A780
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_31_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_0_ADDR 0x1100A780
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_1_ADDR 0x1100A780
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_2_ADDR 0x1100A784
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_3_ADDR 0x1100A784
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_32_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_0_ADDR 0x1100A784
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_1_ADDR 0x1100A784
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_2_ADDR 0x1100A788
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_3_ADDR 0x1100A788
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_33_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_0_ADDR 0x1100A788
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_1_ADDR 0x1100A788
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_2_ADDR 0x1100A78C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_3_ADDR 0x1100A78C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_34_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_0_ADDR 0x1100A78C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_1_ADDR 0x1100A78C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_2_ADDR 0x1100A790
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_3_ADDR 0x1100A790
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_35_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_0_ADDR 0x1100A790
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_1_ADDR 0x1100A790
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_2_ADDR 0x1100A794
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_3_ADDR 0x1100A794
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_36_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_0_ADDR 0x1100A794
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_1_ADDR 0x1100A794
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_2_ADDR 0x1100A798
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_3_ADDR 0x1100A798
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_37_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_0_ADDR 0x1100A798
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_1_ADDR 0x1100A798
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_2_ADDR 0x1100A79C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_3_ADDR 0x1100A79C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_38_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_0_ADDR 0x1100A79C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_1_ADDR 0x1100A79C
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_2_ADDR 0x1100A7A0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_3_ADDR 0x1100A7A0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_39_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_0_ADDR 0x1100A7A0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_1_ADDR 0x1100A7A0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_2_ADDR 0x1100A7A4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_3_ADDR 0x1100A7A4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_40_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_0_ADDR 0x1100A7A4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_1_ADDR 0x1100A7A4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_2_ADDR 0x1100A7A8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_3_ADDR 0x1100A7A8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_41_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_0_ADDR 0x1100A7A8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_1_ADDR 0x1100A7A8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_2_ADDR 0x1100A7AC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_3_ADDR 0x1100A7AC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_42_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_0_ADDR 0x1100A7AC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_1_ADDR 0x1100A7AC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_2_ADDR 0x1100A7B0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_3_ADDR 0x1100A7B0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_43_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_0_ADDR 0x1100A7B0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_1_ADDR 0x1100A7B0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_2_ADDR 0x1100A7B4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_3_ADDR 0x1100A7B4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_44_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_0_ADDR 0x1100A7B4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_1_ADDR 0x1100A7B4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_2_ADDR 0x1100A7B8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_3_ADDR 0x1100A7B8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_45_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_0_ADDR 0x1100A7B8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_1_ADDR 0x1100A7B8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_2_ADDR 0x1100A7BC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_3_ADDR 0x1100A7BC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_46_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_0_ADDR 0x1100A7BC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_1_ADDR 0x1100A7BC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_2_ADDR 0x1100A7C0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_3_ADDR 0x1100A7C0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_47_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_0_ADDR 0x1100A7C0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_1_ADDR 0x1100A7C0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_2_ADDR 0x1100A7C4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_3_ADDR 0x1100A7C4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_48_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_0_ADDR 0x1100A7C4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_1_ADDR 0x1100A7C4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_2_ADDR 0x1100A7C8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_3_ADDR 0x1100A7C8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_49_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_0_ADDR 0x1100A7C8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_1_ADDR 0x1100A7C8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_2_ADDR 0x1100A7CC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_3_ADDR 0x1100A7CC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_50_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_0_ADDR 0x1100A7CC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_1_ADDR 0x1100A7CC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_2_ADDR 0x1100A7D0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_3_ADDR 0x1100A7D0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_51_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_0_ADDR 0x1100A7D0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_1_ADDR 0x1100A7D0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_2_ADDR 0x1100A7D4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_3_ADDR 0x1100A7D4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_52_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_0_ADDR 0x1100A7D4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_1_ADDR 0x1100A7D4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_2_ADDR 0x1100A7D8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_3_ADDR 0x1100A7D8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_53_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_0_ADDR 0x1100A7D8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_1_ADDR 0x1100A7D8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_2_ADDR 0x1100A7DC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_3_ADDR 0x1100A7DC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_54_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_0_ADDR 0x1100A7DC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_1_ADDR 0x1100A7DC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_2_ADDR 0x1100A7E0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_3_ADDR 0x1100A7E0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_55_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_0_ADDR 0x1100A7E0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_1_ADDR 0x1100A7E0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_2_ADDR 0x1100A7E4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_3_ADDR 0x1100A7E4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_56_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_0_ADDR 0x1100A7E4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_1_ADDR 0x1100A7E4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_2_ADDR 0x1100A7E8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_3_ADDR 0x1100A7E8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_57_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_0_ADDR 0x1100A7E8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_1_ADDR 0x1100A7E8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_2_ADDR 0x1100A7EC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_3_ADDR 0x1100A7EC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_58_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_0_ADDR 0x1100A7EC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_1_ADDR 0x1100A7EC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_2_ADDR 0x1100A7F0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_3_ADDR 0x1100A7F0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_59_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_0_ADDR 0x1100A7F0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_1_ADDR 0x1100A7F0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_2_ADDR 0x1100A7F4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_3_ADDR 0x1100A7F4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_60_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_0_ADDR 0x1100A7F4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_1_ADDR 0x1100A7F4
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_2_ADDR 0x1100A7F8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_3_ADDR 0x1100A7F8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_61_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_0_ADDR 0x1100A7F8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_1_ADDR 0x1100A7F8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_2_ADDR 0x1100A7FC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_3_ADDR 0x1100A7FC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_62_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_63_0_ADDR 0x1100A7FC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_63_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_63_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_63_1_ADDR 0x1100A7FC
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_63_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_00__regr_00_rx_msg_data_object_63_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_63_2_ADDR 0x1100A800
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_63_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_63_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_63_3_ADDR 0x1100A800
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_63_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_63_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_0_ADDR 0x1100A800
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_1_ADDR 0x1100A800
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_2_ADDR 0x1100A804
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_3_ADDR 0x1100A804
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_64_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_0_ADDR 0x1100A804
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_1_ADDR 0x1100A804
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_2_ADDR 0x1100A808
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_3_ADDR 0x1100A808
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_65_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_0_ADDR 0x1100A808
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_1_ADDR 0x1100A808
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_2_ADDR 0x1100A80C
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_3_ADDR 0x1100A80C
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_66_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_0_ADDR 0x1100A80C
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_1_ADDR 0x1100A80C
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_2_ADDR 0x1100A810
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_3_ADDR 0x1100A810
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_67_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_0_ADDR 0x1100A810
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_1_ADDR 0x1100A810
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_2_ADDR 0x1100A814
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_3_ADDR 0x1100A814
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_68_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_69_0_ADDR 0x1100A814
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_69_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_69_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_69_1_ADDR 0x1100A814
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_69_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_00__regr_00_rx_msg_data_object_69_1_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C01_RX_IRQFLAG_ADDR 0x1100A900
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C01_RX_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C01_RX_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C02_TX_IRQFLAG_ADDR 0x1100A900
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C02_TX_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C02_TX_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C03_RXFSM_SOP_IRQFLAG_ADDR 0x1100A900
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C03_RXFSM_SOP_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C03_RXFSM_SOP_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C04_RXFSM_SOPP_IRQFLAG_ADDR 0x1100A904
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C04_RXFSM_SOPP_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C04_RXFSM_SOPP_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C05_TXFSM_SOP_IRQFLAG_ADDR 0x1100A904
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C05_TXFSM_SOP_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C05_TXFSM_SOP_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C06_TXFSM_SOPP_IRQFLAG_ADDR 0x1100A904
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C06_TXFSM_SOPP_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C06_TXFSM_SOPP_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C07_RSTFSM_IRQFLAG_ADDR 0x1100A904
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C07_RSTFSM_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C07_RSTFSM_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C08_PE_TIMER_IRQFLAG_ADDR 0x1100A908
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C08_PE_TIMER_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C08_PE_TIMER_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C09_PE_TIMER_IRQFLAG_ADDR 0x1100A908
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C09_PE_TIMER_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C09_PE_TIMER_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0A_Reserved_for_PE_TIMER_IRQFLAG_ADDR 0x1100A908
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0A_Reserved_for_PE_TIMER_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0A_Reserved_for_PE_TIMER_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_ADDR 0x1100A908
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0C_PD_TOP_IRQFALG_ADDR 0x1100A90C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0C_PD_TOP_IRQFALG_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0C_PD_TOP_IRQFALG_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0D_IRQ_PWR_DET_ADDR 0x1100A90C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0D_IRQ_PWR_DET_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0D_IRQ_PWR_DET_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0E_IRQ_CCVOL_DET_ADDR 0x1100A90C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0E_IRQ_CCVOL_DET_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0E_IRQ_CCVOL_DET_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0F_IRQ_MISC_ADDR 0x1100A90C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0F_IRQ_MISC_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C0F_IRQ_MISC_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C10_Reserved_ADDR 0x1100A910
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C10_Reserved_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C10_Reserved_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C11_RX_RAW_IRQFLAG_ADDR 0x1100A910
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C11_RX_RAW_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C11_RX_RAW_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C12_TX_RAW_IRQFLAG_ADDR 0x1100A910
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C12_TX_RAW_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C12_TX_RAW_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C13_RXFSM_SOP_RAW_IRQFLAG_ADDR 0x1100A910
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C13_RXFSM_SOP_RAW_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C13_RXFSM_SOP_RAW_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C14_RXFSM_SOPP_RAW_IRQFLAG_ADDR 0x1100A914
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C14_RXFSM_SOPP_RAW_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C14_RXFSM_SOPP_RAW_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C15_TXFSM_SOP_RAW_IRQFLAG_ADDR 0x1100A914
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C15_TXFSM_SOP_RAW_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C15_TXFSM_SOP_RAW_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C16_TXFSM_SOPP_RAW_IRQFLAG_ADDR 0x1100A914
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C16_TXFSM_SOPP_RAW_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C16_TXFSM_SOPP_RAW_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C17_RSTFSM_RAW_IRQFLAG_ADDR 0x1100A914
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C17_RSTFSM_RAW_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C17_RSTFSM_RAW_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C18_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A918
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C18_PE_TIMER_RAW_IRQFLAG_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C18_PE_TIMER_RAW_IRQFLAG_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C19_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A918
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C19_PE_TIMER_RAW_IRQFLAG_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C19_PE_TIMER_RAW_IRQFLAG_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1A_Reserved_for_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A918
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1A_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1A_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1B_Reserved_for_PE_TIMER_RAW_IRQFLAG_ADDR 0x1100A918
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1B_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1B_Reserved_for_PE_TIMER_RAW_IRQFLAG_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1C_PD_TOP_RAW_IRQFALG_ADDR 0x1100A91C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1C_PD_TOP_RAW_IRQFALG_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1C_PD_TOP_RAW_IRQFALG_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1D_IRQ_RAW_PWR_DET_ADDR 0x1100A91C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1D_IRQ_RAW_PWR_DET_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1D_IRQ_RAW_PWR_DET_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1E_IRQ_RAW_CCVOL_DET_ADDR 0x1100A91C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1E_IRQ_RAW_CCVOL_DET_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1E_IRQ_RAW_CCVOL_DET_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1F_IRQ_RAW_MISC_ADDR 0x1100A91C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1F_IRQ_RAW_MISC_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C1F_IRQ_RAW_MISC_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C3E_PD_RX_status_register_ADDR 0x1100A93C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C3E_PD_RX_status_register_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C3E_PD_RX_status_register_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C3F_PD_RX_received_SOP_type_ADDR 0x1100A93C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C3F_PD_RX_received_SOP_type_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C3F_PD_RX_received_SOP_type_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C40_PD_RX_status_register_ADDR 0x1100A940
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C40_PD_RX_status_register_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C40_PD_RX_status_register_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C41_PD_RX_Received_CRC_ADDR 0x1100A940
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C41_PD_RX_Received_CRC_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C41_PD_RX_Received_CRC_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C42_PD_RX_Received_CRC_ADDR 0x1100A940
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C42_PD_RX_Received_CRC_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C42_PD_RX_Received_CRC_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C43_PD_RX_Received_CRC_ADDR 0x1100A940
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C43_PD_RX_Received_CRC_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C43_PD_RX_Received_CRC_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C44_PD_RX_Received_CRC_ADDR 0x1100A944
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C44_PD_RX_Received_CRC_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C44_PD_RX_Received_CRC_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C45_Reserved_ADDR 0x1100A944
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C45_Reserved_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C45_Reserved_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C46_Reserved_ADDR 0x1100A944
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C46_Reserved_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C46_Reserved_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C47_Reserved_ADDR 0x1100A944
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C47_Reserved_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C47_Reserved_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C48_PD_RX_Received_MessageID_ADDR 0x1100A948
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C48_PD_RX_Received_MessageID_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C48_PD_RX_Received_MessageID_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C49_FSM_for_SOP_status_register_ADDR 0x1100A948
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C49_FSM_for_SOP_status_register_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C49_FSM_for_SOP_status_register_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4A_FSM_for_SOPP_status_register_ADDR 0x1100A948
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4A_FSM_for_SOPP_status_register_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4A_FSM_for_SOPP_status_register_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4B_TX_FSM_for_SOP_status_register_ADDR 0x1100A948
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4B_TX_FSM_for_SOP_status_register_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4B_TX_FSM_for_SOP_status_register_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4C_TX_FSM_for_SOPP_status_register_ADDR 0x1100A94C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4C_TX_FSM_for_SOPP_status_register_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4C_TX_FSM_for_SOPP_status_register_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4D_Hard_Reset_FSM_for_SOPs_state_ADDR 0x1100A94C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4D_Hard_Reset_FSM_for_SOPs_state_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4D_Hard_Reset_FSM_for_SOPs_state_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4E_PD_PHY_status_register_ADDR 0x1100A94C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4E_PD_PHY_status_register_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4E_PD_PHY_status_register_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4F_Resevered_ADDR 0x1100A94C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4F_Resevered_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C4F_Resevered_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C54_PD_TXPATH_status_register_ADDR 0x1100A954
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C54_PD_TXPATH_status_register_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C54_PD_TXPATH_status_register_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C55_PD_PHY_FSM_status_register_ADDR 0x1100A954
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C55_PD_PHY_FSM_status_register_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C55_PD_PHY_FSM_status_register_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C56_PD_TX_DATA_CRC_ADDR 0x1100A954
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C56_PD_TX_DATA_CRC_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C56_PD_TX_DATA_CRC_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C57_PD_TX_DATA_CRC_ADDR 0x1100A954
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C57_PD_TX_DATA_CRC_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C57_PD_TX_DATA_CRC_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C58_PD_TX_DATA_CRC_ADDR 0x1100A958
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C58_PD_TX_DATA_CRC_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C58_PD_TX_DATA_CRC_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C59_PD_TX_DATA_CRC_ADDR 0x1100A958
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C59_PD_TX_DATA_CRC_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C59_PD_TX_DATA_CRC_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5A_PD_TX_DATA_CRC_newc_ADDR 0x1100A958
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5A_PD_TX_DATA_CRC_newc_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5A_PD_TX_DATA_CRC_newc_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5B_PD_TX_DATA_CRC_newc_ADDR 0x1100A958
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5B_PD_TX_DATA_CRC_newc_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5B_PD_TX_DATA_CRC_newc_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5C_PE_TIMER_time_out_ADDR 0x1100A95C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5C_PE_TIMER_time_out_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5C_PE_TIMER_time_out_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5D_PE_TIMER_time_out_ADDR 0x1100A95C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5D_PE_TIMER_time_out_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5D_PE_TIMER_time_out_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5E_Reserved_ADDR 0x1100A95C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5E_Reserved_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5E_Reserved_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5F_Reserved_ADDR 0x1100A95C
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5F_Reserved_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C5F_Reserved_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_TRIM_CCSR_ADDR 0x1100A964
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_TRIM_CCSR_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_TRIM_CCSR_BITEND 4

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_CCTX_AUX_DONE_ADDR 0x1100A964
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_CCTX_AUX_DONE_BITSTART 5
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_CCTX_AUX_DONE_BITEND 5

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_SENSE_CC2A_ADDR 0x1100A964
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_SENSE_CC2A_BITSTART 6
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C64_SENSE_CC2A_BITEND 6

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C65_SENSE_PULSE_LEN_ADDR 0x1100A964
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C65_SENSE_PULSE_LEN_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C65_SENSE_PULSE_LEN_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C66_SENSE_CYCLE_NUM_ADDR 0x1100A964
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C66_SENSE_CYCLE_NUM_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C66_SENSE_CYCLE_NUM_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C67_reserved_ADDR 0x1100A964
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C67_reserved_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C67_reserved_BITEND 31

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C80_cc_power_detect_ADDR 0x1100A980
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C80_cc_power_detect_BITSTART 0
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C80_cc_power_detect_BITEND 7

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C81_cc_connection_detect_ADDR 0x1100A980
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C81_cc_connection_detect_BITSTART 8
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C81_cc_connection_detect_BITEND 15

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C82_cc_connection_detect_ADDR 0x1100A980
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C82_cc_connection_detect_BITSTART 16
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C82_cc_connection_detect_BITEND 23

#define HS_Standby__usb_typec_0_01__REG_01_RO_2C83_cc_plug_detect_ADDR 0x1100A980
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C83_cc_plug_detect_BITSTART 24
#define HS_Standby__usb_typec_0_01__REG_01_RO_2C83_cc_plug_detect_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_RX_clock_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_RX_clock_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_RX_clock_BITEND 8

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_SOP_FSM_clock_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_SOP_FSM_clock_BITSTART 9
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_SOP_FSM_clock_BITEND 9

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_SOPP_FSM_clock_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_SOPP_FSM_clock_BITSTART 10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_SOPP_FSM_clock_BITEND 10

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_Reset_FSM_clock_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_Reset_FSM_clock_BITSTART 11
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_Reset_FSM_clock_BITEND 11

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_PE_Timer_clock_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_PE_Timer_clock_BITSTART 12
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_PE_Timer_clock_BITEND 12

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_CC_TX_Auxiliary_logic_clock_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_CC_TX_Auxiliary_logic_clock_BITSTART 13
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_CC_TX_Auxiliary_logic_clock_BITEND 13

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_TX_clock_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_TX_clock_BITSTART 14
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_TX_clock_BITEND 14

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_Clock_Gating_Control_for_PD_TX_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_Clock_Gating_Control_for_PD_TX_BITSTART 15
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D01_Clock_Gating_Control_for_PD_TX_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D02_RX_SOP_packet_type_setting_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D02_RX_SOP_packet_type_setting_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D02_RX_SOP_packet_type_setting_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D03_RXOS_MPAT1_ADDR 0x1100AA00
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D03_RXOS_MPAT1_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D03_RXOS_MPAT1_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D04_RXOS_MPAT2_ADDR 0x1100AA04
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D04_RXOS_MPAT2_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D04_RXOS_MPAT2_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D05_RXOS_MPAT3_ADDR 0x1100AA04
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D05_RXOS_MPAT3_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D05_RXOS_MPAT3_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D06_RXOS_MPAT4_ADDR 0x1100AA04
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D06_RXOS_MPAT4_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D06_RXOS_MPAT4_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D07_TX_SOP_packet_type_setting_ADDR 0x1100AA04
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D07_TX_SOP_packet_type_setting_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D07_TX_SOP_packet_type_setting_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D08_TXOS_MPAT1_ADDR 0x1100AA08
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D08_TXOS_MPAT1_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D08_TXOS_MPAT1_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D09_TXOS_MPAT2_ADDR 0x1100AA08
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D09_TXOS_MPAT2_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D09_TXOS_MPAT2_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0A_TXOS_MPAT3_ADDR 0x1100AA08
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0A_TXOS_MPAT3_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0A_TXOS_MPAT3_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0B_TXOS_MPAT4_ADDR 0x1100AA08
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0B_TXOS_MPAT4_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0B_TXOS_MPAT4_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_IDLE_counter_length_bit_8_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_IDLE_counter_length_bit_8_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_IDLE_counter_length_bit_8_BITEND 0

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_IDLE_counter_clear_enable_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_IDLE_counter_clear_enable_BITSTART 1
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_IDLE_counter_clear_enable_BITEND 1

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_SOP_Search_Window_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_SOP_Search_Window_BITSTART 2
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0C_SOP_Search_Window_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0D_IDLE_counter_length_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0D_IDLE_counter_length_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0D_IDLE_counter_length_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0E_CC_Spike_Filter_counter_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0E_CC_Spike_Filter_counter_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0E_CC_Spike_Filter_counter_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_CRC_check_bypass_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_CRC_check_bypass_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_CRC_check_bypass_BITEND 24

#define HS_Standby__usb_typec_1_01__01_PREDISCTX_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__01_PREDISCTX_BITSTART 25
#define HS_Standby__usb_typec_1_01__01_PREDISCTX_BITEND 26

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_RX_FIFO_reset_control_by_HW_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_RX_FIFO_reset_control_by_HW_BITSTART 27
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_RX_FIFO_reset_control_by_HW_BITEND 27

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_BMC_UI_Average_Delay_count_ADDR 0x1100AA0C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_BMC_UI_Average_Delay_count_BITSTART 28
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D0F_BMC_UI_Average_Delay_count_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D10_reserved_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D10_reserved_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D10_reserved_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_TXEN_enable_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_TXEN_enable_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_TXEN_enable_BITEND 8

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_RXEN_enable_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_RXEN_enable_BITSTART 9
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_RXEN_enable_BITEND 9

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_enable_control_mode_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_enable_control_mode_BITSTART 10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_CC_enable_control_mode_BITEND 10

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_reserved_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_reserved_BITSTART 11
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_reserved_BITEND 13

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_Disable_TXHIZ_to_block_CCIN_RX_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_Disable_TXHIZ_to_block_CCIN_RX_BITSTART 14
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_Disable_TXHIZ_to_block_CCIN_RX_BITEND 14

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_all_K_code_are_same_flag_set_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_all_K_code_are_same_flag_set_BITSTART 15
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D11_all_K_code_are_same_flag_set_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D12_PD_TX_message_control_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D12_PD_TX_message_control_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D12_PD_TX_message_control_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D13_PD_RX_message_control_ADDR 0x1100AA10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D13_PD_RX_message_control_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D13_PD_RX_message_control_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D14_PD_TX_message_data_buffer_control_ADDR 0x1100AA14
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D14_PD_TX_message_data_buffer_control_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D14_PD_TX_message_data_buffer_control_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D15_MSG_TX_BITRATE_ADDR 0x1100AA14
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D15_MSG_TX_BITRATE_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D15_MSG_TX_BITRATE_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D16_MSG_TX_CRC_FW_ADDR 0x1100AA14
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D16_MSG_TX_CRC_FW_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D16_MSG_TX_CRC_FW_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D17_MSG_TX_CRC_FW_ADDR 0x1100AA14
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D17_MSG_TX_CRC_FW_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D17_MSG_TX_CRC_FW_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D18_MSG_TX_CRC_FW_ADDR 0x1100AA18
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D18_MSG_TX_CRC_FW_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D18_MSG_TX_CRC_FW_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D19_MSG_TX_CRC_FW_ADDR 0x1100AA18
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D19_MSG_TX_CRC_FW_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D19_MSG_TX_CRC_FW_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_CHEN_CTL_BPRX_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_CHEN_CTL_BPRX_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_CHEN_CTL_BPRX_BITEND 0

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_CHEN_CTL_BPTX_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_CHEN_CTL_BPTX_BITSTART 1
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_CHEN_CTL_BPTX_BITEND 1

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_TX_IRQ_MODE_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_TX_IRQ_MODE_BITSTART 2
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_TX_IRQ_MODE_BITEND 2

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_reserved_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_reserved_BITSTART 3
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3C_reserved_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_set_to_Cable_plug_mode_if_cable_plug_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_set_to_Cable_plug_mode_if_cable_plug_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_set_to_Cable_plug_mode_if_cable_plug_BITEND 8

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_Cable_plug_mode_for_SOP_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_Cable_plug_mode_for_SOP_BITSTART 9
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_Cable_plug_mode_for_SOP_BITEND 9

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_Cable_plug_mode_for_SOPP_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_Cable_plug_mode_for_SOPP_BITSTART 10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_Cable_plug_mode_for_SOPP_BITEND 10

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_reserved_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_reserved_BITSTART 11
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_reserved_BITEND 11

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_TX_Retry_Counter_for_SOP_SOPP_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_TX_Retry_Counter_for_SOP_SOPP_BITSTART 12
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3D_TX_Retry_Counter_for_SOP_SOPP_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_register_control_for_SOP_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_register_control_for_SOP_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_register_control_for_SOP_BITEND 16

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_select_for_SOP_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_select_for_SOP_BITSTART 17
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_select_for_SOP_BITEND 17

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_register_control_for_SOPP_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_register_control_for_SOPP_BITSTART 18
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_register_control_for_SOPP_BITEND 18

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_select_for_SOPP_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_select_for_SOPP_BITSTART 19
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_MSGID_Reset_select_for_SOPP_BITEND 19

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_Reserved_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_Reserved_BITSTART 20
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3E_Reserved_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3F_set_if_MCU_finished_HardReset_ADDR 0x1100AA3C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3F_set_if_MCU_finished_HardReset_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D3F_set_if_MCU_finished_HardReset_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D44_PE_TIMER_timer_enable_ADDR 0x1100AA44
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D44_PE_TIMER_timer_enable_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D44_PE_TIMER_timer_enable_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D45_PE_TIMER_timer_enable_ADDR 0x1100AA44
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D45_PE_TIMER_timer_enable_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D45_PE_TIMER_timer_enable_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D46_PE_TIMER_timer_enable_ADDR 0x1100AA44
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D46_PE_TIMER_timer_enable_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D46_PE_TIMER_timer_enable_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D47_PE_TIMER_timer_enable_ADDR 0x1100AA44
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D47_PE_TIMER_timer_enable_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D47_PE_TIMER_timer_enable_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D48_PE_TIMER_timer_start_ADDR 0x1100AA48
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D48_PE_TIMER_timer_start_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D48_PE_TIMER_timer_start_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D49_PE_TIMER_timer_start_ADDR 0x1100AA48
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D49_PE_TIMER_timer_start_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D49_PE_TIMER_timer_start_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4A_PE_TIMER_timer_start_ADDR 0x1100AA48
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4A_PE_TIMER_timer_start_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4A_PE_TIMER_timer_start_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4B_PE_TIMER_timer_start_ADDR 0x1100AA48
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4B_PE_TIMER_timer_start_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4B_PE_TIMER_timer_start_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4C_PE_TIMER_timer_stop_ADDR 0x1100AA4C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4C_PE_TIMER_timer_stop_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4C_PE_TIMER_timer_stop_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4D_PE_TIMER_timer_stop_ADDR 0x1100AA4C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4D_PE_TIMER_timer_stop_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4D_PE_TIMER_timer_stop_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4E_PE_TIMER_timer_stop_ADDR 0x1100AA4C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4E_PE_TIMER_timer_stop_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4E_PE_TIMER_timer_stop_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4F_PE_TIMER_timer_stop_ADDR 0x1100AA4C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4F_PE_TIMER_timer_stop_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D4F_PE_TIMER_timer_stop_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D50_PE_TIMER_timeout_value_ADDR 0x1100AA50
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D50_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D50_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D51_PE_TIMER_timeout_value_ADDR 0x1100AA50
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D51_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D51_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D52_PE_TIMER_timeout_value_ADDR 0x1100AA50
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D52_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D52_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D53_PE_TIMER_timeout_value_ADDR 0x1100AA50
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D53_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D53_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D54_PE_TIMER_timeout_value_ADDR 0x1100AA54
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D54_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D54_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D55_PE_TIMER_timeout_value_ADDR 0x1100AA54
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D55_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D55_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D56_PE_TIMER_timeout_value_ADDR 0x1100AA54
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D56_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D56_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D57_PE_TIMER_timeout_value_ADDR 0x1100AA54
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D57_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D57_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D58_PE_TIMER_timeout_value_ADDR 0x1100AA58
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D58_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D58_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D59_PE_TIMER_timeout_value_ADDR 0x1100AA58
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D59_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D59_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5A_PE_TIMER_timeout_value_ADDR 0x1100AA58
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5A_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5A_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5B_PE_TIMER_timeout_value_ADDR 0x1100AA58
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5B_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5B_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5C_PE_TIMER_timeout_value_ADDR 0x1100AA5C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5C_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5C_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5D_PE_TIMER_timeout_value_ADDR 0x1100AA5C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5D_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5D_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5E_PE_TIMER_timeout_value_ADDR 0x1100AA5C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5E_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5E_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5F_PE_TIMER_timeout_value_ADDR 0x1100AA5C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5F_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D5F_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D60_PE_TIMER_timeout_value_ADDR 0x1100AA60
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D60_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D60_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D61_PE_TIMER_timeout_value_ADDR 0x1100AA60
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D61_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D61_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D62_PE_TIMER_timeout_value_ADDR 0x1100AA60
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D62_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D62_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D63_PE_TIMER_timeout_value_ADDR 0x1100AA60
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D63_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D63_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D64_PE_TIMER_timeout_value_ADDR 0x1100AA64
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D64_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D64_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D65_PE_TIMER_timeout_value_ADDR 0x1100AA64
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D65_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D65_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D66_PE_TIMER_timeout_value_ADDR 0x1100AA64
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D66_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D66_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D67_PE_TIMER_timeout_value_ADDR 0x1100AA64
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D67_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D67_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D68_PE_TIMER_timeout_value_ADDR 0x1100AA68
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D68_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D68_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D69_PE_TIMER_timeout_value_ADDR 0x1100AA68
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D69_PE_TIMER_timeout_value_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D69_PE_TIMER_timeout_value_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D6A_PE_TIMER_timeout_value_ADDR 0x1100AA68
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D6A_PE_TIMER_timeout_value_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D6A_PE_TIMER_timeout_value_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D6B_PE_TIMER_timeout_value_ADDR 0x1100AA68
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D6B_PE_TIMER_timeout_value_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D6B_PE_TIMER_timeout_value_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D80_PE_TIMER_timeout_value_ADDR 0x1100AA80
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D80_PE_TIMER_timeout_value_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D80_PE_TIMER_timeout_value_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D81_PD_RX_IRQ_Mask_ADDR 0x1100AA80
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D81_PD_RX_IRQ_Mask_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D81_PD_RX_IRQ_Mask_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D82_PD_TX_IRQ_Mask_ADDR 0x1100AA80
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D82_PD_TX_IRQ_Mask_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D82_PD_TX_IRQ_Mask_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_ADDR 0x1100AA80
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D84_PD_RX_FSM_SOPP_IRQ_Mask_ADDR 0x1100AA84
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D84_PD_RX_FSM_SOPP_IRQ_Mask_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D84_PD_RX_FSM_SOPP_IRQ_Mask_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D85_PD_TX_FSM_SOP_IRQ_Mask_ADDR 0x1100AA84
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D85_PD_TX_FSM_SOP_IRQ_Mask_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D85_PD_TX_FSM_SOP_IRQ_Mask_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D86_PD_TX_FSM_SOPP_IRQ_Mask_ADDR 0x1100AA84
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D86_PD_TX_FSM_SOPP_IRQ_Mask_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D86_PD_TX_FSM_SOPP_IRQ_Mask_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D87_PD_Reset_FSM_IRQ_Mask_ADDR 0x1100AA84
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D87_PD_Reset_FSM_IRQ_Mask_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D87_PD_Reset_FSM_IRQ_Mask_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D88_PE_TIMER_IRQ_Mask_ADDR 0x1100AA88
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D88_PE_TIMER_IRQ_Mask_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D88_PE_TIMER_IRQ_Mask_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D89_PE_TIMER_IRQ_Mask_ADDR 0x1100AA88
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D89_PE_TIMER_IRQ_Mask_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D89_PE_TIMER_IRQ_Mask_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8A_PE_TIMER_IRQ_Mask_ADDR 0x1100AA88
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8A_PE_TIMER_IRQ_Mask_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8A_PE_TIMER_IRQ_Mask_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8B_PE_TIMER_IRQ_Mask_ADDR 0x1100AA88
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8B_PE_TIMER_IRQ_Mask_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8B_PE_TIMER_IRQ_Mask_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8C_USBPD_MISC_IRQ_Mask_ADDR 0x1100AA8C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8C_USBPD_MISC_IRQ_Mask_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8C_USBPD_MISC_IRQ_Mask_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8D_Reserved_ADDR 0x1100AA8C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8D_Reserved_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8D_Reserved_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8E_Reserved_ADDR 0x1100AA8C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8E_Reserved_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8E_Reserved_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8F_Reserved_ADDR 0x1100AA8C
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8F_Reserved_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D8F_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_START_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_START_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_START_BITEND 0

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_STOP_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_STOP_BITSTART 1
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_STOP_BITEND 1

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_EN_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_EN_BITSTART 2
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_CCTX_AUX_EN_BITEND 2

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_Reserved_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_Reserved_BITSTART 3
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D90_Reserved_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D91_TRIM_INITIAL_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D91_TRIM_INITIAL_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D91_TRIM_INITIAL_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D92_TRIM_DOWN_LIMIT_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D92_TRIM_DOWN_LIMIT_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D92_TRIM_DOWN_LIMIT_BITEND 20

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D92_TRIM_WINDOW_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D92_TRIM_WINDOW_BITSTART 21
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D92_TRIM_WINDOW_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_TRIM_STEP_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_TRIM_STEP_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_TRIM_STEP_BITEND 26

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_ADJUST_DIR_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_ADJUST_DIR_BITSTART 27
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_ADJUST_DIR_BITEND 27

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_Reserved_ADDR 0x1100AA90
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_Reserved_BITSTART 28
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D93_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D94_PD_START_DLY_ADDR 0x1100AA94
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D94_PD_START_DLY_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D94_PD_START_DLY_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D95_PD_START_DLY_ADDR 0x1100AA94
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D95_PD_START_DLY_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D95_PD_START_DLY_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D96_MAX_CYCLE_NUM_ADDR 0x1100AA94
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D96_MAX_CYCLE_NUM_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D96_MAX_CYCLE_NUM_BITEND 20

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D96_MAX_CYCLE_EN_ADDR 0x1100AA94
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D96_MAX_CYCLE_EN_BITSTART 21
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D96_MAX_CYCLE_EN_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2D97_Reserved_ADDR 0x1100AA94
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D97_Reserved_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2D97_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_MISC_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_MISC_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_MISC_BITEND 0

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_UFP_FSM_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_UFP_FSM_BITSTART 1
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_UFP_FSM_BITEND 1

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_DRP_FSM_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_DRP_FSM_BITSTART 2
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_DRP_FSM_BITEND 2

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_TERM_DET_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_TERM_DET_BITSTART 3
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_CLK_TERM_DET_BITEND 3

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_Clock_Gating_Control_for_CC_Detect_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_Clock_Gating_Control_for_CC_Detect_BITSTART 4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA0_Clock_Gating_Control_for_CC_Detect_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA1_VBUS_or_VCONN_power_detection_configuration_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA1_VBUS_or_VCONN_power_detection_configuration_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA1_VBUS_or_VCONN_power_detection_configuration_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA2_VBUS_or_VCONN_IRQ_edge_setting_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA2_VBUS_or_VCONN_IRQ_edge_setting_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA2_VBUS_or_VCONN_IRQ_edge_setting_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_FW_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_FW_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_FW_BITEND 24

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_MODE_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_MODE_BITSTART 25
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_MODE_BITEND 25

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_INV_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_INV_BITSTART 26
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_CCSEL_ANA_INV_BITEND 26

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_Reserved_ADDR 0x1100AAA0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_Reserved_BITSTART 27
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA3_Reserved_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_RD_GND_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_RD_GND_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_RD_GND_BITEND 1

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_RD_CON_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_RD_CON_BITSTART 2
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_RD_CON_BITEND 3

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SWAP_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SWAP_BITSTART 4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SWAP_BITEND 4

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SEL_FW_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SEL_FW_BITSTART 5
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SEL_FW_BITEND 5

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SEL_MODE_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SEL_MODE_BITSTART 6
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_CCVOL_SEL_MODE_BITEND 6

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_DBBP_CCVOL_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_DBBP_CCVOL_BITSTART 7
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA4_DBBP_CCVOL_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_OPEN_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_OPEN_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_OPEN_BITEND 9

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_RD_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_RD_BITSTART 10
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_RD_BITEND 11

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_RA_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_RA_BITSTART 12
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA5_CCVOL_RP_RA_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA6_Plug_Flip_detection_configuration_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA6_Plug_Flip_detection_configuration_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA6_Plug_Flip_detection_configuration_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA7_STATE_DIRECT_TRIG_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA7_STATE_DIRECT_TRIG_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA7_STATE_DIRECT_TRIG_BITEND 24

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA7_STATE_DIRECT_ADDR 0x1100AAA4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA7_STATE_DIRECT_BITSTART 25
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA7_STATE_DIRECT_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA8_TERR_RECOV_ADDR 0x1100AAA8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA8_TERR_RECOV_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA8_TERR_RECOV_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA9_Reserved_ADDR 0x1100AAA8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA9_Reserved_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DA9_Reserved_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAA_Debounce_attach_for_tCCDebounce_ADDR 0x1100AAA8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAA_Debounce_attach_for_tCCDebounce_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAA_Debounce_attach_for_tCCDebounce_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAB_Debounce_detach_for_tPDDebounce_ADDR 0x1100AAA8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAB_Debounce_detach_for_tPDDebounce_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAB_Debounce_detach_for_tPDDebounce_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAC_Debounce_VBUS_ON_for_tVBUSON_ADDR 0x1100AAAC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAC_Debounce_VBUS_ON_for_tVBUSON_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAC_Debounce_VBUS_ON_for_tVBUSON_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAD_Debounce_VBUS_OFF_for_tVBUSOFF_ADDR 0x1100AAAC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAD_Debounce_VBUS_OFF_for_tVBUSOFF_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAD_Debounce_VBUS_OFF_for_tVBUSOFF_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAE_Debounce_VCONN_ON_for_tVCONNON_ADDR 0x1100AAAC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAE_Debounce_VCONN_ON_for_tVCONNON_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAE_Debounce_VCONN_ON_for_tVCONNON_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAF_Debounce_VCONN_OFF_for_tVCONNOFF_ADDR 0x1100AAAC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAF_Debounce_VCONN_OFF_for_tVCONNOFF_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DAF_Debounce_VCONN_OFF_for_tVCONNOFF_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB0_reg_cc_chg_cnt_ADDR 0x1100AAB0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB0_reg_cc_chg_cnt_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB0_reg_cc_chg_cnt_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB1_reg_cc_vol_chg_thd_ADDR 0x1100AAB0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB1_reg_cc_vol_chg_thd_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB1_reg_cc_vol_chg_thd_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB2_Reserved_ADDR 0x1100AAB0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB2_Reserved_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB2_Reserved_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB3_CCDET_test_signal_index_ADDR 0x1100AAB0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB3_CCDET_test_signal_index_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB3_CCDET_test_signal_index_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB4_DRP_PERIOD_ADDR 0x1100AAB4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB4_DRP_PERIOD_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB4_DRP_PERIOD_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB5_DRP_DUTY_ADDR 0x1100AAB4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB5_DRP_DUTY_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB5_DRP_DUTY_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB6_DRP_HOLD_ADDR 0x1100AAB4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB6_DRP_HOLD_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB6_DRP_HOLD_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB7_DRP_LOCK_ADDR 0x1100AAB4
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB7_DRP_LOCK_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DB7_DRP_LOCK_BITEND 31

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCC_Reserved_ADDR 0x1100AACC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCC_Reserved_BITSTART 0
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCC_Reserved_BITEND 7

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_ADDR 0x1100AACC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_BITSTART 8
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_BITEND 15

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_ADDR 0x1100AACC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITSTART 16
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITEND 23

#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCF_IRQ_mask_for_connection_detection_FSM_ADDR 0x1100AACC
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCF_IRQ_mask_for_connection_detection_FSM_BITSTART 24
#define HS_Standby__usb_typec_1_01__REG_01_RW_2DCF_IRQ_mask_for_connection_detection_FSM_BITEND 31

#define HS_Standby__usb_typec_top_01__01_rstn_peri_ADDR 0x1100AB00
#define HS_Standby__usb_typec_top_01__01_rstn_peri_BITSTART 0
#define HS_Standby__usb_typec_top_01__01_rstn_peri_BITEND 0

#define HS_Standby__usb_typec_top_01__01_rstn_ccdet_ADDR 0x1100AB00
#define HS_Standby__usb_typec_top_01__01_rstn_ccdet_BITSTART 1
#define HS_Standby__usb_typec_top_01__01_rstn_ccdet_BITEND 1

#define HS_Standby__usb_typec_top_01__01_rstn_usbpd_ADDR 0x1100AB00
#define HS_Standby__usb_typec_top_01__01_rstn_usbpd_BITSTART 2
#define HS_Standby__usb_typec_top_01__01_rstn_usbpd_BITEND 2

#define HS_Standby__usb_typec_top_01__01_SENSE2A_SEL_ADDR 0x1100AB00
#define HS_Standby__usb_typec_top_01__01_SENSE2A_SEL_BITSTART 26
#define HS_Standby__usb_typec_top_01__01_SENSE2A_SEL_BITEND 26

#define HS_Standby__usb_typec_top_01__01_SENSE2A_FW_ADDR 0x1100AB00
#define HS_Standby__usb_typec_top_01__01_SENSE2A_FW_BITSTART 27
#define HS_Standby__usb_typec_top_01__01_SENSE2A_FW_BITEND 27

#define HS_Standby__usb_typec_top_01__reg_01_cc1_rd_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rd_en_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rd_en_BITEND 0

#define HS_Standby__usb_typec_top_01__reg_01_cc2_rd_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rd_en_BITSTART 1
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rd_en_BITEND 1

#define HS_Standby__usb_typec_top_01__reg_01_cc1_rp_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rp_en_BITSTART 2
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rp_en_BITEND 2

#define HS_Standby__usb_typec_top_01__reg_01_cc2_rp_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rp_en_BITSTART 3
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rp_en_BITEND 3

#define HS_Standby__usb_typec_top_01__reg_01_cc1_vconn_sel_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc1_vconn_sel_BITSTART 4
#define HS_Standby__usb_typec_top_01__reg_01_cc1_vconn_sel_BITEND 4

#define HS_Standby__usb_typec_top_01__reg_01_cc2_vconn_sel_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc2_vconn_sel_BITSTART 5
#define HS_Standby__usb_typec_top_01__reg_01_cc2_vconn_sel_BITEND 5

#define HS_Standby__usb_typec_top_01__reg_01_cc1_det_2bit_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc1_det_2bit_en_BITSTART 6
#define HS_Standby__usb_typec_top_01__reg_01_cc1_det_2bit_en_BITEND 6

#define HS_Standby__usb_typec_top_01__reg_01_cc2_det_2bit_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_cc2_det_2bit_en_BITSTART 7
#define HS_Standby__usb_typec_top_01__reg_01_cc2_det_2bit_en_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_sw_ctrl_rd_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_sw_ctrl_rd_en_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_sw_ctrl_rd_en_BITEND 8

#define HS_Standby__usb_typec_top_01__reg_01_sw_ctrl_rp_en_ADDR 0x1100AB04
#define HS_Standby__usb_typec_top_01__reg_01_sw_ctrl_rp_en_BITSTART 9
#define HS_Standby__usb_typec_top_01__reg_01_sw_ctrl_rp_en_BITEND 9

#define HS_Standby__usb_typec_top_01__reg_01_power_role_state_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_power_role_state_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_power_role_state_BITEND 1

#define HS_Standby__usb_typec_top_01__reg_01_drp_preference_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_drp_preference_BITSTART 2
#define HS_Standby__usb_typec_top_01__reg_01_drp_preference_BITEND 2

#define HS_Standby__usb_typec_top_01__reg_01_self_powered_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_self_powered_BITSTART 3
#define HS_Standby__usb_typec_top_01__reg_01_self_powered_BITEND 3

#define HS_Standby__usb_typec_top_01__reg_01_accessory_support_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_accessory_support_BITSTART 4
#define HS_Standby__usb_typec_top_01__reg_01_accessory_support_BITEND 4

#define HS_Standby__usb_typec_top_01__reg_01_audio_accessory_support_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_audio_accessory_support_BITSTART 5
#define HS_Standby__usb_typec_top_01__reg_01_audio_accessory_support_BITEND 5

#define HS_Standby__usb_typec_top_01__reg_01_debug_accessory_support_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_debug_accessory_support_BITSTART 6
#define HS_Standby__usb_typec_top_01__reg_01_debug_accessory_support_BITEND 6

#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_accessory_support_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_accessory_support_BITSTART 7
#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_accessory_support_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_pd_support_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_pd_support_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_pd_support_BITEND 8

#define HS_Standby__usb_typec_top_01__reg_01_try_src_support_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_try_src_support_BITSTART 9
#define HS_Standby__usb_typec_top_01__reg_01_try_src_support_BITEND 9

#define HS_Standby__usb_typec_top_01__reg_01_try_snk_support_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_try_snk_support_BITSTART 10
#define HS_Standby__usb_typec_top_01__reg_01_try_snk_support_BITEND 10

#define HS_Standby__usb_typec_top_01__reg_01_vbus_operating_mode_ADDR 0x1100AB08
#define HS_Standby__usb_typec_top_01__reg_01_vbus_operating_mode_BITSTART 11
#define HS_Standby__usb_typec_top_01__reg_01_vbus_operating_mode_BITEND 11

#define HS_Standby__usb_typec_top_01__reg_01_vbus_on_thd_ADDR 0x1100AB10
#define HS_Standby__usb_typec_top_01__reg_01_vbus_on_thd_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_vbus_on_thd_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_vbus_off_thd_ADDR 0x1100AB10
#define HS_Standby__usb_typec_top_01__reg_01_vbus_off_thd_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_vbus_off_thd_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_vconn_on_thd_ADDR 0x1100AB14
#define HS_Standby__usb_typec_top_01__reg_01_vconn_on_thd_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_vconn_on_thd_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_vconn_off_thd_ADDR 0x1100AB14
#define HS_Standby__usb_typec_top_01__reg_01_vconn_off_thd_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_vconn_off_thd_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_vsink_disconnect_vol_ADDR 0x1100AB18
#define HS_Standby__usb_typec_top_01__reg_01_vsink_disconnect_vol_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_vsink_disconnect_vol_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_vsink_disconnect_pd_vol_ADDR 0x1100AB18
#define HS_Standby__usb_typec_top_01__reg_01_vsink_disconnect_pd_vol_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_vsink_disconnect_pd_vol_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_vsafe0v_ADDR 0x1100AB18
#define HS_Standby__usb_typec_top_01__reg_01_vsafe0v_BITSTART 16
#define HS_Standby__usb_typec_top_01__reg_01_vsafe0v_BITEND 23

#define HS_Standby__usb_typec_top_01__reg_01_vvconn_disconnect_vol_ADDR 0x1100AB18
#define HS_Standby__usb_typec_top_01__reg_01_vvconn_disconnect_vol_BITSTART 24
#define HS_Standby__usb_typec_top_01__reg_01_vvconn_disconnect_vol_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_vvconn_discharge_vol_ADDR 0x1100AB1C
#define HS_Standby__usb_typec_top_01__reg_01_vvconn_discharge_vol_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_vvconn_discharge_vol_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_vrd_usb_vol_ADDR 0x1100AB1C
#define HS_Standby__usb_typec_top_01__reg_01_vrd_usb_vol_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_vrd_usb_vol_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_ra_threshold_ADDR 0x1100AB20
#define HS_Standby__usb_typec_top_01__reg_01_ra_threshold_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_ra_threshold_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_rd_threshold_ADDR 0x1100AB20
#define HS_Standby__usb_typec_top_01__reg_01_rd_threshold_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_rd_threshold_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_sink_con_threshold_ADDR 0x1100AB20
#define HS_Standby__usb_typec_top_01__reg_01_sink_con_threshold_BITSTART 16
#define HS_Standby__usb_typec_top_01__reg_01_sink_con_threshold_BITEND 23

#define HS_Standby__usb_typec_top_01__reg_01_cc_adc_in_db_ADDR 0x1100AB20
#define HS_Standby__usb_typec_top_01__reg_01_cc_adc_in_db_BITSTART 24
#define HS_Standby__usb_typec_top_01__reg_01_cc_adc_in_db_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_delay_cnt_ADDR 0x1100AB24
#define HS_Standby__usb_typec_top_01__reg_01_delay_cnt_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_delay_cnt_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_typec_vbus_value_ADDR 0x1100AB28
#define HS_Standby__usb_typec_top_01__reg_01_typec_vbus_value_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_typec_vbus_value_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_typec_vbus_sel_ADDR 0x1100AB28
#define HS_Standby__usb_typec_top_01__reg_01_typec_vbus_sel_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_typec_vbus_sel_BITEND 8

#define HS_Standby__usb_typec_top_01__reg_01_clk_freq_ADDR 0x1100AB30
#define HS_Standby__usb_typec_top_01__reg_01_clk_freq_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_clk_freq_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_terror_recovery_ADDR 0x1100AB30
#define HS_Standby__usb_typec_top_01__reg_01_terror_recovery_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_terror_recovery_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_tccdebounce_ADDR 0x1100AB30
#define HS_Standby__usb_typec_top_01__reg_01_tccdebounce_BITSTART 16
#define HS_Standby__usb_typec_top_01__reg_01_tccdebounce_BITEND 23

#define HS_Standby__usb_typec_top_01__reg_01_tpddebounce_ADDR 0x1100AB30
#define HS_Standby__usb_typec_top_01__reg_01_tpddebounce_BITSTART 24
#define HS_Standby__usb_typec_top_01__reg_01_tpddebounce_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_ttryccdebounce_ADDR 0x1100AB34
#define HS_Standby__usb_typec_top_01__reg_01_ttryccdebounce_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_ttryccdebounce_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_tdrp_ADDR 0x1100AB34
#define HS_Standby__usb_typec_top_01__reg_01_tdrp_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_tdrp_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_dcsrc_drp_ADDR 0x1100AB34
#define HS_Standby__usb_typec_top_01__reg_01_dcsrc_drp_BITSTART 16
#define HS_Standby__usb_typec_top_01__reg_01_dcsrc_drp_BITEND 23

#define HS_Standby__usb_typec_top_01__reg_01_tdrptry_ADDR 0x1100AB34
#define HS_Standby__usb_typec_top_01__reg_01_tdrptry_BITSTART 24
#define HS_Standby__usb_typec_top_01__reg_01_tdrptry_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_tdrptrywait_ADDR 0x1100AB38
#define HS_Standby__usb_typec_top_01__reg_01_tdrptrywait_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_tdrptrywait_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_ttrytimeout_ADDR 0x1100AB38
#define HS_Standby__usb_typec_top_01__reg_01_ttrytimeout_BITSTART 16
#define HS_Standby__usb_typec_top_01__reg_01_ttrytimeout_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_cmd_direct_ADDR 0x1100AB3C
#define HS_Standby__usb_typec_top_01__reg_01_cmd_direct_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_cmd_direct_BITEND 4

#define HS_Standby__usb_typec_top_01__reg_01_cmd_direct_en_ADDR 0x1100AB3C
#define HS_Standby__usb_typec_top_01__reg_01_cmd_direct_en_BITSTART 5
#define HS_Standby__usb_typec_top_01__reg_01_cmd_direct_en_BITEND 6

#define HS_Standby__usb_typec_top_01__reg_01_source_vconn_supply_ADDR 0x1100AB3C
#define HS_Standby__usb_typec_top_01__reg_01_source_vconn_supply_BITSTART 7
#define HS_Standby__usb_typec_top_01__reg_01_source_vconn_supply_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_oriention_required_ADDR 0x1100AB3C
#define HS_Standby__usb_typec_top_01__reg_01_oriention_required_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_oriention_required_BITEND 8

#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_acc_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_acc_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_acc_BITEND 0

#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_dev_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_dev_BITSTART 1
#define HS_Standby__usb_typec_top_01__reg_01_vconn_powered_dev_BITEND 1

#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_inflow_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_inflow_BITSTART 2
#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_inflow_BITEND 2

#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_rdy_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_rdy_BITSTART 3
#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_rdy_BITEND 3

#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_accept_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_accept_BITSTART 4
#define HS_Standby__usb_typec_top_01__reg_01_pr_swap_accept_BITEND 4

#define HS_Standby__usb_typec_top_01__reg_01_drp_toggle_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_drp_toggle_BITSTART 5
#define HS_Standby__usb_typec_top_01__reg_01_drp_toggle_BITEND 5

#define HS_Standby__usb_typec_top_01__reg_01_attached_vconn_powered_acc_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_attached_vconn_powered_acc_BITSTART 6
#define HS_Standby__usb_typec_top_01__reg_01_attached_vconn_powered_acc_BITEND 6

#define HS_Standby__usb_typec_top_01__reg_01_attached_vconn_powered_dev_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_attached_vconn_powered_dev_BITSTART 7
#define HS_Standby__usb_typec_top_01__reg_01_attached_vconn_powered_dev_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_dev_enter_alternate_success_ADDR 0x1100AB40
#define HS_Standby__usb_typec_top_01__reg_01_dev_enter_alternate_success_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_dev_enter_alternate_success_BITEND 8

#define HS_Standby__usb_typec_top_01__regr_01_vbus_value_ADDR 0x1100AB44
#define HS_Standby__usb_typec_top_01__regr_01_vbus_value_BITSTART 0
#define HS_Standby__usb_typec_top_01__regr_01_vbus_value_BITEND 7

#define HS_Standby__usb_typec_top_01__regr_01_vconn_value_ADDR 0x1100AB44
#define HS_Standby__usb_typec_top_01__regr_01_vconn_value_BITSTART 16
#define HS_Standby__usb_typec_top_01__regr_01_vconn_value_BITEND 27

#define HS_Standby__usb_typec_top_01__regr_01_cc1_adc_in_ADDR 0x1100AB48
#define HS_Standby__usb_typec_top_01__regr_01_cc1_adc_in_BITSTART 0
#define HS_Standby__usb_typec_top_01__regr_01_cc1_adc_in_BITEND 11

#define HS_Standby__usb_typec_top_01__regr_01_cc2_adc_in_ADDR 0x1100AB48
#define HS_Standby__usb_typec_top_01__regr_01_cc2_adc_in_BITSTART 16
#define HS_Standby__usb_typec_top_01__regr_01_cc2_adc_in_BITEND 27

#define HS_Standby__usb_typec_top_01__regr_01_state_c_ADDR 0x1100AB4C
#define HS_Standby__usb_typec_top_01__regr_01_state_c_BITSTART 0
#define HS_Standby__usb_typec_top_01__regr_01_state_c_BITEND 4

#define HS_Standby__usb_typec_top_01__regr_01_cc_turn_on_vbus_ADDR 0x1100AB4C
#define HS_Standby__usb_typec_top_01__regr_01_cc_turn_on_vbus_BITSTART 8
#define HS_Standby__usb_typec_top_01__regr_01_cc_turn_on_vbus_BITEND 8

#define HS_Standby__usb_typec_top_01__regr_01_cc1_turn_on_vconn_ADDR 0x1100AB4C
#define HS_Standby__usb_typec_top_01__regr_01_cc1_turn_on_vconn_BITSTART 9
#define HS_Standby__usb_typec_top_01__regr_01_cc1_turn_on_vconn_BITEND 9

#define HS_Standby__usb_typec_top_01__regr_01_cc2_turn_on_vconn_ADDR 0x1100AB4C
#define HS_Standby__usb_typec_top_01__regr_01_cc2_turn_on_vconn_BITSTART 10
#define HS_Standby__usb_typec_top_01__regr_01_cc2_turn_on_vconn_BITEND 10

#define HS_Standby__usb_typec_top_01__regr_01_cc1_resistance_ADDR 0x1100AB4C
#define HS_Standby__usb_typec_top_01__regr_01_cc1_resistance_BITSTART 11
#define HS_Standby__usb_typec_top_01__regr_01_cc1_resistance_BITEND 13

#define HS_Standby__usb_typec_top_01__regr_01_cc2_resistance_ADDR 0x1100AB4C
#define HS_Standby__usb_typec_top_01__regr_01_cc2_resistance_BITSTART 14
#define HS_Standby__usb_typec_top_01__regr_01_cc2_resistance_BITEND 16

#define HS_Standby__usb_typec_top_01__reg_01_res_en_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_res_en_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_res_en_BITEND 0

#define HS_Standby__usb_typec_top_01__reg_01_res_seta_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_res_seta_BITSTART 1
#define HS_Standby__usb_typec_top_01__reg_01_res_seta_BITEND 1

#define HS_Standby__usb_typec_top_01__reg_01_res_setb_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_res_setb_BITSTART 2
#define HS_Standby__usb_typec_top_01__reg_01_res_setb_BITEND 2

#define HS_Standby__usb_typec_top_01__reg_01_aux_pn_set_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_aux_pn_set_BITSTART 3
#define HS_Standby__usb_typec_top_01__reg_01_aux_pn_set_BITEND 3

#define HS_Standby__usb_typec_top_01__reg_01_cc1_rd_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rd_BITSTART 4
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rd_BITEND 4

#define HS_Standby__usb_typec_top_01__reg_01_cc2_rd_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rd_BITSTART 5
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rd_BITEND 5

#define HS_Standby__usb_typec_top_01__reg_01_cc1_von_sw_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc1_von_sw_BITSTART 6
#define HS_Standby__usb_typec_top_01__reg_01_cc1_von_sw_BITEND 6

#define HS_Standby__usb_typec_top_01__reg_01_cc2_von_sw_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc2_von_sw_BITSTART 7
#define HS_Standby__usb_typec_top_01__reg_01_cc2_von_sw_BITEND 7

#define HS_Standby__usb_typec_top_01__reg_01_discha_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_discha_BITSTART 8
#define HS_Standby__usb_typec_top_01__reg_01_discha_BITEND 8

#define HS_Standby__usb_typec_top_01__reg_01_vbus_pmu_en_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_vbus_pmu_en_BITSTART 9
#define HS_Standby__usb_typec_top_01__reg_01_vbus_pmu_en_BITEND 9

#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_BITSTART 10
#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_BITEND 10

#define HS_Standby__usb_typec_top_01__reg_01_cc1_disable_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc1_disable_BITSTART 11
#define HS_Standby__usb_typec_top_01__reg_01_cc1_disable_BITEND 12

#define HS_Standby__usb_typec_top_01__reg_01_cc2_disable_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc2_disable_BITSTART 13
#define HS_Standby__usb_typec_top_01__reg_01_cc2_disable_BITEND 14

#define HS_Standby__usb_typec_top_01__reg_01_cc1_tx_bmc_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc1_tx_bmc_BITSTART 15
#define HS_Standby__usb_typec_top_01__reg_01_cc1_tx_bmc_BITEND 16

#define HS_Standby__usb_typec_top_01__reg_01_cc2_tx_bmc_ADDR 0x1100AB50
#define HS_Standby__usb_typec_top_01__reg_01_cc2_tx_bmc_BITSTART 17
#define HS_Standby__usb_typec_top_01__reg_01_cc2_tx_bmc_BITEND 18

#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_drp_noreal_chip_ADDR 0x1100AB54
#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_drp_noreal_chip_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_drp_noreal_chip_BITEND 0

#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_drp_real_chip_ADDR 0x1100AB54
#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_drp_real_chip_BITSTART 1
#define HS_Standby__usb_typec_top_01__reg_01_cc_rp_en_drp_real_chip_BITEND 1

#define HS_Standby__usb_typec_top_01__reg_01_pattern_en_ADDR 0x1100AB60
#define HS_Standby__usb_typec_top_01__reg_01_pattern_en_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_pattern_en_BITEND 0

#define HS_Standby__usb_typec_top_01__reg_01_unuse0_ADDR 0x1100ABA0
#define HS_Standby__usb_typec_top_01__reg_01_unuse0_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_unuse0_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_unuse1_ADDR 0x1100ABA4
#define HS_Standby__usb_typec_top_01__reg_01_unuse1_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_unuse1_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_unuse2_ADDR 0x1100ABA8
#define HS_Standby__usb_typec_top_01__reg_01_unuse2_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_unuse2_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_pd_bg_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_pd_bg_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_pd_bg_BITEND 0

#define HS_Standby__usb_typec_top_01__reg_01_pd_bginr_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_pd_bginr_BITSTART 1
#define HS_Standby__usb_typec_top_01__reg_01_pd_bginr_BITEND 1

#define HS_Standby__usb_typec_top_01__reg_01_sw_datalen_en_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_sw_datalen_en_BITSTART 2
#define HS_Standby__usb_typec_top_01__reg_01_sw_datalen_en_BITEND 2

#define HS_Standby__usb_typec_top_01__reg_01_sw_datalen_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_sw_datalen_BITSTART 4
#define HS_Standby__usb_typec_top_01__reg_01_sw_datalen_BITEND 13

#define HS_Standby__usb_typec_top_01__reg_01_sw_ctr_extendmsg_en_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_sw_ctr_extendmsg_en_BITSTART 14
#define HS_Standby__usb_typec_top_01__reg_01_sw_ctr_extendmsg_en_BITEND 14

#define HS_Standby__usb_typec_top_01__reg_01_discard_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_discard_BITSTART 15
#define HS_Standby__usb_typec_top_01__reg_01_discard_BITEND 15

#define HS_Standby__usb_typec_top_01__reg_01_spikesize_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_spikesize_BITSTART 16
#define HS_Standby__usb_typec_top_01__reg_01_spikesize_BITEND 20

#define HS_Standby__usb_typec_top_01__reg_01_delta_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_delta_BITSTART 24
#define HS_Standby__usb_typec_top_01__reg_01_delta_BITEND 28

#define HS_Standby__usb_typec_top_01__reg_01_cc1_rprd_keep_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rprd_keep_BITSTART 29
#define HS_Standby__usb_typec_top_01__reg_01_cc1_rprd_keep_BITEND 29

#define HS_Standby__usb_typec_top_01__reg_01_cc2_rprd_keep_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rprd_keep_BITSTART 30
#define HS_Standby__usb_typec_top_01__reg_01_cc2_rprd_keep_BITEND 30

#define HS_Standby__usb_typec_top_01__reg_01_cc_state_keep_ADDR 0x1100ABAC
#define HS_Standby__usb_typec_top_01__reg_01_cc_state_keep_BITSTART 31
#define HS_Standby__usb_typec_top_01__reg_01_cc_state_keep_BITEND 31

#define HS_Standby__usb_typec_top_01__reg_01_msg_recv_irq_fake_ADDR 0x1100ABB0
#define HS_Standby__usb_typec_top_01__reg_01_msg_recv_irq_fake_BITSTART 0
#define HS_Standby__usb_typec_top_01__reg_01_msg_recv_irq_fake_BITEND 0

#define HS_Standby__usb_typec_top_01__reg_01_channel_busy_irq_fake_ADDR 0x1100ABB0
#define HS_Standby__usb_typec_top_01__reg_01_channel_busy_irq_fake_BITSTART 1
#define HS_Standby__usb_typec_top_01__reg_01_channel_busy_irq_fake_BITEND 1

#define HS_Standby__usb_typec_top_01__reg_01_preamble_det_irq_fake_ADDR 0x1100ABB0
#define HS_Standby__usb_typec_top_01__reg_01_preamble_det_irq_fake_BITSTART 2
#define HS_Standby__usb_typec_top_01__reg_01_preamble_det_irq_fake_BITEND 2

#define HS_Standby__usb_typec_top_01__reg_01_dfp_attach_chg_irq_fake_ADDR 0x1100ABB0
#define HS_Standby__usb_typec_top_01__reg_01_dfp_attach_chg_irq_fake_BITSTART 3
#define HS_Standby__usb_typec_top_01__reg_01_dfp_attach_chg_irq_fake_BITEND 3

#define HS_Standby__usb_typec_top_01__reg_01_ufp_attach_chg_irq_fake_ADDR 0x1100ABB0
#define HS_Standby__usb_typec_top_01__reg_01_ufp_attach_chg_irq_fake_BITSTART 4
#define HS_Standby__usb_typec_top_01__reg_01_ufp_attach_chg_irq_fake_BITEND 4

#define HS_Standby__usb_typec_top_01__reg_01_ufp_attach_irq_fake_ADDR 0x1100ABB0
#define HS_Standby__usb_typec_top_01__reg_01_ufp_attach_irq_fake_BITSTART 5
#define HS_Standby__usb_typec_top_01__reg_01_ufp_attach_irq_fake_BITEND 5

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_en_ADDR 0x1100AC00
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_en_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_en_BITEND 0

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_pat_sel_ADDR 0x1100AC00
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_pat_sel_BITSTART 1
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_pat_sel_BITEND 4

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_precoder_en_ADDR 0x1100AC00
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_precoder_en_BITSTART 5
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_precoder_en_BITEND 5

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_gray_coding_value_ADDR 0x1100AC00
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_gray_coding_value_BITSTART 6
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_gray_coding_value_BITEND 13

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_0_ADDR 0x1100AC04
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_0_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_0_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_1_ADDR 0x1100AC08
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_1_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_1_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_2_ADDR 0x1100AC0C
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_2_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_2_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_3_ADDR 0x1100AC10
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_3_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_3_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_4_ADDR 0x1100AC14
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_4_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data0_4_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_0_ADDR 0x1100AC18
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_0_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_0_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_1_ADDR 0x1100AC1C
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_1_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_1_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_2_ADDR 0x1100AC20
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_2_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_2_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_3_ADDR 0x1100AC24
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_3_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_3_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_4_ADDR 0x1100AC28
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_4_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data1_4_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_0_ADDR 0x1100AC2C
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_0_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_0_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_1_ADDR 0x1100AC30
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_1_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_1_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_2_ADDR 0x1100AC34
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_2_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_2_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_3_ADDR 0x1100AC38
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_3_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_3_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_4_ADDR 0x1100AC3C
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_4_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_tx_prbs_data2_4_BITEND 31

#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_en_ADDR 0x1100AC50
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_en_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_en_BITEND 0

#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_mon_sel_ADDR 0x1100AC50
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_mon_sel_BITSTART 8
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_mon_sel_BITEND 9

#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_pat_sel_ADDR 0x1100AC54
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_pat_sel_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_pat_sel_BITEND 3

#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_ucnt_time_ADDR 0x1100AC54
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_ucnt_time_BITSTART 8
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_ucnt_time_BITEND 17

#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_mcnt_time_ADDR 0x1100AC54
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_mcnt_time_BITSTART 18
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_mcnt_time_BITEND 27

#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_match_sel_ADDR 0x1100AC54
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_match_sel_BITSTART 28
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_match_sel_BITEND 29

#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_match_thd_ADDR 0x1100AC58
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_match_thd_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__reg_01_rx_prbs_20b_match_thd_BITEND 5

#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_1us_ADDR 0x1100AC5C
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_1us_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_1us_BITEND 14

#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_locked_ADDR 0x1100AC5C
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_locked_BITSTART 16
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_locked_BITEND 16

#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_alllane_ADDR 0x1100AC5C
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_alllane_BITSTART 17
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_alllane_BITEND 20

#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_1ms_ADDR 0x1100AC60
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_1ms_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_1ms_BITEND 24

#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_total_ADDR 0x1100AC64
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_total_BITSTART 0
#define HS_Standby__typec_prbs_pattern_01__regr_01_rx_prbs_20b_error_total_BITEND 31

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adc_brige_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adc_brige_BITSTART 0
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adc_brige_BITEND 3

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adcib_comp_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adcib_comp_BITSTART 4
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adcib_comp_BITEND 5

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adcpulse_mode_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adcpulse_mode_BITSTART 6
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_adcpulse_mode_BITEND 6

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_atestsel_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_atestsel_BITSTART 7
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_atestsel_BITEND 10

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_ccrxvrefh_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_ccrxvrefh_BITSTART 11
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_ccrxvrefh_BITEND 18

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_ccrxvrefl_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_ccrxvrefl_BITSTART 19
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_ccrxvrefl_BITEND 26

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_divsel_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_divsel_BITSTART 27
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_divsel_BITEND 28

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_pd_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_pd_BITSTART 29
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_pd_BITEND 29

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_radc_en_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_radc_en_BITSTART 30
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_radc_en_BITEND 30

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rd_deten_ADDR 0x1100AD00
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rd_deten_BITSTART 31
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rd_deten_BITEND 31

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_keep_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_keep_BITSTART 0
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_keep_BITEND 7

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rdtrim_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rdtrim_BITSTART 8
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rdtrim_BITEND 11

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rdtrim_sel_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rdtrim_sel_BITSTART 12
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rdtrim_sel_BITEND 12

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rptrim_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rptrim_BITSTART 13
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rptrim_BITEND 18

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_slpsel_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_slpsel_BITSTART 19
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_slpsel_BITEND 19

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p1_adj_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p1_adj_BITSTART 20
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p1_adj_BITEND 22

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p02_adj_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p02_adj_BITSTART 23
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p02_adj_BITEND 25

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p8_adj_ADDR 0x1100AD04
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p8_adj_BITSTART 26
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_v1p8_adj_BITEND 28

#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rdtrim_ADDR 0x1100AD08
#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rdtrim_BITSTART 0
#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rdtrim_BITEND 3

#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rd_cmpout_ADDR 0x1100AD08
#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rd_cmpout_BITSTART 4
#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rd_cmpout_BITEND 4

#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rdtrim_done_ADDR 0x1100AD08
#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rdtrim_done_BITSTART 5
#define HS_Standby__usb_typec_phy_top_01__regr_01_ccphy_rdtrim_done_BITEND 5

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rstn_cc_ADDR 0x1100AD10
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rstn_cc_BITSTART 0
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rstn_cc_BITEND 0

#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rstn_adc_ADDR 0x1100AD10
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rstn_adc_BITSTART 1
#define HS_Standby__usb_typec_phy_top_01__reg_01_ccphy_rstn_adc_BITEND 1

#define HS_Standby__usb_typec_phy_top_01__reg_01_din_rdtrim_start_ADDR 0x1100AD10
#define HS_Standby__usb_typec_phy_top_01__reg_01_din_rdtrim_start_BITSTART 2
#define HS_Standby__usb_typec_phy_top_01__reg_01_din_rdtrim_start_BITEND 2

#define HS_Standby__usb_typec_phy_top_01__reg_01_din_sleepmode_ADDR 0x1100AD10
#define HS_Standby__usb_typec_phy_top_01__reg_01_din_sleepmode_BITSTART 3
#define HS_Standby__usb_typec_phy_top_01__reg_01_din_sleepmode_BITEND 3

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_header_0_ADDR 0x1100AE00
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_header_0_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_header_0_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_header_1_ADDR 0x1100AE00
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_header_1_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_header_1_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_0_ADDR 0x1100AE00
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_1_ADDR 0x1100AE00
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_2_ADDR 0x1100AE04
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_3_ADDR 0x1100AE04
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_0_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_0_ADDR 0x1100AE04
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_1_ADDR 0x1100AE04
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_2_ADDR 0x1100AE08
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_3_ADDR 0x1100AE08
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_1_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_0_ADDR 0x1100AE08
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_1_ADDR 0x1100AE08
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_2_ADDR 0x1100AE0C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_3_ADDR 0x1100AE0C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_2_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_0_ADDR 0x1100AE0C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_1_ADDR 0x1100AE0C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_2_ADDR 0x1100AE10
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_3_ADDR 0x1100AE10
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_3_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_0_ADDR 0x1100AE10
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_1_ADDR 0x1100AE10
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_2_ADDR 0x1100AE14
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_3_ADDR 0x1100AE14
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_4_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_0_ADDR 0x1100AE14
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_1_ADDR 0x1100AE14
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_2_ADDR 0x1100AE18
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_3_ADDR 0x1100AE18
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_5_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_0_ADDR 0x1100AE18
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_1_ADDR 0x1100AE18
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_2_ADDR 0x1100AE1C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_3_ADDR 0x1100AE1C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_6_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_0_ADDR 0x1100AE1C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_1_ADDR 0x1100AE1C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_2_ADDR 0x1100AE20
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_3_ADDR 0x1100AE20
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_7_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_0_ADDR 0x1100AE20
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_1_ADDR 0x1100AE20
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_2_ADDR 0x1100AE24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_3_ADDR 0x1100AE24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_8_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_0_ADDR 0x1100AE24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_1_ADDR 0x1100AE24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_2_ADDR 0x1100AE28
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_3_ADDR 0x1100AE28
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_9_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_0_ADDR 0x1100AE28
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_1_ADDR 0x1100AE28
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_2_ADDR 0x1100AE2C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_3_ADDR 0x1100AE2C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_10_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_0_ADDR 0x1100AE2C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_1_ADDR 0x1100AE2C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_2_ADDR 0x1100AE30
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_3_ADDR 0x1100AE30
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_11_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_0_ADDR 0x1100AE30
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_1_ADDR 0x1100AE30
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_2_ADDR 0x1100AE34
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_3_ADDR 0x1100AE34
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_12_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_0_ADDR 0x1100AE34
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_1_ADDR 0x1100AE34
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_2_ADDR 0x1100AE38
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_3_ADDR 0x1100AE38
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_13_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_0_ADDR 0x1100AE38
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_1_ADDR 0x1100AE38
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_2_ADDR 0x1100AE3C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_3_ADDR 0x1100AE3C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_14_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_0_ADDR 0x1100AE3C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_1_ADDR 0x1100AE3C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_2_ADDR 0x1100AE40
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_3_ADDR 0x1100AE40
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_15_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_0_ADDR 0x1100AE40
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_1_ADDR 0x1100AE40
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_2_ADDR 0x1100AE44
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_3_ADDR 0x1100AE44
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_16_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_0_ADDR 0x1100AE44
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_1_ADDR 0x1100AE44
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_2_ADDR 0x1100AE48
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_3_ADDR 0x1100AE48
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_17_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_0_ADDR 0x1100AE48
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_1_ADDR 0x1100AE48
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_2_ADDR 0x1100AE4C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_3_ADDR 0x1100AE4C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_18_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_0_ADDR 0x1100AE4C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_1_ADDR 0x1100AE4C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_2_ADDR 0x1100AE50
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_3_ADDR 0x1100AE50
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_19_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_0_ADDR 0x1100AE50
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_1_ADDR 0x1100AE50
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_2_ADDR 0x1100AE54
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_3_ADDR 0x1100AE54
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_20_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_0_ADDR 0x1100AE54
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_1_ADDR 0x1100AE54
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_2_ADDR 0x1100AE58
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_3_ADDR 0x1100AE58
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_21_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_0_ADDR 0x1100AE58
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_1_ADDR 0x1100AE58
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_2_ADDR 0x1100AE5C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_3_ADDR 0x1100AE5C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_22_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_0_ADDR 0x1100AE5C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_1_ADDR 0x1100AE5C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_2_ADDR 0x1100AE60
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_3_ADDR 0x1100AE60
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_23_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_0_ADDR 0x1100AE60
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_1_ADDR 0x1100AE60
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_2_ADDR 0x1100AE64
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_3_ADDR 0x1100AE64
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_24_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_0_ADDR 0x1100AE64
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_1_ADDR 0x1100AE64
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_2_ADDR 0x1100AE68
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_3_ADDR 0x1100AE68
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_25_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_0_ADDR 0x1100AE68
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_1_ADDR 0x1100AE68
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_2_ADDR 0x1100AE6C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_3_ADDR 0x1100AE6C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_26_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_0_ADDR 0x1100AE6C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_1_ADDR 0x1100AE6C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_2_ADDR 0x1100AE70
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_3_ADDR 0x1100AE70
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_27_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_0_ADDR 0x1100AE70
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_1_ADDR 0x1100AE70
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_2_ADDR 0x1100AE74
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_3_ADDR 0x1100AE74
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_28_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_0_ADDR 0x1100AE74
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_1_ADDR 0x1100AE74
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_2_ADDR 0x1100AE78
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_3_ADDR 0x1100AE78
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_29_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_0_ADDR 0x1100AE78
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_1_ADDR 0x1100AE78
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_2_ADDR 0x1100AE7C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_3_ADDR 0x1100AE7C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_30_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_0_ADDR 0x1100AE7C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_1_ADDR 0x1100AE7C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_2_ADDR 0x1100AE80
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_3_ADDR 0x1100AE80
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_31_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_0_ADDR 0x1100AE80
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_1_ADDR 0x1100AE80
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_2_ADDR 0x1100AE84
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_3_ADDR 0x1100AE84
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_32_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_0_ADDR 0x1100AE84
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_1_ADDR 0x1100AE84
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_2_ADDR 0x1100AE88
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_3_ADDR 0x1100AE88
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_33_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_0_ADDR 0x1100AE88
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_1_ADDR 0x1100AE88
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_2_ADDR 0x1100AE8C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_3_ADDR 0x1100AE8C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_34_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_0_ADDR 0x1100AE8C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_1_ADDR 0x1100AE8C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_2_ADDR 0x1100AE90
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_3_ADDR 0x1100AE90
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_35_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_0_ADDR 0x1100AE90
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_1_ADDR 0x1100AE90
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_2_ADDR 0x1100AE94
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_3_ADDR 0x1100AE94
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_36_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_0_ADDR 0x1100AE94
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_1_ADDR 0x1100AE94
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_2_ADDR 0x1100AE98
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_3_ADDR 0x1100AE98
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_37_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_0_ADDR 0x1100AE98
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_1_ADDR 0x1100AE98
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_2_ADDR 0x1100AE9C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_3_ADDR 0x1100AE9C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_38_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_0_ADDR 0x1100AE9C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_1_ADDR 0x1100AE9C
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_2_ADDR 0x1100AEA0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_3_ADDR 0x1100AEA0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_39_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_0_ADDR 0x1100AEA0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_1_ADDR 0x1100AEA0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_2_ADDR 0x1100AEA4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_3_ADDR 0x1100AEA4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_40_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_0_ADDR 0x1100AEA4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_1_ADDR 0x1100AEA4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_2_ADDR 0x1100AEA8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_3_ADDR 0x1100AEA8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_41_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_0_ADDR 0x1100AEA8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_1_ADDR 0x1100AEA8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_2_ADDR 0x1100AEAC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_3_ADDR 0x1100AEAC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_42_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_0_ADDR 0x1100AEAC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_1_ADDR 0x1100AEAC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_2_ADDR 0x1100AEB0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_3_ADDR 0x1100AEB0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_43_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_0_ADDR 0x1100AEB0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_1_ADDR 0x1100AEB0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_2_ADDR 0x1100AEB4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_3_ADDR 0x1100AEB4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_44_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_0_ADDR 0x1100AEB4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_1_ADDR 0x1100AEB4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_2_ADDR 0x1100AEB8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_3_ADDR 0x1100AEB8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_45_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_0_ADDR 0x1100AEB8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_1_ADDR 0x1100AEB8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_2_ADDR 0x1100AEBC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_3_ADDR 0x1100AEBC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_46_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_0_ADDR 0x1100AEBC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_1_ADDR 0x1100AEBC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_2_ADDR 0x1100AEC0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_3_ADDR 0x1100AEC0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_47_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_0_ADDR 0x1100AEC0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_1_ADDR 0x1100AEC0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_2_ADDR 0x1100AEC4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_3_ADDR 0x1100AEC4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_48_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_0_ADDR 0x1100AEC4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_1_ADDR 0x1100AEC4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_2_ADDR 0x1100AEC8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_3_ADDR 0x1100AEC8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_49_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_0_ADDR 0x1100AEC8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_1_ADDR 0x1100AEC8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_2_ADDR 0x1100AECC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_3_ADDR 0x1100AECC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_50_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_0_ADDR 0x1100AECC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_1_ADDR 0x1100AECC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_2_ADDR 0x1100AED0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_3_ADDR 0x1100AED0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_51_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_0_ADDR 0x1100AED0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_1_ADDR 0x1100AED0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_2_ADDR 0x1100AED4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_3_ADDR 0x1100AED4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_52_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_0_ADDR 0x1100AED4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_1_ADDR 0x1100AED4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_2_ADDR 0x1100AED8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_3_ADDR 0x1100AED8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_53_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_0_ADDR 0x1100AED8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_1_ADDR 0x1100AED8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_2_ADDR 0x1100AEDC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_3_ADDR 0x1100AEDC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_54_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_0_ADDR 0x1100AEDC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_1_ADDR 0x1100AEDC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_2_ADDR 0x1100AEE0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_3_ADDR 0x1100AEE0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_55_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_0_ADDR 0x1100AEE0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_1_ADDR 0x1100AEE0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_2_ADDR 0x1100AEE4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_3_ADDR 0x1100AEE4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_56_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_0_ADDR 0x1100AEE4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_1_ADDR 0x1100AEE4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_2_ADDR 0x1100AEE8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_3_ADDR 0x1100AEE8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_57_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_0_ADDR 0x1100AEE8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_1_ADDR 0x1100AEE8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_2_ADDR 0x1100AEEC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_3_ADDR 0x1100AEEC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_58_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_0_ADDR 0x1100AEEC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_1_ADDR 0x1100AEEC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_2_ADDR 0x1100AEF0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_3_ADDR 0x1100AEF0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_59_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_0_ADDR 0x1100AEF0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_1_ADDR 0x1100AEF0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_2_ADDR 0x1100AEF4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_3_ADDR 0x1100AEF4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_60_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_0_ADDR 0x1100AEF4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_1_ADDR 0x1100AEF4
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_2_ADDR 0x1100AEF8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_3_ADDR 0x1100AEF8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_61_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_0_ADDR 0x1100AEF8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_1_ADDR 0x1100AEF8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_1_BITEND 31

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_2_ADDR 0x1100AEFC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_2_BITEND 7

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_3_ADDR 0x1100AEFC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_62_3_BITEND 15

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_63_0_ADDR 0x1100AEFC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_63_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_63_0_BITEND 23

#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_63_1_ADDR 0x1100AEFC
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_63_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_0_reg_01__reg_01_tx_msg_data_object_63_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_63_2_ADDR 0x1100AF00
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_63_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_63_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_63_3_ADDR 0x1100AF00
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_63_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_63_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_0_ADDR 0x1100AF00
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_1_ADDR 0x1100AF00
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_2_ADDR 0x1100AF04
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_3_ADDR 0x1100AF04
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_64_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_0_ADDR 0x1100AF04
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_1_ADDR 0x1100AF04
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_2_ADDR 0x1100AF08
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_3_ADDR 0x1100AF08
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_65_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_0_ADDR 0x1100AF08
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_1_ADDR 0x1100AF08
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_2_ADDR 0x1100AF0C
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_3_ADDR 0x1100AF0C
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_66_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_0_ADDR 0x1100AF0C
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_1_ADDR 0x1100AF0C
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_2_ADDR 0x1100AF10
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_3_ADDR 0x1100AF10
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_67_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_0_ADDR 0x1100AF10
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_1_ADDR 0x1100AF10
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_1_BITEND 31

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_2_ADDR 0x1100AF14
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_2_BITSTART 0
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_2_BITEND 7

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_3_ADDR 0x1100AF14
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_3_BITSTART 8
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_68_3_BITEND 15

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_69_0_ADDR 0x1100AF14
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_69_0_BITSTART 16
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_69_0_BITEND 23

#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_69_1_ADDR 0x1100AF14
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_69_1_BITSTART 24
#define HS_Standby__usb_typec_txdata_1_reg_01__reg_01_tx_msg_data_object_69_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_header_0_ADDR 0x1100B000
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_header_0_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_header_0_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_header_1_ADDR 0x1100B000
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_header_1_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_header_1_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_0_ADDR 0x1100B000
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_1_ADDR 0x1100B000
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_2_ADDR 0x1100B004
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_3_ADDR 0x1100B004
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_0_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_0_ADDR 0x1100B004
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_1_ADDR 0x1100B004
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_2_ADDR 0x1100B008
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_3_ADDR 0x1100B008
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_1_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_0_ADDR 0x1100B008
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_1_ADDR 0x1100B008
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_2_ADDR 0x1100B00C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_3_ADDR 0x1100B00C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_2_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_0_ADDR 0x1100B00C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_1_ADDR 0x1100B00C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_2_ADDR 0x1100B010
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_3_ADDR 0x1100B010
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_3_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_0_ADDR 0x1100B010
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_1_ADDR 0x1100B010
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_2_ADDR 0x1100B014
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_3_ADDR 0x1100B014
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_4_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_0_ADDR 0x1100B014
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_1_ADDR 0x1100B014
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_2_ADDR 0x1100B018
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_3_ADDR 0x1100B018
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_5_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_0_ADDR 0x1100B018
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_1_ADDR 0x1100B018
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_2_ADDR 0x1100B01C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_3_ADDR 0x1100B01C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_6_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_0_ADDR 0x1100B01C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_1_ADDR 0x1100B01C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_2_ADDR 0x1100B020
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_3_ADDR 0x1100B020
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_7_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_0_ADDR 0x1100B020
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_1_ADDR 0x1100B020
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_2_ADDR 0x1100B024
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_3_ADDR 0x1100B024
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_8_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_0_ADDR 0x1100B024
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_1_ADDR 0x1100B024
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_2_ADDR 0x1100B028
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_3_ADDR 0x1100B028
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_9_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_0_ADDR 0x1100B028
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_1_ADDR 0x1100B028
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_2_ADDR 0x1100B02C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_3_ADDR 0x1100B02C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_10_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_0_ADDR 0x1100B02C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_1_ADDR 0x1100B02C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_2_ADDR 0x1100B030
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_3_ADDR 0x1100B030
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_11_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_0_ADDR 0x1100B030
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_1_ADDR 0x1100B030
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_2_ADDR 0x1100B034
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_3_ADDR 0x1100B034
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_12_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_0_ADDR 0x1100B034
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_1_ADDR 0x1100B034
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_2_ADDR 0x1100B038
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_3_ADDR 0x1100B038
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_13_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_0_ADDR 0x1100B038
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_1_ADDR 0x1100B038
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_2_ADDR 0x1100B03C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_3_ADDR 0x1100B03C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_14_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_0_ADDR 0x1100B03C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_1_ADDR 0x1100B03C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_2_ADDR 0x1100B040
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_3_ADDR 0x1100B040
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_15_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_0_ADDR 0x1100B040
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_1_ADDR 0x1100B040
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_2_ADDR 0x1100B044
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_3_ADDR 0x1100B044
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_16_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_0_ADDR 0x1100B044
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_1_ADDR 0x1100B044
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_2_ADDR 0x1100B048
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_3_ADDR 0x1100B048
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_17_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_0_ADDR 0x1100B048
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_1_ADDR 0x1100B048
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_2_ADDR 0x1100B04C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_3_ADDR 0x1100B04C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_18_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_0_ADDR 0x1100B04C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_1_ADDR 0x1100B04C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_2_ADDR 0x1100B050
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_3_ADDR 0x1100B050
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_19_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_0_ADDR 0x1100B050
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_1_ADDR 0x1100B050
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_2_ADDR 0x1100B054
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_3_ADDR 0x1100B054
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_20_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_0_ADDR 0x1100B054
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_1_ADDR 0x1100B054
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_2_ADDR 0x1100B058
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_3_ADDR 0x1100B058
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_21_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_0_ADDR 0x1100B058
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_1_ADDR 0x1100B058
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_2_ADDR 0x1100B05C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_3_ADDR 0x1100B05C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_22_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_0_ADDR 0x1100B05C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_1_ADDR 0x1100B05C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_2_ADDR 0x1100B060
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_3_ADDR 0x1100B060
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_23_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_0_ADDR 0x1100B060
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_1_ADDR 0x1100B060
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_2_ADDR 0x1100B064
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_3_ADDR 0x1100B064
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_24_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_0_ADDR 0x1100B064
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_1_ADDR 0x1100B064
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_2_ADDR 0x1100B068
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_3_ADDR 0x1100B068
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_25_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_0_ADDR 0x1100B068
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_1_ADDR 0x1100B068
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_2_ADDR 0x1100B06C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_3_ADDR 0x1100B06C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_26_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_0_ADDR 0x1100B06C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_1_ADDR 0x1100B06C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_2_ADDR 0x1100B070
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_3_ADDR 0x1100B070
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_27_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_0_ADDR 0x1100B070
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_1_ADDR 0x1100B070
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_2_ADDR 0x1100B074
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_3_ADDR 0x1100B074
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_28_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_0_ADDR 0x1100B074
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_1_ADDR 0x1100B074
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_2_ADDR 0x1100B078
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_3_ADDR 0x1100B078
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_29_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_0_ADDR 0x1100B078
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_1_ADDR 0x1100B078
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_2_ADDR 0x1100B07C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_3_ADDR 0x1100B07C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_30_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_0_ADDR 0x1100B07C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_1_ADDR 0x1100B07C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_2_ADDR 0x1100B080
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_3_ADDR 0x1100B080
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_31_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_0_ADDR 0x1100B080
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_1_ADDR 0x1100B080
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_2_ADDR 0x1100B084
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_3_ADDR 0x1100B084
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_32_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_0_ADDR 0x1100B084
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_1_ADDR 0x1100B084
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_2_ADDR 0x1100B088
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_3_ADDR 0x1100B088
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_33_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_0_ADDR 0x1100B088
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_1_ADDR 0x1100B088
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_2_ADDR 0x1100B08C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_3_ADDR 0x1100B08C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_34_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_0_ADDR 0x1100B08C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_1_ADDR 0x1100B08C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_2_ADDR 0x1100B090
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_3_ADDR 0x1100B090
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_35_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_0_ADDR 0x1100B090
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_1_ADDR 0x1100B090
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_2_ADDR 0x1100B094
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_3_ADDR 0x1100B094
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_36_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_0_ADDR 0x1100B094
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_1_ADDR 0x1100B094
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_2_ADDR 0x1100B098
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_3_ADDR 0x1100B098
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_37_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_0_ADDR 0x1100B098
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_1_ADDR 0x1100B098
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_2_ADDR 0x1100B09C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_3_ADDR 0x1100B09C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_38_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_0_ADDR 0x1100B09C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_1_ADDR 0x1100B09C
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_2_ADDR 0x1100B0A0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_3_ADDR 0x1100B0A0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_39_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_0_ADDR 0x1100B0A0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_1_ADDR 0x1100B0A0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_2_ADDR 0x1100B0A4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_3_ADDR 0x1100B0A4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_40_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_0_ADDR 0x1100B0A4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_1_ADDR 0x1100B0A4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_2_ADDR 0x1100B0A8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_3_ADDR 0x1100B0A8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_41_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_0_ADDR 0x1100B0A8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_1_ADDR 0x1100B0A8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_2_ADDR 0x1100B0AC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_3_ADDR 0x1100B0AC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_42_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_0_ADDR 0x1100B0AC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_1_ADDR 0x1100B0AC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_2_ADDR 0x1100B0B0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_3_ADDR 0x1100B0B0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_43_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_0_ADDR 0x1100B0B0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_1_ADDR 0x1100B0B0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_2_ADDR 0x1100B0B4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_3_ADDR 0x1100B0B4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_44_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_0_ADDR 0x1100B0B4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_1_ADDR 0x1100B0B4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_2_ADDR 0x1100B0B8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_3_ADDR 0x1100B0B8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_45_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_0_ADDR 0x1100B0B8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_1_ADDR 0x1100B0B8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_2_ADDR 0x1100B0BC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_3_ADDR 0x1100B0BC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_46_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_0_ADDR 0x1100B0BC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_1_ADDR 0x1100B0BC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_2_ADDR 0x1100B0C0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_3_ADDR 0x1100B0C0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_47_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_0_ADDR 0x1100B0C0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_1_ADDR 0x1100B0C0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_2_ADDR 0x1100B0C4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_3_ADDR 0x1100B0C4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_48_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_0_ADDR 0x1100B0C4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_1_ADDR 0x1100B0C4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_2_ADDR 0x1100B0C8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_3_ADDR 0x1100B0C8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_49_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_0_ADDR 0x1100B0C8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_1_ADDR 0x1100B0C8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_2_ADDR 0x1100B0CC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_3_ADDR 0x1100B0CC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_50_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_0_ADDR 0x1100B0CC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_1_ADDR 0x1100B0CC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_2_ADDR 0x1100B0D0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_3_ADDR 0x1100B0D0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_51_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_0_ADDR 0x1100B0D0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_1_ADDR 0x1100B0D0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_2_ADDR 0x1100B0D4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_3_ADDR 0x1100B0D4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_52_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_0_ADDR 0x1100B0D4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_1_ADDR 0x1100B0D4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_2_ADDR 0x1100B0D8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_3_ADDR 0x1100B0D8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_53_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_0_ADDR 0x1100B0D8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_1_ADDR 0x1100B0D8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_2_ADDR 0x1100B0DC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_3_ADDR 0x1100B0DC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_54_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_0_ADDR 0x1100B0DC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_1_ADDR 0x1100B0DC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_2_ADDR 0x1100B0E0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_3_ADDR 0x1100B0E0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_55_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_0_ADDR 0x1100B0E0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_1_ADDR 0x1100B0E0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_2_ADDR 0x1100B0E4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_3_ADDR 0x1100B0E4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_56_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_0_ADDR 0x1100B0E4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_1_ADDR 0x1100B0E4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_2_ADDR 0x1100B0E8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_3_ADDR 0x1100B0E8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_57_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_0_ADDR 0x1100B0E8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_1_ADDR 0x1100B0E8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_2_ADDR 0x1100B0EC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_3_ADDR 0x1100B0EC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_58_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_0_ADDR 0x1100B0EC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_1_ADDR 0x1100B0EC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_2_ADDR 0x1100B0F0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_3_ADDR 0x1100B0F0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_59_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_0_ADDR 0x1100B0F0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_1_ADDR 0x1100B0F0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_2_ADDR 0x1100B0F4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_3_ADDR 0x1100B0F4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_60_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_0_ADDR 0x1100B0F4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_1_ADDR 0x1100B0F4
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_2_ADDR 0x1100B0F8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_3_ADDR 0x1100B0F8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_61_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_0_ADDR 0x1100B0F8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_1_ADDR 0x1100B0F8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_2_ADDR 0x1100B0FC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_3_ADDR 0x1100B0FC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_62_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_63_0_ADDR 0x1100B0FC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_63_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_63_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_63_1_ADDR 0x1100B0FC
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_63_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_0_reg_01__regr_01_rx_msg_data_object_63_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_63_2_ADDR 0x1100B100
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_63_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_63_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_63_3_ADDR 0x1100B100
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_63_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_63_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_0_ADDR 0x1100B100
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_1_ADDR 0x1100B100
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_2_ADDR 0x1100B104
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_3_ADDR 0x1100B104
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_64_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_0_ADDR 0x1100B104
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_1_ADDR 0x1100B104
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_2_ADDR 0x1100B108
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_3_ADDR 0x1100B108
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_65_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_0_ADDR 0x1100B108
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_1_ADDR 0x1100B108
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_2_ADDR 0x1100B10C
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_3_ADDR 0x1100B10C
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_66_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_0_ADDR 0x1100B10C
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_1_ADDR 0x1100B10C
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_2_ADDR 0x1100B110
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_3_ADDR 0x1100B110
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_67_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_0_ADDR 0x1100B110
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_1_ADDR 0x1100B110
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_1_BITEND 31

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_2_ADDR 0x1100B114
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_2_BITSTART 0
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_2_BITEND 7

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_3_ADDR 0x1100B114
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_3_BITSTART 8
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_68_3_BITEND 15

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_69_0_ADDR 0x1100B114
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_69_0_BITSTART 16
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_69_0_BITEND 23

#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_69_1_ADDR 0x1100B114
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_69_1_BITSTART 24
#define HS_Standby__usb_typec_rxdata_1_reg_01__regr_01_rx_msg_data_object_69_1_BITEND 31



#endif

