#ifndef _HV_PAGE_HT7315_BOE_TX1_H_
#define _HV_PAGE_HT7315_BOE_TX1_H_

#ifndef HV_BOE_TX1_BASE_ADDRESS
    #define HV_BOE_TX1_BASE_ADDRESS                                         0x1105E800
#endif


#define TX_BOE_TX1_BOE_P2P_REGISTER1_0                                   (HV_BOE_TX1_BASE_ADDRESS + 0x00)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_0_struct                            rs_tx_boe_tx1_boe_p2p_register1_0

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_0  rs_tx_boe_tx1_boe_p2p_register1_0;
struct _rs_tx_boe_tx1_boe_p2p_register1_0 {
    unsigned int reg_boe_tx_v_scram_reset_lane24            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane25            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_0(val) ((rs_tx_boe_tx1_boe_p2p_register1_0*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_1                                   (HV_BOE_TX1_BASE_ADDRESS + 0x04)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_1_struct                            rs_tx_boe_tx1_boe_p2p_register1_1

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_1  rs_tx_boe_tx1_boe_p2p_register1_1;
struct _rs_tx_boe_tx1_boe_p2p_register1_1 {
    unsigned int reg_boe_tx_v_scram_reset_lane26            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane27            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_1(val) ((rs_tx_boe_tx1_boe_p2p_register1_1*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_2                                   (HV_BOE_TX1_BASE_ADDRESS + 0x08)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_2_struct                            rs_tx_boe_tx1_boe_p2p_register1_2

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_2  rs_tx_boe_tx1_boe_p2p_register1_2;
struct _rs_tx_boe_tx1_boe_p2p_register1_2 {
    unsigned int reg_boe_tx_v_scram_reset_lane28            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane29            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_2(val) ((rs_tx_boe_tx1_boe_p2p_register1_2*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_3                                   (HV_BOE_TX1_BASE_ADDRESS + 0x0C)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_3_struct                            rs_tx_boe_tx1_boe_p2p_register1_3

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_3  rs_tx_boe_tx1_boe_p2p_register1_3;
struct _rs_tx_boe_tx1_boe_p2p_register1_3 {
    unsigned int reg_boe_tx_v_scram_reset_lane30            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane31            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_3(val) ((rs_tx_boe_tx1_boe_p2p_register1_3*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_4                                   (HV_BOE_TX1_BASE_ADDRESS + 0x10)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_4_struct                            rs_tx_boe_tx1_boe_p2p_register1_4

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_4  rs_tx_boe_tx1_boe_p2p_register1_4;
struct _rs_tx_boe_tx1_boe_p2p_register1_4 {
    unsigned int reg_boe_tx_v_scram_reset_lane32            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane33            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_4(val) ((rs_tx_boe_tx1_boe_p2p_register1_4*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_5                                   (HV_BOE_TX1_BASE_ADDRESS + 0x14)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_5_struct                            rs_tx_boe_tx1_boe_p2p_register1_5

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_5  rs_tx_boe_tx1_boe_p2p_register1_5;
struct _rs_tx_boe_tx1_boe_p2p_register1_5 {
    unsigned int reg_boe_tx_v_scram_reset_lane34            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane35            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_5(val) ((rs_tx_boe_tx1_boe_p2p_register1_5*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_6                                   (HV_BOE_TX1_BASE_ADDRESS + 0x18)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_6_struct                            rs_tx_boe_tx1_boe_p2p_register1_6

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_6  rs_tx_boe_tx1_boe_p2p_register1_6;
struct _rs_tx_boe_tx1_boe_p2p_register1_6 {
    unsigned int reg_boe_tx_v_scram_reset_lane36            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane37            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_6(val) ((rs_tx_boe_tx1_boe_p2p_register1_6*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_7                                   (HV_BOE_TX1_BASE_ADDRESS + 0x1C)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_7_struct                            rs_tx_boe_tx1_boe_p2p_register1_7

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_7  rs_tx_boe_tx1_boe_p2p_register1_7;
struct _rs_tx_boe_tx1_boe_p2p_register1_7 {
    unsigned int reg_boe_tx_v_scram_reset_lane38            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane39            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_7(val) ((rs_tx_boe_tx1_boe_p2p_register1_7*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_8                                   (HV_BOE_TX1_BASE_ADDRESS + 0x20)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_8_struct                            rs_tx_boe_tx1_boe_p2p_register1_8

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_8  rs_tx_boe_tx1_boe_p2p_register1_8;
struct _rs_tx_boe_tx1_boe_p2p_register1_8 {
    unsigned int reg_boe_tx_v_scram_reset_lane40            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane41            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_8(val) ((rs_tx_boe_tx1_boe_p2p_register1_8*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_9                                   (HV_BOE_TX1_BASE_ADDRESS + 0x24)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_9_struct                            rs_tx_boe_tx1_boe_p2p_register1_9

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_9  rs_tx_boe_tx1_boe_p2p_register1_9;
struct _rs_tx_boe_tx1_boe_p2p_register1_9 {
    unsigned int reg_boe_tx_v_scram_reset_lane42            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane43            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_9(val) ((rs_tx_boe_tx1_boe_p2p_register1_9*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_10                                  (HV_BOE_TX1_BASE_ADDRESS + 0x28)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_10_struct                           rs_tx_boe_tx1_boe_p2p_register1_10

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_10  rs_tx_boe_tx1_boe_p2p_register1_10;
struct _rs_tx_boe_tx1_boe_p2p_register1_10 {
    unsigned int reg_boe_tx_v_scram_reset_lane44            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane45            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_10(val) ((rs_tx_boe_tx1_boe_p2p_register1_10*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_11                                  (HV_BOE_TX1_BASE_ADDRESS + 0x2C)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_11_struct                           rs_tx_boe_tx1_boe_p2p_register1_11

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_11  rs_tx_boe_tx1_boe_p2p_register1_11;
struct _rs_tx_boe_tx1_boe_p2p_register1_11 {
    unsigned int reg_boe_tx_v_scram_reset_lane46            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane47            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx1_boe_p2p_register1_11(val) ((rs_tx_boe_tx1_boe_p2p_register1_11*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_12                                  (HV_BOE_TX1_BASE_ADDRESS + 0x30)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_12_struct                           rs_tx_boe_tx1_boe_p2p_register1_12

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_12  rs_tx_boe_tx1_boe_p2p_register1_12;
struct _rs_tx_boe_tx1_boe_p2p_register1_12 {
    unsigned int reg_boe_tx_lsp_k3_position_lane24          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane25          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane26          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane27          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane28          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane29          : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_register1_12(val) ((rs_tx_boe_tx1_boe_p2p_register1_12*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_13                                  (HV_BOE_TX1_BASE_ADDRESS + 0x34)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_13_struct                           rs_tx_boe_tx1_boe_p2p_register1_13

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_13  rs_tx_boe_tx1_boe_p2p_register1_13;
struct _rs_tx_boe_tx1_boe_p2p_register1_13 {
    unsigned int reg_boe_tx_lsp_k3_position_lane30          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane31          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane32          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane33          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane34          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane35          : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_register1_13(val) ((rs_tx_boe_tx1_boe_p2p_register1_13*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_14                                  (HV_BOE_TX1_BASE_ADDRESS + 0x38)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_14_struct                           rs_tx_boe_tx1_boe_p2p_register1_14

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_14  rs_tx_boe_tx1_boe_p2p_register1_14;
struct _rs_tx_boe_tx1_boe_p2p_register1_14 {
    unsigned int reg_boe_tx_lsp_k3_position_lane36          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane37          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane38          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane39          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane40          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane41          : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_register1_14(val) ((rs_tx_boe_tx1_boe_p2p_register1_14*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_15                                  (HV_BOE_TX1_BASE_ADDRESS + 0x3C)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_15_struct                           rs_tx_boe_tx1_boe_p2p_register1_15

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_15  rs_tx_boe_tx1_boe_p2p_register1_15;
struct _rs_tx_boe_tx1_boe_p2p_register1_15 {
    unsigned int reg_boe_tx_lsp_k3_position_lane42          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane43          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane44          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane45          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane46          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane47          : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_register1_15(val) ((rs_tx_boe_tx1_boe_p2p_register1_15*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_16                                  (HV_BOE_TX1_BASE_ADDRESS + 0x40)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_16_struct                           rs_tx_boe_tx1_boe_p2p_register1_16

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_16  rs_tx_boe_tx1_boe_p2p_register1_16;
struct _rs_tx_boe_tx1_boe_p2p_register1_16 {
    unsigned int reg_boe_tx_lane_delay_num_lane24           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane25           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane26           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane27           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane28           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane29           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane30           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane31           : 4;
};
#define tx_boe_tx1_boe_p2p_register1_16(val) ((rs_tx_boe_tx1_boe_p2p_register1_16*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_17                                  (HV_BOE_TX1_BASE_ADDRESS + 0x44)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_17_struct                           rs_tx_boe_tx1_boe_p2p_register1_17

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_17  rs_tx_boe_tx1_boe_p2p_register1_17;
struct _rs_tx_boe_tx1_boe_p2p_register1_17 {
    unsigned int reg_boe_tx_lane_delay_num_lane32           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane33           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane34           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane35           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane36           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane37           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane38           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane39           : 4;
};
#define tx_boe_tx1_boe_p2p_register1_17(val) ((rs_tx_boe_tx1_boe_p2p_register1_17*)&(val))



#define TX_BOE_TX1_BOE_P2P_REGISTER1_18                                  (HV_BOE_TX1_BASE_ADDRESS + 0x48)

#define TX_BOE_TX1_BOE_P2P_REGISTER1_18_struct                           rs_tx_boe_tx1_boe_p2p_register1_18

typedef struct _rs_tx_boe_tx1_boe_p2p_register1_18  rs_tx_boe_tx1_boe_p2p_register1_18;
struct _rs_tx_boe_tx1_boe_p2p_register1_18 {
    unsigned int reg_boe_tx_lane_delay_num_lane40           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane41           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane42           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane43           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane44           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane45           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane46           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane47           : 4;
};
#define tx_boe_tx1_boe_p2p_register1_18(val) ((rs_tx_boe_tx1_boe_p2p_register1_18*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE01                   (HV_BOE_TX1_BASE_ADDRESS + 0x50)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE01_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane01

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane01  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane01;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane01 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane01          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane01         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane01         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane01              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane01(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane01*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE01                   (HV_BOE_TX1_BASE_ADDRESS + 0x54)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE01_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane01

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane01  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane01;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane01 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane01              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane01                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane01              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane01         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane01              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane01                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane01               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane01(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane01*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE01                   (HV_BOE_TX1_BASE_ADDRESS + 0x58)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE01_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane01

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane01  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane01;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane01 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane01               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane01          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane01          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane01          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane01          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane01          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane01           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane01          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane01          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane01            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane01(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane01*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE01                   (HV_BOE_TX1_BASE_ADDRESS + 0x5C)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE01_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane01

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane01  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane01;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane01 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane01             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane01               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane01           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane01             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane01           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane01            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane01          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane01          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane01         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane01(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane01*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE02                   (HV_BOE_TX1_BASE_ADDRESS + 0x60)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE02_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane02

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane02  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane02;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane02 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane02          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane02         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane02         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane02              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane02(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane02*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE02                   (HV_BOE_TX1_BASE_ADDRESS + 0x64)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE02_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane02

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane02  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane02;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane02 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane02              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane02                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane02              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane02         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane02              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane02                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane02               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane02(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane02*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE02                   (HV_BOE_TX1_BASE_ADDRESS + 0x68)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE02_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane02

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane02  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane02;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane02 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane02               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane02          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane02          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane02          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane02          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane02          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane02           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane02          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane02          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane02            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane02(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane02*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE02                   (HV_BOE_TX1_BASE_ADDRESS + 0x6C)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE02_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane02

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane02  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane02;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane02 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane02             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane02               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane02           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane02             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane02           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane02            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane02          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane02          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane02         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane02(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane02*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE03                   (HV_BOE_TX1_BASE_ADDRESS + 0x70)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE03_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane03

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane03  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane03;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane03 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane03          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane03         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane03         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane03              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane03(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane03*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE03                   (HV_BOE_TX1_BASE_ADDRESS + 0x74)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE03_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane03

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane03  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane03;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane03 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane03              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane03                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane03              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane03         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane03              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane03                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane03               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane03(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane03*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE03                   (HV_BOE_TX1_BASE_ADDRESS + 0x78)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE03_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane03

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane03  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane03;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane03 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane03               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane03          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane03          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane03          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane03          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane03          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane03           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane03          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane03          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane03            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane03(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane03*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE03                   (HV_BOE_TX1_BASE_ADDRESS + 0x7C)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE03_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane03

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane03  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane03;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane03 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane03             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane03               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane03           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane03             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane03           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane03            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane03          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane03          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane03         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane03(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane03*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE04                   (HV_BOE_TX1_BASE_ADDRESS + 0x80)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE04_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane04

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane04  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane04;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane04 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane04          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane04         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane04         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane04              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane04(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane04*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE04                   (HV_BOE_TX1_BASE_ADDRESS + 0x84)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE04_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane04

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane04  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane04;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane04 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane04              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane04                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane04              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane04         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane04              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane04                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane04               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane04(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane04*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE04                   (HV_BOE_TX1_BASE_ADDRESS + 0x88)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE04_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane04

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane04  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane04;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane04 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane04               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane04          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane04          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane04          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane04          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane04          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane04           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane04          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane04          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane04            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane04(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane04*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE04                   (HV_BOE_TX1_BASE_ADDRESS + 0x8C)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE04_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane04

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane04  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane04;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane04 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane04             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane04               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane04           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane04             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane04           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane04            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane04          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane04          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane04         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane04(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane04*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE05                   (HV_BOE_TX1_BASE_ADDRESS + 0x90)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE05_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane05

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane05  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane05;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane05 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane05          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane05         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane05         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane05              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane05(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane05*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE05                   (HV_BOE_TX1_BASE_ADDRESS + 0x94)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE05_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane05

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane05  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane05;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane05 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane05              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane05                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane05              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane05         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane05              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane05                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane05               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane05(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane05*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE05                   (HV_BOE_TX1_BASE_ADDRESS + 0x98)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE05_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane05

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane05  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane05;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane05 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane05               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane05          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane05          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane05          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane05          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane05          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane05           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane05          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane05          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane05            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane05(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane05*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE05                   (HV_BOE_TX1_BASE_ADDRESS + 0x9C)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE05_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane05

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane05  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane05;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane05 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane05             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane05               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane05           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane05             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane05           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane05            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane05          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane05          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane05         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane05(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane05*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE06                   (HV_BOE_TX1_BASE_ADDRESS + 0xA0)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE06_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane06

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane06  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane06;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane06 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane06          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane06         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane06         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane06              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane06(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane06*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE06                   (HV_BOE_TX1_BASE_ADDRESS + 0xA4)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE06_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane06

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane06  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane06;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane06 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane06              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane06                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane06              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane06         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane06              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane06                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane06               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane06(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane06*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE06                   (HV_BOE_TX1_BASE_ADDRESS + 0xA8)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE06_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane06

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane06  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane06;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane06 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane06               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane06          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane06          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane06          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane06          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane06          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane06           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane06          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane06          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane06            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane06(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane06*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE06                   (HV_BOE_TX1_BASE_ADDRESS + 0xAC)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE06_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane06

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane06  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane06;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane06 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane06             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane06               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane06           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane06             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane06           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane06            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane06          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane06          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane06         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane06(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane06*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE07                   (HV_BOE_TX1_BASE_ADDRESS + 0xB0)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE07_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane07

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane07  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane07;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane07 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane07          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane07         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane07         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane07              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane07(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane07*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE07                   (HV_BOE_TX1_BASE_ADDRESS + 0xB4)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE07_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane07

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane07  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane07;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane07 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane07              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane07                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane07              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane07         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane07              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane07                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane07               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane07(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane07*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE07                   (HV_BOE_TX1_BASE_ADDRESS + 0xB8)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE07_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane07

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane07  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane07;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane07 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane07               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane07          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane07          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane07          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane07          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane07          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane07           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane07          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane07          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane07            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane07(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane07*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE07                   (HV_BOE_TX1_BASE_ADDRESS + 0xBC)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE07_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane07

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane07  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane07;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane07 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane07             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane07               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane07           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane07             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane07           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane07            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane07          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane07          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane07         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane07(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane07*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE08                   (HV_BOE_TX1_BASE_ADDRESS + 0xC0)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE08_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane08

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane08  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane08;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane08 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane08          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane08         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane08         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane08              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane08(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane08*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE08                   (HV_BOE_TX1_BASE_ADDRESS + 0xC4)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE08_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane08

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane08  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane08;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane08 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane08              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane08                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane08              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane08         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane08              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane08                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane08               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane08(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane08*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE08                   (HV_BOE_TX1_BASE_ADDRESS + 0xC8)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE08_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane08

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane08  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane08;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane08 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane08               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane08          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane08          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane08          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane08          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane08          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane08           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane08          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane08          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane08            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane08(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane08*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE08                   (HV_BOE_TX1_BASE_ADDRESS + 0xCC)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE08_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane08

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane08  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane08;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane08 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane08             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane08               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane08           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane08             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane08           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane08            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane08          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane08          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane08         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane08(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane08*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE09                   (HV_BOE_TX1_BASE_ADDRESS + 0xD0)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE09_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane09

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane09  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane09;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane09 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane09          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane09         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane09         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane09              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane09(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane09*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE09                   (HV_BOE_TX1_BASE_ADDRESS + 0xD4)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE09_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane09

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane09  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane09;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane09 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane09              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane09                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane09              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane09         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane09              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane09                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane09               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane09(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane09*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE09                   (HV_BOE_TX1_BASE_ADDRESS + 0xD8)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE09_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane09

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane09  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane09;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane09 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane09               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane09          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane09          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane09          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane09          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane09          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane09           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane09          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane09          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane09            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane09(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane09*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE09                   (HV_BOE_TX1_BASE_ADDRESS + 0xDC)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE09_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane09

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane09  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane09;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane09 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane09             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane09               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane09           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane09             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane09           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane09            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane09          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane09          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane09         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane09(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane09*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE10                   (HV_BOE_TX1_BASE_ADDRESS + 0xE0)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE10_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane10

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane10  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane10;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane10 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane10          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane10         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane10         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane10              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane10(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane10*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE10                   (HV_BOE_TX1_BASE_ADDRESS + 0xE4)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE10_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane10

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane10  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane10;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane10 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane10              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane10                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane10              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane10         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane10              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane10                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane10               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane10(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane10*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE10                   (HV_BOE_TX1_BASE_ADDRESS + 0xE8)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE10_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane10

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane10  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane10;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane10 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane10               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane10          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane10          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane10          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane10          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane10          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane10           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane10          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane10          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane10            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane10(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane10*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE10                   (HV_BOE_TX1_BASE_ADDRESS + 0xEC)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE10_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane10

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane10  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane10;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane10 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane10             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane10               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane10           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane10             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane10           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane10            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane10          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane10          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane10         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane10(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane10*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE11                   (HV_BOE_TX1_BASE_ADDRESS + 0xF0)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE11_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane11

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane11  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane11;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane11 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane11          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane11         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane11         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane11              : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane11(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_0_lane11*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE11                   (HV_BOE_TX1_BASE_ADDRESS + 0xF4)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE11_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane11

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane11  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane11;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane11 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane11              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane11                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane11              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane11         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane11              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane11                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane11               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane11(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_1_lane11*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE11                   (HV_BOE_TX1_BASE_ADDRESS + 0xF8)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE11_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane11

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane11  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane11;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane11 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane11               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane11          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane11          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane11          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane11          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane11          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane11           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane11          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane11          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane11            : 3;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane11(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_2_lane11*)&(val))



#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE11                   (HV_BOE_TX1_BASE_ADDRESS + 0xFC)

#define TX_BOE_TX1_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE11_struct            rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane11

typedef struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane11  rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane11;
struct _rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane11 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane11             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane11               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane11           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane11             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane11           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane11            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane11          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane11          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane11         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane11(val) ((rs_tx_boe_tx1_boe_p2p_ctrl_packet_config_3_lane11*)&(val))



#endif