#ifndef _HV_PAGE_HT7315_KV_1DIMMER_CTRL_REG5_H_
#define _HV_PAGE_HT7315_KV_1DIMMER_CTRL_REG5_H_

#ifndef HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS
    #define HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS                                         0x11045E00
#endif


#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_20                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x00)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_20_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_20

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_20  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_20;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_20 {
    unsigned int reg_dim_cmd_vaule0_20                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_20(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_20*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_20                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x04)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_20_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_20

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_20  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_20;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_20 {
    unsigned int reg_dim_cmd_vaule1_20                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_20(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_20*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_20                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x08)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_20_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_20

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_20  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_20;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_20 {
    unsigned int reg_dim_cmd_vaule2_20                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_20(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_20*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__20                   (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x0C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__20_struct            rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__20

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__20  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__20;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__20 {
    unsigned int reg_dim_cmd_vaule3_20                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__20(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__20*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_21                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x10)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_21_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_21

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_21  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_21;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_21 {
    unsigned int reg_dim_cmd_vaule0_21                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_21(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_21*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_21                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x14)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_21_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_21

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_21  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_21;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_21 {
    unsigned int reg_dim_cmd_vaule1_21                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_21(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_21*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_21                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x18)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_21_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_21

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_21  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_21;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_21 {
    unsigned int reg_dim_cmd_vaule2_21                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_21(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_21*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__21                   (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x1C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__21_struct            rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__21

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__21  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__21;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__21 {
    unsigned int reg_dim_cmd_vaule3_21                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__21(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__21*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_22                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x20)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_22_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_22

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_22  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_22;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_22 {
    unsigned int reg_dim_cmd_vaule0_22                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_22(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_22*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_22                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x24)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_22_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_22

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_22  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_22;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_22 {
    unsigned int reg_dim_cmd_vaule1_22                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_22(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_22*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_22                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x28)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_22_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_22

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_22  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_22;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_22 {
    unsigned int reg_dim_cmd_vaule2_22                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_22(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_22*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__22                   (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x2C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__22_struct            rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__22

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__22  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__22;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__22 {
    unsigned int reg_dim_cmd_vaule3_22                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__22(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__22*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_23                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x30)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE0_23_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_23

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_23  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_23;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_23 {
    unsigned int reg_dim_cmd_vaule0_23                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_23(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule0_23*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_23                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x34)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE1_23_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_23

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_23  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_23;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_23 {
    unsigned int reg_dim_cmd_vaule1_23                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_23(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule1_23*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_23                    (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x38)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE2_23_struct             rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_23

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_23  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_23;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_23 {
    unsigned int reg_dim_cmd_vaule2_23                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_23(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule2_23*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__23                   (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x3C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_DIM_CMD_VAULE3__23_struct            rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__23

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__23  rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__23;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__23 {
    unsigned int reg_dim_cmd_vaule3_23                      :32;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__23(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_dim_cmd_vaule3__23*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_0                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x40)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_0_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_0

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_0  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_0;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_0 {
    unsigned int reg_ram_ofst_0                             :16;
    unsigned int reg_lane_stride_0                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_0(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_0*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_1                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x44)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_1_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_1

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_1  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_1;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_1 {
    unsigned int reg_ram_ofst_1                             :16;
    unsigned int reg_lane_stride_1                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_1(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_1*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_2                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x48)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_2_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_2

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_2  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_2;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_2 {
    unsigned int reg_ram_ofst_2                             :16;
    unsigned int reg_lane_stride_2                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_2(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_2*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_3                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x4C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_3_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_3

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_3  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_3;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_3 {
    unsigned int reg_ram_ofst_3                             :16;
    unsigned int reg_lane_stride_3                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_3(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_3*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_4                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x50)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_4_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_4

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_4  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_4;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_4 {
    unsigned int reg_ram_ofst_4                             :16;
    unsigned int reg_lane_stride_4                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_4(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_4*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_5                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x5C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_5_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_5

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_5  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_5;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_5 {
    unsigned int reg_ram_ofst_5                             :16;
    unsigned int reg_lane_stride_5                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_5(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_5*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_6                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x60)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_6_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_6

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_6  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_6;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_6 {
    unsigned int reg_ram_ofst_6                             :16;
    unsigned int reg_lane_stride_6                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_6(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_6*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_7                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x64)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_7_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_7

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_7  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_7;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_7 {
    unsigned int reg_ram_ofst_7                             :16;
    unsigned int reg_lane_stride_7                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_7(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_7*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_8                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x68)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_8_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_8

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_8  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_8;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_8 {
    unsigned int reg_ram_ofst_8                             :16;
    unsigned int reg_lane_stride_8                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_8(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_8*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_9                           (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x6C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_9_struct                    rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_9

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_9  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_9;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_9 {
    unsigned int reg_ram_ofst_9                             :16;
    unsigned int reg_lane_stride_9                          :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_9(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_9*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_10                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x70)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_10_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_10

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_10  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_10;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_10 {
    unsigned int reg_ram_ofst_10                            :16;
    unsigned int reg_lane_stride_10                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_10(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_10*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_11                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x74)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_11_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_11

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_11  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_11;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_11 {
    unsigned int reg_ram_ofst_11                            :16;
    unsigned int reg_lane_stride_11                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_11(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_11*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_12                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x78)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_12_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_12

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_12  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_12;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_12 {
    unsigned int reg_ram_ofst_12                            :16;
    unsigned int reg_lane_stride_12                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_12(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_12*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_13                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x7C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_13_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_13

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_13  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_13;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_13 {
    unsigned int reg_ram_ofst_13                            :16;
    unsigned int reg_lane_stride_13                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_13(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_13*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_14                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x80)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_14_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_14

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_14  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_14;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_14 {
    unsigned int reg_ram_ofst_14                            :16;
    unsigned int reg_lane_stride_14                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_14(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_14*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_15                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x84)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_15_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_15

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_15  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_15;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_15 {
    unsigned int reg_ram_ofst_15                            :16;
    unsigned int reg_lane_stride_15                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_15(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_15*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_16                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x88)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_16_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_16

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_16  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_16;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_16 {
    unsigned int reg_ram_ofst_16                            :16;
    unsigned int reg_lane_stride_16                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_16(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_16*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_17                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x8C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_17_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_17

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_17  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_17;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_17 {
    unsigned int reg_ram_ofst_17                            :16;
    unsigned int reg_lane_stride_17                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_17(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_17*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_18                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x90)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_18_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_18

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_18  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_18;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_18 {
    unsigned int reg_ram_ofst_18                            :16;
    unsigned int reg_lane_stride_18                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_18(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_18*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_19                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x94)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_19_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_19

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_19  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_19;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_19 {
    unsigned int reg_ram_ofst_19                            :16;
    unsigned int reg_lane_stride_19                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_19(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_19*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_20                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x98)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_20_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_20

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_20  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_20;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_20 {
    unsigned int reg_ram_ofst_20                            :16;
    unsigned int reg_lane_stride_20                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_20(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_20*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_21                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0x9C)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_21_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_21

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_21  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_21;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_21 {
    unsigned int reg_ram_ofst_21                            :16;
    unsigned int reg_lane_stride_21                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_21(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_21*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_22                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0xA0)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_22_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_22

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_22  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_22;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_22 {
    unsigned int reg_ram_ofst_22                            :16;
    unsigned int reg_lane_stride_22                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_22(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_22*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_23                          (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0xA4)

#define RX_KV_1DIMMER_CTRL_REG5_REG_RAM_OFST_23_struct                   rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_23

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_23  rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_23;
struct _rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_23 {
    unsigned int reg_ram_ofst_23                            :16;
    unsigned int reg_lane_stride_23                         :16;
};
#define rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_23(val) ((rs_rx_kv_1dimmer_ctrl_reg5_reg_ram_ofst_23*)&(val))



#define RX_KV_1DIMMER_CTRL_REG5_A8                                       (HV_KV_1DIMMER_CTRL_REG5_BASE_ADDRESS + 0xA8)

#define RX_KV_1DIMMER_CTRL_REG5_A8_struct                                rs_rx_kv_1dimmer_ctrl_reg5_a8

typedef struct _rs_rx_kv_1dimmer_ctrl_reg5_a8  rs_rx_kv_1dimmer_ctrl_reg5_a8;
struct _rs_rx_kv_1dimmer_ctrl_reg5_a8 {
    unsigned int reg_lane_stride_unit                       :16;
    unsigned int reserved                                   :16;
};
#define rx_kv_1dimmer_ctrl_reg5_a8(val) ((rs_rx_kv_1dimmer_ctrl_reg5_a8*)&(val))



#endif