#ifndef _HV_PAGE_HT7315_DMAC_H_
#define _HV_PAGE_HT7315_DMAC_H_

#ifndef HV_DMAC_BASE_ADDRESS
    #define HV_DMAC_BASE_ADDRESS                                         0x1108C000
#endif


#define CPU_SYS_DMAC_SAR0                                                (HV_DMAC_BASE_ADDRESS + 0x000)

#define CPU_SYS_DMAC_SAR0_struct                                         rs_cpu_sys_dmac_sar0

typedef struct _rs_cpu_sys_dmac_sar0  rs_cpu_sys_dmac_sar0;
struct _rs_cpu_sys_dmac_sar0 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar0(val) ((rs_cpu_sys_dmac_sar0*)&(val))



#define CPU_SYS_DMAC_DAR0                                                (HV_DMAC_BASE_ADDRESS + 0x008)

#define CPU_SYS_DMAC_DAR0_struct                                         rs_cpu_sys_dmac_dar0

typedef struct _rs_cpu_sys_dmac_dar0  rs_cpu_sys_dmac_dar0;
struct _rs_cpu_sys_dmac_dar0 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar0(val) ((rs_cpu_sys_dmac_dar0*)&(val))



#define CPU_SYS_DMAC_LLP0                                                (HV_DMAC_BASE_ADDRESS + 0x010)

#define CPU_SYS_DMAC_LLP0_struct                                         rs_cpu_sys_dmac_llp0

typedef struct _rs_cpu_sys_dmac_llp0  rs_cpu_sys_dmac_llp0;
struct _rs_cpu_sys_dmac_llp0 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp0(val) ((rs_cpu_sys_dmac_llp0*)&(val))



#define CPU_SYS_DMAC_CTL0_L                                              (HV_DMAC_BASE_ADDRESS + 0x018)

#define CPU_SYS_DMAC_CTL0_L_struct                                       rs_cpu_sys_dmac_ctl0_l

typedef struct _rs_cpu_sys_dmac_ctl0_l  rs_cpu_sys_dmac_ctl0_l;
struct _rs_cpu_sys_dmac_ctl0_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl0_l(val) ((rs_cpu_sys_dmac_ctl0_l*)&(val))



#define CPU_SYS_DMAC_CTL0_H                                              (HV_DMAC_BASE_ADDRESS + 0x01C)

#define CPU_SYS_DMAC_CTL0_H_struct                                       rs_cpu_sys_dmac_ctl0_h

typedef struct _rs_cpu_sys_dmac_ctl0_h  rs_cpu_sys_dmac_ctl0_h;
struct _rs_cpu_sys_dmac_ctl0_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl0_h(val) ((rs_cpu_sys_dmac_ctl0_h*)&(val))



#define CPU_SYS_DMAC_SSTAT0                                              (HV_DMAC_BASE_ADDRESS + 0x020)

#define CPU_SYS_DMAC_SSTAT0_struct                                       rs_cpu_sys_dmac_sstat0

typedef struct _rs_cpu_sys_dmac_sstat0  rs_cpu_sys_dmac_sstat0;
struct _rs_cpu_sys_dmac_sstat0 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat0(val) ((rs_cpu_sys_dmac_sstat0*)&(val))



#define CPU_SYS_DMAC_DSTAT0                                              (HV_DMAC_BASE_ADDRESS + 0x028)

#define CPU_SYS_DMAC_DSTAT0_struct                                       rs_cpu_sys_dmac_dstat0

typedef struct _rs_cpu_sys_dmac_dstat0  rs_cpu_sys_dmac_dstat0;
struct _rs_cpu_sys_dmac_dstat0 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat0(val) ((rs_cpu_sys_dmac_dstat0*)&(val))



#define CPU_SYS_DMAC_SSTATAR0                                            (HV_DMAC_BASE_ADDRESS + 0x030)

#define CPU_SYS_DMAC_SSTATAR0_struct                                     rs_cpu_sys_dmac_sstatar0

typedef struct _rs_cpu_sys_dmac_sstatar0  rs_cpu_sys_dmac_sstatar0;
struct _rs_cpu_sys_dmac_sstatar0 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar0(val) ((rs_cpu_sys_dmac_sstatar0*)&(val))



#define CPU_SYS_DMAC_DSTATAR0                                            (HV_DMAC_BASE_ADDRESS + 0x038)

#define CPU_SYS_DMAC_DSTATAR0_struct                                     rs_cpu_sys_dmac_dstatar0

typedef struct _rs_cpu_sys_dmac_dstatar0  rs_cpu_sys_dmac_dstatar0;
struct _rs_cpu_sys_dmac_dstatar0 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar0(val) ((rs_cpu_sys_dmac_dstatar0*)&(val))



#define CPU_SYS_DMAC_CFG0_L                                              (HV_DMAC_BASE_ADDRESS + 0x040)

#define CPU_SYS_DMAC_CFG0_L_struct                                       rs_cpu_sys_dmac_cfg0_l

typedef struct _rs_cpu_sys_dmac_cfg0_l  rs_cpu_sys_dmac_cfg0_l;
struct _rs_cpu_sys_dmac_cfg0_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg0_l(val) ((rs_cpu_sys_dmac_cfg0_l*)&(val))



#define CPU_SYS_DMAC_CFG0_H                                              (HV_DMAC_BASE_ADDRESS + 0x044)

#define CPU_SYS_DMAC_CFG0_H_struct                                       rs_cpu_sys_dmac_cfg0_h

typedef struct _rs_cpu_sys_dmac_cfg0_h  rs_cpu_sys_dmac_cfg0_h;
struct _rs_cpu_sys_dmac_cfg0_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg0_h(val) ((rs_cpu_sys_dmac_cfg0_h*)&(val))



#define CPU_SYS_DMAC_SGR0                                                (HV_DMAC_BASE_ADDRESS + 0x048)

#define CPU_SYS_DMAC_SGR0_struct                                         rs_cpu_sys_dmac_sgr0

typedef struct _rs_cpu_sys_dmac_sgr0  rs_cpu_sys_dmac_sgr0;
struct _rs_cpu_sys_dmac_sgr0 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr0(val) ((rs_cpu_sys_dmac_sgr0*)&(val))



#define CPU_SYS_DMAC_DSR0                                                (HV_DMAC_BASE_ADDRESS + 0x050)

#define CPU_SYS_DMAC_DSR0_struct                                         rs_cpu_sys_dmac_dsr0

typedef struct _rs_cpu_sys_dmac_dsr0  rs_cpu_sys_dmac_dsr0;
struct _rs_cpu_sys_dmac_dsr0 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr0(val) ((rs_cpu_sys_dmac_dsr0*)&(val))



#define CPU_SYS_DMAC_SAR1                                                (HV_DMAC_BASE_ADDRESS + 0x058)

#define CPU_SYS_DMAC_SAR1_struct                                         rs_cpu_sys_dmac_sar1

typedef struct _rs_cpu_sys_dmac_sar1  rs_cpu_sys_dmac_sar1;
struct _rs_cpu_sys_dmac_sar1 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar1(val) ((rs_cpu_sys_dmac_sar1*)&(val))



#define CPU_SYS_DMAC_DAR1                                                (HV_DMAC_BASE_ADDRESS + 0x060)

#define CPU_SYS_DMAC_DAR1_struct                                         rs_cpu_sys_dmac_dar1

typedef struct _rs_cpu_sys_dmac_dar1  rs_cpu_sys_dmac_dar1;
struct _rs_cpu_sys_dmac_dar1 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar1(val) ((rs_cpu_sys_dmac_dar1*)&(val))



#define CPU_SYS_DMAC_LLP1                                                (HV_DMAC_BASE_ADDRESS + 0x068)

#define CPU_SYS_DMAC_LLP1_struct                                         rs_cpu_sys_dmac_llp1

typedef struct _rs_cpu_sys_dmac_llp1  rs_cpu_sys_dmac_llp1;
struct _rs_cpu_sys_dmac_llp1 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp1(val) ((rs_cpu_sys_dmac_llp1*)&(val))



#define CPU_SYS_DMAC_CTL1_L                                              (HV_DMAC_BASE_ADDRESS + 0x070)

#define CPU_SYS_DMAC_CTL1_L_struct                                       rs_cpu_sys_dmac_ctl1_l

typedef struct _rs_cpu_sys_dmac_ctl1_l  rs_cpu_sys_dmac_ctl1_l;
struct _rs_cpu_sys_dmac_ctl1_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl1_l(val) ((rs_cpu_sys_dmac_ctl1_l*)&(val))



#define CPU_SYS_DMAC_CTL1_H                                              (HV_DMAC_BASE_ADDRESS + 0x074)

#define CPU_SYS_DMAC_CTL1_H_struct                                       rs_cpu_sys_dmac_ctl1_h

typedef struct _rs_cpu_sys_dmac_ctl1_h  rs_cpu_sys_dmac_ctl1_h;
struct _rs_cpu_sys_dmac_ctl1_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl1_h(val) ((rs_cpu_sys_dmac_ctl1_h*)&(val))



#define CPU_SYS_DMAC_SSTAT1                                              (HV_DMAC_BASE_ADDRESS + 0x078)

#define CPU_SYS_DMAC_SSTAT1_struct                                       rs_cpu_sys_dmac_sstat1

typedef struct _rs_cpu_sys_dmac_sstat1  rs_cpu_sys_dmac_sstat1;
struct _rs_cpu_sys_dmac_sstat1 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat1(val) ((rs_cpu_sys_dmac_sstat1*)&(val))



#define CPU_SYS_DMAC_DSTAT1                                              (HV_DMAC_BASE_ADDRESS + 0x080)

#define CPU_SYS_DMAC_DSTAT1_struct                                       rs_cpu_sys_dmac_dstat1

typedef struct _rs_cpu_sys_dmac_dstat1  rs_cpu_sys_dmac_dstat1;
struct _rs_cpu_sys_dmac_dstat1 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat1(val) ((rs_cpu_sys_dmac_dstat1*)&(val))



#define CPU_SYS_DMAC_SSTATAR1                                            (HV_DMAC_BASE_ADDRESS + 0x088)

#define CPU_SYS_DMAC_SSTATAR1_struct                                     rs_cpu_sys_dmac_sstatar1

typedef struct _rs_cpu_sys_dmac_sstatar1  rs_cpu_sys_dmac_sstatar1;
struct _rs_cpu_sys_dmac_sstatar1 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar1(val) ((rs_cpu_sys_dmac_sstatar1*)&(val))



#define CPU_SYS_DMAC_DSTATAR1                                            (HV_DMAC_BASE_ADDRESS + 0x090)

#define CPU_SYS_DMAC_DSTATAR1_struct                                     rs_cpu_sys_dmac_dstatar1

typedef struct _rs_cpu_sys_dmac_dstatar1  rs_cpu_sys_dmac_dstatar1;
struct _rs_cpu_sys_dmac_dstatar1 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar1(val) ((rs_cpu_sys_dmac_dstatar1*)&(val))



#define CPU_SYS_DMAC_CFG1_L                                              (HV_DMAC_BASE_ADDRESS + 0x094)

#define CPU_SYS_DMAC_CFG1_L_struct                                       rs_cpu_sys_dmac_cfg1_l

typedef struct _rs_cpu_sys_dmac_cfg1_l  rs_cpu_sys_dmac_cfg1_l;
struct _rs_cpu_sys_dmac_cfg1_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg1_l(val) ((rs_cpu_sys_dmac_cfg1_l*)&(val))



#define CPU_SYS_DMAC_CFG1_H                                              (HV_DMAC_BASE_ADDRESS + 0x09C)

#define CPU_SYS_DMAC_CFG1_H_struct                                       rs_cpu_sys_dmac_cfg1_h

typedef struct _rs_cpu_sys_dmac_cfg1_h  rs_cpu_sys_dmac_cfg1_h;
struct _rs_cpu_sys_dmac_cfg1_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg1_h(val) ((rs_cpu_sys_dmac_cfg1_h*)&(val))



#define CPU_SYS_DMAC_SGR1                                                (HV_DMAC_BASE_ADDRESS + 0x0A0)

#define CPU_SYS_DMAC_SGR1_struct                                         rs_cpu_sys_dmac_sgr1

typedef struct _rs_cpu_sys_dmac_sgr1  rs_cpu_sys_dmac_sgr1;
struct _rs_cpu_sys_dmac_sgr1 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr1(val) ((rs_cpu_sys_dmac_sgr1*)&(val))



#define CPU_SYS_DMAC_DSR1                                                (HV_DMAC_BASE_ADDRESS + 0x0A8)

#define CPU_SYS_DMAC_DSR1_struct                                         rs_cpu_sys_dmac_dsr1

typedef struct _rs_cpu_sys_dmac_dsr1  rs_cpu_sys_dmac_dsr1;
struct _rs_cpu_sys_dmac_dsr1 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr1(val) ((rs_cpu_sys_dmac_dsr1*)&(val))



#define CPU_SYS_DMAC_SAR2                                                (HV_DMAC_BASE_ADDRESS + 0x0B0)

#define CPU_SYS_DMAC_SAR2_struct                                         rs_cpu_sys_dmac_sar2

typedef struct _rs_cpu_sys_dmac_sar2  rs_cpu_sys_dmac_sar2;
struct _rs_cpu_sys_dmac_sar2 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar2(val) ((rs_cpu_sys_dmac_sar2*)&(val))



#define CPU_SYS_DMAC_DAR2                                                (HV_DMAC_BASE_ADDRESS + 0x0B8)

#define CPU_SYS_DMAC_DAR2_struct                                         rs_cpu_sys_dmac_dar2

typedef struct _rs_cpu_sys_dmac_dar2  rs_cpu_sys_dmac_dar2;
struct _rs_cpu_sys_dmac_dar2 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar2(val) ((rs_cpu_sys_dmac_dar2*)&(val))



#define CPU_SYS_DMAC_LLP2                                                (HV_DMAC_BASE_ADDRESS + 0x0C0)

#define CPU_SYS_DMAC_LLP2_struct                                         rs_cpu_sys_dmac_llp2

typedef struct _rs_cpu_sys_dmac_llp2  rs_cpu_sys_dmac_llp2;
struct _rs_cpu_sys_dmac_llp2 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp2(val) ((rs_cpu_sys_dmac_llp2*)&(val))



#define CPU_SYS_DMAC_CTL2_L                                              (HV_DMAC_BASE_ADDRESS + 0x0C8)

#define CPU_SYS_DMAC_CTL2_L_struct                                       rs_cpu_sys_dmac_ctl2_l

typedef struct _rs_cpu_sys_dmac_ctl2_l  rs_cpu_sys_dmac_ctl2_l;
struct _rs_cpu_sys_dmac_ctl2_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl2_l(val) ((rs_cpu_sys_dmac_ctl2_l*)&(val))



#define CPU_SYS_DMAC_CTL2_H                                              (HV_DMAC_BASE_ADDRESS + 0x0CC)

#define CPU_SYS_DMAC_CTL2_H_struct                                       rs_cpu_sys_dmac_ctl2_h

typedef struct _rs_cpu_sys_dmac_ctl2_h  rs_cpu_sys_dmac_ctl2_h;
struct _rs_cpu_sys_dmac_ctl2_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl2_h(val) ((rs_cpu_sys_dmac_ctl2_h*)&(val))



#define CPU_SYS_DMAC_SSTAT2                                              (HV_DMAC_BASE_ADDRESS + 0x0D0)

#define CPU_SYS_DMAC_SSTAT2_struct                                       rs_cpu_sys_dmac_sstat2

typedef struct _rs_cpu_sys_dmac_sstat2  rs_cpu_sys_dmac_sstat2;
struct _rs_cpu_sys_dmac_sstat2 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat2(val) ((rs_cpu_sys_dmac_sstat2*)&(val))



#define CPU_SYS_DMAC_DSTAT2                                              (HV_DMAC_BASE_ADDRESS + 0x0D8)

#define CPU_SYS_DMAC_DSTAT2_struct                                       rs_cpu_sys_dmac_dstat2

typedef struct _rs_cpu_sys_dmac_dstat2  rs_cpu_sys_dmac_dstat2;
struct _rs_cpu_sys_dmac_dstat2 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat2(val) ((rs_cpu_sys_dmac_dstat2*)&(val))



#define CPU_SYS_DMAC_SSTATAR2                                            (HV_DMAC_BASE_ADDRESS + 0x0E0)

#define CPU_SYS_DMAC_SSTATAR2_struct                                     rs_cpu_sys_dmac_sstatar2

typedef struct _rs_cpu_sys_dmac_sstatar2  rs_cpu_sys_dmac_sstatar2;
struct _rs_cpu_sys_dmac_sstatar2 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar2(val) ((rs_cpu_sys_dmac_sstatar2*)&(val))



#define CPU_SYS_DMAC_DSTATAR2                                            (HV_DMAC_BASE_ADDRESS + 0x0E8)

#define CPU_SYS_DMAC_DSTATAR2_struct                                     rs_cpu_sys_dmac_dstatar2

typedef struct _rs_cpu_sys_dmac_dstatar2  rs_cpu_sys_dmac_dstatar2;
struct _rs_cpu_sys_dmac_dstatar2 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar2(val) ((rs_cpu_sys_dmac_dstatar2*)&(val))



#define CPU_SYS_DMAC_CFG2_L                                              (HV_DMAC_BASE_ADDRESS + 0x0F0)

#define CPU_SYS_DMAC_CFG2_L_struct                                       rs_cpu_sys_dmac_cfg2_l

typedef struct _rs_cpu_sys_dmac_cfg2_l  rs_cpu_sys_dmac_cfg2_l;
struct _rs_cpu_sys_dmac_cfg2_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg2_l(val) ((rs_cpu_sys_dmac_cfg2_l*)&(val))



#define CPU_SYS_DMAC_CFG2_H                                              (HV_DMAC_BASE_ADDRESS + 0x0F4)

#define CPU_SYS_DMAC_CFG2_H_struct                                       rs_cpu_sys_dmac_cfg2_h

typedef struct _rs_cpu_sys_dmac_cfg2_h  rs_cpu_sys_dmac_cfg2_h;
struct _rs_cpu_sys_dmac_cfg2_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg2_h(val) ((rs_cpu_sys_dmac_cfg2_h*)&(val))



#define CPU_SYS_DMAC_SGR2                                                (HV_DMAC_BASE_ADDRESS + 0x0F8)

#define CPU_SYS_DMAC_SGR2_struct                                         rs_cpu_sys_dmac_sgr2

typedef struct _rs_cpu_sys_dmac_sgr2  rs_cpu_sys_dmac_sgr2;
struct _rs_cpu_sys_dmac_sgr2 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr2(val) ((rs_cpu_sys_dmac_sgr2*)&(val))



#define CPU_SYS_DMAC_DSR2                                                (HV_DMAC_BASE_ADDRESS + 0x100)

#define CPU_SYS_DMAC_DSR2_struct                                         rs_cpu_sys_dmac_dsr2

typedef struct _rs_cpu_sys_dmac_dsr2  rs_cpu_sys_dmac_dsr2;
struct _rs_cpu_sys_dmac_dsr2 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr2(val) ((rs_cpu_sys_dmac_dsr2*)&(val))



#define CPU_SYS_DMAC_SAR3                                                (HV_DMAC_BASE_ADDRESS + 0x108)

#define CPU_SYS_DMAC_SAR3_struct                                         rs_cpu_sys_dmac_sar3

typedef struct _rs_cpu_sys_dmac_sar3  rs_cpu_sys_dmac_sar3;
struct _rs_cpu_sys_dmac_sar3 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar3(val) ((rs_cpu_sys_dmac_sar3*)&(val))



#define CPU_SYS_DMAC_DAR3                                                (HV_DMAC_BASE_ADDRESS + 0x110)

#define CPU_SYS_DMAC_DAR3_struct                                         rs_cpu_sys_dmac_dar3

typedef struct _rs_cpu_sys_dmac_dar3  rs_cpu_sys_dmac_dar3;
struct _rs_cpu_sys_dmac_dar3 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar3(val) ((rs_cpu_sys_dmac_dar3*)&(val))



#define CPU_SYS_DMAC_LLP3                                                (HV_DMAC_BASE_ADDRESS + 0x118)

#define CPU_SYS_DMAC_LLP3_struct                                         rs_cpu_sys_dmac_llp3

typedef struct _rs_cpu_sys_dmac_llp3  rs_cpu_sys_dmac_llp3;
struct _rs_cpu_sys_dmac_llp3 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp3(val) ((rs_cpu_sys_dmac_llp3*)&(val))



#define CPU_SYS_DMAC_CTL3_L                                              (HV_DMAC_BASE_ADDRESS + 0x120)

#define CPU_SYS_DMAC_CTL3_L_struct                                       rs_cpu_sys_dmac_ctl3_l

typedef struct _rs_cpu_sys_dmac_ctl3_l  rs_cpu_sys_dmac_ctl3_l;
struct _rs_cpu_sys_dmac_ctl3_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl3_l(val) ((rs_cpu_sys_dmac_ctl3_l*)&(val))



#define CPU_SYS_DMAC_CTL3_H                                              (HV_DMAC_BASE_ADDRESS + 0x124)

#define CPU_SYS_DMAC_CTL3_H_struct                                       rs_cpu_sys_dmac_ctl3_h

typedef struct _rs_cpu_sys_dmac_ctl3_h  rs_cpu_sys_dmac_ctl3_h;
struct _rs_cpu_sys_dmac_ctl3_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl3_h(val) ((rs_cpu_sys_dmac_ctl3_h*)&(val))



#define CPU_SYS_DMAC_SSTAT3                                              (HV_DMAC_BASE_ADDRESS + 0x128)

#define CPU_SYS_DMAC_SSTAT3_struct                                       rs_cpu_sys_dmac_sstat3

typedef struct _rs_cpu_sys_dmac_sstat3  rs_cpu_sys_dmac_sstat3;
struct _rs_cpu_sys_dmac_sstat3 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat3(val) ((rs_cpu_sys_dmac_sstat3*)&(val))



#define CPU_SYS_DMAC_DSTAT3                                              (HV_DMAC_BASE_ADDRESS + 0x130)

#define CPU_SYS_DMAC_DSTAT3_struct                                       rs_cpu_sys_dmac_dstat3

typedef struct _rs_cpu_sys_dmac_dstat3  rs_cpu_sys_dmac_dstat3;
struct _rs_cpu_sys_dmac_dstat3 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat3(val) ((rs_cpu_sys_dmac_dstat3*)&(val))



#define CPU_SYS_DMAC_SSTATAR3                                            (HV_DMAC_BASE_ADDRESS + 0x138)

#define CPU_SYS_DMAC_SSTATAR3_struct                                     rs_cpu_sys_dmac_sstatar3

typedef struct _rs_cpu_sys_dmac_sstatar3  rs_cpu_sys_dmac_sstatar3;
struct _rs_cpu_sys_dmac_sstatar3 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar3(val) ((rs_cpu_sys_dmac_sstatar3*)&(val))



#define CPU_SYS_DMAC_DSTATAR3                                            (HV_DMAC_BASE_ADDRESS + 0x140)

#define CPU_SYS_DMAC_DSTATAR3_struct                                     rs_cpu_sys_dmac_dstatar3

typedef struct _rs_cpu_sys_dmac_dstatar3  rs_cpu_sys_dmac_dstatar3;
struct _rs_cpu_sys_dmac_dstatar3 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar3(val) ((rs_cpu_sys_dmac_dstatar3*)&(val))



#define CPU_SYS_DMAC_CFG3_L                                              (HV_DMAC_BASE_ADDRESS + 0x148)

#define CPU_SYS_DMAC_CFG3_L_struct                                       rs_cpu_sys_dmac_cfg3_l

typedef struct _rs_cpu_sys_dmac_cfg3_l  rs_cpu_sys_dmac_cfg3_l;
struct _rs_cpu_sys_dmac_cfg3_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg3_l(val) ((rs_cpu_sys_dmac_cfg3_l*)&(val))



#define CPU_SYS_DMAC_CFG3_H                                              (HV_DMAC_BASE_ADDRESS + 0x14C)

#define CPU_SYS_DMAC_CFG3_H_struct                                       rs_cpu_sys_dmac_cfg3_h

typedef struct _rs_cpu_sys_dmac_cfg3_h  rs_cpu_sys_dmac_cfg3_h;
struct _rs_cpu_sys_dmac_cfg3_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg3_h(val) ((rs_cpu_sys_dmac_cfg3_h*)&(val))



#define CPU_SYS_DMAC_SGR3                                                (HV_DMAC_BASE_ADDRESS + 0x150)

#define CPU_SYS_DMAC_SGR3_struct                                         rs_cpu_sys_dmac_sgr3

typedef struct _rs_cpu_sys_dmac_sgr3  rs_cpu_sys_dmac_sgr3;
struct _rs_cpu_sys_dmac_sgr3 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr3(val) ((rs_cpu_sys_dmac_sgr3*)&(val))



#define CPU_SYS_DMAC_DSR3                                                (HV_DMAC_BASE_ADDRESS + 0x158)

#define CPU_SYS_DMAC_DSR3_struct                                         rs_cpu_sys_dmac_dsr3

typedef struct _rs_cpu_sys_dmac_dsr3  rs_cpu_sys_dmac_dsr3;
struct _rs_cpu_sys_dmac_dsr3 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr3(val) ((rs_cpu_sys_dmac_dsr3*)&(val))



#define CPU_SYS_DMAC_SAR4                                                (HV_DMAC_BASE_ADDRESS + 0x160)

#define CPU_SYS_DMAC_SAR4_struct                                         rs_cpu_sys_dmac_sar4

typedef struct _rs_cpu_sys_dmac_sar4  rs_cpu_sys_dmac_sar4;
struct _rs_cpu_sys_dmac_sar4 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar4(val) ((rs_cpu_sys_dmac_sar4*)&(val))



#define CPU_SYS_DMAC_DAR4                                                (HV_DMAC_BASE_ADDRESS + 0x168)

#define CPU_SYS_DMAC_DAR4_struct                                         rs_cpu_sys_dmac_dar4

typedef struct _rs_cpu_sys_dmac_dar4  rs_cpu_sys_dmac_dar4;
struct _rs_cpu_sys_dmac_dar4 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar4(val) ((rs_cpu_sys_dmac_dar4*)&(val))



#define CPU_SYS_DMAC_LLP4                                                (HV_DMAC_BASE_ADDRESS + 0x170)

#define CPU_SYS_DMAC_LLP4_struct                                         rs_cpu_sys_dmac_llp4

typedef struct _rs_cpu_sys_dmac_llp4  rs_cpu_sys_dmac_llp4;
struct _rs_cpu_sys_dmac_llp4 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp4(val) ((rs_cpu_sys_dmac_llp4*)&(val))



#define CPU_SYS_DMAC_CTL4_L                                              (HV_DMAC_BASE_ADDRESS + 0x178)

#define CPU_SYS_DMAC_CTL4_L_struct                                       rs_cpu_sys_dmac_ctl4_l

typedef struct _rs_cpu_sys_dmac_ctl4_l  rs_cpu_sys_dmac_ctl4_l;
struct _rs_cpu_sys_dmac_ctl4_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl4_l(val) ((rs_cpu_sys_dmac_ctl4_l*)&(val))



#define CPU_SYS_DMAC_CTL4_H                                              (HV_DMAC_BASE_ADDRESS + 0x17C)

#define CPU_SYS_DMAC_CTL4_H_struct                                       rs_cpu_sys_dmac_ctl4_h

typedef struct _rs_cpu_sys_dmac_ctl4_h  rs_cpu_sys_dmac_ctl4_h;
struct _rs_cpu_sys_dmac_ctl4_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl4_h(val) ((rs_cpu_sys_dmac_ctl4_h*)&(val))



#define CPU_SYS_DMAC_SSTAT4                                              (HV_DMAC_BASE_ADDRESS + 0x180)

#define CPU_SYS_DMAC_SSTAT4_struct                                       rs_cpu_sys_dmac_sstat4

typedef struct _rs_cpu_sys_dmac_sstat4  rs_cpu_sys_dmac_sstat4;
struct _rs_cpu_sys_dmac_sstat4 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat4(val) ((rs_cpu_sys_dmac_sstat4*)&(val))



#define CPU_SYS_DMAC_DSTAT4                                              (HV_DMAC_BASE_ADDRESS + 0x188)

#define CPU_SYS_DMAC_DSTAT4_struct                                       rs_cpu_sys_dmac_dstat4

typedef struct _rs_cpu_sys_dmac_dstat4  rs_cpu_sys_dmac_dstat4;
struct _rs_cpu_sys_dmac_dstat4 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat4(val) ((rs_cpu_sys_dmac_dstat4*)&(val))



#define CPU_SYS_DMAC_SSTATAR4                                            (HV_DMAC_BASE_ADDRESS + 0x190)

#define CPU_SYS_DMAC_SSTATAR4_struct                                     rs_cpu_sys_dmac_sstatar4

typedef struct _rs_cpu_sys_dmac_sstatar4  rs_cpu_sys_dmac_sstatar4;
struct _rs_cpu_sys_dmac_sstatar4 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar4(val) ((rs_cpu_sys_dmac_sstatar4*)&(val))



#define CPU_SYS_DMAC_DSTATAR4                                            (HV_DMAC_BASE_ADDRESS + 0x198)

#define CPU_SYS_DMAC_DSTATAR4_struct                                     rs_cpu_sys_dmac_dstatar4

typedef struct _rs_cpu_sys_dmac_dstatar4  rs_cpu_sys_dmac_dstatar4;
struct _rs_cpu_sys_dmac_dstatar4 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar4(val) ((rs_cpu_sys_dmac_dstatar4*)&(val))



#define CPU_SYS_DMAC_CFG4_L                                              (HV_DMAC_BASE_ADDRESS + 0x1A0)

#define CPU_SYS_DMAC_CFG4_L_struct                                       rs_cpu_sys_dmac_cfg4_l

typedef struct _rs_cpu_sys_dmac_cfg4_l  rs_cpu_sys_dmac_cfg4_l;
struct _rs_cpu_sys_dmac_cfg4_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg4_l(val) ((rs_cpu_sys_dmac_cfg4_l*)&(val))



#define CPU_SYS_DMAC_CFG4_H                                              (HV_DMAC_BASE_ADDRESS + 0x1A4)

#define CPU_SYS_DMAC_CFG4_H_struct                                       rs_cpu_sys_dmac_cfg4_h

typedef struct _rs_cpu_sys_dmac_cfg4_h  rs_cpu_sys_dmac_cfg4_h;
struct _rs_cpu_sys_dmac_cfg4_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg4_h(val) ((rs_cpu_sys_dmac_cfg4_h*)&(val))



#define CPU_SYS_DMAC_SGR4                                                (HV_DMAC_BASE_ADDRESS + 0x1A8)

#define CPU_SYS_DMAC_SGR4_struct                                         rs_cpu_sys_dmac_sgr4

typedef struct _rs_cpu_sys_dmac_sgr4  rs_cpu_sys_dmac_sgr4;
struct _rs_cpu_sys_dmac_sgr4 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr4(val) ((rs_cpu_sys_dmac_sgr4*)&(val))



#define CPU_SYS_DMAC_DSR4                                                (HV_DMAC_BASE_ADDRESS + 0x1B0)

#define CPU_SYS_DMAC_DSR4_struct                                         rs_cpu_sys_dmac_dsr4

typedef struct _rs_cpu_sys_dmac_dsr4  rs_cpu_sys_dmac_dsr4;
struct _rs_cpu_sys_dmac_dsr4 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr4(val) ((rs_cpu_sys_dmac_dsr4*)&(val))



#define CPU_SYS_DMAC_SAR5                                                (HV_DMAC_BASE_ADDRESS + 0x1B8)

#define CPU_SYS_DMAC_SAR5_struct                                         rs_cpu_sys_dmac_sar5

typedef struct _rs_cpu_sys_dmac_sar5  rs_cpu_sys_dmac_sar5;
struct _rs_cpu_sys_dmac_sar5 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar5(val) ((rs_cpu_sys_dmac_sar5*)&(val))



#define CPU_SYS_DMAC_DAR5                                                (HV_DMAC_BASE_ADDRESS + 0x1C0)

#define CPU_SYS_DMAC_DAR5_struct                                         rs_cpu_sys_dmac_dar5

typedef struct _rs_cpu_sys_dmac_dar5  rs_cpu_sys_dmac_dar5;
struct _rs_cpu_sys_dmac_dar5 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar5(val) ((rs_cpu_sys_dmac_dar5*)&(val))



#define CPU_SYS_DMAC_LLP5                                                (HV_DMAC_BASE_ADDRESS + 0x1C8)

#define CPU_SYS_DMAC_LLP5_struct                                         rs_cpu_sys_dmac_llp5

typedef struct _rs_cpu_sys_dmac_llp5  rs_cpu_sys_dmac_llp5;
struct _rs_cpu_sys_dmac_llp5 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp5(val) ((rs_cpu_sys_dmac_llp5*)&(val))



#define CPU_SYS_DMAC_CTL5_L                                              (HV_DMAC_BASE_ADDRESS + 0x1D0)

#define CPU_SYS_DMAC_CTL5_L_struct                                       rs_cpu_sys_dmac_ctl5_l

typedef struct _rs_cpu_sys_dmac_ctl5_l  rs_cpu_sys_dmac_ctl5_l;
struct _rs_cpu_sys_dmac_ctl5_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl5_l(val) ((rs_cpu_sys_dmac_ctl5_l*)&(val))



#define CPU_SYS_DMAC_CTL5_H                                              (HV_DMAC_BASE_ADDRESS + 0x1D4)

#define CPU_SYS_DMAC_CTL5_H_struct                                       rs_cpu_sys_dmac_ctl5_h

typedef struct _rs_cpu_sys_dmac_ctl5_h  rs_cpu_sys_dmac_ctl5_h;
struct _rs_cpu_sys_dmac_ctl5_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl5_h(val) ((rs_cpu_sys_dmac_ctl5_h*)&(val))



#define CPU_SYS_DMAC_SSTAT5                                              (HV_DMAC_BASE_ADDRESS + 0x1D8)

#define CPU_SYS_DMAC_SSTAT5_struct                                       rs_cpu_sys_dmac_sstat5

typedef struct _rs_cpu_sys_dmac_sstat5  rs_cpu_sys_dmac_sstat5;
struct _rs_cpu_sys_dmac_sstat5 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat5(val) ((rs_cpu_sys_dmac_sstat5*)&(val))



#define CPU_SYS_DMAC_DSTAT5                                              (HV_DMAC_BASE_ADDRESS + 0x1E0)

#define CPU_SYS_DMAC_DSTAT5_struct                                       rs_cpu_sys_dmac_dstat5

typedef struct _rs_cpu_sys_dmac_dstat5  rs_cpu_sys_dmac_dstat5;
struct _rs_cpu_sys_dmac_dstat5 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat5(val) ((rs_cpu_sys_dmac_dstat5*)&(val))



#define CPU_SYS_DMAC_SSTATAR5                                            (HV_DMAC_BASE_ADDRESS + 0x1E8)

#define CPU_SYS_DMAC_SSTATAR5_struct                                     rs_cpu_sys_dmac_sstatar5

typedef struct _rs_cpu_sys_dmac_sstatar5  rs_cpu_sys_dmac_sstatar5;
struct _rs_cpu_sys_dmac_sstatar5 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar5(val) ((rs_cpu_sys_dmac_sstatar5*)&(val))



#define CPU_SYS_DMAC_DSTATAR5                                            (HV_DMAC_BASE_ADDRESS + 0x1F0)

#define CPU_SYS_DMAC_DSTATAR5_struct                                     rs_cpu_sys_dmac_dstatar5

typedef struct _rs_cpu_sys_dmac_dstatar5  rs_cpu_sys_dmac_dstatar5;
struct _rs_cpu_sys_dmac_dstatar5 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar5(val) ((rs_cpu_sys_dmac_dstatar5*)&(val))



#define CPU_SYS_DMAC_CFG5_L                                              (HV_DMAC_BASE_ADDRESS + 0x1F8)

#define CPU_SYS_DMAC_CFG5_L_struct                                       rs_cpu_sys_dmac_cfg5_l

typedef struct _rs_cpu_sys_dmac_cfg5_l  rs_cpu_sys_dmac_cfg5_l;
struct _rs_cpu_sys_dmac_cfg5_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg5_l(val) ((rs_cpu_sys_dmac_cfg5_l*)&(val))



#define CPU_SYS_DMAC_CFG5_H                                              (HV_DMAC_BASE_ADDRESS + 0x1FC)

#define CPU_SYS_DMAC_CFG5_H_struct                                       rs_cpu_sys_dmac_cfg5_h

typedef struct _rs_cpu_sys_dmac_cfg5_h  rs_cpu_sys_dmac_cfg5_h;
struct _rs_cpu_sys_dmac_cfg5_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg5_h(val) ((rs_cpu_sys_dmac_cfg5_h*)&(val))



#define CPU_SYS_DMAC_SGR5                                                (HV_DMAC_BASE_ADDRESS + 0x200)

#define CPU_SYS_DMAC_SGR5_struct                                         rs_cpu_sys_dmac_sgr5

typedef struct _rs_cpu_sys_dmac_sgr5  rs_cpu_sys_dmac_sgr5;
struct _rs_cpu_sys_dmac_sgr5 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr5(val) ((rs_cpu_sys_dmac_sgr5*)&(val))



#define CPU_SYS_DMAC_DSR5                                                (HV_DMAC_BASE_ADDRESS + 0x208)

#define CPU_SYS_DMAC_DSR5_struct                                         rs_cpu_sys_dmac_dsr5

typedef struct _rs_cpu_sys_dmac_dsr5  rs_cpu_sys_dmac_dsr5;
struct _rs_cpu_sys_dmac_dsr5 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr5(val) ((rs_cpu_sys_dmac_dsr5*)&(val))



#define CPU_SYS_DMAC_SAR6                                                (HV_DMAC_BASE_ADDRESS + 0x210)

#define CPU_SYS_DMAC_SAR6_struct                                         rs_cpu_sys_dmac_sar6

typedef struct _rs_cpu_sys_dmac_sar6  rs_cpu_sys_dmac_sar6;
struct _rs_cpu_sys_dmac_sar6 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar6(val) ((rs_cpu_sys_dmac_sar6*)&(val))



#define CPU_SYS_DMAC_DAR6                                                (HV_DMAC_BASE_ADDRESS + 0x218)

#define CPU_SYS_DMAC_DAR6_struct                                         rs_cpu_sys_dmac_dar6

typedef struct _rs_cpu_sys_dmac_dar6  rs_cpu_sys_dmac_dar6;
struct _rs_cpu_sys_dmac_dar6 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar6(val) ((rs_cpu_sys_dmac_dar6*)&(val))



#define CPU_SYS_DMAC_LLP6                                                (HV_DMAC_BASE_ADDRESS + 0x220)

#define CPU_SYS_DMAC_LLP6_struct                                         rs_cpu_sys_dmac_llp6

typedef struct _rs_cpu_sys_dmac_llp6  rs_cpu_sys_dmac_llp6;
struct _rs_cpu_sys_dmac_llp6 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp6(val) ((rs_cpu_sys_dmac_llp6*)&(val))



#define CPU_SYS_DMAC_CTL6_L                                              (HV_DMAC_BASE_ADDRESS + 0x228)

#define CPU_SYS_DMAC_CTL6_L_struct                                       rs_cpu_sys_dmac_ctl6_l

typedef struct _rs_cpu_sys_dmac_ctl6_l  rs_cpu_sys_dmac_ctl6_l;
struct _rs_cpu_sys_dmac_ctl6_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl6_l(val) ((rs_cpu_sys_dmac_ctl6_l*)&(val))



#define CPU_SYS_DMAC_CTL6_H                                              (HV_DMAC_BASE_ADDRESS + 0x22C)

#define CPU_SYS_DMAC_CTL6_H_struct                                       rs_cpu_sys_dmac_ctl6_h

typedef struct _rs_cpu_sys_dmac_ctl6_h  rs_cpu_sys_dmac_ctl6_h;
struct _rs_cpu_sys_dmac_ctl6_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl6_h(val) ((rs_cpu_sys_dmac_ctl6_h*)&(val))



#define CPU_SYS_DMAC_SSTAT6                                              (HV_DMAC_BASE_ADDRESS + 0x230)

#define CPU_SYS_DMAC_SSTAT6_struct                                       rs_cpu_sys_dmac_sstat6

typedef struct _rs_cpu_sys_dmac_sstat6  rs_cpu_sys_dmac_sstat6;
struct _rs_cpu_sys_dmac_sstat6 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat6(val) ((rs_cpu_sys_dmac_sstat6*)&(val))



#define CPU_SYS_DMAC_DSTAT6                                              (HV_DMAC_BASE_ADDRESS + 0x238)

#define CPU_SYS_DMAC_DSTAT6_struct                                       rs_cpu_sys_dmac_dstat6

typedef struct _rs_cpu_sys_dmac_dstat6  rs_cpu_sys_dmac_dstat6;
struct _rs_cpu_sys_dmac_dstat6 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat6(val) ((rs_cpu_sys_dmac_dstat6*)&(val))



#define CPU_SYS_DMAC_SSTATAR6                                            (HV_DMAC_BASE_ADDRESS + 0x240)

#define CPU_SYS_DMAC_SSTATAR6_struct                                     rs_cpu_sys_dmac_sstatar6

typedef struct _rs_cpu_sys_dmac_sstatar6  rs_cpu_sys_dmac_sstatar6;
struct _rs_cpu_sys_dmac_sstatar6 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar6(val) ((rs_cpu_sys_dmac_sstatar6*)&(val))



#define CPU_SYS_DMAC_DSTATAR6                                            (HV_DMAC_BASE_ADDRESS + 0x248)

#define CPU_SYS_DMAC_DSTATAR6_struct                                     rs_cpu_sys_dmac_dstatar6

typedef struct _rs_cpu_sys_dmac_dstatar6  rs_cpu_sys_dmac_dstatar6;
struct _rs_cpu_sys_dmac_dstatar6 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar6(val) ((rs_cpu_sys_dmac_dstatar6*)&(val))



#define CPU_SYS_DMAC_CFG6_L                                              (HV_DMAC_BASE_ADDRESS + 0x250)

#define CPU_SYS_DMAC_CFG6_L_struct                                       rs_cpu_sys_dmac_cfg6_l

typedef struct _rs_cpu_sys_dmac_cfg6_l  rs_cpu_sys_dmac_cfg6_l;
struct _rs_cpu_sys_dmac_cfg6_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg6_l(val) ((rs_cpu_sys_dmac_cfg6_l*)&(val))



#define CPU_SYS_DMAC_CFG6_H                                              (HV_DMAC_BASE_ADDRESS + 0x254)

#define CPU_SYS_DMAC_CFG6_H_struct                                       rs_cpu_sys_dmac_cfg6_h

typedef struct _rs_cpu_sys_dmac_cfg6_h  rs_cpu_sys_dmac_cfg6_h;
struct _rs_cpu_sys_dmac_cfg6_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg6_h(val) ((rs_cpu_sys_dmac_cfg6_h*)&(val))



#define CPU_SYS_DMAC_SGR6                                                (HV_DMAC_BASE_ADDRESS + 0x258)

#define CPU_SYS_DMAC_SGR6_struct                                         rs_cpu_sys_dmac_sgr6

typedef struct _rs_cpu_sys_dmac_sgr6  rs_cpu_sys_dmac_sgr6;
struct _rs_cpu_sys_dmac_sgr6 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr6(val) ((rs_cpu_sys_dmac_sgr6*)&(val))



#define CPU_SYS_DMAC_DSR6                                                (HV_DMAC_BASE_ADDRESS + 0x260)

#define CPU_SYS_DMAC_DSR6_struct                                         rs_cpu_sys_dmac_dsr6

typedef struct _rs_cpu_sys_dmac_dsr6  rs_cpu_sys_dmac_dsr6;
struct _rs_cpu_sys_dmac_dsr6 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr6(val) ((rs_cpu_sys_dmac_dsr6*)&(val))



#define CPU_SYS_DMAC_SAR7                                                (HV_DMAC_BASE_ADDRESS + 0x268)

#define CPU_SYS_DMAC_SAR7_struct                                         rs_cpu_sys_dmac_sar7

typedef struct _rs_cpu_sys_dmac_sar7  rs_cpu_sys_dmac_sar7;
struct _rs_cpu_sys_dmac_sar7 {
    unsigned int SAR                                        :32;
};
#define cpu_sys_dmac_sar7(val) ((rs_cpu_sys_dmac_sar7*)&(val))



#define CPU_SYS_DMAC_DAR7                                                (HV_DMAC_BASE_ADDRESS + 0x270)

#define CPU_SYS_DMAC_DAR7_struct                                         rs_cpu_sys_dmac_dar7

typedef struct _rs_cpu_sys_dmac_dar7  rs_cpu_sys_dmac_dar7;
struct _rs_cpu_sys_dmac_dar7 {
    unsigned int DAR                                        :32;
};
#define cpu_sys_dmac_dar7(val) ((rs_cpu_sys_dmac_dar7*)&(val))



#define CPU_SYS_DMAC_LLP7                                                (HV_DMAC_BASE_ADDRESS + 0x278)

#define CPU_SYS_DMAC_LLP7_struct                                         rs_cpu_sys_dmac_llp7

typedef struct _rs_cpu_sys_dmac_llp7  rs_cpu_sys_dmac_llp7;
struct _rs_cpu_sys_dmac_llp7 {
    unsigned int LMS                                        : 2;
    unsigned int LOC                                        :30;
};
#define cpu_sys_dmac_llp7(val) ((rs_cpu_sys_dmac_llp7*)&(val))



#define CPU_SYS_DMAC_CTL7_L                                              (HV_DMAC_BASE_ADDRESS + 0x280)

#define CPU_SYS_DMAC_CTL7_L_struct                                       rs_cpu_sys_dmac_ctl7_l

typedef struct _rs_cpu_sys_dmac_ctl7_l  rs_cpu_sys_dmac_ctl7_l;
struct _rs_cpu_sys_dmac_ctl7_l {
    unsigned int INT_EN                                     : 1;
    unsigned int DST_TR_WIDTH                               : 3;
    unsigned int SRC_TR_WIDTH                               : 3;
    unsigned int DINC                                       : 2;
    unsigned int SINC                                       : 2;
    unsigned int DEST_MSIZE                                 : 3;
    unsigned int SRC_MSIZE                                  : 3;
    unsigned int SRC_GATHER_EN                              : 1;
    unsigned int DST_SCATTER_EN                             : 1;
    unsigned int reserved                                   : 1;
    unsigned int TT_FC                                      : 3;
    unsigned int DMS                                        : 2;
    unsigned int SMS                                        : 2;
    unsigned int LLP_DST_EN                                 : 1;
    unsigned int LLP_SRC_EN                                 : 1;
    unsigned int reserved_1                                 : 3;
};
#define cpu_sys_dmac_ctl7_l(val) ((rs_cpu_sys_dmac_ctl7_l*)&(val))



#define CPU_SYS_DMAC_CTL7_H                                              (HV_DMAC_BASE_ADDRESS + 0x284)

#define CPU_SYS_DMAC_CTL7_H_struct                                       rs_cpu_sys_dmac_ctl7_h

typedef struct _rs_cpu_sys_dmac_ctl7_h  rs_cpu_sys_dmac_ctl7_h;
struct _rs_cpu_sys_dmac_ctl7_h {
    unsigned int BLOCK_TS                                   :12;
    unsigned int DONE                                       : 1;
    unsigned int reserved                                   :19;
};
#define cpu_sys_dmac_ctl7_h(val) ((rs_cpu_sys_dmac_ctl7_h*)&(val))



#define CPU_SYS_DMAC_SSTAT7                                              (HV_DMAC_BASE_ADDRESS + 0x288)

#define CPU_SYS_DMAC_SSTAT7_struct                                       rs_cpu_sys_dmac_sstat7

typedef struct _rs_cpu_sys_dmac_sstat7  rs_cpu_sys_dmac_sstat7;
struct _rs_cpu_sys_dmac_sstat7 {
    unsigned int SSTAT                                      :32;
};
#define cpu_sys_dmac_sstat7(val) ((rs_cpu_sys_dmac_sstat7*)&(val))



#define CPU_SYS_DMAC_DSTAT7                                              (HV_DMAC_BASE_ADDRESS + 0x290)

#define CPU_SYS_DMAC_DSTAT7_struct                                       rs_cpu_sys_dmac_dstat7

typedef struct _rs_cpu_sys_dmac_dstat7  rs_cpu_sys_dmac_dstat7;
struct _rs_cpu_sys_dmac_dstat7 {
    unsigned int DSTAT                                      :32;
};
#define cpu_sys_dmac_dstat7(val) ((rs_cpu_sys_dmac_dstat7*)&(val))



#define CPU_SYS_DMAC_SSTATAR7                                            (HV_DMAC_BASE_ADDRESS + 0x298)

#define CPU_SYS_DMAC_SSTATAR7_struct                                     rs_cpu_sys_dmac_sstatar7

typedef struct _rs_cpu_sys_dmac_sstatar7  rs_cpu_sys_dmac_sstatar7;
struct _rs_cpu_sys_dmac_sstatar7 {
    unsigned int SSTATAR                                    :32;
};
#define cpu_sys_dmac_sstatar7(val) ((rs_cpu_sys_dmac_sstatar7*)&(val))



#define CPU_SYS_DMAC_DSTATAR7                                            (HV_DMAC_BASE_ADDRESS + 0x2A0)

#define CPU_SYS_DMAC_DSTATAR7_struct                                     rs_cpu_sys_dmac_dstatar7

typedef struct _rs_cpu_sys_dmac_dstatar7  rs_cpu_sys_dmac_dstatar7;
struct _rs_cpu_sys_dmac_dstatar7 {
    unsigned int DSTATAR                                    :32;
};
#define cpu_sys_dmac_dstatar7(val) ((rs_cpu_sys_dmac_dstatar7*)&(val))



#define CPU_SYS_DMAC_CFG7_L                                              (HV_DMAC_BASE_ADDRESS + 0x2A8)

#define CPU_SYS_DMAC_CFG7_L_struct                                       rs_cpu_sys_dmac_cfg7_l

typedef struct _rs_cpu_sys_dmac_cfg7_l  rs_cpu_sys_dmac_cfg7_l;
struct _rs_cpu_sys_dmac_cfg7_l {
    unsigned int reserved                                   : 5;
    unsigned int CH_PRIOR                                   : 3;
    unsigned int CH_SUSP                                    : 1;
    unsigned int FIFO_EMPTY                                 : 1;
    unsigned int HS_SEL_DST                                 : 1;
    unsigned int HS_SEL_SRC                                 : 1;
    unsigned int LOCK_CH_L                                  : 2;
    unsigned int LOCK_B_L                                   : 2;
    unsigned int LOCK_CH                                    : 1;
    unsigned int LOCK_B                                     : 1;
    unsigned int DST_HS_POL                                 : 1;
    unsigned int SRC_HS_POL                                 : 1;
    unsigned int MAX_ABRST                                  :10;
    unsigned int RELOAD_SRC                                 : 1;
    unsigned int RELOAD_DST                                 : 1;
};
#define cpu_sys_dmac_cfg7_l(val) ((rs_cpu_sys_dmac_cfg7_l*)&(val))



#define CPU_SYS_DMAC_CFG7_H                                              (HV_DMAC_BASE_ADDRESS + 0x2AC)

#define CPU_SYS_DMAC_CFG7_H_struct                                       rs_cpu_sys_dmac_cfg7_h

typedef struct _rs_cpu_sys_dmac_cfg7_h  rs_cpu_sys_dmac_cfg7_h;
struct _rs_cpu_sys_dmac_cfg7_h {
    unsigned int FCMODE                                     : 1;
    unsigned int FIFO_MODE                                  : 1;
    unsigned int PROTCTL                                    : 3;
    unsigned int DS_UPD_EN                                  : 1;
    unsigned int SS_UPD_EN                                  : 1;
    unsigned int SRC_PER                                    : 4;
    unsigned int DEST_PER                                   : 4;
    unsigned int reserved                                   :17;
};
#define cpu_sys_dmac_cfg7_h(val) ((rs_cpu_sys_dmac_cfg7_h*)&(val))



#define CPU_SYS_DMAC_SGR7                                                (HV_DMAC_BASE_ADDRESS + 0x2B0)

#define CPU_SYS_DMAC_SGR7_struct                                         rs_cpu_sys_dmac_sgr7

typedef struct _rs_cpu_sys_dmac_sgr7  rs_cpu_sys_dmac_sgr7;
struct _rs_cpu_sys_dmac_sgr7 {
    unsigned int SGI                                        :20;
    unsigned int SGC                                        :12;
};
#define cpu_sys_dmac_sgr7(val) ((rs_cpu_sys_dmac_sgr7*)&(val))



#define CPU_SYS_DMAC_DSR7                                                (HV_DMAC_BASE_ADDRESS + 0x2B8)

#define CPU_SYS_DMAC_DSR7_struct                                         rs_cpu_sys_dmac_dsr7

typedef struct _rs_cpu_sys_dmac_dsr7  rs_cpu_sys_dmac_dsr7;
struct _rs_cpu_sys_dmac_dsr7 {
    unsigned int DGI                                        :20;
    unsigned int DGC                                        :12;
};
#define cpu_sys_dmac_dsr7(val) ((rs_cpu_sys_dmac_dsr7*)&(val))



#define CPU_SYS_DMAC_RAWTFR                                              (HV_DMAC_BASE_ADDRESS + 0x2C0)

#define CPU_SYS_DMAC_RAWTFR_struct                                       rs_cpu_sys_dmac_rawtfr

typedef struct _rs_cpu_sys_dmac_rawtfr  rs_cpu_sys_dmac_rawtfr;
struct _rs_cpu_sys_dmac_rawtfr {
    unsigned int RAW                                        : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_rawtfr(val) ((rs_cpu_sys_dmac_rawtfr*)&(val))



#define CPU_SYS_DMAC_RAWBLOCK                                            (HV_DMAC_BASE_ADDRESS + 0x2C8)

#define CPU_SYS_DMAC_RAWBLOCK_struct                                     rs_cpu_sys_dmac_rawblock

typedef struct _rs_cpu_sys_dmac_rawblock  rs_cpu_sys_dmac_rawblock;
struct _rs_cpu_sys_dmac_rawblock {
    unsigned int RAW                                        : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_rawblock(val) ((rs_cpu_sys_dmac_rawblock*)&(val))



#define CPU_SYS_DMAC_RAWSRCTRAN                                          (HV_DMAC_BASE_ADDRESS + 0x2D0)

#define CPU_SYS_DMAC_RAWSRCTRAN_struct                                   rs_cpu_sys_dmac_rawsrctran

typedef struct _rs_cpu_sys_dmac_rawsrctran  rs_cpu_sys_dmac_rawsrctran;
struct _rs_cpu_sys_dmac_rawsrctran {
    unsigned int RAW                                        : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_rawsrctran(val) ((rs_cpu_sys_dmac_rawsrctran*)&(val))



#define CPU_SYS_DMAC_RAWDSTTRAN                                          (HV_DMAC_BASE_ADDRESS + 0x2D8)

#define CPU_SYS_DMAC_RAWDSTTRAN_struct                                   rs_cpu_sys_dmac_rawdsttran

typedef struct _rs_cpu_sys_dmac_rawdsttran  rs_cpu_sys_dmac_rawdsttran;
struct _rs_cpu_sys_dmac_rawdsttran {
    unsigned int RAW                                        : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_rawdsttran(val) ((rs_cpu_sys_dmac_rawdsttran*)&(val))



#define CPU_SYS_DMAC_RAWERR                                              (HV_DMAC_BASE_ADDRESS + 0x2E0)

#define CPU_SYS_DMAC_RAWERR_struct                                       rs_cpu_sys_dmac_rawerr

typedef struct _rs_cpu_sys_dmac_rawerr  rs_cpu_sys_dmac_rawerr;
struct _rs_cpu_sys_dmac_rawerr {
    unsigned int RAW                                        : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_rawerr(val) ((rs_cpu_sys_dmac_rawerr*)&(val))



#define CPU_SYS_DMAC_STATUSTFR                                           (HV_DMAC_BASE_ADDRESS + 0x2E8)

#define CPU_SYS_DMAC_STATUSTFR_struct                                    rs_cpu_sys_dmac_statustfr

typedef struct _rs_cpu_sys_dmac_statustfr  rs_cpu_sys_dmac_statustfr;
struct _rs_cpu_sys_dmac_statustfr {
    unsigned int STATUS                                     : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_statustfr(val) ((rs_cpu_sys_dmac_statustfr*)&(val))



#define CPU_SYS_DMAC_STATUSBLOCK                                         (HV_DMAC_BASE_ADDRESS + 0x2F0)

#define CPU_SYS_DMAC_STATUSBLOCK_struct                                  rs_cpu_sys_dmac_statusblock

typedef struct _rs_cpu_sys_dmac_statusblock  rs_cpu_sys_dmac_statusblock;
struct _rs_cpu_sys_dmac_statusblock {
    unsigned int STATUS                                     : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_statusblock(val) ((rs_cpu_sys_dmac_statusblock*)&(val))



#define CPU_SYS_DMAC_STATUSSRCTRAN                                       (HV_DMAC_BASE_ADDRESS + 0x2F8)

#define CPU_SYS_DMAC_STATUSSRCTRAN_struct                                rs_cpu_sys_dmac_statussrctran

typedef struct _rs_cpu_sys_dmac_statussrctran  rs_cpu_sys_dmac_statussrctran;
struct _rs_cpu_sys_dmac_statussrctran {
    unsigned int STATUS                                     : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_statussrctran(val) ((rs_cpu_sys_dmac_statussrctran*)&(val))



#define CPU_SYS_DMAC_STATUSDSTTRAN                                       (HV_DMAC_BASE_ADDRESS + 0x300)

#define CPU_SYS_DMAC_STATUSDSTTRAN_struct                                rs_cpu_sys_dmac_statusdsttran

typedef struct _rs_cpu_sys_dmac_statusdsttran  rs_cpu_sys_dmac_statusdsttran;
struct _rs_cpu_sys_dmac_statusdsttran {
    unsigned int STATUS                                     : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_statusdsttran(val) ((rs_cpu_sys_dmac_statusdsttran*)&(val))



#define CPU_SYS_DMAC_STATUSERR                                           (HV_DMAC_BASE_ADDRESS + 0x308)

#define CPU_SYS_DMAC_STATUSERR_struct                                    rs_cpu_sys_dmac_statuserr

typedef struct _rs_cpu_sys_dmac_statuserr  rs_cpu_sys_dmac_statuserr;
struct _rs_cpu_sys_dmac_statuserr {
    unsigned int STATUS                                     : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_statuserr(val) ((rs_cpu_sys_dmac_statuserr*)&(val))



#define CPU_SYS_DMAC_MASKTFR                                             (HV_DMAC_BASE_ADDRESS + 0x310)

#define CPU_SYS_DMAC_MASKTFR_struct                                      rs_cpu_sys_dmac_masktfr

typedef struct _rs_cpu_sys_dmac_masktfr  rs_cpu_sys_dmac_masktfr;
struct _rs_cpu_sys_dmac_masktfr {
    unsigned int INT_MASK                                   : 8;
    unsigned int INT_MASK_WE                                : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_masktfr(val) ((rs_cpu_sys_dmac_masktfr*)&(val))



#define CPU_SYS_DMAC_MASKBLOCK                                           (HV_DMAC_BASE_ADDRESS + 0x318)

#define CPU_SYS_DMAC_MASKBLOCK_struct                                    rs_cpu_sys_dmac_maskblock

typedef struct _rs_cpu_sys_dmac_maskblock  rs_cpu_sys_dmac_maskblock;
struct _rs_cpu_sys_dmac_maskblock {
    unsigned int INT_MASK                                   : 8;
    unsigned int INT_MASK_WE                                : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_maskblock(val) ((rs_cpu_sys_dmac_maskblock*)&(val))



#define CPU_SYS_DMAC_MASKSRCTRAN                                         (HV_DMAC_BASE_ADDRESS + 0x320)

#define CPU_SYS_DMAC_MASKSRCTRAN_struct                                  rs_cpu_sys_dmac_masksrctran

typedef struct _rs_cpu_sys_dmac_masksrctran  rs_cpu_sys_dmac_masksrctran;
struct _rs_cpu_sys_dmac_masksrctran {
    unsigned int INT_MASK                                   : 8;
    unsigned int INT_MASK_WE                                : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_masksrctran(val) ((rs_cpu_sys_dmac_masksrctran*)&(val))



#define CPU_SYS_DMAC_MASKDSTTRAN                                         (HV_DMAC_BASE_ADDRESS + 0x328)

#define CPU_SYS_DMAC_MASKDSTTRAN_struct                                  rs_cpu_sys_dmac_maskdsttran

typedef struct _rs_cpu_sys_dmac_maskdsttran  rs_cpu_sys_dmac_maskdsttran;
struct _rs_cpu_sys_dmac_maskdsttran {
    unsigned int INT_MASK                                   : 8;
    unsigned int INT_MASK_WE                                : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_maskdsttran(val) ((rs_cpu_sys_dmac_maskdsttran*)&(val))



#define CPU_SYS_DMAC_MASKERR                                             (HV_DMAC_BASE_ADDRESS + 0x330)

#define CPU_SYS_DMAC_MASKERR_struct                                      rs_cpu_sys_dmac_maskerr

typedef struct _rs_cpu_sys_dmac_maskerr  rs_cpu_sys_dmac_maskerr;
struct _rs_cpu_sys_dmac_maskerr {
    unsigned int INT_MASK                                   : 8;
    unsigned int INT_MASK_WE                                : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_maskerr(val) ((rs_cpu_sys_dmac_maskerr*)&(val))



#define CPU_SYS_DMAC_CLEARTFR                                            (HV_DMAC_BASE_ADDRESS + 0x338)

#define CPU_SYS_DMAC_CLEARTFR_struct                                     rs_cpu_sys_dmac_cleartfr

typedef struct _rs_cpu_sys_dmac_cleartfr  rs_cpu_sys_dmac_cleartfr;
struct _rs_cpu_sys_dmac_cleartfr {
    unsigned int CLEAR                                      : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_cleartfr(val) ((rs_cpu_sys_dmac_cleartfr*)&(val))



#define CPU_SYS_DMAC_CLEARBLOCK                                          (HV_DMAC_BASE_ADDRESS + 0x340)

#define CPU_SYS_DMAC_CLEARBLOCK_struct                                   rs_cpu_sys_dmac_clearblock

typedef struct _rs_cpu_sys_dmac_clearblock  rs_cpu_sys_dmac_clearblock;
struct _rs_cpu_sys_dmac_clearblock {
    unsigned int CLEAR                                      : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_clearblock(val) ((rs_cpu_sys_dmac_clearblock*)&(val))



#define CPU_SYS_DMAC_CLEARSRCTRAN                                        (HV_DMAC_BASE_ADDRESS + 0x348)

#define CPU_SYS_DMAC_CLEARSRCTRAN_struct                                 rs_cpu_sys_dmac_clearsrctran

typedef struct _rs_cpu_sys_dmac_clearsrctran  rs_cpu_sys_dmac_clearsrctran;
struct _rs_cpu_sys_dmac_clearsrctran {
    unsigned int CLEAR                                      : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_clearsrctran(val) ((rs_cpu_sys_dmac_clearsrctran*)&(val))



#define CPU_SYS_DMAC_CLEARDSTTRAN                                        (HV_DMAC_BASE_ADDRESS + 0x350)

#define CPU_SYS_DMAC_CLEARDSTTRAN_struct                                 rs_cpu_sys_dmac_cleardsttran

typedef struct _rs_cpu_sys_dmac_cleardsttran  rs_cpu_sys_dmac_cleardsttran;
struct _rs_cpu_sys_dmac_cleardsttran {
    unsigned int CLEAR                                      : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_cleardsttran(val) ((rs_cpu_sys_dmac_cleardsttran*)&(val))



#define CPU_SYS_DMAC_CLEARERR                                            (HV_DMAC_BASE_ADDRESS + 0x358)

#define CPU_SYS_DMAC_CLEARERR_struct                                     rs_cpu_sys_dmac_clearerr

typedef struct _rs_cpu_sys_dmac_clearerr  rs_cpu_sys_dmac_clearerr;
struct _rs_cpu_sys_dmac_clearerr {
    unsigned int CLEAR                                      : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_dmac_clearerr(val) ((rs_cpu_sys_dmac_clearerr*)&(val))



#define CPU_SYS_DMAC_STATUSINT                                           (HV_DMAC_BASE_ADDRESS + 0x360)

#define CPU_SYS_DMAC_STATUSINT_struct                                    rs_cpu_sys_dmac_statusint

typedef struct _rs_cpu_sys_dmac_statusint  rs_cpu_sys_dmac_statusint;
struct _rs_cpu_sys_dmac_statusint {
    unsigned int TFR                                        : 1;
    unsigned int BLOCK                                      : 1;
    unsigned int SRCT                                       : 1;
    unsigned int DSTT                                       : 1;
    unsigned int ERR                                        : 1;
    unsigned int reserved                                   :27;
};
#define cpu_sys_dmac_statusint(val) ((rs_cpu_sys_dmac_statusint*)&(val))



#define CPU_SYS_DMAC_REQSRCREG                                           (HV_DMAC_BASE_ADDRESS + 0x368)

#define CPU_SYS_DMAC_REQSRCREG_struct                                    rs_cpu_sys_dmac_reqsrcreg

typedef struct _rs_cpu_sys_dmac_reqsrcreg  rs_cpu_sys_dmac_reqsrcreg;
struct _rs_cpu_sys_dmac_reqsrcreg {
    unsigned int SRC_REQ                                    : 8;
    unsigned int SRC_REQ_WE                                 : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_reqsrcreg(val) ((rs_cpu_sys_dmac_reqsrcreg*)&(val))



#define CPU_SYS_DMAC_REQDSTREG                                           (HV_DMAC_BASE_ADDRESS + 0x370)

#define CPU_SYS_DMAC_REQDSTREG_struct                                    rs_cpu_sys_dmac_reqdstreg

typedef struct _rs_cpu_sys_dmac_reqdstreg  rs_cpu_sys_dmac_reqdstreg;
struct _rs_cpu_sys_dmac_reqdstreg {
    unsigned int DST_REQ                                    : 8;
    unsigned int DST_REQ_WE                                 : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_reqdstreg(val) ((rs_cpu_sys_dmac_reqdstreg*)&(val))



#define CPU_SYS_DMAC_SGLRQSRCREG                                         (HV_DMAC_BASE_ADDRESS + 0x378)

#define CPU_SYS_DMAC_SGLRQSRCREG_struct                                  rs_cpu_sys_dmac_sglrqsrcreg

typedef struct _rs_cpu_sys_dmac_sglrqsrcreg  rs_cpu_sys_dmac_sglrqsrcreg;
struct _rs_cpu_sys_dmac_sglrqsrcreg {
    unsigned int SRC_SGLREQ                                 : 8;
    unsigned int SRC_SGLREQ_WE                              : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_sglrqsrcreg(val) ((rs_cpu_sys_dmac_sglrqsrcreg*)&(val))



#define CPU_SYS_DMAC_SGLRQDSTREG                                         (HV_DMAC_BASE_ADDRESS + 0x380)

#define CPU_SYS_DMAC_SGLRQDSTREG_struct                                  rs_cpu_sys_dmac_sglrqdstreg

typedef struct _rs_cpu_sys_dmac_sglrqdstreg  rs_cpu_sys_dmac_sglrqdstreg;
struct _rs_cpu_sys_dmac_sglrqdstreg {
    unsigned int DST_SGLREQ                                 : 8;
    unsigned int DST_SGLREQ_WE                              : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_sglrqdstreg(val) ((rs_cpu_sys_dmac_sglrqdstreg*)&(val))



#define CPU_SYS_DMAC_LSTSRCREG                                           (HV_DMAC_BASE_ADDRESS + 0x388)

#define CPU_SYS_DMAC_LSTSRCREG_struct                                    rs_cpu_sys_dmac_lstsrcreg

typedef struct _rs_cpu_sys_dmac_lstsrcreg  rs_cpu_sys_dmac_lstsrcreg;
struct _rs_cpu_sys_dmac_lstsrcreg {
    unsigned int LSTSRC                                     : 8;
    unsigned int LSTSRC_WE                                  : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_lstsrcreg(val) ((rs_cpu_sys_dmac_lstsrcreg*)&(val))



#define CPU_SYS_DMAC_LSTDSTREG                                           (HV_DMAC_BASE_ADDRESS + 0x390)

#define CPU_SYS_DMAC_LSTDSTREG_struct                                    rs_cpu_sys_dmac_lstdstreg

typedef struct _rs_cpu_sys_dmac_lstdstreg  rs_cpu_sys_dmac_lstdstreg;
struct _rs_cpu_sys_dmac_lstdstreg {
    unsigned int LSTDST                                     : 8;
    unsigned int LSTDST_WE                                  : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_lstdstreg(val) ((rs_cpu_sys_dmac_lstdstreg*)&(val))



#define CPU_SYS_DMACFGREG                                                (HV_DMAC_BASE_ADDRESS + 0x398)

#define CPU_SYS_DMACFGREG_struct                                         rs_cpu_sys_dmacfgreg

typedef struct _rs_cpu_sys_dmacfgreg  rs_cpu_sys_dmacfgreg;
struct _rs_cpu_sys_dmacfgreg {
    unsigned int DMA_EN                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_dmacfgreg(val) ((rs_cpu_sys_dmacfgreg*)&(val))



#define CPU_SYS_DMAC_CHENREG                                             (HV_DMAC_BASE_ADDRESS + 0x3A0)

#define CPU_SYS_DMAC_CHENREG_struct                                      rs_cpu_sys_dmac_chenreg

typedef struct _rs_cpu_sys_dmac_chenreg  rs_cpu_sys_dmac_chenreg;
struct _rs_cpu_sys_dmac_chenreg {
    unsigned int CH_EN                                      : 8;
    unsigned int CH_EN_WE                                   : 8;
    unsigned int reserved                                   :16;
};
#define cpu_sys_dmac_chenreg(val) ((rs_cpu_sys_dmac_chenreg*)&(val))



#define CPU_SYS_DMAC_DMAIDREG                                            (HV_DMAC_BASE_ADDRESS + 0x3A8)

#define CPU_SYS_DMAC_DMAIDREG_struct                                     rs_cpu_sys_dmac_dmaidreg

typedef struct _rs_cpu_sys_dmac_dmaidreg  rs_cpu_sys_dmac_dmaidreg;
struct _rs_cpu_sys_dmac_dmaidreg {
    unsigned int DMA_ID                                     :32;
};
#define cpu_sys_dmac_dmaidreg(val) ((rs_cpu_sys_dmac_dmaidreg*)&(val))



#define CPU_SYS_DMAC_DMATESTREG                                          (HV_DMAC_BASE_ADDRESS + 0x3B0)

#define CPU_SYS_DMAC_DMATESTREG_struct                                   rs_cpu_sys_dmac_dmatestreg

typedef struct _rs_cpu_sys_dmac_dmatestreg  rs_cpu_sys_dmac_dmatestreg;
struct _rs_cpu_sys_dmac_dmatestreg {
    unsigned int TEST_SLV_IF                                : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_dmac_dmatestreg(val) ((rs_cpu_sys_dmac_dmatestreg*)&(val))



#define CPU_SYS_DMAC_DMALPTIMEOUTREG                                     (HV_DMAC_BASE_ADDRESS + 0x3B8)

#define CPU_SYS_DMAC_DMALPTIMEOUTREG_struct                              rs_cpu_sys_dmac_dmalptimeoutreg

typedef struct _rs_cpu_sys_dmac_dmalptimeoutreg  rs_cpu_sys_dmac_dmalptimeoutreg;
struct _rs_cpu_sys_dmac_dmalptimeoutreg {
    unsigned int DMA_LP_TIMEOUT                             : 6;
    unsigned int reserved                                   :26;
};
#define cpu_sys_dmac_dmalptimeoutreg(val) ((rs_cpu_sys_dmac_dmalptimeoutreg*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH7                                 (HV_DMAC_BASE_ADDRESS + 0x3CC)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH7_struct                          rs_cpu_sys_dmac_dma_comp_params_ch7

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch7  rs_cpu_sys_dmac_dma_comp_params_ch7;
struct _rs_cpu_sys_dmac_dma_comp_params_ch7 {
    unsigned int CH7_DTW                                    : 3;
    unsigned int CH7_STW                                    : 3;
    unsigned int CH7_STAT_DST                               : 1;
    unsigned int CH7_STAT_SRC                               : 1;
    unsigned int CH7_DST_SCA_EN                             : 1;
    unsigned int CH7_SRC_GAT_EN                             : 1;
    unsigned int CH7_LOCK_EN                                : 1;
    unsigned int CH7_MULTI_BLK_EN                           : 1;
    unsigned int CH7_CTL_WB_EN                              : 1;
    unsigned int CH7_HC_LLP                                 : 1;
    unsigned int CH7_FC                                     : 2;
    unsigned int CH7_MAX_MULT_SIZE                          : 3;
    unsigned int CH7_DMS                                    : 3;
    unsigned int CH7_LMS                                    : 3;
    unsigned int CH7_SMS                                    : 3;
    unsigned int CH7_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch7(val) ((rs_cpu_sys_dmac_dma_comp_params_ch7*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH6                                 (HV_DMAC_BASE_ADDRESS + 0x3D0)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH6_struct                          rs_cpu_sys_dmac_dma_comp_params_ch6

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch6  rs_cpu_sys_dmac_dma_comp_params_ch6;
struct _rs_cpu_sys_dmac_dma_comp_params_ch6 {
    unsigned int CH6_DTW                                    : 3;
    unsigned int CH6_STW                                    : 3;
    unsigned int CH6_STAT_DST                               : 1;
    unsigned int CH6_STAT_SRC                               : 1;
    unsigned int CH6_DST_SCA_EN                             : 1;
    unsigned int CH6_SRC_GAT_EN                             : 1;
    unsigned int CH6_LOCK_EN                                : 1;
    unsigned int CH6_MULTI_BLK_EN                           : 1;
    unsigned int CH6_CTL_WB_EN                              : 1;
    unsigned int CH6_HC_LLP                                 : 1;
    unsigned int CH6_FC                                     : 2;
    unsigned int CH6_MAX_MULT_SIZE                          : 3;
    unsigned int CH6_DMS                                    : 3;
    unsigned int CH6_LMS                                    : 3;
    unsigned int CH6_SMS                                    : 3;
    unsigned int CH6_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch6(val) ((rs_cpu_sys_dmac_dma_comp_params_ch6*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH5                                 (HV_DMAC_BASE_ADDRESS + 0x3D4)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH5_struct                          rs_cpu_sys_dmac_dma_comp_params_ch5

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch5  rs_cpu_sys_dmac_dma_comp_params_ch5;
struct _rs_cpu_sys_dmac_dma_comp_params_ch5 {
    unsigned int CH5_DTW                                    : 3;
    unsigned int CH5_STW                                    : 3;
    unsigned int CH5_STAT_DST                               : 1;
    unsigned int CH5_STAT_SRC                               : 1;
    unsigned int CH5_DST_SCA_EN                             : 1;
    unsigned int CH5_SRC_GAT_EN                             : 1;
    unsigned int CH5_LOCK_EN                                : 1;
    unsigned int CH5_MULTI_BLK_EN                           : 1;
    unsigned int CH5_CTL_WB_EN                              : 1;
    unsigned int CH5_HC_LLP                                 : 1;
    unsigned int CH5_FC                                     : 2;
    unsigned int CH5_MAX_MULT_SIZE                          : 3;
    unsigned int CH5_DMS                                    : 3;
    unsigned int CH5_LMS                                    : 3;
    unsigned int CH5_SMS                                    : 3;
    unsigned int CH5_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch5(val) ((rs_cpu_sys_dmac_dma_comp_params_ch5*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH4                                 (HV_DMAC_BASE_ADDRESS + 0x3D8)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH4_struct                          rs_cpu_sys_dmac_dma_comp_params_ch4

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch4  rs_cpu_sys_dmac_dma_comp_params_ch4;
struct _rs_cpu_sys_dmac_dma_comp_params_ch4 {
    unsigned int CH4_DTW                                    : 3;
    unsigned int CH4_STW                                    : 3;
    unsigned int CH4_STAT_DST                               : 1;
    unsigned int CH4_STAT_SRC                               : 1;
    unsigned int CH4_DST_SCA_EN                             : 1;
    unsigned int CH4_SRC_GAT_EN                             : 1;
    unsigned int CH4_LOCK_EN                                : 1;
    unsigned int CH4_MULTI_BLK_EN                           : 1;
    unsigned int CH4_CTL_WB_EN                              : 1;
    unsigned int CH4_HC_LLP                                 : 1;
    unsigned int CH4_FC                                     : 2;
    unsigned int CH4_MAX_MULT_SIZE                          : 3;
    unsigned int CH4_DMS                                    : 3;
    unsigned int CH4_LMS                                    : 3;
    unsigned int CH4_SMS                                    : 3;
    unsigned int CH4_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch4(val) ((rs_cpu_sys_dmac_dma_comp_params_ch4*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH3                                 (HV_DMAC_BASE_ADDRESS + 0x3DC)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH3_struct                          rs_cpu_sys_dmac_dma_comp_params_ch3

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch3  rs_cpu_sys_dmac_dma_comp_params_ch3;
struct _rs_cpu_sys_dmac_dma_comp_params_ch3 {
    unsigned int CH3_DTW                                    : 3;
    unsigned int CH3_STW                                    : 3;
    unsigned int CH3_STAT_DST                               : 1;
    unsigned int CH3_STAT_SRC                               : 1;
    unsigned int CH3_DST_SCA_EN                             : 1;
    unsigned int CH3_SRC_GAT_EN                             : 1;
    unsigned int CH3_LOCK_EN                                : 1;
    unsigned int CH3_MULTI_BLK_EN                           : 1;
    unsigned int CH3_CTL_WB_EN                              : 1;
    unsigned int CH3_HC_LLP                                 : 1;
    unsigned int CH3_FC                                     : 2;
    unsigned int CH3_MAX_MULT_SIZE                          : 3;
    unsigned int CH3_DMS                                    : 3;
    unsigned int CH3_LMS                                    : 3;
    unsigned int CH3_SMS                                    : 3;
    unsigned int CH3_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch3(val) ((rs_cpu_sys_dmac_dma_comp_params_ch3*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH2                                 (HV_DMAC_BASE_ADDRESS + 0x3E0)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH2_struct                          rs_cpu_sys_dmac_dma_comp_params_ch2

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch2  rs_cpu_sys_dmac_dma_comp_params_ch2;
struct _rs_cpu_sys_dmac_dma_comp_params_ch2 {
    unsigned int CH2_DTW                                    : 3;
    unsigned int CH2_STW                                    : 3;
    unsigned int CH2_STAT_DST                               : 1;
    unsigned int CH2_STAT_SRC                               : 1;
    unsigned int CH2_DST_SCA_EN                             : 1;
    unsigned int CH2_SRC_GAT_EN                             : 1;
    unsigned int CH2_LOCK_EN                                : 1;
    unsigned int CH2_MULTI_BLK_EN                           : 1;
    unsigned int CH2_CTL_WB_EN                              : 1;
    unsigned int CH2_HC_LLP                                 : 1;
    unsigned int CH2_FC                                     : 2;
    unsigned int CH2_MAX_MULT_SIZE                          : 3;
    unsigned int CH2_DMS                                    : 3;
    unsigned int CH2_LMS                                    : 3;
    unsigned int CH2_SMS                                    : 3;
    unsigned int CH2_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch2(val) ((rs_cpu_sys_dmac_dma_comp_params_ch2*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH1                                 (HV_DMAC_BASE_ADDRESS + 0x3E4)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH1_struct                          rs_cpu_sys_dmac_dma_comp_params_ch1

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch1  rs_cpu_sys_dmac_dma_comp_params_ch1;
struct _rs_cpu_sys_dmac_dma_comp_params_ch1 {
    unsigned int CH1_DTW                                    : 3;
    unsigned int CH1_STW                                    : 3;
    unsigned int CH1_STAT_DST                               : 1;
    unsigned int CH1_STAT_SRC                               : 1;
    unsigned int CH1_DST_SCA_EN                             : 1;
    unsigned int CH1_SRC_GAT_EN                             : 1;
    unsigned int CH1_LOCK_EN                                : 1;
    unsigned int CH1_MULTI_BLK_EN                           : 1;
    unsigned int CH1_CTL_WB_EN                              : 1;
    unsigned int CH1_HC_LLP                                 : 1;
    unsigned int CH1_FC                                     : 2;
    unsigned int CH1_MAX_MULT_SIZE                          : 3;
    unsigned int CH1_DMS                                    : 3;
    unsigned int CH1_LMS                                    : 3;
    unsigned int CH1_SMS                                    : 3;
    unsigned int CH1_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch1(val) ((rs_cpu_sys_dmac_dma_comp_params_ch1*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH0                                 (HV_DMAC_BASE_ADDRESS + 0x3E8)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_CH0_struct                          rs_cpu_sys_dmac_dma_comp_params_ch0

typedef struct _rs_cpu_sys_dmac_dma_comp_params_ch0  rs_cpu_sys_dmac_dma_comp_params_ch0;
struct _rs_cpu_sys_dmac_dma_comp_params_ch0 {
    unsigned int CH0_DTW                                    : 3;
    unsigned int CH0_STW                                    : 3;
    unsigned int CH0_STAT_DST                               : 1;
    unsigned int CH0_STAT_SRC                               : 1;
    unsigned int CH0_DST_SCA_EN                             : 1;
    unsigned int CH0_SRC_GAT_EN                             : 1;
    unsigned int CH0_LOCK_EN                                : 1;
    unsigned int CH0_MULTI_BLK_EN                           : 1;
    unsigned int CH0_CTL_WB_EN                              : 1;
    unsigned int CH0_HC_LLP                                 : 1;
    unsigned int CH0_FC                                     : 2;
    unsigned int CH0_MAX_MULT_SIZE                          : 3;
    unsigned int CH0_DMS                                    : 3;
    unsigned int CH0_LMS                                    : 3;
    unsigned int CH0_SMS                                    : 3;
    unsigned int CH0_FIFO_DEPTH                             : 3;
    unsigned int reserved                                   : 1;
};
#define cpu_sys_dmac_dma_comp_params_ch0(val) ((rs_cpu_sys_dmac_dma_comp_params_ch0*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_BLK_TYPE                            (HV_DMAC_BASE_ADDRESS + 0x3EC)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_BLK_TYPE_struct                     rs_cpu_sys_dmac_dma_comp_params_blk_type

typedef struct _rs_cpu_sys_dmac_dma_comp_params_blk_type  rs_cpu_sys_dmac_dma_comp_params_blk_type;
struct _rs_cpu_sys_dmac_dma_comp_params_blk_type {
    unsigned int CH0_MULTI_BLK_TYPE                         : 4;
    unsigned int CH1_MULTI_BLK_TYPE                         : 4;
    unsigned int CH2_MULTI_BLK_TYPE                         : 4;
    unsigned int CH3_MULTI_BLK_TYPE                         : 4;
    unsigned int CH4_MULTI_BLK_TYPE                         : 4;
    unsigned int CH5_MULTI_BLK_TYPE                         : 4;
    unsigned int CH6_MULTI_BLK_TYPE                         : 4;
    unsigned int CH7_MULTI_BLK_TYPE                         : 4;
};
#define cpu_sys_dmac_dma_comp_params_blk_type(val) ((rs_cpu_sys_dmac_dma_comp_params_blk_type*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS_BLK_SIZE                            (HV_DMAC_BASE_ADDRESS + 0x3F0)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_BLK_SIZE_struct                     rs_cpu_sys_dmac_dma_comp_params_blk_size

typedef struct _rs_cpu_sys_dmac_dma_comp_params_blk_size  rs_cpu_sys_dmac_dma_comp_params_blk_size;
struct _rs_cpu_sys_dmac_dma_comp_params_blk_size {
    unsigned int CH0_MAX_BLK_SIZE                           : 4;
    unsigned int CH1_MAX_BLK_SIZE                           : 4;
    unsigned int CH2_MAX_BLK_SIZE                           : 4;
    unsigned int CH3_MAX_BLK_SIZE                           : 4;
    unsigned int CH4_MAX_BLK_SIZE                           : 4;
    unsigned int CH5_MAX_BLK_SIZE                           : 4;
    unsigned int CH6_MAX_BLK_SIZE                           : 4;
    unsigned int CH7_MAX_BLK_SIZE                           : 4;
};
#define cpu_sys_dmac_dma_comp_params_blk_size(val) ((rs_cpu_sys_dmac_dma_comp_params_blk_size*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_PARAMS                                     (HV_DMAC_BASE_ADDRESS + 0x3F4)

#define CPU_SYS_DMAC_DMA_COMP_PARAMS_struct                              rs_cpu_sys_dmac_dma_comp_params

typedef struct _rs_cpu_sys_dmac_dma_comp_params  rs_cpu_sys_dmac_dma_comp_params;
struct _rs_cpu_sys_dmac_dma_comp_params {
    unsigned int REG_ENDIAN                                 : 1;
    unsigned int INTR_IO                                    : 2;
    unsigned int MAX_ABRST                                  : 1;
    unsigned int reserved                                   : 4;
    unsigned int NUM_CHANNELS                               : 3;
    unsigned int NUM_MASTER_INT                             : 2;
    unsigned int S_HDATA_WIDTH                              : 2;
    unsigned int M4_HDATA_WIDTH                             : 2;
    unsigned int M3_HDATA_WIDTH                             : 2;
    unsigned int M2_HDATA_WIDTH                             : 2;
    unsigned int M1_HDATA_WIDTH                             : 2;
    unsigned int NUM_HS_INT                                 : 5;
    unsigned int ADD_ENCODED_PARAMS                         : 1;
    unsigned int STATIC_ENDIAN_SELECT                       : 1;
    unsigned int reserved_1                                 : 2;
};
#define cpu_sys_dmac_dma_comp_params(val) ((rs_cpu_sys_dmac_dma_comp_params*)&(val))



#define CPU_SYS_DMACOMPSID                                               (HV_DMAC_BASE_ADDRESS + 0x3F8)

#define CPU_SYS_DMACOMPSID_struct                                        rs_cpu_sys_dmacompsid

typedef struct _rs_cpu_sys_dmacompsid  rs_cpu_sys_dmacompsid;
struct _rs_cpu_sys_dmacompsid {
    unsigned int DMA_COMP_TYPE                              :32;
};
#define cpu_sys_dmacompsid(val) ((rs_cpu_sys_dmacompsid*)&(val))



#define CPU_SYS_DMAC_DMA_COMP_VERSION                                    (HV_DMAC_BASE_ADDRESS + 0x3FC)

#define CPU_SYS_DMAC_DMA_COMP_VERSION_struct                             rs_cpu_sys_dmac_dma_comp_version

typedef struct _rs_cpu_sys_dmac_dma_comp_version  rs_cpu_sys_dmac_dma_comp_version;
struct _rs_cpu_sys_dmac_dma_comp_version {
    unsigned int DMA_COMP_VERSION                           :32;
};
#define cpu_sys_dmac_dma_comp_version(val) ((rs_cpu_sys_dmac_dma_comp_version*)&(val))



#endif