#ifndef _HV_PAGE_HT7315_LDG_HDR_REG_01_H_
#define _HV_PAGE_HT7315_LDG_HDR_REG_01_H_

#ifndef HV_LDG_HDR_REG_01_BASE_ADDRESS
    #define HV_LDG_HDR_REG_01_BASE_ADDRESS                                         0x11022200
#endif


#define DISP_TOP_LDG_HDR_REG_01_00                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x00)

#define DISP_TOP_LDG_HDR_REG_01_00_struct                                rs_disp_top_ldg_hdr_reg_01_00

typedef struct _rs_disp_top_ldg_hdr_reg_01_00  rs_disp_top_ldg_hdr_reg_01_00;
struct _rs_disp_top_ldg_hdr_reg_01_00 {
    unsigned int reg_01_ct_ldg_hdr_passthrough              : 1;
    unsigned int reg_01_clk_en                              : 1;
    unsigned int reg_01_engine_en                           : 1;
    unsigned int reg_01_de_mode_en                          : 1;
    unsigned int reg_01_ct_en_gmi_enable                    : 1;
    unsigned int reg_01_en                                  : 1;
    unsigned int reg_01_no_latch                            : 1;
    unsigned int reserved                                   :25;
};
#define disp_top_ldg_hdr_reg_01_00(val) ((rs_disp_top_ldg_hdr_reg_01_00*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_04                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x04)

#define DISP_TOP_LDG_HDR_REG_01_04_struct                                rs_disp_top_ldg_hdr_reg_01_04

typedef struct _rs_disp_top_ldg_hdr_reg_01_04  rs_disp_top_ldg_hdr_reg_01_04;
struct _rs_disp_top_ldg_hdr_reg_01_04 {
    unsigned int reg_01_ct_en_ootf_enable                   : 1;
    unsigned int reserved                                   :31;
};
#define disp_top_ldg_hdr_reg_01_04(val) ((rs_disp_top_ldg_hdr_reg_01_04*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_08                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x08)

#define DISP_TOP_LDG_HDR_REG_01_08_struct                                rs_disp_top_ldg_hdr_reg_01_08

typedef struct _rs_disp_top_ldg_hdr_reg_01_08  rs_disp_top_ldg_hdr_reg_01_08;
struct _rs_disp_top_ldg_hdr_reg_01_08 {
    unsigned int reg_01_ct_en_ootf_y_r                      :16;
    unsigned int reserved                                   :16;
};
#define disp_top_ldg_hdr_reg_01_08(val) ((rs_disp_top_ldg_hdr_reg_01_08*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_0C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x0C)

#define DISP_TOP_LDG_HDR_REG_01_0C_struct                                rs_disp_top_ldg_hdr_reg_01_0c

typedef struct _rs_disp_top_ldg_hdr_reg_01_0c  rs_disp_top_ldg_hdr_reg_01_0c;
struct _rs_disp_top_ldg_hdr_reg_01_0c {
    unsigned int reg_01_ct_en_ootf_y_g                      :16;
    unsigned int reserved                                   :16;
};
#define disp_top_ldg_hdr_reg_01_0c(val) ((rs_disp_top_ldg_hdr_reg_01_0c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_10                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x10)

#define DISP_TOP_LDG_HDR_REG_01_10_struct                                rs_disp_top_ldg_hdr_reg_01_10

typedef struct _rs_disp_top_ldg_hdr_reg_01_10  rs_disp_top_ldg_hdr_reg_01_10;
struct _rs_disp_top_ldg_hdr_reg_01_10 {
    unsigned int reg_01_ct_en_ootf_y_b                      :16;
    unsigned int reserved                                   :16;
};
#define disp_top_ldg_hdr_reg_01_10(val) ((rs_disp_top_ldg_hdr_reg_01_10*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_14                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x14)

#define DISP_TOP_LDG_HDR_REG_01_14_struct                                rs_disp_top_ldg_hdr_reg_01_14

typedef struct _rs_disp_top_ldg_hdr_reg_01_14  rs_disp_top_ldg_hdr_reg_01_14;
struct _rs_disp_top_ldg_hdr_reg_01_14 {
    unsigned int reg_01_ct_en_gmd_enable                    : 1;
    unsigned int reserved                                   :31;
};
#define disp_top_ldg_hdr_reg_01_14(val) ((rs_disp_top_ldg_hdr_reg_01_14*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_18                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x18)

#define DISP_TOP_LDG_HDR_REG_01_18_struct                                rs_disp_top_ldg_hdr_reg_01_18

typedef struct _rs_disp_top_ldg_hdr_reg_01_18  rs_disp_top_ldg_hdr_reg_01_18;
struct _rs_disp_top_ldg_hdr_reg_01_18 {
    unsigned int reg_01_ct_en_gmd_sample2                   : 4;
    unsigned int reg_01_ct_en_gmd_sample1                   : 4;
    unsigned int reg_01_ct_en_gmd_sample0                   : 4;
    unsigned int reserved                                   :20;
};
#define disp_top_ldg_hdr_reg_01_18(val) ((rs_disp_top_ldg_hdr_reg_01_18*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_1C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x1C)

#define DISP_TOP_LDG_HDR_REG_01_1C_struct                                rs_disp_top_ldg_hdr_reg_01_1c

typedef struct _rs_disp_top_ldg_hdr_reg_01_1c  rs_disp_top_ldg_hdr_reg_01_1c;
struct _rs_disp_top_ldg_hdr_reg_01_1c {
    unsigned int reg_01_ct_en_demo_side                     : 1;
    unsigned int reserved                                   :11;
    unsigned int reg_01_ct_en_gmd_demo_en                   : 1;
    unsigned int reg_01_ct_en_ootf_demo_en                  : 1;
    unsigned int reg_01_ct_en_gmi_demo_en                   : 1;
    unsigned int reg_01_ct_en_pb_o_hsz                      :13;
    unsigned int reserved_1                                 : 4;
};
#define disp_top_ldg_hdr_reg_01_1c(val) ((rs_disp_top_ldg_hdr_reg_01_1c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_20                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x20)

#define DISP_TOP_LDG_HDR_REG_01_20_struct                                rs_disp_top_ldg_hdr_reg_01_20

typedef struct _rs_disp_top_ldg_hdr_reg_01_20  rs_disp_top_ldg_hdr_reg_01_20;
struct _rs_disp_top_ldg_hdr_reg_01_20 {
    unsigned int reg_01_lut_hdr_gmi                         : 9;
    unsigned int reserved                                   : 7;
    unsigned int reg_01_lut_hdr_ootf                        : 2;
    unsigned int reserved_1                                 :14;
};
#define disp_top_ldg_hdr_reg_01_20(val) ((rs_disp_top_ldg_hdr_reg_01_20*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_24                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x24)

#define DISP_TOP_LDG_HDR_REG_01_24_struct                                rs_disp_top_ldg_hdr_reg_01_24

typedef struct _rs_disp_top_ldg_hdr_reg_01_24  rs_disp_top_ldg_hdr_reg_01_24;
struct _rs_disp_top_ldg_hdr_reg_01_24 {
    unsigned int reg_01_lut_hdr_gmd                         :27;
    unsigned int reserved                                   : 5;
};
#define disp_top_ldg_hdr_reg_01_24(val) ((rs_disp_top_ldg_hdr_reg_01_24*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_28                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x28)

#define DISP_TOP_LDG_HDR_REG_01_28_struct                                rs_disp_top_ldg_hdr_reg_01_28

typedef struct _rs_disp_top_ldg_hdr_reg_01_28  rs_disp_top_ldg_hdr_reg_01_28;
struct _rs_disp_top_ldg_hdr_reg_01_28 {
    unsigned int reg_01_hdr_act_hsize                       :13;
    unsigned int reg_01_hdr_act_vsize                       :13;
    unsigned int reserved                                   : 6;
};
#define disp_top_ldg_hdr_reg_01_28(val) ((rs_disp_top_ldg_hdr_reg_01_28*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_2C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x2C)

#define DISP_TOP_LDG_HDR_REG_01_2C_struct                                rs_disp_top_ldg_hdr_reg_01_2c

typedef struct _rs_disp_top_ldg_hdr_reg_01_2c  rs_disp_top_ldg_hdr_reg_01_2c;
struct _rs_disp_top_ldg_hdr_reg_01_2c {
    unsigned int reg_01_hdr_gmi_smple_en                    : 1;
    unsigned int reg_01_hdr_ootf_smple_en                   : 1;
    unsigned int reg_01_hdr_csc2_smple_en                   : 1;
    unsigned int reserved                                   :29;
};
#define disp_top_ldg_hdr_reg_01_2c(val) ((rs_disp_top_ldg_hdr_reg_01_2c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_30                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x30)

#define DISP_TOP_LDG_HDR_REG_01_30_struct                                rs_disp_top_ldg_hdr_reg_01_30

typedef struct _rs_disp_top_ldg_hdr_reg_01_30  rs_disp_top_ldg_hdr_reg_01_30;
struct _rs_disp_top_ldg_hdr_reg_01_30 {
    unsigned int reg_01_ct_pixsmpl_x                        :13;
    unsigned int reg_01_ct_pixsmpl_y                        :13;
    unsigned int reg_01_ct_pixsmpl_disp                     : 3;
    unsigned int reserved                                   : 3;
};
#define disp_top_ldg_hdr_reg_01_30(val) ((rs_disp_top_ldg_hdr_reg_01_30*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_34                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x34)

#define DISP_TOP_LDG_HDR_REG_01_34_struct                                rs_disp_top_ldg_hdr_reg_01_34

typedef struct _rs_disp_top_ldg_hdr_reg_01_34  rs_disp_top_ldg_hdr_reg_01_34;
struct _rs_disp_top_ldg_hdr_reg_01_34 {
    unsigned int reg_01_ct_pixsmpl_rdata                    :32;
};
#define disp_top_ldg_hdr_reg_01_34(val) ((rs_disp_top_ldg_hdr_reg_01_34*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_38                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x38)

#define DISP_TOP_LDG_HDR_REG_01_38_struct                                rs_disp_top_ldg_hdr_reg_01_38

typedef struct _rs_disp_top_ldg_hdr_reg_01_38  rs_disp_top_ldg_hdr_reg_01_38;
struct _rs_disp_top_ldg_hdr_reg_01_38 {
    unsigned int reg_01_ct_pixsmpl_gdata                    :32;
};
#define disp_top_ldg_hdr_reg_01_38(val) ((rs_disp_top_ldg_hdr_reg_01_38*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_3C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x3C)

#define DISP_TOP_LDG_HDR_REG_01_3C_struct                                rs_disp_top_ldg_hdr_reg_01_3c

typedef struct _rs_disp_top_ldg_hdr_reg_01_3c  rs_disp_top_ldg_hdr_reg_01_3c;
struct _rs_disp_top_ldg_hdr_reg_01_3c {
    unsigned int reg_01_ct_pixsmpl_bdata                    :32;
};
#define disp_top_ldg_hdr_reg_01_3c(val) ((rs_disp_top_ldg_hdr_reg_01_3c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_40                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x40)

#define DISP_TOP_LDG_HDR_REG_01_40_struct                                rs_disp_top_ldg_hdr_reg_01_40

typedef struct _rs_disp_top_ldg_hdr_reg_01_40  rs_disp_top_ldg_hdr_reg_01_40;
struct _rs_disp_top_ldg_hdr_reg_01_40 {
    unsigned int reg_01_ct_pixsmpl_gd_rdata                 :14;
    unsigned int reg_01_ct_pixsmpl_gd_gdata                 :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_ldg_hdr_reg_01_40(val) ((rs_disp_top_ldg_hdr_reg_01_40*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_44                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x44)

#define DISP_TOP_LDG_HDR_REG_01_44_struct                                rs_disp_top_ldg_hdr_reg_01_44

typedef struct _rs_disp_top_ldg_hdr_reg_01_44  rs_disp_top_ldg_hdr_reg_01_44;
struct _rs_disp_top_ldg_hdr_reg_01_44 {
    unsigned int reg_01_ct_pixsmpl_gd_bdata                 :14;
    unsigned int reserved                                   :18;
};
#define disp_top_ldg_hdr_reg_01_44(val) ((rs_disp_top_ldg_hdr_reg_01_44*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_48                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x48)

#define DISP_TOP_LDG_HDR_REG_01_48_struct                                rs_disp_top_ldg_hdr_reg_01_48

typedef struct _rs_disp_top_ldg_hdr_reg_01_48  rs_disp_top_ldg_hdr_reg_01_48;
struct _rs_disp_top_ldg_hdr_reg_01_48 {
    unsigned int reg_01_ldg_hdr_gmi_pattern_en              : 1;
    unsigned int reg_01_ldg_hdr_ootf_pattern_en             : 1;
    unsigned int reg_01_ldg_hdr_gmd_pattern_en              : 1;
    unsigned int reg_01_ldg_hdr_csc2_pattern_en             : 1;
    unsigned int reserved                                   :28;
};
#define disp_top_ldg_hdr_reg_01_48(val) ((rs_disp_top_ldg_hdr_reg_01_48*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_4C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x4C)

#define DISP_TOP_LDG_HDR_REG_01_4C_struct                                rs_disp_top_ldg_hdr_reg_01_4c

typedef struct _rs_disp_top_ldg_hdr_reg_01_4c  rs_disp_top_ldg_hdr_reg_01_4c;
struct _rs_disp_top_ldg_hdr_reg_01_4c {
    unsigned int reg_01_ldg_hdr_pattern_rdata               :32;
};
#define disp_top_ldg_hdr_reg_01_4c(val) ((rs_disp_top_ldg_hdr_reg_01_4c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_50                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x50)

#define DISP_TOP_LDG_HDR_REG_01_50_struct                                rs_disp_top_ldg_hdr_reg_01_50

typedef struct _rs_disp_top_ldg_hdr_reg_01_50  rs_disp_top_ldg_hdr_reg_01_50;
struct _rs_disp_top_ldg_hdr_reg_01_50 {
    unsigned int reg_01_ldg_hdr_pattern_gdata               :32;
};
#define disp_top_ldg_hdr_reg_01_50(val) ((rs_disp_top_ldg_hdr_reg_01_50*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_54                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x54)

#define DISP_TOP_LDG_HDR_REG_01_54_struct                                rs_disp_top_ldg_hdr_reg_01_54

typedef struct _rs_disp_top_ldg_hdr_reg_01_54  rs_disp_top_ldg_hdr_reg_01_54;
struct _rs_disp_top_ldg_hdr_reg_01_54 {
    unsigned int reg_01_ldg_hdr_pattern_bdata               :32;
};
#define disp_top_ldg_hdr_reg_01_54(val) ((rs_disp_top_ldg_hdr_reg_01_54*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_58                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x58)

#define DISP_TOP_LDG_HDR_REG_01_58_struct                                rs_disp_top_ldg_hdr_reg_01_58

typedef struct _rs_disp_top_ldg_hdr_reg_01_58  rs_disp_top_ldg_hdr_reg_01_58;
struct _rs_disp_top_ldg_hdr_reg_01_58 {
    unsigned int reg_01_lut_hdr_gmi_en                      : 1;
    unsigned int reg_01_lut_hdr_ootf_en                     : 1;
    unsigned int reg_01_lut_hdr_gmd_en                      : 1;
    unsigned int reserved                                   :29;
};
#define disp_top_ldg_hdr_reg_01_58(val) ((rs_disp_top_ldg_hdr_reg_01_58*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_5C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x5C)

#define DISP_TOP_LDG_HDR_REG_01_5C_struct                                rs_disp_top_ldg_hdr_reg_01_5c

typedef struct _rs_disp_top_ldg_hdr_reg_01_5c  rs_disp_top_ldg_hdr_reg_01_5c;
struct _rs_disp_top_ldg_hdr_reg_01_5c {
    unsigned int reg_01_debug_en                            : 1;
    unsigned int reg_01_debug_mode                          : 1;
    unsigned int reserved                                   :14;
    unsigned int reg_01_debug_addr                          : 9;
    unsigned int reserved_1                                 : 7;
};
#define disp_top_ldg_hdr_reg_01_5c(val) ((rs_disp_top_ldg_hdr_reg_01_5c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_60                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x60)

#define DISP_TOP_LDG_HDR_REG_01_60_struct                                rs_disp_top_ldg_hdr_reg_01_60

typedef struct _rs_disp_top_ldg_hdr_reg_01_60  rs_disp_top_ldg_hdr_reg_01_60;
struct _rs_disp_top_ldg_hdr_reg_01_60 {
    unsigned int reg_01_debug_wdata                         :32;
};
#define disp_top_ldg_hdr_reg_01_60(val) ((rs_disp_top_ldg_hdr_reg_01_60*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_64                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x64)

#define DISP_TOP_LDG_HDR_REG_01_64_struct                                rs_disp_top_ldg_hdr_reg_01_64

typedef struct _rs_disp_top_ldg_hdr_reg_01_64  rs_disp_top_ldg_hdr_reg_01_64;
struct _rs_disp_top_ldg_hdr_reg_01_64 {
    unsigned int reg_01_debug_rdata                         :32;
};
#define disp_top_ldg_hdr_reg_01_64(val) ((rs_disp_top_ldg_hdr_reg_01_64*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_68                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x68)

#define DISP_TOP_LDG_HDR_REG_01_68_struct                                rs_disp_top_ldg_hdr_reg_01_68

typedef struct _rs_disp_top_ldg_hdr_reg_01_68  rs_disp_top_ldg_hdr_reg_01_68;
struct _rs_disp_top_ldg_hdr_reg_01_68 {
    unsigned int reg_01_tbl_id_gmi                          : 4;
    unsigned int reg_01_tbl_id_ootf                         : 4;
    unsigned int reg_01_tbl_id_gmd                          : 4;
    unsigned int reg_01_no_latch_id                         : 1;
    unsigned int reserved                                   :19;
};
#define disp_top_ldg_hdr_reg_01_68(val) ((rs_disp_top_ldg_hdr_reg_01_68*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_6C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x6C)

#define DISP_TOP_LDG_HDR_REG_01_6C_struct                                rs_disp_top_ldg_hdr_reg_01_6c

typedef struct _rs_disp_top_ldg_hdr_reg_01_6c  rs_disp_top_ldg_hdr_reg_01_6c;
struct _rs_disp_top_ldg_hdr_reg_01_6c {
    unsigned int reg_01_mem_reg1                            : 8;
    unsigned int reg_01_mem_reg2                            : 8;
    unsigned int reg_01_mem_reg3                            : 8;
    unsigned int reg_01_mem_reg4                            : 8;
};
#define disp_top_ldg_hdr_reg_01_6c(val) ((rs_disp_top_ldg_hdr_reg_01_6c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_70                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x70)

#define DISP_TOP_LDG_HDR_REG_01_70_struct                                rs_disp_top_ldg_hdr_reg_01_70

typedef struct _rs_disp_top_ldg_hdr_reg_01_70  rs_disp_top_ldg_hdr_reg_01_70;
struct _rs_disp_top_ldg_hdr_reg_01_70 {
    unsigned int reg_01_mem_reg5                            : 8;
    unsigned int reg_01_mem_reg6                            : 8;
    unsigned int reg_01_mem_reg7                            : 8;
    unsigned int reg_01_mem_reg8                            : 8;
};
#define disp_top_ldg_hdr_reg_01_70(val) ((rs_disp_top_ldg_hdr_reg_01_70*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_74                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x74)

#define DISP_TOP_LDG_HDR_REG_01_74_struct                                rs_disp_top_ldg_hdr_reg_01_74

typedef struct _rs_disp_top_ldg_hdr_reg_01_74  rs_disp_top_ldg_hdr_reg_01_74;
struct _rs_disp_top_ldg_hdr_reg_01_74 {
    unsigned int reg_01_mem_reg9                            : 8;
    unsigned int reg_01_mem_reg10                           : 8;
    unsigned int reg_01_mem_reg11                           : 8;
    unsigned int reg_01_mem_reg12                           : 8;
};
#define disp_top_ldg_hdr_reg_01_74(val) ((rs_disp_top_ldg_hdr_reg_01_74*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_78                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x78)

#define DISP_TOP_LDG_HDR_REG_01_78_struct                                rs_disp_top_ldg_hdr_reg_01_78

typedef struct _rs_disp_top_ldg_hdr_reg_01_78  rs_disp_top_ldg_hdr_reg_01_78;
struct _rs_disp_top_ldg_hdr_reg_01_78 {
    unsigned int reg_01_mem_reg13                           : 8;
    unsigned int reg_01_mem_reg14                           : 8;
    unsigned int reg_01_mem_reg15                           : 8;
    unsigned int reg_01_mem_reg16                           : 8;
};
#define disp_top_ldg_hdr_reg_01_78(val) ((rs_disp_top_ldg_hdr_reg_01_78*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_7C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x7C)

#define DISP_TOP_LDG_HDR_REG_01_7C_struct                                rs_disp_top_ldg_hdr_reg_01_7c

typedef struct _rs_disp_top_ldg_hdr_reg_01_7c  rs_disp_top_ldg_hdr_reg_01_7c;
struct _rs_disp_top_ldg_hdr_reg_01_7c {
    unsigned int reg_01_mem_reg17                           : 8;
    unsigned int reg_01_mem_reg18                           : 8;
    unsigned int reg_01_mem_reg19                           : 8;
    unsigned int reg_01_mem_reg20                           : 8;
};
#define disp_top_ldg_hdr_reg_01_7c(val) ((rs_disp_top_ldg_hdr_reg_01_7c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_80                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x80)

#define DISP_TOP_LDG_HDR_REG_01_80_struct                                rs_disp_top_ldg_hdr_reg_01_80

typedef struct _rs_disp_top_ldg_hdr_reg_01_80  rs_disp_top_ldg_hdr_reg_01_80;
struct _rs_disp_top_ldg_hdr_reg_01_80 {
    unsigned int reg_01_mem_reg21                           : 8;
    unsigned int reg_01_mem_reg22                           : 8;
    unsigned int reg_01_mem_reg23                           : 8;
    unsigned int reg_01_mem_reg24                           : 8;
};
#define disp_top_ldg_hdr_reg_01_80(val) ((rs_disp_top_ldg_hdr_reg_01_80*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_84                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x84)

#define DISP_TOP_LDG_HDR_REG_01_84_struct                                rs_disp_top_ldg_hdr_reg_01_84

typedef struct _rs_disp_top_ldg_hdr_reg_01_84  rs_disp_top_ldg_hdr_reg_01_84;
struct _rs_disp_top_ldg_hdr_reg_01_84 {
    unsigned int reg_01_mem_reg25                           : 8;
    unsigned int reg_01_mem_reg26                           : 8;
    unsigned int reg_01_mem_reg27                           : 8;
    unsigned int reg_01_mem_reg28                           : 8;
};
#define disp_top_ldg_hdr_reg_01_84(val) ((rs_disp_top_ldg_hdr_reg_01_84*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_88                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x88)

#define DISP_TOP_LDG_HDR_REG_01_88_struct                                rs_disp_top_ldg_hdr_reg_01_88

typedef struct _rs_disp_top_ldg_hdr_reg_01_88  rs_disp_top_ldg_hdr_reg_01_88;
struct _rs_disp_top_ldg_hdr_reg_01_88 {
    unsigned int reg_01_mem_reg29                           : 8;
    unsigned int reg_01_mem_reg30                           : 8;
    unsigned int reg_01_mem_reg31                           : 8;
    unsigned int reg_01_mem_reg32                           : 8;
};
#define disp_top_ldg_hdr_reg_01_88(val) ((rs_disp_top_ldg_hdr_reg_01_88*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_8C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x8C)

#define DISP_TOP_LDG_HDR_REG_01_8C_struct                                rs_disp_top_ldg_hdr_reg_01_8c

typedef struct _rs_disp_top_ldg_hdr_reg_01_8c  rs_disp_top_ldg_hdr_reg_01_8c;
struct _rs_disp_top_ldg_hdr_reg_01_8c {
    unsigned int reg_01_mem_reg33                           : 8;
    unsigned int reg_01_mem_reg34                           : 8;
    unsigned int reg_01_mem_reg35                           : 8;
    unsigned int reg_01_mem_reg36                           : 8;
};
#define disp_top_ldg_hdr_reg_01_8c(val) ((rs_disp_top_ldg_hdr_reg_01_8c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_90                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x90)

#define DISP_TOP_LDG_HDR_REG_01_90_struct                                rs_disp_top_ldg_hdr_reg_01_90

typedef struct _rs_disp_top_ldg_hdr_reg_01_90  rs_disp_top_ldg_hdr_reg_01_90;
struct _rs_disp_top_ldg_hdr_reg_01_90 {
    unsigned int reg_01_mem_reg37                           : 8;
    unsigned int reg_01_mem_reg38                           : 8;
    unsigned int reserved                                   :16;
};
#define disp_top_ldg_hdr_reg_01_90(val) ((rs_disp_top_ldg_hdr_reg_01_90*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_94                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x94)

#define DISP_TOP_LDG_HDR_REG_01_94_struct                                rs_disp_top_ldg_hdr_reg_01_94

typedef struct _rs_disp_top_ldg_hdr_reg_01_94  rs_disp_top_ldg_hdr_reg_01_94;
struct _rs_disp_top_ldg_hdr_reg_01_94 {
    unsigned int reg_01_hdr_csc2_en                         : 1;
    unsigned int reg_01_hdr_csc2_mode                       : 3;
    unsigned int reserved                                   : 4;
    unsigned int reg_01_hdr_csc2_ofs_in_y                   :24;
};
#define disp_top_ldg_hdr_reg_01_94(val) ((rs_disp_top_ldg_hdr_reg_01_94*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_98                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x98)

#define DISP_TOP_LDG_HDR_REG_01_98_struct                                rs_disp_top_ldg_hdr_reg_01_98

typedef struct _rs_disp_top_ldg_hdr_reg_01_98  rs_disp_top_ldg_hdr_reg_01_98;
struct _rs_disp_top_ldg_hdr_reg_01_98 {
    unsigned int reg_01_hdr_csc2_ofs_in_u                   :24;
    unsigned int reserved                                   : 8;
};
#define disp_top_ldg_hdr_reg_01_98(val) ((rs_disp_top_ldg_hdr_reg_01_98*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_9C                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0x9C)

#define DISP_TOP_LDG_HDR_REG_01_9C_struct                                rs_disp_top_ldg_hdr_reg_01_9c

typedef struct _rs_disp_top_ldg_hdr_reg_01_9c  rs_disp_top_ldg_hdr_reg_01_9c;
struct _rs_disp_top_ldg_hdr_reg_01_9c {
    unsigned int reg_01_hdr_csc2_ofs_in_v                   :24;
    unsigned int reserved                                   : 8;
};
#define disp_top_ldg_hdr_reg_01_9c(val) ((rs_disp_top_ldg_hdr_reg_01_9c*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_A0                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xA0)

#define DISP_TOP_LDG_HDR_REG_01_A0_struct                                rs_disp_top_ldg_hdr_reg_01_a0

typedef struct _rs_disp_top_ldg_hdr_reg_01_a0  rs_disp_top_ldg_hdr_reg_01_a0;
struct _rs_disp_top_ldg_hdr_reg_01_a0 {
    unsigned int reg_01_hdr_csc2_y_r_coef                   :16;
    unsigned int reg_01_hdr_csc2_y_g_coef                   :16;
};
#define disp_top_ldg_hdr_reg_01_a0(val) ((rs_disp_top_ldg_hdr_reg_01_a0*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_A4                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xA4)

#define DISP_TOP_LDG_HDR_REG_01_A4_struct                                rs_disp_top_ldg_hdr_reg_01_a4

typedef struct _rs_disp_top_ldg_hdr_reg_01_a4  rs_disp_top_ldg_hdr_reg_01_a4;
struct _rs_disp_top_ldg_hdr_reg_01_a4 {
    unsigned int reg_01_hdr_csc2_y_b_coef                   :16;
    unsigned int reg_01_hdr_csc2_u_r_coef                   :16;
};
#define disp_top_ldg_hdr_reg_01_a4(val) ((rs_disp_top_ldg_hdr_reg_01_a4*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_A8                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xA8)

#define DISP_TOP_LDG_HDR_REG_01_A8_struct                                rs_disp_top_ldg_hdr_reg_01_a8

typedef struct _rs_disp_top_ldg_hdr_reg_01_a8  rs_disp_top_ldg_hdr_reg_01_a8;
struct _rs_disp_top_ldg_hdr_reg_01_a8 {
    unsigned int reg_01_hdr_csc2_u_g_coef                   :16;
    unsigned int reg_01_hdr_csc2_u_b_coef                   :16;
};
#define disp_top_ldg_hdr_reg_01_a8(val) ((rs_disp_top_ldg_hdr_reg_01_a8*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_AC                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xAC)

#define DISP_TOP_LDG_HDR_REG_01_AC_struct                                rs_disp_top_ldg_hdr_reg_01_ac

typedef struct _rs_disp_top_ldg_hdr_reg_01_ac  rs_disp_top_ldg_hdr_reg_01_ac;
struct _rs_disp_top_ldg_hdr_reg_01_ac {
    unsigned int reg_01_hdr_csc2_v_r_coef                   :16;
    unsigned int reg_01_hdr_csc2_v_g_coef                   :16;
};
#define disp_top_ldg_hdr_reg_01_ac(val) ((rs_disp_top_ldg_hdr_reg_01_ac*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_B0                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xB0)

#define DISP_TOP_LDG_HDR_REG_01_B0_struct                                rs_disp_top_ldg_hdr_reg_01_b0

typedef struct _rs_disp_top_ldg_hdr_reg_01_b0  rs_disp_top_ldg_hdr_reg_01_b0;
struct _rs_disp_top_ldg_hdr_reg_01_b0 {
    unsigned int reg_01_hdr_csc2_v_b_coef                   :16;
    unsigned int reserved                                   :16;
};
#define disp_top_ldg_hdr_reg_01_b0(val) ((rs_disp_top_ldg_hdr_reg_01_b0*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_B4                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xB4)

#define DISP_TOP_LDG_HDR_REG_01_B4_struct                                rs_disp_top_ldg_hdr_reg_01_b4

typedef struct _rs_disp_top_ldg_hdr_reg_01_b4  rs_disp_top_ldg_hdr_reg_01_b4;
struct _rs_disp_top_ldg_hdr_reg_01_b4 {
    unsigned int reg_01_hdr_csc2_ofs_out_r                  :24;
    unsigned int reserved                                   : 8;
};
#define disp_top_ldg_hdr_reg_01_b4(val) ((rs_disp_top_ldg_hdr_reg_01_b4*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_B8                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xB8)

#define DISP_TOP_LDG_HDR_REG_01_B8_struct                                rs_disp_top_ldg_hdr_reg_01_b8

typedef struct _rs_disp_top_ldg_hdr_reg_01_b8  rs_disp_top_ldg_hdr_reg_01_b8;
struct _rs_disp_top_ldg_hdr_reg_01_b8 {
    unsigned int reg_01_hdr_csc2_ofs_out_g                  :24;
    unsigned int reserved                                   : 8;
};
#define disp_top_ldg_hdr_reg_01_b8(val) ((rs_disp_top_ldg_hdr_reg_01_b8*)&(val))



#define DISP_TOP_LDG_HDR_REG_01_BC                                       (HV_LDG_HDR_REG_01_BASE_ADDRESS + 0xBC)

#define DISP_TOP_LDG_HDR_REG_01_BC_struct                                rs_disp_top_ldg_hdr_reg_01_bc

typedef struct _rs_disp_top_ldg_hdr_reg_01_bc  rs_disp_top_ldg_hdr_reg_01_bc;
struct _rs_disp_top_ldg_hdr_reg_01_bc {
    unsigned int reg_01_hdr_csc2_ofs_out_b                  :24;
    unsigned int reserved                                   : 8;
};
#define disp_top_ldg_hdr_reg_01_bc(val) ((rs_disp_top_ldg_hdr_reg_01_bc*)&(val))



#endif