#ifndef _HV_PAGE_HT7315_STANDBY_PERI_REG_H_
#define _HV_PAGE_HT7315_STANDBY_PERI_REG_H_

#ifndef HV_STANDBY_PERI_REG_BASE_ADDRESS
    #define HV_STANDBY_PERI_REG_BASE_ADDRESS                                         0x11008100
#endif


#define STANDBY_STANDBY_PERI_REG_STBY_AUX0                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x00)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX0_struct                        rs_standby_standby_peri_reg_stby_aux0

typedef struct _rs_standby_standby_peri_reg_stby_aux0  rs_standby_standby_peri_reg_stby_aux0;
struct _rs_standby_standby_peri_reg_stby_aux0 {
    unsigned int reg_dprx0_ana_aux_drv                      : 4;
    unsigned int reg_dprx0_ana_aux_eng                      : 8;
    unsigned int reg_dprx0_ana_aux_hys                      : 2;
    unsigned int reg_dprx0_ana_aux_ie                       : 1;
    unsigned int reg_dprx0_ana_aux_pn_swap                  : 1;
    unsigned int reg_dprx0_ana_aux_pwd                      : 1;
    unsigned int reg_dprx0_ana_aux_res                      : 4;
    unsigned int reg_dprx0_aux_from_pin                     : 2;
    unsigned int reserved                                   : 9;
};
#define standby_standby_peri_reg_stby_aux0(val) ((rs_standby_standby_peri_reg_stby_aux0*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX1                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x04)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX1_struct                        rs_standby_standby_peri_reg_stby_aux1

typedef struct _rs_standby_standby_peri_reg_stby_aux1  rs_standby_standby_peri_reg_stby_aux1;
struct _rs_standby_standby_peri_reg_stby_aux1 {
    unsigned int reg_dprx0_aux_actual_freq_th               : 4;
    unsigned int reg_dprx0_aux_corr_value_th                : 8;
    unsigned int reg_dprx0_aux_debug_clr_en                 : 1;
    unsigned int reg_dprx0_aux_en                           : 1;
    unsigned int reg_dprx0_aux_glitch_th                    : 6;
    unsigned int reg_dprx0_aux_half_1us_thd                 :10;
    unsigned int reg_dprx0_aux_phase_sync_bypass            : 1;
    unsigned int reserved                                   : 1;
};
#define standby_standby_peri_reg_stby_aux1(val) ((rs_standby_standby_peri_reg_stby_aux1*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX2                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x08)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX2_struct                        rs_standby_standby_peri_reg_stby_aux2

typedef struct _rs_standby_standby_peri_reg_stby_aux2  rs_standby_standby_peri_reg_stby_aux2;
struct _rs_standby_standby_peri_reg_stby_aux2 {
    unsigned int reg_dprx0_aux_phase_sync_mask              : 8;
    unsigned int reg_dprx0_aux_phase_sync_pat_sel           : 2;
    unsigned int reg_dprx0_aux_pre_amble_num                : 5;
    unsigned int reg_dprx0_aux_pre_charge_num               : 5;
    unsigned int reg_dprx0_aux_rdata_num_limit_en           : 1;
    unsigned int reg_dprx0_aux_rdback_clr_en                : 1;
    unsigned int reg_dprx0_aux_rx_inv                       : 1;
    unsigned int reg_dprx0_aux_slp_sel                      : 2;
    unsigned int reg_dprx0_aux_start_patt1_en               : 1;
    unsigned int reg_dprx0_aux_state_rst_en                 : 1;
    unsigned int reg_dprx0_aux_sw_sel                       : 2;
    unsigned int reg_dprx0_aux_time_out_clr_en              : 1;
    unsigned int reserved                                   : 2;
};
#define standby_standby_peri_reg_stby_aux2(val) ((rs_standby_standby_peri_reg_stby_aux2*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX3                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x0C)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX3_struct                        rs_standby_standby_peri_reg_stby_aux3

typedef struct _rs_standby_standby_peri_reg_stby_aux3  rs_standby_standby_peri_reg_stby_aux3;
struct _rs_standby_standby_peri_reg_stby_aux3 {
    unsigned int reg_dprx0_aux_timeout_th                   :16;
    unsigned int reg_dprx0_aux_tx_dly_thro                  :16;
};
#define standby_standby_peri_reg_stby_aux3(val) ((rs_standby_standby_peri_reg_stby_aux3*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX4                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x10)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX4_struct                        rs_standby_standby_peri_reg_stby_aux4

typedef struct _rs_standby_standby_peri_reg_stby_aux4  rs_standby_standby_peri_reg_stby_aux4;
struct _rs_standby_standby_peri_reg_stby_aux4 {
    unsigned int reg_dprx0_aux_tx_inv                       : 1;
    unsigned int reg_dprx0_aux_tx_phase_dly_en              : 1;
    unsigned int reg_dprx0_aux_tx_precharge_on              : 1;
    unsigned int reg_dprx0_aux_tx_wake_sel                  : 2;
    unsigned int reg_dprx0_aux_wake_addr                    :20;
    unsigned int reserved                                   : 7;
};
#define standby_standby_peri_reg_stby_aux4(val) ((rs_standby_standby_peri_reg_stby_aux4*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX5                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x14)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX5_struct                        rs_standby_standby_peri_reg_stby_aux5

typedef struct _rs_standby_standby_peri_reg_stby_aux5  rs_standby_standby_peri_reg_stby_aux5;
struct _rs_standby_standby_peri_reg_stby_aux5 {
    unsigned int reg_dprx0_aux_wake_sel                     :12;
    unsigned int reg_dprx0_aux_wake_wdata                   : 8;
    unsigned int reg_dprx0_aux_wake_wr                      : 1;
    unsigned int reg_dprx0_edid_addr0                       : 8;
    unsigned int reserved                                   : 3;
};
#define standby_standby_peri_reg_stby_aux5(val) ((rs_standby_standby_peri_reg_stby_aux5*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX6                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x18)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX6_struct                        rs_standby_standby_peri_reg_stby_aux6

typedef struct _rs_standby_standby_peri_reg_stby_aux6  rs_standby_standby_peri_reg_stby_aux6;
struct _rs_standby_standby_peri_reg_stby_aux6 {
    unsigned int reg_dprx0_edid_addr1                       : 8;
    unsigned int reg_dprx0_edid_seg_addr                    : 8;
    unsigned int reg_dprx0_aux_i2c_invalid_addr_en          : 1;
    unsigned int reserved                                   :15;
};
#define standby_standby_peri_reg_stby_aux6(val) ((rs_standby_standby_peri_reg_stby_aux6*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX7                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x1C)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX7_struct                        rs_standby_standby_peri_reg_stby_aux7

typedef struct _rs_standby_standby_peri_reg_stby_aux7  rs_standby_standby_peri_reg_stby_aux7;
struct _rs_standby_standby_peri_reg_stby_aux7 {
    unsigned int regr_dprx0_aux_addr                        :20;
    unsigned int regr_dprx0_aux_commd                       : 4;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_aux7(val) ((rs_standby_standby_peri_reg_stby_aux7*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX8                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x20)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX8_struct                        rs_standby_standby_peri_reg_stby_aux8

typedef struct _rs_standby_standby_peri_reg_stby_aux8  rs_standby_standby_peri_reg_stby_aux8;
struct _rs_standby_standby_peri_reg_stby_aux8 {
    unsigned int regr_dprx0_aux_dbg_cmd_cnt                 :16;
    unsigned int regr_dprx0_aux_freq_cnt                    :16;
};
#define standby_standby_peri_reg_stby_aux8(val) ((rs_standby_standby_peri_reg_stby_aux8*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX9                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x24)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX9_struct                        rs_standby_standby_peri_reg_stby_aux9

typedef struct _rs_standby_standby_peri_reg_stby_aux9  rs_standby_standby_peri_reg_stby_aux9;
struct _rs_standby_standby_peri_reg_stby_aux9 {
    unsigned int regr_dprx0_aux_len                         : 8;
    unsigned int regr_dprx0_aux_rx_time_out                 : 1;
    unsigned int regr_dprx0_aux_state                       : 4;
    unsigned int reserved                                   :19;
};
#define standby_standby_peri_reg_stby_aux9(val) ((rs_standby_standby_peri_reg_stby_aux9*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_AUX10                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x28)

#define STANDBY_STANDBY_PERI_REG_STBY_AUX10_struct                       rs_standby_standby_peri_reg_stby_aux10

typedef struct _rs_standby_standby_peri_reg_stby_aux10  rs_standby_standby_peri_reg_stby_aux10;
struct _rs_standby_standby_peri_reg_stby_aux10 {
    unsigned int regr_dprx0_aux_100_wdata                   : 8;
    unsigned int regr_dprx0_aux_101_wdata                   : 8;
    unsigned int reserved                                   :16;
};
#define standby_standby_peri_reg_stby_aux10(val) ((rs_standby_standby_peri_reg_stby_aux10*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_RX0                                (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x40)

#define STANDBY_STANDBY_PERI_REG_STBY_RX0_struct                         rs_standby_standby_peri_reg_stby_rx0

typedef struct _rs_standby_standby_peri_reg_stby_rx0  rs_standby_standby_peri_reg_stby_rx0;
struct _rs_standby_standby_peri_reg_stby_rx0 {
    unsigned int reg_rx_standby_0p9                         : 4;
    unsigned int reg_rx_ckdet_en_0p9                        : 4;
    unsigned int regr_rx_clk_flag_0p9                       : 4;
    unsigned int reg_rx_clk_mode                            : 4;
    unsigned int reserved                                   :16;
};
#define standby_standby_peri_reg_stby_rx0(val) ((rs_standby_standby_peri_reg_stby_rx0*)&(val))



#define STANDBY_STANDBY_PERI_REG_50                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x50)

#define STANDBY_STANDBY_PERI_REG_50_struct                               rs_standby_standby_peri_reg_50

typedef struct _rs_standby_standby_peri_reg_50  rs_standby_standby_peri_reg_50;
struct _rs_standby_standby_peri_reg_50 {
    unsigned int reg_dprx1_ana_aux_drv                      : 4;
    unsigned int reg_dprx1_ana_aux_eng                      : 8;
    unsigned int reg_dprx1_ana_aux_hys                      : 2;
    unsigned int reg_dprx1_ana_aux_ie                       : 1;
    unsigned int reg_dprx1_ana_aux_pn_swap                  : 1;
    unsigned int reg_dprx1_ana_aux_pwd                      : 1;
    unsigned int reg_dprx1_ana_aux_res                      : 4;
    unsigned int reg_dprx1_aux_from_pin                     : 2;
    unsigned int reserved                                   : 9;
};
#define standby_standby_peri_reg_50(val) ((rs_standby_standby_peri_reg_50*)&(val))



#define STANDBY_STANDBY_PERI_REG_54                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x54)

#define STANDBY_STANDBY_PERI_REG_54_struct                               rs_standby_standby_peri_reg_54

typedef struct _rs_standby_standby_peri_reg_54  rs_standby_standby_peri_reg_54;
struct _rs_standby_standby_peri_reg_54 {
    unsigned int reg_dprx1_aux_actual_freq_th               : 4;
    unsigned int reg_dprx1_aux_corr_value_th                : 8;
    unsigned int reg_dprx1_aux_debug_clr_en                 : 1;
    unsigned int reg_dprx1_aux_en                           : 1;
    unsigned int reg_dprx1_aux_glitch_th                    : 6;
    unsigned int reg_dprx1_aux_half_1us_thd                 :10;
    unsigned int reg_dprx1_aux_phase_sync_bypass            : 1;
    unsigned int reserved                                   : 1;
};
#define standby_standby_peri_reg_54(val) ((rs_standby_standby_peri_reg_54*)&(val))



#define STANDBY_STANDBY_PERI_REG_58                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x58)

#define STANDBY_STANDBY_PERI_REG_58_struct                               rs_standby_standby_peri_reg_58

typedef struct _rs_standby_standby_peri_reg_58  rs_standby_standby_peri_reg_58;
struct _rs_standby_standby_peri_reg_58 {
    unsigned int reg_dprx1_aux_phase_sync_mask              : 8;
    unsigned int reg_dprx1_aux_phase_sync_pat_sel           : 2;
    unsigned int reg_dprx1_aux_pre_amble_num                : 5;
    unsigned int reg_dprx1_aux_pre_charge_num               : 5;
    unsigned int reg_dprx1_aux_rdata_num_limit_en           : 1;
    unsigned int reg_dprx1_aux_rdback_clr_en                : 1;
    unsigned int reg_dprx1_aux_rx_inv                       : 1;
    unsigned int reg_dprx1_aux_slp_sel                      : 2;
    unsigned int reg_dprx1_aux_start_patt1_en               : 1;
    unsigned int reg_dprx1_aux_state_rst_en                 : 1;
    unsigned int reg_dprx1_aux_sw_sel                       : 2;
    unsigned int reg_dprx1_aux_time_out_clr_en              : 1;
    unsigned int reserved                                   : 2;
};
#define standby_standby_peri_reg_58(val) ((rs_standby_standby_peri_reg_58*)&(val))



#define STANDBY_STANDBY_PERI_REG_5C                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x5C)

#define STANDBY_STANDBY_PERI_REG_5C_struct                               rs_standby_standby_peri_reg_5c

typedef struct _rs_standby_standby_peri_reg_5c  rs_standby_standby_peri_reg_5c;
struct _rs_standby_standby_peri_reg_5c {
    unsigned int reg_dprx1_aux_timeout_th                   :16;
    unsigned int reg_dprx1_aux_tx_dly_thro                  :16;
};
#define standby_standby_peri_reg_5c(val) ((rs_standby_standby_peri_reg_5c*)&(val))



#define STANDBY_STANDBY_PERI_REG_60                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x60)

#define STANDBY_STANDBY_PERI_REG_60_struct                               rs_standby_standby_peri_reg_60

typedef struct _rs_standby_standby_peri_reg_60  rs_standby_standby_peri_reg_60;
struct _rs_standby_standby_peri_reg_60 {
    unsigned int reg_dprx1_aux_tx_inv                       : 1;
    unsigned int reg_dprx1_aux_tx_phase_dly_en              : 1;
    unsigned int reg_dprx1_aux_tx_precharge_on              : 1;
    unsigned int reg_dprx1_aux_tx_wake_sel                  : 2;
    unsigned int reg_dprx1_aux_wake_addr                    :20;
    unsigned int reserved                                   : 7;
};
#define standby_standby_peri_reg_60(val) ((rs_standby_standby_peri_reg_60*)&(val))



#define STANDBY_STANDBY_PERI_REG_64                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x64)

#define STANDBY_STANDBY_PERI_REG_64_struct                               rs_standby_standby_peri_reg_64

typedef struct _rs_standby_standby_peri_reg_64  rs_standby_standby_peri_reg_64;
struct _rs_standby_standby_peri_reg_64 {
    unsigned int reg_dprx1_aux_wake_sel                     :12;
    unsigned int reg_dprx1_aux_wake_wdata                   : 8;
    unsigned int reg_dprx1_aux_wake_wr                      : 1;
    unsigned int reg_dprx1_edid_addr0                       : 8;
    unsigned int reserved                                   : 3;
};
#define standby_standby_peri_reg_64(val) ((rs_standby_standby_peri_reg_64*)&(val))



#define STANDBY_STANDBY_PERI_REG_68                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x68)

#define STANDBY_STANDBY_PERI_REG_68_struct                               rs_standby_standby_peri_reg_68

typedef struct _rs_standby_standby_peri_reg_68  rs_standby_standby_peri_reg_68;
struct _rs_standby_standby_peri_reg_68 {
    unsigned int reg_dprx1_edid_addr1                       : 8;
    unsigned int reg_dprx1_edid_seg_addr                    : 8;
    unsigned int reg_dprx1_aux_i2c_invalid_addr_en          : 1;
    unsigned int reserved                                   :15;
};
#define standby_standby_peri_reg_68(val) ((rs_standby_standby_peri_reg_68*)&(val))



#define STANDBY_STANDBY_PERI_REG_6C                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x6C)

#define STANDBY_STANDBY_PERI_REG_6C_struct                               rs_standby_standby_peri_reg_6c

typedef struct _rs_standby_standby_peri_reg_6c  rs_standby_standby_peri_reg_6c;
struct _rs_standby_standby_peri_reg_6c {
    unsigned int regr_dprx1_aux_addr                        :20;
    unsigned int regr_dprx1_aux_commd                       : 4;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_6c(val) ((rs_standby_standby_peri_reg_6c*)&(val))



#define STANDBY_STANDBY_PERI_REG_70                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x70)

#define STANDBY_STANDBY_PERI_REG_70_struct                               rs_standby_standby_peri_reg_70

typedef struct _rs_standby_standby_peri_reg_70  rs_standby_standby_peri_reg_70;
struct _rs_standby_standby_peri_reg_70 {
    unsigned int regr_dprx1_aux_dbg_cmd_cnt                 :16;
    unsigned int regr_dprx1_aux_freq_cnt                    :16;
};
#define standby_standby_peri_reg_70(val) ((rs_standby_standby_peri_reg_70*)&(val))



#define STANDBY_STANDBY_PERI_REG_74                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x74)

#define STANDBY_STANDBY_PERI_REG_74_struct                               rs_standby_standby_peri_reg_74

typedef struct _rs_standby_standby_peri_reg_74  rs_standby_standby_peri_reg_74;
struct _rs_standby_standby_peri_reg_74 {
    unsigned int regr_dprx1_aux_len                         : 8;
    unsigned int regr_dprx1_aux_rx_time_out                 : 1;
    unsigned int regr_dprx1_aux_state                       : 4;
    unsigned int reserved                                   :19;
};
#define standby_standby_peri_reg_74(val) ((rs_standby_standby_peri_reg_74*)&(val))



#define STANDBY_STANDBY_PERI_REG_78                                      (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x78)

#define STANDBY_STANDBY_PERI_REG_78_struct                               rs_standby_standby_peri_reg_78

typedef struct _rs_standby_standby_peri_reg_78  rs_standby_standby_peri_reg_78;
struct _rs_standby_standby_peri_reg_78 {
    unsigned int regr_dprx1_aux_100_wdata                   : 8;
    unsigned int regr_dprx1_aux_101_wdata                   : 8;
    unsigned int reserved                                   :16;
};
#define standby_standby_peri_reg_78(val) ((rs_standby_standby_peri_reg_78*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_ADC0                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x80)

#define STANDBY_STANDBY_PERI_REG_STBY_ADC0_struct                        rs_standby_standby_peri_reg_stby_adc0

typedef struct _rs_standby_standby_peri_reg_stby_adc0  rs_standby_standby_peri_reg_stby_adc0;
struct _rs_standby_standby_peri_reg_stby_adc0 {
    unsigned int reg_adc0_en                                : 1;
    unsigned int reg_adc0_pd                                : 1;
    unsigned int reg_adc0_puls_mod                          : 1;
    unsigned int reg_adc0_bridge                            : 4;
    unsigned int reg_adc0_ib_comp                           : 2;
    unsigned int reg_adc0_odmode                            : 1;
    unsigned int reg_adc0_clk_div                           : 2;
    unsigned int reg_adc0_vref_sel                          : 4;
    unsigned int reg_adc1_en                                : 1;
    unsigned int reg_adc1_pd                                : 1;
    unsigned int reg_adc1_puls_mod                          : 1;
    unsigned int reg_adc1_bridge                            : 4;
    unsigned int reg_adc1_ib_comp                           : 2;
    unsigned int reg_adc1_odmode                            : 1;
    unsigned int reg_adc1_clk_div                           : 2;
    unsigned int reg_adc1_vref_sel                          : 4;
};
#define standby_standby_peri_reg_stby_adc0(val) ((rs_standby_standby_peri_reg_stby_adc0*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_ADC1                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x84)

#define STANDBY_STANDBY_PERI_REG_STBY_ADC1_struct                        rs_standby_standby_peri_reg_stby_adc1

typedef struct _rs_standby_standby_peri_reg_stby_adc1  rs_standby_standby_peri_reg_stby_adc1;
struct _rs_standby_standby_peri_reg_stby_adc1 {
    unsigned int reg_adc0_lth                               :12;
    unsigned int reserved                                   : 4;
    unsigned int reg_adc0_hth                               :12;
    unsigned int reserved_1                                 : 4;
};
#define standby_standby_peri_reg_stby_adc1(val) ((rs_standby_standby_peri_reg_stby_adc1*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_ADC2                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x88)

#define STANDBY_STANDBY_PERI_REG_STBY_ADC2_struct                        rs_standby_standby_peri_reg_stby_adc2

typedef struct _rs_standby_standby_peri_reg_stby_adc2  rs_standby_standby_peri_reg_stby_adc2;
struct _rs_standby_standby_peri_reg_stby_adc2 {
    unsigned int reg_adc1_lth                               :12;
    unsigned int reserved                                   : 4;
    unsigned int reg_adc1_hth                               :12;
    unsigned int reserved_1                                 : 4;
};
#define standby_standby_peri_reg_stby_adc2(val) ((rs_standby_standby_peri_reg_stby_adc2*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_ADC3                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x8C)

#define STANDBY_STANDBY_PERI_REG_STBY_ADC3_struct                        rs_standby_standby_peri_reg_stby_adc3

typedef struct _rs_standby_standby_peri_reg_stby_adc3  rs_standby_standby_peri_reg_stby_adc3;
struct _rs_standby_standby_peri_reg_stby_adc3 {
    unsigned int regr_adc0_data                             :12;
    unsigned int reserved                                   : 4;
    unsigned int regr_adc1_data                             :12;
    unsigned int reserved_1                                 : 4;
};
#define standby_standby_peri_reg_stby_adc3(val) ((rs_standby_standby_peri_reg_stby_adc3*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO0                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x90)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO0_struct                       rs_standby_standby_peri_reg_stby_gpio0

typedef struct _rs_standby_standby_peri_reg_stby_gpio0  rs_standby_standby_peri_reg_stby_gpio0;
struct _rs_standby_standby_peri_reg_stby_gpio0 {
    unsigned int reg_gpio_o                                 : 8;
    unsigned int reg_gpio_oe                                : 8;
    unsigned int regr_gpio_i                                : 8;
    unsigned int reg_gpio_pol                               : 8;
};
#define standby_standby_peri_reg_stby_gpio0(val) ((rs_standby_standby_peri_reg_stby_gpio0*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO2                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x94)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO2_struct                       rs_standby_standby_peri_reg_stby_gpio2

typedef struct _rs_standby_standby_peri_reg_stby_gpio2  rs_standby_standby_peri_reg_stby_gpio2;
struct _rs_standby_standby_peri_reg_stby_gpio2 {
    unsigned int reg_gp0_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio2(val) ((rs_standby_standby_peri_reg_stby_gpio2*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO3                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x98)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO3_struct                       rs_standby_standby_peri_reg_stby_gpio3

typedef struct _rs_standby_standby_peri_reg_stby_gpio3  rs_standby_standby_peri_reg_stby_gpio3;
struct _rs_standby_standby_peri_reg_stby_gpio3 {
    unsigned int reg_gp1_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio3(val) ((rs_standby_standby_peri_reg_stby_gpio3*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO4                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0x9C)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO4_struct                       rs_standby_standby_peri_reg_stby_gpio4

typedef struct _rs_standby_standby_peri_reg_stby_gpio4  rs_standby_standby_peri_reg_stby_gpio4;
struct _rs_standby_standby_peri_reg_stby_gpio4 {
    unsigned int reg_gp2_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio4(val) ((rs_standby_standby_peri_reg_stby_gpio4*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO5                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xA0)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO5_struct                       rs_standby_standby_peri_reg_stby_gpio5

typedef struct _rs_standby_standby_peri_reg_stby_gpio5  rs_standby_standby_peri_reg_stby_gpio5;
struct _rs_standby_standby_peri_reg_stby_gpio5 {
    unsigned int reg_gp3_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio5(val) ((rs_standby_standby_peri_reg_stby_gpio5*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO6                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xA4)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO6_struct                       rs_standby_standby_peri_reg_stby_gpio6

typedef struct _rs_standby_standby_peri_reg_stby_gpio6  rs_standby_standby_peri_reg_stby_gpio6;
struct _rs_standby_standby_peri_reg_stby_gpio6 {
    unsigned int reg_gp4_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio6(val) ((rs_standby_standby_peri_reg_stby_gpio6*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO7                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xA8)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO7_struct                       rs_standby_standby_peri_reg_stby_gpio7

typedef struct _rs_standby_standby_peri_reg_stby_gpio7  rs_standby_standby_peri_reg_stby_gpio7;
struct _rs_standby_standby_peri_reg_stby_gpio7 {
    unsigned int reg_gp5_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio7(val) ((rs_standby_standby_peri_reg_stby_gpio7*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO8                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xAC)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO8_struct                       rs_standby_standby_peri_reg_stby_gpio8

typedef struct _rs_standby_standby_peri_reg_stby_gpio8  rs_standby_standby_peri_reg_stby_gpio8;
struct _rs_standby_standby_peri_reg_stby_gpio8 {
    unsigned int reg_gp6_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio8(val) ((rs_standby_standby_peri_reg_stby_gpio8*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_GPIO9                              (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xB0)

#define STANDBY_STANDBY_PERI_REG_STBY_GPIO9_struct                       rs_standby_standby_peri_reg_stby_gpio9

typedef struct _rs_standby_standby_peri_reg_stby_gpio9  rs_standby_standby_peri_reg_stby_gpio9;
struct _rs_standby_standby_peri_reg_stby_gpio9 {
    unsigned int reg_gp7_filter_num                         :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_gpio9(val) ((rs_standby_standby_peri_reg_stby_gpio9*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_ADC4                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xB4)

#define STANDBY_STANDBY_PERI_REG_STBY_ADC4_struct                        rs_standby_standby_peri_reg_stby_adc4

typedef struct _rs_standby_standby_peri_reg_stby_adc4  rs_standby_standby_peri_reg_stby_adc4;
struct _rs_standby_standby_peri_reg_stby_adc4 {
    unsigned int reg_adc0_filter_num                        :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_adc4(val) ((rs_standby_standby_peri_reg_stby_adc4*)&(val))



#define STANDBY_STANDBY_PERI_REG_STBY_ADC5                               (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xB8)

#define STANDBY_STANDBY_PERI_REG_STBY_ADC5_struct                        rs_standby_standby_peri_reg_stby_adc5

typedef struct _rs_standby_standby_peri_reg_stby_adc5  rs_standby_standby_peri_reg_stby_adc5;
struct _rs_standby_standby_peri_reg_stby_adc5 {
    unsigned int reg_adc1_filter_num                        :24;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_stby_adc5(val) ((rs_standby_standby_peri_reg_stby_adc5*)&(val))



#define STANDBY_STANDBY_PERI_REG_PWM0                                    (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xC0)

#define STANDBY_STANDBY_PERI_REG_PWM0_struct                             rs_standby_standby_peri_reg_pwm0

typedef struct _rs_standby_standby_peri_reg_pwm0  rs_standby_standby_peri_reg_pwm0;
struct _rs_standby_standby_peri_reg_pwm0 {
    unsigned int reg_pwm_ch_en                              : 1;
    unsigned int reg_pwm_cnt_mode                           : 1;
    unsigned int reg_pwm_output_mode                        : 1;
    unsigned int reg_pwm_pol                                : 1;
    unsigned int reg_pwm_prescaler                          : 4;
    unsigned int reg_pwm_counter_top                        :16;
    unsigned int reserved                                   : 8;
};
#define standby_standby_peri_reg_pwm0(val) ((rs_standby_standby_peri_reg_pwm0*)&(val))



#define STANDBY_STANDBY_PERI_REG_PWM1                                    (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xC4)

#define STANDBY_STANDBY_PERI_REG_PWM1_struct                             rs_standby_standby_peri_reg_pwm1

typedef struct _rs_standby_standby_peri_reg_pwm1  rs_standby_standby_peri_reg_pwm1;
struct _rs_standby_standby_peri_reg_pwm1 {
    unsigned int reg_pwm_cmp_start_val                      :16;
    unsigned int reg_pwm_cmp_end_val                        :16;
};
#define standby_standby_peri_reg_pwm1(val) ((rs_standby_standby_peri_reg_pwm1*)&(val))



#define STANDBY_STANDBY_PERI_REG_PWM2                                    (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xC8)

#define STANDBY_STANDBY_PERI_REG_PWM2_struct                             rs_standby_standby_peri_reg_pwm2

typedef struct _rs_standby_standby_peri_reg_pwm2  rs_standby_standby_peri_reg_pwm2;
struct _rs_standby_standby_peri_reg_pwm2 {
    unsigned int reg_pwm_cmp_step_val                       :16;
    unsigned int reg_pwm_cycle_num                          :16;
};
#define standby_standby_peri_reg_pwm2(val) ((rs_standby_standby_peri_reg_pwm2*)&(val))



#define STANDBY_STANDBY_PERI_REG_PWM3                                    (HV_STANDBY_PERI_REG_BASE_ADDRESS + 0xCC)

#define STANDBY_STANDBY_PERI_REG_PWM3_struct                             rs_standby_standby_peri_reg_pwm3

typedef struct _rs_standby_standby_peri_reg_pwm3  rs_standby_standby_peri_reg_pwm3;
struct _rs_standby_standby_peri_reg_pwm3 {
    unsigned int reg_pwm_rep                                :16;
    unsigned int regr_pwm_cnt_val                           :16;
};
#define standby_standby_peri_reg_pwm3(val) ((rs_standby_standby_peri_reg_pwm3*)&(val))



#endif