#ifndef _HV_PAGE_HT7315_REG_SH5_TOP0_H_
#define _HV_PAGE_HT7315_REG_SH5_TOP0_H_

#ifndef HV_REG_SH5_TOP0_BASE_ADDRESS
    #define HV_REG_SH5_TOP0_BASE_ADDRESS                                         0x11011100
#endif


#define SYS_REG_SH5_TOP0_MIPS0_CTRL0                                     (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x10)

#define SYS_REG_SH5_TOP0_MIPS0_CTRL0_struct                              rs_sys_reg_sh5_top0_mips0_ctrl0

typedef struct _rs_sys_reg_sh5_top0_mips0_ctrl0  rs_sys_reg_sh5_top0_mips0_ctrl0;
struct _rs_sys_reg_sh5_top0_mips0_ctrl0 {
    unsigned int reserved                                   :12;
    unsigned int mips0_ExceptionBase                        :20;
};
#define sys_reg_sh5_top0_mips0_ctrl0(val) ((rs_sys_reg_sh5_top0_mips0_ctrl0*)&(val))



#define SYS_REG_SH5_TOP0_MIPS0_CTRL1                                     (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x14)

#define SYS_REG_SH5_TOP0_MIPS0_CTRL1_struct                              rs_sys_reg_sh5_top0_mips0_ctrl1

typedef struct _rs_sys_reg_sh5_top0_mips0_ctrl1  rs_sys_reg_sh5_top0_mips0_ctrl1;
struct _rs_sys_reg_sh5_top0_mips0_ctrl1 {
    unsigned int mips0_UseExceptionBase                     : 1;
    unsigned int mips0_EVAReset                             : 1;
    unsigned int mips0_srst_en                              : 1;
    unsigned int mips0_peri_srst_en                         : 1;
    unsigned int mips0_reg_rstn                             : 1;
    unsigned int reserved                                   :15;
    unsigned int mips0_ExceptionBaseMask                    : 8;
    unsigned int reserved_1                                 : 1;
    unsigned int mips0_ExceptionBasePA                      : 3;
};
#define sys_reg_sh5_top0_mips0_ctrl1(val) ((rs_sys_reg_sh5_top0_mips0_ctrl1*)&(val))



#define SYS_REG_SH5_TOP0_MIPS0_GIC                                       (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x18)

#define SYS_REG_SH5_TOP0_MIPS0_GIC_struct                                rs_sys_reg_sh5_top0_mips0_gic

typedef struct _rs_sys_reg_sh5_top0_mips0_gic  rs_sys_reg_sh5_top0_mips0_gic;
struct _rs_sys_reg_sh5_top0_mips0_gic {
    unsigned int mips0_IPFDCI                               : 3;
    unsigned int reserved                                   : 1;
    unsigned int mips0_IPPCI                                : 3;
    unsigned int reserved_1                                 : 1;
    unsigned int mips0_IPTI                                 : 3;
    unsigned int reserved_2                                 : 1;
    unsigned int mips0_EICPresent                           : 1;
    unsigned int reserved_3                                 : 3;
    unsigned int mips0_PCEvent                              : 8;
    unsigned int mips0_EISS                                 : 4;
    unsigned int reserved_4                                 : 4;
};
#define sys_reg_sh5_top0_mips0_gic(val) ((rs_sys_reg_sh5_top0_mips0_gic*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_PERIPHER_CG_RG                          (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x1C)

#define SYS_REG_SH5_TOP0_REG_SH5_PERIPHER_CG_RG_struct                   rs_sys_reg_sh5_top0_reg_sh5_peripher_cg_rg

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_peripher_cg_rg  rs_sys_reg_sh5_top0_reg_sh5_peripher_cg_rg;
struct _rs_sys_reg_sh5_top0_reg_sh5_peripher_cg_rg {
    unsigned int reg_sh5_peripher_pdma_clk_en               : 1;
    unsigned int reg_sh5_peripher_gpio_clk_en               : 1;
    unsigned int reg_sh5_peripher_iic0_clk_en               : 1;
    unsigned int reg_sh5_peripher_iic1_clk_en               : 1;
    unsigned int reg_sh5_peripher_qspi_clk_en               : 1;
    unsigned int reg_sh5_peripher_spim_clk_en               : 1;
    unsigned int reg_sh5_peripher_timer0_clk_en             : 1;
    unsigned int reg_sh5_peripher_timer1_clk_en             : 1;
    unsigned int reg_sh5_peripher_timer2_clk_en             : 1;
    unsigned int reg_sh5_peripher_timer3_clk_en             : 1;
    unsigned int reg_sh5_peripher_timer4_clk_en             : 1;
    unsigned int reg_sh5_peripher_timer5_clk_en             : 1;
    unsigned int reg_sh5_peripher_uart0_clk_en              : 1;
    unsigned int reg_sh5_peripher_uart1_clk_en              : 1;
    unsigned int reg_sh5_peripher_wdg_clk_en                : 1;
    unsigned int reg_sh5_peripher_res0_clk_en               : 1;
    unsigned int reg_sh5_peripher_pdma_rstn                 : 1;
    unsigned int reg_sh5_peripher_gpio_rstn                 : 1;
    unsigned int reg_sh5_peripher_iic0_rstn                 : 1;
    unsigned int reg_sh5_peripher_iic1_rstn                 : 1;
    unsigned int reg_sh5_peripher_qspi_rstn                 : 1;
    unsigned int reg_sh5_peripher_spim_rstn                 : 1;
    unsigned int reg_sh5_peripher_timer0_rstn               : 1;
    unsigned int reg_sh5_peripher_timer1_rstn               : 1;
    unsigned int reg_sh5_peripher_timer2_rstn               : 1;
    unsigned int reg_sh5_peripher_timer3_rstn               : 1;
    unsigned int reg_sh5_peripher_timer4_rstn               : 1;
    unsigned int reg_sh5_peripher_timer5_rstn               : 1;
    unsigned int reg_sh5_peripher_uart0_rstn                : 1;
    unsigned int reg_sh5_peripher_uart1_rstn                : 1;
    unsigned int reg_sh5_peripher_wdg_rstn                  : 1;
    unsigned int reg_sh5_peripher_res0_rstn                 : 1;
};
#define sys_reg_sh5_top0_reg_sh5_peripher_cg_rg(val) ((rs_sys_reg_sh5_top0_reg_sh5_peripher_cg_rg*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_MEM_BIST                                (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x20)

#define SYS_REG_SH5_TOP0_REG_SH5_MEM_BIST_struct                         rs_sys_reg_sh5_top0_reg_sh5_mem_bist

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_mem_bist  rs_sys_reg_sh5_top0_reg_sh5_mem_bist;
struct _rs_sys_reg_sh5_top0_reg_sh5_mem_bist {
    unsigned int reg_mem_ema                                :16;
    unsigned int reg_mem_reg                                : 8;
    unsigned int reserved                                   : 8;
};
#define sys_reg_sh5_top0_reg_sh5_mem_bist(val) ((rs_sys_reg_sh5_top0_reg_sh5_mem_bist*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED0                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x24)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED0_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed0

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed0  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed0;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed0 {
    unsigned int reg_sh5_dbg_spi_sel                        : 1;
    unsigned int reg_sh5_uart0_rx_sel                       : 1;
    unsigned int reg_sh5_dbg_spiclk_en                      : 1;
    unsigned int reg_qspi_fixed_little_endian               : 1;
    unsigned int reg_sh5_dbg_spi_clk_inv_en                 : 1;
    unsigned int reserved                                   :27;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed0(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed0*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED1                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x28)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED1_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed1

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed1  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed1;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed1 {
    unsigned int reg_sh5_int_mux                            :32;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed1(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed1*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED2                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x2C)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED2_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed2

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed2  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed2;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed2 {
    unsigned int reg_sh5_qspi_xip_en                        : 1;
    unsigned int reg_mips0_jtag_rstn                        : 1;
    unsigned int reg_mips0_jtag_xor_rstn                    : 1;
    unsigned int reserved                                   :29;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed2(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed2*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED3                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x30)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED3_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed3

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed3  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed3;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed3 {
    unsigned int reg_sh5_debug_signal_mux                   :16;
    unsigned int reserved                                   :16;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed3(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed3*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED4                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x34)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED4_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed4

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed4  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed4;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed4 {
    unsigned int reg_sh5_wdg_ctl                            :32;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed4(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed4*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED5                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x38)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED5_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed5

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed5  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed5;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed5 {
    unsigned int reg_sh5_wdg_cnt                            :32;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed5(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed5*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED6                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x3C)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED6_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed6

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed6  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed6;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed6 {
    unsigned int reg_sh5_wdg_prl                            :32;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed6(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed6*)&(val))



#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED7                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x40)

#define SYS_REG_SH5_TOP0_REG_SH5_WDG_FILED7_struct                       rs_sys_reg_sh5_top0_reg_sh5_wdg_filed7

typedef struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed7  rs_sys_reg_sh5_top0_reg_sh5_wdg_filed7;
struct _rs_sys_reg_sh5_top0_reg_sh5_wdg_filed7 {
    unsigned int reg_sh5_wdg_prediv                         :16;
    unsigned int reg_sh5_wdg_reload_en                      : 1;
    unsigned int reg_sh5_wdg_reset                          : 1;
    unsigned int reserved                                   :14;
};
#define sys_reg_sh5_top0_reg_sh5_wdg_filed7(val) ((rs_sys_reg_sh5_top0_reg_sh5_wdg_filed7*)&(val))



#define SYS_REG_SH5_TOP0_MISC_INT_0                                      (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x44)

#define SYS_REG_SH5_TOP0_MISC_INT_0_struct                               rs_sys_reg_sh5_top0_misc_int_0

typedef struct _rs_sys_reg_sh5_top0_misc_int_0  rs_sys_reg_sh5_top0_misc_int_0;
struct _rs_sys_reg_sh5_top0_misc_int_0 {
    unsigned int reg_misc_int_bypass                        :32;
};
#define sys_reg_sh5_top0_misc_int_0(val) ((rs_sys_reg_sh5_top0_misc_int_0*)&(val))



#define SYS_REG_SH5_TOP0_48                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x48)

#define SYS_REG_SH5_TOP0_48_struct                                       rs_sys_reg_sh5_top0_48

typedef struct _rs_sys_reg_sh5_top0_48  rs_sys_reg_sh5_top0_48;
struct _rs_sys_reg_sh5_top0_48 {
    unsigned int reg_misc_int_en                            :32;
};
#define sys_reg_sh5_top0_48(val) ((rs_sys_reg_sh5_top0_48*)&(val))



#define SYS_REG_SH5_TOP0_MISC_INT_1                                      (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x4C)

#define SYS_REG_SH5_TOP0_MISC_INT_1_struct                               rs_sys_reg_sh5_top0_misc_int_1

typedef struct _rs_sys_reg_sh5_top0_misc_int_1  rs_sys_reg_sh5_top0_misc_int_1;
struct _rs_sys_reg_sh5_top0_misc_int_1 {
    unsigned int reg_misc_int_wclr                          :32;
};
#define sys_reg_sh5_top0_misc_int_1(val) ((rs_sys_reg_sh5_top0_misc_int_1*)&(val))



#define SYS_REG_SH5_TOP0_MISC_INT_2                                      (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x50)

#define SYS_REG_SH5_TOP0_MISC_INT_2_struct                               rs_sys_reg_sh5_top0_misc_int_2

typedef struct _rs_sys_reg_sh5_top0_misc_int_2  rs_sys_reg_sh5_top0_misc_int_2;
struct _rs_sys_reg_sh5_top0_misc_int_2 {
    unsigned int reg_misc_int_level_p                       :32;
};
#define sys_reg_sh5_top0_misc_int_2(val) ((rs_sys_reg_sh5_top0_misc_int_2*)&(val))



#define SYS_REG_SH5_TOP0_MISC_INT_3                                      (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x54)

#define SYS_REG_SH5_TOP0_MISC_INT_3_struct                               rs_sys_reg_sh5_top0_misc_int_3

typedef struct _rs_sys_reg_sh5_top0_misc_int_3  rs_sys_reg_sh5_top0_misc_int_3;
struct _rs_sys_reg_sh5_top0_misc_int_3 {
    unsigned int reg_misc_int_level_n                       :32;
};
#define sys_reg_sh5_top0_misc_int_3(val) ((rs_sys_reg_sh5_top0_misc_int_3*)&(val))



#define SYS_REG_SH5_TOP0_MISC_INT_4                                      (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x58)

#define SYS_REG_SH5_TOP0_MISC_INT_4_struct                               rs_sys_reg_sh5_top0_misc_int_4

typedef struct _rs_sys_reg_sh5_top0_misc_int_4  rs_sys_reg_sh5_top0_misc_int_4;
struct _rs_sys_reg_sh5_top0_misc_int_4 {
    unsigned int reg_misc_int_edge_p                        :32;
};
#define sys_reg_sh5_top0_misc_int_4(val) ((rs_sys_reg_sh5_top0_misc_int_4*)&(val))



#define SYS_REG_SH5_TOP0_MISC_INT_5                                      (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x5C)

#define SYS_REG_SH5_TOP0_MISC_INT_5_struct                               rs_sys_reg_sh5_top0_misc_int_5

typedef struct _rs_sys_reg_sh5_top0_misc_int_5  rs_sys_reg_sh5_top0_misc_int_5;
struct _rs_sys_reg_sh5_top0_misc_int_5 {
    unsigned int reg_misc_int_edge_n                        :32;
};
#define sys_reg_sh5_top0_misc_int_5(val) ((rs_sys_reg_sh5_top0_misc_int_5*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE0                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x60)

#define SYS_REG_SH5_TOP0_SW_USE0_struct                                  rs_sys_reg_sh5_top0_sw_use0

typedef struct _rs_sys_reg_sh5_top0_sw_use0  rs_sys_reg_sh5_top0_sw_use0;
struct _rs_sys_reg_sh5_top0_sw_use0 {
    unsigned int reg_sw_use_dummy0                          :32;
};
#define sys_reg_sh5_top0_sw_use0(val) ((rs_sys_reg_sh5_top0_sw_use0*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE1                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x64)

#define SYS_REG_SH5_TOP0_SW_USE1_struct                                  rs_sys_reg_sh5_top0_sw_use1

typedef struct _rs_sys_reg_sh5_top0_sw_use1  rs_sys_reg_sh5_top0_sw_use1;
struct _rs_sys_reg_sh5_top0_sw_use1 {
    unsigned int reg_sw_use_dummy1                          :32;
};
#define sys_reg_sh5_top0_sw_use1(val) ((rs_sys_reg_sh5_top0_sw_use1*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE2                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x68)

#define SYS_REG_SH5_TOP0_SW_USE2_struct                                  rs_sys_reg_sh5_top0_sw_use2

typedef struct _rs_sys_reg_sh5_top0_sw_use2  rs_sys_reg_sh5_top0_sw_use2;
struct _rs_sys_reg_sh5_top0_sw_use2 {
    unsigned int reg_sw_use_dummy2                          :32;
};
#define sys_reg_sh5_top0_sw_use2(val) ((rs_sys_reg_sh5_top0_sw_use2*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE3                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x6C)

#define SYS_REG_SH5_TOP0_SW_USE3_struct                                  rs_sys_reg_sh5_top0_sw_use3

typedef struct _rs_sys_reg_sh5_top0_sw_use3  rs_sys_reg_sh5_top0_sw_use3;
struct _rs_sys_reg_sh5_top0_sw_use3 {
    unsigned int reg_sw_use_dummy3                          :32;
};
#define sys_reg_sh5_top0_sw_use3(val) ((rs_sys_reg_sh5_top0_sw_use3*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE4                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x70)

#define SYS_REG_SH5_TOP0_SW_USE4_struct                                  rs_sys_reg_sh5_top0_sw_use4

typedef struct _rs_sys_reg_sh5_top0_sw_use4  rs_sys_reg_sh5_top0_sw_use4;
struct _rs_sys_reg_sh5_top0_sw_use4 {
    unsigned int reg_sw_use_dummy4                          :32;
};
#define sys_reg_sh5_top0_sw_use4(val) ((rs_sys_reg_sh5_top0_sw_use4*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE5                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x74)

#define SYS_REG_SH5_TOP0_SW_USE5_struct                                  rs_sys_reg_sh5_top0_sw_use5

typedef struct _rs_sys_reg_sh5_top0_sw_use5  rs_sys_reg_sh5_top0_sw_use5;
struct _rs_sys_reg_sh5_top0_sw_use5 {
    unsigned int reg_sw_use_dummy5                          :32;
};
#define sys_reg_sh5_top0_sw_use5(val) ((rs_sys_reg_sh5_top0_sw_use5*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE6                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x78)

#define SYS_REG_SH5_TOP0_SW_USE6_struct                                  rs_sys_reg_sh5_top0_sw_use6

typedef struct _rs_sys_reg_sh5_top0_sw_use6  rs_sys_reg_sh5_top0_sw_use6;
struct _rs_sys_reg_sh5_top0_sw_use6 {
    unsigned int reg_sw_use_dummy6                          :32;
};
#define sys_reg_sh5_top0_sw_use6(val) ((rs_sys_reg_sh5_top0_sw_use6*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE7                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x7C)

#define SYS_REG_SH5_TOP0_SW_USE7_struct                                  rs_sys_reg_sh5_top0_sw_use7

typedef struct _rs_sys_reg_sh5_top0_sw_use7  rs_sys_reg_sh5_top0_sw_use7;
struct _rs_sys_reg_sh5_top0_sw_use7 {
    unsigned int reg_sw_use_dummy7                          :32;
};
#define sys_reg_sh5_top0_sw_use7(val) ((rs_sys_reg_sh5_top0_sw_use7*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE8                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x80)

#define SYS_REG_SH5_TOP0_SW_USE8_struct                                  rs_sys_reg_sh5_top0_sw_use8

typedef struct _rs_sys_reg_sh5_top0_sw_use8  rs_sys_reg_sh5_top0_sw_use8;
struct _rs_sys_reg_sh5_top0_sw_use8 {
    unsigned int reg_sw_use_dummy8                          :32;
};
#define sys_reg_sh5_top0_sw_use8(val) ((rs_sys_reg_sh5_top0_sw_use8*)&(val))



#define SYS_REG_SH5_TOP0_SW_USE9                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x84)

#define SYS_REG_SH5_TOP0_SW_USE9_struct                                  rs_sys_reg_sh5_top0_sw_use9

typedef struct _rs_sys_reg_sh5_top0_sw_use9  rs_sys_reg_sh5_top0_sw_use9;
struct _rs_sys_reg_sh5_top0_sw_use9 {
    unsigned int reg_sw_use_dummy9                          :32;
};
#define sys_reg_sh5_top0_sw_use9(val) ((rs_sys_reg_sh5_top0_sw_use9*)&(val))



#define SYS_REG_SH5_TOP0_88                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x88)

#define SYS_REG_SH5_TOP0_88_struct                                       rs_sys_reg_sh5_top0_88

typedef struct _rs_sys_reg_sh5_top0_88  rs_sys_reg_sh5_top0_88;
struct _rs_sys_reg_sh5_top0_88 {
    unsigned int reg_misc_int_mon_sel                       : 8;
    unsigned int reserved                                   :24;
};
#define sys_reg_sh5_top0_88(val) ((rs_sys_reg_sh5_top0_88*)&(val))



#define SYS_REG_SH5_TOP0_8C                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x8C)

#define SYS_REG_SH5_TOP0_8C_struct                                       rs_sys_reg_sh5_top0_8c

typedef struct _rs_sys_reg_sh5_top0_8c  rs_sys_reg_sh5_top0_8c;
struct _rs_sys_reg_sh5_top0_8c {
    unsigned int regr_misc_int_mon_cnt                      : 8;
    unsigned int reserved                                   :24;
};
#define sys_reg_sh5_top0_8c(val) ((rs_sys_reg_sh5_top0_8c*)&(val))



#define SYS_REG_SH5_TOP0_90                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0x90)

#define SYS_REG_SH5_TOP0_90_struct                                       rs_sys_reg_sh5_top0_90

typedef struct _rs_sys_reg_sh5_top0_90  rs_sys_reg_sh5_top0_90;
struct _rs_sys_reg_sh5_top0_90 {
    unsigned int reg_dbgspi2ahb_rd_time                     : 9;
    unsigned int reserved                                   :23;
};
#define sys_reg_sh5_top0_90(val) ((rs_sys_reg_sh5_top0_90*)&(val))



#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD0                          (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xA0)

#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD0_struct                   rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field0

typedef struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field0  rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field0;
struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field0 {
    unsigned int mips0_regr_sh5_mem_ro_dd0                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_dd1                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_dd2                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_dd3                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_dt0                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_dt1                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_dt2                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_dt3                  : 4;
};
#define sys_reg_sh5_top0_regr_sh5_mem_ro_field0(val) ((rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field0*)&(val))



#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD1                          (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xA4)

#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD1_struct                   rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field1

typedef struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field1  rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field1;
struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field1 {
    unsigned int mips0_regr_sh5_mem_ro_id0                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_id1                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_id2                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_id3                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_it0                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_it1                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_it2                  : 4;
    unsigned int mips0_regr_sh5_mem_ro_it3                  : 4;
};
#define sys_reg_sh5_top0_regr_sh5_mem_ro_field1(val) ((rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field1*)&(val))



#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD2                          (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xA8)

#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD2_struct                   rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field2

typedef struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field2  rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field2;
struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field2 {
    unsigned int mips0_regr_sh5_mem_ro_mips                 : 4;
    unsigned int regr_sh5_mem_ro_iram                       : 4;
    unsigned int mips0_regr_mem1_ro_dsp0                    : 4;
    unsigned int mips0_regr_mem1_ro_dsp1                    : 4;
    unsigned int mips0_regr_mem1_ro_isp                     : 4;
    unsigned int reserved                                   :12;
};
#define sys_reg_sh5_top0_regr_sh5_mem_ro_field2(val) ((rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field2*)&(val))



#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD3                          (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xAC)

#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD3_struct                   rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field3

typedef struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field3  rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field3;
struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field3 {
    unsigned int regr_wdg_sts                               :32;
};
#define sys_reg_sh5_top0_regr_sh5_mem_ro_field3(val) ((rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field3*)&(val))



#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD4                          (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xB0)

#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD4_struct                   rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field4

typedef struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field4  rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field4;
struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field4 {
    unsigned int regr_wdg_cnt                               :32;
};
#define sys_reg_sh5_top0_regr_sh5_mem_ro_field4(val) ((rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field4*)&(val))



#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD5                          (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xB4)

#define SYS_REG_SH5_TOP0_REGR_SH5_MEM_RO_FIELD5_struct                   rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field5

typedef struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field5  rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field5;
struct _rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field5 {
    unsigned int regr_wdg_ts_cnt                            :16;
    unsigned int reserved                                   :16;
};
#define sys_reg_sh5_top0_regr_sh5_mem_ro_field5(val) ((rs_sys_reg_sh5_top0_regr_sh5_mem_ro_field5*)&(val))



#define SYS_REG_SH5_TOP0_MISC_INT_READBACK                               (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xB8)

#define SYS_REG_SH5_TOP0_MISC_INT_READBACK_struct                        rs_sys_reg_sh5_top0_misc_int_readback

typedef struct _rs_sys_reg_sh5_top0_misc_int_readback  rs_sys_reg_sh5_top0_misc_int_readback;
struct _rs_sys_reg_sh5_top0_misc_int_readback {
    unsigned int regr_misc_int_pending                      :32;
};
#define sys_reg_sh5_top0_misc_int_readback(val) ((rs_sys_reg_sh5_top0_misc_int_readback*)&(val))



#define SYS_REG_SH5_TOP0_MIPS1_CTRL0                                     (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xBC)

#define SYS_REG_SH5_TOP0_MIPS1_CTRL0_struct                              rs_sys_reg_sh5_top0_mips1_ctrl0

typedef struct _rs_sys_reg_sh5_top0_mips1_ctrl0  rs_sys_reg_sh5_top0_mips1_ctrl0;
struct _rs_sys_reg_sh5_top0_mips1_ctrl0 {
    unsigned int reserved                                   :12;
    unsigned int mips1_ExceptionBase                        :20;
};
#define sys_reg_sh5_top0_mips1_ctrl0(val) ((rs_sys_reg_sh5_top0_mips1_ctrl0*)&(val))



#define SYS_REG_SH5_TOP0_MIPS1_CTRL1                                     (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xD0)

#define SYS_REG_SH5_TOP0_MIPS1_CTRL1_struct                              rs_sys_reg_sh5_top0_mips1_ctrl1

typedef struct _rs_sys_reg_sh5_top0_mips1_ctrl1  rs_sys_reg_sh5_top0_mips1_ctrl1;
struct _rs_sys_reg_sh5_top0_mips1_ctrl1 {
    unsigned int mips1_UseExceptionBase                     : 1;
    unsigned int mips1_EVAReset                             : 1;
    unsigned int mips1_srst_en                              : 1;
    unsigned int mips1_peri_srst_en                         : 1;
    unsigned int mips1_reg_rstn                             : 1;
    unsigned int reserved                                   :15;
    unsigned int mips1_ExceptionBaseMask                    : 8;
    unsigned int reserved_1                                 : 1;
    unsigned int mips1_ExceptionBasePA                      : 3;
};
#define sys_reg_sh5_top0_mips1_ctrl1(val) ((rs_sys_reg_sh5_top0_mips1_ctrl1*)&(val))



#define SYS_REG_SH5_TOP0_MIPS1_GIC                                       (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xD4)

#define SYS_REG_SH5_TOP0_MIPS1_GIC_struct                                rs_sys_reg_sh5_top0_mips1_gic

typedef struct _rs_sys_reg_sh5_top0_mips1_gic  rs_sys_reg_sh5_top0_mips1_gic;
struct _rs_sys_reg_sh5_top0_mips1_gic {
    unsigned int mips1_IPFDCI                               : 3;
    unsigned int reserved                                   : 1;
    unsigned int mips1_IPPCI                                : 3;
    unsigned int reserved_1                                 : 1;
    unsigned int mips1_IPTI                                 : 3;
    unsigned int reserved_2                                 : 1;
    unsigned int mips1_EICPresent                           : 1;
    unsigned int reserved_3                                 : 3;
    unsigned int mips1_PCEvent                              : 8;
    unsigned int mips1_EISS                                 : 4;
    unsigned int reserved_4                                 : 4;
};
#define sys_reg_sh5_top0_mips1_gic(val) ((rs_sys_reg_sh5_top0_mips1_gic*)&(val))



#define SYS_REG_SH5_TOP0_DC                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xDC)

#define SYS_REG_SH5_TOP0_DC_struct                                       rs_sys_reg_sh5_top0_dc

typedef struct _rs_sys_reg_sh5_top0_dc  rs_sys_reg_sh5_top0_dc;
struct _rs_sys_reg_sh5_top0_dc {
    unsigned int reg_cl_ss_clr_status                       : 1;
    unsigned int reserved                                   :31;
};
#define sys_reg_sh5_top0_dc(val) ((rs_sys_reg_sh5_top0_dc*)&(val))



#define SYS_REG_SH5_TOP0_E0                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xE0)

#define SYS_REG_SH5_TOP0_E0_struct                                       rs_sys_reg_sh5_top0_e0

typedef struct _rs_sys_reg_sh5_top0_e0  rs_sys_reg_sh5_top0_e0;
struct _rs_sys_reg_sh5_top0_e0 {
    unsigned int mips1_regr_sh5_mem_ro_dd0                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_dd1                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_dd2                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_dd3                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_dt0                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_dt1                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_dt2                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_dt3                  : 4;
};
#define sys_reg_sh5_top0_e0(val) ((rs_sys_reg_sh5_top0_e0*)&(val))



#define SYS_REG_SH5_TOP0_E4                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xE4)

#define SYS_REG_SH5_TOP0_E4_struct                                       rs_sys_reg_sh5_top0_e4

typedef struct _rs_sys_reg_sh5_top0_e4  rs_sys_reg_sh5_top0_e4;
struct _rs_sys_reg_sh5_top0_e4 {
    unsigned int mips1_regr_sh5_mem_ro_id0                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_id1                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_id2                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_id3                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_it0                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_it1                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_it2                  : 4;
    unsigned int mips1_regr_sh5_mem_ro_it3                  : 4;
};
#define sys_reg_sh5_top0_e4(val) ((rs_sys_reg_sh5_top0_e4*)&(val))



#define SYS_REG_SH5_TOP0_PEC_RUN                                         (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xE8)

#define SYS_REG_SH5_TOP0_PEC_RUN_struct                                  rs_sys_reg_sh5_top0_pec_run

typedef struct _rs_sys_reg_sh5_top0_pec_run  rs_sys_reg_sh5_top0_pec_run;
struct _rs_sys_reg_sh5_top0_pec_run {
    unsigned int reg_pec_run_adr                            :24;
    unsigned int reserved                                   : 8;
};
#define sys_reg_sh5_top0_pec_run(val) ((rs_sys_reg_sh5_top0_pec_run*)&(val))



#define SYS_REG_SH5_TOP0_EC                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xEC)

#define SYS_REG_SH5_TOP0_EC_struct                                       rs_sys_reg_sh5_top0_ec

typedef struct _rs_sys_reg_sh5_top0_ec  rs_sys_reg_sh5_top0_ec;
struct _rs_sys_reg_sh5_top0_ec {
    unsigned int mips1_regr_sh5_mem_ro_mips                 : 4;
    unsigned int mips1_regr_mem1_ro_dsp0                    : 4;
    unsigned int mips1_regr_mem1_ro_dsp1                    : 4;
    unsigned int mips1_regr_mem1_ro_isp                     : 4;
    unsigned int reserved                                   :16;
};
#define sys_reg_sh5_top0_ec(val) ((rs_sys_reg_sh5_top0_ec*)&(val))



#define SYS_REG_SH5_TOP0_F0                                              (HV_REG_SH5_TOP0_BASE_ADDRESS + 0xF0)

#define SYS_REG_SH5_TOP0_F0_struct                                       rs_sys_reg_sh5_top0_f0

typedef struct _rs_sys_reg_sh5_top0_f0  rs_sys_reg_sh5_top0_f0;
struct _rs_sys_reg_sh5_top0_f0 {
    unsigned int reg_sh5_mi2c_pinshare_sel                  : 1;
    unsigned int reserved                                   :31;
};
#define sys_reg_sh5_top0_f0(val) ((rs_sys_reg_sh5_top0_f0*)&(val))



#endif