#ifndef _HV_PAGE_HT7315_EDP_RX_DPCD_3_REG_01_H_
#define _HV_PAGE_HT7315_EDP_RX_DPCD_3_REG_01_H_

#ifndef HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS
    #define HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS                                         0x1104A300
#endif


#define RX_EDP_RX_DPCD_3_REG_01_00                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_DPCD_3_REG_01_00_struct                                rs_rx_edp_rx_dpcd_3_reg_01_00

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_00  rs_rx_edp_rx_dpcd_3_reg_01_00;
struct _rs_rx_edp_rx_dpcd_3_reg_01_00 {
    unsigned int reg_01_dprx_dpcd_source_ieee_oui           :24;
    unsigned int reg_01_dprx_dpcd_source_device_identification_string0: 8;
};
#define rx_edp_rx_dpcd_3_reg_01_00(val) ((rs_rx_edp_rx_dpcd_3_reg_01_00*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_04                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_DPCD_3_REG_01_04_struct                                rs_rx_edp_rx_dpcd_3_reg_01_04

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_04  rs_rx_edp_rx_dpcd_3_reg_01_04;
struct _rs_rx_edp_rx_dpcd_3_reg_01_04 {
    unsigned int reg_01_dprx_dpcd_source_device_identification_string1:32;
};
#define rx_edp_rx_dpcd_3_reg_01_04(val) ((rs_rx_edp_rx_dpcd_3_reg_01_04*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_08                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_DPCD_3_REG_01_08_struct                                rs_rx_edp_rx_dpcd_3_reg_01_08

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_08  rs_rx_edp_rx_dpcd_3_reg_01_08;
struct _rs_rx_edp_rx_dpcd_3_reg_01_08 {
    unsigned int reg_01_dprx_dpcd_source_device_identification_string2: 8;
    unsigned int reg_01_dprx_dpcd_source_hardware_minor_revision: 4;
    unsigned int reg_01_dprx_dpcd_source_hardware_major_revision: 4;
    unsigned int reg_01_dprx_dpcd_source_firmware_software_major_revision: 8;
    unsigned int reg_01_dprx_dpcd_source_firmware_software_minor_revision: 8;
};
#define rx_edp_rx_dpcd_3_reg_01_08(val) ((rs_rx_edp_rx_dpcd_3_reg_01_08*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_20                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_DPCD_3_REG_01_20_struct                                rs_rx_edp_rx_dpcd_3_reg_01_20

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_20  rs_rx_edp_rx_dpcd_3_reg_01_20;
struct _rs_rx_edp_rx_dpcd_3_reg_01_20 {
    unsigned int reg_01_dprx_dpcd_sink_ieee_oui             :24;
    unsigned int reg_01_dprx_dpcd_sink_device_identification_string0: 8;
};
#define rx_edp_rx_dpcd_3_reg_01_20(val) ((rs_rx_edp_rx_dpcd_3_reg_01_20*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_24                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_DPCD_3_REG_01_24_struct                                rs_rx_edp_rx_dpcd_3_reg_01_24

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_24  rs_rx_edp_rx_dpcd_3_reg_01_24;
struct _rs_rx_edp_rx_dpcd_3_reg_01_24 {
    unsigned int reg_01_dprx_dpcd_sink_device_identification_string1:32;
};
#define rx_edp_rx_dpcd_3_reg_01_24(val) ((rs_rx_edp_rx_dpcd_3_reg_01_24*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_28                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_DPCD_3_REG_01_28_struct                                rs_rx_edp_rx_dpcd_3_reg_01_28

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_28  rs_rx_edp_rx_dpcd_3_reg_01_28;
struct _rs_rx_edp_rx_dpcd_3_reg_01_28 {
    unsigned int reg_01_dprx_dpcd_sink_device_identification_string2: 8;
    unsigned int reg_01_dprx_dpcd_sink_hardware_minor_revision: 4;
    unsigned int reg_01_dprx_dpcd_sink_hardware_major_revision: 4;
    unsigned int reg_01_dprx_dpcd_sink_firmware_software_major_revision: 8;
    unsigned int reg_01_dprx_dpcd_sink_firmware_software_minor_revision: 8;
};
#define rx_edp_rx_dpcd_3_reg_01_28(val) ((rs_rx_edp_rx_dpcd_3_reg_01_28*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_40                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_DPCD_3_REG_01_40_struct                                rs_rx_edp_rx_dpcd_3_reg_01_40

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_40  rs_rx_edp_rx_dpcd_3_reg_01_40;
struct _rs_rx_edp_rx_dpcd_3_reg_01_40 {
    unsigned int reg_01_dprx_dpcd_branch_ieee_oui           :24;
    unsigned int reg_01_dprx_dpcd_branch_device_identification_string0: 8;
};
#define rx_edp_rx_dpcd_3_reg_01_40(val) ((rs_rx_edp_rx_dpcd_3_reg_01_40*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_44                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_DPCD_3_REG_01_44_struct                                rs_rx_edp_rx_dpcd_3_reg_01_44

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_44  rs_rx_edp_rx_dpcd_3_reg_01_44;
struct _rs_rx_edp_rx_dpcd_3_reg_01_44 {
    unsigned int reg_01_dprx_dpcd_branch_device_identification_string1:32;
};
#define rx_edp_rx_dpcd_3_reg_01_44(val) ((rs_rx_edp_rx_dpcd_3_reg_01_44*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_48                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_DPCD_3_REG_01_48_struct                                rs_rx_edp_rx_dpcd_3_reg_01_48

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_48  rs_rx_edp_rx_dpcd_3_reg_01_48;
struct _rs_rx_edp_rx_dpcd_3_reg_01_48 {
    unsigned int reg_01_dprx_dpcd_branch_device_identification_string2: 8;
    unsigned int reg_01_dprx_dpcd_branch_hardware_minor_revision: 4;
    unsigned int reg_01_dprx_dpcd_branch_hardware_major_revision: 4;
    unsigned int reg_01_dprx_dpcd_branch_firmware_software_major_revision: 8;
    unsigned int reg_01_dprx_dpcd_branch_firmware_software_minor_revision: 8;
};
#define rx_edp_rx_dpcd_3_reg_01_48(val) ((rs_rx_edp_rx_dpcd_3_reg_01_48*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_60                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_DPCD_3_REG_01_60_struct                                rs_rx_edp_rx_dpcd_3_reg_01_60

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_60  rs_rx_edp_rx_dpcd_3_reg_01_60;
struct _rs_rx_edp_rx_dpcd_3_reg_01_60 {
    unsigned int reg_01_dprx_dpcd_set_power_state           : 3;
    unsigned int reserved                                   : 2;
    unsigned int reg_01_dprx_dpcd_set_dn_device_dp_pwr_5v   : 1;
    unsigned int reg_01_dprx_dpcd_set_dn_device_dp_pwr_12v  : 1;
    unsigned int reg_01_dprx_dpcd_set_dn_device_dp_pwr_18v  : 1;
    unsigned int reserved_1                                 :24;
};
#define rx_edp_rx_dpcd_3_reg_01_60(val) ((rs_rx_edp_rx_dpcd_3_reg_01_60*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_84                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x84)

#define RX_EDP_RX_DPCD_3_REG_01_84_struct                                rs_rx_edp_rx_dpcd_3_reg_01_84

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_84  rs_rx_edp_rx_dpcd_3_reg_01_84;
struct _rs_rx_edp_rx_dpcd_3_reg_01_84 {
    unsigned int reg_01_dprx_dpcd_output_htotal             :16;
    unsigned int reg_01_dprx_dpcd_output_hstart             :16;
};
#define rx_edp_rx_dpcd_3_reg_01_84(val) ((rs_rx_edp_rx_dpcd_3_reg_01_84*)&(val))



#define RX_EDP_RX_DPCD_3_REG_01_88                                       (HV_EDP_RX_DPCD_3_REG_01_BASE_ADDRESS + 0x88)

#define RX_EDP_RX_DPCD_3_REG_01_88_struct                                rs_rx_edp_rx_dpcd_3_reg_01_88

typedef struct _rs_rx_edp_rx_dpcd_3_reg_01_88  rs_rx_edp_rx_dpcd_3_reg_01_88;
struct _rs_rx_edp_rx_dpcd_3_reg_01_88 {
    unsigned int reg_01_dprx_dpcd_output_hsp_hsw            :15;
    unsigned int reg_01_dprx_dpcd_output_hsp                : 1;
    unsigned int reserved                                   :16;
};
#define rx_edp_rx_dpcd_3_reg_01_88(val) ((rs_rx_edp_rx_dpcd_3_reg_01_88*)&(val))



#endif