/**
 * @file hv_cal_PLL.h
 * @brief PHY driver layer interface.
 * @verbatim
 * ==============================================================================
 *                        ##### How to use this driver #####
 * ==============================================================================
 * (+) Use Hv_Cal_PLL_SetRxDpllInit(...) to Init Rx Dpll.
 * (+) Use Hv_Cal_PLL_ConfigRxDpllSel(...) to Select the RX Dpll path.
 * (+) Use Hv_Cal_PLL_SetRxDpllFbdiv(...) to Set the Rx Dpll Fbdiv. 
 *
 * @endverbatim
 *
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 2022-08-22
 */

#ifndef __HV_CAL_PLL_H__
#define __HV_CAL_PLL_H__

#include "hv_comm_DataType.h"
#include "hv_comm_Define.h"


/**
 * @brief initialize sscg.
 */
VOID Hv_Cal_Sscg_Init(VOID);

/**
 * @brief set sscg enable.
 * @param[in] enType: vbo/edp/ddr.  bEnble: on/off
 */
VOID Hv_Cal_Sscg_Enalbe(SscgType enType, BOOL bEnble);

/**
 * @brief set sscg freq.
  * @param[in] enType: vbo/edp/ddr.  uiFreq: modulation frequency: 0-100(k)
 */
VOID Hv_Cal_Sscg_SetSscgFreq(SscgType enType, UCHAR8 ucFreq);

/**
 * @brief set sscg step.
  * @param[in] enType: vbo/edp/ddr.  uiFreq: modulation step: 0-30(0%-3%)
 */
VOID Hv_Cal_Sscg_SetSscgStep(SscgType enType, UCHAR8 ucStep);

/**
 * @brief set sscg spread.
  * @param[in] enType: vbo/edp/ddr.
  * @param[in] ucFreq: vbo/edp/ddr.  uiFreq: modulation frequency: 0-100(k)
  * @param[in] ucStep: vbo/edp/ddr.  uiFreq: modulation step: 0-20(0%-2%)
 */

VOID Hv_Cal_Sscg_SetSscg(SscgType enType, UCHAR8 ucStep, UCHAR8 ucFreq);
/**
 * @brief set sscg mode.
  * @param[in] enType: vbo/edp/ddr.  uiFreq: modulation ucMode: up/down/center
 */
VOID Hv_Cal_Sscg_SetSscgMode(SscgType enType, UCHAR8 ucMode);


Status Hv_Cal_PLL_SetAudioLaneClock(LinkPortIndex enAudioRefPortIndex);

Status Hv_Cal_PLL_RxDpllInit(UCHAR8 ucPortIndex);

Status Hv_Cal_PLL_SetRxDpllFbdiv(ChannelType enChannelCfg, UINT32 uiValue);

Status Hv_Cal_PLL_SetRxDpllPreDiv(ChannelType enChannelCfg, UINT32 uiValue);

Status Hv_Cal_PLL_SetRxDpllPostdivIP(ChannelType enChannelCfg, UINT32 uiValue);

Status Hv_Cal_PLL_SetRxDpllPostdiv0_XIP(ChannelType enChannelCfg, UINT32 uiValue);

Status Hv_Cal_PLL_SetRxDpllFrac(ChannelType enChannelCfg, UINT32 uiValue);

Status Hv_Cal_PLL_ConfigRxDpllSel(UINT32 uiRxPllIndex, LinkPortIndex enReleasePortIndex, LinkPortIndex enBindPortIndex);

Status Hv_Cal_PLL_ConfigRxDpllMuteSel(BOOL bSamePll);

VOID Hv_Cal_DpuScaler_DtcDynamicPllEn(UINT32 uiValue);

BOOL Hv_Cal_DpuScaler_GetDtcDynamicPllEn(VOID);

VOID Hv_Cal_PLL_SetPtcdPllFbdiv(UINT32 uiValue);

VOID Hv_Cal_PLL_SetPtcdpllSscgPllnFrac(UINT32 uiValue);

VOID Hv_Cal_PLL_SetPtcdpllPreDiv(UINT32 uiValue);

VOID Hv_Cal_PLL_SetPtcdpllPostdivD(UINT32 uiValue);

UINT32 Hv_Cal_PLL_GetPtcdpllPostdiv0(VOID);

UINT32 Hv_Cal_PLL_GetDtcFbdivInt(VOID);

UINT32 Hv_Cal_PLL_GetDtcFbdivFrac(VOID);

VOID Hv_Cal_PLL_TogglePtcdUpdate(VOID);

VOID Hv_Cal_PLL_ToggleTxdUpdate(VOID);

VOID Hv_Cal_PLL_PtcdReload(VOID);
VOID Hv_Cal_PLL_PtcdpllInit(VOID);

VOID Hv_Cal_PLL_SysPllInit(VOID);

VOID Hv_Cal_PLL_TxdPllInit(VOID);

VOID Hv_Cal_PLL_AudioPllInit(VOID);

VOID Hv_Cal_PLL_FNPllInit(VOID);

Status Hv_Cal_PLL_CheckRxDpllLock(UCHAR8 ucPortIndex);

Status Hv_Cal_PLL_CheckPtcdPllLock(VOID);

Status Hv_Cal_PLL_CheckSysPllLock(VOID);

Status Hv_Cal_PLL_CheckTxdPllLock(VOID);

Status Hv_Cal_PLL_CheckAudioPllLock(VOID);

Status Hv_Cal_PLL_CheckFNPllLock(VOID);

VOID Hv_Cal_PLL_ResetRxDpll(UCHAR8 ucPortIndex);

VOID Hv_Cal_PLL_ResetPtcdPll(VOID);

VOID Hv_Cal_PLL_ResetSysPll(VOID);

VOID Hv_Cal_PLL_ResetTxdPll(VOID);

VOID Hv_Cal_PLL_ResetFNPll(VOID);

VOID Hv_Cal_PLL_ResetAudioPll(VOID);

UINT32 Hv_Cal_PLL_Ptcd_WaitUntilLock(VOID);

VOID Hv_Cal_PLL_Txd_WaitUntilLock(VOID);

VOID Hv_Cal_PLL_Sys_WaitUntilLock(VOID);

VOID Hv_Cal_PLL_Audio_WaitUntilLock(VOID);

VOID Hv_Cal_PLL_FN_WaitUntilLock(VOID);

VOID Hv_Cal_PLL_RXD_WaitUntilLock(UCHAR8 ucPortIndex);

VOID Hv_Cal_PLL_FN_ClearPllLockFlag(VOID);

VOID Hv_Cal_PLL_FN_ToggleDpuClkCapRst(VOID);
#endif
