#ifndef _HV_PAGE_HT7315_KV_DMA_CTRL_H_
#define _HV_PAGE_HT7315_KV_DMA_CTRL_H_

#ifndef HV_KV_DMA_CTRL_BASE_ADDRESS
    #define HV_KV_DMA_CTRL_BASE_ADDRESS                                         0x11060800
#endif


#define OSD_KV_DMA_CTRL_00                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x00)

#define OSD_KV_DMA_CTRL_00_struct                                        rs_osd_kv_dma_ctrl_00

typedef struct _rs_osd_kv_dma_ctrl_00  rs_osd_kv_dma_ctrl_00;
struct _rs_osd_kv_dma_ctrl_00 {
    unsigned int DMA_RESET                                  : 1;
    unsigned int DMA_START                                  : 1;
    unsigned int reserved                                   :30;
};
#define osd_kv_dma_ctrl_00(val) ((rs_osd_kv_dma_ctrl_00*)&(val))



#define OSD_KV_DMA_CTRL_08                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x08)

#define OSD_KV_DMA_CTRL_08_struct                                        rs_osd_kv_dma_ctrl_08

typedef struct _rs_osd_kv_dma_ctrl_08  rs_osd_kv_dma_ctrl_08;
struct _rs_osd_kv_dma_ctrl_08 {
    unsigned int DMA_READ_NUM                               : 3;
    unsigned int reserved                                   :29;
};
#define osd_kv_dma_ctrl_08(val) ((rs_osd_kv_dma_ctrl_08*)&(val))



#define OSD_KV_DMA_CTRL_10                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x10)

#define OSD_KV_DMA_CTRL_10_struct                                        rs_osd_kv_dma_ctrl_10

typedef struct _rs_osd_kv_dma_ctrl_10  rs_osd_kv_dma_ctrl_10;
struct _rs_osd_kv_dma_ctrl_10 {
    unsigned int DMA_READ0_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_10(val) ((rs_osd_kv_dma_ctrl_10*)&(val))



#define OSD_KV_DMA_CTRL_14                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x14)

#define OSD_KV_DMA_CTRL_14_struct                                        rs_osd_kv_dma_ctrl_14

typedef struct _rs_osd_kv_dma_ctrl_14  rs_osd_kv_dma_ctrl_14;
struct _rs_osd_kv_dma_ctrl_14 {
    unsigned int DMA_READ0_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ0_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_14(val) ((rs_osd_kv_dma_ctrl_14*)&(val))



#define OSD_KV_DMA_CTRL_18                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x18)

#define OSD_KV_DMA_CTRL_18_struct                                        rs_osd_kv_dma_ctrl_18

typedef struct _rs_osd_kv_dma_ctrl_18  rs_osd_kv_dma_ctrl_18;
struct _rs_osd_kv_dma_ctrl_18 {
    unsigned int DMA_READ1_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_18(val) ((rs_osd_kv_dma_ctrl_18*)&(val))



#define OSD_KV_DMA_CTRL_1C                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x1C)

#define OSD_KV_DMA_CTRL_1C_struct                                        rs_osd_kv_dma_ctrl_1c

typedef struct _rs_osd_kv_dma_ctrl_1c  rs_osd_kv_dma_ctrl_1c;
struct _rs_osd_kv_dma_ctrl_1c {
    unsigned int DMA_READ1_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ1_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_1c(val) ((rs_osd_kv_dma_ctrl_1c*)&(val))



#define OSD_KV_DMA_CTRL_20                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x20)

#define OSD_KV_DMA_CTRL_20_struct                                        rs_osd_kv_dma_ctrl_20

typedef struct _rs_osd_kv_dma_ctrl_20  rs_osd_kv_dma_ctrl_20;
struct _rs_osd_kv_dma_ctrl_20 {
    unsigned int DMA_READ2_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_20(val) ((rs_osd_kv_dma_ctrl_20*)&(val))



#define OSD_KV_DMA_CTRL_24                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x24)

#define OSD_KV_DMA_CTRL_24_struct                                        rs_osd_kv_dma_ctrl_24

typedef struct _rs_osd_kv_dma_ctrl_24  rs_osd_kv_dma_ctrl_24;
struct _rs_osd_kv_dma_ctrl_24 {
    unsigned int DMA_READ2_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ2_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_24(val) ((rs_osd_kv_dma_ctrl_24*)&(val))



#define OSD_KV_DMA_CTRL_28                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x28)

#define OSD_KV_DMA_CTRL_28_struct                                        rs_osd_kv_dma_ctrl_28

typedef struct _rs_osd_kv_dma_ctrl_28  rs_osd_kv_dma_ctrl_28;
struct _rs_osd_kv_dma_ctrl_28 {
    unsigned int DMA_READ3_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_28(val) ((rs_osd_kv_dma_ctrl_28*)&(val))



#define OSD_KV_DMA_CTRL_2C                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x2C)

#define OSD_KV_DMA_CTRL_2C_struct                                        rs_osd_kv_dma_ctrl_2c

typedef struct _rs_osd_kv_dma_ctrl_2c  rs_osd_kv_dma_ctrl_2c;
struct _rs_osd_kv_dma_ctrl_2c {
    unsigned int DMA_READ3_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ3_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_2c(val) ((rs_osd_kv_dma_ctrl_2c*)&(val))



#define OSD_KV_DMA_CTRL_30                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x30)

#define OSD_KV_DMA_CTRL_30_struct                                        rs_osd_kv_dma_ctrl_30

typedef struct _rs_osd_kv_dma_ctrl_30  rs_osd_kv_dma_ctrl_30;
struct _rs_osd_kv_dma_ctrl_30 {
    unsigned int DMA_READ4_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_30(val) ((rs_osd_kv_dma_ctrl_30*)&(val))



#define OSD_KV_DMA_CTRL_34                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x34)

#define OSD_KV_DMA_CTRL_34_struct                                        rs_osd_kv_dma_ctrl_34

typedef struct _rs_osd_kv_dma_ctrl_34  rs_osd_kv_dma_ctrl_34;
struct _rs_osd_kv_dma_ctrl_34 {
    unsigned int DMA_READ4_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ4_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_34(val) ((rs_osd_kv_dma_ctrl_34*)&(val))



#define OSD_KV_DMA_CTRL_38                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x38)

#define OSD_KV_DMA_CTRL_38_struct                                        rs_osd_kv_dma_ctrl_38

typedef struct _rs_osd_kv_dma_ctrl_38  rs_osd_kv_dma_ctrl_38;
struct _rs_osd_kv_dma_ctrl_38 {
    unsigned int DMA_READ5_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_38(val) ((rs_osd_kv_dma_ctrl_38*)&(val))



#define OSD_KV_DMA_CTRL_3C                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x3C)

#define OSD_KV_DMA_CTRL_3C_struct                                        rs_osd_kv_dma_ctrl_3c

typedef struct _rs_osd_kv_dma_ctrl_3c  rs_osd_kv_dma_ctrl_3c;
struct _rs_osd_kv_dma_ctrl_3c {
    unsigned int DMA_READ5_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ5_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_3c(val) ((rs_osd_kv_dma_ctrl_3c*)&(val))



#define OSD_KV_DMA_CTRL_40                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x40)

#define OSD_KV_DMA_CTRL_40_struct                                        rs_osd_kv_dma_ctrl_40

typedef struct _rs_osd_kv_dma_ctrl_40  rs_osd_kv_dma_ctrl_40;
struct _rs_osd_kv_dma_ctrl_40 {
    unsigned int DMA_READ6_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_40(val) ((rs_osd_kv_dma_ctrl_40*)&(val))



#define OSD_KV_DMA_CTRL_44                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x44)

#define OSD_KV_DMA_CTRL_44_struct                                        rs_osd_kv_dma_ctrl_44

typedef struct _rs_osd_kv_dma_ctrl_44  rs_osd_kv_dma_ctrl_44;
struct _rs_osd_kv_dma_ctrl_44 {
    unsigned int DMA_READ6_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ6_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_44(val) ((rs_osd_kv_dma_ctrl_44*)&(val))



#define OSD_KV_DMA_CTRL_48                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x48)

#define OSD_KV_DMA_CTRL_48_struct                                        rs_osd_kv_dma_ctrl_48

typedef struct _rs_osd_kv_dma_ctrl_48  rs_osd_kv_dma_ctrl_48;
struct _rs_osd_kv_dma_ctrl_48 {
    unsigned int DMA_READ7_ADDR                             :28;
    unsigned int reserved                                   : 4;
};
#define osd_kv_dma_ctrl_48(val) ((rs_osd_kv_dma_ctrl_48*)&(val))



#define OSD_KV_DMA_CTRL_4C                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x4C)

#define OSD_KV_DMA_CTRL_4C_struct                                        rs_osd_kv_dma_ctrl_4c

typedef struct _rs_osd_kv_dma_ctrl_4c  rs_osd_kv_dma_ctrl_4c;
struct _rs_osd_kv_dma_ctrl_4c {
    unsigned int DMA_READ7_Burst_Num                        :13;
    unsigned int reserved                                   : 3;
    unsigned int DMA_READ7_CTRL                             :13;
    unsigned int reserved_1                                 : 3;
};
#define osd_kv_dma_ctrl_4c(val) ((rs_osd_kv_dma_ctrl_4c*)&(val))



#define OSD_KV_DMA_CTRL_78                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x78)

#define OSD_KV_DMA_CTRL_78_struct                                        rs_osd_kv_dma_ctrl_78

typedef struct _rs_osd_kv_dma_ctrl_78  rs_osd_kv_dma_ctrl_78;
struct _rs_osd_kv_dma_ctrl_78 {
    unsigned int DMA_READ_OPR_COUNTER_CTRL2                 : 1;
    unsigned int DMA_READ_OPR_COUNTER_CTRL1                 : 1;
    unsigned int DMA_READ_BURST_COUNTER_CTRL3               : 1;
    unsigned int DMA_READ_BURST_COUNTER_CTRL2               : 1;
    unsigned int DMA_READ_BURST_COUNTER_CTRL1               : 1;
    unsigned int DMA_READ_COUNTER_CTRL3                     : 1;
    unsigned int DMA_READ_COUNTER_CTRL2                     : 1;
    unsigned int DMA_READ_COUNTER_CTRL1                     : 1;
    unsigned int DMA_WRITE_COUNTER_CTRL3                    : 1;
    unsigned int DMA_WRITE_COUNTER_CTRL2                    : 1;
    unsigned int DMA_WRITE_COUNTER_CTRL1                    : 1;
    unsigned int reserved                                   : 5;
    unsigned int DMA_READ_COUNT_ENABLE                      : 3;
    unsigned int reserved_1                                 : 5;
    unsigned int DMA_READ_DONE_CTRL2                        : 1;
    unsigned int DMA_READ_DONE_CTRL1                        : 1;
    unsigned int DMA_READ_RESET_ERROR_CTRL                  : 1;
    unsigned int DMA_READ_START_ERROR_CTRL                  : 1;
    unsigned int reserved_2                                 : 4;
};
#define osd_kv_dma_ctrl_78(val) ((rs_osd_kv_dma_ctrl_78*)&(val))



#define OSD_KV_DMA_CTRL_7C                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x7C)

#define OSD_KV_DMA_CTRL_7C_struct                                        rs_osd_kv_dma_ctrl_7c

typedef struct _rs_osd_kv_dma_ctrl_7c  rs_osd_kv_dma_ctrl_7c;
struct _rs_osd_kv_dma_ctrl_7c {
    unsigned int DMA_DBG_CTRL2                              : 8;
    unsigned int DMA_DBG_CTRL1                              :24;
};
#define osd_kv_dma_ctrl_7c(val) ((rs_osd_kv_dma_ctrl_7c*)&(val))



#define OSD_KV_DMA_CTRL_80                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x80)

#define OSD_KV_DMA_CTRL_80_struct                                        rs_osd_kv_dma_ctrl_80

typedef struct _rs_osd_kv_dma_ctrl_80  rs_osd_kv_dma_ctrl_80;
struct _rs_osd_kv_dma_ctrl_80 {
    unsigned int RDMA_STATE_FLAG                            : 4;
    unsigned int RDMA_READ_LENGTH_ERR                       : 1;
    unsigned int reserved                                   : 3;
    unsigned int RDMA_CUR_READ_OPR_COUNTER                  : 4;
    unsigned int reserved_1                                 : 4;
    unsigned int DMA_READ_GOING_FLAG                        : 1;
    unsigned int DMA_READ_DONE_FLAG                         : 1;
    unsigned int reserved_2                                 : 2;
    unsigned int DMA_RESET_ERR_FLAG                         : 1;
    unsigned int DMA_START_ERR_FLAG                         : 1;
    unsigned int DMA_READ_COUNTER_ERR_FLAG                  : 1;
    unsigned int reserved_3                                 : 1;
    unsigned int RDMA_TOTAL_READ_OPT_COUNTER                : 8;
};
#define osd_kv_dma_ctrl_80(val) ((rs_osd_kv_dma_ctrl_80*)&(val))



#define OSD_KV_DMA_CTRL_84                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x84)

#define OSD_KV_DMA_CTRL_84_struct                                        rs_osd_kv_dma_ctrl_84

typedef struct _rs_osd_kv_dma_ctrl_84  rs_osd_kv_dma_ctrl_84;
struct _rs_osd_kv_dma_ctrl_84 {
    unsigned int DMA_STATUS1                                :32;
};
#define osd_kv_dma_ctrl_84(val) ((rs_osd_kv_dma_ctrl_84*)&(val))



#define OSD_KV_DMA_CTRL_88                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x88)

#define OSD_KV_DMA_CTRL_88_struct                                        rs_osd_kv_dma_ctrl_88

typedef struct _rs_osd_kv_dma_ctrl_88  rs_osd_kv_dma_ctrl_88;
struct _rs_osd_kv_dma_ctrl_88 {
    unsigned int DMA_STATUS2                                :32;
};
#define osd_kv_dma_ctrl_88(val) ((rs_osd_kv_dma_ctrl_88*)&(val))



#define OSD_KV_DMA_CTRL_8C                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0x8C)

#define OSD_KV_DMA_CTRL_8C_struct                                        rs_osd_kv_dma_ctrl_8c

typedef struct _rs_osd_kv_dma_ctrl_8c  rs_osd_kv_dma_ctrl_8c;
struct _rs_osd_kv_dma_ctrl_8c {
    unsigned int reserved                                   : 1;
    unsigned int DMA_STATUS3                                :31;
};
#define osd_kv_dma_ctrl_8c(val) ((rs_osd_kv_dma_ctrl_8c*)&(val))



#define OSD_KV_DMA_CTRL_A0                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0xA0)

#define OSD_KV_DMA_CTRL_A0_struct                                        rs_osd_kv_dma_ctrl_a0

typedef struct _rs_osd_kv_dma_ctrl_a0  rs_osd_kv_dma_ctrl_a0;
struct _rs_osd_kv_dma_ctrl_a0 {
    unsigned int rdma_int_msk                               :10;
    unsigned int rdma_int_rel                               :10;
    unsigned int rdma_int_sta                               :10;
    unsigned int reserved                                   : 2;
};
#define osd_kv_dma_ctrl_a0(val) ((rs_osd_kv_dma_ctrl_a0*)&(val))



#define OSD_KV_DMA_CTRL_A4                                               (HV_KV_DMA_CTRL_BASE_ADDRESS + 0xA4)

#define OSD_KV_DMA_CTRL_A4_struct                                        rs_osd_kv_dma_ctrl_a4

typedef struct _rs_osd_kv_dma_ctrl_a4  rs_osd_kv_dma_ctrl_a4;
struct _rs_osd_kv_dma_ctrl_a4 {
    unsigned int RDMA_INTR_TRIGGER_MODE                     :30;
    unsigned int reserved                                   : 2;
};
#define osd_kv_dma_ctrl_a4(val) ((rs_osd_kv_dma_ctrl_a4*)&(val))



#endif