#ifndef _HV_PAGE_HT7315_SH01_MISC_H_
#define _HV_PAGE_HT7315_SH01_MISC_H_

#ifndef HV_SH01_MISC_BASE_ADDRESS
    #define HV_SH01_MISC_BASE_ADDRESS                                         0x1101C100
#endif


#define SYS_SH01_MISC_SH1_MISC_04                                        (HV_SH01_MISC_BASE_ADDRESS + 0x10)

#define SYS_SH01_MISC_SH1_MISC_04_struct                                 rs_sys_sh01_misc_sh1_misc_04

typedef struct _rs_sys_sh01_misc_sh1_misc_04  rs_sys_sh01_misc_sh1_misc_04;
struct _rs_sys_sh01_misc_sh1_misc_04 {
    unsigned int reg_phy_bist_start                         : 1;
    unsigned int reg_phy_bist_mux                           : 1;
    unsigned int reg_phy_bist_mode                          : 1;
    unsigned int reg_dft_mux                                : 1;
    unsigned int reg_dft_dfi_init_start                     : 1;
    unsigned int reserved                                   :11;
    unsigned int reg_CSYSREQ_port0                          : 1;
    unsigned int reg_CSYSREQ_port1                          : 1;
    unsigned int reg_CSYSREQ_port2                          : 1;
    unsigned int reg_CSYSREQ_port3                          : 1;
    unsigned int reg_CSYSREQ_port4                          : 1;
    unsigned int reg_CSYSREQ_port5                          : 1;
    unsigned int reg_CSYSREQ_port6                          : 1;
    unsigned int reg_CSYSREQ_port7                          : 1;
    unsigned int reserved_1                                 : 8;
};
#define sys_sh01_misc_sh1_misc_04(val) ((rs_sys_sh01_misc_sh1_misc_04*)&(val))



#define SYS_SH01_MISC_SH1_MISC_05                                        (HV_SH01_MISC_BASE_ADDRESS + 0x14)

#define SYS_SH01_MISC_SH1_MISC_05_struct                                 rs_sys_sh01_misc_sh1_misc_05

typedef struct _rs_sys_sh01_misc_sh1_misc_05  rs_sys_sh01_misc_sh1_misc_05;
struct _rs_sys_sh01_misc_sh1_misc_05 {
    unsigned int reg_bufferen_core                          : 1;
    unsigned int reserved                                   :31;
};
#define sys_sh01_misc_sh1_misc_05(val) ((rs_sys_sh01_misc_sh1_misc_05*)&(val))



#define SYS_SH01_MISC_SH1_MISC_RO_00                                     (HV_SH01_MISC_BASE_ADDRESS + 0xF8)

#define SYS_SH01_MISC_SH1_MISC_RO_00_struct                              rs_sys_sh01_misc_sh1_misc_ro_00

typedef struct _rs_sys_sh01_misc_sh1_misc_ro_00  rs_sys_sh01_misc_sh1_misc_ro_00;
struct _rs_sys_sh01_misc_sh1_misc_ro_00 {
    unsigned int regr_CACTIVE_port0                         : 1;
    unsigned int regr_CACTIVE_port1                         : 1;
    unsigned int regr_CACTIVE_port2                         : 1;
    unsigned int regr_CACTIVE_port3                         : 1;
    unsigned int regr_CACTIVE_port4                         : 1;
    unsigned int regr_CACTIVE_port5                         : 1;
    unsigned int regr_CACTIVE_port6                         : 1;
    unsigned int regr_CACTIVE_port7                         : 1;
    unsigned int regr_CSYSACK_port0                         : 1;
    unsigned int regr_CSYSACK_port1                         : 1;
    unsigned int regr_CSYSACK_port2                         : 1;
    unsigned int regr_CSYSACK_port3                         : 1;
    unsigned int regr_CSYSACK_port4                         : 1;
    unsigned int regr_CSYSACK_port5                         : 1;
    unsigned int regr_CSYSACK_port6                         : 1;
    unsigned int regr_CSYSACK_port7                         : 1;
    unsigned int reserved                                   :16;
};
#define sys_sh01_misc_sh1_misc_ro_00(val) ((rs_sys_sh01_misc_sh1_misc_ro_00*)&(val))



#define SYS_SH01_MISC_SH1_MISC_RO_01                                     (HV_SH01_MISC_BASE_ADDRESS + 0xFC)

#define SYS_SH01_MISC_SH1_MISC_RO_01_struct                              rs_sys_sh01_misc_sh1_misc_ro_01

typedef struct _rs_sys_sh01_misc_sh1_misc_ro_01  rs_sys_sh01_misc_sh1_misc_ro_01;
struct _rs_sys_sh01_misc_sh1_misc_ro_01 {
    unsigned int regr_phy_bist_error                        : 1;
    unsigned int regr_phy_bist_complete                     : 1;
    unsigned int regr_dft_dfi_init_complete                 : 1;
    unsigned int reserved                                   :29;
};
#define sys_sh01_misc_sh1_misc_ro_01(val) ((rs_sys_sh01_misc_sh1_misc_ro_01*)&(val))



#endif