/**
 * @file hv_cal_SubMute.c
 * @brief mute module driver
 * @details This module provide interfaces for Hiview-Madia-Ware.
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20221013
 * @copyright Copyright(c),2022-9, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date             <th>Details
 * <tr><td>HiView SoC Software Team   <td>20221013       <td>Create and first Version.
 * </table>
 **/


#include "hv_cal_SubMute.h"
#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Assert.h"

VOID Hv_Cal_DpuScaler_SetSubMuteClkEn(BOOL bEn)
{
    HV_W32_FIELD(RX_SH12_TOP_01_00, reg_01_sh12_clk_en, bEn);  /*sub mute clk en*/
    return;
}

Status Hv_Cal_DpuScaler_SetSubMuteCompW2Enable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_30, reg_01_mute_comp_w2_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_LDGSubInsertBlackEventInit(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F8, reg_sub_ext_black_insert_enable, uiValue);
    return HV_SUCCESS;
}

#define HV_BLACK_INSERT_SUB_CABLE (BIT_2 | BIT_3 | BIT_4 | BIT_5)
Status Hv_Cal_DpuScaler_LDGSubInsertBlackCableDetect()
{
    HV_R32_DECL_VAR();

    UINT32 uiInserEvent = HV_R32_FIELD(DISP_TOP_SUB_LDG_F8, reg_sub_ext_black_insert_enable);
    UINT32 uiHxrxOutSel = HV_R32_FIELD(RX_HSRX_TOP_00, reg_hsrx_out_sel);

    uiInserEvent &= (~HV_BLACK_INSERT_SUB_CABLE);

    uiHxrxOutSel >>= 4;
    uiHxrxOutSel = uiHxrxOutSel & 0x7;

    if(uiHxrxOutSel < 4)
    {
        uiInserEvent |= (BIT_0 << (2 + uiHxrxOutSel));
        HV_W32_FIELD(DISP_TOP_SUB_LDG_F8, reg_sub_ext_black_insert_enable, uiInserEvent);
    }

    return HV_SUCCESS;
}

void Hv_Cal_DpuScaler_LDGSubReleaseBlack(VOID)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F8, reg_sub_ext_black_insert_sw_clear, (BIT_1 | HV_BLACK_INSERT_SUB_CABLE));
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F8, reg_sub_ext_black_insert_sw_clear, 0);
}
Status Hv_Cal_DpuScaler_SetSubMisc84(UINT32 uiValue)
{
    HV_R32_DECL_VAR();
    UINT32 uiValueMisc = HV_R32(RX_HDMI21_RX_MISC_01_84);

    /*FreeRun Status is Abnormal*/
    if( HV_R32_FIELD(RX_SH12_TOP_01_E0, regr_01_mute_ip_freerun_en_pre) )
    {
        HV_W32(RX_HDMI21_RX_MISC_01_84, (uiValueMisc + uiValue));
    }
    else
    {
        uiValueMisc = HV_R32(RX_HDMI21_RX_MISC_01_88);
        HV_W32(RX_HDMI21_RX_MISC_01_88, (uiValueMisc + uiValue));
    }

    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubSh12MuteInt(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_3C, reg_01_sh12_mute_int, uiValue);

    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHtotal(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_00, reg_01_mute_htotal, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVtotal(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_00, reg_01_mute_vtotal, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHact(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_04, reg_01_mute_hact, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVact(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_08, reg_01_mute_vact, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHactMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_0C, reg_01_mute_hact_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHactMax(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_0C, reg_01_mute_hact_max, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVactMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_10, reg_01_mute_vact_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVactMax(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_10, reg_01_mute_vact_max, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubFrmTrigPos(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_14, reg_01_mute_frm_trig_pos, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubNormOption(VOID)
{
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubForceStable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_18, reg_01_mute_force_stable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHminDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_hmin_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHmaxDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_hmax_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVminDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_vmin_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVmaxDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_vmax_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHttlMaxDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_httl_max_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubSh12ProgSrcStableEn(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_sh12_prog_src_stable_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHtotalMax(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_24, reg_01_mute_htotal_max, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubStateW4Enable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_24, reg_01_mute_state_w4_enable, uiValue);
    return HV_SUCCESS;
}


Status Hv_Cal_DpuScaler_SetMuteSubHtotalMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_5C, reg_01_mute_htotal_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVttlMinDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_28, reg_01_mute_vttl_min_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHttlMinDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_5C, reg_01_mute_httl_min_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHsBporth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_04, reg_01_mute_hs_bporch, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVsBporth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_08, reg_01_mute_vs_bporch, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHsWidth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_08, reg_01_mute_hs_width, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVsWidth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_08, reg_01_mute_vs_width, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubFreerunKeepTime(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_14, reg_01_mute_freerun_keep_time, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubRxLocknDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_18, reg_01_mute_rx_lockn_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubRxDeDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_18, reg_01_mute_rx_de_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHsPos(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_18, reg_01_mute_hs_pos, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVsPos(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_18, reg_01_mute_vs_pos, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubForceFreeRun(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_force_freerun, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubNormPostDelay(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_norm_post_delay, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubFreerun2normThreshold(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_freerun2norm_threshold, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubClkDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_clk_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubInclkUnlockedTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_20, reg_01_inclk_unlocked_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubRxclkStableSel(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_24, reg_01_rxclk_stable_sel, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubInclkNoCkOption(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_24, reg_01_inclk_no_ck_option, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubAntiglitchTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_28, reg_01_mute_antiglitch_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubNoDeEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_28, reg_01_mute_no_de_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHtotalOutMode(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_30, reg_01_mute_htotal_out_mode, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVsMeasureEn(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_30, reg_01_vs_measure_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubNormClrDelay(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_30, reg_01_mute_norm_clr_delay, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHttlMinCompEn(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_58, reg_01_mute_httl_min_comp_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVblankMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_5C, reg_01_mute_vblank_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubInclkFreqLowTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_20, reg_01_inclk_freq_low_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubHactOut(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_2C, reg_01_mute_hact_out, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubVactOut(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_44, reg_01_mute_vact_out, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubInclkFreqHighTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_20, reg_01_inclk_freq_high_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSubNormDelay(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_2C, reg_01_mute_norm_delay, uiValue);
    return HV_SUCCESS;
}

/* no de detection threshold */
Status Hv_Cal_DpuScaler_SetMuteSubNoDeTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_01_40, reg_01_mute_no_de_th, uiValue);
    return HV_SUCCESS;
}

UINT32 Hv_Cal_DpuScaler_GetMuteSubResult(VOID)
{
   HV_R32_DECL_VAR();
   return HV_R32_FIELD(RX_SH12_TOP_01_F4, regr_01_mute_result);
}

UINT32 Hv_Cal_DpuScaler_GetMuteSubState(VOID)
{
   HV_R32_DECL_VAR();
   return HV_R32_FIELD(RX_SH12_TOP_01_F4, regr_01_mute_state);
}

/* readback of clock detection abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubClkAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_clk_abn);
}

/* readback of DE H active minimal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubHdeMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_hde_min_abn);
}

/* readback of DE H active maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubHdeMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_hde_max_abn);
}

/* readback of H total maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubHTotalMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_htotal_max_abn);
}

/* readback of DE V active minimal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVDeMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vde_min_abn);
}

/* readback of DE V active maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVDeMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vde_max_abn);
}

/* readback of V blanking maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVBlkMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vblk_max_abn);
}

/* readback of no DE at all */
UINT32 Hv_Cal_DpuScaler_GetMuteSubNoDe(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_no_de);
}

/* readback of MUTE function enable */
UINT32 Hv_Cal_DpuScaler_GetMuteSubEn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_en);
}

/* readback of vx1 lock abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVx1LockAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vx1_lock_abn);
}

/* readback of vx1 de abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVx1DeAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vx1_de_abn);
}

/* readback of low vs frequency abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVsFreqIsLow(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vs_freq_is_low);
}

/* readback of high vs frequency abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVsFreqIsHigh(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vs_freq_is_high);
}

/* readback of v total minimal abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVttlMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vttl_min_abn);
}

/* readback of vs frequency diff abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVsFreqDiffHigh(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vs_freq_diff_high);
}

/* readback of vs frequency diff abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteSubVsFreqDiffLong(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vs_freq_diff_long);
}

UINT32 Hv_Cal_DpuScaler_GetMuteSubHTotalMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_htotal_min_abn);
}


UINT32 Hv_Cal_DpuScaler_GetMuteSubVBlkMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_vblk_min_abn);
}


UINT32 Hv_Cal_DpuScaler_GetSubMuteStatus(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32(RX_SH12_TOP_01_FC);
}

Status Hv_Cal_DpuScaler_SubMuteClearInsertBlack(VOID)
{
    Hv_Cal_DpuScaler_LDGSubReleaseBlack();

    return HV_SUCCESS;
}

UINT32 Hv_Cal_DpuScaler_GetMuteSubIntReason(VOID)
{
    HV_R32_DECL_VAR();

    return HV_R32_FIELD(RX_SH12_TOP_01_E0, regr_01_mute_ip_freerun_en_pre);
}

Status Hv_Cal_DpuScaler_SubMuteForceFreeRun(BOOL bSwitch)
{
    HV_W32_FIELD(RX_SH12_TOP_01_1C, reg_01_mute_force_freerun, bSwitch);

    return HV_SUCCESS;
}

UINT32 Hv_Cal_DpuScaler_SubGetBalckInsertStatus(ChannelType mutePath)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_SUB_LDG_FC, regr_sub_black_insert_status);
}

VOID Hv_Cal_DpuScaler_SetSubMuteThreahold(VOID)
{
    /* 只有两行错误，不进行异常上报，按照正常处理 */
    HV_W32_FIELD(RX_SH12_TOP_01_58, reg_01_mute_abh_min_int_cnt_th, 2);
    HV_W32_FIELD(RX_SH12_TOP_01_58, reg_01_mute_abh_max_int_cnt_th, 2);
    return;
}

VOID Hv_Cal_DpuScaler_SubClearMuteEn(VOID)
{
    HV_W32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_en, 1);
    HV_W32_FIELD(RX_SH12_TOP_01_FC, regr_01_mute_en, 0);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubSeamlessApplyInEn(BOOL bEn)
{
    HV_W32_FIELD(RX_SH12_TOP_01_64, reg_01_seamless_apply_in, bEn);
    return;
}

