/**
 * @file drv_hdmi_inc.h
 * @brief HDMI RX driver layer interface.
 * @verbatim
 * ==============================================================================
 *                        ##### How to use this driver #####
 * ==============================================================================
 * (+) Use HS_HAL_WDT_Start(...) to start the wdt immediately.
 * (+) Use HS_HAL_WDT_Stop(...) to stop the wdt immediately.
 * (+) Use HS_HAL_WDT_Feed(...) to feed the watchdog and it will restart the counter immediately. 
 * @endverbatim
 *
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 2022-08-22
 */

#ifndef __HV_CAL_HDMIRX_H__
#define __HV_CAL_HDMIRX_H__

#include "Common/hv_comm_DataType.h"
#include "hv_comm_Define.h"

#define HV_HDMIRX_INT_EVENT_MAX_SIZE 30

#define DMAX_CEC_MSG_CACHE_NUM       16
#define DCEC_CMD_CACHE_NUM           16
#define DCEC_NODATA_WAIT_TIME        10

#define DMAX_DDC_MSG_CACHE_NUM                      24

#define HDMI_RX_ORG_CLK_FRQ         27000000


#define HV_HDMIRX_INT_1_EVENT_PLL_CHG               0
#define HV_HDMIRX_INT_1_EVENT_RR_CHG                BIT_1
#define HV_HDMIRX_INT_1_EVENT_RATIO_CHG             BIT_2
#define HV_HDMIRX_INT_1_EVENT_DECODE_ERROR          BIT_4
#define HV_HDMIRX_INT_1_EVENT_PKT_ERR               BIT_8
#define HV_HDMIRX_INT_1_LANE_CLK_STABLE             BIT_9
#define HV_HDMIRX_INT_1_LANE_CLK_UNSTABLE           BIT_10
#define HV_HDMIRX_INT_1_EVENT_FRL_RATE_CHG          BIT_11
#if (HV_PROJECT_CONFIG_FRL)
/* FRL Training Done Interrupt */
#define HV_HDMIRX_INT_1_EVENT_FRL_START_RD          BIT_12
#else
#define HV_HDMIRX_INT_1_EVENT_FRL_START_RD          0
#endif
#define HV_HDMIRX_INT_1_EVENT_TMDS_DESKEW_LOCK      BIT_13
#define HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_OVERFLOW   BIT_19
#define HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_MAX        BIT_20
#define HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_MIN        BIT_21
#define HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_PASS       BIT_22
#define HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_UNDERFLOW  BIT_23
#define HV_HDMIRX_INT_1_EVENT_PD_NEW_ENTRY          BIT_24
#define HV_HDMIRX_INT_1_EVENT_PD_OVER_FLOW          BIT_25
#define HV_HDMIRX_INT_1_EVENT_PD_UNDER_FLOW         BIT_29
#define HV_HDMIRX_INT_1_EVENT_AV_MUTE               BIT_30
#define HV_HDMIRX_INT_1_EVENT_AUDIO_CTS_CHG         BIT_31

#define HV_HDMIRX_INT_1_CHECK  (HV_HDMIRX_INT_1_EVENT_PLL_CHG\
|HV_HDMIRX_INT_1_EVENT_RATIO_CHG\
|HV_HDMIRX_INT_1_EVENT_PKT_ERR\
|HV_HDMIRX_INT_1_LANE_CLK_UNSTABLE\
|HV_HDMIRX_INT_1_EVENT_FRL_RATE_CHG\
|HV_HDMIRX_INT_1_EVENT_FRL_START_RD\
|HV_HDMIRX_INT_1_EVENT_TMDS_DESKEW_LOCK\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_OVERFLOW\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_MAX\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_MIN\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_PASS\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_UNDERFLOW\
|HV_HDMIRX_INT_1_EVENT_AUDIO_CTS_CHG)

#define HV_HDMIRX_INT_1_INIT_OPEN (HV_HDMIRX_INT_1_EVENT_RATIO_CHG\
|HV_HDMIRX_INT_1_EVENT_FRL_RATE_CHG\
|HV_HDMIRX_INT_1_EVENT_FRL_START_RD\
|HV_HDMIRX_INT_1_EVENT_TMDS_DESKEW_LOCK)

#define HV_HDMIRX_INT_1_REDUCE_RPEAT (HV_HDMIRX_INT_1_EVENT_PLL_CHG\
|HV_HDMIRX_INT_1_EVENT_DECODE_ERROR\
|HV_HDMIRX_INT_1_EVENT_PKT_ERR\
|HV_HDMIRX_INT_1_EVENT_FRL_START_RD\
|HV_HDMIRX_INT_1_EVENT_TMDS_DESKEW_LOCK\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_MAX\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_MIN\
|HV_HDMIRX_INT_1_EVENT_AUDIO_FIFO_PASS\
|HV_HDMIRX_INT_1_EVENT_AUDIO_CTS_CHG)

#define HV_HDMIRX_INT_1_HANDLE_IMM (HV_HDMIRX_INT_1_EVENT_RATIO_CHG\
|HV_HDMIRX_INT_1_EVENT_FRL_RATE_CHG\
|HV_HDMIRX_INT_1_EVENT_FRL_START_RD\
|HV_HDMIRX_INT_1_EVENT_TMDS_DESKEW_LOCK\
|HV_HDMIRX_INT_1_EVENT_AV_MUTE)

#define HV_HDMIRX_INT_1_HANDLE_NIN_TASK HV_HDMIRX_INT_1_EVENT_AV_MUTE


//|HV_HDMIRX_INT_1_EVENT_AV_MUTE

#define HV_HDMIRX_INT_2_EVENT_AUDIO_N_CHG           BIT_0
#define HV_HDMIRX_INT_2_EVENT_ACR_RCV               BIT_1
#define HV_HDMIRX_INT_2_EVENT_AIF_CKS_CHG           BIT_2
#define HV_HDMIRX_INT_2_EVENT_AUDIO_TYPE_CHG        BIT_6
#define HV_HDMIRX_INT_2_EVENT_AVI_CKS_CHG           BIT_7
#define HV_HDMIRX_INT_2_EVENT_AVI_RCVED             BIT_8
#define HV_HDMIRX_INT_2_EVENT_DRM_CKS_CHG           BIT_10
#define HV_HDMIRX_INT_2_EVENT_SPD_RCV               BIT_17
#define HV_HDMIRX_INT_2_EVENT_VSI_CKS_CHG           BIT_19
#define HV_HDMIRX_INT_2_EVENT_AUDIO_STABLE          BIT_21
#define HV_HDMIRX_INT_2_EVENT_EMP_RCV               BIT_22
#define HV_HDMIRX_INT_2_EVENT_SPD_CKS_CHG           BIT_23
#define HV_HDMIRX_INT_2_EVENT_TMDS_TIMING_CHG       BIT_24
#define HV_HDMIRX_INT_2_EVENT_TIMING_STABLE         BIT_25
#define HV_HDMIRX_INT_2_EVENT_PHY_CONFIG            BIT_26
#define HV_HDMIRX_INT_2_EVENT_STANDBY_DDC           BIT_27
#define HV_HDMIRX_INT_2_EVENT_LANEFASTLOCK          BIT_28
#define HV_HDMIRX_INT_2_EVENT_DETINTERLACE          BIT_29
#define HV_HDMIRX_INT_2_EVENT_GCP_CD_CHG            BIT_30

#define HV_HDMIRX_INT_2_CHECK (HV_HDMIRX_INT_2_EVENT_AIF_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_AVI_RCVED\
|HV_HDMIRX_INT_2_EVENT_AVI_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_DRM_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_EMP_RCV\
|HV_HDMIRX_INT_2_EVENT_VSI_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_SPD_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_TMDS_TIMING_CHG\
|HV_HDMIRX_INT_2_EVENT_TIMING_STABLE\
|HV_HDMIRX_INT_2_EVENT_PHY_CONFIG\
|HV_HDMIRX_INT_2_EVENT_STANDBY_DDC\
|HV_HDMIRX_INT_2_EVENT_LANEFASTLOCK\
|HV_HDMIRX_INT_2_EVENT_GCP_CD_CHG\
|HV_HDMIRX_INT_2_EVENT_AUDIO_N_CHG\
|HV_HDMIRX_INT_2_EVENT_AUDIO_TYPE_CHG\
|HV_HDMIRX_INT_2_EVENT_ACR_RCV)

#define HV_HDMIRX_INT_2_INIT_OPEN (HV_HDMIRX_INT_2_EVENT_EMP_RCV\
|HV_HDMIRX_INT_2_EVENT_VSI_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_SPD_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_TIMING_STABLE\
|HV_HDMIRX_INT_2_EVENT_STANDBY_DDC\
|HV_HDMIRX_INT_2_EVENT_LANEFASTLOCK)

#define HV_HDMIRX_INT_2_REDUCE_RPEAT (HV_HDMIRX_INT_2_EVENT_AIF_CKS_CHG\
|HV_HDMIRX_INT_2_EVENT_AVI_RCVED\
| HV_HDMIRX_INT_2_EVENT_TMDS_TIMING_CHG \
| HV_HDMIRX_INT_2_EVENT_LANEFASTLOCK \
| HV_HDMIRX_INT_2_EVENT_AUDIO_N_CHG \
| HV_HDMIRX_INT_2_EVENT_AUDIO_TYPE_CHG \
| HV_HDMIRX_INT_2_EVENT_ACR_RCV)

#define HV_HDMIRX_INT_2_HANDLE_IMM (HV_HDMIRX_INT_2_EVENT_PHY_CONFIG\
|HV_HDMIRX_INT_2_EVENT_STANDBY_DDC\
|HV_HDMIRX_INT_2_EVENT_LANEFASTLOCK)

#define HV_HDMIRX_INT_2_HANDLE_NIN_TASK HV_HDMIRX_INT_2_EVENT_STANDBY_DDC

#define HV_HDMI_INT_3_EVENT_START_PULSE             BIT_0
#define HV_HDMI_INT_3_EVENT_RESTART_PULSE           BIT_1
#define HV_HDMI_INT_3_EVENT_STOP_PULSE              BIT_2
#define HV_HDMI_INT_3_EVENT_SLVADDR_VALID           BIT_3
#define HV_HDMI_INT_3_EVENT_WRDATA_VALID            BIT_4
#define HV_HDMI_INT_3_EVENT_READ_REQUEST            BIT_5
#if (HV_PROJECT_CONFIG_EDID_EXTER_EEPROM)
    #define HV_HDMI_INT_3_EVENT_EDID_UPDATE             0
#else
    #if (HV_PROJECT_CONFIG_ESEGMENT == HV_CONFIG_ON)
    #define HV_HDMI_INT_3_EVENT_EDID_UPDATE             BIT_6
    #else
    #define HV_HDMI_INT_3_EVENT_EDID_UPDATE             0
    #endif
#endif
#define HV_HDMI_INT_3_EVENT_CEC_LOSS                BIT_7
#define HV_HDMI_INT_3_EVENT_CEC_RCV                 BIT_8
#define HV_HDMI_INT_3_EVENT_CEC_DONE                BIT_11
#define HV_HDMI_INT_3_EVENT_CEC_WAKE                BIT_13

#define HV_HDMIRX_INT_3_CHECK (HV_HDMI_INT_3_EVENT_WRDATA_VALID\
|HV_HDMI_INT_3_EVENT_READ_REQUEST\
|HV_HDMI_INT_3_EVENT_EDID_UPDATE\
|HV_HDMI_INT_3_EVENT_CEC_RCV)

#define HV_HDMIRX_INT_3_INIT_OPEN (HV_HDMI_INT_3_EVENT_WRDATA_VALID\
|HV_HDMI_INT_3_EVENT_READ_REQUEST\
|HV_HDMI_INT_3_EVENT_EDID_UPDATE\
|HV_HDMI_INT_3_EVENT_CEC_RCV)


/**
 * @brief Status of the Interrupt value on the HDMI RX.
 * @details status of the Status Value of the Interrupt.
 *   The status is used to indicate the detail HW interrupt type.
 */
typedef struct _HdmiRxIntStatus
{
    UINT32      uiIntrruptStatus1;
    UINT32      uiIntrruptStatus2;
    //UINT32      uiIntrruptStatus3;
}HdmiRxIntStatus;

/**
 * @brief Status of the Interrupt on the HDMI RX.
 * @details status of the HDMI Connection and the Status of the Interrupt.
 *   The status is used to indicate the detail HW interrupt type.
 */
typedef struct _HdmiRxInterruptEvent
{
    UCHAR8      ucPortIndex;
    USHORT16    usStbyIntrStatus;
    /*HDMIR RX 中断状态及各事件*/
    HdmiRxIntStatus stHdmiIntRxStatus;

}HdmiRxInterruptEvent;

typedef struct
{
    UCHAR8   ucSize;
    UCHAR8   ucPortIndex;
    USHORT16 usEventList[HV_HDMIRX_INT_EVENT_MAX_SIZE];
}HDMIRxIntEventList;

typedef enum
{
    E_D4LANETMDS                   = 0,
    E_D3LANEFRL                    = 1,
    E_D4LANEFRL                    = 2
}HDMIRxLaneMode;

typedef enum
{
    E_FRL_RATE_TMDS                   = 0,
    E_FRL_RATE_3G3L                   = 1,
    E_FRL_RATE_6G3L                   = 2,
    E_FRL_RATE_6G4L                   = 3,
    E_FRL_RATE_8G4L                   = 4,
    E_FRL_RATE_10G4L                  = 5,
    E_FRL_RATE_12G4L                  = 6,
    E_FRL_RATE_16G4L                  = 7,
    E_FRL_RATE_20G4L                  = 8,
    E_FRL_RATE_24G4L                  = 9,
    E_FRL_RATE_MAX
}HDMIFRLRate;

typedef enum _HdmiRxGearMode
{
    E_LOWGEAR                      = 0,  /* 2 1 10 : min   <------> 650  */
    E_MIDDLEGEAR                   = 1,  /* 1 1 5  : 600M  <------> 1.75G */
    E_HIGHGEAR                     = 2,  /* 0 2 5  : 1.7G  <------>  max */
    E_RATIOGEAR                    = 3,  /* Ratio is configured with TMDS > 340 M */
    E_FRLMODE                      = 4,  /* FRL Mode */
    E_UNLOCKED                     = 5   /* PHY is unlocked */
}HdmiRxGearMode;

/* EMP 目前只需要支持GSYNC的 
 * ucDsType == 0 && Sync == 0 && VFR == 1 && Organization == 1 && usDataSetLength == 4: Class 0 -- 
 *      Gaming VRR and FVA
 * ucDsType == 0 && Sync == 1 && VFR == 1 && Organization == 1 && usDataSetLength == 4: Class 1 -- 
 *      QMS VRR
 */
typedef struct _HdmiRxPacketEMPStru
{
    UCHAR8 ucPacketType;        /* 0x7F */
    UCHAR8 ucFirst : 1;         /* 是否为第一个 */
    UCHAR8 ucLast : 1;          /* 是否为最后一个 */
    UCHAR8 ucReserved : 6;      /* 保留 */
    UCHAR8 ucSequenceIndex;     /* 序号，标识EMP报文的第几个，编号从0开始。 */
    union {
        /*u8SequenceIndex == 0 */
        struct 
        {
            UCHAR8 ucNew : 1;
            UCHAR8 ucEnd : 1;       /* ucDsType == 2 的时候一定需要设置该位为1，表示一帧内完成解析 */
            /* 2Bit, 0 - 3
             *  0: Periodic Pseudo-static EM Data : 周期性的发送，每9帧至少发送一个。例如 CVTEM 就设置为0
             *  1: Periodic dynamic EM Data : 周期性发送，每9帧至少发送一个
             *  2: Unique EM Data : 配合下面的 Sync, Sync = 1表示 EMD 只应用于下一帧显影区
             *  3: Reserved
             */
            UCHAR8 ucDsType : 2;
            UCHAR8 ucAFR : 1;       /* Audio Formate Ralated */
            UCHAR8 ucVFR : 1;       /* Video Formate Ralated */
            UCHAR8 ucSync : 1;      /* 同步matedata */
            UCHAR8 ucRsvd : 1;
            UCHAR8 ucRsvdData;
            UCHAR8 ucOrgnizationId; /* 0:Vendor Specific Em Data, 1: HDMI, 2: CTA-861-H 3: VESA 4-255: Reseved */
            USHORT16 usDataSetTag;
            USHORT16 usDataSetLength;  /* MD 数据长度 , VRR 时候使用 4 */
            UINT32 uiCID;
            union {
                struct
                {
                    UCHAR8 ucFirstMD[17];
                }stCommon;
                /* 10.10.2.4 Class 0 */
                struct 
                {
                    UCHAR8 ucVRREnable : 1;   /* Gaming VRR Enable */
                    UCHAR8 ucClass0Rsv0 : 3;
                    UCHAR8 FVAFactorM1 : 4;   /* 0: FVA Disable Other:FVA Enable */
                    UCHAR8 ucBaseFront;
                    UCHAR8 ucBaseRefreshRateMsb : 2;
                    UCHAR8 ucClass0Rsv1 : 6;
                    UCHAR8 ucBaseRefreshRateLsb;
                }stClass0;
                /* 10.10.2.4 Class 1 */
                struct 
                {
                    UCHAR8 ucClass1Rsv0 : 1;
                    UCHAR8 ucMconst : 1;    /* MVRR is Constant or dithers */
                    UCHAR8 ucQMSEnable : 1; /* QMS VRR Enable */
                    UCHAR8 ucClass1Rsv1 : 1;
                    UCHAR8 ucClass1Rsv2 : 4;
                    UCHAR8 ucBaseFront;
                    UCHAR8 ucBaseRefreshRateMsb : 2;
                    UCHAR8 ucClass1Rsv3 : 1;
                    UCHAR8 ucNextTRF : 4;
                    UCHAR8 ucBaseRefreshRateLsb;
                }stClass1;
            }uVrr;
        }stFirstSet;

        /* u8SequenceIndex != 0 */
        struct
        {
            UCHAR8 ucMD[28];
        }stFirstNotSet;
    } u;
}HdmiRxPacketEMPStru;


#endif

