#ifndef _HV_PAGE_HT7315_HV_HDCP_TOP1_H_
#define _HV_PAGE_HT7315_HV_HDCP_TOP1_H_

#ifndef HV_HV_HDCP_TOP1_BASE_ADDRESS
    #define HV_HV_HDCP_TOP1_BASE_ADDRESS                                         0x1104CE00
#endif


#define RX_HV_HDCP_TOP1_00                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x00)

#define RX_HV_HDCP_TOP1_00_struct                                        rs_rx_hv_hdcp_top1_00

typedef struct _rs_rx_hv_hdcp_top1_00  rs_rx_hv_hdcp_top1_00;
struct _rs_rx_hv_hdcp_top1_00 {
    unsigned int reg_port1_hdcp_en                          : 1;
    unsigned int reg_port1_hdcp_hdmi_dp_sel                 : 1;
    unsigned int regr_port1_rctl1001_total                  :16;
    unsigned int regr_port1_rctl1001_perframe               : 6;
    unsigned int reserved                                   : 1;
    unsigned int reg_port1_hdcp1x2x_video_latch_sel_thr     : 7;
};
#define rx_hv_hdcp_top1_00(val) ((rs_rx_hv_hdcp_top1_00*)&(val))



#define RX_HV_HDCP_TOP1_04                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x04)

#define RX_HV_HDCP_TOP1_04_struct                                        rs_rx_hv_hdcp_top1_04

typedef struct _rs_rx_hv_hdcp_top1_04  rs_rx_hv_hdcp_top1_04;
struct _rs_rx_hv_hdcp_top1_04 {
    unsigned int reg_hdcp_irq_en                            :32;
};
#define rx_hv_hdcp_top1_04(val) ((rs_rx_hv_hdcp_top1_04*)&(val))



#define RX_HV_HDCP_TOP1_08                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x08)

#define RX_HV_HDCP_TOP1_08_struct                                        rs_rx_hv_hdcp_top1_08

typedef struct _rs_rx_hv_hdcp_top1_08  rs_rx_hv_hdcp_top1_08;
struct _rs_rx_hv_hdcp_top1_08 {
    unsigned int reg_hdcp_irq_wclr                          :32;
};
#define rx_hv_hdcp_top1_08(val) ((rs_rx_hv_hdcp_top1_08*)&(val))



#define RX_HV_HDCP_TOP1_10                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x10)

#define RX_HV_HDCP_TOP1_10_struct                                        rs_rx_hv_hdcp_top1_10

typedef struct _rs_rx_hv_hdcp_top1_10  rs_rx_hv_hdcp_top1_10;
struct _rs_rx_hv_hdcp_top1_10 {
    unsigned int regr_hdcp_irq                              :32;
};
#define rx_hv_hdcp_top1_10(val) ((rs_rx_hv_hdcp_top1_10*)&(val))



#define RX_HV_HDCP_TOP1_14                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x14)

#define RX_HV_HDCP_TOP1_14_struct                                        rs_rx_hv_hdcp_top1_14

typedef struct _rs_rx_hv_hdcp_top1_14  rs_rx_hv_hdcp_top1_14;
struct _rs_rx_hv_hdcp_top1_14 {
    unsigned int reg_port1_dp2x_datapath_sel                : 1;
    unsigned int reg_hdcp_dp1_clr                           : 1;
    unsigned int reg_hdcp_dp1_dbg_clr                       : 1;
    unsigned int reg_hdcp_dp1_key_thro                      : 3;
    unsigned int reg_hdcp_dp1_lic_en                        : 1;
    unsigned int reg_hdcp_dp1_mix_en                        : 1;
    unsigned int reg_hdcp_dp1_mst_ecf_swap                  : 1;
    unsigned int reg_hdcp_dp1_1x2x_sel                      : 1;
    unsigned int reg_port1_hdcp_dp1x_mix_clr                : 1;
    unsigned int reg_hdcp_dp1_mix_rdepth                    : 5;
    unsigned int reg_hdcp_dp1_mix_mode_sel                  : 4;
    unsigned int reg_hdcp2x_hdmi1_aes_enc_dly               : 8;
    unsigned int reg_port1_hdcp_dp2x_mix_clr                : 1;
    unsigned int reg_port1_hdcp_dp1x_path_clr               : 1;
    unsigned int reg_port1_hdcp_dp2x_path_clr               : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hv_hdcp_top1_14(val) ((rs_rx_hv_hdcp_top1_14*)&(val))



#define RX_HV_HDCP_TOP1_18                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x18)

#define RX_HV_HDCP_TOP1_18_struct                                        rs_rx_hv_hdcp_top1_18

typedef struct _rs_rx_hv_hdcp_top1_18  rs_rx_hv_hdcp_top1_18;
struct _rs_rx_hv_hdcp_top1_18 {
    unsigned int reg_hdcp_dp1_lic_val                       :16;
    unsigned int reg_hdcp_dp1_mst_ts_bd_thro                :16;
};
#define rx_hv_hdcp_top1_18(val) ((rs_rx_hv_hdcp_top1_18*)&(val))



#define RX_HV_HDCP_TOP1_1C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x1C)

#define RX_HV_HDCP_TOP1_1C_struct                                        rs_rx_hv_hdcp_top1_1c

typedef struct _rs_rx_hv_hdcp_top1_1c  rs_rx_hv_hdcp_top1_1c;
struct _rs_rx_hv_hdcp_top1_1c {
    unsigned int regr_hdcp_dp1_mst_lic                      :16;
    unsigned int regr_hdcp_dp1_sst_lic                      :16;
};
#define rx_hv_hdcp_top1_1c(val) ((rs_rx_hv_hdcp_top1_1c*)&(val))



#define RX_HV_HDCP_TOP1_20                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x20)

#define RX_HV_HDCP_TOP1_20_struct                                        rs_rx_hv_hdcp_top1_20

typedef struct _rs_rx_hv_hdcp_top1_20  rs_rx_hv_hdcp_top1_20;
struct _rs_rx_hv_hdcp_top1_20 {
    unsigned int regr_hdcp_dp1_mix_fk_en                    :16;
    unsigned int regr_hdcp_dp1_mix_rk_en                    :16;
};
#define rx_hv_hdcp_top1_20(val) ((rs_rx_hv_hdcp_top1_20*)&(val))



#define RX_HV_HDCP_TOP1_24                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x24)

#define RX_HV_HDCP_TOP1_24_struct                                        rs_rx_hv_hdcp_top1_24

typedef struct _rs_rx_hv_hdcp_top1_24  rs_rx_hv_hdcp_top1_24;
struct _rs_rx_hv_hdcp_top1_24 {
    unsigned int regr_hdcp_dp1_mix_cp_en                    :16;
    unsigned int regr_port1_enc_en_cnt                      :16;
};
#define rx_hv_hdcp_top1_24(val) ((rs_rx_hv_hdcp_top1_24*)&(val))



#define RX_HV_HDCP_TOP1_28                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x28)

#define RX_HV_HDCP_TOP1_28_struct                                        rs_rx_hv_hdcp_top1_28

typedef struct _rs_rx_hv_hdcp_top1_28  rs_rx_hv_hdcp_top1_28;
struct _rs_rx_hv_hdcp_top1_28 {
    unsigned int reg_hdcp_hdmi1_en_1_1_feat                 : 1;
    unsigned int reg_hdcp1x_hdmi1_start                     : 1;
    unsigned int reg_hdcp2x_hdmi1_start                     : 1;
    unsigned int reg_hdcp1_hdmi1x_decode_mode               : 1;
    unsigned int reg_hdcp_hdmi1_eessoess_qstc               : 2;
    unsigned int reg_hdcp_hdmi1_mode_mx                     : 1;
    unsigned int reg_hdcp_hdmi1_oessctl3_thr_qstc           : 4;
    unsigned int reg_hdcp1x2x_hdmi1_sel                     : 1;
    unsigned int reg_hdcp1x_hdmi1_frame_ki                  : 1;
    unsigned int reg_hdcp1x_hdmi1_frame_ki_sel              : 1;
    unsigned int reg_hdcp1x_hdmi1_vld_fk                    : 6;
    unsigned int reg_hdcp1x_hdmi1_vld_rk                    : 6;
    unsigned int reg_hdcp_hdmi1_eessctl_thr_qstc            : 4;
    unsigned int reg_hdcp_hdmi1_ih2_h14_sel                 : 1;
    unsigned int reg_hdcp_hdmi1_iwoo_cnt_sel                : 1;
};
#define rx_hv_hdcp_top1_28(val) ((rs_rx_hv_hdcp_top1_28*)&(val))



#define RX_HV_HDCP_TOP1_2C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x2C)

#define RX_HV_HDCP_TOP1_2C_struct                                        rs_rx_hv_hdcp_top1_2c

typedef struct _rs_rx_hv_hdcp_top1_2c  rs_rx_hv_hdcp_top1_2c;
struct _rs_rx_hv_hdcp_top1_2c {
    unsigned int reg_hdcp_hdmi1_end_qstc                    :16;
    unsigned int reg_hdcp_hdmi1_start_qstc                  :16;
};
#define rx_hv_hdcp_top1_2c(val) ((rs_rx_hv_hdcp_top1_2c*)&(val))



#define RX_HV_HDCP_TOP1_30                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x30)

#define RX_HV_HDCP_TOP1_30_struct                                        rs_rx_hv_hdcp_top1_30

typedef struct _rs_rx_hv_hdcp_top1_30  rs_rx_hv_hdcp_top1_30;
struct _rs_rx_hv_hdcp_top1_30 {
    unsigned int reg_hdcp1x_hdmi1_rk_dly_cycle              : 5;
    unsigned int reg_hdcp1x_hdmi1_pack_dely_cycle           : 5;
    unsigned int reg_hdcp1x_hdmi1_fk_dly_cycle              : 5;
    unsigned int reg_hdcp1x_hdmi1_fkcpvld_for_fk            : 4;
    unsigned int reg_hdcp1x_hdmi1_rkcpvld_for_rk            : 4;
    unsigned int reg_hdcp1x_hdmi1_vld_for_oth               : 4;
    unsigned int reg_hdcp1x_hdmi1_fk_rk_mode                : 1;
    unsigned int reg_hdcp1x_hdmi1_avmute_disable            : 1;
    unsigned int reg_hdcp1x_hdmi1_rk_vld                    : 1;
    unsigned int reg_hdcp1x_hdmi1_pack_decode_vld           : 1;
    unsigned int reg_hdcp1x_hdmi1_debug_pin_sel_1x2x        : 1;
};
#define rx_hv_hdcp_top1_30(val) ((rs_rx_hv_hdcp_top1_30*)&(val))



#define RX_HV_HDCP_TOP1_34                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x34)

#define RX_HV_HDCP_TOP1_34_struct                                        rs_rx_hv_hdcp_top1_34

typedef struct _rs_rx_hv_hdcp_top1_34  rs_rx_hv_hdcp_top1_34;
struct _rs_rx_hv_hdcp_top1_34 {
    unsigned int reg_port1_hdcp1x_cm_mode_sel               : 8;
    unsigned int reg_port1_hdcp1x_cm_r_upate_cnt            : 8;
    unsigned int regr_port1_hact                            :13;
    unsigned int reg_port1_debug_pin_mode                   : 3;
};
#define rx_hv_hdcp_top1_34(val) ((rs_rx_hv_hdcp_top1_34*)&(val))



#define RX_HV_HDCP_TOP1_38                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x38)

#define RX_HV_HDCP_TOP1_38_struct                                        rs_rx_hv_hdcp_top1_38

typedef struct _rs_rx_hv_hdcp_top1_38  rs_rx_hv_hdcp_top1_38;
struct _rs_rx_hv_hdcp_top1_38 {
    unsigned int reg_port1_hdcp1x_cm_sta                    : 1;
    unsigned int reg_port1_hdcp1x_cm_hw_sta                 : 1;
    unsigned int reg_port1_hdcp1x_cm_fk_win                 :12;
    unsigned int reg_port1_hdcp1x_cm_rk_win                 :12;
    unsigned int reg_port1_hdcp1x_cm_key_sel                : 1;
    unsigned int reg_port1_debug_hdcp1x_ciphercon_pin       : 1;
    unsigned int reg_port1_cipher_key_dly                   : 2;
    unsigned int reg_port1_hdcp_enc_dis_mode                : 1;
    unsigned int reg_port1_hdcp1x_datapath_sfifo_init       : 1;
};
#define rx_hv_hdcp_top1_38(val) ((rs_rx_hv_hdcp_top1_38*)&(val))



#define RX_HV_HDCP_TOP1_3C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x3C)

#define RX_HV_HDCP_TOP1_3C_struct                                        rs_rx_hv_hdcp_top1_3c

typedef struct _rs_rx_hv_hdcp_top1_3c  rs_rx_hv_hdcp_top1_3c;
struct _rs_rx_hv_hdcp_top1_3c {
    unsigned int reg_port1_hdcp1x_cm_an_0                   :32;
};
#define rx_hv_hdcp_top1_3c(val) ((rs_rx_hv_hdcp_top1_3c*)&(val))



#define RX_HV_HDCP_TOP1_40                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x40)

#define RX_HV_HDCP_TOP1_40_struct                                        rs_rx_hv_hdcp_top1_40

typedef struct _rs_rx_hv_hdcp_top1_40  rs_rx_hv_hdcp_top1_40;
struct _rs_rx_hv_hdcp_top1_40 {
    unsigned int reg_port1_hdcp1x_cm_an_1                   :32;
};
#define rx_hv_hdcp_top1_40(val) ((rs_rx_hv_hdcp_top1_40*)&(val))



#define RX_HV_HDCP_TOP1_44                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x44)

#define RX_HV_HDCP_TOP1_44_struct                                        rs_rx_hv_hdcp_top1_44

typedef struct _rs_rx_hv_hdcp_top1_44  rs_rx_hv_hdcp_top1_44;
struct _rs_rx_hv_hdcp_top1_44 {
    unsigned int reg_port1_hdcp1x_cm_km_0                   :32;
};
#define rx_hv_hdcp_top1_44(val) ((rs_rx_hv_hdcp_top1_44*)&(val))



#define RX_HV_HDCP_TOP1_48                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x48)

#define RX_HV_HDCP_TOP1_48_struct                                        rs_rx_hv_hdcp_top1_48

typedef struct _rs_rx_hv_hdcp_top1_48  rs_rx_hv_hdcp_top1_48;
struct _rs_rx_hv_hdcp_top1_48 {
    unsigned int reg_port1_hdcp1x_cm_km_1                   :24;
    unsigned int reg_port1_hdcp1x_cm_rpt                    : 1;
    unsigned int reg_port1_hdcp2x_aesctr_clr                : 1;
    unsigned int reg_port1_hdcp2x_aesctr_hw_sta             : 1;
    unsigned int reg_port1_hdcp_dp_mst_lic_abn_cnt          : 4;
    unsigned int reg_port1_hdcp1x_hdmi_data_path_sel        : 1;
};
#define rx_hv_hdcp_top1_48(val) ((rs_rx_hv_hdcp_top1_48*)&(val))



#define RX_HV_HDCP_TOP1_4C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x4C)

#define RX_HV_HDCP_TOP1_4C_struct                                        rs_rx_hv_hdcp_top1_4c

typedef struct _rs_rx_hv_hdcp_top1_4c  rs_rx_hv_hdcp_top1_4c;
struct _rs_rx_hv_hdcp_top1_4c {
    unsigned int regr_port1_hdcp1x_cm_ks_0                  :32;
};
#define rx_hv_hdcp_top1_4c(val) ((rs_rx_hv_hdcp_top1_4c*)&(val))



#define RX_HV_HDCP_TOP1_50                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x50)

#define RX_HV_HDCP_TOP1_50_struct                                        rs_rx_hv_hdcp_top1_50

typedef struct _rs_rx_hv_hdcp_top1_50  rs_rx_hv_hdcp_top1_50;
struct _rs_rx_hv_hdcp_top1_50 {
    unsigned int regr_port1_hdcp1x_cm_ks_1                  :32;
};
#define rx_hv_hdcp_top1_50(val) ((rs_rx_hv_hdcp_top1_50*)&(val))



#define RX_HV_HDCP_TOP1_54                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x54)

#define RX_HV_HDCP_TOP1_54_struct                                        rs_rx_hv_hdcp_top1_54

typedef struct _rs_rx_hv_hdcp_top1_54  rs_rx_hv_hdcp_top1_54;
struct _rs_rx_hv_hdcp_top1_54 {
    unsigned int regr_port1_hdcp1x_cm_ks_2                  :20;
    unsigned int regr_port1_hdcp1x_cm_st                    : 5;
    unsigned int reg_port1_pack_for_datapath_dly            : 7;
};
#define rx_hv_hdcp_top1_54(val) ((rs_rx_hv_hdcp_top1_54*)&(val))



#define RX_HV_HDCP_TOP1_58                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x58)

#define RX_HV_HDCP_TOP1_58_struct                                        rs_rx_hv_hdcp_top1_58

typedef struct _rs_rx_hv_hdcp_top1_58  rs_rx_hv_hdcp_top1_58;
struct _rs_rx_hv_hdcp_top1_58 {
    unsigned int regr_port1_hdcp1x_cm_m0_0                  :32;
};
#define rx_hv_hdcp_top1_58(val) ((rs_rx_hv_hdcp_top1_58*)&(val))



#define RX_HV_HDCP_TOP1_5C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x5C)

#define RX_HV_HDCP_TOP1_5C_struct                                        rs_rx_hv_hdcp_top1_5c

typedef struct _rs_rx_hv_hdcp_top1_5c  rs_rx_hv_hdcp_top1_5c;
struct _rs_rx_hv_hdcp_top1_5c {
    unsigned int regr_port1_hdcp1x_cm_m0_1                  :32;
};
#define rx_hv_hdcp_top1_5c(val) ((rs_rx_hv_hdcp_top1_5c*)&(val))



#define RX_HV_HDCP_TOP1_60                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x60)

#define RX_HV_HDCP_TOP1_60_struct                                        rs_rx_hv_hdcp_top1_60

typedef struct _rs_rx_hv_hdcp_top1_60  rs_rx_hv_hdcp_top1_60;
struct _rs_rx_hv_hdcp_top1_60 {
    unsigned int regr_port1_hdcp1x_cm_r0                    :16;
    unsigned int regr_port1_hdcp1x_cm_fk                    : 8;
    unsigned int regr_port1_hdcp1x_cm_rk                    : 8;
};
#define rx_hv_hdcp_top1_60(val) ((rs_rx_hv_hdcp_top1_60*)&(val))



#define RX_HV_HDCP_TOP1_64                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x64)

#define RX_HV_HDCP_TOP1_64_struct                                        rs_rx_hv_hdcp_top1_64

typedef struct _rs_rx_hv_hdcp_top1_64  rs_rx_hv_hdcp_top1_64;
struct _rs_rx_hv_hdcp_top1_64 {
    unsigned int regr_port1_hsrx_cursor_bd_h2               :32;
};
#define rx_hv_hdcp_top1_64(val) ((rs_rx_hv_hdcp_top1_64*)&(val))



#define RX_HV_HDCP_TOP1_68                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x68)

#define RX_HV_HDCP_TOP1_68_struct                                        rs_rx_hv_hdcp_top1_68

typedef struct _rs_rx_hv_hdcp_top1_68  rs_rx_hv_hdcp_top1_68;
struct _rs_rx_hv_hdcp_top1_68 {
    unsigned int reg_port1_hdcp2x_aesctr_ks_0               :32;
};
#define rx_hv_hdcp_top1_68(val) ((rs_rx_hv_hdcp_top1_68*)&(val))



#define RX_HV_HDCP_TOP1_6C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x6C)

#define RX_HV_HDCP_TOP1_6C_struct                                        rs_rx_hv_hdcp_top1_6c

typedef struct _rs_rx_hv_hdcp_top1_6c  rs_rx_hv_hdcp_top1_6c;
struct _rs_rx_hv_hdcp_top1_6c {
    unsigned int reg_port1_hdcp2x_aesctr_ks_1               :32;
};
#define rx_hv_hdcp_top1_6c(val) ((rs_rx_hv_hdcp_top1_6c*)&(val))



#define RX_HV_HDCP_TOP1_70                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x70)

#define RX_HV_HDCP_TOP1_70_struct                                        rs_rx_hv_hdcp_top1_70

typedef struct _rs_rx_hv_hdcp_top1_70  rs_rx_hv_hdcp_top1_70;
struct _rs_rx_hv_hdcp_top1_70 {
    unsigned int reg_port1_hdcp2x_aesctr_ks_2               :32;
};
#define rx_hv_hdcp_top1_70(val) ((rs_rx_hv_hdcp_top1_70*)&(val))



#define RX_HV_HDCP_TOP1_74                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x74)

#define RX_HV_HDCP_TOP1_74_struct                                        rs_rx_hv_hdcp_top1_74

typedef struct _rs_rx_hv_hdcp_top1_74  rs_rx_hv_hdcp_top1_74;
struct _rs_rx_hv_hdcp_top1_74 {
    unsigned int reg_port1_hdcp2x_aesctr_ks_3               :32;
};
#define rx_hv_hdcp_top1_74(val) ((rs_rx_hv_hdcp_top1_74*)&(val))



#define RX_HV_HDCP_TOP1_78                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x78)

#define RX_HV_HDCP_TOP1_78_struct                                        rs_rx_hv_hdcp_top1_78

typedef struct _rs_rx_hv_hdcp_top1_78  rs_rx_hv_hdcp_top1_78;
struct _rs_rx_hv_hdcp_top1_78 {
    unsigned int reg_port1_hdcp2x_aesctr_lc128_0            :32;
};
#define rx_hv_hdcp_top1_78(val) ((rs_rx_hv_hdcp_top1_78*)&(val))



#define RX_HV_HDCP_TOP1_7C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x7C)

#define RX_HV_HDCP_TOP1_7C_struct                                        rs_rx_hv_hdcp_top1_7c

typedef struct _rs_rx_hv_hdcp_top1_7c  rs_rx_hv_hdcp_top1_7c;
struct _rs_rx_hv_hdcp_top1_7c {
    unsigned int reg_port1_hdcp2x_aesctr_lc128_1            :32;
};
#define rx_hv_hdcp_top1_7c(val) ((rs_rx_hv_hdcp_top1_7c*)&(val))



#define RX_HV_HDCP_TOP1_80                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x80)

#define RX_HV_HDCP_TOP1_80_struct                                        rs_rx_hv_hdcp_top1_80

typedef struct _rs_rx_hv_hdcp_top1_80  rs_rx_hv_hdcp_top1_80;
struct _rs_rx_hv_hdcp_top1_80 {
    unsigned int reg_port1_hdcp2x_aesctr_lc128_2            :32;
};
#define rx_hv_hdcp_top1_80(val) ((rs_rx_hv_hdcp_top1_80*)&(val))



#define RX_HV_HDCP_TOP1_84                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x84)

#define RX_HV_HDCP_TOP1_84_struct                                        rs_rx_hv_hdcp_top1_84

typedef struct _rs_rx_hv_hdcp_top1_84  rs_rx_hv_hdcp_top1_84;
struct _rs_rx_hv_hdcp_top1_84 {
    unsigned int reg_port1_hdcp2x_aesctr_lc128_3            :32;
};
#define rx_hv_hdcp_top1_84(val) ((rs_rx_hv_hdcp_top1_84*)&(val))



#define RX_HV_HDCP_TOP1_88                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x88)

#define RX_HV_HDCP_TOP1_88_struct                                        rs_rx_hv_hdcp_top1_88

typedef struct _rs_rx_hv_hdcp_top1_88  rs_rx_hv_hdcp_top1_88;
struct _rs_rx_hv_hdcp_top1_88 {
    unsigned int reg_port1_hdcp2x_aesctr_riv_0              :32;
};
#define rx_hv_hdcp_top1_88(val) ((rs_rx_hv_hdcp_top1_88*)&(val))



#define RX_HV_HDCP_TOP1_8C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x8C)

#define RX_HV_HDCP_TOP1_8C_struct                                        rs_rx_hv_hdcp_top1_8c

typedef struct _rs_rx_hv_hdcp_top1_8c  rs_rx_hv_hdcp_top1_8c;
struct _rs_rx_hv_hdcp_top1_8c {
    unsigned int reg_port1_hdcp2x_aesctr_riv_1              :32;
};
#define rx_hv_hdcp_top1_8c(val) ((rs_rx_hv_hdcp_top1_8c*)&(val))



#define RX_HV_HDCP_TOP1_90                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x90)

#define RX_HV_HDCP_TOP1_90_struct                                        rs_rx_hv_hdcp_top1_90

typedef struct _rs_rx_hv_hdcp_top1_90  rs_rx_hv_hdcp_top1_90;
struct _rs_rx_hv_hdcp_top1_90 {
    unsigned int regr_port1_hdcp2x_aesctr_ks_0              :32;
};
#define rx_hv_hdcp_top1_90(val) ((rs_rx_hv_hdcp_top1_90*)&(val))



#define RX_HV_HDCP_TOP1_94                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x94)

#define RX_HV_HDCP_TOP1_94_struct                                        rs_rx_hv_hdcp_top1_94

typedef struct _rs_rx_hv_hdcp_top1_94  rs_rx_hv_hdcp_top1_94;
struct _rs_rx_hv_hdcp_top1_94 {
    unsigned int regr_port1_hdcp2x_aesctr_ks_1              :32;
};
#define rx_hv_hdcp_top1_94(val) ((rs_rx_hv_hdcp_top1_94*)&(val))



#define RX_HV_HDCP_TOP1_98                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x98)

#define RX_HV_HDCP_TOP1_98_struct                                        rs_rx_hv_hdcp_top1_98

typedef struct _rs_rx_hv_hdcp_top1_98  rs_rx_hv_hdcp_top1_98;
struct _rs_rx_hv_hdcp_top1_98 {
    unsigned int regr_port1_hdcp2x_aesctr_ks_2              :32;
};
#define rx_hv_hdcp_top1_98(val) ((rs_rx_hv_hdcp_top1_98*)&(val))



#define RX_HV_HDCP_TOP1_9C                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0x9C)

#define RX_HV_HDCP_TOP1_9C_struct                                        rs_rx_hv_hdcp_top1_9c

typedef struct _rs_rx_hv_hdcp_top1_9c  rs_rx_hv_hdcp_top1_9c;
struct _rs_rx_hv_hdcp_top1_9c {
    unsigned int regr_port1_hdcp2x_aesctr_ks_3              :32;
};
#define rx_hv_hdcp_top1_9c(val) ((rs_rx_hv_hdcp_top1_9c*)&(val))



#define RX_HV_HDCP_TOP1_A0                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xA0)

#define RX_HV_HDCP_TOP1_A0_struct                                        rs_rx_hv_hdcp_top1_a0

typedef struct _rs_rx_hv_hdcp_top1_a0  rs_rx_hv_hdcp_top1_a0;
struct _rs_rx_hv_hdcp_top1_a0 {
    unsigned int regr_hdmi1_decode_ctl                      :14;
    unsigned int regr_hdmi1_decrypt_on                      : 1;
    unsigned int regr_hdmi1_oeess_oess                      : 1;
    unsigned int reg_port1_timing_for_hact                  :12;
    unsigned int reg_port1_hdcp_dp_sst_lic_abn_cnt          : 4;
};
#define rx_hv_hdcp_top1_a0(val) ((rs_rx_hv_hdcp_top1_a0*)&(val))



#define RX_HV_HDCP_TOP1_A4                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xA4)

#define RX_HV_HDCP_TOP1_A4_struct                                        rs_rx_hv_hdcp_top1_a4

typedef struct _rs_rx_hv_hdcp_top1_a4  rs_rx_hv_hdcp_top1_a4;
struct _rs_rx_hv_hdcp_top1_a4 {
    unsigned int regr_hdcp2x_port1_okey_counter_l           :32;
};
#define rx_hv_hdcp_top1_a4(val) ((rs_rx_hv_hdcp_top1_a4*)&(val))



#define RX_HV_HDCP_TOP1_A8                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xA8)

#define RX_HV_HDCP_TOP1_A8_struct                                        rs_rx_hv_hdcp_top1_a8

typedef struct _rs_rx_hv_hdcp_top1_a8  rs_rx_hv_hdcp_top1_a8;
struct _rs_rx_hv_hdcp_top1_a8 {
    unsigned int reg_port1_dp2x_mix_rdepth                  : 6;
    unsigned int reserved                                   :26;
};
#define rx_hv_hdcp_top1_a8(val) ((rs_rx_hv_hdcp_top1_a8*)&(val))



#define RX_HV_HDCP_TOP1_AC                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xAC)

#define RX_HV_HDCP_TOP1_AC_struct                                        rs_rx_hv_hdcp_top1_ac

typedef struct _rs_rx_hv_hdcp_top1_ac  rs_rx_hv_hdcp_top1_ac;
struct _rs_rx_hv_hdcp_top1_ac {
    unsigned int reg_port1_hsrx_cursor_color                : 3;
    unsigned int reg_port1_hsrx_cursor_en                   : 1;
    unsigned int reg_port1_hsrx_cursor_hcnt                 :13;
    unsigned int reg_port1_hsrx_cursor_hstep                : 6;
    unsigned int reg_port1_hsrx_cursor_hwidth               : 4;
    unsigned int reg_port1_hsrx_cursor_step_en              : 1;
    unsigned int reg_port1_hsrx_cursor_vwidth               : 4;
};
#define rx_hv_hdcp_top1_ac(val) ((rs_rx_hv_hdcp_top1_ac*)&(val))



#define RX_HV_HDCP_TOP1_B0                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xB0)

#define RX_HV_HDCP_TOP1_B0_struct                                        rs_rx_hv_hdcp_top1_b0

typedef struct _rs_rx_hv_hdcp_top1_b0  rs_rx_hv_hdcp_top1_b0;
struct _rs_rx_hv_hdcp_top1_b0 {
    unsigned int reg_port1_hsrx_cursor_scan_cnt             :11;
    unsigned int reg_port1_hsrx_cursor_vcnt                 :13;
    unsigned int reg_port1_hsrx_cursor_vstep                : 6;
    unsigned int reg_port1_hdcp_hdmi_1x2x_sel_mode          : 2;
};
#define rx_hv_hdcp_top1_b0(val) ((rs_rx_hv_hdcp_top1_b0*)&(val))



#define RX_HV_HDCP_TOP1_B4                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xB4)

#define RX_HV_HDCP_TOP1_B4_struct                                        rs_rx_hv_hdcp_top1_b4

typedef struct _rs_rx_hv_hdcp_top1_b4  rs_rx_hv_hdcp_top1_b4;
struct _rs_rx_hv_hdcp_top1_b4 {
    unsigned int regr_hdmi1_decode_video_data0              :24;
    unsigned int regr_hdcp2x_hdmi1_fsm_state                : 3;
    unsigned int reg_port1_hdcp1x_datapath_sfifo_no_rd_thd  : 5;
};
#define rx_hv_hdcp_top1_b4(val) ((rs_rx_hv_hdcp_top1_b4*)&(val))



#define RX_HV_HDCP_TOP1_B8                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xB8)

#define RX_HV_HDCP_TOP1_B8_struct                                        rs_rx_hv_hdcp_top1_b8

typedef struct _rs_rx_hv_hdcp_top1_b8  rs_rx_hv_hdcp_top1_b8;
struct _rs_rx_hv_hdcp_top1_b8 {
    unsigned int regr_hdmi1_decode_video_data1              :24;
    unsigned int reg_port1_hdcp2x_aesctr_type               : 8;
};
#define rx_hv_hdcp_top1_b8(val) ((rs_rx_hv_hdcp_top1_b8*)&(val))



#define RX_HV_HDCP_TOP1_BC                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xBC)

#define RX_HV_HDCP_TOP1_BC_struct                                        rs_rx_hv_hdcp_top1_bc

typedef struct _rs_rx_hv_hdcp_top1_bc  rs_rx_hv_hdcp_top1_bc;
struct _rs_rx_hv_hdcp_top1_bc {
    unsigned int regr_hdmi1_decode_video_data2              :24;
    unsigned int reg_port1_hdcp1x_load_ri_thr               : 8;
};
#define rx_hv_hdcp_top1_bc(val) ((rs_rx_hv_hdcp_top1_bc*)&(val))



#define RX_HV_HDCP_TOP1_C0                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xC0)

#define RX_HV_HDCP_TOP1_C0_struct                                        rs_rx_hv_hdcp_top1_c0

typedef struct _rs_rx_hv_hdcp_top1_c0  rs_rx_hv_hdcp_top1_c0;
struct _rs_rx_hv_hdcp_top1_c0 {
    unsigned int regr_hdmi1_decode_video_data3              :24;
    unsigned int regr_port1_rctl0001_perframe               : 6;
    unsigned int reserved                                   : 2;
};
#define rx_hv_hdcp_top1_c0(val) ((rs_rx_hv_hdcp_top1_c0*)&(val))



#define RX_HV_HDCP_TOP1_C4                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xC4)

#define RX_HV_HDCP_TOP1_C4_struct                                        rs_rx_hv_hdcp_top1_c4

typedef struct _rs_rx_hv_hdcp_top1_c4  rs_rx_hv_hdcp_top1_c4;
struct _rs_rx_hv_hdcp_top1_c4 {
    unsigned int regr_port1_hsrx_cursor_bd_h1               :32;
};
#define rx_hv_hdcp_top1_c4(val) ((rs_rx_hv_hdcp_top1_c4*)&(val))



#define RX_HV_HDCP_TOP1_C8                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xC8)

#define RX_HV_HDCP_TOP1_C8_struct                                        rs_rx_hv_hdcp_top1_c8

typedef struct _rs_rx_hv_hdcp_top1_c8  rs_rx_hv_hdcp_top1_c8;
struct _rs_rx_hv_hdcp_top1_c8 {
    unsigned int regr_port1_hsrx_cursor_bd_h0               :32;
};
#define rx_hv_hdcp_top1_c8(val) ((rs_rx_hv_hdcp_top1_c8*)&(val))



#define RX_HV_HDCP_TOP1_CC                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xCC)

#define RX_HV_HDCP_TOP1_CC_struct                                        rs_rx_hv_hdcp_top1_cc

typedef struct _rs_rx_hv_hdcp_top1_cc  rs_rx_hv_hdcp_top1_cc;
struct _rs_rx_hv_hdcp_top1_cc {
    unsigned int regr_port1_hsrx_cursor_fd_h2               :32;
};
#define rx_hv_hdcp_top1_cc(val) ((rs_rx_hv_hdcp_top1_cc*)&(val))



#define RX_HV_HDCP_TOP1_D0                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xD0)

#define RX_HV_HDCP_TOP1_D0_struct                                        rs_rx_hv_hdcp_top1_d0

typedef struct _rs_rx_hv_hdcp_top1_d0  rs_rx_hv_hdcp_top1_d0;
struct _rs_rx_hv_hdcp_top1_d0 {
    unsigned int regr_port1_hsrx_cursor_fd_h1               :32;
};
#define rx_hv_hdcp_top1_d0(val) ((rs_rx_hv_hdcp_top1_d0*)&(val))



#define RX_HV_HDCP_TOP1_D4                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xD4)

#define RX_HV_HDCP_TOP1_D4_struct                                        rs_rx_hv_hdcp_top1_d4

typedef struct _rs_rx_hv_hdcp_top1_d4  rs_rx_hv_hdcp_top1_d4;
struct _rs_rx_hv_hdcp_top1_d4 {
    unsigned int regr_hdmi1_org_video_data0                 :24;
    unsigned int regr_port1_rctl0001_total                  : 8;
};
#define rx_hv_hdcp_top1_d4(val) ((rs_rx_hv_hdcp_top1_d4*)&(val))



#define RX_HV_HDCP_TOP1_D8                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xD8)

#define RX_HV_HDCP_TOP1_D8_struct                                        rs_rx_hv_hdcp_top1_d8

typedef struct _rs_rx_hv_hdcp_top1_d8  rs_rx_hv_hdcp_top1_d8;
struct _rs_rx_hv_hdcp_top1_d8 {
    unsigned int regr_hdmi1_org_video_data1                 :24;
    unsigned int regr_port1_packde_videode_cnt_orj          : 8;
};
#define rx_hv_hdcp_top1_d8(val) ((rs_rx_hv_hdcp_top1_d8*)&(val))



#define RX_HV_HDCP_TOP1_DC                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xDC)

#define RX_HV_HDCP_TOP1_DC_struct                                        rs_rx_hv_hdcp_top1_dc

typedef struct _rs_rx_hv_hdcp_top1_dc  rs_rx_hv_hdcp_top1_dc;
struct _rs_rx_hv_hdcp_top1_dc {
    unsigned int regr_hdmi1_org_video_data2                 :24;
    unsigned int regr_port1_packde_videode_cnt_remap        : 8;
};
#define rx_hv_hdcp_top1_dc(val) ((rs_rx_hv_hdcp_top1_dc*)&(val))



#define RX_HV_HDCP_TOP1_E0                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xE0)

#define RX_HV_HDCP_TOP1_E0_struct                                        rs_rx_hv_hdcp_top1_e0

typedef struct _rs_rx_hv_hdcp_top1_e0  rs_rx_hv_hdcp_top1_e0;
struct _rs_rx_hv_hdcp_top1_e0 {
    unsigned int regr_hdmi1_org_video_data3                 :24;
    unsigned int regr_port1_hblank_debug                    : 8;
};
#define rx_hv_hdcp_top1_e0(val) ((rs_rx_hv_hdcp_top1_e0*)&(val))



#define RX_HV_HDCP_TOP1_E4                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xE4)

#define RX_HV_HDCP_TOP1_E4_struct                                        rs_rx_hv_hdcp_top1_e4

typedef struct _rs_rx_hv_hdcp_top1_e4  rs_rx_hv_hdcp_top1_e4;
struct _rs_rx_hv_hdcp_top1_e4 {
    unsigned int regr_hdcp_hdmi1_firstpix_data_0            :24;
    unsigned int regr_port1_hblank_packfull                 : 8;
};
#define rx_hv_hdcp_top1_e4(val) ((rs_rx_hv_hdcp_top1_e4*)&(val))



#define RX_HV_HDCP_TOP1_E8                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xE8)

#define RX_HV_HDCP_TOP1_E8_struct                                        rs_rx_hv_hdcp_top1_e8

typedef struct _rs_rx_hv_hdcp_top1_e8  rs_rx_hv_hdcp_top1_e8;
struct _rs_rx_hv_hdcp_top1_e8 {
    unsigned int regr_hdcp_hdmi1_firstpix_data_1            :24;
    unsigned int regr_port1_hblank_videofail2packrise       : 8;
};
#define rx_hv_hdcp_top1_e8(val) ((rs_rx_hv_hdcp_top1_e8*)&(val))



#define RX_HV_HDCP_TOP1_EC                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xEC)

#define RX_HV_HDCP_TOP1_EC_struct                                        rs_rx_hv_hdcp_top1_ec

typedef struct _rs_rx_hv_hdcp_top1_ec  rs_rx_hv_hdcp_top1_ec;
struct _rs_rx_hv_hdcp_top1_ec {
    unsigned int regr_hdcp_hdmi1_firstpix_data_2            :24;
    unsigned int regr_port1_enc_dis_cnt                     : 8;
};
#define rx_hv_hdcp_top1_ec(val) ((rs_rx_hv_hdcp_top1_ec*)&(val))



#define RX_HV_HDCP_TOP1_F0                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xF0)

#define RX_HV_HDCP_TOP1_F0_struct                                        rs_rx_hv_hdcp_top1_f0

typedef struct _rs_rx_hv_hdcp_top1_f0  rs_rx_hv_hdcp_top1_f0;
struct _rs_rx_hv_hdcp_top1_f0 {
    unsigned int regr_hdcp_hdmi1_firstpix_data_3            :24;
    unsigned int regr_port1_hblank_packfail2videorise       : 6;
    unsigned int reserved                                   : 2;
};
#define rx_hv_hdcp_top1_f0(val) ((rs_rx_hv_hdcp_top1_f0*)&(val))



#define RX_HV_HDCP_TOP1_F4                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xF4)

#define RX_HV_HDCP_TOP1_F4_struct                                        rs_rx_hv_hdcp_top1_f4

typedef struct _rs_rx_hv_hdcp_top1_f4  rs_rx_hv_hdcp_top1_f4;
struct _rs_rx_hv_hdcp_top1_f4 {
    unsigned int regr_port1_load_ri_cnt                     :16;
    unsigned int regr_hdcp1x_hdmi1_frameki_updata           :16;
};
#define rx_hv_hdcp_top1_f4(val) ((rs_rx_hv_hdcp_top1_f4*)&(val))



#define RX_HV_HDCP_TOP1_F8                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xF8)

#define RX_HV_HDCP_TOP1_F8_struct                                        rs_rx_hv_hdcp_top1_f8

typedef struct _rs_rx_hv_hdcp_top1_f8  rs_rx_hv_hdcp_top1_f8;
struct _rs_rx_hv_hdcp_top1_f8 {
    unsigned int regr_hdcp1x_hdmi1_fk_updata                :16;
    unsigned int regr_hdcp1x_hdmi1_rk_updata                :16;
};
#define rx_hv_hdcp_top1_f8(val) ((rs_rx_hv_hdcp_top1_f8*)&(val))



#define RX_HV_HDCP_TOP1_FC                                               (HV_HV_HDCP_TOP1_BASE_ADDRESS + 0xFC)

#define RX_HV_HDCP_TOP1_FC_struct                                        rs_rx_hv_hdcp_top1_fc

typedef struct _rs_rx_hv_hdcp_top1_fc  rs_rx_hv_hdcp_top1_fc;
struct _rs_rx_hv_hdcp_top1_fc {
    unsigned int regr_port1_hsrx_cursor_fd_h0               :32;
};
#define rx_hv_hdcp_top1_fc(val) ((rs_rx_hv_hdcp_top1_fc*)&(val))



#endif