#ifndef _HV_PAGE_HT7315_KV_DIMMER_CTRL_REG3_H_
#define _HV_PAGE_HT7315_KV_DIMMER_CTRL_REG3_H_

#ifndef HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS
    #define HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS                                         0x11045C00
#endif


#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_00                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x00)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_00_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_00

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_00  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_00;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_00 {
    unsigned int reg_dim_cmd_vaule0_00                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_00(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_00*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_00                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x04)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_00_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_00

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_00  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_00;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_00 {
    unsigned int reg_dim_cmd_vaule1_00                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_00(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_00*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_00                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x08)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_00_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_00

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_00  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_00;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_00 {
    unsigned int reg_dim_cmd_vaule2_00                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_00(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_00*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__00                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x0C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__00_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__00

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__00  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__00;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__00 {
    unsigned int reg_dim_cmd_vaule3_00                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__00(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__00*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_01                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x10)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_01_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_01

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_01  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_01;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_01 {
    unsigned int reg_dim_cmd_vaule0_01                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_01(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_01*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_01                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x14)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_01_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_01

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_01  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_01;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_01 {
    unsigned int reg_dim_cmd_vaule1_01                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_01(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_01*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_01                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x18)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_01_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_01

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_01  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_01;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_01 {
    unsigned int reg_dim_cmd_vaule2_01                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_01(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_01*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__01                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x1C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__01_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__01

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__01  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__01;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__01 {
    unsigned int reg_dim_cmd_vaule3_01                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__01(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__01*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_02                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x20)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_02_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_02

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_02  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_02;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_02 {
    unsigned int reg_dim_cmd_vaule0_02                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_02(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_02*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_02                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x24)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_02_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_02

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_02  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_02;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_02 {
    unsigned int reg_dim_cmd_vaule1_02                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_02(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_02*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_02                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x28)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_02_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_02

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_02  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_02;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_02 {
    unsigned int reg_dim_cmd_vaule2_02                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_02(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_02*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__02                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x2C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__02_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__02

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__02  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__02;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__02 {
    unsigned int reg_dim_cmd_vaule3_02                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__02(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__02*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_03                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x30)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_03_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_03

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_03  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_03;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_03 {
    unsigned int reg_dim_cmd_vaule0_03                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_03(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_03*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_03                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x34)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_03_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_03

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_03  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_03;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_03 {
    unsigned int reg_dim_cmd_vaule1_03                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_03(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_03*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_03                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x38)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_03_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_03

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_03  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_03;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_03 {
    unsigned int reg_dim_cmd_vaule2_03                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_03(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_03*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__03                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x3C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__03_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__03

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__03  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__03;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__03 {
    unsigned int reg_dim_cmd_vaule3_03                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__03(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__03*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_04                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x40)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_04_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_04

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_04  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_04;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_04 {
    unsigned int reg_dim_cmd_vaule0_04                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_04(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_04*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_04                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x44)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_04_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_04

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_04  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_04;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_04 {
    unsigned int reg_dim_cmd_vaule1_04                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_04(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_04*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_04                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x48)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_04_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_04

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_04  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_04;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_04 {
    unsigned int reg_dim_cmd_vaule2_04                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_04(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_04*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__04                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x4C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__04_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__04

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__04  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__04;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__04 {
    unsigned int reg_dim_cmd_vaule3_04                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__04(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__04*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_05                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x50)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_05_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_05

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_05  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_05;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_05 {
    unsigned int reg_dim_cmd_vaule0_05                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_05(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_05*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_05                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x54)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_05_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_05

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_05  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_05;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_05 {
    unsigned int reg_dim_cmd_vaule1_05                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_05(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_05*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_05                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x58)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_05_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_05

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_05  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_05;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_05 {
    unsigned int reg_dim_cmd_vaule2_05                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_05(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_05*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__05                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x5C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__05_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__05

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__05  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__05;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__05 {
    unsigned int reg_dim_cmd_vaule3_05                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__05(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__05*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_06                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x60)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_06_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_06

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_06  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_06;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_06 {
    unsigned int reg_dim_cmd_vaule0_06                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_06(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_06*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_06                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x64)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_06_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_06

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_06  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_06;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_06 {
    unsigned int reg_dim_cmd_vaule1_06                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_06(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_06*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_06                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x68)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_06_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_06

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_06  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_06;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_06 {
    unsigned int reg_dim_cmd_vaule2_06                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_06(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_06*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__06                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x6C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__06_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__06

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__06  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__06;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__06 {
    unsigned int reg_dim_cmd_vaule3_06                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__06(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__06*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_07                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x70)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_07_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_07

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_07  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_07;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_07 {
    unsigned int reg_dim_cmd_vaule0_07                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_07(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_07*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_07                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x74)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_07_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_07

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_07  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_07;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_07 {
    unsigned int reg_dim_cmd_vaule1_07                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_07(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_07*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_07                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x78)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_07_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_07

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_07  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_07;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_07 {
    unsigned int reg_dim_cmd_vaule2_07                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_07(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_07*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__07                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x7C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__07_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__07

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__07  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__07;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__07 {
    unsigned int reg_dim_cmd_vaule3_07                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__07(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__07*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_08                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x80)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_08_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_08

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_08  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_08;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_08 {
    unsigned int reg_dim_cmd_vaule0_08                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_08(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_08*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_08                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x84)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_08_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_08

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_08  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_08;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_08 {
    unsigned int reg_dim_cmd_vaule1_08                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_08(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_08*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_08                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x88)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_08_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_08

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_08  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_08;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_08 {
    unsigned int reg_dim_cmd_vaule2_08                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_08(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_08*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__08                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x8C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__08_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__08

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__08  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__08;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__08 {
    unsigned int reg_dim_cmd_vaule3_08                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__08(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__08*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_09                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x90)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE0_09_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_09

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_09  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_09;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_09 {
    unsigned int reg_dim_cmd_vaule0_09                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_09(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule0_09*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_09                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x94)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE1_09_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_09

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_09  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_09;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_09 {
    unsigned int reg_dim_cmd_vaule1_09                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_09(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule1_09*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_09                     (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x98)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE2_09_struct              rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_09

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_09  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_09;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_09 {
    unsigned int reg_dim_cmd_vaule2_09                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_09(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule2_09*)&(val))



#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__09                    (HV_KV_DIMMER_CTRL_REG3_BASE_ADDRESS + 0x9C)

#define RX_KV_DIMMER_CTRL_REG3_REG_DIM_CMD_VAULE3__09_struct             rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__09

typedef struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__09  rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__09;
struct _rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__09 {
    unsigned int reg_dim_cmd_vaule3_09                      :32;
};
#define rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__09(val) ((rs_rx_kv_dimmer_ctrl_reg3_reg_dim_cmd_vaule3__09*)&(val))



#endif