#ifndef _HV_PAGE_HT7315_EDP_RX_MAC_WR_REG_00_H_
#define _HV_PAGE_HT7315_EDP_RX_MAC_WR_REG_00_H_

#ifndef HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS
    #define HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS                                         0x11048700
#endif


#define RX_EDP_RX_MAC_WR_REG_00_00                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_MAC_WR_REG_00_00_struct                                rs_rx_edp_rx_mac_wr_reg_00_00

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_00  rs_rx_edp_rx_mac_wr_reg_00_00;
struct _rs_rx_edp_rx_mac_wr_reg_00_00 {
    unsigned int reg_00_dprx_glb_dbg_en                     : 1;
    unsigned int reg_00_dprx_presetn_dpcd_en                : 9;
    unsigned int reg_00_dprx_aux_rst_n_en                   : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_post_rst_n_en                  : 1;
    unsigned int reg_00_dprx_mute_rst_n_en                  : 1;
    unsigned int reg_00_dprx_mbist_rst_n_en                 : 1;
    unsigned int reg_00_dprx_lane_clk_mac_div_num           : 2;
    unsigned int reg_00_dprx_fec_rst_n_en                   : 1;
    unsigned int reg_00_dprx_lane_back_rst_n_en             : 1;
    unsigned int reg_00_dprx_lane_front_rst_n_en            : 1;
    unsigned int reg_00_dprx_lane_other_rst_n_en            : 1;
    unsigned int reserved_1                                 :11;
};
#define rx_edp_rx_mac_wr_reg_00_00(val) ((rs_rx_edp_rx_mac_wr_reg_00_00*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_04                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_MAC_WR_REG_00_04_struct                                rs_rx_edp_rx_mac_wr_reg_00_04

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_04  rs_rx_edp_rx_mac_wr_reg_00_04;
struct _rs_rx_edp_rx_mac_wr_reg_00_04 {
    unsigned int reg_00_dprx_clk_dbg_en                     : 1;
    unsigned int reg_00_dprx_osc_clk_mute_en                : 1;
    unsigned int reg_00_dprx_apb_clk_ro_en                  : 1;
    unsigned int reg_00_dprx_apb_clk_dpcd_en                : 1;
    unsigned int reg_00_dprx_apb_clk_gtc_en                 : 1;
    unsigned int reg_00_dprx_apb_clk_hpd_en                 : 1;
    unsigned int reg_00_dprx_apb_clk_aux_en                 : 1;
    unsigned int reg_00_dprx_apb_clk_ml_en                  : 1;
    unsigned int reg_00_dprx_lanes_clk_en                   : 4;
    unsigned int reg_00_dprx_lane_clk_en                    : 4;
    unsigned int reg_00_dprx_lane_clk_pdet_en               : 1;
    unsigned int reg_00_dprx_lane_clk_msa_en                : 1;
    unsigned int reg_00_dprx_lane_clk_sdp_en                : 1;
    unsigned int reg_00_dprx_lane_clk_vbid_en               : 1;
    unsigned int reg_00_dprx_pix_clk_en                     : 1;
    unsigned int reg_00_dprx_pix_clk_mute_en                : 1;
    unsigned int reg_00_dprx_pix_clk_psr_en                 : 1;
    unsigned int reg_00_dprx_pix_clk_psr_fb_en              : 1;
    unsigned int reg_00_dprx_pix_clk_psr_crc_en             : 1;
    unsigned int reg_00_dprx_sw_hw_ml_clk_en                : 2;
    unsigned int reg_00_dprx_sw_hw_psr_fb_clk_en            : 2;
    unsigned int reg_00_dprx_aux_clk_en                     : 1;
    unsigned int reg_00_dprx_symbol_error_count_sel_tr      : 2;
};
#define rx_edp_rx_mac_wr_reg_00_04(val) ((rs_rx_edp_rx_mac_wr_reg_00_04*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_08                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_MAC_WR_REG_00_08_struct                                rs_rx_edp_rx_mac_wr_reg_00_08

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_08  rs_rx_edp_rx_mac_wr_reg_00_08;
struct _rs_rx_edp_rx_mac_wr_reg_00_08 {
    unsigned int reg_00_dprx_phy_pn_reverse_en              : 4;
    unsigned int reg_00_dprx_phy_hl_reverse_en              : 4;
    unsigned int reg_00_dprx_phy_ml_reverse_en              : 4;
    unsigned int reg_00_dprx_train_start_sel                : 4;
    unsigned int reg_00_dprx_debug_sel                      : 4;
    unsigned int reg_00_dprx_symbol_training_mode           : 7;
    unsigned int reg_00_dprx_train_adjust_norm_en           : 4;
    unsigned int reg_00_dprx_ft_phy_cr_done_en              : 1;
};
#define rx_edp_rx_mac_wr_reg_00_08(val) ((rs_rx_edp_rx_mac_wr_reg_00_08*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_0C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x0C)

#define RX_EDP_RX_MAC_WR_REG_00_0C_struct                                rs_rx_edp_rx_mac_wr_reg_00_0c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_0c  rs_rx_edp_rx_mac_wr_reg_00_0c;
struct _rs_rx_edp_rx_mac_wr_reg_00_0c {
    unsigned int reg_00_dprx_cr_pattern                     :10;
    unsigned int reg_00_dprx_check_eq_thd                   : 8;
    unsigned int reg_00_dprx_sr_filter_en                   : 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_int_sel                        : 2;
    unsigned int reg_00_dprx_state_abn_mode                 : 4;
};
#define rx_edp_rx_mac_wr_reg_00_0c(val) ((rs_rx_edp_rx_mac_wr_reg_00_0c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_10                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x10)

#define RX_EDP_RX_MAC_WR_REG_00_10_struct                                rs_rx_edp_rx_mac_wr_reg_00_10

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_10  rs_rx_edp_rx_mac_wr_reg_00_10;
struct _rs_rx_edp_rx_mac_wr_reg_00_10 {
    unsigned int reg_00_dprx_bw_mode_sel                    : 4;
    unsigned int reg_00_dprx_bw_cnt_thd                     :10;
    unsigned int reg_00_dprx_bw_lv_thd                      : 4;
    unsigned int reg_00_dprx_ana_cr_done_mask               : 4;
    unsigned int reg_00_dprx_dpcd_link_bw_set_src           : 2;
    unsigned int reg_00_dprx_symbol_lock_pos_sw_en          : 4;
    unsigned int reg_00_dprx_assr_change_thro               : 4;
};
#define rx_edp_rx_mac_wr_reg_00_10(val) ((rs_rx_edp_rx_mac_wr_reg_00_10*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_14                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x14)

#define RX_EDP_RX_MAC_WR_REG_00_14_struct                                rs_rx_edp_rx_mac_wr_reg_00_14

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_14  rs_rx_edp_rx_mac_wr_reg_00_14;
struct _rs_rx_edp_rx_mac_wr_reg_00_14 {
    unsigned int reg_00_dprx_decode_err_tr_nwait_thd        :16;
    unsigned int reserved                                   :16;
};
#define rx_edp_rx_mac_wr_reg_00_14(val) ((rs_rx_edp_rx_mac_wr_reg_00_14*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_18                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x18)

#define RX_EDP_RX_MAC_WR_REG_00_18_struct                                rs_rx_edp_rx_mac_wr_reg_00_18

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_18  rs_rx_edp_rx_mac_wr_reg_00_18;
struct _rs_rx_edp_rx_mac_wr_reg_00_18 {
    unsigned int reg_00_dprx_training_time_ms_thd           :12;
    unsigned int reg_00_dprx_aux_to_phy_init_sel            : 1;
    unsigned int reg_00_dprx_decod_err_en                   : 1;
    unsigned int reg_00_dprx_decod_err_en_tr                : 1;
    unsigned int reg_00_dprx_train_force_en                 : 1;
    unsigned int reg_00_dprx_front_afifo_clr                : 1;
    unsigned int reg_00_dprx_froce_ft_st_en                 : 5;
    unsigned int reg_00_dprx_front_dbg_clr_en               : 1;
    unsigned int reg_00_dprx_phy_init_sel                   : 8;
    unsigned int reg_00_dprx_cfg_setting_rdy                : 1;
};
#define rx_edp_rx_mac_wr_reg_00_18(val) ((rs_rx_edp_rx_mac_wr_reg_00_18*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_1C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x1C)

#define RX_EDP_RX_MAC_WR_REG_00_1C_struct                                rs_rx_edp_rx_mac_wr_reg_00_1c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_1c  rs_rx_edp_rx_mac_wr_reg_00_1c;
struct _rs_rx_edp_rx_mac_wr_reg_00_1c {
    unsigned int reg_00_dprx_decoded_err_check_thd_nr       :16;
    unsigned int reg_00_dprx_decoded_err_check_thd_tr       :16;
};
#define rx_edp_rx_mac_wr_reg_00_1c(val) ((rs_rx_edp_rx_mac_wr_reg_00_1c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_20                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_MAC_WR_REG_00_20_struct                                rs_rx_edp_rx_mac_wr_reg_00_20

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_20  rs_rx_edp_rx_mac_wr_reg_00_20;
struct _rs_rx_edp_rx_mac_wr_reg_00_20 {
    unsigned int reg_00_dprx_decoded_check_wind             :16;
    unsigned int reg_00_dprx_dig_cr_done_mask               : 4;
    unsigned int reg_00_dprx_assr_change_con                : 2;
    unsigned int reg_00_dprx_ft_lane_pre_swap               : 8;
    unsigned int reg_00_dprx_aux_wlen_bypass                : 1;
    unsigned int reg_00_dprx_ft_lane_mask_en                : 1;
};
#define rx_edp_rx_mac_wr_reg_00_20(val) ((rs_rx_edp_rx_mac_wr_reg_00_20*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_24                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_MAC_WR_REG_00_24_struct                                rs_rx_edp_rx_mac_wr_reg_00_24

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_24  rs_rx_edp_rx_mac_wr_reg_00_24;
struct _rs_rx_edp_rx_mac_wr_reg_00_24 {
    unsigned int reg_00_dprx_sw_hpd_set                     : 2;
    unsigned int reg_00_dprx_sr_filter_thro                 :10;
    unsigned int reg_00_dprx_irq_hpd_en                     : 1;
    unsigned int reg_00_dprx_hpd_setting_rdy                : 2;
    unsigned int reg_00_dprx_st_cs_mask_tr                  : 1;
    unsigned int reg_00_dprx_hpd_irq_th                     :16;
};
#define rx_edp_rx_mac_wr_reg_00_24(val) ((rs_rx_edp_rx_mac_wr_reg_00_24*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_28                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_MAC_WR_REG_00_28_struct                                rs_rx_edp_rx_mac_wr_reg_00_28

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_28  rs_rx_edp_rx_mac_wr_reg_00_28;
struct _rs_rx_edp_rx_mac_wr_reg_00_28 {
    unsigned int reg_00_dprx_aux_en                         : 1;
    unsigned int reg_00_dprx_aux_glitch_th                  : 6;
    unsigned int reg_00_dprx_half_1us_thd                   :10;
    unsigned int reg_00_dprx_aux_pre_charge_num             : 5;
    unsigned int reg_00_dprx_aux_phase_sync_pat_sel         : 2;
    unsigned int reg_00_dprx_aux_rx_inv                     : 1;
    unsigned int reg_00_dprx_aux_from_pin                   : 2;
    unsigned int reg_00_dprx_aux_dpcd_access_sel            : 1;
    unsigned int reg_00_dprx_aux_actual_freq_th             : 4;
};
#define rx_edp_rx_mac_wr_reg_00_28(val) ((rs_rx_edp_rx_mac_wr_reg_00_28*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_2C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x2C)

#define RX_EDP_RX_MAC_WR_REG_00_2C_struct                                rs_rx_edp_rx_mac_wr_reg_00_2c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_2c  rs_rx_edp_rx_mac_wr_reg_00_2c;
struct _rs_rx_edp_rx_mac_wr_reg_00_2c {
    unsigned int reg_00_dprx_aux_freq_sync_th               : 8;
    unsigned int reg_00_dprx_aux_phase_sync_mask            : 8;
    unsigned int reg_00_dprx_aux_rw_apb_bypass_en           : 1;
    unsigned int reg_00_dprx_aux_time_out_clr_en            : 1;
    unsigned int reg_00_dprx_aux_rdata_num_limit_en         : 1;
    unsigned int reg_00_dprx_aux_edid_wr_en                 : 1;
    unsigned int reg_00_dprx_aux_phase_sync_bypass          : 1;
    unsigned int reg_00_dprx_aux_start_patt1_en             : 1;
    unsigned int reg_00_dprx_aux_tx_wake_sel                : 2;
    unsigned int reg_00_dprx_aux_corr_value_th              : 8;
};
#define rx_edp_rx_mac_wr_reg_00_2c(val) ((rs_rx_edp_rx_mac_wr_reg_00_2c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_30                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x30)

#define RX_EDP_RX_MAC_WR_REG_00_30_struct                                rs_rx_edp_rx_mac_wr_reg_00_30

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_30  rs_rx_edp_rx_mac_wr_reg_00_30;
struct _rs_rx_edp_rx_mac_wr_reg_00_30 {
    unsigned int reg_00_dprx_aux_timeout_th                 :16;
    unsigned int reg_00_dprx_aux_rdback_clr_en              : 1;
    unsigned int reg_00_dprx_aux_tx_inv                     : 1;
    unsigned int reg_00_dprx_aux_tx_phase_dly_en            : 1;
    unsigned int reg_00_dprx_aux_tx_precharge_on            : 1;
    unsigned int reg_00_dprx_aux_state_rst_en               : 1;
    unsigned int reg_00_dprx_aux_debug_clr_en               : 1;
    unsigned int reg_00_dprx_aux_edid_en                    : 1;
    unsigned int reg_00_dprx_aux_test_en                    : 1;
    unsigned int reg_00_dprx_apb_addr                       : 8;
};
#define rx_edp_rx_mac_wr_reg_00_30(val) ((rs_rx_edp_rx_mac_wr_reg_00_30*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_34                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x34)

#define RX_EDP_RX_MAC_WR_REG_00_34_struct                                rs_rx_edp_rx_mac_wr_reg_00_34

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_34  rs_rx_edp_rx_mac_wr_reg_00_34;
struct _rs_rx_edp_rx_mac_wr_reg_00_34 {
    unsigned int reg_00_dprx_edid_addr0                     : 8;
    unsigned int reg_00_dprx_edid_addr1                     : 8;
    unsigned int reg_00_dprx_aux_tx_dly_thro                :16;
};
#define rx_edp_rx_mac_wr_reg_00_34(val) ((rs_rx_edp_rx_mac_wr_reg_00_34*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_38                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x38)

#define RX_EDP_RX_MAC_WR_REG_00_38_struct                                rs_rx_edp_rx_mac_wr_reg_00_38

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_38  rs_rx_edp_rx_mac_wr_reg_00_38;
struct _rs_rx_edp_rx_mac_wr_reg_00_38 {
    unsigned int reg_00_dprx_psr_fsm_de_update_cnt_clr_sel  : 1;
    unsigned int reg_00_dprx_aux_apb_en                     : 1;
    unsigned int reg_00_dprx_mccs_addr                      : 8;
    unsigned int reg_00_dprx_aux_mccs_en                    : 1;
    unsigned int reg_00_dprx_aux_pre_amble_num              : 5;
    unsigned int reg_00_dprx_aux_illegal_en                 : 1;
    unsigned int reg_00_dprx_aux_nack_bypass                : 1;
    unsigned int reg_00_dprx_aux_wr_prot_bypass             : 1;
    unsigned int reg_00_dprx_auto_assr_det_cont             : 1;
    unsigned int reg_00_dprx_eq_init_nolink_cnt             : 5;
    unsigned int reg_00_dprx_ft_dbg_mode_sel                : 4;
    unsigned int reg_00_dprx_ft_init_en                     : 2;
    unsigned int reg_00_dprx_cfg_setting_vs_mask            : 1;
};
#define rx_edp_rx_mac_wr_reg_00_38(val) ((rs_rx_edp_rx_mac_wr_reg_00_38*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_3C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x3C)

#define RX_EDP_RX_MAC_WR_REG_00_3C_struct                                rs_rx_edp_rx_mac_wr_reg_00_3c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_3c  rs_rx_edp_rx_mac_wr_reg_00_3c;
struct _rs_rx_edp_rx_mac_wr_reg_00_3c {
    unsigned int reg_00_dprx_full_link_thd                  :24;
    unsigned int reg_00_dprx_auto_assr_en                   : 1;
    unsigned int reg_00_dprx_auto_assr_sel                  : 2;
    unsigned int reg_00_dprx_mst_en_ft_sel                  : 2;
    unsigned int reg_00_dprx_fec_rs_cnt_sel                 : 3;
};
#define rx_edp_rx_mac_wr_reg_00_3c(val) ((rs_rx_edp_rx_mac_wr_reg_00_3c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_40                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_MAC_WR_REG_00_40_struct                                rs_rx_edp_rx_mac_wr_reg_00_40

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_40  rs_rx_edp_rx_mac_wr_reg_00_40;
struct _rs_rx_edp_rx_mac_wr_reg_00_40 {
    unsigned int reg_00_dprx_pm_en                          : 1;
    unsigned int reg_00_dprx_pm_lock_timeout_en             : 1;
    unsigned int reg_00_dprx_pm_wake_mode_sel               : 1;
    unsigned int reg_00_dprx_alpm_patt_det_en               : 1;
    unsigned int reg_00_dprx_hw_ml_dly                      :28;
};
#define rx_edp_rx_mac_wr_reg_00_40(val) ((rs_rx_edp_rx_mac_wr_reg_00_40*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_44                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_MAC_WR_REG_00_44_struct                                rs_rx_edp_rx_mac_wr_reg_00_44

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_44  rs_rx_edp_rx_mac_wr_reg_00_44;
struct _rs_rx_edp_rx_mac_wr_reg_00_44 {
    unsigned int reg_00_dprx_pm_lock_timeout_thro           :32;
};
#define rx_edp_rx_mac_wr_reg_00_44(val) ((rs_rx_edp_rx_mac_wr_reg_00_44*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_48                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_MAC_WR_REG_00_48_struct                                rs_rx_edp_rx_mac_wr_reg_00_48

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_48  rs_rx_edp_rx_mac_wr_reg_00_48;
struct _rs_rx_edp_rx_mac_wr_reg_00_48 {
    unsigned int reg_00_dprx_tps2_det_thro                  : 8;
    unsigned int reg_00_dprx_tps3_det_thro                  : 8;
    unsigned int reg_00_dprx_tps4_det_thro                  : 8;
    unsigned int reg_00_dprx_alpm_fw_slp_det_thro           : 8;
};
#define rx_edp_rx_mac_wr_reg_00_48(val) ((rs_rx_edp_rx_mac_wr_reg_00_48*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_4C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x4C)

#define RX_EDP_RX_MAC_WR_REG_00_4C_struct                                rs_rx_edp_rx_mac_wr_reg_00_4c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_4c  rs_rx_edp_rx_mac_wr_reg_00_4c;
struct _rs_rx_edp_rx_mac_wr_reg_00_4c {
    unsigned int reg_00_dprx_alpm_fw_stb_det_thro           : 8;
    unsigned int reg_00_dprx_tps_detpro_en                  : 2;
    unsigned int reg_00_dprx_psr_exit_mode                  : 4;
    unsigned int reg_00_dprx_main_link_debug_sel            : 4;
    unsigned int reg_00_dprx_aux_debug_sel                  : 4;
    unsigned int reg_00_dprx_dig_eq_done_mask               : 4;
    unsigned int reg_00_dprx_symbol_lock_mask               : 4;
    unsigned int reg_00_dprx_decod_err_sel                  : 1;
    unsigned int reg_00_dprx_aux_i2c_invalid_addr_en        : 1;
};
#define rx_edp_rx_mac_wr_reg_00_4c(val) ((rs_rx_edp_rx_mac_wr_reg_00_4c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_50                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x50)

#define RX_EDP_RX_MAC_WR_REG_00_50_struct                                rs_rx_edp_rx_mac_wr_reg_00_50

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_50  rs_rx_edp_rx_mac_wr_reg_00_50;
struct _rs_rx_edp_rx_mac_wr_reg_00_50 {
    unsigned int reg_00_dprx_bp_aln_done_dly_thd            : 4;
    unsigned int reg_00_dprx_cfg_setting_rdy_mask           : 1;
    unsigned int reg_00_dprx_hpd_inv                        : 1;
    unsigned int reg_00_dprx_cr_training_time               : 8;
    unsigned int reg_00_dprx_aux_evt_timeout_th             :16;
    unsigned int reg_00_dprx_sw_irqhpd_set                  : 2;
};
#define rx_edp_rx_mac_wr_reg_00_50(val) ((rs_rx_edp_rx_mac_wr_reg_00_50*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_54                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x54)

#define RX_EDP_RX_MAC_WR_REG_00_54_struct                                rs_rx_edp_rx_mac_wr_reg_00_54

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_54  rs_rx_edp_rx_mac_wr_reg_00_54;
struct _rs_rx_edp_rx_mac_wr_reg_00_54 {
    unsigned int reg_00_dprx_hpd_det_th                     :16;
    unsigned int reg_00_dprx_hpd_discon_th                  :16;
};
#define rx_edp_rx_mac_wr_reg_00_54(val) ((rs_rx_edp_rx_mac_wr_reg_00_54*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_58                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x58)

#define RX_EDP_RX_MAC_WR_REG_00_58_struct                                rs_rx_edp_rx_mac_wr_reg_00_58

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_58  rs_rx_edp_rx_mac_wr_reg_00_58;
struct _rs_rx_edp_rx_mac_wr_reg_00_58 {
    unsigned int reg_00_dprx_abnormal_en_l                  :32;
};
#define rx_edp_rx_mac_wr_reg_00_58(val) ((rs_rx_edp_rx_mac_wr_reg_00_58*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_5C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x5C)

#define RX_EDP_RX_MAC_WR_REG_00_5C_struct                                rs_rx_edp_rx_mac_wr_reg_00_5c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_5c  rs_rx_edp_rx_mac_wr_reg_00_5c;
struct _rs_rx_edp_rx_mac_wr_reg_00_5c {
    unsigned int reg_00_dprx_abnormal_en_h                  :32;
};
#define rx_edp_rx_mac_wr_reg_00_5c(val) ((rs_rx_edp_rx_mac_wr_reg_00_5c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_60                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_MAC_WR_REG_00_60_struct                                rs_rx_edp_rx_mac_wr_reg_00_60

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_60  rs_rx_edp_rx_mac_wr_reg_00_60;
struct _rs_rx_edp_rx_mac_wr_reg_00_60 {
    unsigned int reg_00_dprx_aux_rd_timer_interval_cr       :16;
    unsigned int reg_00_dprx_aux_rd_timer_interval_eq       :16;
};
#define rx_edp_rx_mac_wr_reg_00_60(val) ((rs_rx_edp_rx_mac_wr_reg_00_60*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_64                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x64)

#define RX_EDP_RX_MAC_WR_REG_00_64_struct                                rs_rx_edp_rx_mac_wr_reg_00_64

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_64  rs_rx_edp_rx_mac_wr_reg_00_64;
struct _rs_rx_edp_rx_mac_wr_reg_00_64 {
    unsigned int reg_00_dprx_train_start_request            : 4;
    unsigned int reg_00_dprx_train_request0                 : 4;
    unsigned int reg_00_dprx_train_request1                 : 4;
    unsigned int reg_00_dprx_train_request2                 : 4;
    unsigned int reg_00_dprx_train_request3                 : 4;
    unsigned int reg_00_dprx_train_request4                 : 4;
    unsigned int reg_00_dprx_train_request5                 : 4;
    unsigned int reg_00_dprx_train_request6                 : 4;
};
#define rx_edp_rx_mac_wr_reg_00_64(val) ((rs_rx_edp_rx_mac_wr_reg_00_64*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_68                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x68)

#define RX_EDP_RX_MAC_WR_REG_00_68_struct                                rs_rx_edp_rx_mac_wr_reg_00_68

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_68  rs_rx_edp_rx_mac_wr_reg_00_68;
struct _rs_rx_edp_rx_mac_wr_reg_00_68 {
    unsigned int reg_00_dprx_train_request7                 : 4;
    unsigned int reg_00_dprx_train_request8                 : 4;
    unsigned int reg_00_dprx_train_request9                 : 4;
    unsigned int reg_00_dprx_sw_bp_aln_done                 : 2;
    unsigned int reg_00_dprx_aux_tx_mode_sel                : 4;
    unsigned int reg_00_dprx_ana_eq_done_mask               : 4;
    unsigned int reg_00_dprx_aux_dump_bypass                : 4;
    unsigned int reg_00_dprx_deskew_rb_sel                  : 2;
    unsigned int reg_00_dprx_aux_defer_en                   : 4;
};
#define rx_edp_rx_mac_wr_reg_00_68(val) ((rs_rx_edp_rx_mac_wr_reg_00_68*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_6C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x6C)

#define RX_EDP_RX_MAC_WR_REG_00_6C_struct                                rs_rx_edp_rx_mac_wr_reg_00_6c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_6c  rs_rx_edp_rx_mac_wr_reg_00_6c;
struct _rs_rx_edp_rx_mac_wr_reg_00_6c {
    unsigned int reg_00_dprx_deskew_keyval1                 :10;
    unsigned int reg_00_dprx_deskew_max_con                 : 1;
    unsigned int reg_00_dprx_deskew_base_sel                : 4;
    unsigned int reg_00_dprx_fec_en                         : 1;
    unsigned int reg_00_dprx_fec_agent_sel                  : 2;
    unsigned int reg_00_dprx_fec_err_cnt_clr                : 1;
    unsigned int reg_00_dprx_fec_rs_delay                   : 9;
    unsigned int reg_00_dprx_fec_en_sel                     : 1;
    unsigned int reg_00_dprx_fec_rs_bypass                  : 1;
    unsigned int reg_00_dprx_sw_fec_flag                    : 2;
};
#define rx_edp_rx_mac_wr_reg_00_6c(val) ((rs_rx_edp_rx_mac_wr_reg_00_6c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_70                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x70)

#define RX_EDP_RX_MAC_WR_REG_00_70_struct                                rs_rx_edp_rx_mac_wr_reg_00_70

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_70  rs_rx_edp_rx_mac_wr_reg_00_70;
struct _rs_rx_edp_rx_mac_wr_reg_00_70 {
    unsigned int reg_00_dprx_deskew_en                      : 1;
    unsigned int reg_00_dprx_deskew_check_win               : 6;
    unsigned int reg_00_dprx_deskew_max_thro                : 6;
    unsigned int reg_00_dprx_deskew_thd                     : 8;
    unsigned int reg_00_dprx_deskew_keyval0                 :10;
    unsigned int reg_00_dprx_deskew_err_en                  : 1;
};
#define rx_edp_rx_mac_wr_reg_00_70(val) ((rs_rx_edp_rx_mac_wr_reg_00_70*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_74                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x74)

#define RX_EDP_RX_MAC_WR_REG_00_74_struct                                rs_rx_edp_rx_mac_wr_reg_00_74

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_74  rs_rx_edp_rx_mac_wr_reg_00_74;
struct _rs_rx_edp_rx_mac_wr_reg_00_74 {
    unsigned int reg_00_dprx_pm_dbg_clr                     : 1;
    unsigned int reg_00_dprx_sw_irq                         : 1;
    unsigned int reg_00_dprx_psr_en                         : 1;
    unsigned int reg_00_dprx_psr_vspermit_bypass            : 1;
    unsigned int reg_00_dprx_psr_cap_vs_clr_en              : 1;
    unsigned int reg_00_dprx_psr_rv_flag_bypass             : 1;
    unsigned int reg_00_dprx_psr_crc_rgb_swap               : 4;
    unsigned int reg_00_dprx_psr_cap_su_en                  : 1;
    unsigned int reg_00_dprx_psr_crc_en                     : 1;
    unsigned int reg_00_dprx_psr_sdp_dly_thro               :12;
    unsigned int reg_00_dprx_irq_width                      : 8;
};
#define rx_edp_rx_mac_wr_reg_00_74(val) ((rs_rx_edp_rx_mac_wr_reg_00_74*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_78                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x78)

#define RX_EDP_RX_MAC_WR_REG_00_78_struct                                rs_rx_edp_rx_mac_wr_reg_00_78

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_78  rs_rx_edp_rx_mac_wr_reg_00_78;
struct _rs_rx_edp_rx_mac_wr_reg_00_78 {
    unsigned int reg_00_dprx_irq_en_l                       :32;
};
#define rx_edp_rx_mac_wr_reg_00_78(val) ((rs_rx_edp_rx_mac_wr_reg_00_78*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_7C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x7C)

#define RX_EDP_RX_MAC_WR_REG_00_7C_struct                                rs_rx_edp_rx_mac_wr_reg_00_7c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_7c  rs_rx_edp_rx_mac_wr_reg_00_7c;
struct _rs_rx_edp_rx_mac_wr_reg_00_7c {
    unsigned int reg_00_dprx_irq_en_h                       :32;
};
#define rx_edp_rx_mac_wr_reg_00_7c(val) ((rs_rx_edp_rx_mac_wr_reg_00_7c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_80                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x80)

#define RX_EDP_RX_MAC_WR_REG_00_80_struct                                rs_rx_edp_rx_mac_wr_reg_00_80

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_80  rs_rx_edp_rx_mac_wr_reg_00_80;
struct _rs_rx_edp_rx_mac_wr_reg_00_80 {
    unsigned int reg_00_dprx_irq_wclr_l                     :32;
};
#define rx_edp_rx_mac_wr_reg_00_80(val) ((rs_rx_edp_rx_mac_wr_reg_00_80*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_84                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x84)

#define RX_EDP_RX_MAC_WR_REG_00_84_struct                                rs_rx_edp_rx_mac_wr_reg_00_84

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_84  rs_rx_edp_rx_mac_wr_reg_00_84;
struct _rs_rx_edp_rx_mac_wr_reg_00_84 {
    unsigned int reg_00_dprx_irq_wclr_h                     :32;
};
#define rx_edp_rx_mac_wr_reg_00_84(val) ((rs_rx_edp_rx_mac_wr_reg_00_84*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_88                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x88)

#define RX_EDP_RX_MAC_WR_REG_00_88_struct                                rs_rx_edp_rx_mac_wr_reg_00_88

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_88  rs_rx_edp_rx_mac_wr_reg_00_88;
struct _rs_rx_edp_rx_mac_wr_reg_00_88 {
    unsigned int reg_00_dprx_fec_dbg_sel                    : 2;
    unsigned int reg_00_dprx_psr_dbg_clr                    : 1;
    unsigned int reg_00_dprx_hdcp_bypass                    : 1;
    unsigned int reg_00_dprx_psr_dbg_sel                    : 1;
    unsigned int reg_00_dprx_psr2_vcomp                     : 8;
    unsigned int reg_00_dprx_tps_detpro_lvld_en             : 2;
    unsigned int reg_00_dprx_psr_vspermit_sel               : 1;
    unsigned int reg_00_dprx_psr_timing_switch_flag_thro    :16;
};
#define rx_edp_rx_mac_wr_reg_00_88(val) ((rs_rx_edp_rx_mac_wr_reg_00_88*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_8C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x8C)

#define RX_EDP_RX_MAC_WR_REG_00_8C_struct                                rs_rx_edp_rx_mac_wr_reg_00_8c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_8c  rs_rx_edp_rx_mac_wr_reg_00_8c;
struct _rs_rx_edp_rx_mac_wr_reg_00_8c {
    unsigned int reg_00_dprx_psr_crc_timeout_thro           :32;
};
#define rx_edp_rx_mac_wr_reg_00_8c(val) ((rs_rx_edp_rx_mac_wr_reg_00_8c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_90                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x90)

#define RX_EDP_RX_MAC_WR_REG_00_90_struct                                rs_rx_edp_rx_mac_wr_reg_00_90

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_90  rs_rx_edp_rx_mac_wr_reg_00_90;
struct _rs_rx_edp_rx_mac_wr_reg_00_90 {
    unsigned int reg_00_dprx_psr_vactive                    :16;
    unsigned int reg_00_dprx_psr_vs_dly_thro                :16;
};
#define rx_edp_rx_mac_wr_reg_00_90(val) ((rs_rx_edp_rx_mac_wr_reg_00_90*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_94                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x94)

#define RX_EDP_RX_MAC_WR_REG_00_94_struct                                rs_rx_edp_rx_mac_wr_reg_00_94

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_94  rs_rx_edp_rx_mac_wr_reg_00_94;
struct _rs_rx_edp_rx_mac_wr_reg_00_94 {
    unsigned int reg_00_dprx_mst_vc_sel                     :32;
};
#define rx_edp_rx_mac_wr_reg_00_94(val) ((rs_rx_edp_rx_mac_wr_reg_00_94*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_98                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x98)

#define RX_EDP_RX_MAC_WR_REG_00_98_struct                                rs_rx_edp_rx_mac_wr_reg_00_98

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_98  rs_rx_edp_rx_mac_wr_reg_00_98;
struct _rs_rx_edp_rx_mac_wr_reg_00_98 {
    unsigned int reg_00_dprx_sink_st_sel                    : 4;
    unsigned int reg_00_dprx_psr_no_link_mode_sel           : 4;
    unsigned int reg_00_dprx_dfe_init_sel                   : 8;
    unsigned int reg_00_dprx_to_dpcd_st_done_sel            : 2;
    unsigned int reg_00_dprx_force_psr_fsm                  : 4;
    unsigned int reg_00_dprx_force_psr_fsm1                 : 5;
    unsigned int reg_00_dprx_mst_bypass                     : 2;
    unsigned int reg_00_dprx_mst_key_thro                   : 3;
};
#define rx_edp_rx_mac_wr_reg_00_98(val) ((rs_rx_edp_rx_mac_wr_reg_00_98*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_9C                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0x9C)

#define RX_EDP_RX_MAC_WR_REG_00_9C_struct                                rs_rx_edp_rx_mac_wr_reg_00_9c

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_9c  rs_rx_edp_rx_mac_wr_reg_00_9c;
struct _rs_rx_edp_rx_mac_wr_reg_00_9c {
    unsigned int reg_00_dprx_eq_dly_thd                     :16;
    unsigned int reg_00_dprx_eq_init_sel                    : 8;
    unsigned int reg_00_dprx_ft_normal_flt_thd              : 8;
};
#define rx_edp_rx_mac_wr_reg_00_9c(val) ((rs_rx_edp_rx_mac_wr_reg_00_9c*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_A0                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xA0)

#define RX_EDP_RX_MAC_WR_REG_00_A0_struct                                rs_rx_edp_rx_mac_wr_reg_00_a0

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_a0  rs_rx_edp_rx_mac_wr_reg_00_a0;
struct _rs_rx_edp_rx_mac_wr_reg_00_a0 {
    unsigned int reg_00_dprx_ft_st_con                      :16;
    unsigned int reg_00_dprx_full_link_en                   : 2;
    unsigned int reg_00_dprx_full_link_st_con               : 8;
    unsigned int reserved                                   : 6;
};
#define rx_edp_rx_mac_wr_reg_00_a0(val) ((rs_rx_edp_rx_mac_wr_reg_00_a0*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_A4                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xA4)

#define RX_EDP_RX_MAC_WR_REG_00_A4_struct                                rs_rx_edp_rx_mac_wr_reg_00_a4

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_a4  rs_rx_edp_rx_mac_wr_reg_00_a4;
struct _rs_rx_edp_rx_mac_wr_reg_00_a4 {
    unsigned int reg_00_dprx_ft_err_dly_thd                 :16;
    unsigned int reg_00_dprx_aux_pluse_timeout_th           :16;
};
#define rx_edp_rx_mac_wr_reg_00_a4(val) ((rs_rx_edp_rx_mac_wr_reg_00_a4*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_A8                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xA8)

#define RX_EDP_RX_MAC_WR_REG_00_A8_struct                                rs_rx_edp_rx_mac_wr_reg_00_a8

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_a8  rs_rx_edp_rx_mac_wr_reg_00_a8;
struct _rs_rx_edp_rx_mac_wr_reg_00_a8 {
    unsigned int reg_00_dprx_irq_en_l1                      : 8;
    unsigned int reg_00_dprx_irq_wclr_l1                    : 8;
    unsigned int reg_00_dprx_abnormal_en_l1                 : 8;
    unsigned int reg_00_dprx_prbs7_compared_start_max       : 4;
    unsigned int reg_00_dprx_test_patt_det_en               : 4;
};
#define rx_edp_rx_mac_wr_reg_00_a8(val) ((rs_rx_edp_rx_mac_wr_reg_00_a8*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_AC                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xAC)

#define RX_EDP_RX_MAC_WR_REG_00_AC_struct                                rs_rx_edp_rx_mac_wr_reg_00_ac

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_ac  rs_rx_edp_rx_mac_wr_reg_00_ac;
struct _rs_rx_edp_rx_mac_wr_reg_00_ac {
    unsigned int reg_00_dprx_gtc_en                         : 2;
    unsigned int reg_00_dprx_gtc_com0_mode                  : 2;
    unsigned int reg_00_dprx_gtc_com1_mode                  : 2;
    unsigned int reg_00_dprx_frame_sync_irq_hpd_en          : 1;
    unsigned int reg_00_dprx_frame_sync_unlock_en           : 1;
    unsigned int reg_00_dprx_aux_pluse_timeout_sel          : 8;
    unsigned int reg_00_dprx_gtc_com0_val                   :16;
};
#define rx_edp_rx_mac_wr_reg_00_ac(val) ((rs_rx_edp_rx_mac_wr_reg_00_ac*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_B0                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xB0)

#define RX_EDP_RX_MAC_WR_REG_00_B0_struct                                rs_rx_edp_rx_mac_wr_reg_00_b0

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_b0  rs_rx_edp_rx_mac_wr_reg_00_b0;
struct _rs_rx_edp_rx_mac_wr_reg_00_b0 {
    unsigned int reg_00_dprx_gtc_com1_val                   :16;
    unsigned int reg_00_dprx_gtc_rx_cnt_step                :16;
};
#define rx_edp_rx_mac_wr_reg_00_b0(val) ((rs_rx_edp_rx_mac_wr_reg_00_b0*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_B4                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xB4)

#define RX_EDP_RX_MAC_WR_REG_00_B4_struct                                rs_rx_edp_rx_mac_wr_reg_00_b4

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_b4  rs_rx_edp_rx_mac_wr_reg_00_b4;
struct _rs_rx_edp_rx_mac_wr_reg_00_b4 {
    unsigned int reg_00_dprx_gtc_err_max_thro               :16;
    unsigned int reg_00_dprx_gtc_err_min_thro               :16;
};
#define rx_edp_rx_mac_wr_reg_00_b4(val) ((rs_rx_edp_rx_mac_wr_reg_00_b4*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_B8                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xB8)

#define RX_EDP_RX_MAC_WR_REG_00_B8_struct                                rs_rx_edp_rx_mac_wr_reg_00_b8

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_b8  rs_rx_edp_rx_mac_wr_reg_00_b8;
struct _rs_rx_edp_rx_mac_wr_reg_00_b8 {
    unsigned int reg_00_dprx_gtc_lock_thro                  :16;
    unsigned int reg_00_dprx_gtc_unlock_thro                :16;
};
#define rx_edp_rx_mac_wr_reg_00_b8(val) ((rs_rx_edp_rx_mac_wr_reg_00_b8*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_BC                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xBC)

#define RX_EDP_RX_MAC_WR_REG_00_BC_struct                                rs_rx_edp_rx_mac_wr_reg_00_bc

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_bc  rs_rx_edp_rx_mac_wr_reg_00_bc;
struct _rs_rx_edp_rx_mac_wr_reg_00_bc {
    unsigned int reg_00_dprx_test_crc_en                    : 1;
    unsigned int reg_00_dprx_test_crc_sw_clr                : 2;
    unsigned int reg_00_dprx_auto_assr_det_win              :10;
    unsigned int reg_00_dprx_auto_assr_det_thd              :10;
    unsigned int reg_00_dprx_edid_seg_addr                  : 8;
    unsigned int reg_00_dprx_aux_i2c_dis_flag_mask          : 1;
};
#define rx_edp_rx_mac_wr_reg_00_bc(val) ((rs_rx_edp_rx_mac_wr_reg_00_bc*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_C0                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xC0)

#define RX_EDP_RX_MAC_WR_REG_00_C0_struct                                rs_rx_edp_rx_mac_wr_reg_00_c0

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_c0  rs_rx_edp_rx_mac_wr_reg_00_c0;
struct _rs_rx_edp_rx_mac_wr_reg_00_c0 {
    unsigned int reg_00_dprx_crc_seg0_xstart                :16;
    unsigned int reg_00_dprx_crc_seg0_xend                  :16;
};
#define rx_edp_rx_mac_wr_reg_00_c0(val) ((rs_rx_edp_rx_mac_wr_reg_00_c0*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_C4                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xC4)

#define RX_EDP_RX_MAC_WR_REG_00_C4_struct                                rs_rx_edp_rx_mac_wr_reg_00_c4

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_c4  rs_rx_edp_rx_mac_wr_reg_00_c4;
struct _rs_rx_edp_rx_mac_wr_reg_00_c4 {
    unsigned int reg_00_dprx_crc_seg1_xstart                :16;
    unsigned int reg_00_dprx_crc_seg1_xend                  :16;
};
#define rx_edp_rx_mac_wr_reg_00_c4(val) ((rs_rx_edp_rx_mac_wr_reg_00_c4*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_C8                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xC8)

#define RX_EDP_RX_MAC_WR_REG_00_C8_struct                                rs_rx_edp_rx_mac_wr_reg_00_c8

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_c8  rs_rx_edp_rx_mac_wr_reg_00_c8;
struct _rs_rx_edp_rx_mac_wr_reg_00_c8 {
    unsigned int reg_00_dprx_dpcd_editable_addr_start1      :20;
    unsigned int reg_00_dprx_fec_rs_done_thro               :10;
    unsigned int reg_00_dprx_aux_edid_wr_en_fake            : 1;
    unsigned int reg_00_dprx_aux_i2c_edid_cnt_bypass        : 1;
};
#define rx_edp_rx_mac_wr_reg_00_c8(val) ((rs_rx_edp_rx_mac_wr_reg_00_c8*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_CC                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xCC)

#define RX_EDP_RX_MAC_WR_REG_00_CC_struct                                rs_rx_edp_rx_mac_wr_reg_00_cc

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_cc  rs_rx_edp_rx_mac_wr_reg_00_cc;
struct _rs_rx_edp_rx_mac_wr_reg_00_cc {
    unsigned int reg_00_dprx_aux_fw_rdata_0                 :32;
};
#define rx_edp_rx_mac_wr_reg_00_cc(val) ((rs_rx_edp_rx_mac_wr_reg_00_cc*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_D0                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xD0)

#define RX_EDP_RX_MAC_WR_REG_00_D0_struct                                rs_rx_edp_rx_mac_wr_reg_00_d0

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_d0  rs_rx_edp_rx_mac_wr_reg_00_d0;
struct _rs_rx_edp_rx_mac_wr_reg_00_d0 {
    unsigned int reg_00_dprx_aux_fw_rdata_1                 :32;
};
#define rx_edp_rx_mac_wr_reg_00_d0(val) ((rs_rx_edp_rx_mac_wr_reg_00_d0*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_D4                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xD4)

#define RX_EDP_RX_MAC_WR_REG_00_D4_struct                                rs_rx_edp_rx_mac_wr_reg_00_d4

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_d4  rs_rx_edp_rx_mac_wr_reg_00_d4;
struct _rs_rx_edp_rx_mac_wr_reg_00_d4 {
    unsigned int reg_00_dprx_aux_fw_rdata_2                 :32;
};
#define rx_edp_rx_mac_wr_reg_00_d4(val) ((rs_rx_edp_rx_mac_wr_reg_00_d4*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_D8                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xD8)

#define RX_EDP_RX_MAC_WR_REG_00_D8_struct                                rs_rx_edp_rx_mac_wr_reg_00_d8

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_d8  rs_rx_edp_rx_mac_wr_reg_00_d8;
struct _rs_rx_edp_rx_mac_wr_reg_00_d8 {
    unsigned int reg_00_dprx_aux_fw_rdata_3                 :32;
};
#define rx_edp_rx_mac_wr_reg_00_d8(val) ((rs_rx_edp_rx_mac_wr_reg_00_d8*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_DC                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xDC)

#define RX_EDP_RX_MAC_WR_REG_00_DC_struct                                rs_rx_edp_rx_mac_wr_reg_00_dc

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_dc  rs_rx_edp_rx_mac_wr_reg_00_dc;
struct _rs_rx_edp_rx_mac_wr_reg_00_dc {
    unsigned int reg_00_dprx_crc_seg2_xstart                :16;
    unsigned int reg_00_dprx_crc_seg2_xend                  :16;
};
#define rx_edp_rx_mac_wr_reg_00_dc(val) ((rs_rx_edp_rx_mac_wr_reg_00_dc*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_E0                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xE0)

#define RX_EDP_RX_MAC_WR_REG_00_E0_struct                                rs_rx_edp_rx_mac_wr_reg_00_e0

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_e0  rs_rx_edp_rx_mac_wr_reg_00_e0;
struct _rs_rx_edp_rx_mac_wr_reg_00_e0 {
    unsigned int reg_00_dprx_crc_seg3_xstart                :16;
    unsigned int reg_00_dprx_crc_seg3_xend                  :16;
};
#define rx_edp_rx_mac_wr_reg_00_e0(val) ((rs_rx_edp_rx_mac_wr_reg_00_e0*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_E4                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xE4)

#define RX_EDP_RX_MAC_WR_REG_00_E4_struct                                rs_rx_edp_rx_mac_wr_reg_00_e4

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_e4  rs_rx_edp_rx_mac_wr_reg_00_e4;
struct _rs_rx_edp_rx_mac_wr_reg_00_e4 {
    unsigned int reg_00_dprx_psr_su_cnt_max_thro            :16;
    unsigned int reg_00_dprx_psr_su_cnt_min_thro            :16;
};
#define rx_edp_rx_mac_wr_reg_00_e4(val) ((rs_rx_edp_rx_mac_wr_reg_00_e4*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_E8                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xE8)

#define RX_EDP_RX_MAC_WR_REG_00_E8_struct                                rs_rx_edp_rx_mac_wr_reg_00_e8

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_e8  rs_rx_edp_rx_mac_wr_reg_00_e8;
struct _rs_rx_edp_rx_mac_wr_reg_00_e8 {
    unsigned int reg_00_dprx_psr_su_de_cnt_max_thro         : 4;
    unsigned int reg_00_dprx_psr_su_de_cnt_min_thro         : 4;
    unsigned int reg_00_dprx_psr_su_timeout_thro            :16;
    unsigned int reg_00_dprx_cdr_time_max                   : 8;
};
#define rx_edp_rx_mac_wr_reg_00_e8(val) ((rs_rx_edp_rx_mac_wr_reg_00_e8*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_EC                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xEC)

#define RX_EDP_RX_MAC_WR_REG_00_EC_struct                                rs_rx_edp_rx_mac_wr_reg_00_ec

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_ec  rs_rx_edp_rx_mac_wr_reg_00_ec;
struct _rs_rx_edp_rx_mac_wr_reg_00_ec {
    unsigned int reg_00_dprx_aln_time_min                   :16;
    unsigned int reg_00_dprx_ft_phy_init_width              :16;
};
#define rx_edp_rx_mac_wr_reg_00_ec(val) ((rs_rx_edp_rx_mac_wr_reg_00_ec*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_F0                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xF0)

#define RX_EDP_RX_MAC_WR_REG_00_F0_struct                                rs_rx_edp_rx_mac_wr_reg_00_f0

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_f0  rs_rx_edp_rx_mac_wr_reg_00_f0;
struct _rs_rx_edp_rx_mac_wr_reg_00_f0 {
    unsigned int reg_00_dprx_dsc_crc_vsgen_pos              :24;
    unsigned int reg_00_dprx_dsc_crc_sw_vs                  : 1;
    unsigned int reg_00_dprx_dsc_test_compressed_crc_sw_clr : 2;
    unsigned int reg_00_dprx_ft_fec_en_con                  : 4;
    unsigned int reserved                                   : 1;
};
#define rx_edp_rx_mac_wr_reg_00_f0(val) ((rs_rx_edp_rx_mac_wr_reg_00_f0*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_F4                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xF4)

#define RX_EDP_RX_MAC_WR_REG_00_F4_struct                                rs_rx_edp_rx_mac_wr_reg_00_f4

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_f4  rs_rx_edp_rx_mac_wr_reg_00_f4;
struct _rs_rx_edp_rx_mac_wr_reg_00_f4 {
    unsigned int reg_00_dprx_dpcd_editable_addr_start0      :20;
    unsigned int reg_00_dprx_aux_fw_ack                     : 8;
    unsigned int reg_00_dprx_aux_fw_en                      : 2;
    unsigned int reg_00_dprx_aux_fw_start                   : 1;
    unsigned int reserved                                   : 1;
};
#define rx_edp_rx_mac_wr_reg_00_f4(val) ((rs_rx_edp_rx_mac_wr_reg_00_f4*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_F8                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xF8)

#define RX_EDP_RX_MAC_WR_REG_00_F8_struct                                rs_rx_edp_rx_mac_wr_reg_00_f8

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_f8  rs_rx_edp_rx_mac_wr_reg_00_f8;
struct _rs_rx_edp_rx_mac_wr_reg_00_f8 {
    unsigned int reg_00_dprx_dpcd_editable_addr_end0        :20;
    unsigned int reg_00_dprx_aux_fw_len                     : 8;
    unsigned int reserved                                   : 4;
};
#define rx_edp_rx_mac_wr_reg_00_f8(val) ((rs_rx_edp_rx_mac_wr_reg_00_f8*)&(val))



#define RX_EDP_RX_MAC_WR_REG_00_FC                                       (HV_EDP_RX_MAC_WR_REG_00_BASE_ADDRESS + 0xFC)

#define RX_EDP_RX_MAC_WR_REG_00_FC_struct                                rs_rx_edp_rx_mac_wr_reg_00_fc

typedef struct _rs_rx_edp_rx_mac_wr_reg_00_fc  rs_rx_edp_rx_mac_wr_reg_00_fc;
struct _rs_rx_edp_rx_mac_wr_reg_00_fc {
    unsigned int reg_00_dprx_dpcd_editable_addr_end1        :20;
    unsigned int reg_00_dprx_ft_lane_swap                   : 8;
    unsigned int reserved                                   : 4;
};
#define rx_edp_rx_mac_wr_reg_00_fc(val) ((rs_rx_edp_rx_mac_wr_reg_00_fc*)&(val))



#endif