#ifndef _HV_PAGE_HT7315_DPU_SR_DPC_H_
#define _HV_PAGE_HT7315_DPU_SR_DPC_H_

#ifndef HV_DPU_SR_DPC_BASE_ADDRESS
    #define HV_DPU_SR_DPC_BASE_ADDRESS                                         0x11024600
#endif


#define DISP_TOP_DPU_SR_DPC_00                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_SR_DPC_00_struct                                    rs_disp_top_dpu_sr_dpc_00

typedef struct _rs_disp_top_dpu_sr_dpc_00  rs_disp_top_dpu_sr_dpc_00;
struct _rs_disp_top_dpu_sr_dpc_00 {
    unsigned int reg_en                                     : 1;
    unsigned int reg_en_no_latch                            : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_sr_dpc_00(val) ((rs_disp_top_dpu_sr_dpc_00*)&(val))



#define DISP_TOP_DPU_SR_DPC_04                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_SR_DPC_04_struct                                    rs_disp_top_dpu_sr_dpc_04

typedef struct _rs_disp_top_dpu_sr_dpc_04  rs_disp_top_dpu_sr_dpc_04;
struct _rs_disp_top_dpu_sr_dpc_04 {
    unsigned int reg_m_dec_unpack_sel                       : 1;
    unsigned int reg_m_upk_width                            :13;
    unsigned int reg_m_upk_height                           :13;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_sr_dpc_04(val) ((rs_disp_top_dpu_sr_dpc_04*)&(val))



#define DISP_TOP_DPU_SR_DPC_08                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_SR_DPC_08_struct                                    rs_disp_top_dpu_sr_dpc_08

typedef struct _rs_disp_top_dpu_sr_dpc_08  rs_disp_top_dpu_sr_dpc_08;
struct _rs_disp_top_dpu_sr_dpc_08 {
    unsigned int reg_m_upk_hbp                              : 8;
    unsigned int reg_m_upk_last_mode                        : 1;
    unsigned int reg_m_data_mode                            : 2;
    unsigned int reg_m_data_width                           : 2;
    unsigned int reg_m_frc_framesync_sel                    : 1;
    unsigned int reg_m_dec_clk_en                           : 1;
    unsigned int reg_m_unpack_clk_en                        : 1;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_sr_dpc_08(val) ((rs_disp_top_dpu_sr_dpc_08*)&(val))



#define DISP_TOP_DPU_SR_DPC_0C                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_SR_DPC_0C_struct                                    rs_disp_top_dpu_sr_dpc_0c

typedef struct _rs_disp_top_dpu_sr_dpc_0c  rs_disp_top_dpu_sr_dpc_0c;
struct _rs_disp_top_dpu_sr_dpc_0c {
    unsigned int reserved_l1                                : 1;
    unsigned int reg_s_upk_width                            :13;
    unsigned int reg_s_upk_height                           :13;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_sr_dpc_0c(val) ((rs_disp_top_dpu_sr_dpc_0c*)&(val))



#define DISP_TOP_DPU_SR_DPC_10                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_SR_DPC_10_struct                                    rs_disp_top_dpu_sr_dpc_10

typedef struct _rs_disp_top_dpu_sr_dpc_10  rs_disp_top_dpu_sr_dpc_10;
struct _rs_disp_top_dpu_sr_dpc_10 {
    unsigned int reg_s_upk_hbp                              : 8;
    unsigned int reg_s_upk_last_mode                        : 1;
    unsigned int reg_s_data_mode                            : 2;
    unsigned int reg_s_data_width                           : 2;
    unsigned int reg_s_frc_framesync_sel                    : 1;
    unsigned int reg_s_dec_clk_en                           : 1;
    unsigned int reg_s_unpack_clk_en                        : 1;
    unsigned int reg_sr_vd_dp_tbl_clk_en                    : 1;
    unsigned int reserved                                   :15;
};
#define disp_top_dpu_sr_dpc_10(val) ((rs_disp_top_dpu_sr_dpc_10*)&(val))



#define DISP_TOP_DPU_SR_DPC_14                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_SR_DPC_14_struct                                    rs_disp_top_dpu_sr_dpc_14

typedef struct _rs_disp_top_dpu_sr_dpc_14  rs_disp_top_dpu_sr_dpc_14;
struct _rs_disp_top_dpu_sr_dpc_14 {
    unsigned int reg_srp_mhi_hia_int_en                     : 3;
    unsigned int reg_srp_mhi_hib_int_mode                   : 6;
    unsigned int reg_srp_mhi_hib_int_clr                    : 3;
    unsigned int reserved                                   :20;
};
#define disp_top_dpu_sr_dpc_14(val) ((rs_disp_top_dpu_sr_dpc_14*)&(val))



#define DISP_TOP_DPU_SR_DPC_E0                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xE0)

#define DISP_TOP_DPU_SR_DPC_E0_struct                                    rs_disp_top_dpu_sr_dpc_e0

typedef struct _rs_disp_top_dpu_sr_dpc_e0  rs_disp_top_dpu_sr_dpc_e0;
struct _rs_disp_top_dpu_sr_dpc_e0 {
    unsigned int regr_srp_mhi_int_without_mask              : 3;
    unsigned int regr_srp_mhi_int_with_mask                 : 3;
    unsigned int reserved                                   :26;
};
#define disp_top_dpu_sr_dpc_e0(val) ((rs_disp_top_dpu_sr_dpc_e0*)&(val))



#define DISP_TOP_DPU_SR_DPC_E4                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xE4)

#define DISP_TOP_DPU_SR_DPC_E4_struct                                    rs_disp_top_dpu_sr_dpc_e4

typedef struct _rs_disp_top_dpu_sr_dpc_e4  rs_disp_top_dpu_sr_dpc_e4;
struct _rs_disp_top_dpu_sr_dpc_e4 {
    unsigned int mem_reg_0                                  :32;
};
#define disp_top_dpu_sr_dpc_e4(val) ((rs_disp_top_dpu_sr_dpc_e4*)&(val))



#define DISP_TOP_DPU_SR_DPC_E8                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xE8)

#define DISP_TOP_DPU_SR_DPC_E8_struct                                    rs_disp_top_dpu_sr_dpc_e8

typedef struct _rs_disp_top_dpu_sr_dpc_e8  rs_disp_top_dpu_sr_dpc_e8;
struct _rs_disp_top_dpu_sr_dpc_e8 {
    unsigned int mem_reg_1                                  :32;
};
#define disp_top_dpu_sr_dpc_e8(val) ((rs_disp_top_dpu_sr_dpc_e8*)&(val))



#define DISP_TOP_DPU_SR_DPC_EC                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xEC)

#define DISP_TOP_DPU_SR_DPC_EC_struct                                    rs_disp_top_dpu_sr_dpc_ec

typedef struct _rs_disp_top_dpu_sr_dpc_ec  rs_disp_top_dpu_sr_dpc_ec;
struct _rs_disp_top_dpu_sr_dpc_ec {
    unsigned int mem_ema_0                                  :32;
};
#define disp_top_dpu_sr_dpc_ec(val) ((rs_disp_top_dpu_sr_dpc_ec*)&(val))



#define DISP_TOP_DPU_SR_DPC_F0                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xF0)

#define DISP_TOP_DPU_SR_DPC_F0_struct                                    rs_disp_top_dpu_sr_dpc_f0

typedef struct _rs_disp_top_dpu_sr_dpc_f0  rs_disp_top_dpu_sr_dpc_f0;
struct _rs_disp_top_dpu_sr_dpc_f0 {
    unsigned int mem_ema_1                                  :32;
};
#define disp_top_dpu_sr_dpc_f0(val) ((rs_disp_top_dpu_sr_dpc_f0*)&(val))



#define DISP_TOP_DPU_SR_DPC_F4                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xF4)

#define DISP_TOP_DPU_SR_DPC_F4_struct                                    rs_disp_top_dpu_sr_dpc_f4

typedef struct _rs_disp_top_dpu_sr_dpc_f4  rs_disp_top_dpu_sr_dpc_f4;
struct _rs_disp_top_dpu_sr_dpc_f4 {
    unsigned int mem_ema_2                                  :32;
};
#define disp_top_dpu_sr_dpc_f4(val) ((rs_disp_top_dpu_sr_dpc_f4*)&(val))



#define DISP_TOP_DPU_SR_DPC_F8                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xF8)

#define DISP_TOP_DPU_SR_DPC_F8_struct                                    rs_disp_top_dpu_sr_dpc_f8

typedef struct _rs_disp_top_dpu_sr_dpc_f8  rs_disp_top_dpu_sr_dpc_f8;
struct _rs_disp_top_dpu_sr_dpc_f8 {
    unsigned int mem_ema_3                                  :32;
};
#define disp_top_dpu_sr_dpc_f8(val) ((rs_disp_top_dpu_sr_dpc_f8*)&(val))



#define DISP_TOP_DPU_SR_DPC_FC                                           (HV_DPU_SR_DPC_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_SR_DPC_FC_struct                                    rs_disp_top_dpu_sr_dpc_fc

typedef struct _rs_disp_top_dpu_sr_dpc_fc  rs_disp_top_dpu_sr_dpc_fc;
struct _rs_disp_top_dpu_sr_dpc_fc {
    unsigned int mem_ro_0                                   :16;
    unsigned int mem_ro_1                                   :16;
};
#define disp_top_dpu_sr_dpc_fc(val) ((rs_disp_top_dpu_sr_dpc_fc*)&(val))



#endif