#ifndef _HV_PAGE_HT7315_HDMI21_RX_INT_01_H_
#define _HV_PAGE_HT7315_HDMI21_RX_INT_01_H_

#ifndef HV_HDMI21_RX_INT_01_BASE_ADDRESS
    #define HV_HDMI21_RX_INT_01_BASE_ADDRESS                                         0x1104E500
#endif


#define RX_HDMI21_RX_INT_01_00                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX_INT_01_00_struct                                    rs_rx_hdmi21_rx_int_01_00

typedef struct _rs_rx_hdmi21_rx_int_01_00  rs_rx_hdmi21_rx_int_01_00;
struct _rs_rx_hdmi21_rx_int_01_00 {
    unsigned int reg_01_pll_lck_chg_int_byp                 : 1;
    unsigned int reg_01_scdccfgchange_int_byp               : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_byp          : 1;
    unsigned int reg_01_scdcscstatuschange_int_byp          : 1;
    unsigned int reg_01_hd21_decode_err_all_int_byp         : 1;
    unsigned int reg_01_ltp_int_byp                         : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_byp            : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_byp            : 1;
    unsigned int reg_01_pkt_error_int_byp                   : 1;
    unsigned int reg_01_clk_frq_stbl_int_byp                : 1;
    unsigned int reg_01_clk_frq_unstbl_int_byp              : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_byp         : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_byp           : 1;
    unsigned int reg_01_hd20_deskew_lock_int_byp            : 1;
    unsigned int reg_01_hd21_deskew_lock_int_byp            : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_byp      : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_byp             : 1;
    unsigned int reg_01_aud_afif_th_max_int_byp             : 1;
    unsigned int reg_01_aud_afif_th_min_int_byp             : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_byp           : 1;
    unsigned int reg_01_aud_afif_underfl_int_byp            : 1;
    unsigned int reg_01_pd_fif_new_entry_int_byp            : 1;
    unsigned int reg_01_pd_fif_overfl_int_byp               : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_byp          : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_byp          : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_byp        : 1;
    unsigned int reg_01_pd_fif_underfl_int_byp              : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_byp             : 1;
    unsigned int reg_01_acr_cts_chg_int_byp                 : 1;
};
#define rx_hdmi21_rx_int_01_00(val) ((rs_rx_hdmi21_rx_int_01_00*)&(val))



#define RX_HDMI21_RX_INT_01_04                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX_INT_01_04_struct                                    rs_rx_hdmi21_rx_int_01_04

typedef struct _rs_rx_hdmi21_rx_int_01_04  rs_rx_hdmi21_rx_int_01_04;
struct _rs_rx_hdmi21_rx_int_01_04 {
    unsigned int reg_01_acr_n_chg_int_byp                   : 1;
    unsigned int reg_01_acr_rcv_int_byp                     : 1;
    unsigned int reg_01_aif_cks_chg_int_byp                 : 1;
    unsigned int reg_01_aif_rcv_int_byp                     : 1;
    unsigned int reg_01_amp_chg_int_byp                     : 1;
    unsigned int reg_01_amp_rcv_int_byp                     : 1;
    unsigned int reg_01_aud_type_chg_int_byp                : 1;
    unsigned int reg_01_avi_cks_chg_int_byp                 : 1;
    unsigned int reg_01_avi_rcv_chg_int_byp                 : 1;
    unsigned int reg_01_ctsn_cnt_int_byp                    : 1;
    unsigned int reg_01_drm_cks_chg_int_byp                 : 1;
    unsigned int reg_01_drm_rcv_chg_int_byp                 : 1;
    unsigned int reg_01_gcp_rcv_int_byp                     : 1;
    unsigned int reg_01_gmd_cks_chg_int_byp                 : 1;
    unsigned int reg_01_gmd_rcv_int_byp                     : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_byp             : 1;
    unsigned int reg_01_ntscvbi_rcv_int_byp                 : 1;
    unsigned int reg_01_spd_rcv_int_byp                     : 1;
    unsigned int reg_01_vsi20_rcv_int_byp                   : 1;
    unsigned int reg_01_vsi_cks_chg_int_byp                 : 1;
    unsigned int reg_01_vsi_rcv_int_byp                     : 1;
    unsigned int reg_01_sck_stable_int_byp                  : 1;
    unsigned int reg_01_emp_rcv_int_byp                     : 1;
    unsigned int reg_01_spd_cks_int_byp                     : 1;
    unsigned int reg_01_tmds_timing_chg_int_byp             : 1;
    unsigned int reg_01_rx_timing_stable_int_byp            : 1;
    unsigned int reg_01_phy_config_int_byp                  : 1;
    unsigned int reg_01_standby_int_byp                     : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_byp          : 1;
    unsigned int reg_01_video_interlaced_det_int_byp        : 1;
    unsigned int reg_01_gcp_cd_chg_int_byp                  : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_04(val) ((rs_rx_hdmi21_rx_int_01_04*)&(val))



#define RX_HDMI21_RX_INT_01_08                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX_INT_01_08_struct                                    rs_rx_hdmi21_rx_int_01_08

typedef struct _rs_rx_hdmi21_rx_int_01_08  rs_rx_hdmi21_rx_int_01_08;
struct _rs_rx_hdmi21_rx_int_01_08 {
    unsigned int reg_01_pll_lck_chg_int_en                  : 1;
    unsigned int reg_01_scdccfgchange_int_en                : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_en           : 1;
    unsigned int reg_01_scdcscstatuschange_int_en           : 1;
    unsigned int reg_01_hd21_decode_err_all_int_en          : 1;
    unsigned int reg_01_ltp_int_en                          : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_en             : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_en             : 1;
    unsigned int reg_01_pkt_error_int_en                    : 1;
    unsigned int reg_01_clk_frq_stbl_int_en                 : 1;
    unsigned int reg_01_clk_frq_unstbl_int_en               : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_en          : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_en            : 1;
    unsigned int reg_01_hd20_deskew_lock_int_en             : 1;
    unsigned int reg_01_hd21_deskew_lock_int_en             : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_en       : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_en              : 1;
    unsigned int reg_01_aud_afif_th_max_int_en              : 1;
    unsigned int reg_01_aud_afif_th_min_int_en              : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_en            : 1;
    unsigned int reg_01_aud_afif_underfl_int_en             : 1;
    unsigned int reg_01_pd_fif_new_entry_int_en             : 1;
    unsigned int reg_01_pd_fif_overfl_int_en                : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_en           : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_en           : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_en         : 1;
    unsigned int reg_01_pd_fif_underfl_int_en               : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_en              : 1;
    unsigned int reg_01_acr_cts_chg_int_en                  : 1;
};
#define rx_hdmi21_rx_int_01_08(val) ((rs_rx_hdmi21_rx_int_01_08*)&(val))



#define RX_HDMI21_RX_INT_01_0C                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x0C)

#define RX_HDMI21_RX_INT_01_0C_struct                                    rs_rx_hdmi21_rx_int_01_0c

typedef struct _rs_rx_hdmi21_rx_int_01_0c  rs_rx_hdmi21_rx_int_01_0c;
struct _rs_rx_hdmi21_rx_int_01_0c {
    unsigned int reg_01_acr_n_chg_int_en                    : 1;
    unsigned int reg_01_acr_rcv_int_en                      : 1;
    unsigned int reg_01_aif_cks_chg_int_en                  : 1;
    unsigned int reg_01_aif_rcv_int_en                      : 1;
    unsigned int reg_01_amp_chg_int_en                      : 1;
    unsigned int reg_01_amp_rcv_int_en                      : 1;
    unsigned int reg_01_aud_type_chg_int_en                 : 1;
    unsigned int reg_01_avi_cks_chg_int_en                  : 1;
    unsigned int reg_01_avi_rcv_chg_int_en                  : 1;
    unsigned int reg_01_ctsn_cnt_int_en                     : 1;
    unsigned int reg_01_drm_cks_chg_int_en                  : 1;
    unsigned int reg_01_drm_rcv_chg_int_en                  : 1;
    unsigned int reg_01_gcp_rcv_int_en                      : 1;
    unsigned int reg_01_gmd_cks_chg_int_en                  : 1;
    unsigned int reg_01_gmd_rcv_int_en                      : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_en              : 1;
    unsigned int reg_01_ntscvbi_rcv_int_en                  : 1;
    unsigned int reg_01_spd_rcv_int_en                      : 1;
    unsigned int reg_01_vsi20_rcv_int_en                    : 1;
    unsigned int reg_01_vsi_cks_chg_int_en                  : 1;
    unsigned int reg_01_vsi_rcv_int_en                      : 1;
    unsigned int reg_01_sck_stable_int_en                   : 1;
    unsigned int reg_01_emp_rcv_int_en                      : 1;
    unsigned int reg_01_spd_cks_int_en                      : 1;
    unsigned int reg_01_tmds_timing_chg_int_en              : 1;
    unsigned int reg_01_rx_timing_stable_int_en             : 1;
    unsigned int reg_01_phy_config_int_en                   : 1;
    unsigned int reg_01_standby_int_en                      : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_en           : 1;
    unsigned int reg_01_video_interlaced_det_int_en         : 1;
    unsigned int reg_01_gcp_cd_chg_int_en                   : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_0c(val) ((rs_rx_hdmi21_rx_int_01_0c*)&(val))



#define RX_HDMI21_RX_INT_01_10                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x10)

#define RX_HDMI21_RX_INT_01_10_struct                                    rs_rx_hdmi21_rx_int_01_10

typedef struct _rs_rx_hdmi21_rx_int_01_10  rs_rx_hdmi21_rx_int_01_10;
struct _rs_rx_hdmi21_rx_int_01_10 {
    unsigned int reg_01_pll_lck_chg_int_clr                 : 1;
    unsigned int reg_01_scdccfgchange_int_clr               : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_clr          : 1;
    unsigned int reg_01_scdcscstatuschange_int_clr          : 1;
    unsigned int reg_01_hd21_decode_err_all_int_clr         : 1;
    unsigned int reg_01_ltp_int_clr                         : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_clr            : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_clr            : 1;
    unsigned int reg_01_pkt_error_int_clr                   : 1;
    unsigned int reg_01_clk_frq_stbl_int_clr                : 1;
    unsigned int reg_01_clk_frq_unstbl_int_clr              : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_clr         : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_clr           : 1;
    unsigned int reg_01_hd20_deskew_lock_int_clr            : 1;
    unsigned int reg_01_hd21_deskew_lock_int_clr            : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_clr      : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_clr             : 1;
    unsigned int reg_01_aud_afif_th_max_int_clr             : 1;
    unsigned int reg_01_aud_afif_th_min_int_clr             : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_clr           : 1;
    unsigned int reg_01_aud_afif_underfl_int_clr            : 1;
    unsigned int reg_01_pd_fif_new_entry_int_clr            : 1;
    unsigned int reg_01_pd_fif_overfl_int_clr               : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_clr          : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_clr          : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_clr        : 1;
    unsigned int reg_01_pd_fif_underfl_int_clr              : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_clr             : 1;
    unsigned int reg_01_acr_cts_chg_int_clr                 : 1;
};
#define rx_hdmi21_rx_int_01_10(val) ((rs_rx_hdmi21_rx_int_01_10*)&(val))



#define RX_HDMI21_RX_INT_01_14                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x14)

#define RX_HDMI21_RX_INT_01_14_struct                                    rs_rx_hdmi21_rx_int_01_14

typedef struct _rs_rx_hdmi21_rx_int_01_14  rs_rx_hdmi21_rx_int_01_14;
struct _rs_rx_hdmi21_rx_int_01_14 {
    unsigned int reg_01_acr_n_chg_int_clr                   : 1;
    unsigned int reg_01_acr_rcv_int_clr                     : 1;
    unsigned int reg_01_aif_cks_chg_int_clr                 : 1;
    unsigned int reg_01_aif_rcv_int_clr                     : 1;
    unsigned int reg_01_amp_chg_int_clr                     : 1;
    unsigned int reg_01_amp_rcv_int_clr                     : 1;
    unsigned int reg_01_aud_type_chg_int_clr                : 1;
    unsigned int reg_01_avi_cks_chg_int_clr                 : 1;
    unsigned int reg_01_avi_rcv_chg_int_clr                 : 1;
    unsigned int reg_01_ctsn_cnt_int_clr                    : 1;
    unsigned int reg_01_drm_cks_chg_int_clr                 : 1;
    unsigned int reg_01_drm_rcv_chg_int_clr                 : 1;
    unsigned int reg_01_gcp_rcv_int_clr                     : 1;
    unsigned int reg_01_gmd_cks_chg_int_clr                 : 1;
    unsigned int reg_01_gmd_rcv_int_clr                     : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_clr             : 1;
    unsigned int reg_01_ntscvbi_rcv_int_clr                 : 1;
    unsigned int reg_01_spd_rcv_int_clr                     : 1;
    unsigned int reg_01_vsi20_rcv_int_clr                   : 1;
    unsigned int reg_01_vsi_cks_chg_int_clr                 : 1;
    unsigned int reg_01_vsi_rcv_int_clr                     : 1;
    unsigned int reg_01_sck_stable_int_clr                  : 1;
    unsigned int reg_01_emp_rcv_int_clr                     : 1;
    unsigned int reg_01_spd_cks_int_clr                     : 1;
    unsigned int reg_01_tmds_timing_chg_int_clr             : 1;
    unsigned int reg_01_rx_timing_stable_int_clr            : 1;
    unsigned int reg_01_phy_config_int_clr                  : 1;
    unsigned int reg_01_standby_int_clr                     : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_clr          : 1;
    unsigned int reg_01_video_interlaced_det_int_clr        : 1;
    unsigned int reg_01_gcp_cd_chg_int_clr                  : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_14(val) ((rs_rx_hdmi21_rx_int_01_14*)&(val))



#define RX_HDMI21_RX_INT_01_18                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX_INT_01_18_struct                                    rs_rx_hdmi21_rx_int_01_18

typedef struct _rs_rx_hdmi21_rx_int_01_18  rs_rx_hdmi21_rx_int_01_18;
struct _rs_rx_hdmi21_rx_int_01_18 {
    unsigned int reg_01_pll_lck_chg_int_lvl_p               : 1;
    unsigned int reg_01_scdccfgchange_int_lvl_p             : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_lvl_p        : 1;
    unsigned int reg_01_scdcscstatuschange_int_lvl_p        : 1;
    unsigned int reg_01_hd21_decode_err_all_int_lvl_p       : 1;
    unsigned int reg_01_ltp_int_lvl_p                       : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_lvl_p          : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_lvl_p          : 1;
    unsigned int reg_01_pkt_error_int_lvl_p                 : 1;
    unsigned int reg_01_clk_frq_stbl_int_lvl_p              : 1;
    unsigned int reg_01_clk_frq_unstbl_int_lvl_p            : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_lvl_p       : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_lvl_p         : 1;
    unsigned int reg_01_hd20_deskew_lock_int_lvl_p          : 1;
    unsigned int reg_01_hd21_deskew_lock_int_lvl_p          : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_lvl_p    : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_lvl_p           : 1;
    unsigned int reg_01_aud_afif_th_max_int_lvl_p           : 1;
    unsigned int reg_01_aud_afif_th_min_int_lvl_p           : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_lvl_p         : 1;
    unsigned int reg_01_aud_afif_underfl_int_lvl_p          : 1;
    unsigned int reg_01_pd_fif_new_entry_int_lvl_p          : 1;
    unsigned int reg_01_pd_fif_overfl_int_lvl_p             : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_lvl_p        : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_lvl_p        : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_lvl_p      : 1;
    unsigned int reg_01_pd_fif_underfl_int_lvl_p            : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_lvl_p           : 1;
    unsigned int reg_01_acr_cts_chg_int_lvl_p               : 1;
};
#define rx_hdmi21_rx_int_01_18(val) ((rs_rx_hdmi21_rx_int_01_18*)&(val))



#define RX_HDMI21_RX_INT_01_1C                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX_INT_01_1C_struct                                    rs_rx_hdmi21_rx_int_01_1c

typedef struct _rs_rx_hdmi21_rx_int_01_1c  rs_rx_hdmi21_rx_int_01_1c;
struct _rs_rx_hdmi21_rx_int_01_1c {
    unsigned int reg_01_acr_n_chg_int_lvl_p                 : 1;
    unsigned int reg_01_acr_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_aif_cks_chg_int_lvl_p               : 1;
    unsigned int reg_01_aif_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_amp_chg_int_lvl_p                   : 1;
    unsigned int reg_01_amp_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_aud_type_chg_int_lvl_p              : 1;
    unsigned int reg_01_avi_cks_chg_int_lvl_p               : 1;
    unsigned int reg_01_avi_rcv_chg_int_lvl_p               : 1;
    unsigned int reg_01_ctsn_cnt_int_lvl_p                  : 1;
    unsigned int reg_01_drm_cks_chg_int_lvl_p               : 1;
    unsigned int reg_01_drm_rcv_chg_int_lvl_p               : 1;
    unsigned int reg_01_gcp_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_gmd_cks_chg_int_lvl_p               : 1;
    unsigned int reg_01_gmd_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_lvl_p           : 1;
    unsigned int reg_01_ntscvbi_rcv_int_lvl_p               : 1;
    unsigned int reg_01_spd_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_vsi20_rcv_int_lvl_p                 : 1;
    unsigned int reg_01_vsi_cks_chg_int_lvl_p               : 1;
    unsigned int reg_01_vsi_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_sck_stable_int_lvl_p                : 1;
    unsigned int reg_01_emp_rcv_int_lvl_p                   : 1;
    unsigned int reg_01_spd_cks_int_lvl_p                   : 1;
    unsigned int reg_01_tmds_timing_chg_int_lvl_p           : 1;
    unsigned int reg_01_rx_timing_stable_int_lvl_p          : 1;
    unsigned int reg_01_phy_config_int_lvl_p                : 1;
    unsigned int reg_01_standby_int_lvl_p                   : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_lvl_p        : 1;
    unsigned int reg_01_video_interlaced_det_int_lvl_p      : 1;
    unsigned int reg_01_gcp_cd_chg_int_lvl_p                : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_1c(val) ((rs_rx_hdmi21_rx_int_01_1c*)&(val))



#define RX_HDMI21_RX_INT_01_20                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x20)

#define RX_HDMI21_RX_INT_01_20_struct                                    rs_rx_hdmi21_rx_int_01_20

typedef struct _rs_rx_hdmi21_rx_int_01_20  rs_rx_hdmi21_rx_int_01_20;
struct _rs_rx_hdmi21_rx_int_01_20 {
    unsigned int reg_01_pll_lck_chg_int_lvl_n               : 1;
    unsigned int reg_01_scdccfgchange_int_lvl_n             : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_lvl_n        : 1;
    unsigned int reg_01_scdcscstatuschange_int_lvl_n        : 1;
    unsigned int reg_01_hd21_decode_err_all_int_lvl_n       : 1;
    unsigned int reg_01_ltp_int_lvl_n                       : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_lvl_n          : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_lvl_n          : 1;
    unsigned int reg_01_pkt_error_int_lvl_n                 : 1;
    unsigned int reg_01_clk_frq_stbl_int_lvl_n              : 1;
    unsigned int reg_01_clk_frq_unstbl_int_lvl_n            : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_lvl_n       : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_lvl_n         : 1;
    unsigned int reg_01_hd20_deskew_lock_int_lvl_n          : 1;
    unsigned int reg_01_hd21_deskew_lock_int_lvl_n          : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_lvl_n    : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_lvl_n           : 1;
    unsigned int reg_01_aud_afif_th_max_int_lvl_n           : 1;
    unsigned int reg_01_aud_afif_th_min_int_lvl_n           : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_lvl_n         : 1;
    unsigned int reg_01_aud_afif_underfl_int_lvl_n          : 1;
    unsigned int reg_01_pd_fif_new_entry_int_lvl_n          : 1;
    unsigned int reg_01_pd_fif_overfl_int_lvl_n             : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_lvl_n        : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_lvl_n        : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_lvl_n      : 1;
    unsigned int reg_01_pd_fif_underfl_int_lvl_n            : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_lvl_n           : 1;
    unsigned int reg_01_acr_cts_chg_int_lvl_n               : 1;
};
#define rx_hdmi21_rx_int_01_20(val) ((rs_rx_hdmi21_rx_int_01_20*)&(val))



#define RX_HDMI21_RX_INT_01_24                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x24)

#define RX_HDMI21_RX_INT_01_24_struct                                    rs_rx_hdmi21_rx_int_01_24

typedef struct _rs_rx_hdmi21_rx_int_01_24  rs_rx_hdmi21_rx_int_01_24;
struct _rs_rx_hdmi21_rx_int_01_24 {
    unsigned int reg_01_acr_n_chg_int_lvl_n                 : 1;
    unsigned int reg_01_acr_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_aif_cks_chg_int_lvl_n               : 1;
    unsigned int reg_01_aif_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_amp_chg_int_lvl_n                   : 1;
    unsigned int reg_01_amp_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_aud_type_chg_int_lvl_n              : 1;
    unsigned int reg_01_avi_cks_chg_int_lvl_n               : 1;
    unsigned int reg_01_avi_rcv_chg_int_lvl_n               : 1;
    unsigned int reg_01_ctsn_cnt_int_lvl_n                  : 1;
    unsigned int reg_01_drm_cks_chg_int_lvl_n               : 1;
    unsigned int reg_01_drm_rcv_chg_int_lvl_n               : 1;
    unsigned int reg_01_gcp_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_gmd_cks_chg_int_lvl_n               : 1;
    unsigned int reg_01_gmd_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_lvl_n           : 1;
    unsigned int reg_01_ntscvbi_rcv_int_lvl_n               : 1;
    unsigned int reg_01_spd_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_vsi20_rcv_int_lvl_n                 : 1;
    unsigned int reg_01_vsi_cks_chg_int_lvl_n               : 1;
    unsigned int reg_01_vsi_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_sck_stable_int_lvl_n                : 1;
    unsigned int reg_01_emp_rcv_int_lvl_n                   : 1;
    unsigned int reg_01_spd_cks_int_lvl_n                   : 1;
    unsigned int reg_01_tmds_timing_chg_int_lvl_n           : 1;
    unsigned int reg_01_rx_timing_stable_int_lvl_n          : 1;
    unsigned int reg_01_phy_config_int_lvl_n                : 1;
    unsigned int reg_01_standby_int_lvl_n                   : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_lvl_n        : 1;
    unsigned int reg_01_video_interlaced_det_int_lvl_n      : 1;
    unsigned int reg_01_gcp_cd_chg_int_lvl_n                : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_24(val) ((rs_rx_hdmi21_rx_int_01_24*)&(val))



#define RX_HDMI21_RX_INT_01_28                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x28)

#define RX_HDMI21_RX_INT_01_28_struct                                    rs_rx_hdmi21_rx_int_01_28

typedef struct _rs_rx_hdmi21_rx_int_01_28  rs_rx_hdmi21_rx_int_01_28;
struct _rs_rx_hdmi21_rx_int_01_28 {
    unsigned int reg_01_pll_lck_chg_int_edg_p               : 1;
    unsigned int reg_01_scdccfgchange_int_edg_p             : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_edg_p        : 1;
    unsigned int reg_01_scdcscstatuschange_int_edg_p        : 1;
    unsigned int reg_01_hd21_decode_err_all_int_edg_p       : 1;
    unsigned int reg_01_ltp_int_edg_p                       : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_edg_p          : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_edg_p          : 1;
    unsigned int reg_01_pkt_error_int_edg_p                 : 1;
    unsigned int reg_01_clk_frq_stbl_int_edg_p              : 1;
    unsigned int reg_01_clk_frq_unstbl_int_edg_p            : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_edg_p       : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_edg_p         : 1;
    unsigned int reg_01_hd20_deskew_lock_int_edg_p          : 1;
    unsigned int reg_01_hd21_deskew_lock_int_edg_p          : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_edg_p    : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_edg_p           : 1;
    unsigned int reg_01_aud_afif_th_max_int_edg_p           : 1;
    unsigned int reg_01_aud_afif_th_min_int_edg_p           : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_edg_p         : 1;
    unsigned int reg_01_aud_afif_underfl_int_edg_p          : 1;
    unsigned int reg_01_pd_fif_new_entry_int_edg_p          : 1;
    unsigned int reg_01_pd_fif_overfl_int_edg_p             : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_edg_p        : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_edg_p        : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_edg_p      : 1;
    unsigned int reg_01_pd_fif_underfl_int_edg_p            : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_edg_p           : 1;
    unsigned int reg_01_acr_cts_chg_int_edg_p               : 1;
};
#define rx_hdmi21_rx_int_01_28(val) ((rs_rx_hdmi21_rx_int_01_28*)&(val))



#define RX_HDMI21_RX_INT_01_2C                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x2C)

#define RX_HDMI21_RX_INT_01_2C_struct                                    rs_rx_hdmi21_rx_int_01_2c

typedef struct _rs_rx_hdmi21_rx_int_01_2c  rs_rx_hdmi21_rx_int_01_2c;
struct _rs_rx_hdmi21_rx_int_01_2c {
    unsigned int reg_01_acr_n_chg_int_edg_p                 : 1;
    unsigned int reg_01_acr_rcv_int_edg_p                   : 1;
    unsigned int reg_01_aif_cks_chg_int_edg_p               : 1;
    unsigned int reg_01_aif_rcv_int_edg_p                   : 1;
    unsigned int reg_01_amp_chg_int_edg_p                   : 1;
    unsigned int reg_01_amp_rcv_int_edg_p                   : 1;
    unsigned int reg_01_aud_type_chg_int_edg_p              : 1;
    unsigned int reg_01_avi_cks_chg_int_edg_p               : 1;
    unsigned int reg_01_avi_rcv_chg_int_edg_p               : 1;
    unsigned int reg_01_ctsn_cnt_int_edg_p                  : 1;
    unsigned int reg_01_drm_cks_chg_int_edg_p               : 1;
    unsigned int reg_01_drm_rcv_chg_int_edg_p               : 1;
    unsigned int reg_01_gcp_rcv_int_edg_p                   : 1;
    unsigned int reg_01_gmd_cks_chg_int_edg_p               : 1;
    unsigned int reg_01_gmd_rcv_int_edg_p                   : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_edg_p           : 1;
    unsigned int reg_01_ntscvbi_rcv_int_edg_p               : 1;
    unsigned int reg_01_spd_rcv_int_edg_p                   : 1;
    unsigned int reg_01_vsi20_rcv_int_edg_p                 : 1;
    unsigned int reg_01_vsi_cks_chg_int_edg_p               : 1;
    unsigned int reg_01_vsi_rcv_int_edg_p                   : 1;
    unsigned int reg_01_sck_stable_int_edg_p                : 1;
    unsigned int reg_01_emp_rcv_int_edg_p                   : 1;
    unsigned int reg_01_spd_cks_int_edg_p                   : 1;
    unsigned int reg_01_tmds_timing_chg_int_edg_p           : 1;
    unsigned int reg_01_rx_timing_stable_int_edg_p          : 1;
    unsigned int reg_01_phy_config_int_edg_p                : 1;
    unsigned int reg_01_standby_int_edg_p                   : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_edg_p        : 1;
    unsigned int reg_01_video_interlaced_det_int_edg_p      : 1;
    unsigned int reg_01_gcp_cd_chg_int_edg_p                : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_2c(val) ((rs_rx_hdmi21_rx_int_01_2c*)&(val))



#define RX_HDMI21_RX_INT_01_30                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x30)

#define RX_HDMI21_RX_INT_01_30_struct                                    rs_rx_hdmi21_rx_int_01_30

typedef struct _rs_rx_hdmi21_rx_int_01_30  rs_rx_hdmi21_rx_int_01_30;
struct _rs_rx_hdmi21_rx_int_01_30 {
    unsigned int reg_01_pll_lck_chg_int_edg_n               : 1;
    unsigned int reg_01_scdccfgchange_int_edg_n             : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_edg_n        : 1;
    unsigned int reg_01_scdcscstatuschange_int_edg_n        : 1;
    unsigned int reg_01_hd21_decode_err_all_int_edg_n       : 1;
    unsigned int reg_01_ltp_int_edg_n                       : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_edg_n          : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_edg_n          : 1;
    unsigned int reg_01_pkt_error_int_edg_n                 : 1;
    unsigned int reg_01_clk_frq_stbl_int_edg_n              : 1;
    unsigned int reg_01_clk_frq_unstbl_int_edg_n            : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_edg_n       : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_edg_n         : 1;
    unsigned int reg_01_hd20_deskew_lock_int_edg_n          : 1;
    unsigned int reg_01_hd21_deskew_lock_int_edg_n          : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_edg_n    : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_edg_n           : 1;
    unsigned int reg_01_aud_afif_th_max_int_edg_n           : 1;
    unsigned int reg_01_aud_afif_th_min_int_edg_n           : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_edg_n         : 1;
    unsigned int reg_01_aud_afif_underfl_int_edg_n          : 1;
    unsigned int reg_01_pd_fif_new_entry_int_edg_n          : 1;
    unsigned int reg_01_pd_fif_overfl_int_edg_n             : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_edg_n        : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_edg_n        : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_edg_n      : 1;
    unsigned int reg_01_pd_fif_underfl_int_edg_n            : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_edg_n           : 1;
    unsigned int reg_01_acr_cts_chg_int_edg_n               : 1;
};
#define rx_hdmi21_rx_int_01_30(val) ((rs_rx_hdmi21_rx_int_01_30*)&(val))



#define RX_HDMI21_RX_INT_01_34                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX_INT_01_34_struct                                    rs_rx_hdmi21_rx_int_01_34

typedef struct _rs_rx_hdmi21_rx_int_01_34  rs_rx_hdmi21_rx_int_01_34;
struct _rs_rx_hdmi21_rx_int_01_34 {
    unsigned int reg_01_acr_n_chg_int_edg_n                 : 1;
    unsigned int reg_01_acr_rcv_int_edg_n                   : 1;
    unsigned int reg_01_aif_cks_chg_int_edg_n               : 1;
    unsigned int reg_01_aif_rcv_int_edg_n                   : 1;
    unsigned int reg_01_amp_chg_int_edg_n                   : 1;
    unsigned int reg_01_amp_rcv_int_edg_n                   : 1;
    unsigned int reg_01_aud_type_chg_int_edg_n              : 1;
    unsigned int reg_01_avi_cks_chg_int_edg_n               : 1;
    unsigned int reg_01_avi_rcv_chg_int_edg_n               : 1;
    unsigned int reg_01_ctsn_cnt_int_edg_n                  : 1;
    unsigned int reg_01_drm_cks_chg_int_edg_n               : 1;
    unsigned int reg_01_drm_rcv_chg_int_edg_n               : 1;
    unsigned int reg_01_gcp_rcv_int_edg_n                   : 1;
    unsigned int reg_01_gmd_cks_chg_int_edg_n               : 1;
    unsigned int reg_01_gmd_rcv_int_edg_n                   : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_edg_n           : 1;
    unsigned int reg_01_ntscvbi_rcv_int_edg_n               : 1;
    unsigned int reg_01_spd_rcv_int_edg_n                   : 1;
    unsigned int reg_01_vsi20_rcv_int_edg_n                 : 1;
    unsigned int reg_01_vsi_cks_chg_int_edg_n               : 1;
    unsigned int reg_01_vsi_rcv_int_edg_n                   : 1;
    unsigned int reg_01_sck_stable_int_edg_n                : 1;
    unsigned int reg_01_emp_rcv_int_edg_n                   : 1;
    unsigned int reg_01_spd_cks_int_edg_n                   : 1;
    unsigned int reg_01_tmds_timing_chg_int_edg_n           : 1;
    unsigned int reg_01_rx_timing_stable_int_edg_n          : 1;
    unsigned int reg_01_phy_config_int_edg_n                : 1;
    unsigned int reg_01_standby_int_edg_n                   : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_edg_n        : 1;
    unsigned int reg_01_video_interlaced_det_int_edg_n      : 1;
    unsigned int reg_01_gcp_cd_chg_int_edg_n                : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_34(val) ((rs_rx_hdmi21_rx_int_01_34*)&(val))



#define RX_HDMI21_RX_INT_01_38                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX_INT_01_38_struct                                    rs_rx_hdmi21_rx_int_01_38

typedef struct _rs_rx_hdmi21_rx_int_01_38  rs_rx_hdmi21_rx_int_01_38;
struct _rs_rx_hdmi21_rx_int_01_38 {
    unsigned int reg_01_pll_lck_chg_int_sta                 : 1;
    unsigned int reg_01_scdccfgchange_int_sta               : 1;
    unsigned int reg_01_scdctmdsccfgchange_int_sta          : 1;
    unsigned int reg_01_scdcscstatuschange_int_sta          : 1;
    unsigned int reg_01_hd21_decode_err_all_int_sta         : 1;
    unsigned int reg_01_ltp_int_sta                         : 1;
    unsigned int reg_01_lnx_ltp_req_alle_int_sta            : 1;
    unsigned int reg_01_lnx_ltp_req_allf_int_sta            : 1;
    unsigned int reg_01_pkt_error_int_sta                   : 1;
    unsigned int reg_01_clk_frq_stbl_int_sta                : 1;
    unsigned int reg_01_clk_frq_unstbl_int_sta              : 1;
    unsigned int reg_01_scdc_frl_rate_txset_int_sta         : 1;
    unsigned int reg_01_scdc_frl_start_rd_int_sta           : 1;
    unsigned int reg_01_hd20_deskew_lock_int_sta            : 1;
    unsigned int reg_01_hd21_deskew_lock_int_sta            : 1;
    unsigned int reg_01_int_fr_auto_eq_retrain_int_sta      : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_aud_afif_overfl_int_sta             : 1;
    unsigned int reg_01_aud_afif_th_max_int_sta             : 1;
    unsigned int reg_01_aud_afif_th_min_int_sta             : 1;
    unsigned int reg_01_aud_afif_ths_pass_int_sta           : 1;
    unsigned int reg_01_aud_afif_underfl_int_sta            : 1;
    unsigned int reg_01_pd_fif_new_entry_int_sta            : 1;
    unsigned int reg_01_pd_fif_overfl_int_sta               : 1;
    unsigned int reg_01_pd_fif_th_max_pass_int_sta          : 1;
    unsigned int reg_01_pd_fif_th_min_pass_int_sta          : 1;
    unsigned int reg_01_pd_fif_th_start_pass_int_sta        : 1;
    unsigned int reg_01_pd_fif_underfl_int_sta              : 1;
    unsigned int reg_01_gcp_av_mute_chg_int_sta             : 1;
    unsigned int reg_01_acr_cts_chg_int_sta                 : 1;
};
#define rx_hdmi21_rx_int_01_38(val) ((rs_rx_hdmi21_rx_int_01_38*)&(val))



#define RX_HDMI21_RX_INT_01_3C                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX_INT_01_3C_struct                                    rs_rx_hdmi21_rx_int_01_3c

typedef struct _rs_rx_hdmi21_rx_int_01_3c  rs_rx_hdmi21_rx_int_01_3c;
struct _rs_rx_hdmi21_rx_int_01_3c {
    unsigned int reg_01_acr_n_chg_int_sta                   : 1;
    unsigned int reg_01_acr_rcv_int_sta                     : 1;
    unsigned int reg_01_aif_cks_chg_int_sta                 : 1;
    unsigned int reg_01_aif_rcv_int_sta                     : 1;
    unsigned int reg_01_amp_chg_int_sta                     : 1;
    unsigned int reg_01_amp_rcv_int_sta                     : 1;
    unsigned int reg_01_aud_type_chg_int_sta                : 1;
    unsigned int reg_01_avi_cks_chg_int_sta                 : 1;
    unsigned int reg_01_avi_rcv_chg_int_sta                 : 1;
    unsigned int reg_01_ctsn_cnt_int_sta                    : 1;
    unsigned int reg_01_drm_cks_chg_int_sta                 : 1;
    unsigned int reg_01_drm_rcv_chg_int_sta                 : 1;
    unsigned int reg_01_gcp_rcv_int_sta                     : 1;
    unsigned int reg_01_gmd_cks_chg_int_sta                 : 1;
    unsigned int reg_01_gmd_rcv_int_sta                     : 1;
    unsigned int reg_01_ntscvbi_cks_chg_int_sta             : 1;
    unsigned int reg_01_ntscvbi_rcv_int_sta                 : 1;
    unsigned int reg_01_spd_rcv_int_sta                     : 1;
    unsigned int reg_01_vsi20_rcv_int_sta                   : 1;
    unsigned int reg_01_vsi_cks_chg_int_sta                 : 1;
    unsigned int reg_01_vsi_rcv_int_sta                     : 1;
    unsigned int reg_01_sck_stable_int_sta                  : 1;
    unsigned int reg_01_emp_rcv_int_sta                     : 1;
    unsigned int reg_01_spd_cks_int_sta                     : 1;
    unsigned int reg_01_tmds_timing_chg_int_sta             : 1;
    unsigned int reg_01_rx_timing_stable_int_sta            : 1;
    unsigned int reg_01_phy_config_int_sta                  : 1;
    unsigned int reg_01_standby_int_sta                     : 1;
    unsigned int reg_01_lane_pll_fast_lock_int_sta          : 1;
    unsigned int reg_01_video_interlaced_det_int_sta        : 1;
    unsigned int reg_01_gcp_cd_chg_int_sta                  : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_int_01_3c(val) ((rs_rx_hdmi21_rx_int_01_3c*)&(val))



#define RX_HDMI21_RX_INT_01_60                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x60)

#define RX_HDMI21_RX_INT_01_60_struct                                    rs_rx_hdmi21_rx_int_01_60

typedef struct _rs_rx_hdmi21_rx_int_01_60  rs_rx_hdmi21_rx_int_01_60;
struct _rs_rx_hdmi21_rx_int_01_60 {
    unsigned int reg_01_access_00_int_byp                   : 1;
    unsigned int reg_01_access_08_int_byp                   : 1;
    unsigned int reg_01_access_0a_int_byp                   : 1;
    unsigned int reg_01_access_10_int_byp                   : 1;
    unsigned int reg_01_access_15_int_byp                   : 1;
    unsigned int reg_01_access_18_int_byp                   : 1;
    unsigned int reg_01_access_30_int_byp                   : 1;
    unsigned int reg_01_access_40_int_byp                   : 1;
    unsigned int reg_01_access_43_int_byp                   : 1;
    unsigned int reg_01_access_50_int_byp                   : 1;
    unsigned int reg_01_access_51_int_byp                   : 1;
    unsigned int reg_01_access_60_int_byp                   : 1;
    unsigned int reg_01_access_70_int_byp                   : 1;
    unsigned int reg_01_access_80_int_byp                   : 1;
    unsigned int reg_01_wmsg_id_2_int_byp                   : 1;
    unsigned int reg_01_wmsg_id_4_int_byp                   : 1;
    unsigned int reg_01_wmsg_id_5_int_byp                   : 1;
    unsigned int reg_01_wmsg_id_9_int_byp                   : 1;
    unsigned int reg_01_wmsg_id_11_int_byp                  : 1;
    unsigned int reg_01_wmsg_id_15_int_byp                  : 1;
    unsigned int reg_01_wmsg_id_16_int_byp                  : 1;
    unsigned int reserved                                   :11;
};
#define rx_hdmi21_rx_int_01_60(val) ((rs_rx_hdmi21_rx_int_01_60*)&(val))



#define RX_HDMI21_RX_INT_01_64                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x64)

#define RX_HDMI21_RX_INT_01_64_struct                                    rs_rx_hdmi21_rx_int_01_64

typedef struct _rs_rx_hdmi21_rx_int_01_64  rs_rx_hdmi21_rx_int_01_64;
struct _rs_rx_hdmi21_rx_int_01_64 {
    unsigned int reg_01_access_00_int_en                    : 1;
    unsigned int reg_01_access_08_int_en                    : 1;
    unsigned int reg_01_access_0a_int_en                    : 1;
    unsigned int reg_01_access_10_int_en                    : 1;
    unsigned int reg_01_access_15_int_en                    : 1;
    unsigned int reg_01_access_18_int_en                    : 1;
    unsigned int reg_01_access_30_int_en                    : 1;
    unsigned int reg_01_access_40_int_en                    : 1;
    unsigned int reg_01_access_43_int_en                    : 1;
    unsigned int reg_01_access_50_int_en                    : 1;
    unsigned int reg_01_access_51_int_en                    : 1;
    unsigned int reg_01_access_60_int_en                    : 1;
    unsigned int reg_01_access_70_int_en                    : 1;
    unsigned int reg_01_access_80_int_en                    : 1;
    unsigned int reg_01_wmsg_id_2_int_en                    : 1;
    unsigned int reg_01_wmsg_id_4_int_en                    : 1;
    unsigned int reg_01_wmsg_id_5_int_en                    : 1;
    unsigned int reg_01_wmsg_id_9_int_en                    : 1;
    unsigned int reg_01_wmsg_id_11_int_en                   : 1;
    unsigned int reg_01_wmsg_id_15_int_en                   : 1;
    unsigned int reg_01_wmsg_id_16_int_en                   : 1;
    unsigned int reserved                                   :11;
};
#define rx_hdmi21_rx_int_01_64(val) ((rs_rx_hdmi21_rx_int_01_64*)&(val))



#define RX_HDMI21_RX_INT_01_68                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x68)

#define RX_HDMI21_RX_INT_01_68_struct                                    rs_rx_hdmi21_rx_int_01_68

typedef struct _rs_rx_hdmi21_rx_int_01_68  rs_rx_hdmi21_rx_int_01_68;
struct _rs_rx_hdmi21_rx_int_01_68 {
    unsigned int reg_01_access_00_int_clr                   : 1;
    unsigned int reg_01_access_08_int_clr                   : 1;
    unsigned int reg_01_access_0a_int_clr                   : 1;
    unsigned int reg_01_access_10_int_clr                   : 1;
    unsigned int reg_01_access_15_int_clr                   : 1;
    unsigned int reg_01_access_18_int_clr                   : 1;
    unsigned int reg_01_access_30_int_clr                   : 1;
    unsigned int reg_01_access_40_int_clr                   : 1;
    unsigned int reg_01_access_43_int_clr                   : 1;
    unsigned int reg_01_access_50_int_clr                   : 1;
    unsigned int reg_01_access_51_int_clr                   : 1;
    unsigned int reg_01_access_60_int_clr                   : 1;
    unsigned int reg_01_access_70_int_clr                   : 1;
    unsigned int reg_01_access_80_int_clr                   : 1;
    unsigned int reg_01_wmsg_id_2_int_clr                   : 1;
    unsigned int reg_01_wmsg_id_4_int_clr                   : 1;
    unsigned int reg_01_wmsg_id_5_int_clr                   : 1;
    unsigned int reg_01_wmsg_id_9_int_clr                   : 1;
    unsigned int reg_01_wmsg_id_11_int_clr                  : 1;
    unsigned int reg_01_wmsg_id_15_int_clr                  : 1;
    unsigned int reg_01_wmsg_id_16_int_clr                  : 1;
    unsigned int reserved                                   :11;
};
#define rx_hdmi21_rx_int_01_68(val) ((rs_rx_hdmi21_rx_int_01_68*)&(val))



#define RX_HDMI21_RX_INT_01_6C                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x6C)

#define RX_HDMI21_RX_INT_01_6C_struct                                    rs_rx_hdmi21_rx_int_01_6c

typedef struct _rs_rx_hdmi21_rx_int_01_6c  rs_rx_hdmi21_rx_int_01_6c;
struct _rs_rx_hdmi21_rx_int_01_6c {
    unsigned int reg_01_access_00_int_lvl_p                 : 1;
    unsigned int reg_01_access_08_int_lvl_p                 : 1;
    unsigned int reg_01_access_0a_int_lvl_p                 : 1;
    unsigned int reg_01_access_10_int_lvl_p                 : 1;
    unsigned int reg_01_access_15_int_lvl_p                 : 1;
    unsigned int reg_01_access_18_int_lvl_p                 : 1;
    unsigned int reg_01_access_30_int_lvl_p                 : 1;
    unsigned int reg_01_access_40_int_lvl_p                 : 1;
    unsigned int reg_01_access_43_int_lvl_p                 : 1;
    unsigned int reg_01_access_50_int_lvl_p                 : 1;
    unsigned int reg_01_access_51_int_lvl_p                 : 1;
    unsigned int reg_01_access_60_int_lvl_p                 : 1;
    unsigned int reg_01_access_70_int_lvl_p                 : 1;
    unsigned int reg_01_access_80_int_lvl_p                 : 1;
    unsigned int reg_01_wmsg_id_2_int_lvl_p                 : 1;
    unsigned int reg_01_wmsg_id_4_int_lvl_p                 : 1;
    unsigned int reg_01_wmsg_id_5_int_lvl_p                 : 1;
    unsigned int reg_01_wmsg_id_9_int_lvl_p                 : 1;
    unsigned int reg_01_wmsg_id_11_int_lvl_p                : 1;
    unsigned int reg_01_wmsg_id_15_int_lvl_p                : 1;
    unsigned int reg_01_wmsg_id_16_int_lvl_p                : 1;
    unsigned int reserved                                   :11;
};
#define rx_hdmi21_rx_int_01_6c(val) ((rs_rx_hdmi21_rx_int_01_6c*)&(val))



#define RX_HDMI21_RX_INT_01_70                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x70)

#define RX_HDMI21_RX_INT_01_70_struct                                    rs_rx_hdmi21_rx_int_01_70

typedef struct _rs_rx_hdmi21_rx_int_01_70  rs_rx_hdmi21_rx_int_01_70;
struct _rs_rx_hdmi21_rx_int_01_70 {
    unsigned int reg_01_access_00_int_lvl_n                 : 1;
    unsigned int reg_01_access_08_int_lvl_n                 : 1;
    unsigned int reg_01_access_0a_int_lvl_n                 : 1;
    unsigned int reg_01_access_10_int_lvl_n                 : 1;
    unsigned int reg_01_access_15_int_lvl_n                 : 1;
    unsigned int reg_01_access_18_int_lvl_n                 : 1;
    unsigned int reg_01_access_30_int_lvl_n                 : 1;
    unsigned int reg_01_access_40_int_lvl_n                 : 1;
    unsigned int reg_01_access_43_int_lvl_n                 : 1;
    unsigned int reg_01_access_50_int_lvl_n                 : 1;
    unsigned int reg_01_access_51_int_lvl_n                 : 1;
    unsigned int reg_01_access_60_int_lvl_n                 : 1;
    unsigned int reg_01_access_70_int_lvl_n                 : 1;
    unsigned int reg_01_access_80_int_lvl_n                 : 1;
    unsigned int reg_01_wmsg_id_2_int_lvl_n                 : 1;
    unsigned int reg_01_wmsg_id_4_int_lvl_n                 : 1;
    unsigned int reg_01_wmsg_id_5_int_lvl_n                 : 1;
    unsigned int reg_01_wmsg_id_9_int_lvl_n                 : 1;
    unsigned int reg_01_wmsg_id_11_int_lvl_n                : 1;
    unsigned int reg_01_wmsg_id_15_int_lvl_n                : 1;
    unsigned int reg_01_wmsg_id_16_int_lvl_n                : 1;
    unsigned int reserved                                   :11;
};
#define rx_hdmi21_rx_int_01_70(val) ((rs_rx_hdmi21_rx_int_01_70*)&(val))



#define RX_HDMI21_RX_INT_01_74                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x74)

#define RX_HDMI21_RX_INT_01_74_struct                                    rs_rx_hdmi21_rx_int_01_74

typedef struct _rs_rx_hdmi21_rx_int_01_74  rs_rx_hdmi21_rx_int_01_74;
struct _rs_rx_hdmi21_rx_int_01_74 {
    unsigned int reg_01_access_00_int_edg_p                 : 1;
    unsigned int reg_01_access_08_int_edg_p                 : 1;
    unsigned int reg_01_access_0a_int_edg_p                 : 1;
    unsigned int reg_01_access_10_int_edg_p                 : 1;
    unsigned int reg_01_access_15_int_edg_p                 : 1;
    unsigned int reg_01_access_18_int_edg_p                 : 1;
    unsigned int reg_01_access_30_int_edg_p                 : 1;
    unsigned int reg_01_access_40_int_edg_p                 : 1;
    unsigned int reg_01_access_43_int_edg_p                 : 1;
    unsigned int reg_01_access_50_int_edg_p                 : 1;
    unsigned int reg_01_access_51_int_edg_p                 : 1;
    unsigned int reg_01_access_60_int_edg_p                 : 1;
    unsigned int reg_01_access_70_int_edg_p                 : 1;
    unsigned int reg_01_access_80_int_edg_p                 : 1;
    unsigned int reg_01_wmsg_id_2_int_edg_p                 : 1;
    unsigned int reg_01_wmsg_id_4_int_edg_p                 : 1;
    unsigned int reg_01_wmsg_id_5_int_edg_p                 : 1;
    unsigned int reg_01_wmsg_id_9_int_edg_p                 : 1;
    unsigned int reg_01_wmsg_id_11_int_edg_p                : 1;
    unsigned int reg_01_wmsg_id_15_int_edg_p                : 1;
    unsigned int reg_01_wmsg_id_16_int_edg_p                : 1;
    unsigned int reserved                                   :11;
};
#define rx_hdmi21_rx_int_01_74(val) ((rs_rx_hdmi21_rx_int_01_74*)&(val))



#define RX_HDMI21_RX_INT_01_78                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x78)

#define RX_HDMI21_RX_INT_01_78_struct                                    rs_rx_hdmi21_rx_int_01_78

typedef struct _rs_rx_hdmi21_rx_int_01_78  rs_rx_hdmi21_rx_int_01_78;
struct _rs_rx_hdmi21_rx_int_01_78 {
    unsigned int reg_01_access_00_int_edg_n                 : 1;
    unsigned int reg_01_access_08_int_edg_n                 : 1;
    unsigned int reg_01_access_0a_int_edg_n                 : 1;
    unsigned int reg_01_access_10_int_edg_n                 : 1;
    unsigned int reg_01_access_15_int_edg_n                 : 1;
    unsigned int reg_01_access_18_int_edg_n                 : 1;
    unsigned int reg_01_access_30_int_edg_n                 : 1;
    unsigned int reg_01_access_40_int_edg_n                 : 1;
    unsigned int reg_01_access_43_int_edg_n                 : 1;
    unsigned int reg_01_access_50_int_edg_n                 : 1;
    unsigned int reg_01_access_51_int_edg_n                 : 1;
    unsigned int reg_01_access_60_int_edg_n                 : 1;
    unsigned int reg_01_access_70_int_edg_n                 : 1;
    unsigned int reg_01_access_80_int_edg_n                 : 1;
    unsigned int reg_01_wmsg_id_2_int_edg_n                 : 1;
    unsigned int reg_01_wmsg_id_4_int_edg_n                 : 1;
    unsigned int reg_01_wmsg_id_5_int_edg_n                 : 1;
    unsigned int reg_01_wmsg_id_9_int_edg_n                 : 1;
    unsigned int reg_01_wmsg_id_11_int_edg_n                : 1;
    unsigned int reg_01_wmsg_id_15_int_edg_n                : 1;
    unsigned int reg_01_wmsg_id_16_int_edg_n                : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_int_mon_sel                         : 8;
};
#define rx_hdmi21_rx_int_01_78(val) ((rs_rx_hdmi21_rx_int_01_78*)&(val))



#define RX_HDMI21_RX_INT_01_7C                                           (HV_HDMI21_RX_INT_01_BASE_ADDRESS + 0x7C)

#define RX_HDMI21_RX_INT_01_7C_struct                                    rs_rx_hdmi21_rx_int_01_7c

typedef struct _rs_rx_hdmi21_rx_int_01_7c  rs_rx_hdmi21_rx_int_01_7c;
struct _rs_rx_hdmi21_rx_int_01_7c {
    unsigned int reg_01_access_00_int_sta                   : 1;
    unsigned int reg_01_access_08_int_sta                   : 1;
    unsigned int reg_01_access_0a_int_sta                   : 1;
    unsigned int reg_01_access_10_int_sta                   : 1;
    unsigned int reg_01_access_15_int_sta                   : 1;
    unsigned int reg_01_access_18_int_sta                   : 1;
    unsigned int reg_01_access_30_int_sta                   : 1;
    unsigned int reg_01_access_40_int_sta                   : 1;
    unsigned int reg_01_access_43_int_sta                   : 1;
    unsigned int reg_01_access_50_int_sta                   : 1;
    unsigned int reg_01_access_51_int_sta                   : 1;
    unsigned int reg_01_access_60_int_sta                   : 1;
    unsigned int reg_01_access_70_int_sta                   : 1;
    unsigned int reg_01_access_80_int_sta                   : 1;
    unsigned int reg_01_wmsg_id_2_int_sta                   : 1;
    unsigned int reg_01_wmsg_id_4_int_sta                   : 1;
    unsigned int reg_01_wmsg_id_5_int_sta                   : 1;
    unsigned int reg_01_wmsg_id_9_int_sta                   : 1;
    unsigned int reg_01_wmsg_id_11_int_sta                  : 1;
    unsigned int reg_01_wmsg_id_15_int_sta                  : 1;
    unsigned int reg_01_wmsg_id_16_int_sta                  : 1;
    unsigned int reserved                                   : 3;
    unsigned int regr_01_int_mon_cnt                        : 8;
};
#define rx_hdmi21_rx_int_01_7c(val) ((rs_rx_hdmi21_rx_int_01_7c*)&(val))



#endif