/**
 * @file hv_cal_MainMute.c
 * @brief mute module driver
 * @details This module provide interfaces for Hiview-Madia-Ware.
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20221013
 * @copyright Copyright(c),2022-9, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date             <th>Details
 * <tr><td>HiView SoC Software Team   <td>20221013       <td>Create and first Version.
 * </table>
 **/


#include "hv_cal_MainMute.h"
#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Assert.h"


Status Hv_Cal_DpuScaler_SetMuteHtotal(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_00, reg_00_mute_htotal, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVtotal(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_00, reg_00_mute_vtotal, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHact(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_04, reg_00_mute_hact, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVact(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_08, reg_00_mute_vact, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHactMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_0C, reg_00_mute_hact_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHactMax(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_0C, reg_00_mute_hact_max, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVactMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_10, reg_00_mute_vact_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVactMax(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_10, reg_00_mute_vact_max, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteFrmTrigPos(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_14, reg_00_mute_frm_trig_pos, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteNormOption(VOID)
{
    //HV_W32_FIELD(RX_SH12_TOP_00_28, reg_00_mute_de_normal_option, 1);
    //HV_W32_FIELD(RX_SH12_TOP_00_28, reg_00_mute_de_normal_option, 3);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteForceStable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_18, reg_00_mute_force_stable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHminDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_hmin_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHmaxDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_hmax_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVminDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_vmin_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVmaxDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_vmax_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHttlMaxDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_httl_max_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteSh12ProgSrcStableEn(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_sh12_prog_src_stable_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHtotalMax(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_24, reg_00_mute_htotal_max, uiValue);

    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHtotalMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_5C, reg_00_mute_htotal_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVttlMinDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_28, reg_00_mute_vttl_min_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHttlMinDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_5C, reg_00_mute_httl_min_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHsBporth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_04, reg_00_mute_hs_bporch, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVsBporth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_08, reg_00_mute_vs_bporch, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHsWidth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_08, reg_00_mute_hs_width, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVsWidth(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_08, reg_00_mute_vs_width, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteFreerunKeepTime(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_14, reg_00_mute_freerun_keep_time, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteRxLocknDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_18, reg_00_mute_rx_lockn_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteRxDeDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_18, reg_00_mute_rx_de_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHsPos(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_18, reg_00_mute_hs_pos, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVsPos(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_18, reg_00_mute_vs_pos, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteStateW4Enable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_24, reg_00_mute_state_w4_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMainMuteCompW2Enable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_30, reg_00_mute_comp_w2_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_LDGMainInsertBlackEventInit(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F0, reg_main_ext_black_insert_enable, uiValue);
    return HV_SUCCESS;
}

#define HV_BLACK_INSERT_MAIN_CABLE (BIT_6 | BIT_7 | BIT_8 | BIT_9)
Status Hv_Cal_DpuScaler_LDGMainInsertBlackCableDetect(VOID)
{
    HV_R32_DECL_VAR();
    UINT32 uiInserEvent = HV_R32_FIELD(DISP_TOP_SUB_LDG_F0, reg_main_ext_black_insert_enable);
    UINT32 uiHxrxOutSel = HV_R32_FIELD(RX_HSRX_TOP_00, reg_hsrx_out_sel);

    uiInserEvent &= (~HV_BLACK_INSERT_MAIN_CABLE);
    uiHxrxOutSel = uiHxrxOutSel & 0x7;

    if(uiHxrxOutSel < 4)
    {
        uiInserEvent |= (BIT_0 << (6 + uiHxrxOutSel));
#if (HV_BOARD_CONFIG_DP0_TYPE == DP_PORT_ALTMODE)
        /*如果DP0用于typec Alter Mode的话，不需要检查DP0_RX_CABLE_DET来进行硬件遮黑*/
        uiInserEvent &= (~BIT_6);
#endif
        HV_W32_FIELD(DISP_TOP_SUB_LDG_F0, reg_main_ext_black_insert_enable, uiInserEvent);
    }

    return HV_SUCCESS;
}

void Hv_Cal_DpuScaler_LDGMainReleaseBlack(VOID)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F4, reg_main_ext_black_insert_sw_clear, (BIT_5 | HV_BLACK_INSERT_MAIN_CABLE));
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F4, reg_main_ext_black_insert_sw_clear, 0);
}
Status Hv_Cal_DpuScaler_SetMuteSh12MuteInt(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_3C, reg_00_sh12_mute_int, uiValue);

    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMainMisc84(UINT32 uiValue)
{
    HV_R32_DECL_VAR();
    UINT32 uiValueMisc = HV_R32(RX_HDMI21_RX_MISC_01_84);

    /*FreeRun Status is Abnormal*/
    if( HV_R32_FIELD(RX_SH12_TOP_00_E0, regr_00_mute_ip_freerun_en_pre) )
    {
        HV_W32(RX_HDMI21_RX_MISC_01_84, (uiValueMisc + uiValue));
    }
    else
    {
        uiValueMisc = HV_R32(RX_HDMI21_RX_MISC_01_88);
        HV_W32(RX_HDMI21_RX_MISC_01_88, (uiValueMisc + uiValue));
    }

    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteNormPostDelay(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_norm_post_delay, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteFreerun2normThreshold(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_freerun2norm_threshold, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteClkDetEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_clk_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteInclkUnlockedTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_20, reg_00_inclk_unlocked_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteRxclkStableSel(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_24, reg_00_rxclk_stable_sel, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteInclkNoCkOption(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_24, reg_00_inclk_no_ck_option, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteAntiglitchTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_28, reg_00_mute_antiglitch_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteNoDeEnable(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_28, reg_00_mute_no_de_det_enable, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHtotalOutMode(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_30, reg_00_mute_htotal_out_mode, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVsMeasureEn(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_30, reg_00_vs_measure_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteNormClrDelay(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_30, reg_00_mute_norm_clr_delay, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHttlMinCompEn(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_58, reg_00_mute_httl_min_comp_en, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVblankMin(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_5C, reg_00_mute_vblank_min, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteInclkFreqLowTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_20, reg_00_inclk_freq_low_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteInclkFreqHighTh(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_20, reg_00_inclk_freq_high_th, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteHactOut(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_2C, reg_00_mute_hact_out, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteVactOut(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_44, reg_00_mute_vact_out, uiValue);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMuteNormDelay(UINT32 uiValue)
{
    HV_W32_FIELD(RX_SH12_TOP_00_2C, reg_00_mute_norm_delay, uiValue);
    return HV_SUCCESS;
}

/* no de detection threshold */
Status Hv_Cal_DpuScaler_SetMuteNoDeTh(UINT32 uiValue)
{

    HV_W32_FIELD(RX_SH12_TOP_00_40, reg_00_mute_no_de_th, uiValue);
    return HV_SUCCESS;
}

UINT32 Hv_Cal_DpuScaler_GetMuteResult(VOID)
{
   HV_R32_DECL_VAR();
   return HV_R32_FIELD(RX_SH12_TOP_00_F4, regr_00_mute_result);
}

UINT32 Hv_Cal_DpuScaler_GetMuteState(VOID)
{
   HV_R32_DECL_VAR();
   return HV_R32_FIELD(RX_SH12_TOP_00_F4, regr_00_mute_state);
}

/* readback of clock detection abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteClkAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_clk_abn);
}

/* readback of DE H active minimal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteHdeMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_hde_min_abn);
}

/* readback of DE H active maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteHdeMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_hde_max_abn);
}

/* readback of H total maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteHTotalMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_htotal_max_abn);
}

/* readback of DE V active minimal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVDeMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vde_min_abn);
}

/* readback of DE V active maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVDeMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vde_max_abn);
}

/* readback of V blanking maximal abnormal. High is abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVBlkMaxAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vblk_max_abn);
}

/* readback of no DE at all */
UINT32 Hv_Cal_DpuScaler_GetMuteNoDe(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_no_de);
}


VOID Hv_Cal_DpuScaler_ClearMuteEn(VOID)
{
    HV_W32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_en, 1);
    HV_W32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_en, 0);
}

UINT32 Hv_Cal_DpuScaler_GetMuteStatus(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32(RX_SH12_TOP_00_FC);
}

UINT32 Hv_Cal_DpuScaler_GetMuteEn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_en);
}

/* readback of vx1 lock abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVx1LockAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vx1_lock_abn);
}

/* readback of vx1 de abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVx1DeAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vx1_de_abn);
}

/* readback of low vs frequency abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVsFreqIsLow(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vs_freq_is_low);
}

/* readback of high vs frequency abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVsFreqIsHigh(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vs_freq_is_high);
}

/* readback of v total minimal abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVttlMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vttl_min_abn);
}

/* readback of vs frequency diff abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVsFreqDiffHigh(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vs_freq_diff_high);
}

/* readback of vs frequency diff abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteVsFreqDiffLong(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vs_freq_diff_long);
}

UINT32 Hv_Cal_DpuScaler_GetMuteHTotalMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_htotal_min_abn);
}

UINT32 Hv_Cal_DpuScaler_GetMuteVBlkMinAbn(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_FC, regr_00_mute_vblk_min_abn);
}


UINT32 Hv_Cal_DpuScaler_GetDtcMonCycleRefclkVblank(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DTC_TOP_B8, regr_mon_cycle_refclk_vblank);
}

Status Hv_Cal_DpuScaler_SetIntTriggerInfo(UINT32 uiValue)
{
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetKtxFullBlackPatt(BOOL bKtxPattSwitch)
{
    static UINT32 uiValue = 1;
    static UINT32 uiLoop = 1;

    HV_R32_DECL_VAR();

    if(0x21 == HV_R32_FIELD(RX_SH12_TOP_00_F4 , regr_00_mute_state ))
    {
        HV_W32(RX_HDMI21_RX_MISC_01_88, uiValue);
        uiValue++;
    }
    else
    {
        HV_W32(RX_HDMI21_RX_MISC_01_84, uiLoop);
        uiLoop++;
    }

    return HV_SUCCESS;
}


Status Hv_Cal_DpuScaler_SetMiscInt2BitEnable(VOID)
{
    HV_W32_SET_BIT(SYS_REG_SH5_TOP0_48, 2);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_SetMiscInt2BitDisable(VOID)
{
    HV_W32_CLR_BIT(SYS_REG_SH5_TOP0_48, 2);
    return HV_SUCCESS;
}

UINT32 Hv_Cal_DpuScaler_GetMainMuteStatus(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(RX_SH12_TOP_00_F4, regr_00_mute_state);
}

Status Hv_Cal_DpuScaler_MuteClearInsertBlack(ChannelType enChannelType)
{
    Hv_Cal_DpuScaler_LDGMainReleaseBlack();

    return HV_SUCCESS;
}

/* 0 表示Normal, 1 表示 Abnormal */
UINT32 Hv_Cal_DpuScaler_GetMuteMainIntReason(VOID)
{
    HV_R32_DECL_VAR();

    return HV_R32_FIELD(RX_SH12_TOP_00_E0, regr_00_mute_ip_freerun_en_pre);
}

Status Hv_Cal_DpuScaler_MainMuteForceFreeRun(BOOL bSwitch)
{
    HV_W32_FIELD(RX_SH12_TOP_00_1C, reg_00_mute_force_freerun, bSwitch);
    return HV_SUCCESS;
}

UINT32 Hv_Cal_DpuScaler_GetBalckInsertStatus(ChannelType mutePath)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_SUB_LDG_FC, regr_main_black_insert_status);
}

UINT32 Hv_Cal_DpuScaler_GetAudioBalckInsertStatus(VOID)
{
    HV_R32_DECL_VAR();

    return HV_R32_FIELD(RX_AUDIO_TOP0_0C, regr_audio_mute_status);
}

VOID Hv_Cal_DpuScaler_SetMuteThreahold(ChannelType mutePath)
{
    /* 只有两行错误，不进行异常上报，按照正常处理 */
    HV_W32_FIELD(RX_SH12_TOP_00_58, reg_00_mute_abh_min_int_cnt_th, 2);
    HV_W32_FIELD(RX_SH12_TOP_00_58, reg_00_mute_abh_max_int_cnt_th, 2);
}

