#ifndef _HV_PAGE_HT7315_BOE_TX2_H_
#define _HV_PAGE_HT7315_BOE_TX2_H_

#ifndef HV_BOE_TX2_BASE_ADDRESS
    #define HV_BOE_TX2_BASE_ADDRESS                                         0x1105E900
#endif


#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE12                   (HV_BOE_TX2_BASE_ADDRESS + 0x00)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE12_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane12

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane12  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane12;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane12 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane12          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane12         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane12         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane12              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane12(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane12*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE12                   (HV_BOE_TX2_BASE_ADDRESS + 0x04)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE12_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane12

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane12  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane12;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane12 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane12              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane12                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane12              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane12         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane12              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane12                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane12               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane12(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane12*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE12                   (HV_BOE_TX2_BASE_ADDRESS + 0x08)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE12_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane12

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane12  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane12;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane12 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane12               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane12          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane12          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane12          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane12          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane12          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane12           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane12          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane12          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane12            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane12(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane12*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE12                   (HV_BOE_TX2_BASE_ADDRESS + 0x0C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE12_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane12

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane12  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane12;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane12 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane12             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane12               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane12           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane12             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane12           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane12            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane12          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane12          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane12         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane12(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane12*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE13                   (HV_BOE_TX2_BASE_ADDRESS + 0x10)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE13_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane13

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane13  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane13;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane13 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane13          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane13         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane13         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane13              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane13(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane13*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE13                   (HV_BOE_TX2_BASE_ADDRESS + 0x14)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE13_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane13

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane13  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane13;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane13 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane13              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane13                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane13              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane13         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane13              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane13                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane13               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane13(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane13*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE13                   (HV_BOE_TX2_BASE_ADDRESS + 0x18)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE13_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane13

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane13  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane13;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane13 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane13               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane13          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane13          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane13          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane13          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane13          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane13           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane13          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane13          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane13            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane13(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane13*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE13                   (HV_BOE_TX2_BASE_ADDRESS + 0x1C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE13_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane13

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane13  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane13;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane13 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane13             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane13               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane13           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane13             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane13           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane13            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane13          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane13          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane13         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane13(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane13*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE14                   (HV_BOE_TX2_BASE_ADDRESS + 0x20)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE14_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane14

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane14  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane14;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane14 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane14          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane14         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane14         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane14              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane14(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane14*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE14                   (HV_BOE_TX2_BASE_ADDRESS + 0x24)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE14_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane14

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane14  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane14;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane14 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane14              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane14                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane14              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane14         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane14              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane14                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane14               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane14(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane14*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE14                   (HV_BOE_TX2_BASE_ADDRESS + 0x28)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE14_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane14

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane14  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane14;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane14 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane14               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane14          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane14          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane14          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane14          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane14          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane14           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane14          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane14          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane14            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane14(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane14*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE14                   (HV_BOE_TX2_BASE_ADDRESS + 0x2C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE14_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane14

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane14  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane14;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane14 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane14             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane14               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane14           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane14             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane14           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane14            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane14          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane14          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane14         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane14(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane14*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE15                   (HV_BOE_TX2_BASE_ADDRESS + 0x30)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE15_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane15

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane15  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane15;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane15 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane15          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane15         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane15         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane15              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane15(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane15*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE15                   (HV_BOE_TX2_BASE_ADDRESS + 0x34)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE15_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane15

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane15  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane15;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane15 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane15              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane15                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane15              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane15         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane15              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane15                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane15               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane15(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane15*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE15                   (HV_BOE_TX2_BASE_ADDRESS + 0x38)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE15_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane15

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane15  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane15;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane15 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane15               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane15          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane15          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane15          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane15          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane15          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane15           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane15          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane15          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane15            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane15(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane15*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE15                   (HV_BOE_TX2_BASE_ADDRESS + 0x3C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE15_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane15

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane15  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane15;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane15 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane15             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane15               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane15           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane15             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane15           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane15            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane15          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane15          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane15         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane15(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane15*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE16                   (HV_BOE_TX2_BASE_ADDRESS + 0x40)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE16_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane16

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane16  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane16;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane16 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane16          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane16         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane16         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane16              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane16(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane16*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE16                   (HV_BOE_TX2_BASE_ADDRESS + 0x44)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE16_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane16

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane16  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane16;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane16 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane16              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane16                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane16              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane16         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane16              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane16                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane16               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane16(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane16*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE16                   (HV_BOE_TX2_BASE_ADDRESS + 0x48)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE16_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane16

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane16  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane16;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane16 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane16               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane16          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane16          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane16          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane16          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane16          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane16           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane16          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane16          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane16            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane16(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane16*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE16                   (HV_BOE_TX2_BASE_ADDRESS + 0x4C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE16_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane16

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane16  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane16;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane16 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane16             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane16               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane16           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane16             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane16           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane16            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane16          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane16          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane16         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane16(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane16*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE17                   (HV_BOE_TX2_BASE_ADDRESS + 0x50)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE17_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane17

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane17  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane17;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane17 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane17          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane17         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane17         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane17              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane17(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane17*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE17                   (HV_BOE_TX2_BASE_ADDRESS + 0x54)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE17_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane17

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane17  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane17;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane17 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane17              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane17                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane17              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane17         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane17              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane17                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane17               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane17(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane17*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE17                   (HV_BOE_TX2_BASE_ADDRESS + 0x58)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE17_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane17

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane17  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane17;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane17 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane17               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane17          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane17          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane17          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane17          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane17          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane17           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane17          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane17          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane17            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane17(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane17*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE17                   (HV_BOE_TX2_BASE_ADDRESS + 0x5C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE17_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane17

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane17  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane17;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane17 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane17             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane17               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane17           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane17             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane17           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane17            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane17          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane17          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane17         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane17(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane17*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE18                   (HV_BOE_TX2_BASE_ADDRESS + 0x60)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE18_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane18

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane18  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane18;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane18 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane18          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane18         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane18         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane18              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane18(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane18*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE18                   (HV_BOE_TX2_BASE_ADDRESS + 0x64)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE18_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane18

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane18  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane18;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane18 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane18              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane18                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane18              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane18         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane18              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane18                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane18               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane18(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane18*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE18                   (HV_BOE_TX2_BASE_ADDRESS + 0x68)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE18_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane18

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane18  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane18;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane18 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane18               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane18          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane18          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane18          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane18          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane18          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane18           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane18          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane18          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane18            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane18(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane18*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE18                   (HV_BOE_TX2_BASE_ADDRESS + 0x6C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE18_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane18

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane18  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane18;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane18 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane18             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane18               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane18           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane18             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane18           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane18            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane18          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane18          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane18         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane18(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane18*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE19                   (HV_BOE_TX2_BASE_ADDRESS + 0x70)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE19_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane19

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane19  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane19;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane19 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane19          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane19         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane19         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane19              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane19(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane19*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE19                   (HV_BOE_TX2_BASE_ADDRESS + 0x74)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE19_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane19

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane19  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane19;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane19 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane19              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane19                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane19              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane19         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane19              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane19                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane19               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane19(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane19*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE19                   (HV_BOE_TX2_BASE_ADDRESS + 0x78)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE19_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane19

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane19  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane19;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane19 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane19               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane19          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane19          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane19          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane19          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane19          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane19           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane19          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane19          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane19            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane19(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane19*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE19                   (HV_BOE_TX2_BASE_ADDRESS + 0x7C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE19_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane19

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane19  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane19;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane19 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane19             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane19               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane19           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane19             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane19           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane19            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane19          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane19          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane19         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane19(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane19*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE20                   (HV_BOE_TX2_BASE_ADDRESS + 0x80)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE20_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane20

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane20  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane20;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane20 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane20          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane20         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane20         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane20              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane20(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane20*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE20                   (HV_BOE_TX2_BASE_ADDRESS + 0x84)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE20_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane20

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane20  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane20;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane20 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane20              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane20                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane20              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane20         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane20              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane20                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane20               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane20(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane20*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE20                   (HV_BOE_TX2_BASE_ADDRESS + 0x88)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE20_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane20

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane20  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane20;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane20 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane20               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane20          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane20          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane20          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane20          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane20          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane20           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane20          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane20          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane20            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane20(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane20*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE20                   (HV_BOE_TX2_BASE_ADDRESS + 0x8C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE20_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane20

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane20  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane20;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane20 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane20             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane20               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane20           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane20             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane20           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane20            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane20          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane20          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane20         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane20(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane20*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE21                   (HV_BOE_TX2_BASE_ADDRESS + 0x90)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE21_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane21

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane21  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane21;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane21 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane21          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane21         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane21         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane21              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane21(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane21*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE21                   (HV_BOE_TX2_BASE_ADDRESS + 0x94)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE21_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane21

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane21  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane21;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane21 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane21              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane21                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane21              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane21         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane21              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane21                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane21               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane21(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane21*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE21                   (HV_BOE_TX2_BASE_ADDRESS + 0x98)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE21_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane21

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane21  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane21;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane21 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane21               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane21          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane21          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane21          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane21          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane21          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane21           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane21          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane21          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane21            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane21(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane21*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE21                   (HV_BOE_TX2_BASE_ADDRESS + 0x9C)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE21_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane21

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane21  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane21;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane21 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane21             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane21               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane21           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane21             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane21           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane21            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane21          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane21          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane21         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane21(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane21*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE22                   (HV_BOE_TX2_BASE_ADDRESS + 0xA0)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE22_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane22

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane22  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane22;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane22 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane22          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane22         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane22         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane22              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane22(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane22*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE22                   (HV_BOE_TX2_BASE_ADDRESS + 0xA4)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE22_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane22

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane22  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane22;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane22 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane22              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane22                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane22              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane22         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane22              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane22                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane22               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane22(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane22*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE22                   (HV_BOE_TX2_BASE_ADDRESS + 0xA8)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE22_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane22

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane22  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane22;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane22 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane22               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane22          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane22          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane22          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane22          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane22          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane22           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane22          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane22          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane22            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane22(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane22*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE22                   (HV_BOE_TX2_BASE_ADDRESS + 0xAC)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE22_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane22

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane22  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane22;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane22 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane22             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane22               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane22           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane22             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane22           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane22            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane22          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane22          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane22         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane22(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane22*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE23                   (HV_BOE_TX2_BASE_ADDRESS + 0xB0)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_0_LANE23_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane23

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane23  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane23;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane23 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane23          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane23         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane23         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane23              : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane23(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_0_lane23*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE23                   (HV_BOE_TX2_BASE_ADDRESS + 0xB4)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_1_LANE23_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane23

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane23  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane23;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane23 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane23              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane23                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane23              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane23         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane23              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane23                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane23               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane23(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_1_lane23*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE23                   (HV_BOE_TX2_BASE_ADDRESS + 0xB8)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_2_LANE23_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane23

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane23  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane23;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane23 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane23               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane23          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane23          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane23          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane23          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane23          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane23           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane23          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane23          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane23            : 3;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane23(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_2_lane23*)&(val))



#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE23                   (HV_BOE_TX2_BASE_ADDRESS + 0xBC)

#define TX_BOE_TX2_BOE_P2P_CTRL_PACKET_CONFIG_3_LANE23_struct            rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane23

typedef struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane23  rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane23;
struct _rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane23 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane23             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane23               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane23           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane23             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane23           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane23            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane23          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane23          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane23         : 8;
    unsigned int reserved_1                                 : 8;
};
#define tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane23(val) ((rs_tx_boe_tx2_boe_p2p_ctrl_packet_config_3_lane23*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_00                                 (HV_BOE_TX2_BASE_ADDRESS + 0xC0)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_00_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_00

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_00  rs_tx_boe_tx2_chpi_tx_sec_config_00;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_00 {
    unsigned int reg_boe_tx_sec0_w_lane00                   : 8;
    unsigned int reg_boe_tx_sec1_w_lane00                   : 8;
    unsigned int reg_boe_tx_sec2_w_lane00                   : 8;
    unsigned int reg_boe_tx_sec3_w_lane00                   : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_00(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_00*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_01                                 (HV_BOE_TX2_BASE_ADDRESS + 0xC4)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_01_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_01

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_01  rs_tx_boe_tx2_chpi_tx_sec_config_01;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_01 {
    unsigned int reg_boe_tx_sec4_w_lane00                   : 8;
    unsigned int reg_boe_tx_sec5_w_lane00                   : 8;
    unsigned int reg_boe_tx_sec0_strl_lane00                : 8;
    unsigned int reg_boe_tx_sec1_strl_lane00                : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_01(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_01*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_02                                 (HV_BOE_TX2_BASE_ADDRESS + 0xC8)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_02_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_02

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_02  rs_tx_boe_tx2_chpi_tx_sec_config_02;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_02 {
    unsigned int reg_boe_tx_sec2_strl_lane00                : 8;
    unsigned int reg_boe_tx_sec3_strl_lane00                : 8;
    unsigned int reg_boe_tx_sec4_strl_lane00                : 8;
    unsigned int reg_boe_tx_sec5_strl_lane00                : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_02(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_02*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_03                                 (HV_BOE_TX2_BASE_ADDRESS + 0xCC)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_03_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_03

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_03  rs_tx_boe_tx2_chpi_tx_sec_config_03;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_03 {
    unsigned int reg_boe_tx_sec0_strh_lane00                : 2;
    unsigned int reg_boe_tx_sec1_strh_lane00                : 2;
    unsigned int reg_boe_tx_sec2_strh_lane00                : 2;
    unsigned int reg_boe_tx_sec3_strh_lane00                : 2;
    unsigned int reg_boe_tx_sec4_strh_lane00                : 2;
    unsigned int reg_boe_tx_sec5_strh_lane00                : 2;
    unsigned int reg_boe_tx_sec0_slop_lane00                : 2;
    unsigned int reg_boe_tx_sec1_slop_lane00                : 2;
    unsigned int reg_boe_tx_sec2_slop_lane00                : 2;
    unsigned int reg_boe_tx_sec3_slop_lane00                : 2;
    unsigned int reg_boe_tx_sec4_slop_lane00                : 2;
    unsigned int reg_boe_tx_sec5_slop_lane00                : 2;
    unsigned int reg_boe_tx_sec_en_lane00                   : 1;
    unsigned int reserved                                   : 7;
};
#define tx_boe_tx2_chpi_tx_sec_config_03(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_03*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_04                                 (HV_BOE_TX2_BASE_ADDRESS + 0xD0)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_04_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_04

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_04  rs_tx_boe_tx2_chpi_tx_sec_config_04;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_04 {
    unsigned int reg_boe_tx_sec0_group_lane00               : 8;
    unsigned int reg_boe_tx_sec1_group_lane00               : 8;
    unsigned int reg_boe_tx_sec2_group_lane00               : 8;
    unsigned int reg_boe_tx_sec3_group_lane00               : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_04(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_04*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_05                                 (HV_BOE_TX2_BASE_ADDRESS + 0xD4)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_05_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_05

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_05  rs_tx_boe_tx2_chpi_tx_sec_config_05;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_05 {
    unsigned int reg_boe_tx_sec4_group_lane00               : 8;
    unsigned int reg_boe_tx_sec5_group_lane00               : 8;
    unsigned int reserved                                   :16;
};
#define tx_boe_tx2_chpi_tx_sec_config_05(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_05*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_06                                 (HV_BOE_TX2_BASE_ADDRESS + 0xD8)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_06_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_06

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_06  rs_tx_boe_tx2_chpi_tx_sec_config_06;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_06 {
    unsigned int reg_boe_tx_sec0_w_lane01                   : 8;
    unsigned int reg_boe_tx_sec1_w_lane01                   : 8;
    unsigned int reg_boe_tx_sec2_w_lane01                   : 8;
    unsigned int reg_boe_tx_sec3_w_lane01                   : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_06(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_06*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_07                                 (HV_BOE_TX2_BASE_ADDRESS + 0xDC)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_07_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_07

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_07  rs_tx_boe_tx2_chpi_tx_sec_config_07;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_07 {
    unsigned int reg_boe_tx_sec4_w_lane01                   : 8;
    unsigned int reg_boe_tx_sec5_w_lane01                   : 8;
    unsigned int reg_boe_tx_sec0_strl_lane01                : 8;
    unsigned int reg_boe_tx_sec1_strl_lane01                : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_07(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_07*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_08                                 (HV_BOE_TX2_BASE_ADDRESS + 0xE0)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_08_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_08

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_08  rs_tx_boe_tx2_chpi_tx_sec_config_08;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_08 {
    unsigned int reg_boe_tx_sec2_strl_lane01                : 8;
    unsigned int reg_boe_tx_sec3_strl_lane01                : 8;
    unsigned int reg_boe_tx_sec4_strl_lane01                : 8;
    unsigned int reg_boe_tx_sec5_strl_lane01                : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_08(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_08*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_09                                 (HV_BOE_TX2_BASE_ADDRESS + 0xE4)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_09_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_09

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_09  rs_tx_boe_tx2_chpi_tx_sec_config_09;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_09 {
    unsigned int reg_boe_tx_sec0_strh_lane01                : 2;
    unsigned int reg_boe_tx_sec1_strh_lane01                : 2;
    unsigned int reg_boe_tx_sec2_strh_lane01                : 2;
    unsigned int reg_boe_tx_sec3_strh_lane01                : 2;
    unsigned int reg_boe_tx_sec4_strh_lane01                : 2;
    unsigned int reg_boe_tx_sec5_strh_lane01                : 2;
    unsigned int reg_boe_tx_sec0_slop_lane01                : 2;
    unsigned int reg_boe_tx_sec1_slop_lane01                : 2;
    unsigned int reg_boe_tx_sec2_slop_lane01                : 2;
    unsigned int reg_boe_tx_sec3_slop_lane01                : 2;
    unsigned int reg_boe_tx_sec4_slop_lane01                : 2;
    unsigned int reg_boe_tx_sec5_slop_lane01                : 2;
    unsigned int reg_boe_tx_sec_en_lane01                   : 1;
    unsigned int reserved                                   : 7;
};
#define tx_boe_tx2_chpi_tx_sec_config_09(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_09*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_10                                 (HV_BOE_TX2_BASE_ADDRESS + 0xE8)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_10_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_10

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_10  rs_tx_boe_tx2_chpi_tx_sec_config_10;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_10 {
    unsigned int reg_boe_tx_sec0_group_lane01               : 8;
    unsigned int reg_boe_tx_sec1_group_lane01               : 8;
    unsigned int reg_boe_tx_sec2_group_lane01               : 8;
    unsigned int reg_boe_tx_sec3_group_lane01               : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_10(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_10*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_11                                 (HV_BOE_TX2_BASE_ADDRESS + 0xEC)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_11_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_11

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_11  rs_tx_boe_tx2_chpi_tx_sec_config_11;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_11 {
    unsigned int reg_boe_tx_sec4_group_lane01               : 8;
    unsigned int reg_boe_tx_sec5_group_lane01               : 8;
    unsigned int reserved                                   :16;
};
#define tx_boe_tx2_chpi_tx_sec_config_11(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_11*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_12                                 (HV_BOE_TX2_BASE_ADDRESS + 0xF0)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_12_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_12

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_12  rs_tx_boe_tx2_chpi_tx_sec_config_12;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_12 {
    unsigned int reg_boe_tx_sec0_w_lane02                   : 8;
    unsigned int reg_boe_tx_sec1_w_lane02                   : 8;
    unsigned int reg_boe_tx_sec2_w_lane02                   : 8;
    unsigned int reg_boe_tx_sec3_w_lane02                   : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_12(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_12*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_13                                 (HV_BOE_TX2_BASE_ADDRESS + 0xF4)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_13_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_13

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_13  rs_tx_boe_tx2_chpi_tx_sec_config_13;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_13 {
    unsigned int reg_boe_tx_sec4_w_lane02                   : 8;
    unsigned int reg_boe_tx_sec5_w_lane02                   : 8;
    unsigned int reg_boe_tx_sec0_strl_lane02                : 8;
    unsigned int reg_boe_tx_sec1_strl_lane02                : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_13(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_13*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_14                                 (HV_BOE_TX2_BASE_ADDRESS + 0xF8)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_14_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_14

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_14  rs_tx_boe_tx2_chpi_tx_sec_config_14;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_14 {
    unsigned int reg_boe_tx_sec2_strl_lane02                : 8;
    unsigned int reg_boe_tx_sec3_strl_lane02                : 8;
    unsigned int reg_boe_tx_sec4_strl_lane02                : 8;
    unsigned int reg_boe_tx_sec5_strl_lane02                : 8;
};
#define tx_boe_tx2_chpi_tx_sec_config_14(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_14*)&(val))



#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_15                                 (HV_BOE_TX2_BASE_ADDRESS + 0xFC)

#define TX_BOE_TX2_CHPI_TX_SEC_CONFIG_15_struct                          rs_tx_boe_tx2_chpi_tx_sec_config_15

typedef struct _rs_tx_boe_tx2_chpi_tx_sec_config_15  rs_tx_boe_tx2_chpi_tx_sec_config_15;
struct _rs_tx_boe_tx2_chpi_tx_sec_config_15 {
    unsigned int reg_boe_tx_sec0_strh_lane02                : 2;
    unsigned int reg_boe_tx_sec1_strh_lane02                : 2;
    unsigned int reg_boe_tx_sec2_strh_lane02                : 2;
    unsigned int reg_boe_tx_sec3_strh_lane02                : 2;
    unsigned int reg_boe_tx_sec4_strh_lane02                : 2;
    unsigned int reg_boe_tx_sec5_strh_lane02                : 2;
    unsigned int reg_boe_tx_sec0_slop_lane02                : 2;
    unsigned int reg_boe_tx_sec1_slop_lane02                : 2;
    unsigned int reg_boe_tx_sec2_slop_lane02                : 2;
    unsigned int reg_boe_tx_sec3_slop_lane02                : 2;
    unsigned int reg_boe_tx_sec4_slop_lane02                : 2;
    unsigned int reg_boe_tx_sec5_slop_lane02                : 2;
    unsigned int reg_boe_tx_sec_en_lane02                   : 1;
    unsigned int reserved                                   : 7;
};
#define tx_boe_tx2_chpi_tx_sec_config_15(val) ((rs_tx_boe_tx2_chpi_tx_sec_config_15*)&(val))



#endif