/*
* @file hv_drv_UsbMusbCorePeri.c
* @brief MUSB OTG driver core code.
*        Inventra (Multipoint) Dual-Role Controller Driver for Linux.
*
* @author HiView SoC Software Team
* @version 1.0.0
* @date 2022-06-15
*/


#include "hv_drv_UsbCh9.h"
#include "hv_drv_UsbGadget.h"
#include "hv_drv_UsbMusb.h"
#include "hv_drv_UsbCompat.h"
#include "hv_drv_UsbMusbCoreDev.h"

#include "hv_drv_UsbDefines.h"
#include "hv_drv_UsbMusbHsDmaDev.h"


#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)


#define DRIVER_AUTHOR   "Mentor Graphics, Texas Instruments, Nokia"
#define DRIVER_DESC     "Inventra Dual-Role USB Controller Driver"

#define MUSB_VERSION    "6.0"

#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION


#define MUSB_DRIVER_NAME "musb-hdrc"
const char musb_driver_name[] = MUSB_DRIVER_NAME;


extern void USB_IntEnable(void);

/*-------------------------------------------------------------------------*/

/*
 * Load an endpoint's FIFO
 */
void musb_write_fifo_dev(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
    struct musb *musb = hw_ep->musb;
    void  *fifo = hw_ep->fifo;

    pr_debug("musb_write_fifo, %cX ep%d fifo 0x%x count %d buf 0x%x.\n",
            'T', hw_ep->epnum, fifo, len, src);
    USB_UNUSED(musb);

    /* we can't assume unaligned reads work */
    if (likely((0x01 & (unsigned long) src) == 0)) {
        u16    index = 0;

        /* best case is 32bit-aligned source address */
        if ((0x02 & (unsigned long) src) == 0) {
            if (len >= 4) {
                writesl(fifo, src + index, len >> 2);
                index += len & ~0x03;
            }
            if (len & 0x02) {
                musb_writew(fifo, 0, *(u16 *)&src[index]);
                index += 2;
            }
        } else {
            if (len >= 2) {
                writesw(fifo, src + index, len >> 1);
                index += len & ~0x01;
            }
        }
        if (len & 0x01)
            musb_writeb(fifo, 0, src[index]);
    } else  {
        /* byte aligned */
        writesb(fifo, src, len);
    }
}

/*
 * Unload an endpoint's FIFO
 */
void musb_read_fifo_dev(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
    struct musb *musb = hw_ep->musb;
    void  *fifo = hw_ep->fifo;

    pr_debug("%cX ep%d fifo 0x%x count %d  buf 0x%x.\n",
            'R', hw_ep->epnum, fifo, len, dst);
    USB_UNUSED(musb);

    /* we can't assume unaligned writes work */
    if (likely((0x01 & (unsigned long) dst) == 0)) {
        u16    index = 0;

        /* best case is 32bit-aligned destination address */
        if ((0x02 & (unsigned long) dst) == 0) {
            if (len >= 4) {
                readsl(fifo, dst, len >> 2);
                index = len & ~0x03;
            }
            if (len & 0x02) {
                *(u16 *)&dst[index] = musb_readw(fifo, 0);
                index += 2;
            }
        } else {
            if (len >= 2) {
                readsw(fifo, dst, len >> 1);
                index = len & ~0x01;
            }
        }
        if (len & 0x01)
            dst[index] = musb_readb(fifo, 0);
    } else  {
        /* byte aligned */
        readsb(fifo, dst, len);
    }
}


/*-------------------------------------------------------------------------*/

/* for high speed test mode; see USB 2.0 spec 7.1.20 */
static const u8 musb_test_packet[53] = {
    /* implicit SYNC then DATA0 to start */

    /* JKJKJKJK x9 */
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
    /* JJKKJJKK x8 */
    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
    /* JJJJKKKK x8 */
    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
    /* JJJJJJJKKKKKKK x8 */
    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
    /* JJJJJJJK x8 */
    0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
    /* JKKKKKKK x10, JK */
    0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e

    /* implicit CRC16 then EOP to end */
};

void musb_load_testpacket_dev(struct musb *musb)
{
    void     *regs = musb->endpoints[0].regs;

    musb_ep_select(musb->mregs, 0);
    musb_write_fifo_dev(musb->control_ep,
            sizeof(musb_test_packet), musb_test_packet);
    musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
}


/*
 * Interrupt Service Routine to record USB "global" interrupts.
 * Since these do not happen often and signify things of
 * paramount importance, it seems OK to check them individually;
 * the order of the tests is specified in the manual
 *
 * @param musb instance pointer
 * @param int_usb register contents
 * @param devctl
 * @param power
 */

static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                u8 devctl, u8 power)
{
    irqreturn_t handled = IRQ_NONE;

    if (int_usb & MUSB_INTR_CONNECT) {

        handled = IRQ_HANDLED;
        musb->is_active = 1;

        musb->ep0_stage = MUSB_EP0_START;

        /* flush endpoints when transitioning from Device Mode */
        if (is_peripheral_active(musb)) {
            /* REVISIT HNP; just force disconnect */
        }
        musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
        musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
        musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
    }

    return handled;
}

/*-------------------------------------------------------------------------*/

/*
* Program the HDRC to start (enable interrupts, dma, etc.).
*/
int musb_start_dev(struct musb *musb)
{
    void     *regs = musb->mregs;
    u8        devctl = musb_readb(regs, MUSB_DEVCTL);
    int ret;

    dev_dbg(musb->controller, "<== devctl %x\n", devctl);

    /*  Set INT enable registers, enable interrupts */
    musb_writew(regs, MUSB_INTRTXE, musb->epmask);
    musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
    musb_writeb(regs, MUSB_INTRUSBE, 0xf7);

    musb_writeb(regs, MUSB_TESTMODE, 0);

    /* put into basic highspeed mode and start session */
    musb_writeb(regs, MUSB_POWER, 
                        MUSB_POWER_ISOUPDATE|
                        MUSB_POWER_SOFTCONN
#ifdef CONFIG_USB_HIGHSPEED
                        | MUSB_POWER_HSENAB
#endif
                        /* ENSUSPEND wedges tusb */
                         | MUSB_POWER_ENSUSPEND 
                        );

    musb->is_active = 0;
    devctl = musb_readb(regs, MUSB_DEVCTL);
    devctl &= ~MUSB_DEVCTL_SESSION;

    if (is_otg_enabled(musb)) {

    } else if (is_host_enabled(musb)) {
        /* assume ID pin is hard-wired to ground */
        devctl |= MUSB_DEVCTL_SESSION;

    } else /* peripheral is enabled */ {
        if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
            musb->is_active = 1;
    }

    ret = musb_platform_enable(musb);
    if (ret) {
        musb->is_active = 0;
        return ret;
    }
    musb_writeb(regs, MUSB_DEVCTL, devctl);

    return 0;
}


static void musb_generic_disable(struct musb *musb)
{
    void     *mbase = musb->mregs;
    u16    temp;

    /* disable interrupts */
    musb_writeb(mbase, MUSB_INTRUSBE, 0);
    musb_writew(mbase, MUSB_INTRTXE, 0);
    musb_writew(mbase, MUSB_INTRRXE, 0);

    /* off */
    musb_writeb(mbase, MUSB_DEVCTL, 0);

    /*  flush pending interrupts */
    temp = musb_readb(mbase, MUSB_INTRUSB);
    temp = musb_readw(mbase, MUSB_INTRTX);
    temp = musb_readw(mbase, MUSB_INTRRX);
    USB_UNUSED(temp);
}

/*
 * Make the HDRC stop (disable interrupts, etc.);
 * reversible by musb_start
 * called on gadget driver unregister
 * with controller locked, irqs blocked
 * acts as a NOP unless some role activated the hardware
 */
void musb_stop_dev(struct musb *musb)
{
    /* stop IRQs, timers, ... */
    musb_platform_disable(musb);
    musb_generic_disable(musb);
    dev_dbg(musb->controller, "HDRC disabled\n");

    /* FIXME
     *  - mark host and/or peripheral drivers unusable/inactive
     *  - disable DMA (and enable it in HdrcStart)
     *  - make sure we can musb_start() after musb_stop(); with
     *    OTG mode, gadget driver module rmmod/modprobe cycles that
     *  - ...
     */
    musb_platform_try_idle(musb, 0);
}



/*-------------------------------------------------------------------------*/

/*
 * The silicon either has hard-wired endpoint configurations, or else
 * "dynamic fifo" sizing.  The driver has support for both, though at this
 * writing only the dynamic sizing is very well tested.   Since we switched
 * away from compile-time hardware parameters, we can no longer rely on
 * dead code elimination to leave only the relevant one in the object file.
 *
 * We don't currently use dynamic fifo setup capability to do anything
 * more than selecting one of a bunch of predefined configurations.
 */
static ushort fifo_mode = 2;


/*
 * tables defining fifo_mode values.  define more if you like.
 * for host side, make sure both halves of ep1 are set up.
 */

/* mode 0 - fits in 2KB */
static struct musb_fifo_cfg mode_0_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
};

/* mode 1 - fits in 4KB */
static struct musb_fifo_cfg mode_1_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
};

/* mode 2 - fits in 4KB */
static struct musb_fifo_cfg mode_2_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
};

/* mode 3 - fits in 4KB */
static struct musb_fifo_cfg mode_3_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
{ .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
};

/* mode 4 - fits in 16KB */
static struct musb_fifo_cfg mode_4_cfg[] = {
{ .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
};

/* mode 5 - fits in 8KB */
static struct musb_fifo_cfg mode_5_cfg[] = {
{ .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
{ .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
{ .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
{ .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
{ .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
{ .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
{ .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
{ .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
};

/*
 * configure a fifo; for non-shared endpoints, this may be called
 * once for a tx fifo and once for an rx fifo.
 *
 * returns negative errno or offset for next fifo.
 */
static int __devinit
fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
        const struct musb_fifo_cfg *cfg, u16 offset)
{
    void     *mbase = musb->mregs;
    int    size = 0;
    u16    maxpacket = cfg->maxpacket;
    u16    c_off = offset >> 3;
    u8    c_size;

    /* expect hw_ep has already been zero-initialized */

    size = ffs_me(max(maxpacket, (u16) 8)) - 1;
    maxpacket = 1 << size;

    c_size = size - 3;
    if (cfg->mode == BUF_DOUBLE) {
        if ((offset + (maxpacket << 1)) >
                (1 << (musb->config->ram_bits + 2)))
            return -EMSGSIZE;
        c_size |= MUSB_FIFOSZ_DPB;
    } else {
        if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
            return -EMSGSIZE;
    }

    /* configure the FIFO */
    musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);

    /* EP0 reserved endpoint for control, bidirectional;
     * EP1 reserved for bulk, two unidirection halves.
     */
    if (hw_ep->epnum == 1)
        musb->bulk_ep = hw_ep;
    /* REVISIT error check:  be sure ep0 can both rx and tx ... */
    switch (cfg->style) {
    case FIFO_TX:
        musb_write_txfifosz(mbase, c_size);
        musb_write_txfifoadd(mbase, c_off);
        hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
        hw_ep->max_packet_sz_tx = maxpacket;
        break;
    case FIFO_RX:
        musb_write_rxfifosz(mbase, c_size);
        musb_write_rxfifoadd(mbase, c_off);
        hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
        hw_ep->max_packet_sz_rx = maxpacket;
        break;
    case FIFO_RXTX:
        musb_write_txfifosz(mbase, c_size);
        musb_write_txfifoadd(mbase, c_off);
        hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
        hw_ep->max_packet_sz_rx = maxpacket;

        musb_write_rxfifosz(mbase, c_size);
        musb_write_rxfifoadd(mbase, c_off);
        hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
        hw_ep->max_packet_sz_tx = maxpacket;

        hw_ep->is_shared_fifo = true;
        break;
    }

    /* NOTE rx and tx endpoint irqs aren't managed separately,
     * which happens to be ok
     */
    musb->epmask |= (1 << hw_ep->epnum);

    return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
}

static struct musb_fifo_cfg ep0_cfg = {
    .style = FIFO_RXTX, .maxpacket = 64,
};

static int __devinit ep_config_from_table(struct musb *musb)
{
    const struct musb_fifo_cfg    *cfg;
    unsigned        i, n;
    int            offset;
    struct musb_hw_ep    *hw_ep = musb->endpoints;

    if (musb->config->fifo_cfg) {
        cfg = musb->config->fifo_cfg;
        n = musb->config->fifo_cfg_size;
        goto done;
    }

    switch (fifo_mode) {
    default:
        fifo_mode = 0;
        /* FALLTHROUGH */
    case 0:
        cfg = mode_0_cfg;
        n = ARRAY_SIZE(mode_0_cfg);
        break;
    case 1:
        cfg = mode_1_cfg;
        n = ARRAY_SIZE(mode_1_cfg);
        break;
    case 2:
        cfg = mode_2_cfg;
        n = ARRAY_SIZE(mode_2_cfg);
        break;
    case 3:
        cfg = mode_3_cfg;
        n = ARRAY_SIZE(mode_3_cfg);
        break;
    case 4:
        cfg = mode_4_cfg;
        n = ARRAY_SIZE(mode_4_cfg);
        break;
    case 5:
        cfg = mode_5_cfg;
        n = ARRAY_SIZE(mode_5_cfg);
        break;
    }

    pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);

done:
    offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
    /* assert(offset > 0) */

    /* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
     * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
     */

    for (i = 0; i < n; i++) {
        u8    epn = cfg->hw_ep_num;

        if (epn >= musb->config->num_eps) {
            pr_debug("%s: invalid ep %d\n",
                    musb_driver_name, epn);
            return -EINVAL;
        }
        offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
        if (offset < 0) {
            pr_debug("%s: mem overrun, ep %d\n",
                    musb_driver_name, epn);
            return -EINVAL;
        }
        epn++;
        musb->nr_endpoints = max(epn, musb->nr_endpoints);
    }

    pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1,
         musb->config->num_eps * 2 - 1, offset,
         (1 << (musb->config->ram_bits + 2)));

    if (!musb->bulk_ep) {
        pr_debug("%s: missing bulk\n", musb_driver_name);
        return -EINVAL;
    }

    return 0;
}


/*
 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
 * @param musb the controller
 */
static int __devinit ep_config_from_hw(struct musb *musb)
{
    u8 epnum = 0;
    struct musb_hw_ep *hw_ep;
    void *mbase = musb->mregs;
    int ret = 0;

    dev_dbg(musb->controller, "<== static silicon ep config\n");

    /* FIXME pick up ep0 maxpacket size */

    for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
        musb_ep_select(mbase, epnum);
        hw_ep = musb->endpoints + epnum;

        ret = musb_read_fifosize(musb, hw_ep, epnum);
        if (ret < 0)
            break;

        /* FIXME set up hw_ep->{rx,tx}_double_buffered */

        /* pick an RX/TX endpoint for bulk */
        if (hw_ep->max_packet_sz_tx < 512
                || hw_ep->max_packet_sz_rx < 512)
            continue;

        /* REVISIT:  this algorithm is lazy, we should at least
         * try to pick a double buffered endpoint.
         */
        if (musb->bulk_ep)
            continue;
        musb->bulk_ep = hw_ep;
    }

    if (!musb->bulk_ep) {
        pr_debug("%s: missing bulk\n", musb_driver_name);
        return -EINVAL;
    }

    return 0;
}

enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };

/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
 * configure endpoints, or take their config from silicon
 */
static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
{
    u8 reg;
    char *type;
    char aInfo[90], aRevision[32], aDate[12];
    void     *mbase = musb->mregs;
    int        status = 0;
    int        i;

    /* log core options (read using indexed model) */
    reg = musb_read_configdata(mbase);

    strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
    if (reg & MUSB_CONFIGDATA_DYNFIFO) {
        strcat(aInfo, ", dyn FIFOs");
        musb->dyn_fifo = true;
    }
#ifndef CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
    if (reg & MUSB_CONFIGDATA_MPRXE) {
        strcat(aInfo, ", bulk combine");
        musb->bulk_combine = true;
    }
    if (reg & MUSB_CONFIGDATA_MPTXE) {
        strcat(aInfo, ", bulk split");
        musb->bulk_split = true;
    }
#else
    musb->bulk_combine = false;
    musb->bulk_split = false;
#endif
    if (reg & MUSB_CONFIGDATA_HBRXE) {
        strcat(aInfo, ", HB-ISO Rx");
        musb->hb_iso_rx = true;
    }
    if (reg & MUSB_CONFIGDATA_HBTXE) {
        strcat(aInfo, ", HB-ISO Tx");
        musb->hb_iso_tx = true;
    }
    if (reg & MUSB_CONFIGDATA_SOFTCONE)
        strcat(aInfo, ", SoftConn");

    pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);

    aDate[0] = 0;
    if (MUSB_CONTROLLER_MHDRC == musb_type) {
        musb->is_multipoint = 1;
        type = "M";
    } else {
        musb->is_multipoint = 0;
        type = "";
#ifndef    CONFIG_USB_OTG_BLACKLIST_HUB
        pr_info("%s: kernel must blacklist external hubs\n",
            musb_driver_name);
#endif
    }

    /* log release info */
    musb->hwvers = musb_read_hwvers(mbase);
    //snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
    //    MUSB_HWVERS_MINOR(musb->hwvers),
    //    (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
    pr_debug("%s: %sHDRC RTL version.\n", musb_driver_name, type);

    /* configure ep0 */
    musb_configure_ep0(musb);

    /* discover endpoint configuration */
    musb->nr_endpoints = 1;
    musb->epmask = 1;

    if (musb->dyn_fifo)
        status = ep_config_from_table(musb);
    else
        status = ep_config_from_hw(musb);

    if (status < 0)
        return status;

    /* finish init, and print endpoint config */
    for (i = 0; i < musb->nr_endpoints; i++) {
        struct musb_hw_ep    *hw_ep = musb->endpoints + i;

        //hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
        hw_ep->fifo = MUSB_FIFO_OFFSET(i) + (void *)0xB1090000;

        hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
        hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
        hw_ep->rx_reinit = 1;
        hw_ep->tx_reinit = 1;

        if (hw_ep->max_packet_sz_tx) {
            dev_info(musb->controller,
                "%s: hw_ep %d%s, %smax %d\n",
                musb_driver_name, i,
                hw_ep->is_shared_fifo ? "shared" : "tx",
                hw_ep->tx_double_buffered
                    ? "doublebuffer, " : "",
                hw_ep->max_packet_sz_tx);
        }
        if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
            dev_info(musb->controller,
                "%s: hw_ep %d%s, %smax %d\n",
                musb_driver_name, i,
                "rx",
                hw_ep->rx_double_buffered
                    ? "doublebuffer, " : "",
                hw_ep->max_packet_sz_rx);
        }
        if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
            dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
    }

    return 0;
}


/*-------------------------------------------------------------------------*/
#ifdef CONFIG_USB_WITH_INTERRUPT
static HV_VOS_ISR_RESULT_E generic_interrupt(u32 irq, void *__hci)
#else
static irqreturn_t generic_interrupt(int irq, void *__hci)
#endif
{
    unsigned long    flags;
    irqreturn_t    retval = IRQ_NONE;
    struct musb    *musb = __hci;
    u8    int_hsdma = 0;

    USB_UNUSED(flags);
    spin_lock_irqsave(&musb->lock, flags);

    musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
    musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
    musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
    
#ifndef CONFIG_USB_MUSB_PIO_ONLY
    //szq for dma
    int_hsdma = musb_readb(musb->mregs, MUSB_HSDMA_INTR);
    if(int_hsdma)
        dma_controller_irq_dev(0, musb);
#endif

  //  pr_info("musb->int_usb is 0x%x,musb->int_tx is 0x%x,musb->int_rx is 0x%x.\n",musb->int_usb,musb->int_tx,musb->int_rx);
    if (musb->int_usb || musb->int_tx || musb->int_rx)
        retval = musb_interrupt_dev(musb);

    spin_unlock_irqrestore(&musb->lock, flags);
#ifdef CONFIG_USB_WITH_INTERRUPT
            return HV_VOS_ISR_HANDLED;
#else
            return retval;
#endif    
}

/*
 * handle all the irqs defined by the HDRC core. for now we expect:  other
 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
 * will be assigned, and the irq will already have been acked.
 *
 * called in irq context with spinlock held, irqs blocked
 */
irqreturn_t musb_interrupt_dev(struct musb *musb)
{
    irqreturn_t    retval = IRQ_NONE;
    u8        devctl, power;
    int        ep_num;
    u32        reg;
    u16     csr;

    devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
    power = musb_readb(musb->mregs, MUSB_POWER);


    /* the core can interrupt us for multiple reasons; docs have
     * a generic interrupt flowchart to follow
     */
    if (musb->int_usb)
        retval |= musb_stage0_irq(musb, musb->int_usb,
                devctl, power);

    /* "stage 1" is handling endpoint irqs */

    /* handle endpoint 0 first */
    if (musb->int_tx & 1) {
        if (devctl & MUSB_DEVCTL_HM) {
            //if (is_host_capable())
            //retval |= musb_h_ep0_irq(musb);
        } else {
            if (is_peripheral_capable())
                retval |= musb_g_ep0_irq(musb);
        }
    }

    /* RX on endpoints 1-15 */
    reg = musb->int_rx >> 1;
    ep_num = 1;
    while (reg) {
        if (reg & 1) {
            /* musb_ep_select(musb->mregs, ep_num); */
            /* REVISIT just retval = ep->rx_irq(...) */
            retval = IRQ_HANDLED;
            if (devctl & MUSB_DEVCTL_HM) {
                if (is_host_capable())
                    musb_host_rx(musb, ep_num);
            } else {
                if (is_peripheral_capable())
                    musb_g_rx(musb, ep_num);
            }
        }

        reg >>= 1;
        ep_num++;
    }

    /* TX on endpoints 1-15 */
    reg = musb->int_tx >> 1;
    ep_num = 1;
    while (reg) {
        if (reg & 1) {
            /* musb_ep_select(musb->mregs, ep_num); */
            /* REVISIT just retval |= ep->tx_irq(...) */
            retval = IRQ_HANDLED;
            if (devctl & MUSB_DEVCTL_HM) {
                if (is_host_capable())
                    musb_host_tx(musb, ep_num);
            } else {
                if (is_peripheral_capable())
                    musb_g_tx(musb, ep_num);
            }
        }
        reg >>= 1;
        ep_num++;
    }
    power = musb_readb(musb->mregs, MUSB_POWER);
    devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
    csr = musb_readw(musb->endpoints[0].regs, MUSB_CSR0);
    return retval;
}


#ifdef CONFIG_USB_WITH_INTERRUPT
void HS_HAL_USB_IRQHandler(u32 irqNum, void *arg) {
    generic_interrupt(irqNum, arg);
}
#endif


#ifndef CONFIG_USB_MUSB_PIO_ONLY
static bool use_dma = 1;

void musb_dma_completion_dev(struct musb *musb, u8 epnum, u8 transmit)
{
    u8    devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

    /* called with controller lock already held */

    if (!epnum) {
#ifndef CONFIG_USB_TUSB_OMAP_DMA
        if (!is_cppi_enabled()) {
            /* endpoint 0 */
            if (devctl & MUSB_DEVCTL_HM){
                //musb_h_ep0_irq(musb);
            }
            else
                musb_g_ep0_irq(musb);
        }
#endif
    } else {
        /* endpoints 1..15 */
        if (transmit) {
            if (devctl & MUSB_DEVCTL_HM) {
                if (is_host_capable())
                    musb_host_tx(musb, epnum);
            } else {
                if (is_peripheral_capable())
                    musb_g_tx(musb, epnum);
            }
        } else {
            /* receive */
            if (devctl & MUSB_DEVCTL_HM) {
                if (is_host_capable())
                    musb_host_rx(musb, epnum);
            } else {
                if (is_peripheral_capable())
                    musb_g_rx(musb, epnum);
            }
        }
    }
}

#else
#define use_dma            0
#endif

/*-------------------------------------------------------------------------*/



/* --------------------------------------------------------------------------
 * Init support
 */

static struct musb *__devinit
allocate_instance(struct device *dev,
        struct musb_hdrc_config *config, void  *mbase)
{
    struct musb        *musb;
    struct musb_hw_ep    *ep;
    int            epnum;

    musb = USB_MALLOC(sizeof(*musb));
    HV_MEMSET(musb, 0, (sizeof(*musb)));
    
    if (!musb){
        pr_info("musb malloc failed\n");
        return NULL;
    }

    INIT_LIST_HEAD(&musb->control);
    INIT_LIST_HEAD(&musb->in_bulk);
    INIT_LIST_HEAD(&musb->out_bulk);

    musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
    musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
    dev_set_drvdata(dev, musb);
    musb->mregs = mbase;
    musb->ctrl_base = mbase;
    musb->nIrq = -ENODEV;
    musb->config = config;
    BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
    for (epnum = 0, ep = musb->endpoints;
            epnum < musb->config->num_eps;
            epnum++, ep++) {
        ep->musb = musb;
        ep->epnum = epnum;
    }

    musb->controller = dev;

    return musb;
}

static void musb_free(struct musb *musb)
{
    /* this has multiple entry modes. it handles fault cleanup after
     * probe(), where things may be partially set up, as well as rmmod
     * cleanup after everything's been de-activated.
     */
    if (musb->nIrq >= 0) {
        if (musb->irq_wake)
            disable_irq_wake(musb->nIrq);
        free_irq(musb->nIrq, musb);
    }
#ifndef CONFIG_USB_MUSB_PIO_ONLY
    if (is_dma_capable() && musb->dma_controller) {
        struct dma_controller    *c = musb->dma_controller;

        if(c->stop)
        {
            (void) c->stop(c);
        }
        musbhs_dma_controller_destroy(c);
    }
#endif
    kfree(musb);
}

/*
 * Perform generic per-controller initialization.
 *
 * @pDevice: the controller (already clocked, etc)
 * @nIrq: irq
 * @mregs: virtual address of controller registers,
 *    not yet corrected for platform-specific offsets
 */

struct musb *
musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev,
                 void *ctrl)
{
    int            status;
    struct musb        *musb;
    int nIrq = 0;
    pr_debug("--->musb_init_controller \n");

    /* The driver might handle more features than the board; OK.
     * Fail when the board needs a feature that's not enabled.
     */
    if (!plat) {
        dev_dbg(dev, "no platform_data?\n");
        status = -ENODEV;
        goto fail0;
    }

    /* allocate */
    musb = allocate_instance(dev, plat->config, ctrl);
    if (!musb) {
        status = -ENOMEM;
        pr_info("musb malloc failed!\n");
        goto fail0;
    }

    pm_runtime_use_autosuspend(musb->controller);
    pm_runtime_set_autosuspend_delay(musb->controller, 200);
    pm_runtime_enable(musb->controller);

    spin_lock_init(&musb->lock);
    musb->board_mode = plat->mode;
    musb->board_set_power = plat->set_power;
    musb->min_power = plat->min_power;
    musb->ops = plat->platform_ops;

    /* The musb_platform_init() call:
     *   - adjusts musb->mregs and musb->isr if needed,
     *   - may initialize an integrated tranceiver
     *   - initializes musb->xceiv, usually by otg_get_phy()
     *   - stops powering VBUS
     *
     * There are various transceiver configurations.  Blackfin,
     * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
     * external/discrete ones in various flavors (twl4030 family,
     * isp1504, non-OTG, etc) mostly hooking up through ULPI.
     */

    status = musb_platform_init(musb);
    if (status < 0)
        goto fail1;
//#ifndef CONFIG_USB_WITH_INTERRUPT
    musb->isr = generic_interrupt;
    if (!musb->isr) {
        status = -ENODEV;
        goto fail2;
    }
//#endif


    pm_runtime_get_sync(musb->controller);

#ifndef CONFIG_USB_MUSB_PIO_ONLY
    if (use_dma) {
        struct dma_controller    *c;

        c = musbhs_dma_controller_create(musb, musb->mregs);
        musb->dma_controller = c;
    }
#endif

    /* be sure interrupts are disabled before connecting ISR */
    musb_platform_disable(musb);
    musb_generic_disable(musb);

    /* setup musb parts of the core (especially endpoints) */
    status = musb_core_init(plat->config->multipoint
            ? MUSB_CONTROLLER_MHDRC
            : MUSB_CONTROLLER_HDRC, musb);
    if (status < 0)
        goto fail3;

    /* attach to the IRQ */
    if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
        dev_err(dev, "request_irq %d failed!\n", nIrq);
        status = -ENODEV;
        goto fail3;
    }
#ifdef CONFIG_USB_WITH_INTERRUPT
    nIrq = 40;
#endif
    musb->nIrq = nIrq;
    
/* FIXME this handles wakeup irqs wrong */
    if (enable_irq_wake(nIrq) == 0) {
        musb->irq_wake = 1;
        device_init_wakeup(dev, 1);
    } else {
        musb->irq_wake = 0;
    }


    /* For the host-only role, we can activate right away.
     * (We expect the ID pin to be forcibly grounded!!)
     * Otherwise, wait till the gadget driver hooks up.
     */
    if (!is_otg_enabled(musb) && is_host_enabled(musb)) {

        MUSB_HST_MODE(musb);

    } else /* peripheral is enabled */ {
        MUSB_DEV_MODE(musb);

        if (is_peripheral_capable())
            status = musb_gadget_setup(musb);


    }
    if (status < 0)
        goto fail3;

    pm_runtime_put(musb->controller);

    /*
    pr_debug("USB %s mode controller at %x using %s, IRQ %d\n",
            ({char *s;
             switch (musb->board_mode) {
             case MUSB_HOST:        s = "Host"; break;
             case MUSB_PERIPHERAL:    s = "Peripheral"; break;
             default:        s = "OTG"; break;
             }; s; }),
            ctrl,
            (is_dma_capable() && musb->dma_controller)
            ? "DMA" : "PIO",
            musb->nIrq);
    */

    return status == 0 ? musb : NULL;


    musb_gadget_cleanup(musb);

fail3:
    pm_runtime_put_sync(musb->controller);
//#ifndef CONFIG_USB_WITH_INTERRUPT
fail2:
    if (musb->irq_wake)
        device_init_wakeup(dev, 0);
    musb_platform_exit(musb);
//#endif
fail1:
    dev_err(musb->controller,
        "musb_init_controller failed with status %d\n", status);

    musb_free(musb);

fail0:

    return status == 0 ? musb : NULL;

}


void musb_deinit_controller(struct musb *musb)
{
    musb_free(musb);
}

/*-------------------------------------------------------------------------*/

