#ifndef _HV_PAGE_HT7315_GIC_H_
#define _HV_PAGE_HT7315_GIC_H_

#ifndef HV_GIC_BASE_ADDRESS
    #define HV_GIC_BASE_ADDRESS                                         0x11089400
#endif


#define CPU_SYS_GIC0_IRQ_INTEN_L                                         (HV_GIC_BASE_ADDRESS + 0x000)

#define CPU_SYS_GIC0_IRQ_INTEN_L_struct                                  rs_cpu_sys_gic0_irq_inten_l

typedef struct _rs_cpu_sys_gic0_irq_inten_l  rs_cpu_sys_gic0_irq_inten_l;
struct _rs_cpu_sys_gic0_irq_inten_l {
    unsigned int REG0_IRQ_INTEN_L                           :32;
};
#define cpu_sys_gic0_irq_inten_l(val) ((rs_cpu_sys_gic0_irq_inten_l*)&(val))



#define CPU_SYS_GIC0_IRQ_INTEN_H                                         (HV_GIC_BASE_ADDRESS + 0x004)

#define CPU_SYS_GIC0_IRQ_INTEN_H_struct                                  rs_cpu_sys_gic0_irq_inten_h

typedef struct _rs_cpu_sys_gic0_irq_inten_h  rs_cpu_sys_gic0_irq_inten_h;
struct _rs_cpu_sys_gic0_irq_inten_h {
    unsigned int REG0_IRQ_INTEN_H                           :32;
};
#define cpu_sys_gic0_irq_inten_h(val) ((rs_cpu_sys_gic0_irq_inten_h*)&(val))



#define CPU_SYS_GIC0_IRQ_INTMASK_L                                       (HV_GIC_BASE_ADDRESS + 0x008)

#define CPU_SYS_GIC0_IRQ_INTMASK_L_struct                                rs_cpu_sys_gic0_irq_intmask_l

typedef struct _rs_cpu_sys_gic0_irq_intmask_l  rs_cpu_sys_gic0_irq_intmask_l;
struct _rs_cpu_sys_gic0_irq_intmask_l {
    unsigned int REG0_IRQ_INTMASK_L                         :32;
};
#define cpu_sys_gic0_irq_intmask_l(val) ((rs_cpu_sys_gic0_irq_intmask_l*)&(val))



#define CPU_SYS_GIC0_IRQ_INTMASK_H                                       (HV_GIC_BASE_ADDRESS + 0x00C)

#define CPU_SYS_GIC0_IRQ_INTMASK_H_struct                                rs_cpu_sys_gic0_irq_intmask_h

typedef struct _rs_cpu_sys_gic0_irq_intmask_h  rs_cpu_sys_gic0_irq_intmask_h;
struct _rs_cpu_sys_gic0_irq_intmask_h {
    unsigned int REG0_IRQ_INTMASK_H                         :32;
};
#define cpu_sys_gic0_irq_intmask_h(val) ((rs_cpu_sys_gic0_irq_intmask_h*)&(val))



#define CPU_SYS_GIC0_IRQ_INTFORCE_L                                      (HV_GIC_BASE_ADDRESS + 0x010)

#define CPU_SYS_GIC0_IRQ_INTFORCE_L_struct                               rs_cpu_sys_gic0_irq_intforce_l

typedef struct _rs_cpu_sys_gic0_irq_intforce_l  rs_cpu_sys_gic0_irq_intforce_l;
struct _rs_cpu_sys_gic0_irq_intforce_l {
    unsigned int REG0_IRQ_INTFORCE_L                        :32;
};
#define cpu_sys_gic0_irq_intforce_l(val) ((rs_cpu_sys_gic0_irq_intforce_l*)&(val))



#define CPU_SYS_GIC0_IRQ_INTFORCE_H                                      (HV_GIC_BASE_ADDRESS + 0x014)

#define CPU_SYS_GIC0_IRQ_INTFORCE_H_struct                               rs_cpu_sys_gic0_irq_intforce_h

typedef struct _rs_cpu_sys_gic0_irq_intforce_h  rs_cpu_sys_gic0_irq_intforce_h;
struct _rs_cpu_sys_gic0_irq_intforce_h {
    unsigned int REG0_IRQ_INTFORCE_H                        :32;
};
#define cpu_sys_gic0_irq_intforce_h(val) ((rs_cpu_sys_gic0_irq_intforce_h*)&(val))



#define CPU_SYS_GIC0_IRQ_RAWSTATUS_L                                     (HV_GIC_BASE_ADDRESS + 0x018)

#define CPU_SYS_GIC0_IRQ_RAWSTATUS_L_struct                              rs_cpu_sys_gic0_irq_rawstatus_l

typedef struct _rs_cpu_sys_gic0_irq_rawstatus_l  rs_cpu_sys_gic0_irq_rawstatus_l;
struct _rs_cpu_sys_gic0_irq_rawstatus_l {
    unsigned int REG0_IRQ_RAWSTATUS_L                       :32;
};
#define cpu_sys_gic0_irq_rawstatus_l(val) ((rs_cpu_sys_gic0_irq_rawstatus_l*)&(val))



#define CPU_SYS_GIC0_IRQ_RAWSTATUS_H                                     (HV_GIC_BASE_ADDRESS + 0x01C)

#define CPU_SYS_GIC0_IRQ_RAWSTATUS_H_struct                              rs_cpu_sys_gic0_irq_rawstatus_h

typedef struct _rs_cpu_sys_gic0_irq_rawstatus_h  rs_cpu_sys_gic0_irq_rawstatus_h;
struct _rs_cpu_sys_gic0_irq_rawstatus_h {
    unsigned int REG0_IRQ_RAWSTATUS_H                       :32;
};
#define cpu_sys_gic0_irq_rawstatus_h(val) ((rs_cpu_sys_gic0_irq_rawstatus_h*)&(val))



#define CPU_SYS_GIC0_IRQ_STATUS_L                                        (HV_GIC_BASE_ADDRESS + 0x020)

#define CPU_SYS_GIC0_IRQ_STATUS_L_struct                                 rs_cpu_sys_gic0_irq_status_l

typedef struct _rs_cpu_sys_gic0_irq_status_l  rs_cpu_sys_gic0_irq_status_l;
struct _rs_cpu_sys_gic0_irq_status_l {
    unsigned int REG0_IRQ_STATUS_L                          :32;
};
#define cpu_sys_gic0_irq_status_l(val) ((rs_cpu_sys_gic0_irq_status_l*)&(val))



#define CPU_SYS_GIC0_IRQ_STATUS_H                                        (HV_GIC_BASE_ADDRESS + 0x024)

#define CPU_SYS_GIC0_IRQ_STATUS_H_struct                                 rs_cpu_sys_gic0_irq_status_h

typedef struct _rs_cpu_sys_gic0_irq_status_h  rs_cpu_sys_gic0_irq_status_h;
struct _rs_cpu_sys_gic0_irq_status_h {
    unsigned int REG0_IRQ_STATUS_H                          :32;
};
#define cpu_sys_gic0_irq_status_h(val) ((rs_cpu_sys_gic0_irq_status_h*)&(val))



#define CPU_SYS_GIC0_IRQ_MASKSTATUS_L                                    (HV_GIC_BASE_ADDRESS + 0x028)

#define CPU_SYS_GIC0_IRQ_MASKSTATUS_L_struct                             rs_cpu_sys_gic0_irq_maskstatus_l

typedef struct _rs_cpu_sys_gic0_irq_maskstatus_l  rs_cpu_sys_gic0_irq_maskstatus_l;
struct _rs_cpu_sys_gic0_irq_maskstatus_l {
    unsigned int REG0_IRQ_MASKSTATUS_L                      :32;
};
#define cpu_sys_gic0_irq_maskstatus_l(val) ((rs_cpu_sys_gic0_irq_maskstatus_l*)&(val))



#define CPU_SYS_GIC0_IRQ_MASKSTATUS_H                                    (HV_GIC_BASE_ADDRESS + 0x02C)

#define CPU_SYS_GIC0_IRQ_MASKSTATUS_H_struct                             rs_cpu_sys_gic0_irq_maskstatus_h

typedef struct _rs_cpu_sys_gic0_irq_maskstatus_h  rs_cpu_sys_gic0_irq_maskstatus_h;
struct _rs_cpu_sys_gic0_irq_maskstatus_h {
    unsigned int REG0_IRQ_MASKSTATUS_H                      :32;
};
#define cpu_sys_gic0_irq_maskstatus_h(val) ((rs_cpu_sys_gic0_irq_maskstatus_h*)&(val))



#define CPU_SYS_GIC0_IRQ_FINALSTATUS_L                                   (HV_GIC_BASE_ADDRESS + 0x030)

#define CPU_SYS_GIC0_IRQ_FINALSTATUS_L_struct                            rs_cpu_sys_gic0_irq_finalstatus_l

typedef struct _rs_cpu_sys_gic0_irq_finalstatus_l  rs_cpu_sys_gic0_irq_finalstatus_l;
struct _rs_cpu_sys_gic0_irq_finalstatus_l {
    unsigned int REG0_IRQ_FINALSTATUS_L                     :32;
};
#define cpu_sys_gic0_irq_finalstatus_l(val) ((rs_cpu_sys_gic0_irq_finalstatus_l*)&(val))



#define CPU_SYS_GIC0_IRQ_FINALSTATUS_H                                   (HV_GIC_BASE_ADDRESS + 0x034)

#define CPU_SYS_GIC0_IRQ_FINALSTATUS_H_struct                            rs_cpu_sys_gic0_irq_finalstatus_h

typedef struct _rs_cpu_sys_gic0_irq_finalstatus_h  rs_cpu_sys_gic0_irq_finalstatus_h;
struct _rs_cpu_sys_gic0_irq_finalstatus_h {
    unsigned int REG0_IRQ_FINALSTATUS_H                     :32;
};
#define cpu_sys_gic0_irq_finalstatus_h(val) ((rs_cpu_sys_gic0_irq_finalstatus_h*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR                                          (HV_GIC_BASE_ADDRESS + 0x038)

#define CPU_SYS_GIC0_IRQ_VECTOR_struct                                   rs_cpu_sys_gic0_irq_vector

typedef struct _rs_cpu_sys_gic0_irq_vector  rs_cpu_sys_gic0_irq_vector;
struct _rs_cpu_sys_gic0_irq_vector {
    unsigned int REG0_IRQ_VECTOR                            :32;
};
#define cpu_sys_gic0_irq_vector(val) ((rs_cpu_sys_gic0_irq_vector*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_0                                        (HV_GIC_BASE_ADDRESS + 0x040)

#define CPU_SYS_GIC0_IRQ_VECTOR_0_struct                                 rs_cpu_sys_gic0_irq_vector_0

typedef struct _rs_cpu_sys_gic0_irq_vector_0  rs_cpu_sys_gic0_irq_vector_0;
struct _rs_cpu_sys_gic0_irq_vector_0 {
    unsigned int REG0_IRQ_VECTOR_0                          :32;
};
#define cpu_sys_gic0_irq_vector_0(val) ((rs_cpu_sys_gic0_irq_vector_0*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_1                                        (HV_GIC_BASE_ADDRESS + 0x048)

#define CPU_SYS_GIC0_IRQ_VECTOR_1_struct                                 rs_cpu_sys_gic0_irq_vector_1

typedef struct _rs_cpu_sys_gic0_irq_vector_1  rs_cpu_sys_gic0_irq_vector_1;
struct _rs_cpu_sys_gic0_irq_vector_1 {
    unsigned int REG0_IRQ_VECTOR_1                          :32;
};
#define cpu_sys_gic0_irq_vector_1(val) ((rs_cpu_sys_gic0_irq_vector_1*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_2                                        (HV_GIC_BASE_ADDRESS + 0x050)

#define CPU_SYS_GIC0_IRQ_VECTOR_2_struct                                 rs_cpu_sys_gic0_irq_vector_2

typedef struct _rs_cpu_sys_gic0_irq_vector_2  rs_cpu_sys_gic0_irq_vector_2;
struct _rs_cpu_sys_gic0_irq_vector_2 {
    unsigned int REG0_IRQ_VECTOR_2                          :32;
};
#define cpu_sys_gic0_irq_vector_2(val) ((rs_cpu_sys_gic0_irq_vector_2*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_3                                        (HV_GIC_BASE_ADDRESS + 0x058)

#define CPU_SYS_GIC0_IRQ_VECTOR_3_struct                                 rs_cpu_sys_gic0_irq_vector_3

typedef struct _rs_cpu_sys_gic0_irq_vector_3  rs_cpu_sys_gic0_irq_vector_3;
struct _rs_cpu_sys_gic0_irq_vector_3 {
    unsigned int REG0_IRQ_VECTOR_3                          :32;
};
#define cpu_sys_gic0_irq_vector_3(val) ((rs_cpu_sys_gic0_irq_vector_3*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_4                                        (HV_GIC_BASE_ADDRESS + 0x060)

#define CPU_SYS_GIC0_IRQ_VECTOR_4_struct                                 rs_cpu_sys_gic0_irq_vector_4

typedef struct _rs_cpu_sys_gic0_irq_vector_4  rs_cpu_sys_gic0_irq_vector_4;
struct _rs_cpu_sys_gic0_irq_vector_4 {
    unsigned int REG0_IRQ_VECTOR_4                          :32;
};
#define cpu_sys_gic0_irq_vector_4(val) ((rs_cpu_sys_gic0_irq_vector_4*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_5                                        (HV_GIC_BASE_ADDRESS + 0x068)

#define CPU_SYS_GIC0_IRQ_VECTOR_5_struct                                 rs_cpu_sys_gic0_irq_vector_5

typedef struct _rs_cpu_sys_gic0_irq_vector_5  rs_cpu_sys_gic0_irq_vector_5;
struct _rs_cpu_sys_gic0_irq_vector_5 {
    unsigned int REG0_IRQ_VECTOR_5                          :32;
};
#define cpu_sys_gic0_irq_vector_5(val) ((rs_cpu_sys_gic0_irq_vector_5*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_6                                        (HV_GIC_BASE_ADDRESS + 0x070)

#define CPU_SYS_GIC0_IRQ_VECTOR_6_struct                                 rs_cpu_sys_gic0_irq_vector_6

typedef struct _rs_cpu_sys_gic0_irq_vector_6  rs_cpu_sys_gic0_irq_vector_6;
struct _rs_cpu_sys_gic0_irq_vector_6 {
    unsigned int REG0_IRQ_VECTOR_6                          :32;
};
#define cpu_sys_gic0_irq_vector_6(val) ((rs_cpu_sys_gic0_irq_vector_6*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_7                                        (HV_GIC_BASE_ADDRESS + 0x078)

#define CPU_SYS_GIC0_IRQ_VECTOR_7_struct                                 rs_cpu_sys_gic0_irq_vector_7

typedef struct _rs_cpu_sys_gic0_irq_vector_7  rs_cpu_sys_gic0_irq_vector_7;
struct _rs_cpu_sys_gic0_irq_vector_7 {
    unsigned int REG0_IRQ_VECTOR_7                          :32;
};
#define cpu_sys_gic0_irq_vector_7(val) ((rs_cpu_sys_gic0_irq_vector_7*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_8                                        (HV_GIC_BASE_ADDRESS + 0x080)

#define CPU_SYS_GIC0_IRQ_VECTOR_8_struct                                 rs_cpu_sys_gic0_irq_vector_8

typedef struct _rs_cpu_sys_gic0_irq_vector_8  rs_cpu_sys_gic0_irq_vector_8;
struct _rs_cpu_sys_gic0_irq_vector_8 {
    unsigned int REG0_IRQ_VECTOR_8                          :32;
};
#define cpu_sys_gic0_irq_vector_8(val) ((rs_cpu_sys_gic0_irq_vector_8*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_9                                        (HV_GIC_BASE_ADDRESS + 0x088)

#define CPU_SYS_GIC0_IRQ_VECTOR_9_struct                                 rs_cpu_sys_gic0_irq_vector_9

typedef struct _rs_cpu_sys_gic0_irq_vector_9  rs_cpu_sys_gic0_irq_vector_9;
struct _rs_cpu_sys_gic0_irq_vector_9 {
    unsigned int REG0_IRQ_VECTOR_9                          :32;
};
#define cpu_sys_gic0_irq_vector_9(val) ((rs_cpu_sys_gic0_irq_vector_9*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_10                                       (HV_GIC_BASE_ADDRESS + 0x090)

#define CPU_SYS_GIC0_IRQ_VECTOR_10_struct                                rs_cpu_sys_gic0_irq_vector_10

typedef struct _rs_cpu_sys_gic0_irq_vector_10  rs_cpu_sys_gic0_irq_vector_10;
struct _rs_cpu_sys_gic0_irq_vector_10 {
    unsigned int REG0_IRQ_VECTOR_10                         :32;
};
#define cpu_sys_gic0_irq_vector_10(val) ((rs_cpu_sys_gic0_irq_vector_10*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_11                                       (HV_GIC_BASE_ADDRESS + 0x098)

#define CPU_SYS_GIC0_IRQ_VECTOR_11_struct                                rs_cpu_sys_gic0_irq_vector_11

typedef struct _rs_cpu_sys_gic0_irq_vector_11  rs_cpu_sys_gic0_irq_vector_11;
struct _rs_cpu_sys_gic0_irq_vector_11 {
    unsigned int REG0_IRQ_VECTOR_11                         :32;
};
#define cpu_sys_gic0_irq_vector_11(val) ((rs_cpu_sys_gic0_irq_vector_11*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_12                                       (HV_GIC_BASE_ADDRESS + 0x0A0)

#define CPU_SYS_GIC0_IRQ_VECTOR_12_struct                                rs_cpu_sys_gic0_irq_vector_12

typedef struct _rs_cpu_sys_gic0_irq_vector_12  rs_cpu_sys_gic0_irq_vector_12;
struct _rs_cpu_sys_gic0_irq_vector_12 {
    unsigned int REG0_IRQ_VECTOR_12                         :32;
};
#define cpu_sys_gic0_irq_vector_12(val) ((rs_cpu_sys_gic0_irq_vector_12*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_13                                       (HV_GIC_BASE_ADDRESS + 0x0A8)

#define CPU_SYS_GIC0_IRQ_VECTOR_13_struct                                rs_cpu_sys_gic0_irq_vector_13

typedef struct _rs_cpu_sys_gic0_irq_vector_13  rs_cpu_sys_gic0_irq_vector_13;
struct _rs_cpu_sys_gic0_irq_vector_13 {
    unsigned int REG0_IRQ_VECTOR_13                         :32;
};
#define cpu_sys_gic0_irq_vector_13(val) ((rs_cpu_sys_gic0_irq_vector_13*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_14                                       (HV_GIC_BASE_ADDRESS + 0x0B0)

#define CPU_SYS_GIC0_IRQ_VECTOR_14_struct                                rs_cpu_sys_gic0_irq_vector_14

typedef struct _rs_cpu_sys_gic0_irq_vector_14  rs_cpu_sys_gic0_irq_vector_14;
struct _rs_cpu_sys_gic0_irq_vector_14 {
    unsigned int REG0_IRQ_VECTOR_14                         :32;
};
#define cpu_sys_gic0_irq_vector_14(val) ((rs_cpu_sys_gic0_irq_vector_14*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_15                                       (HV_GIC_BASE_ADDRESS + 0x0B8)

#define CPU_SYS_GIC0_IRQ_VECTOR_15_struct                                rs_cpu_sys_gic0_irq_vector_15

typedef struct _rs_cpu_sys_gic0_irq_vector_15  rs_cpu_sys_gic0_irq_vector_15;
struct _rs_cpu_sys_gic0_irq_vector_15 {
    unsigned int REG0_IRQ_VECTOR_15                         :32;
};
#define cpu_sys_gic0_irq_vector_15(val) ((rs_cpu_sys_gic0_irq_vector_15*)&(val))



#define CPU_SYS_GIC0_FIQ_INTEN                                           (HV_GIC_BASE_ADDRESS + 0x0C0)

#define CPU_SYS_GIC0_FIQ_INTEN_struct                                    rs_cpu_sys_gic0_fiq_inten

typedef struct _rs_cpu_sys_gic0_fiq_inten  rs_cpu_sys_gic0_fiq_inten;
struct _rs_cpu_sys_gic0_fiq_inten {
    unsigned int REG0_FIQ_INTEN                             : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic0_fiq_inten(val) ((rs_cpu_sys_gic0_fiq_inten*)&(val))



#define CPU_SYS_GIC0_FIQ_INTMASK                                         (HV_GIC_BASE_ADDRESS + 0x0C4)

#define CPU_SYS_GIC0_FIQ_INTMASK_struct                                  rs_cpu_sys_gic0_fiq_intmask

typedef struct _rs_cpu_sys_gic0_fiq_intmask  rs_cpu_sys_gic0_fiq_intmask;
struct _rs_cpu_sys_gic0_fiq_intmask {
    unsigned int REG0_FIQ_INTMASK                           : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic0_fiq_intmask(val) ((rs_cpu_sys_gic0_fiq_intmask*)&(val))



#define CPU_SYS_GIC0_FIQ_INTFORCE                                        (HV_GIC_BASE_ADDRESS + 0x0C8)

#define CPU_SYS_GIC0_FIQ_INTFORCE_struct                                 rs_cpu_sys_gic0_fiq_intforce

typedef struct _rs_cpu_sys_gic0_fiq_intforce  rs_cpu_sys_gic0_fiq_intforce;
struct _rs_cpu_sys_gic0_fiq_intforce {
    unsigned int REG0_FIQ_INTFORCE                          : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic0_fiq_intforce(val) ((rs_cpu_sys_gic0_fiq_intforce*)&(val))



#define CPU_SYS_GIC0_FIQ_RAWSTATUS                                       (HV_GIC_BASE_ADDRESS + 0x0CC)

#define CPU_SYS_GIC0_FIQ_RAWSTATUS_struct                                rs_cpu_sys_gic0_fiq_rawstatus

typedef struct _rs_cpu_sys_gic0_fiq_rawstatus  rs_cpu_sys_gic0_fiq_rawstatus;
struct _rs_cpu_sys_gic0_fiq_rawstatus {
    unsigned int REG0_FIQ_RAWSTATUS                         : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic0_fiq_rawstatus(val) ((rs_cpu_sys_gic0_fiq_rawstatus*)&(val))



#define CPU_SYS_GIC0_FIQ_STATUS                                          (HV_GIC_BASE_ADDRESS + 0x0D0)

#define CPU_SYS_GIC0_FIQ_STATUS_struct                                   rs_cpu_sys_gic0_fiq_status

typedef struct _rs_cpu_sys_gic0_fiq_status  rs_cpu_sys_gic0_fiq_status;
struct _rs_cpu_sys_gic0_fiq_status {
    unsigned int REG0_FIQ_STATUS                            : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic0_fiq_status(val) ((rs_cpu_sys_gic0_fiq_status*)&(val))



#define CPU_SYS_GIC0_FIQ_FINALSTATUS                                     (HV_GIC_BASE_ADDRESS + 0x0D4)

#define CPU_SYS_GIC0_FIQ_FINALSTATUS_struct                              rs_cpu_sys_gic0_fiq_finalstatus

typedef struct _rs_cpu_sys_gic0_fiq_finalstatus  rs_cpu_sys_gic0_fiq_finalstatus;
struct _rs_cpu_sys_gic0_fiq_finalstatus {
    unsigned int REG0_FIQ_FINALSTATUS                       : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic0_fiq_finalstatus(val) ((rs_cpu_sys_gic0_fiq_finalstatus*)&(val))



#define CPU_SYS_GIC0_IRQ_PLEVEL                                          (HV_GIC_BASE_ADDRESS + 0x0D8)

#define CPU_SYS_GIC0_IRQ_PLEVEL_struct                                   rs_cpu_sys_gic0_irq_plevel

typedef struct _rs_cpu_sys_gic0_irq_plevel  rs_cpu_sys_gic0_irq_plevel;
struct _rs_cpu_sys_gic0_irq_plevel {
    unsigned int REG0_IRQ_PLEVEL                            : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_plevel(val) ((rs_cpu_sys_gic0_irq_plevel*)&(val))



#define CPU_SYS_GIC0_IRQ_INTERNAL_PLEVEL                                 (HV_GIC_BASE_ADDRESS + 0x0DC)

#define CPU_SYS_GIC0_IRQ_INTERNAL_PLEVEL_struct                          rs_cpu_sys_gic0_irq_internal_plevel

typedef struct _rs_cpu_sys_gic0_irq_internal_plevel  rs_cpu_sys_gic0_irq_internal_plevel;
struct _rs_cpu_sys_gic0_irq_internal_plevel {
    unsigned int REG0_IRQ_INTERNAL_PLEVEL                   : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_gic0_irq_internal_plevel(val) ((rs_cpu_sys_gic0_irq_internal_plevel*)&(val))



#define CPU_SYS_GIC0_ICTL_VERSION_ID                                     (HV_GIC_BASE_ADDRESS + 0x0E0)

#define CPU_SYS_GIC0_ICTL_VERSION_ID_struct                              rs_cpu_sys_gic0_ictl_version_id

typedef struct _rs_cpu_sys_gic0_ictl_version_id  rs_cpu_sys_gic0_ictl_version_id;
struct _rs_cpu_sys_gic0_ictl_version_id {
    unsigned int REG0_ICTL_VERSION_ID                       :32;
};
#define cpu_sys_gic0_ictl_version_id(val) ((rs_cpu_sys_gic0_ictl_version_id*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_0                                            (HV_GIC_BASE_ADDRESS + 0x0E8)

#define CPU_SYS_GIC0_IRQ_PR_0_struct                                     rs_cpu_sys_gic0_irq_pr_0

typedef struct _rs_cpu_sys_gic0_irq_pr_0  rs_cpu_sys_gic0_irq_pr_0;
struct _rs_cpu_sys_gic0_irq_pr_0 {
    unsigned int REG0_IRQ_PR_0                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_0(val) ((rs_cpu_sys_gic0_irq_pr_0*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_1                                            (HV_GIC_BASE_ADDRESS + 0x0EC)

#define CPU_SYS_GIC0_IRQ_PR_1_struct                                     rs_cpu_sys_gic0_irq_pr_1

typedef struct _rs_cpu_sys_gic0_irq_pr_1  rs_cpu_sys_gic0_irq_pr_1;
struct _rs_cpu_sys_gic0_irq_pr_1 {
    unsigned int REG0_IRQ_PR_1                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_1(val) ((rs_cpu_sys_gic0_irq_pr_1*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_2                                            (HV_GIC_BASE_ADDRESS + 0x0F0)

#define CPU_SYS_GIC0_IRQ_PR_2_struct                                     rs_cpu_sys_gic0_irq_pr_2

typedef struct _rs_cpu_sys_gic0_irq_pr_2  rs_cpu_sys_gic0_irq_pr_2;
struct _rs_cpu_sys_gic0_irq_pr_2 {
    unsigned int REG0_IRQ_PR_2                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_2(val) ((rs_cpu_sys_gic0_irq_pr_2*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_3                                            (HV_GIC_BASE_ADDRESS + 0x0F4)

#define CPU_SYS_GIC0_IRQ_PR_3_struct                                     rs_cpu_sys_gic0_irq_pr_3

typedef struct _rs_cpu_sys_gic0_irq_pr_3  rs_cpu_sys_gic0_irq_pr_3;
struct _rs_cpu_sys_gic0_irq_pr_3 {
    unsigned int REG0_IRQ_PR_3                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_3(val) ((rs_cpu_sys_gic0_irq_pr_3*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_4                                            (HV_GIC_BASE_ADDRESS + 0x0F8)

#define CPU_SYS_GIC0_IRQ_PR_4_struct                                     rs_cpu_sys_gic0_irq_pr_4

typedef struct _rs_cpu_sys_gic0_irq_pr_4  rs_cpu_sys_gic0_irq_pr_4;
struct _rs_cpu_sys_gic0_irq_pr_4 {
    unsigned int REG0_IRQ_PR_4                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_4(val) ((rs_cpu_sys_gic0_irq_pr_4*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_5                                            (HV_GIC_BASE_ADDRESS + 0x0FC)

#define CPU_SYS_GIC0_IRQ_PR_5_struct                                     rs_cpu_sys_gic0_irq_pr_5

typedef struct _rs_cpu_sys_gic0_irq_pr_5  rs_cpu_sys_gic0_irq_pr_5;
struct _rs_cpu_sys_gic0_irq_pr_5 {
    unsigned int REG0_IRQ_PR_5                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_5(val) ((rs_cpu_sys_gic0_irq_pr_5*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_6                                            (HV_GIC_BASE_ADDRESS + 0x100)

#define CPU_SYS_GIC0_IRQ_PR_6_struct                                     rs_cpu_sys_gic0_irq_pr_6

typedef struct _rs_cpu_sys_gic0_irq_pr_6  rs_cpu_sys_gic0_irq_pr_6;
struct _rs_cpu_sys_gic0_irq_pr_6 {
    unsigned int REG0_IRQ_PR_6                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_6(val) ((rs_cpu_sys_gic0_irq_pr_6*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_7                                            (HV_GIC_BASE_ADDRESS + 0x104)

#define CPU_SYS_GIC0_IRQ_PR_7_struct                                     rs_cpu_sys_gic0_irq_pr_7

typedef struct _rs_cpu_sys_gic0_irq_pr_7  rs_cpu_sys_gic0_irq_pr_7;
struct _rs_cpu_sys_gic0_irq_pr_7 {
    unsigned int REG0_IRQ_PR_7                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_7(val) ((rs_cpu_sys_gic0_irq_pr_7*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_8                                            (HV_GIC_BASE_ADDRESS + 0x108)

#define CPU_SYS_GIC0_IRQ_PR_8_struct                                     rs_cpu_sys_gic0_irq_pr_8

typedef struct _rs_cpu_sys_gic0_irq_pr_8  rs_cpu_sys_gic0_irq_pr_8;
struct _rs_cpu_sys_gic0_irq_pr_8 {
    unsigned int REG0_IRQ_PR_8                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_8(val) ((rs_cpu_sys_gic0_irq_pr_8*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_9                                            (HV_GIC_BASE_ADDRESS + 0x10C)

#define CPU_SYS_GIC0_IRQ_PR_9_struct                                     rs_cpu_sys_gic0_irq_pr_9

typedef struct _rs_cpu_sys_gic0_irq_pr_9  rs_cpu_sys_gic0_irq_pr_9;
struct _rs_cpu_sys_gic0_irq_pr_9 {
    unsigned int REG0_IRQ_PR_9                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_9(val) ((rs_cpu_sys_gic0_irq_pr_9*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_10                                           (HV_GIC_BASE_ADDRESS + 0x110)

#define CPU_SYS_GIC0_IRQ_PR_10_struct                                    rs_cpu_sys_gic0_irq_pr_10

typedef struct _rs_cpu_sys_gic0_irq_pr_10  rs_cpu_sys_gic0_irq_pr_10;
struct _rs_cpu_sys_gic0_irq_pr_10 {
    unsigned int REG0_IRQ_PR_10                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_10(val) ((rs_cpu_sys_gic0_irq_pr_10*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_11                                           (HV_GIC_BASE_ADDRESS + 0x114)

#define CPU_SYS_GIC0_IRQ_PR_11_struct                                    rs_cpu_sys_gic0_irq_pr_11

typedef struct _rs_cpu_sys_gic0_irq_pr_11  rs_cpu_sys_gic0_irq_pr_11;
struct _rs_cpu_sys_gic0_irq_pr_11 {
    unsigned int REG0_IRQ_PR_11                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_11(val) ((rs_cpu_sys_gic0_irq_pr_11*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_12                                           (HV_GIC_BASE_ADDRESS + 0x118)

#define CPU_SYS_GIC0_IRQ_PR_12_struct                                    rs_cpu_sys_gic0_irq_pr_12

typedef struct _rs_cpu_sys_gic0_irq_pr_12  rs_cpu_sys_gic0_irq_pr_12;
struct _rs_cpu_sys_gic0_irq_pr_12 {
    unsigned int REG0_IRQ_PR_12                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_12(val) ((rs_cpu_sys_gic0_irq_pr_12*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_13                                           (HV_GIC_BASE_ADDRESS + 0x11C)

#define CPU_SYS_GIC0_IRQ_PR_13_struct                                    rs_cpu_sys_gic0_irq_pr_13

typedef struct _rs_cpu_sys_gic0_irq_pr_13  rs_cpu_sys_gic0_irq_pr_13;
struct _rs_cpu_sys_gic0_irq_pr_13 {
    unsigned int REG0_IRQ_PR_13                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_13(val) ((rs_cpu_sys_gic0_irq_pr_13*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_14                                           (HV_GIC_BASE_ADDRESS + 0x120)

#define CPU_SYS_GIC0_IRQ_PR_14_struct                                    rs_cpu_sys_gic0_irq_pr_14

typedef struct _rs_cpu_sys_gic0_irq_pr_14  rs_cpu_sys_gic0_irq_pr_14;
struct _rs_cpu_sys_gic0_irq_pr_14 {
    unsigned int REG0_IRQ_PR_14                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_14(val) ((rs_cpu_sys_gic0_irq_pr_14*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_15                                           (HV_GIC_BASE_ADDRESS + 0x124)

#define CPU_SYS_GIC0_IRQ_PR_15_struct                                    rs_cpu_sys_gic0_irq_pr_15

typedef struct _rs_cpu_sys_gic0_irq_pr_15  rs_cpu_sys_gic0_irq_pr_15;
struct _rs_cpu_sys_gic0_irq_pr_15 {
    unsigned int REG0_IRQ_PR_15                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_15(val) ((rs_cpu_sys_gic0_irq_pr_15*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_16                                           (HV_GIC_BASE_ADDRESS + 0x128)

#define CPU_SYS_GIC0_IRQ_PR_16_struct                                    rs_cpu_sys_gic0_irq_pr_16

typedef struct _rs_cpu_sys_gic0_irq_pr_16  rs_cpu_sys_gic0_irq_pr_16;
struct _rs_cpu_sys_gic0_irq_pr_16 {
    unsigned int REG0_IRQ_PR_16                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_16(val) ((rs_cpu_sys_gic0_irq_pr_16*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_17                                           (HV_GIC_BASE_ADDRESS + 0x12C)

#define CPU_SYS_GIC0_IRQ_PR_17_struct                                    rs_cpu_sys_gic0_irq_pr_17

typedef struct _rs_cpu_sys_gic0_irq_pr_17  rs_cpu_sys_gic0_irq_pr_17;
struct _rs_cpu_sys_gic0_irq_pr_17 {
    unsigned int REG0_IRQ_PR_17                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_17(val) ((rs_cpu_sys_gic0_irq_pr_17*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_18                                           (HV_GIC_BASE_ADDRESS + 0x130)

#define CPU_SYS_GIC0_IRQ_PR_18_struct                                    rs_cpu_sys_gic0_irq_pr_18

typedef struct _rs_cpu_sys_gic0_irq_pr_18  rs_cpu_sys_gic0_irq_pr_18;
struct _rs_cpu_sys_gic0_irq_pr_18 {
    unsigned int REG0_IRQ_PR_18                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_18(val) ((rs_cpu_sys_gic0_irq_pr_18*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_19                                           (HV_GIC_BASE_ADDRESS + 0x134)

#define CPU_SYS_GIC0_IRQ_PR_19_struct                                    rs_cpu_sys_gic0_irq_pr_19

typedef struct _rs_cpu_sys_gic0_irq_pr_19  rs_cpu_sys_gic0_irq_pr_19;
struct _rs_cpu_sys_gic0_irq_pr_19 {
    unsigned int REG0_IRQ_PR_19                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_19(val) ((rs_cpu_sys_gic0_irq_pr_19*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_20                                           (HV_GIC_BASE_ADDRESS + 0x138)

#define CPU_SYS_GIC0_IRQ_PR_20_struct                                    rs_cpu_sys_gic0_irq_pr_20

typedef struct _rs_cpu_sys_gic0_irq_pr_20  rs_cpu_sys_gic0_irq_pr_20;
struct _rs_cpu_sys_gic0_irq_pr_20 {
    unsigned int REG0_IRQ_PR_20                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_20(val) ((rs_cpu_sys_gic0_irq_pr_20*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_21                                           (HV_GIC_BASE_ADDRESS + 0x13C)

#define CPU_SYS_GIC0_IRQ_PR_21_struct                                    rs_cpu_sys_gic0_irq_pr_21

typedef struct _rs_cpu_sys_gic0_irq_pr_21  rs_cpu_sys_gic0_irq_pr_21;
struct _rs_cpu_sys_gic0_irq_pr_21 {
    unsigned int REG0_IRQ_PR_21                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_21(val) ((rs_cpu_sys_gic0_irq_pr_21*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_22                                           (HV_GIC_BASE_ADDRESS + 0x140)

#define CPU_SYS_GIC0_IRQ_PR_22_struct                                    rs_cpu_sys_gic0_irq_pr_22

typedef struct _rs_cpu_sys_gic0_irq_pr_22  rs_cpu_sys_gic0_irq_pr_22;
struct _rs_cpu_sys_gic0_irq_pr_22 {
    unsigned int REG0_IRQ_PR_22                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_22(val) ((rs_cpu_sys_gic0_irq_pr_22*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_23                                           (HV_GIC_BASE_ADDRESS + 0x144)

#define CPU_SYS_GIC0_IRQ_PR_23_struct                                    rs_cpu_sys_gic0_irq_pr_23

typedef struct _rs_cpu_sys_gic0_irq_pr_23  rs_cpu_sys_gic0_irq_pr_23;
struct _rs_cpu_sys_gic0_irq_pr_23 {
    unsigned int REG0_IRQ_PR_23                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_23(val) ((rs_cpu_sys_gic0_irq_pr_23*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_24                                           (HV_GIC_BASE_ADDRESS + 0x148)

#define CPU_SYS_GIC0_IRQ_PR_24_struct                                    rs_cpu_sys_gic0_irq_pr_24

typedef struct _rs_cpu_sys_gic0_irq_pr_24  rs_cpu_sys_gic0_irq_pr_24;
struct _rs_cpu_sys_gic0_irq_pr_24 {
    unsigned int REG0_IRQ_PR_24                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_24(val) ((rs_cpu_sys_gic0_irq_pr_24*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_25                                           (HV_GIC_BASE_ADDRESS + 0x14C)

#define CPU_SYS_GIC0_IRQ_PR_25_struct                                    rs_cpu_sys_gic0_irq_pr_25

typedef struct _rs_cpu_sys_gic0_irq_pr_25  rs_cpu_sys_gic0_irq_pr_25;
struct _rs_cpu_sys_gic0_irq_pr_25 {
    unsigned int REG0_IRQ_PR_25                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_25(val) ((rs_cpu_sys_gic0_irq_pr_25*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_26                                           (HV_GIC_BASE_ADDRESS + 0x150)

#define CPU_SYS_GIC0_IRQ_PR_26_struct                                    rs_cpu_sys_gic0_irq_pr_26

typedef struct _rs_cpu_sys_gic0_irq_pr_26  rs_cpu_sys_gic0_irq_pr_26;
struct _rs_cpu_sys_gic0_irq_pr_26 {
    unsigned int REG0_IRQ_PR_26                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_26(val) ((rs_cpu_sys_gic0_irq_pr_26*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_27                                           (HV_GIC_BASE_ADDRESS + 0x154)

#define CPU_SYS_GIC0_IRQ_PR_27_struct                                    rs_cpu_sys_gic0_irq_pr_27

typedef struct _rs_cpu_sys_gic0_irq_pr_27  rs_cpu_sys_gic0_irq_pr_27;
struct _rs_cpu_sys_gic0_irq_pr_27 {
    unsigned int REG0_IRQ_PR_27                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_27(val) ((rs_cpu_sys_gic0_irq_pr_27*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_28                                           (HV_GIC_BASE_ADDRESS + 0x158)

#define CPU_SYS_GIC0_IRQ_PR_28_struct                                    rs_cpu_sys_gic0_irq_pr_28

typedef struct _rs_cpu_sys_gic0_irq_pr_28  rs_cpu_sys_gic0_irq_pr_28;
struct _rs_cpu_sys_gic0_irq_pr_28 {
    unsigned int REG0_IRQ_PR_28                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_28(val) ((rs_cpu_sys_gic0_irq_pr_28*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_29                                           (HV_GIC_BASE_ADDRESS + 0x15C)

#define CPU_SYS_GIC0_IRQ_PR_29_struct                                    rs_cpu_sys_gic0_irq_pr_29

typedef struct _rs_cpu_sys_gic0_irq_pr_29  rs_cpu_sys_gic0_irq_pr_29;
struct _rs_cpu_sys_gic0_irq_pr_29 {
    unsigned int REG0_IRQ_PR_29                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_29(val) ((rs_cpu_sys_gic0_irq_pr_29*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_30                                           (HV_GIC_BASE_ADDRESS + 0x160)

#define CPU_SYS_GIC0_IRQ_PR_30_struct                                    rs_cpu_sys_gic0_irq_pr_30

typedef struct _rs_cpu_sys_gic0_irq_pr_30  rs_cpu_sys_gic0_irq_pr_30;
struct _rs_cpu_sys_gic0_irq_pr_30 {
    unsigned int REG0_IRQ_PR_30                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_30(val) ((rs_cpu_sys_gic0_irq_pr_30*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_31                                           (HV_GIC_BASE_ADDRESS + 0x164)

#define CPU_SYS_GIC0_IRQ_PR_31_struct                                    rs_cpu_sys_gic0_irq_pr_31

typedef struct _rs_cpu_sys_gic0_irq_pr_31  rs_cpu_sys_gic0_irq_pr_31;
struct _rs_cpu_sys_gic0_irq_pr_31 {
    unsigned int REG0_IRQ_PR_31                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_31(val) ((rs_cpu_sys_gic0_irq_pr_31*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_32                                           (HV_GIC_BASE_ADDRESS + 0x168)

#define CPU_SYS_GIC0_IRQ_PR_32_struct                                    rs_cpu_sys_gic0_irq_pr_32

typedef struct _rs_cpu_sys_gic0_irq_pr_32  rs_cpu_sys_gic0_irq_pr_32;
struct _rs_cpu_sys_gic0_irq_pr_32 {
    unsigned int REG0_IRQ_PR_32                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_32(val) ((rs_cpu_sys_gic0_irq_pr_32*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_33                                           (HV_GIC_BASE_ADDRESS + 0x16C)

#define CPU_SYS_GIC0_IRQ_PR_33_struct                                    rs_cpu_sys_gic0_irq_pr_33

typedef struct _rs_cpu_sys_gic0_irq_pr_33  rs_cpu_sys_gic0_irq_pr_33;
struct _rs_cpu_sys_gic0_irq_pr_33 {
    unsigned int REG0_IRQ_PR_33                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_33(val) ((rs_cpu_sys_gic0_irq_pr_33*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_34                                           (HV_GIC_BASE_ADDRESS + 0x170)

#define CPU_SYS_GIC0_IRQ_PR_34_struct                                    rs_cpu_sys_gic0_irq_pr_34

typedef struct _rs_cpu_sys_gic0_irq_pr_34  rs_cpu_sys_gic0_irq_pr_34;
struct _rs_cpu_sys_gic0_irq_pr_34 {
    unsigned int REG0_IRQ_PR_34                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_34(val) ((rs_cpu_sys_gic0_irq_pr_34*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_35                                           (HV_GIC_BASE_ADDRESS + 0x174)

#define CPU_SYS_GIC0_IRQ_PR_35_struct                                    rs_cpu_sys_gic0_irq_pr_35

typedef struct _rs_cpu_sys_gic0_irq_pr_35  rs_cpu_sys_gic0_irq_pr_35;
struct _rs_cpu_sys_gic0_irq_pr_35 {
    unsigned int REG0_IRQ_PR_35                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_35(val) ((rs_cpu_sys_gic0_irq_pr_35*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_36                                           (HV_GIC_BASE_ADDRESS + 0x178)

#define CPU_SYS_GIC0_IRQ_PR_36_struct                                    rs_cpu_sys_gic0_irq_pr_36

typedef struct _rs_cpu_sys_gic0_irq_pr_36  rs_cpu_sys_gic0_irq_pr_36;
struct _rs_cpu_sys_gic0_irq_pr_36 {
    unsigned int REG0_IRQ_PR_36                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_36(val) ((rs_cpu_sys_gic0_irq_pr_36*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_37                                           (HV_GIC_BASE_ADDRESS + 0x17C)

#define CPU_SYS_GIC0_IRQ_PR_37_struct                                    rs_cpu_sys_gic0_irq_pr_37

typedef struct _rs_cpu_sys_gic0_irq_pr_37  rs_cpu_sys_gic0_irq_pr_37;
struct _rs_cpu_sys_gic0_irq_pr_37 {
    unsigned int REG0_IRQ_PR_37                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_37(val) ((rs_cpu_sys_gic0_irq_pr_37*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_38                                           (HV_GIC_BASE_ADDRESS + 0x180)

#define CPU_SYS_GIC0_IRQ_PR_38_struct                                    rs_cpu_sys_gic0_irq_pr_38

typedef struct _rs_cpu_sys_gic0_irq_pr_38  rs_cpu_sys_gic0_irq_pr_38;
struct _rs_cpu_sys_gic0_irq_pr_38 {
    unsigned int REG0_IRQ_PR_38                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_38(val) ((rs_cpu_sys_gic0_irq_pr_38*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_39                                           (HV_GIC_BASE_ADDRESS + 0x184)

#define CPU_SYS_GIC0_IRQ_PR_39_struct                                    rs_cpu_sys_gic0_irq_pr_39

typedef struct _rs_cpu_sys_gic0_irq_pr_39  rs_cpu_sys_gic0_irq_pr_39;
struct _rs_cpu_sys_gic0_irq_pr_39 {
    unsigned int REG0_IRQ_PR_39                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_39(val) ((rs_cpu_sys_gic0_irq_pr_39*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_40                                           (HV_GIC_BASE_ADDRESS + 0x188)

#define CPU_SYS_GIC0_IRQ_PR_40_struct                                    rs_cpu_sys_gic0_irq_pr_40

typedef struct _rs_cpu_sys_gic0_irq_pr_40  rs_cpu_sys_gic0_irq_pr_40;
struct _rs_cpu_sys_gic0_irq_pr_40 {
    unsigned int REG0_IRQ_PR_40                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_40(val) ((rs_cpu_sys_gic0_irq_pr_40*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_41                                           (HV_GIC_BASE_ADDRESS + 0x18C)

#define CPU_SYS_GIC0_IRQ_PR_41_struct                                    rs_cpu_sys_gic0_irq_pr_41

typedef struct _rs_cpu_sys_gic0_irq_pr_41  rs_cpu_sys_gic0_irq_pr_41;
struct _rs_cpu_sys_gic0_irq_pr_41 {
    unsigned int REG0_IRQ_PR_41                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_41(val) ((rs_cpu_sys_gic0_irq_pr_41*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_42                                           (HV_GIC_BASE_ADDRESS + 0x190)

#define CPU_SYS_GIC0_IRQ_PR_42_struct                                    rs_cpu_sys_gic0_irq_pr_42

typedef struct _rs_cpu_sys_gic0_irq_pr_42  rs_cpu_sys_gic0_irq_pr_42;
struct _rs_cpu_sys_gic0_irq_pr_42 {
    unsigned int REG0_IRQ_PR_42                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_42(val) ((rs_cpu_sys_gic0_irq_pr_42*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_43                                           (HV_GIC_BASE_ADDRESS + 0x194)

#define CPU_SYS_GIC0_IRQ_PR_43_struct                                    rs_cpu_sys_gic0_irq_pr_43

typedef struct _rs_cpu_sys_gic0_irq_pr_43  rs_cpu_sys_gic0_irq_pr_43;
struct _rs_cpu_sys_gic0_irq_pr_43 {
    unsigned int REG0_IRQ_PR_43                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_43(val) ((rs_cpu_sys_gic0_irq_pr_43*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_44                                           (HV_GIC_BASE_ADDRESS + 0x198)

#define CPU_SYS_GIC0_IRQ_PR_44_struct                                    rs_cpu_sys_gic0_irq_pr_44

typedef struct _rs_cpu_sys_gic0_irq_pr_44  rs_cpu_sys_gic0_irq_pr_44;
struct _rs_cpu_sys_gic0_irq_pr_44 {
    unsigned int REG0_IRQ_PR_44                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_44(val) ((rs_cpu_sys_gic0_irq_pr_44*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_45                                           (HV_GIC_BASE_ADDRESS + 0x19C)

#define CPU_SYS_GIC0_IRQ_PR_45_struct                                    rs_cpu_sys_gic0_irq_pr_45

typedef struct _rs_cpu_sys_gic0_irq_pr_45  rs_cpu_sys_gic0_irq_pr_45;
struct _rs_cpu_sys_gic0_irq_pr_45 {
    unsigned int REG0_IRQ_PR_45                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_45(val) ((rs_cpu_sys_gic0_irq_pr_45*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_46                                           (HV_GIC_BASE_ADDRESS + 0x1A0)

#define CPU_SYS_GIC0_IRQ_PR_46_struct                                    rs_cpu_sys_gic0_irq_pr_46

typedef struct _rs_cpu_sys_gic0_irq_pr_46  rs_cpu_sys_gic0_irq_pr_46;
struct _rs_cpu_sys_gic0_irq_pr_46 {
    unsigned int REG0_IRQ_PR_46                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_46(val) ((rs_cpu_sys_gic0_irq_pr_46*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_47                                           (HV_GIC_BASE_ADDRESS + 0x1A4)

#define CPU_SYS_GIC0_IRQ_PR_47_struct                                    rs_cpu_sys_gic0_irq_pr_47

typedef struct _rs_cpu_sys_gic0_irq_pr_47  rs_cpu_sys_gic0_irq_pr_47;
struct _rs_cpu_sys_gic0_irq_pr_47 {
    unsigned int REG0_IRQ_PR_47                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_47(val) ((rs_cpu_sys_gic0_irq_pr_47*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_48                                           (HV_GIC_BASE_ADDRESS + 0x1A8)

#define CPU_SYS_GIC0_IRQ_PR_48_struct                                    rs_cpu_sys_gic0_irq_pr_48

typedef struct _rs_cpu_sys_gic0_irq_pr_48  rs_cpu_sys_gic0_irq_pr_48;
struct _rs_cpu_sys_gic0_irq_pr_48 {
    unsigned int REG0_IRQ_PR_48                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_48(val) ((rs_cpu_sys_gic0_irq_pr_48*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_49                                           (HV_GIC_BASE_ADDRESS + 0x1AC)

#define CPU_SYS_GIC0_IRQ_PR_49_struct                                    rs_cpu_sys_gic0_irq_pr_49

typedef struct _rs_cpu_sys_gic0_irq_pr_49  rs_cpu_sys_gic0_irq_pr_49;
struct _rs_cpu_sys_gic0_irq_pr_49 {
    unsigned int REG0_IRQ_PR_49                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_49(val) ((rs_cpu_sys_gic0_irq_pr_49*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_50                                           (HV_GIC_BASE_ADDRESS + 0x1B0)

#define CPU_SYS_GIC0_IRQ_PR_50_struct                                    rs_cpu_sys_gic0_irq_pr_50

typedef struct _rs_cpu_sys_gic0_irq_pr_50  rs_cpu_sys_gic0_irq_pr_50;
struct _rs_cpu_sys_gic0_irq_pr_50 {
    unsigned int REG0_IRQ_PR_50                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_50(val) ((rs_cpu_sys_gic0_irq_pr_50*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_51                                           (HV_GIC_BASE_ADDRESS + 0x1B4)

#define CPU_SYS_GIC0_IRQ_PR_51_struct                                    rs_cpu_sys_gic0_irq_pr_51

typedef struct _rs_cpu_sys_gic0_irq_pr_51  rs_cpu_sys_gic0_irq_pr_51;
struct _rs_cpu_sys_gic0_irq_pr_51 {
    unsigned int REG0_IRQ_PR_51                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_51(val) ((rs_cpu_sys_gic0_irq_pr_51*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_52                                           (HV_GIC_BASE_ADDRESS + 0x1B8)

#define CPU_SYS_GIC0_IRQ_PR_52_struct                                    rs_cpu_sys_gic0_irq_pr_52

typedef struct _rs_cpu_sys_gic0_irq_pr_52  rs_cpu_sys_gic0_irq_pr_52;
struct _rs_cpu_sys_gic0_irq_pr_52 {
    unsigned int REG0_IRQ_PR_52                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_52(val) ((rs_cpu_sys_gic0_irq_pr_52*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_53                                           (HV_GIC_BASE_ADDRESS + 0x1BC)

#define CPU_SYS_GIC0_IRQ_PR_53_struct                                    rs_cpu_sys_gic0_irq_pr_53

typedef struct _rs_cpu_sys_gic0_irq_pr_53  rs_cpu_sys_gic0_irq_pr_53;
struct _rs_cpu_sys_gic0_irq_pr_53 {
    unsigned int REG0_IRQ_PR_53                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_53(val) ((rs_cpu_sys_gic0_irq_pr_53*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_54                                           (HV_GIC_BASE_ADDRESS + 0x1C0)

#define CPU_SYS_GIC0_IRQ_PR_54_struct                                    rs_cpu_sys_gic0_irq_pr_54

typedef struct _rs_cpu_sys_gic0_irq_pr_54  rs_cpu_sys_gic0_irq_pr_54;
struct _rs_cpu_sys_gic0_irq_pr_54 {
    unsigned int REG0_IRQ_PR_54                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_54(val) ((rs_cpu_sys_gic0_irq_pr_54*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_55                                           (HV_GIC_BASE_ADDRESS + 0x1C4)

#define CPU_SYS_GIC0_IRQ_PR_55_struct                                    rs_cpu_sys_gic0_irq_pr_55

typedef struct _rs_cpu_sys_gic0_irq_pr_55  rs_cpu_sys_gic0_irq_pr_55;
struct _rs_cpu_sys_gic0_irq_pr_55 {
    unsigned int REG0_IRQ_PR_55                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_55(val) ((rs_cpu_sys_gic0_irq_pr_55*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_56                                           (HV_GIC_BASE_ADDRESS + 0x1C8)

#define CPU_SYS_GIC0_IRQ_PR_56_struct                                    rs_cpu_sys_gic0_irq_pr_56

typedef struct _rs_cpu_sys_gic0_irq_pr_56  rs_cpu_sys_gic0_irq_pr_56;
struct _rs_cpu_sys_gic0_irq_pr_56 {
    unsigned int REG0_IRQ_PR_56                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_56(val) ((rs_cpu_sys_gic0_irq_pr_56*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_57                                           (HV_GIC_BASE_ADDRESS + 0x1CC)

#define CPU_SYS_GIC0_IRQ_PR_57_struct                                    rs_cpu_sys_gic0_irq_pr_57

typedef struct _rs_cpu_sys_gic0_irq_pr_57  rs_cpu_sys_gic0_irq_pr_57;
struct _rs_cpu_sys_gic0_irq_pr_57 {
    unsigned int REG0_IRQ_PR_57                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_57(val) ((rs_cpu_sys_gic0_irq_pr_57*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_58                                           (HV_GIC_BASE_ADDRESS + 0x1D0)

#define CPU_SYS_GIC0_IRQ_PR_58_struct                                    rs_cpu_sys_gic0_irq_pr_58

typedef struct _rs_cpu_sys_gic0_irq_pr_58  rs_cpu_sys_gic0_irq_pr_58;
struct _rs_cpu_sys_gic0_irq_pr_58 {
    unsigned int REG0_IRQ_PR_58                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_58(val) ((rs_cpu_sys_gic0_irq_pr_58*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_59                                           (HV_GIC_BASE_ADDRESS + 0x1D4)

#define CPU_SYS_GIC0_IRQ_PR_59_struct                                    rs_cpu_sys_gic0_irq_pr_59

typedef struct _rs_cpu_sys_gic0_irq_pr_59  rs_cpu_sys_gic0_irq_pr_59;
struct _rs_cpu_sys_gic0_irq_pr_59 {
    unsigned int REG0_IRQ_PR_59                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_59(val) ((rs_cpu_sys_gic0_irq_pr_59*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_60                                           (HV_GIC_BASE_ADDRESS + 0x1D8)

#define CPU_SYS_GIC0_IRQ_PR_60_struct                                    rs_cpu_sys_gic0_irq_pr_60

typedef struct _rs_cpu_sys_gic0_irq_pr_60  rs_cpu_sys_gic0_irq_pr_60;
struct _rs_cpu_sys_gic0_irq_pr_60 {
    unsigned int REG0_IRQ_PR_60                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_60(val) ((rs_cpu_sys_gic0_irq_pr_60*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_61                                           (HV_GIC_BASE_ADDRESS + 0x1DC)

#define CPU_SYS_GIC0_IRQ_PR_61_struct                                    rs_cpu_sys_gic0_irq_pr_61

typedef struct _rs_cpu_sys_gic0_irq_pr_61  rs_cpu_sys_gic0_irq_pr_61;
struct _rs_cpu_sys_gic0_irq_pr_61 {
    unsigned int REG0_IRQ_PR_61                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_61(val) ((rs_cpu_sys_gic0_irq_pr_61*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_62                                           (HV_GIC_BASE_ADDRESS + 0x1E0)

#define CPU_SYS_GIC0_IRQ_PR_62_struct                                    rs_cpu_sys_gic0_irq_pr_62

typedef struct _rs_cpu_sys_gic0_irq_pr_62  rs_cpu_sys_gic0_irq_pr_62;
struct _rs_cpu_sys_gic0_irq_pr_62 {
    unsigned int REG0_IRQ_PR_62                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_62(val) ((rs_cpu_sys_gic0_irq_pr_62*)&(val))



#define CPU_SYS_GIC0_IRQ_PR_63                                           (HV_GIC_BASE_ADDRESS + 0x1E4)

#define CPU_SYS_GIC0_IRQ_PR_63_struct                                    rs_cpu_sys_gic0_irq_pr_63

typedef struct _rs_cpu_sys_gic0_irq_pr_63  rs_cpu_sys_gic0_irq_pr_63;
struct _rs_cpu_sys_gic0_irq_pr_63 {
    unsigned int REG0_IRQ_PR_63                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic0_irq_pr_63(val) ((rs_cpu_sys_gic0_irq_pr_63*)&(val))



#define CPU_SYS_GIC0_IRQ_VECTOR_DEFAULT                                  (HV_GIC_BASE_ADDRESS + 0x1E8)

#define CPU_SYS_GIC0_IRQ_VECTOR_DEFAULT_struct                           rs_cpu_sys_gic0_irq_vector_default

typedef struct _rs_cpu_sys_gic0_irq_vector_default  rs_cpu_sys_gic0_irq_vector_default;
struct _rs_cpu_sys_gic0_irq_vector_default {
    unsigned int REG0_IRQ_VECTOR_DEFAULT                    :32;
};
#define cpu_sys_gic0_irq_vector_default(val) ((rs_cpu_sys_gic0_irq_vector_default*)&(val))



#define CPU_SYS_GIC1_IRQ_INTEN_L                                         (HV_GIC_BASE_ADDRESS + 0x400)

#define CPU_SYS_GIC1_IRQ_INTEN_L_struct                                  rs_cpu_sys_gic1_irq_inten_l

typedef struct _rs_cpu_sys_gic1_irq_inten_l  rs_cpu_sys_gic1_irq_inten_l;
struct _rs_cpu_sys_gic1_irq_inten_l {
    unsigned int REG1_IRQ_INTEN_L                           :32;
};
#define cpu_sys_gic1_irq_inten_l(val) ((rs_cpu_sys_gic1_irq_inten_l*)&(val))



#define CPU_SYS_GIC1_IRQ_INTEN_H                                         (HV_GIC_BASE_ADDRESS + 0x404)

#define CPU_SYS_GIC1_IRQ_INTEN_H_struct                                  rs_cpu_sys_gic1_irq_inten_h

typedef struct _rs_cpu_sys_gic1_irq_inten_h  rs_cpu_sys_gic1_irq_inten_h;
struct _rs_cpu_sys_gic1_irq_inten_h {
    unsigned int REG1_IRQ_INTEN_H                           :32;
};
#define cpu_sys_gic1_irq_inten_h(val) ((rs_cpu_sys_gic1_irq_inten_h*)&(val))



#define CPU_SYS_GIC1_IRQ_INTMASK_L                                       (HV_GIC_BASE_ADDRESS + 0x408)

#define CPU_SYS_GIC1_IRQ_INTMASK_L_struct                                rs_cpu_sys_gic1_irq_intmask_l

typedef struct _rs_cpu_sys_gic1_irq_intmask_l  rs_cpu_sys_gic1_irq_intmask_l;
struct _rs_cpu_sys_gic1_irq_intmask_l {
    unsigned int REG1_IRQ_INTMASK_L                         :32;
};
#define cpu_sys_gic1_irq_intmask_l(val) ((rs_cpu_sys_gic1_irq_intmask_l*)&(val))



#define CPU_SYS_GIC1_IRQ_INTMASK_H                                       (HV_GIC_BASE_ADDRESS + 0x40C)

#define CPU_SYS_GIC1_IRQ_INTMASK_H_struct                                rs_cpu_sys_gic1_irq_intmask_h

typedef struct _rs_cpu_sys_gic1_irq_intmask_h  rs_cpu_sys_gic1_irq_intmask_h;
struct _rs_cpu_sys_gic1_irq_intmask_h {
    unsigned int REG1_IRQ_INTMASK_H                         :32;
};
#define cpu_sys_gic1_irq_intmask_h(val) ((rs_cpu_sys_gic1_irq_intmask_h*)&(val))



#define CPU_SYS_GIC1_IRQ_INTFORCE_L                                      (HV_GIC_BASE_ADDRESS + 0x410)

#define CPU_SYS_GIC1_IRQ_INTFORCE_L_struct                               rs_cpu_sys_gic1_irq_intforce_l

typedef struct _rs_cpu_sys_gic1_irq_intforce_l  rs_cpu_sys_gic1_irq_intforce_l;
struct _rs_cpu_sys_gic1_irq_intforce_l {
    unsigned int REG1_IRQ_INTFORCE_L                        :32;
};
#define cpu_sys_gic1_irq_intforce_l(val) ((rs_cpu_sys_gic1_irq_intforce_l*)&(val))



#define CPU_SYS_GIC1_IRQ_INTFORCE_H                                      (HV_GIC_BASE_ADDRESS + 0x414)

#define CPU_SYS_GIC1_IRQ_INTFORCE_H_struct                               rs_cpu_sys_gic1_irq_intforce_h

typedef struct _rs_cpu_sys_gic1_irq_intforce_h  rs_cpu_sys_gic1_irq_intforce_h;
struct _rs_cpu_sys_gic1_irq_intforce_h {
    unsigned int REG1_IRQ_INTFORCE_H                        :32;
};
#define cpu_sys_gic1_irq_intforce_h(val) ((rs_cpu_sys_gic1_irq_intforce_h*)&(val))



#define CPU_SYS_GIC1_IRQ_RAWSTATUS_L                                     (HV_GIC_BASE_ADDRESS + 0x418)

#define CPU_SYS_GIC1_IRQ_RAWSTATUS_L_struct                              rs_cpu_sys_gic1_irq_rawstatus_l

typedef struct _rs_cpu_sys_gic1_irq_rawstatus_l  rs_cpu_sys_gic1_irq_rawstatus_l;
struct _rs_cpu_sys_gic1_irq_rawstatus_l {
    unsigned int REG1_IRQ_RAWSTATUS_L                       :32;
};
#define cpu_sys_gic1_irq_rawstatus_l(val) ((rs_cpu_sys_gic1_irq_rawstatus_l*)&(val))



#define CPU_SYS_GIC1_IRQ_RAWSTATUS_H                                     (HV_GIC_BASE_ADDRESS + 0x41C)

#define CPU_SYS_GIC1_IRQ_RAWSTATUS_H_struct                              rs_cpu_sys_gic1_irq_rawstatus_h

typedef struct _rs_cpu_sys_gic1_irq_rawstatus_h  rs_cpu_sys_gic1_irq_rawstatus_h;
struct _rs_cpu_sys_gic1_irq_rawstatus_h {
    unsigned int REG1_IRQ_RAWSTATUS_H                       :32;
};
#define cpu_sys_gic1_irq_rawstatus_h(val) ((rs_cpu_sys_gic1_irq_rawstatus_h*)&(val))



#define CPU_SYS_GIC1_IRQ_STATUS_L                                        (HV_GIC_BASE_ADDRESS + 0x420)

#define CPU_SYS_GIC1_IRQ_STATUS_L_struct                                 rs_cpu_sys_gic1_irq_status_l

typedef struct _rs_cpu_sys_gic1_irq_status_l  rs_cpu_sys_gic1_irq_status_l;
struct _rs_cpu_sys_gic1_irq_status_l {
    unsigned int REG1_IRQ_STATUS_L                          :32;
};
#define cpu_sys_gic1_irq_status_l(val) ((rs_cpu_sys_gic1_irq_status_l*)&(val))



#define CPU_SYS_GIC1_IRQ_STATUS_H                                        (HV_GIC_BASE_ADDRESS + 0x424)

#define CPU_SYS_GIC1_IRQ_STATUS_H_struct                                 rs_cpu_sys_gic1_irq_status_h

typedef struct _rs_cpu_sys_gic1_irq_status_h  rs_cpu_sys_gic1_irq_status_h;
struct _rs_cpu_sys_gic1_irq_status_h {
    unsigned int REG1_IRQ_STATUS_H                          :32;
};
#define cpu_sys_gic1_irq_status_h(val) ((rs_cpu_sys_gic1_irq_status_h*)&(val))



#define CPU_SYS_GIC1_IRQ_MASKSTATUS_L                                    (HV_GIC_BASE_ADDRESS + 0x428)

#define CPU_SYS_GIC1_IRQ_MASKSTATUS_L_struct                             rs_cpu_sys_gic1_irq_maskstatus_l

typedef struct _rs_cpu_sys_gic1_irq_maskstatus_l  rs_cpu_sys_gic1_irq_maskstatus_l;
struct _rs_cpu_sys_gic1_irq_maskstatus_l {
    unsigned int REG1_IRQ_MASKSTATUS_L                      :32;
};
#define cpu_sys_gic1_irq_maskstatus_l(val) ((rs_cpu_sys_gic1_irq_maskstatus_l*)&(val))



#define CPU_SYS_GIC1_IRQ_MASKSTATUS_H                                    (HV_GIC_BASE_ADDRESS + 0x42C)

#define CPU_SYS_GIC1_IRQ_MASKSTATUS_H_struct                             rs_cpu_sys_gic1_irq_maskstatus_h

typedef struct _rs_cpu_sys_gic1_irq_maskstatus_h  rs_cpu_sys_gic1_irq_maskstatus_h;
struct _rs_cpu_sys_gic1_irq_maskstatus_h {
    unsigned int REG1_IRQ_MASKSTATUS_H                      :32;
};
#define cpu_sys_gic1_irq_maskstatus_h(val) ((rs_cpu_sys_gic1_irq_maskstatus_h*)&(val))



#define CPU_SYS_GIC1_IRQ_FINALSTATUS_L                                   (HV_GIC_BASE_ADDRESS + 0x430)

#define CPU_SYS_GIC1_IRQ_FINALSTATUS_L_struct                            rs_cpu_sys_gic1_irq_finalstatus_l

typedef struct _rs_cpu_sys_gic1_irq_finalstatus_l  rs_cpu_sys_gic1_irq_finalstatus_l;
struct _rs_cpu_sys_gic1_irq_finalstatus_l {
    unsigned int REG1_IRQ_FINALSTATUS_L                     :32;
};
#define cpu_sys_gic1_irq_finalstatus_l(val) ((rs_cpu_sys_gic1_irq_finalstatus_l*)&(val))



#define CPU_SYS_GIC1_IRQ_FINALSTATUS_H                                   (HV_GIC_BASE_ADDRESS + 0x434)

#define CPU_SYS_GIC1_IRQ_FINALSTATUS_H_struct                            rs_cpu_sys_gic1_irq_finalstatus_h

typedef struct _rs_cpu_sys_gic1_irq_finalstatus_h  rs_cpu_sys_gic1_irq_finalstatus_h;
struct _rs_cpu_sys_gic1_irq_finalstatus_h {
    unsigned int REG1_IRQ_FINALSTATUS_H                     :32;
};
#define cpu_sys_gic1_irq_finalstatus_h(val) ((rs_cpu_sys_gic1_irq_finalstatus_h*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR                                          (HV_GIC_BASE_ADDRESS + 0x438)

#define CPU_SYS_GIC1_IRQ_VECTOR_struct                                   rs_cpu_sys_gic1_irq_vector

typedef struct _rs_cpu_sys_gic1_irq_vector  rs_cpu_sys_gic1_irq_vector;
struct _rs_cpu_sys_gic1_irq_vector {
    unsigned int REG1_IRQ_VECTOR                            :32;
};
#define cpu_sys_gic1_irq_vector(val) ((rs_cpu_sys_gic1_irq_vector*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_0                                        (HV_GIC_BASE_ADDRESS + 0x440)

#define CPU_SYS_GIC1_IRQ_VECTOR_0_struct                                 rs_cpu_sys_gic1_irq_vector_0

typedef struct _rs_cpu_sys_gic1_irq_vector_0  rs_cpu_sys_gic1_irq_vector_0;
struct _rs_cpu_sys_gic1_irq_vector_0 {
    unsigned int REG1_IRQ_VECTOR_0                          :32;
};
#define cpu_sys_gic1_irq_vector_0(val) ((rs_cpu_sys_gic1_irq_vector_0*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_1                                        (HV_GIC_BASE_ADDRESS + 0x448)

#define CPU_SYS_GIC1_IRQ_VECTOR_1_struct                                 rs_cpu_sys_gic1_irq_vector_1

typedef struct _rs_cpu_sys_gic1_irq_vector_1  rs_cpu_sys_gic1_irq_vector_1;
struct _rs_cpu_sys_gic1_irq_vector_1 {
    unsigned int REG1_IRQ_VECTOR_1                          :32;
};
#define cpu_sys_gic1_irq_vector_1(val) ((rs_cpu_sys_gic1_irq_vector_1*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_2                                        (HV_GIC_BASE_ADDRESS + 0x450)

#define CPU_SYS_GIC1_IRQ_VECTOR_2_struct                                 rs_cpu_sys_gic1_irq_vector_2

typedef struct _rs_cpu_sys_gic1_irq_vector_2  rs_cpu_sys_gic1_irq_vector_2;
struct _rs_cpu_sys_gic1_irq_vector_2 {
    unsigned int REG1_IRQ_VECTOR_2                          :32;
};
#define cpu_sys_gic1_irq_vector_2(val) ((rs_cpu_sys_gic1_irq_vector_2*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_3                                        (HV_GIC_BASE_ADDRESS + 0x458)

#define CPU_SYS_GIC1_IRQ_VECTOR_3_struct                                 rs_cpu_sys_gic1_irq_vector_3

typedef struct _rs_cpu_sys_gic1_irq_vector_3  rs_cpu_sys_gic1_irq_vector_3;
struct _rs_cpu_sys_gic1_irq_vector_3 {
    unsigned int REG1_IRQ_VECTOR_3                          :32;
};
#define cpu_sys_gic1_irq_vector_3(val) ((rs_cpu_sys_gic1_irq_vector_3*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_4                                        (HV_GIC_BASE_ADDRESS + 0x460)

#define CPU_SYS_GIC1_IRQ_VECTOR_4_struct                                 rs_cpu_sys_gic1_irq_vector_4

typedef struct _rs_cpu_sys_gic1_irq_vector_4  rs_cpu_sys_gic1_irq_vector_4;
struct _rs_cpu_sys_gic1_irq_vector_4 {
    unsigned int REG1_IRQ_VECTOR_4                          :32;
};
#define cpu_sys_gic1_irq_vector_4(val) ((rs_cpu_sys_gic1_irq_vector_4*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_5                                        (HV_GIC_BASE_ADDRESS + 0x468)

#define CPU_SYS_GIC1_IRQ_VECTOR_5_struct                                 rs_cpu_sys_gic1_irq_vector_5

typedef struct _rs_cpu_sys_gic1_irq_vector_5  rs_cpu_sys_gic1_irq_vector_5;
struct _rs_cpu_sys_gic1_irq_vector_5 {
    unsigned int REG1_IRQ_VECTOR_5                          :32;
};
#define cpu_sys_gic1_irq_vector_5(val) ((rs_cpu_sys_gic1_irq_vector_5*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_6                                        (HV_GIC_BASE_ADDRESS + 0x470)

#define CPU_SYS_GIC1_IRQ_VECTOR_6_struct                                 rs_cpu_sys_gic1_irq_vector_6

typedef struct _rs_cpu_sys_gic1_irq_vector_6  rs_cpu_sys_gic1_irq_vector_6;
struct _rs_cpu_sys_gic1_irq_vector_6 {
    unsigned int REG1_IRQ_VECTOR_6                          :32;
};
#define cpu_sys_gic1_irq_vector_6(val) ((rs_cpu_sys_gic1_irq_vector_6*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_7                                        (HV_GIC_BASE_ADDRESS + 0x478)

#define CPU_SYS_GIC1_IRQ_VECTOR_7_struct                                 rs_cpu_sys_gic1_irq_vector_7

typedef struct _rs_cpu_sys_gic1_irq_vector_7  rs_cpu_sys_gic1_irq_vector_7;
struct _rs_cpu_sys_gic1_irq_vector_7 {
    unsigned int REG1_IRQ_VECTOR_7                          :32;
};
#define cpu_sys_gic1_irq_vector_7(val) ((rs_cpu_sys_gic1_irq_vector_7*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_8                                        (HV_GIC_BASE_ADDRESS + 0x480)

#define CPU_SYS_GIC1_IRQ_VECTOR_8_struct                                 rs_cpu_sys_gic1_irq_vector_8

typedef struct _rs_cpu_sys_gic1_irq_vector_8  rs_cpu_sys_gic1_irq_vector_8;
struct _rs_cpu_sys_gic1_irq_vector_8 {
    unsigned int REG1_IRQ_VECTOR_8                          :32;
};
#define cpu_sys_gic1_irq_vector_8(val) ((rs_cpu_sys_gic1_irq_vector_8*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_9                                        (HV_GIC_BASE_ADDRESS + 0x488)

#define CPU_SYS_GIC1_IRQ_VECTOR_9_struct                                 rs_cpu_sys_gic1_irq_vector_9

typedef struct _rs_cpu_sys_gic1_irq_vector_9  rs_cpu_sys_gic1_irq_vector_9;
struct _rs_cpu_sys_gic1_irq_vector_9 {
    unsigned int REG1_IRQ_VECTOR_9                          :32;
};
#define cpu_sys_gic1_irq_vector_9(val) ((rs_cpu_sys_gic1_irq_vector_9*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_10                                       (HV_GIC_BASE_ADDRESS + 0x490)

#define CPU_SYS_GIC1_IRQ_VECTOR_10_struct                                rs_cpu_sys_gic1_irq_vector_10

typedef struct _rs_cpu_sys_gic1_irq_vector_10  rs_cpu_sys_gic1_irq_vector_10;
struct _rs_cpu_sys_gic1_irq_vector_10 {
    unsigned int REG1_IRQ_VECTOR_10                         :32;
};
#define cpu_sys_gic1_irq_vector_10(val) ((rs_cpu_sys_gic1_irq_vector_10*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_11                                       (HV_GIC_BASE_ADDRESS + 0x498)

#define CPU_SYS_GIC1_IRQ_VECTOR_11_struct                                rs_cpu_sys_gic1_irq_vector_11

typedef struct _rs_cpu_sys_gic1_irq_vector_11  rs_cpu_sys_gic1_irq_vector_11;
struct _rs_cpu_sys_gic1_irq_vector_11 {
    unsigned int REG1_IRQ_VECTOR_11                         :32;
};
#define cpu_sys_gic1_irq_vector_11(val) ((rs_cpu_sys_gic1_irq_vector_11*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_12                                       (HV_GIC_BASE_ADDRESS + 0x4A0)

#define CPU_SYS_GIC1_IRQ_VECTOR_12_struct                                rs_cpu_sys_gic1_irq_vector_12

typedef struct _rs_cpu_sys_gic1_irq_vector_12  rs_cpu_sys_gic1_irq_vector_12;
struct _rs_cpu_sys_gic1_irq_vector_12 {
    unsigned int REG1_IRQ_VECTOR_12                         :32;
};
#define cpu_sys_gic1_irq_vector_12(val) ((rs_cpu_sys_gic1_irq_vector_12*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_13                                       (HV_GIC_BASE_ADDRESS + 0x4A8)

#define CPU_SYS_GIC1_IRQ_VECTOR_13_struct                                rs_cpu_sys_gic1_irq_vector_13

typedef struct _rs_cpu_sys_gic1_irq_vector_13  rs_cpu_sys_gic1_irq_vector_13;
struct _rs_cpu_sys_gic1_irq_vector_13 {
    unsigned int REG1_IRQ_VECTOR_13                         :32;
};
#define cpu_sys_gic1_irq_vector_13(val) ((rs_cpu_sys_gic1_irq_vector_13*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_14                                       (HV_GIC_BASE_ADDRESS + 0x4B0)

#define CPU_SYS_GIC1_IRQ_VECTOR_14_struct                                rs_cpu_sys_gic1_irq_vector_14

typedef struct _rs_cpu_sys_gic1_irq_vector_14  rs_cpu_sys_gic1_irq_vector_14;
struct _rs_cpu_sys_gic1_irq_vector_14 {
    unsigned int REG1_IRQ_VECTOR_14                         :32;
};
#define cpu_sys_gic1_irq_vector_14(val) ((rs_cpu_sys_gic1_irq_vector_14*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_15                                       (HV_GIC_BASE_ADDRESS + 0x4B8)

#define CPU_SYS_GIC1_IRQ_VECTOR_15_struct                                rs_cpu_sys_gic1_irq_vector_15

typedef struct _rs_cpu_sys_gic1_irq_vector_15  rs_cpu_sys_gic1_irq_vector_15;
struct _rs_cpu_sys_gic1_irq_vector_15 {
    unsigned int REG1_IRQ_VECTOR_15                         :32;
};
#define cpu_sys_gic1_irq_vector_15(val) ((rs_cpu_sys_gic1_irq_vector_15*)&(val))



#define CPU_SYS_GIC1_FIQ_INTEN                                           (HV_GIC_BASE_ADDRESS + 0x4C0)

#define CPU_SYS_GIC1_FIQ_INTEN_struct                                    rs_cpu_sys_gic1_fiq_inten

typedef struct _rs_cpu_sys_gic1_fiq_inten  rs_cpu_sys_gic1_fiq_inten;
struct _rs_cpu_sys_gic1_fiq_inten {
    unsigned int REG1_FIQ_INTEN                             : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic1_fiq_inten(val) ((rs_cpu_sys_gic1_fiq_inten*)&(val))



#define CPU_SYS_GIC1_FIQ_INTMASK                                         (HV_GIC_BASE_ADDRESS + 0x4C4)

#define CPU_SYS_GIC1_FIQ_INTMASK_struct                                  rs_cpu_sys_gic1_fiq_intmask

typedef struct _rs_cpu_sys_gic1_fiq_intmask  rs_cpu_sys_gic1_fiq_intmask;
struct _rs_cpu_sys_gic1_fiq_intmask {
    unsigned int REG1_FIQ_INTMASK                           : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic1_fiq_intmask(val) ((rs_cpu_sys_gic1_fiq_intmask*)&(val))



#define CPU_SYS_GIC1_FIQ_INTFORCE                                        (HV_GIC_BASE_ADDRESS + 0x4C8)

#define CPU_SYS_GIC1_FIQ_INTFORCE_struct                                 rs_cpu_sys_gic1_fiq_intforce

typedef struct _rs_cpu_sys_gic1_fiq_intforce  rs_cpu_sys_gic1_fiq_intforce;
struct _rs_cpu_sys_gic1_fiq_intforce {
    unsigned int REG1_FIQ_INTFORCE                          : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic1_fiq_intforce(val) ((rs_cpu_sys_gic1_fiq_intforce*)&(val))



#define CPU_SYS_GIC1_FIQ_RAWSTATUS                                       (HV_GIC_BASE_ADDRESS + 0x4CC)

#define CPU_SYS_GIC1_FIQ_RAWSTATUS_struct                                rs_cpu_sys_gic1_fiq_rawstatus

typedef struct _rs_cpu_sys_gic1_fiq_rawstatus  rs_cpu_sys_gic1_fiq_rawstatus;
struct _rs_cpu_sys_gic1_fiq_rawstatus {
    unsigned int REG1_FIQ_RAWSTATUS                         : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic1_fiq_rawstatus(val) ((rs_cpu_sys_gic1_fiq_rawstatus*)&(val))



#define CPU_SYS_GIC1_FIQ_STATUS                                          (HV_GIC_BASE_ADDRESS + 0x4D0)

#define CPU_SYS_GIC1_FIQ_STATUS_struct                                   rs_cpu_sys_gic1_fiq_status

typedef struct _rs_cpu_sys_gic1_fiq_status  rs_cpu_sys_gic1_fiq_status;
struct _rs_cpu_sys_gic1_fiq_status {
    unsigned int REG1_FIQ_STATUS                            : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic1_fiq_status(val) ((rs_cpu_sys_gic1_fiq_status*)&(val))



#define CPU_SYS_GIC1_FIQ_FINALSTATUS                                     (HV_GIC_BASE_ADDRESS + 0x4D4)

#define CPU_SYS_GIC1_FIQ_FINALSTATUS_struct                              rs_cpu_sys_gic1_fiq_finalstatus

typedef struct _rs_cpu_sys_gic1_fiq_finalstatus  rs_cpu_sys_gic1_fiq_finalstatus;
struct _rs_cpu_sys_gic1_fiq_finalstatus {
    unsigned int REG1_FIQ_FINALSTATUS                       : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_gic1_fiq_finalstatus(val) ((rs_cpu_sys_gic1_fiq_finalstatus*)&(val))



#define CPU_SYS_GIC1_IRQ_PLEVEL                                          (HV_GIC_BASE_ADDRESS + 0x4D8)

#define CPU_SYS_GIC1_IRQ_PLEVEL_struct                                   rs_cpu_sys_gic1_irq_plevel

typedef struct _rs_cpu_sys_gic1_irq_plevel  rs_cpu_sys_gic1_irq_plevel;
struct _rs_cpu_sys_gic1_irq_plevel {
    unsigned int REG1_IRQ_PLEVEL                            : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_plevel(val) ((rs_cpu_sys_gic1_irq_plevel*)&(val))



#define CPU_SYS_GIC1_IRQ_INTERNAL_PLEVEL                                 (HV_GIC_BASE_ADDRESS + 0x4DC)

#define CPU_SYS_GIC1_IRQ_INTERNAL_PLEVEL_struct                          rs_cpu_sys_gic1_irq_internal_plevel

typedef struct _rs_cpu_sys_gic1_irq_internal_plevel  rs_cpu_sys_gic1_irq_internal_plevel;
struct _rs_cpu_sys_gic1_irq_internal_plevel {
    unsigned int REG1_IRQ_INTERNAL_PLEVEL                   : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_gic1_irq_internal_plevel(val) ((rs_cpu_sys_gic1_irq_internal_plevel*)&(val))



#define CPU_SYS_GIC1_ICTL_VERSION_ID                                     (HV_GIC_BASE_ADDRESS + 0x4E0)

#define CPU_SYS_GIC1_ICTL_VERSION_ID_struct                              rs_cpu_sys_gic1_ictl_version_id

typedef struct _rs_cpu_sys_gic1_ictl_version_id  rs_cpu_sys_gic1_ictl_version_id;
struct _rs_cpu_sys_gic1_ictl_version_id {
    unsigned int REG1_ICTL_VERSION_ID                       :32;
};
#define cpu_sys_gic1_ictl_version_id(val) ((rs_cpu_sys_gic1_ictl_version_id*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_0                                            (HV_GIC_BASE_ADDRESS + 0x4E8)

#define CPU_SYS_GIC1_IRQ_PR_0_struct                                     rs_cpu_sys_gic1_irq_pr_0

typedef struct _rs_cpu_sys_gic1_irq_pr_0  rs_cpu_sys_gic1_irq_pr_0;
struct _rs_cpu_sys_gic1_irq_pr_0 {
    unsigned int REG1_IRQ_PR_0                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_0(val) ((rs_cpu_sys_gic1_irq_pr_0*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_1                                            (HV_GIC_BASE_ADDRESS + 0x4EC)

#define CPU_SYS_GIC1_IRQ_PR_1_struct                                     rs_cpu_sys_gic1_irq_pr_1

typedef struct _rs_cpu_sys_gic1_irq_pr_1  rs_cpu_sys_gic1_irq_pr_1;
struct _rs_cpu_sys_gic1_irq_pr_1 {
    unsigned int REG1_IRQ_PR_1                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_1(val) ((rs_cpu_sys_gic1_irq_pr_1*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_2                                            (HV_GIC_BASE_ADDRESS + 0x4F0)

#define CPU_SYS_GIC1_IRQ_PR_2_struct                                     rs_cpu_sys_gic1_irq_pr_2

typedef struct _rs_cpu_sys_gic1_irq_pr_2  rs_cpu_sys_gic1_irq_pr_2;
struct _rs_cpu_sys_gic1_irq_pr_2 {
    unsigned int REG1_IRQ_PR_2                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_2(val) ((rs_cpu_sys_gic1_irq_pr_2*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_3                                            (HV_GIC_BASE_ADDRESS + 0x4F4)

#define CPU_SYS_GIC1_IRQ_PR_3_struct                                     rs_cpu_sys_gic1_irq_pr_3

typedef struct _rs_cpu_sys_gic1_irq_pr_3  rs_cpu_sys_gic1_irq_pr_3;
struct _rs_cpu_sys_gic1_irq_pr_3 {
    unsigned int REG1_IRQ_PR_3                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_3(val) ((rs_cpu_sys_gic1_irq_pr_3*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_4                                            (HV_GIC_BASE_ADDRESS + 0x4F8)

#define CPU_SYS_GIC1_IRQ_PR_4_struct                                     rs_cpu_sys_gic1_irq_pr_4

typedef struct _rs_cpu_sys_gic1_irq_pr_4  rs_cpu_sys_gic1_irq_pr_4;
struct _rs_cpu_sys_gic1_irq_pr_4 {
    unsigned int REG1_IRQ_PR_4                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_4(val) ((rs_cpu_sys_gic1_irq_pr_4*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_5                                            (HV_GIC_BASE_ADDRESS + 0x4FC)

#define CPU_SYS_GIC1_IRQ_PR_5_struct                                     rs_cpu_sys_gic1_irq_pr_5

typedef struct _rs_cpu_sys_gic1_irq_pr_5  rs_cpu_sys_gic1_irq_pr_5;
struct _rs_cpu_sys_gic1_irq_pr_5 {
    unsigned int REG1_IRQ_PR_5                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_5(val) ((rs_cpu_sys_gic1_irq_pr_5*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_6                                            (HV_GIC_BASE_ADDRESS + 0x500)

#define CPU_SYS_GIC1_IRQ_PR_6_struct                                     rs_cpu_sys_gic1_irq_pr_6

typedef struct _rs_cpu_sys_gic1_irq_pr_6  rs_cpu_sys_gic1_irq_pr_6;
struct _rs_cpu_sys_gic1_irq_pr_6 {
    unsigned int REG1_IRQ_PR_6                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_6(val) ((rs_cpu_sys_gic1_irq_pr_6*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_7                                            (HV_GIC_BASE_ADDRESS + 0x504)

#define CPU_SYS_GIC1_IRQ_PR_7_struct                                     rs_cpu_sys_gic1_irq_pr_7

typedef struct _rs_cpu_sys_gic1_irq_pr_7  rs_cpu_sys_gic1_irq_pr_7;
struct _rs_cpu_sys_gic1_irq_pr_7 {
    unsigned int REG1_IRQ_PR_7                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_7(val) ((rs_cpu_sys_gic1_irq_pr_7*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_8                                            (HV_GIC_BASE_ADDRESS + 0x508)

#define CPU_SYS_GIC1_IRQ_PR_8_struct                                     rs_cpu_sys_gic1_irq_pr_8

typedef struct _rs_cpu_sys_gic1_irq_pr_8  rs_cpu_sys_gic1_irq_pr_8;
struct _rs_cpu_sys_gic1_irq_pr_8 {
    unsigned int REG1_IRQ_PR_8                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_8(val) ((rs_cpu_sys_gic1_irq_pr_8*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_9                                            (HV_GIC_BASE_ADDRESS + 0x50C)

#define CPU_SYS_GIC1_IRQ_PR_9_struct                                     rs_cpu_sys_gic1_irq_pr_9

typedef struct _rs_cpu_sys_gic1_irq_pr_9  rs_cpu_sys_gic1_irq_pr_9;
struct _rs_cpu_sys_gic1_irq_pr_9 {
    unsigned int REG1_IRQ_PR_9                              : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_9(val) ((rs_cpu_sys_gic1_irq_pr_9*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_10                                           (HV_GIC_BASE_ADDRESS + 0x510)

#define CPU_SYS_GIC1_IRQ_PR_10_struct                                    rs_cpu_sys_gic1_irq_pr_10

typedef struct _rs_cpu_sys_gic1_irq_pr_10  rs_cpu_sys_gic1_irq_pr_10;
struct _rs_cpu_sys_gic1_irq_pr_10 {
    unsigned int REG1_IRQ_PR_10                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_10(val) ((rs_cpu_sys_gic1_irq_pr_10*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_11                                           (HV_GIC_BASE_ADDRESS + 0x514)

#define CPU_SYS_GIC1_IRQ_PR_11_struct                                    rs_cpu_sys_gic1_irq_pr_11

typedef struct _rs_cpu_sys_gic1_irq_pr_11  rs_cpu_sys_gic1_irq_pr_11;
struct _rs_cpu_sys_gic1_irq_pr_11 {
    unsigned int REG1_IRQ_PR_11                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_11(val) ((rs_cpu_sys_gic1_irq_pr_11*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_12                                           (HV_GIC_BASE_ADDRESS + 0x518)

#define CPU_SYS_GIC1_IRQ_PR_12_struct                                    rs_cpu_sys_gic1_irq_pr_12

typedef struct _rs_cpu_sys_gic1_irq_pr_12  rs_cpu_sys_gic1_irq_pr_12;
struct _rs_cpu_sys_gic1_irq_pr_12 {
    unsigned int REG1_IRQ_PR_12                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_12(val) ((rs_cpu_sys_gic1_irq_pr_12*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_13                                           (HV_GIC_BASE_ADDRESS + 0x51C)

#define CPU_SYS_GIC1_IRQ_PR_13_struct                                    rs_cpu_sys_gic1_irq_pr_13

typedef struct _rs_cpu_sys_gic1_irq_pr_13  rs_cpu_sys_gic1_irq_pr_13;
struct _rs_cpu_sys_gic1_irq_pr_13 {
    unsigned int REG1_IRQ_PR_13                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_13(val) ((rs_cpu_sys_gic1_irq_pr_13*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_14                                           (HV_GIC_BASE_ADDRESS + 0x520)

#define CPU_SYS_GIC1_IRQ_PR_14_struct                                    rs_cpu_sys_gic1_irq_pr_14

typedef struct _rs_cpu_sys_gic1_irq_pr_14  rs_cpu_sys_gic1_irq_pr_14;
struct _rs_cpu_sys_gic1_irq_pr_14 {
    unsigned int REG1_IRQ_PR_14                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_14(val) ((rs_cpu_sys_gic1_irq_pr_14*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_15                                           (HV_GIC_BASE_ADDRESS + 0x524)

#define CPU_SYS_GIC1_IRQ_PR_15_struct                                    rs_cpu_sys_gic1_irq_pr_15

typedef struct _rs_cpu_sys_gic1_irq_pr_15  rs_cpu_sys_gic1_irq_pr_15;
struct _rs_cpu_sys_gic1_irq_pr_15 {
    unsigned int REG1_IRQ_PR_15                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_15(val) ((rs_cpu_sys_gic1_irq_pr_15*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_16                                           (HV_GIC_BASE_ADDRESS + 0x528)

#define CPU_SYS_GIC1_IRQ_PR_16_struct                                    rs_cpu_sys_gic1_irq_pr_16

typedef struct _rs_cpu_sys_gic1_irq_pr_16  rs_cpu_sys_gic1_irq_pr_16;
struct _rs_cpu_sys_gic1_irq_pr_16 {
    unsigned int REG1_IRQ_PR_16                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_16(val) ((rs_cpu_sys_gic1_irq_pr_16*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_17                                           (HV_GIC_BASE_ADDRESS + 0x52C)

#define CPU_SYS_GIC1_IRQ_PR_17_struct                                    rs_cpu_sys_gic1_irq_pr_17

typedef struct _rs_cpu_sys_gic1_irq_pr_17  rs_cpu_sys_gic1_irq_pr_17;
struct _rs_cpu_sys_gic1_irq_pr_17 {
    unsigned int REG1_IRQ_PR_17                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_17(val) ((rs_cpu_sys_gic1_irq_pr_17*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_18                                           (HV_GIC_BASE_ADDRESS + 0x530)

#define CPU_SYS_GIC1_IRQ_PR_18_struct                                    rs_cpu_sys_gic1_irq_pr_18

typedef struct _rs_cpu_sys_gic1_irq_pr_18  rs_cpu_sys_gic1_irq_pr_18;
struct _rs_cpu_sys_gic1_irq_pr_18 {
    unsigned int REG1_IRQ_PR_18                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_18(val) ((rs_cpu_sys_gic1_irq_pr_18*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_19                                           (HV_GIC_BASE_ADDRESS + 0x534)

#define CPU_SYS_GIC1_IRQ_PR_19_struct                                    rs_cpu_sys_gic1_irq_pr_19

typedef struct _rs_cpu_sys_gic1_irq_pr_19  rs_cpu_sys_gic1_irq_pr_19;
struct _rs_cpu_sys_gic1_irq_pr_19 {
    unsigned int REG1_IRQ_PR_19                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_19(val) ((rs_cpu_sys_gic1_irq_pr_19*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_20                                           (HV_GIC_BASE_ADDRESS + 0x538)

#define CPU_SYS_GIC1_IRQ_PR_20_struct                                    rs_cpu_sys_gic1_irq_pr_20

typedef struct _rs_cpu_sys_gic1_irq_pr_20  rs_cpu_sys_gic1_irq_pr_20;
struct _rs_cpu_sys_gic1_irq_pr_20 {
    unsigned int REG1_IRQ_PR_20                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_20(val) ((rs_cpu_sys_gic1_irq_pr_20*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_21                                           (HV_GIC_BASE_ADDRESS + 0x53C)

#define CPU_SYS_GIC1_IRQ_PR_21_struct                                    rs_cpu_sys_gic1_irq_pr_21

typedef struct _rs_cpu_sys_gic1_irq_pr_21  rs_cpu_sys_gic1_irq_pr_21;
struct _rs_cpu_sys_gic1_irq_pr_21 {
    unsigned int REG1_IRQ_PR_21                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_21(val) ((rs_cpu_sys_gic1_irq_pr_21*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_22                                           (HV_GIC_BASE_ADDRESS + 0x540)

#define CPU_SYS_GIC1_IRQ_PR_22_struct                                    rs_cpu_sys_gic1_irq_pr_22

typedef struct _rs_cpu_sys_gic1_irq_pr_22  rs_cpu_sys_gic1_irq_pr_22;
struct _rs_cpu_sys_gic1_irq_pr_22 {
    unsigned int REG1_IRQ_PR_22                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_22(val) ((rs_cpu_sys_gic1_irq_pr_22*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_23                                           (HV_GIC_BASE_ADDRESS + 0x544)

#define CPU_SYS_GIC1_IRQ_PR_23_struct                                    rs_cpu_sys_gic1_irq_pr_23

typedef struct _rs_cpu_sys_gic1_irq_pr_23  rs_cpu_sys_gic1_irq_pr_23;
struct _rs_cpu_sys_gic1_irq_pr_23 {
    unsigned int REG1_IRQ_PR_23                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_23(val) ((rs_cpu_sys_gic1_irq_pr_23*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_24                                           (HV_GIC_BASE_ADDRESS + 0x548)

#define CPU_SYS_GIC1_IRQ_PR_24_struct                                    rs_cpu_sys_gic1_irq_pr_24

typedef struct _rs_cpu_sys_gic1_irq_pr_24  rs_cpu_sys_gic1_irq_pr_24;
struct _rs_cpu_sys_gic1_irq_pr_24 {
    unsigned int REG1_IRQ_PR_24                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_24(val) ((rs_cpu_sys_gic1_irq_pr_24*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_25                                           (HV_GIC_BASE_ADDRESS + 0x54C)

#define CPU_SYS_GIC1_IRQ_PR_25_struct                                    rs_cpu_sys_gic1_irq_pr_25

typedef struct _rs_cpu_sys_gic1_irq_pr_25  rs_cpu_sys_gic1_irq_pr_25;
struct _rs_cpu_sys_gic1_irq_pr_25 {
    unsigned int REG1_IRQ_PR_25                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_25(val) ((rs_cpu_sys_gic1_irq_pr_25*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_26                                           (HV_GIC_BASE_ADDRESS + 0x550)

#define CPU_SYS_GIC1_IRQ_PR_26_struct                                    rs_cpu_sys_gic1_irq_pr_26

typedef struct _rs_cpu_sys_gic1_irq_pr_26  rs_cpu_sys_gic1_irq_pr_26;
struct _rs_cpu_sys_gic1_irq_pr_26 {
    unsigned int REG1_IRQ_PR_26                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_26(val) ((rs_cpu_sys_gic1_irq_pr_26*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_27                                           (HV_GIC_BASE_ADDRESS + 0x554)

#define CPU_SYS_GIC1_IRQ_PR_27_struct                                    rs_cpu_sys_gic1_irq_pr_27

typedef struct _rs_cpu_sys_gic1_irq_pr_27  rs_cpu_sys_gic1_irq_pr_27;
struct _rs_cpu_sys_gic1_irq_pr_27 {
    unsigned int REG1_IRQ_PR_27                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_27(val) ((rs_cpu_sys_gic1_irq_pr_27*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_28                                           (HV_GIC_BASE_ADDRESS + 0x558)

#define CPU_SYS_GIC1_IRQ_PR_28_struct                                    rs_cpu_sys_gic1_irq_pr_28

typedef struct _rs_cpu_sys_gic1_irq_pr_28  rs_cpu_sys_gic1_irq_pr_28;
struct _rs_cpu_sys_gic1_irq_pr_28 {
    unsigned int REG1_IRQ_PR_28                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_28(val) ((rs_cpu_sys_gic1_irq_pr_28*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_29                                           (HV_GIC_BASE_ADDRESS + 0x55C)

#define CPU_SYS_GIC1_IRQ_PR_29_struct                                    rs_cpu_sys_gic1_irq_pr_29

typedef struct _rs_cpu_sys_gic1_irq_pr_29  rs_cpu_sys_gic1_irq_pr_29;
struct _rs_cpu_sys_gic1_irq_pr_29 {
    unsigned int REG1_IRQ_PR_29                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_29(val) ((rs_cpu_sys_gic1_irq_pr_29*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_30                                           (HV_GIC_BASE_ADDRESS + 0x560)

#define CPU_SYS_GIC1_IRQ_PR_30_struct                                    rs_cpu_sys_gic1_irq_pr_30

typedef struct _rs_cpu_sys_gic1_irq_pr_30  rs_cpu_sys_gic1_irq_pr_30;
struct _rs_cpu_sys_gic1_irq_pr_30 {
    unsigned int REG1_IRQ_PR_30                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_30(val) ((rs_cpu_sys_gic1_irq_pr_30*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_31                                           (HV_GIC_BASE_ADDRESS + 0x564)

#define CPU_SYS_GIC1_IRQ_PR_31_struct                                    rs_cpu_sys_gic1_irq_pr_31

typedef struct _rs_cpu_sys_gic1_irq_pr_31  rs_cpu_sys_gic1_irq_pr_31;
struct _rs_cpu_sys_gic1_irq_pr_31 {
    unsigned int REG1_IRQ_PR_31                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_31(val) ((rs_cpu_sys_gic1_irq_pr_31*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_32                                           (HV_GIC_BASE_ADDRESS + 0x568)

#define CPU_SYS_GIC1_IRQ_PR_32_struct                                    rs_cpu_sys_gic1_irq_pr_32

typedef struct _rs_cpu_sys_gic1_irq_pr_32  rs_cpu_sys_gic1_irq_pr_32;
struct _rs_cpu_sys_gic1_irq_pr_32 {
    unsigned int REG1_IRQ_PR_32                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_32(val) ((rs_cpu_sys_gic1_irq_pr_32*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_33                                           (HV_GIC_BASE_ADDRESS + 0x56C)

#define CPU_SYS_GIC1_IRQ_PR_33_struct                                    rs_cpu_sys_gic1_irq_pr_33

typedef struct _rs_cpu_sys_gic1_irq_pr_33  rs_cpu_sys_gic1_irq_pr_33;
struct _rs_cpu_sys_gic1_irq_pr_33 {
    unsigned int REG1_IRQ_PR_33                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_33(val) ((rs_cpu_sys_gic1_irq_pr_33*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_34                                           (HV_GIC_BASE_ADDRESS + 0x570)

#define CPU_SYS_GIC1_IRQ_PR_34_struct                                    rs_cpu_sys_gic1_irq_pr_34

typedef struct _rs_cpu_sys_gic1_irq_pr_34  rs_cpu_sys_gic1_irq_pr_34;
struct _rs_cpu_sys_gic1_irq_pr_34 {
    unsigned int REG1_IRQ_PR_34                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_34(val) ((rs_cpu_sys_gic1_irq_pr_34*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_35                                           (HV_GIC_BASE_ADDRESS + 0x574)

#define CPU_SYS_GIC1_IRQ_PR_35_struct                                    rs_cpu_sys_gic1_irq_pr_35

typedef struct _rs_cpu_sys_gic1_irq_pr_35  rs_cpu_sys_gic1_irq_pr_35;
struct _rs_cpu_sys_gic1_irq_pr_35 {
    unsigned int REG1_IRQ_PR_35                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_35(val) ((rs_cpu_sys_gic1_irq_pr_35*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_36                                           (HV_GIC_BASE_ADDRESS + 0x578)

#define CPU_SYS_GIC1_IRQ_PR_36_struct                                    rs_cpu_sys_gic1_irq_pr_36

typedef struct _rs_cpu_sys_gic1_irq_pr_36  rs_cpu_sys_gic1_irq_pr_36;
struct _rs_cpu_sys_gic1_irq_pr_36 {
    unsigned int REG1_IRQ_PR_36                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_36(val) ((rs_cpu_sys_gic1_irq_pr_36*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_37                                           (HV_GIC_BASE_ADDRESS + 0x57C)

#define CPU_SYS_GIC1_IRQ_PR_37_struct                                    rs_cpu_sys_gic1_irq_pr_37

typedef struct _rs_cpu_sys_gic1_irq_pr_37  rs_cpu_sys_gic1_irq_pr_37;
struct _rs_cpu_sys_gic1_irq_pr_37 {
    unsigned int REG1_IRQ_PR_37                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_37(val) ((rs_cpu_sys_gic1_irq_pr_37*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_38                                           (HV_GIC_BASE_ADDRESS + 0x580)

#define CPU_SYS_GIC1_IRQ_PR_38_struct                                    rs_cpu_sys_gic1_irq_pr_38

typedef struct _rs_cpu_sys_gic1_irq_pr_38  rs_cpu_sys_gic1_irq_pr_38;
struct _rs_cpu_sys_gic1_irq_pr_38 {
    unsigned int REG1_IRQ_PR_38                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_38(val) ((rs_cpu_sys_gic1_irq_pr_38*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_39                                           (HV_GIC_BASE_ADDRESS + 0x584)

#define CPU_SYS_GIC1_IRQ_PR_39_struct                                    rs_cpu_sys_gic1_irq_pr_39

typedef struct _rs_cpu_sys_gic1_irq_pr_39  rs_cpu_sys_gic1_irq_pr_39;
struct _rs_cpu_sys_gic1_irq_pr_39 {
    unsigned int REG1_IRQ_PR_39                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_39(val) ((rs_cpu_sys_gic1_irq_pr_39*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_40                                           (HV_GIC_BASE_ADDRESS + 0x588)

#define CPU_SYS_GIC1_IRQ_PR_40_struct                                    rs_cpu_sys_gic1_irq_pr_40

typedef struct _rs_cpu_sys_gic1_irq_pr_40  rs_cpu_sys_gic1_irq_pr_40;
struct _rs_cpu_sys_gic1_irq_pr_40 {
    unsigned int REG1_IRQ_PR_40                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_40(val) ((rs_cpu_sys_gic1_irq_pr_40*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_41                                           (HV_GIC_BASE_ADDRESS + 0x58C)

#define CPU_SYS_GIC1_IRQ_PR_41_struct                                    rs_cpu_sys_gic1_irq_pr_41

typedef struct _rs_cpu_sys_gic1_irq_pr_41  rs_cpu_sys_gic1_irq_pr_41;
struct _rs_cpu_sys_gic1_irq_pr_41 {
    unsigned int REG1_IRQ_PR_41                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_41(val) ((rs_cpu_sys_gic1_irq_pr_41*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_42                                           (HV_GIC_BASE_ADDRESS + 0x590)

#define CPU_SYS_GIC1_IRQ_PR_42_struct                                    rs_cpu_sys_gic1_irq_pr_42

typedef struct _rs_cpu_sys_gic1_irq_pr_42  rs_cpu_sys_gic1_irq_pr_42;
struct _rs_cpu_sys_gic1_irq_pr_42 {
    unsigned int REG1_IRQ_PR_42                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_42(val) ((rs_cpu_sys_gic1_irq_pr_42*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_43                                           (HV_GIC_BASE_ADDRESS + 0x594)

#define CPU_SYS_GIC1_IRQ_PR_43_struct                                    rs_cpu_sys_gic1_irq_pr_43

typedef struct _rs_cpu_sys_gic1_irq_pr_43  rs_cpu_sys_gic1_irq_pr_43;
struct _rs_cpu_sys_gic1_irq_pr_43 {
    unsigned int REG1_IRQ_PR_43                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_43(val) ((rs_cpu_sys_gic1_irq_pr_43*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_44                                           (HV_GIC_BASE_ADDRESS + 0x598)

#define CPU_SYS_GIC1_IRQ_PR_44_struct                                    rs_cpu_sys_gic1_irq_pr_44

typedef struct _rs_cpu_sys_gic1_irq_pr_44  rs_cpu_sys_gic1_irq_pr_44;
struct _rs_cpu_sys_gic1_irq_pr_44 {
    unsigned int REG1_IRQ_PR_44                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_44(val) ((rs_cpu_sys_gic1_irq_pr_44*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_45                                           (HV_GIC_BASE_ADDRESS + 0x59C)

#define CPU_SYS_GIC1_IRQ_PR_45_struct                                    rs_cpu_sys_gic1_irq_pr_45

typedef struct _rs_cpu_sys_gic1_irq_pr_45  rs_cpu_sys_gic1_irq_pr_45;
struct _rs_cpu_sys_gic1_irq_pr_45 {
    unsigned int REG1_IRQ_PR_45                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_45(val) ((rs_cpu_sys_gic1_irq_pr_45*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_46                                           (HV_GIC_BASE_ADDRESS + 0x5A0)

#define CPU_SYS_GIC1_IRQ_PR_46_struct                                    rs_cpu_sys_gic1_irq_pr_46

typedef struct _rs_cpu_sys_gic1_irq_pr_46  rs_cpu_sys_gic1_irq_pr_46;
struct _rs_cpu_sys_gic1_irq_pr_46 {
    unsigned int REG1_IRQ_PR_46                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_46(val) ((rs_cpu_sys_gic1_irq_pr_46*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_47                                           (HV_GIC_BASE_ADDRESS + 0x5A4)

#define CPU_SYS_GIC1_IRQ_PR_47_struct                                    rs_cpu_sys_gic1_irq_pr_47

typedef struct _rs_cpu_sys_gic1_irq_pr_47  rs_cpu_sys_gic1_irq_pr_47;
struct _rs_cpu_sys_gic1_irq_pr_47 {
    unsigned int REG1_IRQ_PR_47                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_47(val) ((rs_cpu_sys_gic1_irq_pr_47*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_48                                           (HV_GIC_BASE_ADDRESS + 0x5A8)

#define CPU_SYS_GIC1_IRQ_PR_48_struct                                    rs_cpu_sys_gic1_irq_pr_48

typedef struct _rs_cpu_sys_gic1_irq_pr_48  rs_cpu_sys_gic1_irq_pr_48;
struct _rs_cpu_sys_gic1_irq_pr_48 {
    unsigned int REG1_IRQ_PR_48                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_48(val) ((rs_cpu_sys_gic1_irq_pr_48*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_49                                           (HV_GIC_BASE_ADDRESS + 0x5AC)

#define CPU_SYS_GIC1_IRQ_PR_49_struct                                    rs_cpu_sys_gic1_irq_pr_49

typedef struct _rs_cpu_sys_gic1_irq_pr_49  rs_cpu_sys_gic1_irq_pr_49;
struct _rs_cpu_sys_gic1_irq_pr_49 {
    unsigned int REG1_IRQ_PR_49                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_49(val) ((rs_cpu_sys_gic1_irq_pr_49*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_50                                           (HV_GIC_BASE_ADDRESS + 0x5B0)

#define CPU_SYS_GIC1_IRQ_PR_50_struct                                    rs_cpu_sys_gic1_irq_pr_50

typedef struct _rs_cpu_sys_gic1_irq_pr_50  rs_cpu_sys_gic1_irq_pr_50;
struct _rs_cpu_sys_gic1_irq_pr_50 {
    unsigned int REG1_IRQ_PR_50                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_50(val) ((rs_cpu_sys_gic1_irq_pr_50*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_51                                           (HV_GIC_BASE_ADDRESS + 0x5B4)

#define CPU_SYS_GIC1_IRQ_PR_51_struct                                    rs_cpu_sys_gic1_irq_pr_51

typedef struct _rs_cpu_sys_gic1_irq_pr_51  rs_cpu_sys_gic1_irq_pr_51;
struct _rs_cpu_sys_gic1_irq_pr_51 {
    unsigned int REG1_IRQ_PR_51                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_51(val) ((rs_cpu_sys_gic1_irq_pr_51*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_52                                           (HV_GIC_BASE_ADDRESS + 0x5B8)

#define CPU_SYS_GIC1_IRQ_PR_52_struct                                    rs_cpu_sys_gic1_irq_pr_52

typedef struct _rs_cpu_sys_gic1_irq_pr_52  rs_cpu_sys_gic1_irq_pr_52;
struct _rs_cpu_sys_gic1_irq_pr_52 {
    unsigned int REG1_IRQ_PR_52                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_52(val) ((rs_cpu_sys_gic1_irq_pr_52*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_53                                           (HV_GIC_BASE_ADDRESS + 0x5BC)

#define CPU_SYS_GIC1_IRQ_PR_53_struct                                    rs_cpu_sys_gic1_irq_pr_53

typedef struct _rs_cpu_sys_gic1_irq_pr_53  rs_cpu_sys_gic1_irq_pr_53;
struct _rs_cpu_sys_gic1_irq_pr_53 {
    unsigned int REG1_IRQ_PR_53                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_53(val) ((rs_cpu_sys_gic1_irq_pr_53*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_54                                           (HV_GIC_BASE_ADDRESS + 0x5C0)

#define CPU_SYS_GIC1_IRQ_PR_54_struct                                    rs_cpu_sys_gic1_irq_pr_54

typedef struct _rs_cpu_sys_gic1_irq_pr_54  rs_cpu_sys_gic1_irq_pr_54;
struct _rs_cpu_sys_gic1_irq_pr_54 {
    unsigned int REG1_IRQ_PR_54                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_54(val) ((rs_cpu_sys_gic1_irq_pr_54*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_55                                           (HV_GIC_BASE_ADDRESS + 0x5C4)

#define CPU_SYS_GIC1_IRQ_PR_55_struct                                    rs_cpu_sys_gic1_irq_pr_55

typedef struct _rs_cpu_sys_gic1_irq_pr_55  rs_cpu_sys_gic1_irq_pr_55;
struct _rs_cpu_sys_gic1_irq_pr_55 {
    unsigned int REG1_IRQ_PR_55                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_55(val) ((rs_cpu_sys_gic1_irq_pr_55*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_56                                           (HV_GIC_BASE_ADDRESS + 0x5C8)

#define CPU_SYS_GIC1_IRQ_PR_56_struct                                    rs_cpu_sys_gic1_irq_pr_56

typedef struct _rs_cpu_sys_gic1_irq_pr_56  rs_cpu_sys_gic1_irq_pr_56;
struct _rs_cpu_sys_gic1_irq_pr_56 {
    unsigned int REG1_IRQ_PR_56                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_56(val) ((rs_cpu_sys_gic1_irq_pr_56*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_57                                           (HV_GIC_BASE_ADDRESS + 0x5CC)

#define CPU_SYS_GIC1_IRQ_PR_57_struct                                    rs_cpu_sys_gic1_irq_pr_57

typedef struct _rs_cpu_sys_gic1_irq_pr_57  rs_cpu_sys_gic1_irq_pr_57;
struct _rs_cpu_sys_gic1_irq_pr_57 {
    unsigned int REG1_IRQ_PR_57                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_57(val) ((rs_cpu_sys_gic1_irq_pr_57*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_58                                           (HV_GIC_BASE_ADDRESS + 0x5D0)

#define CPU_SYS_GIC1_IRQ_PR_58_struct                                    rs_cpu_sys_gic1_irq_pr_58

typedef struct _rs_cpu_sys_gic1_irq_pr_58  rs_cpu_sys_gic1_irq_pr_58;
struct _rs_cpu_sys_gic1_irq_pr_58 {
    unsigned int REG1_IRQ_PR_58                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_58(val) ((rs_cpu_sys_gic1_irq_pr_58*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_59                                           (HV_GIC_BASE_ADDRESS + 0x5D4)

#define CPU_SYS_GIC1_IRQ_PR_59_struct                                    rs_cpu_sys_gic1_irq_pr_59

typedef struct _rs_cpu_sys_gic1_irq_pr_59  rs_cpu_sys_gic1_irq_pr_59;
struct _rs_cpu_sys_gic1_irq_pr_59 {
    unsigned int REG1_IRQ_PR_59                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_59(val) ((rs_cpu_sys_gic1_irq_pr_59*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_60                                           (HV_GIC_BASE_ADDRESS + 0x5D8)

#define CPU_SYS_GIC1_IRQ_PR_60_struct                                    rs_cpu_sys_gic1_irq_pr_60

typedef struct _rs_cpu_sys_gic1_irq_pr_60  rs_cpu_sys_gic1_irq_pr_60;
struct _rs_cpu_sys_gic1_irq_pr_60 {
    unsigned int REG1_IRQ_PR_60                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_60(val) ((rs_cpu_sys_gic1_irq_pr_60*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_61                                           (HV_GIC_BASE_ADDRESS + 0x5DC)

#define CPU_SYS_GIC1_IRQ_PR_61_struct                                    rs_cpu_sys_gic1_irq_pr_61

typedef struct _rs_cpu_sys_gic1_irq_pr_61  rs_cpu_sys_gic1_irq_pr_61;
struct _rs_cpu_sys_gic1_irq_pr_61 {
    unsigned int REG1_IRQ_PR_61                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_61(val) ((rs_cpu_sys_gic1_irq_pr_61*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_62                                           (HV_GIC_BASE_ADDRESS + 0x5E0)

#define CPU_SYS_GIC1_IRQ_PR_62_struct                                    rs_cpu_sys_gic1_irq_pr_62

typedef struct _rs_cpu_sys_gic1_irq_pr_62  rs_cpu_sys_gic1_irq_pr_62;
struct _rs_cpu_sys_gic1_irq_pr_62 {
    unsigned int REG1_IRQ_PR_62                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_62(val) ((rs_cpu_sys_gic1_irq_pr_62*)&(val))



#define CPU_SYS_GIC1_IRQ_PR_63                                           (HV_GIC_BASE_ADDRESS + 0x5E4)

#define CPU_SYS_GIC1_IRQ_PR_63_struct                                    rs_cpu_sys_gic1_irq_pr_63

typedef struct _rs_cpu_sys_gic1_irq_pr_63  rs_cpu_sys_gic1_irq_pr_63;
struct _rs_cpu_sys_gic1_irq_pr_63 {
    unsigned int REG1_IRQ_PR_63                             : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_gic1_irq_pr_63(val) ((rs_cpu_sys_gic1_irq_pr_63*)&(val))



#define CPU_SYS_GIC1_IRQ_VECTOR_DEFAULT                                  (HV_GIC_BASE_ADDRESS + 0x5E8)

#define CPU_SYS_GIC1_IRQ_VECTOR_DEFAULT_struct                           rs_cpu_sys_gic1_irq_vector_default

typedef struct _rs_cpu_sys_gic1_irq_vector_default  rs_cpu_sys_gic1_irq_vector_default;
struct _rs_cpu_sys_gic1_irq_vector_default {
    unsigned int REG1_IRQ_VECTOR_DEFAULT                    :32;
};
#define cpu_sys_gic1_irq_vector_default(val) ((rs_cpu_sys_gic1_irq_vector_default*)&(val))



#endif