#ifndef _HV_PAGE_HT7315_DPU_SR_SYNC_H_
#define _HV_PAGE_HT7315_DPU_SR_SYNC_H_

#ifndef HV_DPU_SR_SYNC_BASE_ADDRESS
    #define HV_DPU_SR_SYNC_BASE_ADDRESS                                         0x11024000
#endif


#define DISP_TOP_DPU_SR_SYNC_RW0                                         (HV_DPU_SR_SYNC_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_SR_SYNC_RW0_struct                                  rs_disp_top_dpu_sr_sync_rw0

typedef struct _rs_disp_top_dpu_sr_sync_rw0  rs_disp_top_dpu_sr_sync_rw0;
struct _rs_disp_top_dpu_sr_sync_rw0 {
    unsigned int reg_en                                     : 1;
    unsigned int reg_en_no_latch                            : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_sr_sync_rw0(val) ((rs_disp_top_dpu_sr_sync_rw0*)&(val))



#define DISP_TOP_DPU_SR_SYNC_RW1                                         (HV_DPU_SR_SYNC_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_SR_SYNC_RW1_struct                                  rs_disp_top_dpu_sr_sync_rw1

typedef struct _rs_disp_top_dpu_sr_sync_rw1  rs_disp_top_dpu_sr_sync_rw1;
struct _rs_disp_top_dpu_sr_sync_rw1 {
    unsigned int reg_sr_htotal                              :14;
    unsigned int reg_sr_vact                                :14;
    unsigned int reg_sr_sw_tbl_go                           : 1;
    unsigned int reg_sr_sw_tbl_go_sel                       : 2;
    unsigned int reserved                                   : 1;
};
#define disp_top_dpu_sr_sync_rw1(val) ((rs_disp_top_dpu_sr_sync_rw1*)&(val))



#define DISP_TOP_DPU_SR_SYNC_RW2                                         (HV_DPU_SR_SYNC_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_SR_SYNC_RW2_struct                                  rs_disp_top_dpu_sr_sync_rw2

typedef struct _rs_disp_top_dpu_sr_sync_rw2  rs_disp_top_dpu_sr_sync_rw2;
struct _rs_disp_top_dpu_sr_sync_rw2 {
    unsigned int reg_sr_sync_frc_trig_vdly                  :14;
    unsigned int reg_sr_sync_frc_trig_hdly                  :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_sr_sync_rw2(val) ((rs_disp_top_dpu_sr_sync_rw2*)&(val))



#define DISP_TOP_DPU_SR_SYNC_RW3                                         (HV_DPU_SR_SYNC_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_SR_SYNC_RW3_struct                                  rs_disp_top_dpu_sr_sync_rw3

typedef struct _rs_disp_top_dpu_sr_sync_rw3  rs_disp_top_dpu_sr_sync_rw3;
struct _rs_disp_top_dpu_sr_sync_rw3 {
    unsigned int reg_sr_sync_data_trig_vdly                 :14;
    unsigned int reg_sr_sync_data_trig_hdly                 :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_sr_sync_rw3(val) ((rs_disp_top_dpu_sr_sync_rw3*)&(val))



#define DISP_TOP_DPU_SR_SYNC_RW4                                         (HV_DPU_SR_SYNC_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_SR_SYNC_RW4_struct                                  rs_disp_top_dpu_sr_sync_rw4

typedef struct _rs_disp_top_dpu_sr_sync_rw4  rs_disp_top_dpu_sr_sync_rw4;
struct _rs_disp_top_dpu_sr_sync_rw4 {
    unsigned int reg_sr_sync_tbl_trig_vdly                  :14;
    unsigned int reg_sr_sync_tbl_trig_hdly                  :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_sr_sync_rw4(val) ((rs_disp_top_dpu_sr_sync_rw4*)&(val))



#endif