#ifndef _HV_PAGE_HT7315_DPU_CA_VGSF_00_H_
#define _HV_PAGE_HT7315_DPU_CA_VGSF_00_H_

#ifndef HV_DPU_CA_VGSF_00_BASE_ADDRESS
    #define HV_DPU_CA_VGSF_00_BASE_ADDRESS                                         0x11020000
#endif


#define DISP_TOP_DPU_CA_VGSF_00_00                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_CA_VGSF_00_00_struct                                rs_disp_top_dpu_ca_vgsf_00_00

typedef struct _rs_disp_top_dpu_ca_vgsf_00_00  rs_disp_top_dpu_ca_vgsf_00_00;
struct _rs_disp_top_dpu_ca_vgsf_00_00 {
    unsigned int reg_00_en                                  : 1;
    unsigned int reg_00_en_no_latch                         : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_ca_vgsf_00_00(val) ((rs_disp_top_dpu_ca_vgsf_00_00*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_04                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_CA_VGSF_00_04_struct                                rs_disp_top_dpu_ca_vgsf_00_04

typedef struct _rs_disp_top_dpu_ca_vgsf_00_04  rs_disp_top_dpu_ca_vgsf_00_04;
struct _rs_disp_top_dpu_ca_vgsf_00_04 {
    unsigned int reg_00_ca_vg_on                            : 1;
    unsigned int reg_00_ca_in_hsize                         :13;
    unsigned int reg_00_ca_in_vsize                         :13;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_ca_vgsf_00_04(val) ((rs_disp_top_dpu_ca_vgsf_00_04*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_08                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_CA_VGSF_00_08_struct                                rs_disp_top_dpu_ca_vgsf_00_08

typedef struct _rs_disp_top_dpu_ca_vgsf_00_08  rs_disp_top_dpu_ca_vgsf_00_08;
struct _rs_disp_top_dpu_ca_vgsf_00_08 {
    unsigned int reg_00_ca_in_mask_on                       : 1;
    unsigned int reg_00_ca_in_cut_hstart                    :13;
    unsigned int reserved                                   :18;
};
#define disp_top_dpu_ca_vgsf_00_08(val) ((rs_disp_top_dpu_ca_vgsf_00_08*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_0C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_CA_VGSF_00_0C_struct                                rs_disp_top_dpu_ca_vgsf_00_0c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_0c  rs_disp_top_dpu_ca_vgsf_00_0c;
struct _rs_disp_top_dpu_ca_vgsf_00_0c {
    unsigned int reg_00_ca_in_cut_hend                      :13;
    unsigned int reg_00_ca_in_cut_vstart                    :13;
    unsigned int reserved                                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_0c(val) ((rs_disp_top_dpu_ca_vgsf_00_0c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_10                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_CA_VGSF_00_10_struct                                rs_disp_top_dpu_ca_vgsf_00_10

typedef struct _rs_disp_top_dpu_ca_vgsf_00_10  rs_disp_top_dpu_ca_vgsf_00_10;
struct _rs_disp_top_dpu_ca_vgsf_00_10 {
    unsigned int reg_00_ca_in_cut_vend                      :13;
    unsigned int reg_00_ca_in_pat_en                        : 1;
    unsigned int reg_00_ca_in_pat_func_clk_en               : 1;
    unsigned int reg_00_ca_in_pat_slfgen_en                 : 1;
    unsigned int reg_00_ca_in_pat_mode                      : 8;
    unsigned int reg_00_pat_interlace_en                    : 1;
    unsigned int reserved                                   : 7;
};
#define disp_top_dpu_ca_vgsf_00_10(val) ((rs_disp_top_dpu_ca_vgsf_00_10*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_14                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_CA_VGSF_00_14_struct                                rs_disp_top_dpu_ca_vgsf_00_14

typedef struct _rs_disp_top_dpu_ca_vgsf_00_14  rs_disp_top_dpu_ca_vgsf_00_14;
struct _rs_disp_top_dpu_ca_vgsf_00_14 {
    unsigned int reg_00_ca_in_pat_hact                      :13;
    unsigned int reg_00_ca_in_pat_htotal                    :13;
    unsigned int reserved                                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_14(val) ((rs_disp_top_dpu_ca_vgsf_00_14*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_18                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x18)

#define DISP_TOP_DPU_CA_VGSF_00_18_struct                                rs_disp_top_dpu_ca_vgsf_00_18

typedef struct _rs_disp_top_dpu_ca_vgsf_00_18  rs_disp_top_dpu_ca_vgsf_00_18;
struct _rs_disp_top_dpu_ca_vgsf_00_18 {
    unsigned int reg_00_ca_in_pat_hbp                       :10;
    unsigned int reg_00_ca_in_pat_hwdth                     :10;
    unsigned int reg_00_pat_line_position                   : 6;
    unsigned int reg_00_pat_pixl_position                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_18(val) ((rs_disp_top_dpu_ca_vgsf_00_18*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_1C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x1C)

#define DISP_TOP_DPU_CA_VGSF_00_1C_struct                                rs_disp_top_dpu_ca_vgsf_00_1c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_1c  rs_disp_top_dpu_ca_vgsf_00_1c;
struct _rs_disp_top_dpu_ca_vgsf_00_1c {
    unsigned int reg_00_ca_in_pat_vact                      :13;
    unsigned int reg_00_ca_in_pat_vtotal                    :13;
    unsigned int reserved                                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_1c(val) ((rs_disp_top_dpu_ca_vgsf_00_1c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_20                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x20)

#define DISP_TOP_DPU_CA_VGSF_00_20_struct                                rs_disp_top_dpu_ca_vgsf_00_20

typedef struct _rs_disp_top_dpu_ca_vgsf_00_20  rs_disp_top_dpu_ca_vgsf_00_20;
struct _rs_disp_top_dpu_ca_vgsf_00_20 {
    unsigned int reg_00_ca_in_pat_vbp                       :10;
    unsigned int reg_00_ca_in_pat_vwdth                     :10;
    unsigned int reg_00_ca_in_pat_loop_on                   : 1;
    unsigned int reg_00_ca_in_pat_res                       : 2;
    unsigned int reg_00_ca_in_pat_loop_speed                : 1;
    unsigned int reg_00_ca_in_pat_move_speed                : 1;
    unsigned int reserved                                   : 7;
};
#define disp_top_dpu_ca_vgsf_00_20(val) ((rs_disp_top_dpu_ca_vgsf_00_20*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_24                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x24)

#define DISP_TOP_DPU_CA_VGSF_00_24_struct                                rs_disp_top_dpu_ca_vgsf_00_24

typedef struct _rs_disp_top_dpu_ca_vgsf_00_24  rs_disp_top_dpu_ca_vgsf_00_24;
struct _rs_disp_top_dpu_ca_vgsf_00_24 {
    unsigned int reg_00_ca_vg_pair_mapping_en               : 1;
    unsigned int reg_00_ca_vg_pair_mapping_func_clk_en      : 1;
    unsigned int reg_00_ca_vg_pair_mapping_patt             : 6;
    unsigned int reg_00_ca_vg_c02_func_clk_en               : 1;
    unsigned int reserved                                   :23;
};
#define disp_top_dpu_ca_vgsf_00_24(val) ((rs_disp_top_dpu_ca_vgsf_00_24*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_28                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x28)

#define DISP_TOP_DPU_CA_VGSF_00_28_struct                                rs_disp_top_dpu_ca_vgsf_00_28

typedef struct _rs_disp_top_dpu_ca_vgsf_00_28  rs_disp_top_dpu_ca_vgsf_00_28;
struct _rs_disp_top_dpu_ca_vgsf_00_28 {
    unsigned int reg_00_ca_vg_yuv422to444_func_clk_en       : 1;
    unsigned int reg_00_ca_vg_ch_tap                        : 2;
    unsigned int reg_00_ca_vg_ch_cshift                     : 1;
    unsigned int reg_00_ca_vg_ch_coef_2tap                  :16;
    unsigned int reserved                                   :12;
};
#define disp_top_dpu_ca_vgsf_00_28(val) ((rs_disp_top_dpu_ca_vgsf_00_28*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_2C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x2C)

#define DISP_TOP_DPU_CA_VGSF_00_2C_struct                                rs_disp_top_dpu_ca_vgsf_00_2c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_2c  rs_disp_top_dpu_ca_vgsf_00_2c;
struct _rs_disp_top_dpu_ca_vgsf_00_2c {
    unsigned int reg_00_ca_vg_ch_coef_4tap                  :32;
};
#define disp_top_dpu_ca_vgsf_00_2c(val) ((rs_disp_top_dpu_ca_vgsf_00_2c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_30                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x30)

#define DISP_TOP_DPU_CA_VGSF_00_30_struct                                rs_disp_top_dpu_ca_vgsf_00_30

typedef struct _rs_disp_top_dpu_ca_vgsf_00_30  rs_disp_top_dpu_ca_vgsf_00_30;
struct _rs_disp_top_dpu_ca_vgsf_00_30 {
    unsigned int reg_00_ca_vg_cs1_convert_func_clk_en       : 1;
    unsigned int reg_00_ca_vg_csc1_en                       : 1;
    unsigned int reg_00_ca_vg_csc1_mode_mux                 : 3;
    unsigned int reg_00_ca_vg_csc1_ofs_out_r                :12;
    unsigned int reg_00_ca_vg_hdr_csc1_ofs_in_v             :12;
    unsigned int reserved                                   : 3;
};
#define disp_top_dpu_ca_vgsf_00_30(val) ((rs_disp_top_dpu_ca_vgsf_00_30*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_34                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x34)

#define DISP_TOP_DPU_CA_VGSF_00_34_struct                                rs_disp_top_dpu_ca_vgsf_00_34

typedef struct _rs_disp_top_dpu_ca_vgsf_00_34  rs_disp_top_dpu_ca_vgsf_00_34;
struct _rs_disp_top_dpu_ca_vgsf_00_34 {
    unsigned int reg_00_ca_vg_csc1_v_r_n                    :16;
    unsigned int reg_00_ca_vg_csc1_v_r_p                    :16;
};
#define disp_top_dpu_ca_vgsf_00_34(val) ((rs_disp_top_dpu_ca_vgsf_00_34*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_38                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x38)

#define DISP_TOP_DPU_CA_VGSF_00_38_struct                                rs_disp_top_dpu_ca_vgsf_00_38

typedef struct _rs_disp_top_dpu_ca_vgsf_00_38  rs_disp_top_dpu_ca_vgsf_00_38;
struct _rs_disp_top_dpu_ca_vgsf_00_38 {
    unsigned int reg_00_ca_vg_csc1_u_r_coef                 :16;
    unsigned int reg_00_ca_vg_csc1_y_r_coef                 :16;
};
#define disp_top_dpu_ca_vgsf_00_38(val) ((rs_disp_top_dpu_ca_vgsf_00_38*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_3C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x3C)

#define DISP_TOP_DPU_CA_VGSF_00_3C_struct                                rs_disp_top_dpu_ca_vgsf_00_3c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_3c  rs_disp_top_dpu_ca_vgsf_00_3c;
struct _rs_disp_top_dpu_ca_vgsf_00_3c {
    unsigned int reg_00_ca_vg_csc1_ofs_out_g                :12;
    unsigned int reg_00_ca_vg_hdr_csc1_ofs_in_y             :12;
    unsigned int reserved                                   : 8;
};
#define disp_top_dpu_ca_vgsf_00_3c(val) ((rs_disp_top_dpu_ca_vgsf_00_3c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_40                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x40)

#define DISP_TOP_DPU_CA_VGSF_00_40_struct                                rs_disp_top_dpu_ca_vgsf_00_40

typedef struct _rs_disp_top_dpu_ca_vgsf_00_40  rs_disp_top_dpu_ca_vgsf_00_40;
struct _rs_disp_top_dpu_ca_vgsf_00_40 {
    unsigned int reg_00_ca_vg_csc1_v_g_coef                 :16;
    unsigned int reg_00_ca_vg_csc1_u_g_coef                 :16;
};
#define disp_top_dpu_ca_vgsf_00_40(val) ((rs_disp_top_dpu_ca_vgsf_00_40*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_44                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x44)

#define DISP_TOP_DPU_CA_VGSF_00_44_struct                                rs_disp_top_dpu_ca_vgsf_00_44

typedef struct _rs_disp_top_dpu_ca_vgsf_00_44  rs_disp_top_dpu_ca_vgsf_00_44;
struct _rs_disp_top_dpu_ca_vgsf_00_44 {
    unsigned int reg_00_ca_vg_csc1_y_g_coef                 :16;
    unsigned int reg_00_ca_vg_csc1_ofs_out_b                :12;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_vgsf_00_44(val) ((rs_disp_top_dpu_ca_vgsf_00_44*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_48                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x48)

#define DISP_TOP_DPU_CA_VGSF_00_48_struct                                rs_disp_top_dpu_ca_vgsf_00_48

typedef struct _rs_disp_top_dpu_ca_vgsf_00_48  rs_disp_top_dpu_ca_vgsf_00_48;
struct _rs_disp_top_dpu_ca_vgsf_00_48 {
    unsigned int reg_00_ca_vg_hdr_csc1_ofs_in_u             :12;
    unsigned int reg_00_ca_vg_csc1_v_b_coef                 :16;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_vgsf_00_48(val) ((rs_disp_top_dpu_ca_vgsf_00_48*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_4C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x4C)

#define DISP_TOP_DPU_CA_VGSF_00_4C_struct                                rs_disp_top_dpu_ca_vgsf_00_4c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_4c  rs_disp_top_dpu_ca_vgsf_00_4c;
struct _rs_disp_top_dpu_ca_vgsf_00_4c {
    unsigned int reg_00_ca_vg_csc1_u_b_n                    :16;
    unsigned int reg_00_ca_vg_csc1_u_b_p                    :16;
};
#define disp_top_dpu_ca_vgsf_00_4c(val) ((rs_disp_top_dpu_ca_vgsf_00_4c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_50                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x50)

#define DISP_TOP_DPU_CA_VGSF_00_50_struct                                rs_disp_top_dpu_ca_vgsf_00_50

typedef struct _rs_disp_top_dpu_ca_vgsf_00_50  rs_disp_top_dpu_ca_vgsf_00_50;
struct _rs_disp_top_dpu_ca_vgsf_00_50 {
    unsigned int reg_00_ca_vg_csc1_y_b_coef                 :16;
    unsigned int reserved                                   : 8;
    unsigned int reg_00_ca_vg_hdr_func_clk_en               : 1;
    unsigned int reg_00_ca_vg_cs2_convert_func_clk_en       : 1;
    unsigned int reg_00_ca_vg_cs2_convert_on                : 1;
    unsigned int reg_00_ca_vg_cs2_convert_mode              : 4;
    unsigned int reserved_1                                 : 1;
};
#define disp_top_dpu_ca_vgsf_00_50(val) ((rs_disp_top_dpu_ca_vgsf_00_50*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_54                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x54)

#define DISP_TOP_DPU_CA_VGSF_00_54_struct                                rs_disp_top_dpu_ca_vgsf_00_54

typedef struct _rs_disp_top_dpu_ca_vgsf_00_54  rs_disp_top_dpu_ca_vgsf_00_54;
struct _rs_disp_top_dpu_ca_vgsf_00_54 {
    unsigned int reg_00_ca_vg_cs2_usr_coef00                :15;
    unsigned int reg_00_ca_vg_cs2_usr_coef01                :15;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_ca_vgsf_00_54(val) ((rs_disp_top_dpu_ca_vgsf_00_54*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_58                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x58)

#define DISP_TOP_DPU_CA_VGSF_00_58_struct                                rs_disp_top_dpu_ca_vgsf_00_58

typedef struct _rs_disp_top_dpu_ca_vgsf_00_58  rs_disp_top_dpu_ca_vgsf_00_58;
struct _rs_disp_top_dpu_ca_vgsf_00_58 {
    unsigned int reg_00_ca_vg_cs2_usr_coef02                :15;
    unsigned int reg_00_ca_vg_cs2_usr_coef10                :15;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_ca_vgsf_00_58(val) ((rs_disp_top_dpu_ca_vgsf_00_58*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_5C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x5C)

#define DISP_TOP_DPU_CA_VGSF_00_5C_struct                                rs_disp_top_dpu_ca_vgsf_00_5c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_5c  rs_disp_top_dpu_ca_vgsf_00_5c;
struct _rs_disp_top_dpu_ca_vgsf_00_5c {
    unsigned int reg_00_ca_vg_cs2_usr_coef11                :15;
    unsigned int reg_00_ca_vg_cs2_usr_coef12                :15;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_ca_vgsf_00_5c(val) ((rs_disp_top_dpu_ca_vgsf_00_5c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_60                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x60)

#define DISP_TOP_DPU_CA_VGSF_00_60_struct                                rs_disp_top_dpu_ca_vgsf_00_60

typedef struct _rs_disp_top_dpu_ca_vgsf_00_60  rs_disp_top_dpu_ca_vgsf_00_60;
struct _rs_disp_top_dpu_ca_vgsf_00_60 {
    unsigned int reg_00_ca_vg_cs2_usr_coef20                :15;
    unsigned int reg_00_ca_vg_cs2_usr_coef21                :15;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_ca_vgsf_00_60(val) ((rs_disp_top_dpu_ca_vgsf_00_60*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_64                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x64)

#define DISP_TOP_DPU_CA_VGSF_00_64_struct                                rs_disp_top_dpu_ca_vgsf_00_64

typedef struct _rs_disp_top_dpu_ca_vgsf_00_64  rs_disp_top_dpu_ca_vgsf_00_64;
struct _rs_disp_top_dpu_ca_vgsf_00_64 {
    unsigned int reg_00_ca_vg_cs2_usr_coef22                :15;
    unsigned int reg_00_ca_vg_cs2_usr_const0                :12;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_ca_vgsf_00_64(val) ((rs_disp_top_dpu_ca_vgsf_00_64*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_68                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x68)

#define DISP_TOP_DPU_CA_VGSF_00_68_struct                                rs_disp_top_dpu_ca_vgsf_00_68

typedef struct _rs_disp_top_dpu_ca_vgsf_00_68  rs_disp_top_dpu_ca_vgsf_00_68;
struct _rs_disp_top_dpu_ca_vgsf_00_68 {
    unsigned int reg_00_ca_vg_cs2_usr_const1                :12;
    unsigned int reg_00_ca_vg_cs2_usr_const2                :12;
    unsigned int reg_00_ca_msf_func_clk_en                  : 1;
    unsigned int reg_00_ca_vg_msf_out_waiti                 : 1;
    unsigned int reg_00_ca_vg_msf_tbl_id                    : 4;
    unsigned int reg_00_ca_vg_msf_tbl_sel                   : 1;
    unsigned int reserved                                   : 1;
};
#define disp_top_dpu_ca_vgsf_00_68(val) ((rs_disp_top_dpu_ca_vgsf_00_68*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_6C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x6C)

#define DISP_TOP_DPU_CA_VGSF_00_6C_struct                                rs_disp_top_dpu_ca_vgsf_00_6c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_6c  rs_disp_top_dpu_ca_vgsf_00_6c;
struct _rs_disp_top_dpu_ca_vgsf_00_6c {
    unsigned int reg_00_ca_vg_msf_yhmode                    : 2;
    unsigned int reg_00_ca_vg_msf_yvmode                    : 2;
    unsigned int reg_00_ca_vg_phos                          : 6;
    unsigned int reserved                                   :22;
};
#define disp_top_dpu_ca_vgsf_00_6c(val) ((rs_disp_top_dpu_ca_vgsf_00_6c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_70                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x70)

#define DISP_TOP_DPU_CA_VGSF_00_70_struct                                rs_disp_top_dpu_ca_vgsf_00_70

typedef struct _rs_disp_top_dpu_ca_vgsf_00_70  rs_disp_top_dpu_ca_vgsf_00_70;
struct _rs_disp_top_dpu_ca_vgsf_00_70 {
    unsigned int reg_00_ca_vg_phos_ps                       :26;
    unsigned int reg_00_ca_vg_pvos                          : 6;
};
#define disp_top_dpu_ca_vgsf_00_70(val) ((rs_disp_top_dpu_ca_vgsf_00_70*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_74                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x74)

#define DISP_TOP_DPU_CA_VGSF_00_74_struct                                rs_disp_top_dpu_ca_vgsf_00_74

typedef struct _rs_disp_top_dpu_ca_vgsf_00_74  rs_disp_top_dpu_ca_vgsf_00_74;
struct _rs_disp_top_dpu_ca_vgsf_00_74 {
    unsigned int reg_00_ca_vg_pvos_ps                       :26;
    unsigned int reserved                                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_74(val) ((rs_disp_top_dpu_ca_vgsf_00_74*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_78                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x78)

#define DISP_TOP_DPU_CA_VGSF_00_78_struct                                rs_disp_top_dpu_ca_vgsf_00_78

typedef struct _rs_disp_top_dpu_ca_vgsf_00_78  rs_disp_top_dpu_ca_vgsf_00_78;
struct _rs_disp_top_dpu_ca_vgsf_00_78 {
    unsigned int reg_00_ca_vg_hsf_in_size                   :13;
    unsigned int reg_00_ca_vg_vsf_in_size                   :13;
    unsigned int reserved                                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_78(val) ((rs_disp_top_dpu_ca_vgsf_00_78*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_7C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x7C)

#define DISP_TOP_DPU_CA_VGSF_00_7C_struct                                rs_disp_top_dpu_ca_vgsf_00_7c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_7c  rs_disp_top_dpu_ca_vgsf_00_7c;
struct _rs_disp_top_dpu_ca_vgsf_00_7c {
    unsigned int reg_00_ca_vg_hsf_out_size                  :13;
    unsigned int reg_00_ca_vg_vsf_out_size                  :13;
    unsigned int reserved                                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_7c(val) ((rs_disp_top_dpu_ca_vgsf_00_7c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_80                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x80)

#define DISP_TOP_DPU_CA_VGSF_00_80_struct                                rs_disp_top_dpu_ca_vgsf_00_80

typedef struct _rs_disp_top_dpu_ca_vgsf_00_80  rs_disp_top_dpu_ca_vgsf_00_80;
struct _rs_disp_top_dpu_ca_vgsf_00_80 {
    unsigned int reg_00_ca_vg_hfilbase                      :19;
    unsigned int reg_00_ca_vg_hfilbase_num                  : 4;
    unsigned int reg_00_ca_vg_hfilbase_pixel                : 4;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_ca_vgsf_00_80(val) ((rs_disp_top_dpu_ca_vgsf_00_80*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_84                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x84)

#define DISP_TOP_DPU_CA_VGSF_00_84_struct                                rs_disp_top_dpu_ca_vgsf_00_84

typedef struct _rs_disp_top_dpu_ca_vgsf_00_84  rs_disp_top_dpu_ca_vgsf_00_84;
struct _rs_disp_top_dpu_ca_vgsf_00_84 {
    unsigned int reg_00_ca_vg_vfilbase                      :19;
    unsigned int reg_00_ca_vg_vfilbase_num                  : 4;
    unsigned int reg_00_ca_vg_vfilbase_pixel                : 4;
    unsigned int reg_00_ca_vg_wtr_data_sel                  : 1;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ca_vgsf_00_84(val) ((rs_disp_top_dpu_ca_vgsf_00_84*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_88                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x88)

#define DISP_TOP_DPU_CA_VGSF_00_88_struct                                rs_disp_top_dpu_ca_vgsf_00_88

typedef struct _rs_disp_top_dpu_ca_vgsf_00_88  rs_disp_top_dpu_ca_vgsf_00_88;
struct _rs_disp_top_dpu_ca_vgsf_00_88 {
    unsigned int reg_00_ca_out_mask_on                      : 1;
    unsigned int reg_00_ca_out_cut_hstart                   :13;
    unsigned int reg_00_ca_out_cut_hend                     :13;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_ca_vgsf_00_88(val) ((rs_disp_top_dpu_ca_vgsf_00_88*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_8C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x8C)

#define DISP_TOP_DPU_CA_VGSF_00_8C_struct                                rs_disp_top_dpu_ca_vgsf_00_8c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_8c  rs_disp_top_dpu_ca_vgsf_00_8c;
struct _rs_disp_top_dpu_ca_vgsf_00_8c {
    unsigned int reg_00_ca_out_cut_vstart                   :13;
    unsigned int reg_00_ca_out_cut_vend                     :13;
    unsigned int reserved                                   : 6;
};
#define disp_top_dpu_ca_vgsf_00_8c(val) ((rs_disp_top_dpu_ca_vgsf_00_8c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_90                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x90)

#define DISP_TOP_DPU_CA_VGSF_00_90_struct                                rs_disp_top_dpu_ca_vgsf_00_90

typedef struct _rs_disp_top_dpu_ca_vgsf_00_90  rs_disp_top_dpu_ca_vgsf_00_90;
struct _rs_disp_top_dpu_ca_vgsf_00_90 {
    unsigned int reg_00_ca_vg_c42_func_clk_en               : 1;
    unsigned int reg_00_ca_vg_c20_func_clk_en               : 1;
    unsigned int reg_00_ca_vg_c42_on                        : 1;
    unsigned int reg_00_ca_spch_en                          : 1;
    unsigned int reg_00_ca_out_hsize                        :13;
    unsigned int reg_00_ca_out_vsize                        :13;
    unsigned int reg_00_ca_spch_softrst                     : 1;
    unsigned int reserved                                   : 1;
};
#define disp_top_dpu_ca_vgsf_00_90(val) ((rs_disp_top_dpu_ca_vgsf_00_90*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_94                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x94)

#define DISP_TOP_DPU_CA_VGSF_00_94_struct                                rs_disp_top_dpu_ca_vgsf_00_94

typedef struct _rs_disp_top_dpu_ca_vgsf_00_94  rs_disp_top_dpu_ca_vgsf_00_94;
struct _rs_disp_top_dpu_ca_vgsf_00_94 {
    unsigned int reg_00_ca_mon_ch_sel                       : 4;
    unsigned int reg_00_ca_mon_enable                       : 1;
    unsigned int reserved                                   :27;
};
#define disp_top_dpu_ca_vgsf_00_94(val) ((rs_disp_top_dpu_ca_vgsf_00_94*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_98                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x98)

#define DISP_TOP_DPU_CA_VGSF_00_98_struct                                rs_disp_top_dpu_ca_vgsf_00_98

typedef struct _rs_disp_top_dpu_ca_vgsf_00_98  rs_disp_top_dpu_ca_vgsf_00_98;
struct _rs_disp_top_dpu_ca_vgsf_00_98 {
    unsigned int reg_00_ca_mon_height                       :16;
    unsigned int reg_00_ca_mon_width                        :16;
};
#define disp_top_dpu_ca_vgsf_00_98(val) ((rs_disp_top_dpu_ca_vgsf_00_98*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_9C                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0x9C)

#define DISP_TOP_DPU_CA_VGSF_00_9C_struct                                rs_disp_top_dpu_ca_vgsf_00_9c

typedef struct _rs_disp_top_dpu_ca_vgsf_00_9c  rs_disp_top_dpu_ca_vgsf_00_9c;
struct _rs_disp_top_dpu_ca_vgsf_00_9c {
    unsigned int reg_00_cap_int_en                          : 2;
    unsigned int reg_00_cap_int_mode                        : 4;
    unsigned int reg_00_cap_int_clr                         : 2;
    unsigned int reserved                                   :24;
};
#define disp_top_dpu_ca_vgsf_00_9c(val) ((rs_disp_top_dpu_ca_vgsf_00_9c*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_F4                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0xF4)

#define DISP_TOP_DPU_CA_VGSF_00_F4_struct                                rs_disp_top_dpu_ca_vgsf_00_f4

typedef struct _rs_disp_top_dpu_ca_vgsf_00_f4  rs_disp_top_dpu_ca_vgsf_00_f4;
struct _rs_disp_top_dpu_ca_vgsf_00_f4 {
    unsigned int regr_00_cap_int_with_out_mask              : 2;
    unsigned int regr_00_cap_int_with_mask                  : 2;
    unsigned int reserved                                   :28;
};
#define disp_top_dpu_ca_vgsf_00_f4(val) ((rs_disp_top_dpu_ca_vgsf_00_f4*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_F8                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0xF8)

#define DISP_TOP_DPU_CA_VGSF_00_F8_struct                                rs_disp_top_dpu_ca_vgsf_00_f8

typedef struct _rs_disp_top_dpu_ca_vgsf_00_f8  rs_disp_top_dpu_ca_vgsf_00_f8;
struct _rs_disp_top_dpu_ca_vgsf_00_f8 {
    unsigned int regr_00_ca_mon_frame_htotal                :16;
    unsigned int regr_00_ca_mon_frame_lin_num               :16;
};
#define disp_top_dpu_ca_vgsf_00_f8(val) ((rs_disp_top_dpu_ca_vgsf_00_f8*)&(val))



#define DISP_TOP_DPU_CA_VGSF_00_FC                                       (HV_DPU_CA_VGSF_00_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_CA_VGSF_00_FC_struct                                rs_disp_top_dpu_ca_vgsf_00_fc

typedef struct _rs_disp_top_dpu_ca_vgsf_00_fc  rs_disp_top_dpu_ca_vgsf_00_fc;
struct _rs_disp_top_dpu_ca_vgsf_00_fc {
    unsigned int regr_00_ca_mon_frame_pxl_num               :32;
};
#define disp_top_dpu_ca_vgsf_00_fc(val) ((rs_disp_top_dpu_ca_vgsf_00_fc*)&(val))



#endif