#ifndef _HV_PAGE_HT7315_SPI0_H_
#define _HV_PAGE_HT7315_SPI0_H_

#ifndef HV_SPI0_BASE_ADDRESS
    #define HV_SPI0_BASE_ADDRESS                                         0x11084000
#endif


#define CPU_SYS_SPI0_M_CTRLR0                                            (HV_SPI0_BASE_ADDRESS + 0x000)

#define CPU_SYS_SPI0_M_CTRLR0_struct                                     rs_cpu_sys_spi0_m_ctrlr0

typedef struct _rs_cpu_sys_spi0_m_ctrlr0  rs_cpu_sys_spi0_m_ctrlr0;
struct _rs_cpu_sys_spi0_m_ctrlr0 {
    unsigned int DFS                                        : 4;
    unsigned int FRF                                        : 2;
    unsigned int SCPH                                       : 1;
    unsigned int SCPOL                                      : 1;
    unsigned int TMOD                                       : 2;
    unsigned int reserved                                   : 1;
    unsigned int SRL                                        : 1;
    unsigned int CFS                                        : 4;
    unsigned int DFS_32                                     : 5;
    unsigned int SPI_FRF                                    : 2;
    unsigned int reserved_1                                 : 1;
    unsigned int SSTE                                       : 1;
    unsigned int reserved_2                                 : 7;
};
#define cpu_sys_spi0_m_ctrlr0(val) ((rs_cpu_sys_spi0_m_ctrlr0*)&(val))



#define CPU_SYS_SPI0_M_CTRLR1                                            (HV_SPI0_BASE_ADDRESS + 0x004)

#define CPU_SYS_SPI0_M_CTRLR1_struct                                     rs_cpu_sys_spi0_m_ctrlr1

typedef struct _rs_cpu_sys_spi0_m_ctrlr1  rs_cpu_sys_spi0_m_ctrlr1;
struct _rs_cpu_sys_spi0_m_ctrlr1 {
    unsigned int NDF                                        :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_spi0_m_ctrlr1(val) ((rs_cpu_sys_spi0_m_ctrlr1*)&(val))



#define CPU_SYS_SPI0_M_SSIENR                                            (HV_SPI0_BASE_ADDRESS + 0x008)

#define CPU_SYS_SPI0_M_SSIENR_struct                                     rs_cpu_sys_spi0_m_ssienr

typedef struct _rs_cpu_sys_spi0_m_ssienr  rs_cpu_sys_spi0_m_ssienr;
struct _rs_cpu_sys_spi0_m_ssienr {
    unsigned int SSI_EN                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_m_ssienr(val) ((rs_cpu_sys_spi0_m_ssienr*)&(val))



#define CPU_SYS_SPI0_M_MWCR                                              (HV_SPI0_BASE_ADDRESS + 0x00C)

#define CPU_SYS_SPI0_M_MWCR_struct                                       rs_cpu_sys_spi0_m_mwcr

typedef struct _rs_cpu_sys_spi0_m_mwcr  rs_cpu_sys_spi0_m_mwcr;
struct _rs_cpu_sys_spi0_m_mwcr {
    unsigned int MWMOD                                      : 1;
    unsigned int MDD                                        : 1;
    unsigned int MHS                                        : 1;
    unsigned int reserved                                   :29;
};
#define cpu_sys_spi0_m_mwcr(val) ((rs_cpu_sys_spi0_m_mwcr*)&(val))



#define CPU_SYS_SPI0_M_SER                                               (HV_SPI0_BASE_ADDRESS + 0x010)

#define CPU_SYS_SPI0_M_SER_struct                                        rs_cpu_sys_spi0_m_ser

typedef struct _rs_cpu_sys_spi0_m_ser  rs_cpu_sys_spi0_m_ser;
struct _rs_cpu_sys_spi0_m_ser {
    unsigned int SER                                        : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_m_ser(val) ((rs_cpu_sys_spi0_m_ser*)&(val))



#define CPU_SYS_SPI0_M_BAUDR                                             (HV_SPI0_BASE_ADDRESS + 0x014)

#define CPU_SYS_SPI0_M_BAUDR_struct                                      rs_cpu_sys_spi0_m_baudr

typedef struct _rs_cpu_sys_spi0_m_baudr  rs_cpu_sys_spi0_m_baudr;
struct _rs_cpu_sys_spi0_m_baudr {
    unsigned int SCKDV                                      :16;
    unsigned int reserved                                   :16;
};
#define cpu_sys_spi0_m_baudr(val) ((rs_cpu_sys_spi0_m_baudr*)&(val))



#define CPU_SYS_SPI0_M_TXFTLR                                            (HV_SPI0_BASE_ADDRESS + 0x018)

#define CPU_SYS_SPI0_M_TXFTLR_struct                                     rs_cpu_sys_spi0_m_txftlr

typedef struct _rs_cpu_sys_spi0_m_txftlr  rs_cpu_sys_spi0_m_txftlr;
struct _rs_cpu_sys_spi0_m_txftlr {
    unsigned int TFT                                        : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_m_txftlr(val) ((rs_cpu_sys_spi0_m_txftlr*)&(val))



#define CPU_SYS_SPI0_M_RXFTLR                                            (HV_SPI0_BASE_ADDRESS + 0x01C)

#define CPU_SYS_SPI0_M_RXFTLR_struct                                     rs_cpu_sys_spi0_m_rxftlr

typedef struct _rs_cpu_sys_spi0_m_rxftlr  rs_cpu_sys_spi0_m_rxftlr;
struct _rs_cpu_sys_spi0_m_rxftlr {
    unsigned int RFT                                        : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_m_rxftlr(val) ((rs_cpu_sys_spi0_m_rxftlr*)&(val))



#define CPU_SYS_SPI0_M_TXFLR                                             (HV_SPI0_BASE_ADDRESS + 0x020)

#define CPU_SYS_SPI0_M_TXFLR_struct                                      rs_cpu_sys_spi0_m_txflr

typedef struct _rs_cpu_sys_spi0_m_txflr  rs_cpu_sys_spi0_m_txflr;
struct _rs_cpu_sys_spi0_m_txflr {
    unsigned int TXTFL                                      : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_spi0_m_txflr(val) ((rs_cpu_sys_spi0_m_txflr*)&(val))



#define CPU_SYS_SPI0_M_RXFLR                                             (HV_SPI0_BASE_ADDRESS + 0x024)

#define CPU_SYS_SPI0_M_RXFLR_struct                                      rs_cpu_sys_spi0_m_rxflr

typedef struct _rs_cpu_sys_spi0_m_rxflr  rs_cpu_sys_spi0_m_rxflr;
struct _rs_cpu_sys_spi0_m_rxflr {
    unsigned int RXTFL                                      : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_spi0_m_rxflr(val) ((rs_cpu_sys_spi0_m_rxflr*)&(val))



#define CPU_SYS_SPI0_M_SR                                                (HV_SPI0_BASE_ADDRESS + 0x028)

#define CPU_SYS_SPI0_M_SR_struct                                         rs_cpu_sys_spi0_m_sr

typedef struct _rs_cpu_sys_spi0_m_sr  rs_cpu_sys_spi0_m_sr;
struct _rs_cpu_sys_spi0_m_sr {
    unsigned int BUSY                                       : 1;
    unsigned int TFNF                                       : 1;
    unsigned int TFE                                        : 1;
    unsigned int RFNE                                       : 1;
    unsigned int RFF                                        : 1;
    unsigned int TXE                                        : 1;
    unsigned int DCOL                                       : 1;
    unsigned int reserved                                   :25;
};
#define cpu_sys_spi0_m_sr(val) ((rs_cpu_sys_spi0_m_sr*)&(val))



#define CPU_SYS_SPI0_M_IMR                                               (HV_SPI0_BASE_ADDRESS + 0x02C)

#define CPU_SYS_SPI0_M_IMR_struct                                        rs_cpu_sys_spi0_m_imr

typedef struct _rs_cpu_sys_spi0_m_imr  rs_cpu_sys_spi0_m_imr;
struct _rs_cpu_sys_spi0_m_imr {
    unsigned int TXEIM                                      : 1;
    unsigned int TXOIM                                      : 1;
    unsigned int RXUIM                                      : 1;
    unsigned int RXOIM                                      : 1;
    unsigned int RXFIM                                      : 1;
    unsigned int MSTIM                                      : 1;
    unsigned int reserved                                   :26;
};
#define cpu_sys_spi0_m_imr(val) ((rs_cpu_sys_spi0_m_imr*)&(val))



#define CPU_SYS_SPI0_M_ISR                                               (HV_SPI0_BASE_ADDRESS + 0x030)

#define CPU_SYS_SPI0_M_ISR_struct                                        rs_cpu_sys_spi0_m_isr

typedef struct _rs_cpu_sys_spi0_m_isr  rs_cpu_sys_spi0_m_isr;
struct _rs_cpu_sys_spi0_m_isr {
    unsigned int TXEIS                                      : 1;
    unsigned int TXOIS                                      : 1;
    unsigned int RXUIS                                      : 1;
    unsigned int RXOIS                                      : 1;
    unsigned int RXFIS                                      : 1;
    unsigned int MSTIS                                      : 1;
    unsigned int reserved                                   :26;
};
#define cpu_sys_spi0_m_isr(val) ((rs_cpu_sys_spi0_m_isr*)&(val))



#define CPU_SYS_SPI0_M_RISR                                              (HV_SPI0_BASE_ADDRESS + 0x034)

#define CPU_SYS_SPI0_M_RISR_struct                                       rs_cpu_sys_spi0_m_risr

typedef struct _rs_cpu_sys_spi0_m_risr  rs_cpu_sys_spi0_m_risr;
struct _rs_cpu_sys_spi0_m_risr {
    unsigned int TXEIR                                      : 1;
    unsigned int TXOIR                                      : 1;
    unsigned int RXUIR                                      : 1;
    unsigned int RXOIR                                      : 1;
    unsigned int RXFIR                                      : 1;
    unsigned int MSTIR                                      : 1;
    unsigned int reserved                                   :26;
};
#define cpu_sys_spi0_m_risr(val) ((rs_cpu_sys_spi0_m_risr*)&(val))



#define CPU_SYS_SPI0_M_TXOICR                                            (HV_SPI0_BASE_ADDRESS + 0x038)

#define CPU_SYS_SPI0_M_TXOICR_struct                                     rs_cpu_sys_spi0_m_txoicr

typedef struct _rs_cpu_sys_spi0_m_txoicr  rs_cpu_sys_spi0_m_txoicr;
struct _rs_cpu_sys_spi0_m_txoicr {
    unsigned int TXOICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_m_txoicr(val) ((rs_cpu_sys_spi0_m_txoicr*)&(val))



#define CPU_SYS_SPI0_M_RXOICR                                            (HV_SPI0_BASE_ADDRESS + 0x03C)

#define CPU_SYS_SPI0_M_RXOICR_struct                                     rs_cpu_sys_spi0_m_rxoicr

typedef struct _rs_cpu_sys_spi0_m_rxoicr  rs_cpu_sys_spi0_m_rxoicr;
struct _rs_cpu_sys_spi0_m_rxoicr {
    unsigned int RXOICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_m_rxoicr(val) ((rs_cpu_sys_spi0_m_rxoicr*)&(val))



#define CPU_SYS_SPI0_M_RXUICR                                            (HV_SPI0_BASE_ADDRESS + 0x040)

#define CPU_SYS_SPI0_M_RXUICR_struct                                     rs_cpu_sys_spi0_m_rxuicr

typedef struct _rs_cpu_sys_spi0_m_rxuicr  rs_cpu_sys_spi0_m_rxuicr;
struct _rs_cpu_sys_spi0_m_rxuicr {
    unsigned int RXUICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_m_rxuicr(val) ((rs_cpu_sys_spi0_m_rxuicr*)&(val))



#define CPU_SYS_SPI0_M_MSTICR                                            (HV_SPI0_BASE_ADDRESS + 0x044)

#define CPU_SYS_SPI0_M_MSTICR_struct                                     rs_cpu_sys_spi0_m_msticr

typedef struct _rs_cpu_sys_spi0_m_msticr  rs_cpu_sys_spi0_m_msticr;
struct _rs_cpu_sys_spi0_m_msticr {
    unsigned int MSTICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_m_msticr(val) ((rs_cpu_sys_spi0_m_msticr*)&(val))



#define CPU_SYS_SPI0_M_ICR                                               (HV_SPI0_BASE_ADDRESS + 0x048)

#define CPU_SYS_SPI0_M_ICR_struct                                        rs_cpu_sys_spi0_m_icr

typedef struct _rs_cpu_sys_spi0_m_icr  rs_cpu_sys_spi0_m_icr;
struct _rs_cpu_sys_spi0_m_icr {
    unsigned int ICR                                        : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_m_icr(val) ((rs_cpu_sys_spi0_m_icr*)&(val))



#define CPU_SYS_SPI0_M_DMACR                                             (HV_SPI0_BASE_ADDRESS + 0x04C)

#define CPU_SYS_SPI0_M_DMACR_struct                                      rs_cpu_sys_spi0_m_dmacr

typedef struct _rs_cpu_sys_spi0_m_dmacr  rs_cpu_sys_spi0_m_dmacr;
struct _rs_cpu_sys_spi0_m_dmacr {
    unsigned int RDMAE                                      : 1;
    unsigned int TDMAE                                      : 1;
    unsigned int reserved                                   :30;
};
#define cpu_sys_spi0_m_dmacr(val) ((rs_cpu_sys_spi0_m_dmacr*)&(val))



#define CPU_SYS_SPI0_M_DMATDLR                                           (HV_SPI0_BASE_ADDRESS + 0x050)

#define CPU_SYS_SPI0_M_DMATDLR_struct                                    rs_cpu_sys_spi0_m_dmatdlr

typedef struct _rs_cpu_sys_spi0_m_dmatdlr  rs_cpu_sys_spi0_m_dmatdlr;
struct _rs_cpu_sys_spi0_m_dmatdlr {
    unsigned int DMATDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_m_dmatdlr(val) ((rs_cpu_sys_spi0_m_dmatdlr*)&(val))



#define CPU_SYS_SPI0_M_DMARDLR                                           (HV_SPI0_BASE_ADDRESS + 0x054)

#define CPU_SYS_SPI0_M_DMARDLR_struct                                    rs_cpu_sys_spi0_m_dmardlr

typedef struct _rs_cpu_sys_spi0_m_dmardlr  rs_cpu_sys_spi0_m_dmardlr;
struct _rs_cpu_sys_spi0_m_dmardlr {
    unsigned int DMARDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_m_dmardlr(val) ((rs_cpu_sys_spi0_m_dmardlr*)&(val))



#define CPU_SYS_SPI0_M_IDR                                               (HV_SPI0_BASE_ADDRESS + 0x058)

#define CPU_SYS_SPI0_M_IDR_struct                                        rs_cpu_sys_spi0_m_idr

typedef struct _rs_cpu_sys_spi0_m_idr  rs_cpu_sys_spi0_m_idr;
struct _rs_cpu_sys_spi0_m_idr {
    unsigned int IDCODE                                     :32;
};
#define cpu_sys_spi0_m_idr(val) ((rs_cpu_sys_spi0_m_idr*)&(val))



#define CPU_SYS_SPI0_M_SSI_VERSION_ID                                    (HV_SPI0_BASE_ADDRESS + 0x05C)

#define CPU_SYS_SPI0_M_SSI_VERSION_ID_struct                             rs_cpu_sys_spi0_m_ssi_version_id

typedef struct _rs_cpu_sys_spi0_m_ssi_version_id  rs_cpu_sys_spi0_m_ssi_version_id;
struct _rs_cpu_sys_spi0_m_ssi_version_id {
    unsigned int SSI_COMP_VERSION                           :32;
};
#define cpu_sys_spi0_m_ssi_version_id(val) ((rs_cpu_sys_spi0_m_ssi_version_id*)&(val))



#define CPU_SYS_SPI0_M_DR0                                               (HV_SPI0_BASE_ADDRESS + 0x060)

#define CPU_SYS_SPI0_M_DR0_struct                                        rs_cpu_sys_spi0_m_dr0

typedef struct _rs_cpu_sys_spi0_m_dr0  rs_cpu_sys_spi0_m_dr0;
struct _rs_cpu_sys_spi0_m_dr0 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr0(val) ((rs_cpu_sys_spi0_m_dr0*)&(val))



#define CPU_SYS_SPI0_M_DR1                                               (HV_SPI0_BASE_ADDRESS + 0x064)

#define CPU_SYS_SPI0_M_DR1_struct                                        rs_cpu_sys_spi0_m_dr1

typedef struct _rs_cpu_sys_spi0_m_dr1  rs_cpu_sys_spi0_m_dr1;
struct _rs_cpu_sys_spi0_m_dr1 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr1(val) ((rs_cpu_sys_spi0_m_dr1*)&(val))



#define CPU_SYS_SPI0_M_DR2                                               (HV_SPI0_BASE_ADDRESS + 0x068)

#define CPU_SYS_SPI0_M_DR2_struct                                        rs_cpu_sys_spi0_m_dr2

typedef struct _rs_cpu_sys_spi0_m_dr2  rs_cpu_sys_spi0_m_dr2;
struct _rs_cpu_sys_spi0_m_dr2 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr2(val) ((rs_cpu_sys_spi0_m_dr2*)&(val))



#define CPU_SYS_SPI0_M_DR3                                               (HV_SPI0_BASE_ADDRESS + 0x06C)

#define CPU_SYS_SPI0_M_DR3_struct                                        rs_cpu_sys_spi0_m_dr3

typedef struct _rs_cpu_sys_spi0_m_dr3  rs_cpu_sys_spi0_m_dr3;
struct _rs_cpu_sys_spi0_m_dr3 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr3(val) ((rs_cpu_sys_spi0_m_dr3*)&(val))



#define CPU_SYS_SPI0_M_DR4                                               (HV_SPI0_BASE_ADDRESS + 0x070)

#define CPU_SYS_SPI0_M_DR4_struct                                        rs_cpu_sys_spi0_m_dr4

typedef struct _rs_cpu_sys_spi0_m_dr4  rs_cpu_sys_spi0_m_dr4;
struct _rs_cpu_sys_spi0_m_dr4 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr4(val) ((rs_cpu_sys_spi0_m_dr4*)&(val))



#define CPU_SYS_SPI0_M_DR5                                               (HV_SPI0_BASE_ADDRESS + 0x074)

#define CPU_SYS_SPI0_M_DR5_struct                                        rs_cpu_sys_spi0_m_dr5

typedef struct _rs_cpu_sys_spi0_m_dr5  rs_cpu_sys_spi0_m_dr5;
struct _rs_cpu_sys_spi0_m_dr5 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr5(val) ((rs_cpu_sys_spi0_m_dr5*)&(val))



#define CPU_SYS_SPI0_M_DR6                                               (HV_SPI0_BASE_ADDRESS + 0x078)

#define CPU_SYS_SPI0_M_DR6_struct                                        rs_cpu_sys_spi0_m_dr6

typedef struct _rs_cpu_sys_spi0_m_dr6  rs_cpu_sys_spi0_m_dr6;
struct _rs_cpu_sys_spi0_m_dr6 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr6(val) ((rs_cpu_sys_spi0_m_dr6*)&(val))



#define CPU_SYS_SPI0_M_DR7                                               (HV_SPI0_BASE_ADDRESS + 0x07C)

#define CPU_SYS_SPI0_M_DR7_struct                                        rs_cpu_sys_spi0_m_dr7

typedef struct _rs_cpu_sys_spi0_m_dr7  rs_cpu_sys_spi0_m_dr7;
struct _rs_cpu_sys_spi0_m_dr7 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr7(val) ((rs_cpu_sys_spi0_m_dr7*)&(val))



#define CPU_SYS_SPI0_M_DR8                                               (HV_SPI0_BASE_ADDRESS + 0x080)

#define CPU_SYS_SPI0_M_DR8_struct                                        rs_cpu_sys_spi0_m_dr8

typedef struct _rs_cpu_sys_spi0_m_dr8  rs_cpu_sys_spi0_m_dr8;
struct _rs_cpu_sys_spi0_m_dr8 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr8(val) ((rs_cpu_sys_spi0_m_dr8*)&(val))



#define CPU_SYS_SPI0_M_DR9                                               (HV_SPI0_BASE_ADDRESS + 0x084)

#define CPU_SYS_SPI0_M_DR9_struct                                        rs_cpu_sys_spi0_m_dr9

typedef struct _rs_cpu_sys_spi0_m_dr9  rs_cpu_sys_spi0_m_dr9;
struct _rs_cpu_sys_spi0_m_dr9 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr9(val) ((rs_cpu_sys_spi0_m_dr9*)&(val))



#define CPU_SYS_SPI0_M_DR10                                              (HV_SPI0_BASE_ADDRESS + 0x088)

#define CPU_SYS_SPI0_M_DR10_struct                                       rs_cpu_sys_spi0_m_dr10

typedef struct _rs_cpu_sys_spi0_m_dr10  rs_cpu_sys_spi0_m_dr10;
struct _rs_cpu_sys_spi0_m_dr10 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr10(val) ((rs_cpu_sys_spi0_m_dr10*)&(val))



#define CPU_SYS_SPI0_M_DR11                                              (HV_SPI0_BASE_ADDRESS + 0x08C)

#define CPU_SYS_SPI0_M_DR11_struct                                       rs_cpu_sys_spi0_m_dr11

typedef struct _rs_cpu_sys_spi0_m_dr11  rs_cpu_sys_spi0_m_dr11;
struct _rs_cpu_sys_spi0_m_dr11 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr11(val) ((rs_cpu_sys_spi0_m_dr11*)&(val))



#define CPU_SYS_SPI0_M_DR12                                              (HV_SPI0_BASE_ADDRESS + 0x090)

#define CPU_SYS_SPI0_M_DR12_struct                                       rs_cpu_sys_spi0_m_dr12

typedef struct _rs_cpu_sys_spi0_m_dr12  rs_cpu_sys_spi0_m_dr12;
struct _rs_cpu_sys_spi0_m_dr12 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr12(val) ((rs_cpu_sys_spi0_m_dr12*)&(val))



#define CPU_SYS_SPI0_M_DR13                                              (HV_SPI0_BASE_ADDRESS + 0x094)

#define CPU_SYS_SPI0_M_DR13_struct                                       rs_cpu_sys_spi0_m_dr13

typedef struct _rs_cpu_sys_spi0_m_dr13  rs_cpu_sys_spi0_m_dr13;
struct _rs_cpu_sys_spi0_m_dr13 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr13(val) ((rs_cpu_sys_spi0_m_dr13*)&(val))



#define CPU_SYS_SPI0_M_DR14                                              (HV_SPI0_BASE_ADDRESS + 0x098)

#define CPU_SYS_SPI0_M_DR14_struct                                       rs_cpu_sys_spi0_m_dr14

typedef struct _rs_cpu_sys_spi0_m_dr14  rs_cpu_sys_spi0_m_dr14;
struct _rs_cpu_sys_spi0_m_dr14 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr14(val) ((rs_cpu_sys_spi0_m_dr14*)&(val))



#define CPU_SYS_SPI0_M_DR15                                              (HV_SPI0_BASE_ADDRESS + 0x09C)

#define CPU_SYS_SPI0_M_DR15_struct                                       rs_cpu_sys_spi0_m_dr15

typedef struct _rs_cpu_sys_spi0_m_dr15  rs_cpu_sys_spi0_m_dr15;
struct _rs_cpu_sys_spi0_m_dr15 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr15(val) ((rs_cpu_sys_spi0_m_dr15*)&(val))



#define CPU_SYS_SPI0_M_DR16                                              (HV_SPI0_BASE_ADDRESS + 0x0A0)

#define CPU_SYS_SPI0_M_DR16_struct                                       rs_cpu_sys_spi0_m_dr16

typedef struct _rs_cpu_sys_spi0_m_dr16  rs_cpu_sys_spi0_m_dr16;
struct _rs_cpu_sys_spi0_m_dr16 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr16(val) ((rs_cpu_sys_spi0_m_dr16*)&(val))



#define CPU_SYS_SPI0_M_DR17                                              (HV_SPI0_BASE_ADDRESS + 0x0A4)

#define CPU_SYS_SPI0_M_DR17_struct                                       rs_cpu_sys_spi0_m_dr17

typedef struct _rs_cpu_sys_spi0_m_dr17  rs_cpu_sys_spi0_m_dr17;
struct _rs_cpu_sys_spi0_m_dr17 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr17(val) ((rs_cpu_sys_spi0_m_dr17*)&(val))



#define CPU_SYS_SPI0_M_DR18                                              (HV_SPI0_BASE_ADDRESS + 0x0A8)

#define CPU_SYS_SPI0_M_DR18_struct                                       rs_cpu_sys_spi0_m_dr18

typedef struct _rs_cpu_sys_spi0_m_dr18  rs_cpu_sys_spi0_m_dr18;
struct _rs_cpu_sys_spi0_m_dr18 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr18(val) ((rs_cpu_sys_spi0_m_dr18*)&(val))



#define CPU_SYS_SPI0_M_DR19                                              (HV_SPI0_BASE_ADDRESS + 0x0AC)

#define CPU_SYS_SPI0_M_DR19_struct                                       rs_cpu_sys_spi0_m_dr19

typedef struct _rs_cpu_sys_spi0_m_dr19  rs_cpu_sys_spi0_m_dr19;
struct _rs_cpu_sys_spi0_m_dr19 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr19(val) ((rs_cpu_sys_spi0_m_dr19*)&(val))



#define CPU_SYS_SPI0_M_DR20                                              (HV_SPI0_BASE_ADDRESS + 0x0B0)

#define CPU_SYS_SPI0_M_DR20_struct                                       rs_cpu_sys_spi0_m_dr20

typedef struct _rs_cpu_sys_spi0_m_dr20  rs_cpu_sys_spi0_m_dr20;
struct _rs_cpu_sys_spi0_m_dr20 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr20(val) ((rs_cpu_sys_spi0_m_dr20*)&(val))



#define CPU_SYS_SPI0_M_DR21                                              (HV_SPI0_BASE_ADDRESS + 0x0B4)

#define CPU_SYS_SPI0_M_DR21_struct                                       rs_cpu_sys_spi0_m_dr21

typedef struct _rs_cpu_sys_spi0_m_dr21  rs_cpu_sys_spi0_m_dr21;
struct _rs_cpu_sys_spi0_m_dr21 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr21(val) ((rs_cpu_sys_spi0_m_dr21*)&(val))



#define CPU_SYS_SPI0_M_DR22                                              (HV_SPI0_BASE_ADDRESS + 0x0B8)

#define CPU_SYS_SPI0_M_DR22_struct                                       rs_cpu_sys_spi0_m_dr22

typedef struct _rs_cpu_sys_spi0_m_dr22  rs_cpu_sys_spi0_m_dr22;
struct _rs_cpu_sys_spi0_m_dr22 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr22(val) ((rs_cpu_sys_spi0_m_dr22*)&(val))



#define CPU_SYS_SPI0_M_DR23                                              (HV_SPI0_BASE_ADDRESS + 0x0BC)

#define CPU_SYS_SPI0_M_DR23_struct                                       rs_cpu_sys_spi0_m_dr23

typedef struct _rs_cpu_sys_spi0_m_dr23  rs_cpu_sys_spi0_m_dr23;
struct _rs_cpu_sys_spi0_m_dr23 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr23(val) ((rs_cpu_sys_spi0_m_dr23*)&(val))



#define CPU_SYS_SPI0_M_DR24                                              (HV_SPI0_BASE_ADDRESS + 0x0C0)

#define CPU_SYS_SPI0_M_DR24_struct                                       rs_cpu_sys_spi0_m_dr24

typedef struct _rs_cpu_sys_spi0_m_dr24  rs_cpu_sys_spi0_m_dr24;
struct _rs_cpu_sys_spi0_m_dr24 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr24(val) ((rs_cpu_sys_spi0_m_dr24*)&(val))



#define CPU_SYS_SPI0_M_DR25                                              (HV_SPI0_BASE_ADDRESS + 0x0C4)

#define CPU_SYS_SPI0_M_DR25_struct                                       rs_cpu_sys_spi0_m_dr25

typedef struct _rs_cpu_sys_spi0_m_dr25  rs_cpu_sys_spi0_m_dr25;
struct _rs_cpu_sys_spi0_m_dr25 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr25(val) ((rs_cpu_sys_spi0_m_dr25*)&(val))



#define CPU_SYS_SPI0_M_DR26                                              (HV_SPI0_BASE_ADDRESS + 0x0C8)

#define CPU_SYS_SPI0_M_DR26_struct                                       rs_cpu_sys_spi0_m_dr26

typedef struct _rs_cpu_sys_spi0_m_dr26  rs_cpu_sys_spi0_m_dr26;
struct _rs_cpu_sys_spi0_m_dr26 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr26(val) ((rs_cpu_sys_spi0_m_dr26*)&(val))



#define CPU_SYS_SPI0_M_DR27                                              (HV_SPI0_BASE_ADDRESS + 0x0CC)

#define CPU_SYS_SPI0_M_DR27_struct                                       rs_cpu_sys_spi0_m_dr27

typedef struct _rs_cpu_sys_spi0_m_dr27  rs_cpu_sys_spi0_m_dr27;
struct _rs_cpu_sys_spi0_m_dr27 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr27(val) ((rs_cpu_sys_spi0_m_dr27*)&(val))



#define CPU_SYS_SPI0_M_DR28                                              (HV_SPI0_BASE_ADDRESS + 0x0D0)

#define CPU_SYS_SPI0_M_DR28_struct                                       rs_cpu_sys_spi0_m_dr28

typedef struct _rs_cpu_sys_spi0_m_dr28  rs_cpu_sys_spi0_m_dr28;
struct _rs_cpu_sys_spi0_m_dr28 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr28(val) ((rs_cpu_sys_spi0_m_dr28*)&(val))



#define CPU_SYS_SPI0_M_DR29                                              (HV_SPI0_BASE_ADDRESS + 0x0D4)

#define CPU_SYS_SPI0_M_DR29_struct                                       rs_cpu_sys_spi0_m_dr29

typedef struct _rs_cpu_sys_spi0_m_dr29  rs_cpu_sys_spi0_m_dr29;
struct _rs_cpu_sys_spi0_m_dr29 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr29(val) ((rs_cpu_sys_spi0_m_dr29*)&(val))



#define CPU_SYS_SPI0_M_DR30                                              (HV_SPI0_BASE_ADDRESS + 0x0D8)

#define CPU_SYS_SPI0_M_DR30_struct                                       rs_cpu_sys_spi0_m_dr30

typedef struct _rs_cpu_sys_spi0_m_dr30  rs_cpu_sys_spi0_m_dr30;
struct _rs_cpu_sys_spi0_m_dr30 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr30(val) ((rs_cpu_sys_spi0_m_dr30*)&(val))



#define CPU_SYS_SPI0_M_DR31                                              (HV_SPI0_BASE_ADDRESS + 0x0DC)

#define CPU_SYS_SPI0_M_DR31_struct                                       rs_cpu_sys_spi0_m_dr31

typedef struct _rs_cpu_sys_spi0_m_dr31  rs_cpu_sys_spi0_m_dr31;
struct _rs_cpu_sys_spi0_m_dr31 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr31(val) ((rs_cpu_sys_spi0_m_dr31*)&(val))



#define CPU_SYS_SPI0_M_DR32                                              (HV_SPI0_BASE_ADDRESS + 0x0E0)

#define CPU_SYS_SPI0_M_DR32_struct                                       rs_cpu_sys_spi0_m_dr32

typedef struct _rs_cpu_sys_spi0_m_dr32  rs_cpu_sys_spi0_m_dr32;
struct _rs_cpu_sys_spi0_m_dr32 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr32(val) ((rs_cpu_sys_spi0_m_dr32*)&(val))



#define CPU_SYS_SPI0_M_DR33                                              (HV_SPI0_BASE_ADDRESS + 0x0E4)

#define CPU_SYS_SPI0_M_DR33_struct                                       rs_cpu_sys_spi0_m_dr33

typedef struct _rs_cpu_sys_spi0_m_dr33  rs_cpu_sys_spi0_m_dr33;
struct _rs_cpu_sys_spi0_m_dr33 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr33(val) ((rs_cpu_sys_spi0_m_dr33*)&(val))



#define CPU_SYS_SPI0_M_DR34                                              (HV_SPI0_BASE_ADDRESS + 0x0E8)

#define CPU_SYS_SPI0_M_DR34_struct                                       rs_cpu_sys_spi0_m_dr34

typedef struct _rs_cpu_sys_spi0_m_dr34  rs_cpu_sys_spi0_m_dr34;
struct _rs_cpu_sys_spi0_m_dr34 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr34(val) ((rs_cpu_sys_spi0_m_dr34*)&(val))



#define CPU_SYS_SPI0_M_DR35                                              (HV_SPI0_BASE_ADDRESS + 0x0EC)

#define CPU_SYS_SPI0_M_DR35_struct                                       rs_cpu_sys_spi0_m_dr35

typedef struct _rs_cpu_sys_spi0_m_dr35  rs_cpu_sys_spi0_m_dr35;
struct _rs_cpu_sys_spi0_m_dr35 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_m_dr35(val) ((rs_cpu_sys_spi0_m_dr35*)&(val))



#define CPU_SYS_SPI0_M_RX_SAMPLE_DLY                                     (HV_SPI0_BASE_ADDRESS + 0x0F0)

#define CPU_SYS_SPI0_M_RX_SAMPLE_DLY_struct                              rs_cpu_sys_spi0_m_rx_sample_dly

typedef struct _rs_cpu_sys_spi0_m_rx_sample_dly  rs_cpu_sys_spi0_m_rx_sample_dly;
struct _rs_cpu_sys_spi0_m_rx_sample_dly {
    unsigned int RSD                                        : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_spi0_m_rx_sample_dly(val) ((rs_cpu_sys_spi0_m_rx_sample_dly*)&(val))



#define CPU_SYS_SPI0_S_CTRLR0                                            (HV_SPI0_BASE_ADDRESS + 0x100)

#define CPU_SYS_SPI0_S_CTRLR0_struct                                     rs_cpu_sys_spi0_s_ctrlr0

typedef struct _rs_cpu_sys_spi0_s_ctrlr0  rs_cpu_sys_spi0_s_ctrlr0;
struct _rs_cpu_sys_spi0_s_ctrlr0 {
    unsigned int DFS                                        : 4;
    unsigned int FRF                                        : 2;
    unsigned int SCPH                                       : 1;
    unsigned int SCPOL                                      : 1;
    unsigned int TMOD                                       : 2;
    unsigned int SLV_OE                                     : 1;
    unsigned int SRL                                        : 1;
    unsigned int CFS                                        : 4;
    unsigned int DFS_32                                     : 5;
    unsigned int SPI_FRF                                    : 2;
    unsigned int reserved                                   : 1;
    unsigned int SSTE                                       : 1;
    unsigned int reserved_1                                 : 7;
};
#define cpu_sys_spi0_s_ctrlr0(val) ((rs_cpu_sys_spi0_s_ctrlr0*)&(val))



#define CPU_SYS_SPI0_S_SSIENR                                            (HV_SPI0_BASE_ADDRESS + 0x108)

#define CPU_SYS_SPI0_S_SSIENR_struct                                     rs_cpu_sys_spi0_s_ssienr

typedef struct _rs_cpu_sys_spi0_s_ssienr  rs_cpu_sys_spi0_s_ssienr;
struct _rs_cpu_sys_spi0_s_ssienr {
    unsigned int SSI_EN                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_s_ssienr(val) ((rs_cpu_sys_spi0_s_ssienr*)&(val))



#define CPU_SYS_SPI0_S_MWCR                                              (HV_SPI0_BASE_ADDRESS + 0x10C)

#define CPU_SYS_SPI0_S_MWCR_struct                                       rs_cpu_sys_spi0_s_mwcr

typedef struct _rs_cpu_sys_spi0_s_mwcr  rs_cpu_sys_spi0_s_mwcr;
struct _rs_cpu_sys_spi0_s_mwcr {
    unsigned int MWMOD                                      : 1;
    unsigned int MDD                                        : 1;
    unsigned int MHS                                        : 1;
    unsigned int reserved                                   :29;
};
#define cpu_sys_spi0_s_mwcr(val) ((rs_cpu_sys_spi0_s_mwcr*)&(val))



#define CPU_SYS_SPI0_S_TXFTLR                                            (HV_SPI0_BASE_ADDRESS + 0x118)

#define CPU_SYS_SPI0_S_TXFTLR_struct                                     rs_cpu_sys_spi0_s_txftlr

typedef struct _rs_cpu_sys_spi0_s_txftlr  rs_cpu_sys_spi0_s_txftlr;
struct _rs_cpu_sys_spi0_s_txftlr {
    unsigned int TFT                                        : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_s_txftlr(val) ((rs_cpu_sys_spi0_s_txftlr*)&(val))



#define CPU_SYS_SPI0_S_RXFTLR                                            (HV_SPI0_BASE_ADDRESS + 0x11C)

#define CPU_SYS_SPI0_S_RXFTLR_struct                                     rs_cpu_sys_spi0_s_rxftlr

typedef struct _rs_cpu_sys_spi0_s_rxftlr  rs_cpu_sys_spi0_s_rxftlr;
struct _rs_cpu_sys_spi0_s_rxftlr {
    unsigned int RFT                                        : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_s_rxftlr(val) ((rs_cpu_sys_spi0_s_rxftlr*)&(val))



#define CPU_SYS_SPI0_S_TXFLR                                             (HV_SPI0_BASE_ADDRESS + 0x120)

#define CPU_SYS_SPI0_S_TXFLR_struct                                      rs_cpu_sys_spi0_s_txflr

typedef struct _rs_cpu_sys_spi0_s_txflr  rs_cpu_sys_spi0_s_txflr;
struct _rs_cpu_sys_spi0_s_txflr {
    unsigned int TXTFL                                      : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_spi0_s_txflr(val) ((rs_cpu_sys_spi0_s_txflr*)&(val))



#define CPU_SYS_SPI0_S_RXFLR                                             (HV_SPI0_BASE_ADDRESS + 0x124)

#define CPU_SYS_SPI0_S_RXFLR_struct                                      rs_cpu_sys_spi0_s_rxflr

typedef struct _rs_cpu_sys_spi0_s_rxflr  rs_cpu_sys_spi0_s_rxflr;
struct _rs_cpu_sys_spi0_s_rxflr {
    unsigned int RXTFL                                      : 5;
    unsigned int reserved                                   :27;
};
#define cpu_sys_spi0_s_rxflr(val) ((rs_cpu_sys_spi0_s_rxflr*)&(val))



#define CPU_SYS_SPI0_S_SR                                                (HV_SPI0_BASE_ADDRESS + 0x128)

#define CPU_SYS_SPI0_S_SR_struct                                         rs_cpu_sys_spi0_s_sr

typedef struct _rs_cpu_sys_spi0_s_sr  rs_cpu_sys_spi0_s_sr;
struct _rs_cpu_sys_spi0_s_sr {
    unsigned int BUSY                                       : 1;
    unsigned int TFNF                                       : 1;
    unsigned int TFE                                        : 1;
    unsigned int RFNE                                       : 1;
    unsigned int RFF                                        : 1;
    unsigned int TXE                                        : 1;
    unsigned int DCOL                                       : 1;
    unsigned int reserved                                   :25;
};
#define cpu_sys_spi0_s_sr(val) ((rs_cpu_sys_spi0_s_sr*)&(val))



#define CPU_SYS_SPI0_S_IMR                                               (HV_SPI0_BASE_ADDRESS + 0x12C)

#define CPU_SYS_SPI0_S_IMR_struct                                        rs_cpu_sys_spi0_s_imr

typedef struct _rs_cpu_sys_spi0_s_imr  rs_cpu_sys_spi0_s_imr;
struct _rs_cpu_sys_spi0_s_imr {
    unsigned int TXEIM                                      : 1;
    unsigned int TXOIM                                      : 1;
    unsigned int RXUIM                                      : 1;
    unsigned int RXOIM                                      : 1;
    unsigned int RXFIM                                      : 1;
    unsigned int MSTIM                                      : 1;
    unsigned int reserved                                   :26;
};
#define cpu_sys_spi0_s_imr(val) ((rs_cpu_sys_spi0_s_imr*)&(val))



#define CPU_SYS_SPI0_S_ISR                                               (HV_SPI0_BASE_ADDRESS + 0x130)

#define CPU_SYS_SPI0_S_ISR_struct                                        rs_cpu_sys_spi0_s_isr

typedef struct _rs_cpu_sys_spi0_s_isr  rs_cpu_sys_spi0_s_isr;
struct _rs_cpu_sys_spi0_s_isr {
    unsigned int TXEIS                                      : 1;
    unsigned int TXOIS                                      : 1;
    unsigned int RXUIS                                      : 1;
    unsigned int RXOIS                                      : 1;
    unsigned int RXFIS                                      : 1;
    unsigned int MSTIS                                      : 1;
    unsigned int reserved                                   :26;
};
#define cpu_sys_spi0_s_isr(val) ((rs_cpu_sys_spi0_s_isr*)&(val))



#define CPU_SYS_SPI0_S_RISR                                              (HV_SPI0_BASE_ADDRESS + 0x134)

#define CPU_SYS_SPI0_S_RISR_struct                                       rs_cpu_sys_spi0_s_risr

typedef struct _rs_cpu_sys_spi0_s_risr  rs_cpu_sys_spi0_s_risr;
struct _rs_cpu_sys_spi0_s_risr {
    unsigned int TXEIR                                      : 1;
    unsigned int TXOIR                                      : 1;
    unsigned int RXUIR                                      : 1;
    unsigned int RXOIR                                      : 1;
    unsigned int RXFIR                                      : 1;
    unsigned int MSTIR                                      : 1;
    unsigned int reserved                                   :26;
};
#define cpu_sys_spi0_s_risr(val) ((rs_cpu_sys_spi0_s_risr*)&(val))



#define CPU_SYS_SPI0_S_TXOICR                                            (HV_SPI0_BASE_ADDRESS + 0x138)

#define CPU_SYS_SPI0_S_TXOICR_struct                                     rs_cpu_sys_spi0_s_txoicr

typedef struct _rs_cpu_sys_spi0_s_txoicr  rs_cpu_sys_spi0_s_txoicr;
struct _rs_cpu_sys_spi0_s_txoicr {
    unsigned int TXOICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_s_txoicr(val) ((rs_cpu_sys_spi0_s_txoicr*)&(val))



#define CPU_SYS_SPI0_S_RXOICR                                            (HV_SPI0_BASE_ADDRESS + 0x13C)

#define CPU_SYS_SPI0_S_RXOICR_struct                                     rs_cpu_sys_spi0_s_rxoicr

typedef struct _rs_cpu_sys_spi0_s_rxoicr  rs_cpu_sys_spi0_s_rxoicr;
struct _rs_cpu_sys_spi0_s_rxoicr {
    unsigned int RXOICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_s_rxoicr(val) ((rs_cpu_sys_spi0_s_rxoicr*)&(val))



#define CPU_SYS_SPI0_S_RXUICR                                            (HV_SPI0_BASE_ADDRESS + 0x140)

#define CPU_SYS_SPI0_S_RXUICR_struct                                     rs_cpu_sys_spi0_s_rxuicr

typedef struct _rs_cpu_sys_spi0_s_rxuicr  rs_cpu_sys_spi0_s_rxuicr;
struct _rs_cpu_sys_spi0_s_rxuicr {
    unsigned int RXUICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_s_rxuicr(val) ((rs_cpu_sys_spi0_s_rxuicr*)&(val))



#define CPU_SYS_SPI0_S_MSTICR                                            (HV_SPI0_BASE_ADDRESS + 0x144)

#define CPU_SYS_SPI0_S_MSTICR_struct                                     rs_cpu_sys_spi0_s_msticr

typedef struct _rs_cpu_sys_spi0_s_msticr  rs_cpu_sys_spi0_s_msticr;
struct _rs_cpu_sys_spi0_s_msticr {
    unsigned int MSTICR                                     : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_s_msticr(val) ((rs_cpu_sys_spi0_s_msticr*)&(val))



#define CPU_SYS_SPI0_S_ICR                                               (HV_SPI0_BASE_ADDRESS + 0x148)

#define CPU_SYS_SPI0_S_ICR_struct                                        rs_cpu_sys_spi0_s_icr

typedef struct _rs_cpu_sys_spi0_s_icr  rs_cpu_sys_spi0_s_icr;
struct _rs_cpu_sys_spi0_s_icr {
    unsigned int ICR                                        : 1;
    unsigned int reserved                                   :31;
};
#define cpu_sys_spi0_s_icr(val) ((rs_cpu_sys_spi0_s_icr*)&(val))



#define CPU_SYS_SPI0_S_DMACR                                             (HV_SPI0_BASE_ADDRESS + 0x14C)

#define CPU_SYS_SPI0_S_DMACR_struct                                      rs_cpu_sys_spi0_s_dmacr

typedef struct _rs_cpu_sys_spi0_s_dmacr  rs_cpu_sys_spi0_s_dmacr;
struct _rs_cpu_sys_spi0_s_dmacr {
    unsigned int RDMAE                                      : 1;
    unsigned int TDMAE                                      : 1;
    unsigned int reserved                                   :30;
};
#define cpu_sys_spi0_s_dmacr(val) ((rs_cpu_sys_spi0_s_dmacr*)&(val))



#define CPU_SYS_SPI0_S_DMATDLR                                           (HV_SPI0_BASE_ADDRESS + 0x150)

#define CPU_SYS_SPI0_S_DMATDLR_struct                                    rs_cpu_sys_spi0_s_dmatdlr

typedef struct _rs_cpu_sys_spi0_s_dmatdlr  rs_cpu_sys_spi0_s_dmatdlr;
struct _rs_cpu_sys_spi0_s_dmatdlr {
    unsigned int DMATDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_s_dmatdlr(val) ((rs_cpu_sys_spi0_s_dmatdlr*)&(val))



#define CPU_SYS_SPI0_S_DMARDLR                                           (HV_SPI0_BASE_ADDRESS + 0x154)

#define CPU_SYS_SPI0_S_DMARDLR_struct                                    rs_cpu_sys_spi0_s_dmardlr

typedef struct _rs_cpu_sys_spi0_s_dmardlr  rs_cpu_sys_spi0_s_dmardlr;
struct _rs_cpu_sys_spi0_s_dmardlr {
    unsigned int DMARDL                                     : 4;
    unsigned int reserved                                   :28;
};
#define cpu_sys_spi0_s_dmardlr(val) ((rs_cpu_sys_spi0_s_dmardlr*)&(val))



#define CPU_SYS_SPI0_S_IDR                                               (HV_SPI0_BASE_ADDRESS + 0x158)

#define CPU_SYS_SPI0_S_IDR_struct                                        rs_cpu_sys_spi0_s_idr

typedef struct _rs_cpu_sys_spi0_s_idr  rs_cpu_sys_spi0_s_idr;
struct _rs_cpu_sys_spi0_s_idr {
    unsigned int IDCODE                                     :32;
};
#define cpu_sys_spi0_s_idr(val) ((rs_cpu_sys_spi0_s_idr*)&(val))



#define CPU_SYS_SPI0_S_SSI_VERSION_ID                                    (HV_SPI0_BASE_ADDRESS + 0x15C)

#define CPU_SYS_SPI0_S_SSI_VERSION_ID_struct                             rs_cpu_sys_spi0_s_ssi_version_id

typedef struct _rs_cpu_sys_spi0_s_ssi_version_id  rs_cpu_sys_spi0_s_ssi_version_id;
struct _rs_cpu_sys_spi0_s_ssi_version_id {
    unsigned int SSI_COMP_VERSION                           :32;
};
#define cpu_sys_spi0_s_ssi_version_id(val) ((rs_cpu_sys_spi0_s_ssi_version_id*)&(val))



#define CPU_SYS_SPI0_S_DR0                                               (HV_SPI0_BASE_ADDRESS + 0x160)

#define CPU_SYS_SPI0_S_DR0_struct                                        rs_cpu_sys_spi0_s_dr0

typedef struct _rs_cpu_sys_spi0_s_dr0  rs_cpu_sys_spi0_s_dr0;
struct _rs_cpu_sys_spi0_s_dr0 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr0(val) ((rs_cpu_sys_spi0_s_dr0*)&(val))



#define CPU_SYS_SPI0_S_DR1                                               (HV_SPI0_BASE_ADDRESS + 0x164)

#define CPU_SYS_SPI0_S_DR1_struct                                        rs_cpu_sys_spi0_s_dr1

typedef struct _rs_cpu_sys_spi0_s_dr1  rs_cpu_sys_spi0_s_dr1;
struct _rs_cpu_sys_spi0_s_dr1 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr1(val) ((rs_cpu_sys_spi0_s_dr1*)&(val))



#define CPU_SYS_SPI0_S_DR2                                               (HV_SPI0_BASE_ADDRESS + 0x168)

#define CPU_SYS_SPI0_S_DR2_struct                                        rs_cpu_sys_spi0_s_dr2

typedef struct _rs_cpu_sys_spi0_s_dr2  rs_cpu_sys_spi0_s_dr2;
struct _rs_cpu_sys_spi0_s_dr2 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr2(val) ((rs_cpu_sys_spi0_s_dr2*)&(val))



#define CPU_SYS_SPI0_S_DR3                                               (HV_SPI0_BASE_ADDRESS + 0x16C)

#define CPU_SYS_SPI0_S_DR3_struct                                        rs_cpu_sys_spi0_s_dr3

typedef struct _rs_cpu_sys_spi0_s_dr3  rs_cpu_sys_spi0_s_dr3;
struct _rs_cpu_sys_spi0_s_dr3 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr3(val) ((rs_cpu_sys_spi0_s_dr3*)&(val))



#define CPU_SYS_SPI0_S_DR4                                               (HV_SPI0_BASE_ADDRESS + 0x170)

#define CPU_SYS_SPI0_S_DR4_struct                                        rs_cpu_sys_spi0_s_dr4

typedef struct _rs_cpu_sys_spi0_s_dr4  rs_cpu_sys_spi0_s_dr4;
struct _rs_cpu_sys_spi0_s_dr4 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr4(val) ((rs_cpu_sys_spi0_s_dr4*)&(val))



#define CPU_SYS_SPI0_S_DR5                                               (HV_SPI0_BASE_ADDRESS + 0x174)

#define CPU_SYS_SPI0_S_DR5_struct                                        rs_cpu_sys_spi0_s_dr5

typedef struct _rs_cpu_sys_spi0_s_dr5  rs_cpu_sys_spi0_s_dr5;
struct _rs_cpu_sys_spi0_s_dr5 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr5(val) ((rs_cpu_sys_spi0_s_dr5*)&(val))



#define CPU_SYS_SPI0_S_DR6                                               (HV_SPI0_BASE_ADDRESS + 0x178)

#define CPU_SYS_SPI0_S_DR6_struct                                        rs_cpu_sys_spi0_s_dr6

typedef struct _rs_cpu_sys_spi0_s_dr6  rs_cpu_sys_spi0_s_dr6;
struct _rs_cpu_sys_spi0_s_dr6 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr6(val) ((rs_cpu_sys_spi0_s_dr6*)&(val))



#define CPU_SYS_SPI0_S_DR7                                               (HV_SPI0_BASE_ADDRESS + 0x17C)

#define CPU_SYS_SPI0_S_DR7_struct                                        rs_cpu_sys_spi0_s_dr7

typedef struct _rs_cpu_sys_spi0_s_dr7  rs_cpu_sys_spi0_s_dr7;
struct _rs_cpu_sys_spi0_s_dr7 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr7(val) ((rs_cpu_sys_spi0_s_dr7*)&(val))



#define CPU_SYS_SPI0_S_DR8                                               (HV_SPI0_BASE_ADDRESS + 0x180)

#define CPU_SYS_SPI0_S_DR8_struct                                        rs_cpu_sys_spi0_s_dr8

typedef struct _rs_cpu_sys_spi0_s_dr8  rs_cpu_sys_spi0_s_dr8;
struct _rs_cpu_sys_spi0_s_dr8 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr8(val) ((rs_cpu_sys_spi0_s_dr8*)&(val))



#define CPU_SYS_SPI0_S_DR9                                               (HV_SPI0_BASE_ADDRESS + 0x184)

#define CPU_SYS_SPI0_S_DR9_struct                                        rs_cpu_sys_spi0_s_dr9

typedef struct _rs_cpu_sys_spi0_s_dr9  rs_cpu_sys_spi0_s_dr9;
struct _rs_cpu_sys_spi0_s_dr9 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr9(val) ((rs_cpu_sys_spi0_s_dr9*)&(val))



#define CPU_SYS_SPI0_S_DR10                                              (HV_SPI0_BASE_ADDRESS + 0x188)

#define CPU_SYS_SPI0_S_DR10_struct                                       rs_cpu_sys_spi0_s_dr10

typedef struct _rs_cpu_sys_spi0_s_dr10  rs_cpu_sys_spi0_s_dr10;
struct _rs_cpu_sys_spi0_s_dr10 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr10(val) ((rs_cpu_sys_spi0_s_dr10*)&(val))



#define CPU_SYS_SPI0_S_DR11                                              (HV_SPI0_BASE_ADDRESS + 0x18C)

#define CPU_SYS_SPI0_S_DR11_struct                                       rs_cpu_sys_spi0_s_dr11

typedef struct _rs_cpu_sys_spi0_s_dr11  rs_cpu_sys_spi0_s_dr11;
struct _rs_cpu_sys_spi0_s_dr11 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr11(val) ((rs_cpu_sys_spi0_s_dr11*)&(val))



#define CPU_SYS_SPI0_S_DR12                                              (HV_SPI0_BASE_ADDRESS + 0x190)

#define CPU_SYS_SPI0_S_DR12_struct                                       rs_cpu_sys_spi0_s_dr12

typedef struct _rs_cpu_sys_spi0_s_dr12  rs_cpu_sys_spi0_s_dr12;
struct _rs_cpu_sys_spi0_s_dr12 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr12(val) ((rs_cpu_sys_spi0_s_dr12*)&(val))



#define CPU_SYS_SPI0_S_DR13                                              (HV_SPI0_BASE_ADDRESS + 0x194)

#define CPU_SYS_SPI0_S_DR13_struct                                       rs_cpu_sys_spi0_s_dr13

typedef struct _rs_cpu_sys_spi0_s_dr13  rs_cpu_sys_spi0_s_dr13;
struct _rs_cpu_sys_spi0_s_dr13 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr13(val) ((rs_cpu_sys_spi0_s_dr13*)&(val))



#define CPU_SYS_SPI0_S_DR14                                              (HV_SPI0_BASE_ADDRESS + 0x198)

#define CPU_SYS_SPI0_S_DR14_struct                                       rs_cpu_sys_spi0_s_dr14

typedef struct _rs_cpu_sys_spi0_s_dr14  rs_cpu_sys_spi0_s_dr14;
struct _rs_cpu_sys_spi0_s_dr14 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr14(val) ((rs_cpu_sys_spi0_s_dr14*)&(val))



#define CPU_SYS_SPI0_S_DR15                                              (HV_SPI0_BASE_ADDRESS + 0x19C)

#define CPU_SYS_SPI0_S_DR15_struct                                       rs_cpu_sys_spi0_s_dr15

typedef struct _rs_cpu_sys_spi0_s_dr15  rs_cpu_sys_spi0_s_dr15;
struct _rs_cpu_sys_spi0_s_dr15 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr15(val) ((rs_cpu_sys_spi0_s_dr15*)&(val))



#define CPU_SYS_SPI0_S_DR16                                              (HV_SPI0_BASE_ADDRESS + 0x1A0)

#define CPU_SYS_SPI0_S_DR16_struct                                       rs_cpu_sys_spi0_s_dr16

typedef struct _rs_cpu_sys_spi0_s_dr16  rs_cpu_sys_spi0_s_dr16;
struct _rs_cpu_sys_spi0_s_dr16 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr16(val) ((rs_cpu_sys_spi0_s_dr16*)&(val))



#define CPU_SYS_SPI0_S_DR17                                              (HV_SPI0_BASE_ADDRESS + 0x1A4)

#define CPU_SYS_SPI0_S_DR17_struct                                       rs_cpu_sys_spi0_s_dr17

typedef struct _rs_cpu_sys_spi0_s_dr17  rs_cpu_sys_spi0_s_dr17;
struct _rs_cpu_sys_spi0_s_dr17 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr17(val) ((rs_cpu_sys_spi0_s_dr17*)&(val))



#define CPU_SYS_SPI0_S_DR18                                              (HV_SPI0_BASE_ADDRESS + 0x1A8)

#define CPU_SYS_SPI0_S_DR18_struct                                       rs_cpu_sys_spi0_s_dr18

typedef struct _rs_cpu_sys_spi0_s_dr18  rs_cpu_sys_spi0_s_dr18;
struct _rs_cpu_sys_spi0_s_dr18 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr18(val) ((rs_cpu_sys_spi0_s_dr18*)&(val))



#define CPU_SYS_SPI0_S_DR19                                              (HV_SPI0_BASE_ADDRESS + 0x1AC)

#define CPU_SYS_SPI0_S_DR19_struct                                       rs_cpu_sys_spi0_s_dr19

typedef struct _rs_cpu_sys_spi0_s_dr19  rs_cpu_sys_spi0_s_dr19;
struct _rs_cpu_sys_spi0_s_dr19 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr19(val) ((rs_cpu_sys_spi0_s_dr19*)&(val))



#define CPU_SYS_SPI0_S_DR20                                              (HV_SPI0_BASE_ADDRESS + 0x1B0)

#define CPU_SYS_SPI0_S_DR20_struct                                       rs_cpu_sys_spi0_s_dr20

typedef struct _rs_cpu_sys_spi0_s_dr20  rs_cpu_sys_spi0_s_dr20;
struct _rs_cpu_sys_spi0_s_dr20 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr20(val) ((rs_cpu_sys_spi0_s_dr20*)&(val))



#define CPU_SYS_SPI0_S_DR21                                              (HV_SPI0_BASE_ADDRESS + 0x1B4)

#define CPU_SYS_SPI0_S_DR21_struct                                       rs_cpu_sys_spi0_s_dr21

typedef struct _rs_cpu_sys_spi0_s_dr21  rs_cpu_sys_spi0_s_dr21;
struct _rs_cpu_sys_spi0_s_dr21 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr21(val) ((rs_cpu_sys_spi0_s_dr21*)&(val))



#define CPU_SYS_SPI0_S_DR22                                              (HV_SPI0_BASE_ADDRESS + 0x1B8)

#define CPU_SYS_SPI0_S_DR22_struct                                       rs_cpu_sys_spi0_s_dr22

typedef struct _rs_cpu_sys_spi0_s_dr22  rs_cpu_sys_spi0_s_dr22;
struct _rs_cpu_sys_spi0_s_dr22 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr22(val) ((rs_cpu_sys_spi0_s_dr22*)&(val))



#define CPU_SYS_SPI0_S_DR23                                              (HV_SPI0_BASE_ADDRESS + 0x1BC)

#define CPU_SYS_SPI0_S_DR23_struct                                       rs_cpu_sys_spi0_s_dr23

typedef struct _rs_cpu_sys_spi0_s_dr23  rs_cpu_sys_spi0_s_dr23;
struct _rs_cpu_sys_spi0_s_dr23 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr23(val) ((rs_cpu_sys_spi0_s_dr23*)&(val))



#define CPU_SYS_SPI0_S_DR24                                              (HV_SPI0_BASE_ADDRESS + 0x1C0)

#define CPU_SYS_SPI0_S_DR24_struct                                       rs_cpu_sys_spi0_s_dr24

typedef struct _rs_cpu_sys_spi0_s_dr24  rs_cpu_sys_spi0_s_dr24;
struct _rs_cpu_sys_spi0_s_dr24 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr24(val) ((rs_cpu_sys_spi0_s_dr24*)&(val))



#define CPU_SYS_SPI0_S_DR25                                              (HV_SPI0_BASE_ADDRESS + 0x1C4)

#define CPU_SYS_SPI0_S_DR25_struct                                       rs_cpu_sys_spi0_s_dr25

typedef struct _rs_cpu_sys_spi0_s_dr25  rs_cpu_sys_spi0_s_dr25;
struct _rs_cpu_sys_spi0_s_dr25 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr25(val) ((rs_cpu_sys_spi0_s_dr25*)&(val))



#define CPU_SYS_SPI0_S_DR26                                              (HV_SPI0_BASE_ADDRESS + 0x1C8)

#define CPU_SYS_SPI0_S_DR26_struct                                       rs_cpu_sys_spi0_s_dr26

typedef struct _rs_cpu_sys_spi0_s_dr26  rs_cpu_sys_spi0_s_dr26;
struct _rs_cpu_sys_spi0_s_dr26 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr26(val) ((rs_cpu_sys_spi0_s_dr26*)&(val))



#define CPU_SYS_SPI0_S_DR27                                              (HV_SPI0_BASE_ADDRESS + 0x1CC)

#define CPU_SYS_SPI0_S_DR27_struct                                       rs_cpu_sys_spi0_s_dr27

typedef struct _rs_cpu_sys_spi0_s_dr27  rs_cpu_sys_spi0_s_dr27;
struct _rs_cpu_sys_spi0_s_dr27 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr27(val) ((rs_cpu_sys_spi0_s_dr27*)&(val))



#define CPU_SYS_SPI0_S_DR28                                              (HV_SPI0_BASE_ADDRESS + 0x1D0)

#define CPU_SYS_SPI0_S_DR28_struct                                       rs_cpu_sys_spi0_s_dr28

typedef struct _rs_cpu_sys_spi0_s_dr28  rs_cpu_sys_spi0_s_dr28;
struct _rs_cpu_sys_spi0_s_dr28 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr28(val) ((rs_cpu_sys_spi0_s_dr28*)&(val))



#define CPU_SYS_SPI0_S_DR29                                              (HV_SPI0_BASE_ADDRESS + 0x1D4)

#define CPU_SYS_SPI0_S_DR29_struct                                       rs_cpu_sys_spi0_s_dr29

typedef struct _rs_cpu_sys_spi0_s_dr29  rs_cpu_sys_spi0_s_dr29;
struct _rs_cpu_sys_spi0_s_dr29 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr29(val) ((rs_cpu_sys_spi0_s_dr29*)&(val))



#define CPU_SYS_SPI0_S_DR30                                              (HV_SPI0_BASE_ADDRESS + 0x1D8)

#define CPU_SYS_SPI0_S_DR30_struct                                       rs_cpu_sys_spi0_s_dr30

typedef struct _rs_cpu_sys_spi0_s_dr30  rs_cpu_sys_spi0_s_dr30;
struct _rs_cpu_sys_spi0_s_dr30 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr30(val) ((rs_cpu_sys_spi0_s_dr30*)&(val))



#define CPU_SYS_SPI0_S_DR31                                              (HV_SPI0_BASE_ADDRESS + 0x1DC)

#define CPU_SYS_SPI0_S_DR31_struct                                       rs_cpu_sys_spi0_s_dr31

typedef struct _rs_cpu_sys_spi0_s_dr31  rs_cpu_sys_spi0_s_dr31;
struct _rs_cpu_sys_spi0_s_dr31 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr31(val) ((rs_cpu_sys_spi0_s_dr31*)&(val))



#define CPU_SYS_SPI0_S_DR32                                              (HV_SPI0_BASE_ADDRESS + 0x1E0)

#define CPU_SYS_SPI0_S_DR32_struct                                       rs_cpu_sys_spi0_s_dr32

typedef struct _rs_cpu_sys_spi0_s_dr32  rs_cpu_sys_spi0_s_dr32;
struct _rs_cpu_sys_spi0_s_dr32 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr32(val) ((rs_cpu_sys_spi0_s_dr32*)&(val))



#define CPU_SYS_SPI0_S_DR33                                              (HV_SPI0_BASE_ADDRESS + 0x1E4)

#define CPU_SYS_SPI0_S_DR33_struct                                       rs_cpu_sys_spi0_s_dr33

typedef struct _rs_cpu_sys_spi0_s_dr33  rs_cpu_sys_spi0_s_dr33;
struct _rs_cpu_sys_spi0_s_dr33 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr33(val) ((rs_cpu_sys_spi0_s_dr33*)&(val))



#define CPU_SYS_SPI0_S_DR34                                              (HV_SPI0_BASE_ADDRESS + 0x1E8)

#define CPU_SYS_SPI0_S_DR34_struct                                       rs_cpu_sys_spi0_s_dr34

typedef struct _rs_cpu_sys_spi0_s_dr34  rs_cpu_sys_spi0_s_dr34;
struct _rs_cpu_sys_spi0_s_dr34 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr34(val) ((rs_cpu_sys_spi0_s_dr34*)&(val))



#define CPU_SYS_SPI0_S_DR35                                              (HV_SPI0_BASE_ADDRESS + 0x1EC)

#define CPU_SYS_SPI0_S_DR35_struct                                       rs_cpu_sys_spi0_s_dr35

typedef struct _rs_cpu_sys_spi0_s_dr35  rs_cpu_sys_spi0_s_dr35;
struct _rs_cpu_sys_spi0_s_dr35 {
    unsigned int DR                                         :32;
};
#define cpu_sys_spi0_s_dr35(val) ((rs_cpu_sys_spi0_s_dr35*)&(val))



#define CPU_SYS_SPI0_S_RX_SAMPLE_DLY                                     (HV_SPI0_BASE_ADDRESS + 0x1F0)

#define CPU_SYS_SPI0_S_RX_SAMPLE_DLY_struct                              rs_cpu_sys_spi0_s_rx_sample_dly

typedef struct _rs_cpu_sys_spi0_s_rx_sample_dly  rs_cpu_sys_spi0_s_rx_sample_dly;
struct _rs_cpu_sys_spi0_s_rx_sample_dly {
    unsigned int RSD                                        : 8;
    unsigned int reserved                                   :24;
};
#define cpu_sys_spi0_s_rx_sample_dly(val) ((rs_cpu_sys_spi0_s_rx_sample_dly*)&(val))



#define CPU_SYS_SPI0_MODE_CTL0                                           (HV_SPI0_BASE_ADDRESS + 0x200)

#define CPU_SYS_SPI0_MODE_CTL0_struct                                    rs_cpu_sys_spi0_mode_ctl0

typedef struct _rs_cpu_sys_spi0_mode_ctl0  rs_cpu_sys_spi0_mode_ctl0;
struct _rs_cpu_sys_spi0_mode_ctl0 {
    unsigned int reg_ssi_master                             : 1;
    unsigned int cs_oe_ctrl                                 : 1;
    unsigned int reg_cs_oe                                  : 1;
    unsigned int sck_oe_ctrl                                : 1;
    unsigned int reg_sck_oe                                 : 1;
    unsigned int mosi_oe_ctrl                               : 1;
    unsigned int reg_mosi_oe                                : 1;
    unsigned int miso_oe_ctrl                               : 1;
    unsigned int reg_miso_oe                                : 1;
    unsigned int reserved                                   :23;
};
#define cpu_sys_spi0_mode_ctl0(val) ((rs_cpu_sys_spi0_mode_ctl0*)&(val))



#endif