#ifndef _HV_PAGE_HT7315_EDP_RX_DPCD_2_REG_01_H_
#define _HV_PAGE_HT7315_EDP_RX_DPCD_2_REG_01_H_

#ifndef HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS
    #define HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS                                         0x1104A200
#endif


#define RX_EDP_RX_DPCD_2_REG_01_00                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_DPCD_2_REG_01_00_struct                                rs_rx_edp_rx_dpcd_2_reg_01_00

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_00  rs_rx_edp_rx_dpcd_2_reg_01_00;
struct _rs_rx_edp_rx_dpcd_2_reg_01_00 {
    unsigned int reg_01_dprx_dpcd_sink_count                : 6;
    unsigned int reg_01_dprx_dpcd_cp_ready                  : 1;
    unsigned int reserved                                   : 1;
    unsigned int regr_01_dprx_dpcd_remote_control_command_pending: 1;
    unsigned int regr_01_dprx_dpcd_touch_interrupt          : 1;
    unsigned int regr_01_dprx_dpcd_cp_irq                   : 1;
    unsigned int regr_01_dprx_dpcd_mccs_irq                 : 1;
    unsigned int regr_01_dprx_dpcd_down_rep_msg_rdy         : 1;
    unsigned int regr_01_dprx_dpcd_up_req_msg_rdy           : 1;
    unsigned int regr_01_dprx_dpcd_sink_specific_irq        : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int regr_01_dprx_dpcd_lane0_cr_done            : 1;
    unsigned int regr_01_dprx_dpcd_lane0_channel_eq_done    : 1;
    unsigned int regr_01_dprx_dpcd_lane0_symbol_locked      : 1;
    unsigned int reserved_2                                 : 1;
    unsigned int regr_01_dprx_dpcd_lane1_cr_done            : 1;
    unsigned int regr_01_dprx_dpcd_lane1_channel_eq_done    : 1;
    unsigned int regr_01_dprx_dpcd_lane1_symbol_locked      : 1;
    unsigned int reserved_3                                 : 1;
    unsigned int regr_01_dprx_dpcd_lane2_cr_done            : 1;
    unsigned int regr_01_dprx_dpcd_lane2_channel_eq_done    : 1;
    unsigned int regr_01_dprx_dpcd_lane2_symbol_locked      : 1;
    unsigned int reserved_4                                 : 1;
    unsigned int regr_01_dprx_dpcd_lane3_cr_done            : 1;
    unsigned int regr_01_dprx_dpcd_lane3_channel_eq_done    : 1;
    unsigned int regr_01_dprx_dpcd_lane3_symbol_locked      : 1;
    unsigned int reserved_5                                 : 1;
};
#define rx_edp_rx_dpcd_2_reg_01_00(val) ((rs_rx_edp_rx_dpcd_2_reg_01_00*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_04                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_DPCD_2_REG_01_04_struct                                rs_rx_edp_rx_dpcd_2_reg_01_04

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_04  rs_rx_edp_rx_dpcd_2_reg_01_04;
struct _rs_rx_edp_rx_dpcd_2_reg_01_04 {
    unsigned int regr_01_dprx_dpcd_interlane_align_done     : 1;
    unsigned int regr_01_dprx_dpcd_post_lt_adj_req_in_progress: 1;
    unsigned int reserved                                   : 4;
    unsigned int regr_01_dprx_dpcd_downstream_port_status_changed: 1;
    unsigned int regr_01_dprx_dpcd_link_status_updated      : 1;
    unsigned int regr_01_dprx_dpcd_receive_port_0_status    : 1;
    unsigned int regr_01_dprx_dpcd_receive_port_1_status    : 1;
    unsigned int reserved_1                                 : 6;
    unsigned int regr_01_dprx_dpcd_voltage_swing_lane0      : 2;
    unsigned int regr_01_dprx_dpcd_pre_emphasis_lane0       : 2;
    unsigned int regr_01_dprx_dpcd_voltage_swing_lane1      : 2;
    unsigned int regr_01_dprx_dpcd_pre_emphasis_lane1       : 2;
    unsigned int regr_01_dprx_dpcd_voltage_swing_lane2      : 2;
    unsigned int regr_01_dprx_dpcd_pre_emphasis_lane2       : 2;
    unsigned int regr_01_dprx_dpcd_voltage_swing_lane3      : 2;
    unsigned int regr_01_dprx_dpcd_pre_emphasis_lane3       : 2;
};
#define rx_edp_rx_dpcd_2_reg_01_04(val) ((rs_rx_edp_rx_dpcd_2_reg_01_04*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_08                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_DPCD_2_REG_01_08_struct                                rs_rx_edp_rx_dpcd_2_reg_01_08

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_08  rs_rx_edp_rx_dpcd_2_reg_01_08;
struct _rs_rx_edp_rx_dpcd_2_reg_01_08 {
    unsigned int regr_01_dprx_dpcd_training_score_lane0     : 8;
    unsigned int regr_01_dprx_dpcd_training_score_lane1     : 8;
    unsigned int regr_01_dprx_dpcd_training_score_lane2     : 8;
    unsigned int regr_01_dprx_dpcd_training_score_lane3     : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_08(val) ((rs_rx_edp_rx_dpcd_2_reg_01_08*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_0C                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x0C)

#define RX_EDP_RX_DPCD_2_REG_01_0C_struct                                rs_rx_edp_rx_dpcd_2_reg_01_0c

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_0c  rs_rx_edp_rx_dpcd_2_reg_01_0c;
struct _rs_rx_edp_rx_dpcd_2_reg_01_0c {
    unsigned int reg_01_dprx_dpcd_link_rate_set_status      : 1;
    unsigned int reg_01_dprx_dpcd_link_rate_set_status_valid: 1;
    unsigned int reserved                                   :22;
    unsigned int regr_01_dprx_dpcd_dsc_rc_buffer_underrun   : 1;
    unsigned int regr_01_dprx_dpcd_dsc_rc_buffer_overflow   : 1;
    unsigned int regr_01_dprx_dpcd_dsc_chunk_length_error   : 1;
    unsigned int reserved_1                                 : 5;
};
#define rx_edp_rx_dpcd_2_reg_01_0c(val) ((rs_rx_edp_rx_dpcd_2_reg_01_0c*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_10                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x10)

#define RX_EDP_RX_DPCD_2_REG_01_10_struct                                rs_rx_edp_rx_dpcd_2_reg_01_10

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_10  rs_rx_edp_rx_dpcd_2_reg_01_10;
struct _rs_rx_edp_rx_dpcd_2_reg_01_10 {
    unsigned int regr_01_dprx_dpcd_symbol_error_count_lane0 :16;
    unsigned int regr_01_dprx_dpcd_symbol_error_count_lane1 :16;
};
#define rx_edp_rx_dpcd_2_reg_01_10(val) ((rs_rx_edp_rx_dpcd_2_reg_01_10*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_14                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x14)

#define RX_EDP_RX_DPCD_2_REG_01_14_struct                                rs_rx_edp_rx_dpcd_2_reg_01_14

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_14  rs_rx_edp_rx_dpcd_2_reg_01_14;
struct _rs_rx_edp_rx_dpcd_2_reg_01_14 {
    unsigned int regr_01_dprx_dpcd_symbol_error_count_lane2 :16;
    unsigned int regr_01_dprx_dpcd_symbol_error_count_lane3 :16;
};
#define rx_edp_rx_dpcd_2_reg_01_14(val) ((rs_rx_edp_rx_dpcd_2_reg_01_14*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_18                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x18)

#define RX_EDP_RX_DPCD_2_REG_01_18_struct                                rs_rx_edp_rx_dpcd_2_reg_01_18

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_18  rs_rx_edp_rx_dpcd_2_reg_01_18;
struct _rs_rx_edp_rx_dpcd_2_reg_01_18 {
    unsigned int reg_01_dprx_dpcd_test_link_training_req    : 1;
    unsigned int reg_01_dprx_dpcd_test_pattern_req          : 1;
    unsigned int reg_01_dprx_dpcd_test_edid_read            : 1;
    unsigned int reg_01_dprx_dpcd_phy_test_pattern          : 1;
    unsigned int reserved                                   : 4;
    unsigned int reg_01_dprx_dpcd_test_link_rate            : 8;
    unsigned int reserved_1                                 :16;
};
#define rx_edp_rx_dpcd_2_reg_01_18(val) ((rs_rx_edp_rx_dpcd_2_reg_01_18*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_20                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_DPCD_2_REG_01_20_struct                                rs_rx_edp_rx_dpcd_2_reg_01_20

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_20  rs_rx_edp_rx_dpcd_2_reg_01_20;
struct _rs_rx_edp_rx_dpcd_2_reg_01_20 {
    unsigned int reg_01_dprx_dpcd_test_lane_count           : 5;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_dprx_dpcd_test_pattern              : 8;
    unsigned int reg_01_dprx_dpcd_test_h_total              :16;
};
#define rx_edp_rx_dpcd_2_reg_01_20(val) ((rs_rx_edp_rx_dpcd_2_reg_01_20*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_24                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_DPCD_2_REG_01_24_struct                                rs_rx_edp_rx_dpcd_2_reg_01_24

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_24  rs_rx_edp_rx_dpcd_2_reg_01_24;
struct _rs_rx_edp_rx_dpcd_2_reg_01_24 {
    unsigned int reg_01_dprx_dpcd_test_v_total              :16;
    unsigned int reg_01_dprx_dpcd_test_h_start              :16;
};
#define rx_edp_rx_dpcd_2_reg_01_24(val) ((rs_rx_edp_rx_dpcd_2_reg_01_24*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_28                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_DPCD_2_REG_01_28_struct                                rs_rx_edp_rx_dpcd_2_reg_01_28

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_28  rs_rx_edp_rx_dpcd_2_reg_01_28;
struct _rs_rx_edp_rx_dpcd_2_reg_01_28 {
    unsigned int reg_01_dprx_dpcd_test_v_start              :16;
    unsigned int reg_01_dprx_dpcd_test_hsync_polarity       : 1;
    unsigned int reg_01_dprx_dpcd_test_hsync_width          :15;
};
#define rx_edp_rx_dpcd_2_reg_01_28(val) ((rs_rx_edp_rx_dpcd_2_reg_01_28*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_2C                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x2C)

#define RX_EDP_RX_DPCD_2_REG_01_2C_struct                                rs_rx_edp_rx_dpcd_2_reg_01_2c

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_2c  rs_rx_edp_rx_dpcd_2_reg_01_2c;
struct _rs_rx_edp_rx_dpcd_2_reg_01_2c {
    unsigned int reg_01_dprx_dpcd_test_vsync_polarity       : 1;
    unsigned int reg_01_dprx_dpcd_test_vsync_width          :15;
    unsigned int reg_01_dprx_dpcd_test_h_width              :16;
};
#define rx_edp_rx_dpcd_2_reg_01_2c(val) ((rs_rx_edp_rx_dpcd_2_reg_01_2c*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_30                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x30)

#define RX_EDP_RX_DPCD_2_REG_01_30_struct                                rs_rx_edp_rx_dpcd_2_reg_01_30

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_30  rs_rx_edp_rx_dpcd_2_reg_01_30;
struct _rs_rx_edp_rx_dpcd_2_reg_01_30 {
    unsigned int reg_01_dprx_dpcd_test_v_height             :16;
    unsigned int reg_01_dprx_dpcd_test_sync_clock           : 1;
    unsigned int reg_01_dprx_dpcd_test_color_format         : 2;
    unsigned int reg_01_dprx_dpcd_test_dynamic_range        : 1;
    unsigned int reg_01_dprx_dpcd_test_ycbcr_coefficients   : 1;
    unsigned int reg_01_dprx_dpcd_test_bit_depth            : 3;
    unsigned int reg_01_dprx_dpcd_test_refresh_denominator  : 1;
    unsigned int reg_01_dprx_dpcd_test_interlaced           : 1;
    unsigned int reserved                                   : 6;
};
#define rx_edp_rx_dpcd_2_reg_01_30(val) ((rs_rx_edp_rx_dpcd_2_reg_01_30*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_34                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x34)

#define RX_EDP_RX_DPCD_2_REG_01_34_struct                                rs_rx_edp_rx_dpcd_2_reg_01_34

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_34  rs_rx_edp_rx_dpcd_2_reg_01_34;
struct _rs_rx_edp_rx_dpcd_2_reg_01_34 {
    unsigned int reg_01_dprx_dpcd_test_refresh_rate_numerator: 8;
    unsigned int reserved                                   :24;
};
#define rx_edp_rx_dpcd_2_reg_01_34(val) ((rs_rx_edp_rx_dpcd_2_reg_01_34*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_40                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_DPCD_2_REG_01_40_struct                                rs_rx_edp_rx_dpcd_2_reg_01_40

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_40  rs_rx_edp_rx_dpcd_2_reg_01_40;
struct _rs_rx_edp_rx_dpcd_2_reg_01_40 {
    unsigned int regr_01_dprx_dpcd_test_crc_r_cr_value      :16;
    unsigned int regr_01_dprx_dpcd_test_crc_g_y_value       :16;
};
#define rx_edp_rx_dpcd_2_reg_01_40(val) ((rs_rx_edp_rx_dpcd_2_reg_01_40*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_44                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_DPCD_2_REG_01_44_struct                                rs_rx_edp_rx_dpcd_2_reg_01_44

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_44  rs_rx_edp_rx_dpcd_2_reg_01_44;
struct _rs_rx_edp_rx_dpcd_2_reg_01_44 {
    unsigned int regr_01_dprx_dpcd_test_crc_b_cb_value      :16;
    unsigned int regr_01_dprx_dpcd_test_crc_count           : 4;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_dprx_dpcd_test_crc_supported        : 1;
    unsigned int reserved_1                                 :10;
};
#define rx_edp_rx_dpcd_2_reg_01_44(val) ((rs_rx_edp_rx_dpcd_2_reg_01_44*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_48                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_DPCD_2_REG_01_48_struct                                rs_rx_edp_rx_dpcd_2_reg_01_48

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_48  rs_rx_edp_rx_dpcd_2_reg_01_48;
struct _rs_rx_edp_rx_dpcd_2_reg_01_48 {
    unsigned int reg_01_dprx_dpcd_phy_pattern_sel           : 3;
    unsigned int reserved                                   :13;
    unsigned int regr_01_dprx_dpcd_hbr2_compliance_scrambler_reset_value:16;
};
#define rx_edp_rx_dpcd_2_reg_01_48(val) ((rs_rx_edp_rx_dpcd_2_reg_01_48*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_50                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x50)

#define RX_EDP_RX_DPCD_2_REG_01_50_struct                                rs_rx_edp_rx_dpcd_2_reg_01_50

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_50  rs_rx_edp_rx_dpcd_2_reg_01_50;
struct _rs_rx_edp_rx_dpcd_2_reg_01_50 {
    unsigned int reg_01_dprx_dpcd_test_80bit_custom_pattern_value0:32;
};
#define rx_edp_rx_dpcd_2_reg_01_50(val) ((rs_rx_edp_rx_dpcd_2_reg_01_50*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_54                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x54)

#define RX_EDP_RX_DPCD_2_REG_01_54_struct                                rs_rx_edp_rx_dpcd_2_reg_01_54

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_54  rs_rx_edp_rx_dpcd_2_reg_01_54;
struct _rs_rx_edp_rx_dpcd_2_reg_01_54 {
    unsigned int reg_01_dprx_dpcd_test_80bit_custom_pattern_value1:32;
};
#define rx_edp_rx_dpcd_2_reg_01_54(val) ((rs_rx_edp_rx_dpcd_2_reg_01_54*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_58                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x58)

#define RX_EDP_RX_DPCD_2_REG_01_58_struct                                rs_rx_edp_rx_dpcd_2_reg_01_58

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_58  rs_rx_edp_rx_dpcd_2_reg_01_58;
struct _rs_rx_edp_rx_dpcd_2_reg_01_58 {
    unsigned int reg_01_dprx_dpcd_test_80bit_custom_pattern_value2:16;
    unsigned int reg_01_dprx_dpcd_continuous_80bit_pattern_from_dprx_aux_ch_cap: 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_01_dprx_dpcd_continuous_80bit_pattern_from_dprx_aux_ch_en: 1;
    unsigned int reg_01_dprx_dpcd_continuous_80bit_pattern_duration_ctrl: 3;
    unsigned int reserved_1                                 : 4;
};
#define rx_edp_rx_dpcd_2_reg_01_58(val) ((rs_rx_edp_rx_dpcd_2_reg_01_58*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_5C                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x5C)

#define RX_EDP_RX_DPCD_2_REG_01_5C_struct                                rs_rx_edp_rx_dpcd_2_reg_01_5c

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_5c  rs_rx_edp_rx_dpcd_2_reg_01_5c;
struct _rs_rx_edp_rx_dpcd_2_reg_01_5c {
    unsigned int reg_01_dprx_dpcd_test_act                  : 1;
    unsigned int reg_01_dprx_dpcd_test_nak                  : 1;
    unsigned int reg_01_dprx_dpcd_test_edid_checksum_write  : 1;
    unsigned int reserved                                   : 5;
    unsigned int reg_01_dprx_dpcd_test_edid_checksum        : 8;
    unsigned int regr_01_dprx_dpcd_dsc_crc_0                :16;
};
#define rx_edp_rx_dpcd_2_reg_01_5c(val) ((rs_rx_edp_rx_dpcd_2_reg_01_5c*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_60                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_DPCD_2_REG_01_60_struct                                rs_rx_edp_rx_dpcd_2_reg_01_60

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_60  rs_rx_edp_rx_dpcd_2_reg_01_60;
struct _rs_rx_edp_rx_dpcd_2_reg_01_60 {
    unsigned int regr_01_dprx_dpcd_dsc_crc_1                :16;
    unsigned int regr_01_dprx_dpcd_dsc_crc_2                :16;
};
#define rx_edp_rx_dpcd_2_reg_01_60(val) ((rs_rx_edp_rx_dpcd_2_reg_01_60*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_70                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x70)

#define RX_EDP_RX_DPCD_2_REG_01_70_struct                                rs_rx_edp_rx_dpcd_2_reg_01_70

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_70  rs_rx_edp_rx_dpcd_2_reg_01_70;
struct _rs_rx_edp_rx_dpcd_2_reg_01_70 {
    unsigned int reg_01_dprx_dpcd_test_sink_start           : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_dprx_dpcd_phy_sink_test_lane_sel    : 2;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_01_dprx_dpcd_phy_sink_test_lane_en     : 1;
    unsigned int reg_01_dprx_dpcd_test_audio_sampling_rate  : 4;
    unsigned int reg_01_dprx_dpcd_test_audio_channel_count  : 4;
    unsigned int reg_01_dprx_dpcd_test_audio_pattern        : 8;
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch1     : 4;
    unsigned int reserved_2                                 : 4;
};
#define rx_edp_rx_dpcd_2_reg_01_70(val) ((rs_rx_edp_rx_dpcd_2_reg_01_70*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_74                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x74)

#define RX_EDP_RX_DPCD_2_REG_01_74_struct                                rs_rx_edp_rx_dpcd_2_reg_01_74

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_74  rs_rx_edp_rx_dpcd_2_reg_01_74;
struct _rs_rx_edp_rx_dpcd_2_reg_01_74 {
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch2     : 4;
    unsigned int reserved                                   : 4;
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch3     : 4;
    unsigned int reserved_1                                 : 4;
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch4     : 4;
    unsigned int reserved_2                                 : 4;
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch5     : 4;
    unsigned int reserved_3                                 : 4;
};
#define rx_edp_rx_dpcd_2_reg_01_74(val) ((rs_rx_edp_rx_dpcd_2_reg_01_74*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_78                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x78)

#define RX_EDP_RX_DPCD_2_REG_01_78_struct                                rs_rx_edp_rx_dpcd_2_reg_01_78

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_78  rs_rx_edp_rx_dpcd_2_reg_01_78;
struct _rs_rx_edp_rx_dpcd_2_reg_01_78 {
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch6     : 4;
    unsigned int reserved                                   : 4;
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch7     : 4;
    unsigned int reserved_1                                 : 4;
    unsigned int reg_01_dprx_dpcd_test_audio_period_ch8     : 4;
    unsigned int reserved_2                                 :12;
};
#define rx_edp_rx_dpcd_2_reg_01_78(val) ((rs_rx_edp_rx_dpcd_2_reg_01_78*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_80                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0x80)

#define RX_EDP_RX_DPCD_2_REG_01_80_struct                                rs_rx_edp_rx_dpcd_2_reg_01_80

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_80  rs_rx_edp_rx_dpcd_2_reg_01_80;
struct _rs_rx_edp_rx_dpcd_2_reg_01_80 {
    unsigned int regr_01_dprx_dpcd_fec_decode_en_detected   : 1;
    unsigned int regr_01_dprx_dpcd_fec_decode_dis_detected  : 1;
    unsigned int reserved                                   : 6;
    unsigned int regr_01_dprx_dpcd_fec_error_count          :15;
    unsigned int regr_01_dprx_dpcd_fec_error_count_valid    : 1;
    unsigned int reserved_1                                 : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_80(val) ((rs_rx_edp_rx_dpcd_2_reg_01_80*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_C0                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xC0)

#define RX_EDP_RX_DPCD_2_REG_01_C0_struct                                rs_rx_edp_rx_dpcd_2_reg_01_c0

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_c0  rs_rx_edp_rx_dpcd_2_reg_01_c0;
struct _rs_rx_edp_rx_dpcd_2_reg_01_c0 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_table_updated: 1;
    unsigned int regr_01_dprx_dpcd_vc_payload_act_handled   : 1;
    unsigned int reserved                                   : 6;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_1     : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_2     : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_3     : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_c0(val) ((rs_rx_edp_rx_dpcd_2_reg_01_c0*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_C4                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xC4)

#define RX_EDP_RX_DPCD_2_REG_01_C4_struct                                rs_rx_edp_rx_dpcd_2_reg_01_c4

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_c4  rs_rx_edp_rx_dpcd_2_reg_01_c4;
struct _rs_rx_edp_rx_dpcd_2_reg_01_c4 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_4     : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_5     : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_6     : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_7     : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_c4(val) ((rs_rx_edp_rx_dpcd_2_reg_01_c4*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_C8                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xC8)

#define RX_EDP_RX_DPCD_2_REG_01_C8_struct                                rs_rx_edp_rx_dpcd_2_reg_01_c8

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_c8  rs_rx_edp_rx_dpcd_2_reg_01_c8;
struct _rs_rx_edp_rx_dpcd_2_reg_01_c8 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_8     : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_9     : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_10    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_11    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_c8(val) ((rs_rx_edp_rx_dpcd_2_reg_01_c8*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_CC                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xCC)

#define RX_EDP_RX_DPCD_2_REG_01_CC_struct                                rs_rx_edp_rx_dpcd_2_reg_01_cc

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_cc  rs_rx_edp_rx_dpcd_2_reg_01_cc;
struct _rs_rx_edp_rx_dpcd_2_reg_01_cc {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_12    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_13    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_14    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_15    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_cc(val) ((rs_rx_edp_rx_dpcd_2_reg_01_cc*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_D0                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xD0)

#define RX_EDP_RX_DPCD_2_REG_01_D0_struct                                rs_rx_edp_rx_dpcd_2_reg_01_d0

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_d0  rs_rx_edp_rx_dpcd_2_reg_01_d0;
struct _rs_rx_edp_rx_dpcd_2_reg_01_d0 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_16    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_17    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_18    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_19    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_d0(val) ((rs_rx_edp_rx_dpcd_2_reg_01_d0*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_D4                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xD4)

#define RX_EDP_RX_DPCD_2_REG_01_D4_struct                                rs_rx_edp_rx_dpcd_2_reg_01_d4

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_d4  rs_rx_edp_rx_dpcd_2_reg_01_d4;
struct _rs_rx_edp_rx_dpcd_2_reg_01_d4 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_20    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_21    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_22    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_23    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_d4(val) ((rs_rx_edp_rx_dpcd_2_reg_01_d4*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_D8                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xD8)

#define RX_EDP_RX_DPCD_2_REG_01_D8_struct                                rs_rx_edp_rx_dpcd_2_reg_01_d8

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_d8  rs_rx_edp_rx_dpcd_2_reg_01_d8;
struct _rs_rx_edp_rx_dpcd_2_reg_01_d8 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_24    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_25    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_26    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_27    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_d8(val) ((rs_rx_edp_rx_dpcd_2_reg_01_d8*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_DC                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xDC)

#define RX_EDP_RX_DPCD_2_REG_01_DC_struct                                rs_rx_edp_rx_dpcd_2_reg_01_dc

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_dc  rs_rx_edp_rx_dpcd_2_reg_01_dc;
struct _rs_rx_edp_rx_dpcd_2_reg_01_dc {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_28    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_29    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_30    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_31    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_dc(val) ((rs_rx_edp_rx_dpcd_2_reg_01_dc*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_E0                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xE0)

#define RX_EDP_RX_DPCD_2_REG_01_E0_struct                                rs_rx_edp_rx_dpcd_2_reg_01_e0

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_e0  rs_rx_edp_rx_dpcd_2_reg_01_e0;
struct _rs_rx_edp_rx_dpcd_2_reg_01_e0 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_32    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_33    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_34    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_35    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_e0(val) ((rs_rx_edp_rx_dpcd_2_reg_01_e0*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_E4                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xE4)

#define RX_EDP_RX_DPCD_2_REG_01_E4_struct                                rs_rx_edp_rx_dpcd_2_reg_01_e4

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_e4  rs_rx_edp_rx_dpcd_2_reg_01_e4;
struct _rs_rx_edp_rx_dpcd_2_reg_01_e4 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_36    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_37    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_38    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_39    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_e4(val) ((rs_rx_edp_rx_dpcd_2_reg_01_e4*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_E8                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xE8)

#define RX_EDP_RX_DPCD_2_REG_01_E8_struct                                rs_rx_edp_rx_dpcd_2_reg_01_e8

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_e8  rs_rx_edp_rx_dpcd_2_reg_01_e8;
struct _rs_rx_edp_rx_dpcd_2_reg_01_e8 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_40    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_41    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_42    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_43    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_e8(val) ((rs_rx_edp_rx_dpcd_2_reg_01_e8*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_EC                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xEC)

#define RX_EDP_RX_DPCD_2_REG_01_EC_struct                                rs_rx_edp_rx_dpcd_2_reg_01_ec

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_ec  rs_rx_edp_rx_dpcd_2_reg_01_ec;
struct _rs_rx_edp_rx_dpcd_2_reg_01_ec {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_44    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_45    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_46    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_47    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_ec(val) ((rs_rx_edp_rx_dpcd_2_reg_01_ec*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_F0                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xF0)

#define RX_EDP_RX_DPCD_2_REG_01_F0_struct                                rs_rx_edp_rx_dpcd_2_reg_01_f0

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_f0  rs_rx_edp_rx_dpcd_2_reg_01_f0;
struct _rs_rx_edp_rx_dpcd_2_reg_01_f0 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_48    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_49    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_50    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_51    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_f0(val) ((rs_rx_edp_rx_dpcd_2_reg_01_f0*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_F4                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xF4)

#define RX_EDP_RX_DPCD_2_REG_01_F4_struct                                rs_rx_edp_rx_dpcd_2_reg_01_f4

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_f4  rs_rx_edp_rx_dpcd_2_reg_01_f4;
struct _rs_rx_edp_rx_dpcd_2_reg_01_f4 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_52    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_53    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_54    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_55    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_f4(val) ((rs_rx_edp_rx_dpcd_2_reg_01_f4*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_F8                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xF8)

#define RX_EDP_RX_DPCD_2_REG_01_F8_struct                                rs_rx_edp_rx_dpcd_2_reg_01_f8

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_f8  rs_rx_edp_rx_dpcd_2_reg_01_f8;
struct _rs_rx_edp_rx_dpcd_2_reg_01_f8 {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_56    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_57    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_58    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_59    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_f8(val) ((rs_rx_edp_rx_dpcd_2_reg_01_f8*)&(val))



#define RX_EDP_RX_DPCD_2_REG_01_FC                                       (HV_EDP_RX_DPCD_2_REG_01_BASE_ADDRESS + 0xFC)

#define RX_EDP_RX_DPCD_2_REG_01_FC_struct                                rs_rx_edp_rx_dpcd_2_reg_01_fc

typedef struct _rs_rx_edp_rx_dpcd_2_reg_01_fc  rs_rx_edp_rx_dpcd_2_reg_01_fc;
struct _rs_rx_edp_rx_dpcd_2_reg_01_fc {
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_60    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_61    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_62    : 8;
    unsigned int regr_01_dprx_dpcd_vc_payload_id_slot_63    : 8;
};
#define rx_edp_rx_dpcd_2_reg_01_fc(val) ((rs_rx_edp_rx_dpcd_2_reg_01_fc*)&(val))



#endif