/**
 * @file hv_cal_DpuCprConfig.h
 * @brief Header file of dpu cal Cal module.
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-10
 */

#ifndef __HV_CAL_DPU_SCALER_CPR_CONFIG_H__
#define __HV_CAL_DPU_SCALER_CPR_CONFIG_H__

#include "hv_comm_DataType.h"
#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Define.h"

typedef struct _MainCprDrrAddr
{
    UINT32 uiStartAddress0;
    UINT32 uiStartAddress1;
    UINT32 uiStartAddress2;
    UINT32 uiEndAddress0;
    UINT32 uiEndAddress1;
    UINT32 uiEndAddress2;
    UINT32 uiLineOffsetAddr;
} MainCprDrrAddr;

VOID Hv_Cal_DpuScaler_VdmCprMainInitfig(VOID);

/*dpc/vdm ip enable start*/
VOID Hv_Cal_DpuScaler_DpuEncVdmWriteEnable(BOOL bEn);
VOID Hv_Cal_DpuScaler_DpuDecVdmReadEnable(BOOL bEn);
/*dpc/vdm ip enable end*/

/*dpc/vdm ip dynamic config start*/
VOID Hv_Cal_DpuScaler_DpcSrpMainSettings(DpuDpcCapSrpParam* pstDpuDpcCapSrpParam);
/*dpc/vdm ip dynamic config end*/
VOID Hv_Cal_DpuScaler_DpcSrpMainEnc1ClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_DpcSrpMainDecClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpMainUnpackClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpMainEncClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpMainFrcFrameSyncSel(UINT32 uiValue);

BOOL Hv_Cal_DpuScaler_MainCprDdrAddr(const VideoConfigParams* pstVideoConfigParams, MainCprDrrAddr* pstMainCprDrrAddr);

Status Hv_Cal_DpuScaler_MainCprEncodeConfig(const VideoConfigParams* pstVideoConfigParams);
Status Hv_Cal_DpuScaler_MainCprDecodeConfig(const VideoConfigParams* pstVideoConfigParams);
Status Hv_Cal_DpuScaler_MainCprEncodeVdmConfig(const VideoConfigParams* pstVideoConfigParams);
Status Hv_Cal_DpuScaler_MainCprDecodeVdmConfig(const VideoConfigParams* pstVideoConfigParams);

#endif