#ifndef _HV_PAGE_HT7315_BOE_TX_H_
#define _HV_PAGE_HT7315_BOE_TX_H_

#ifndef HV_BOE_TX_BASE_ADDRESS
    #define HV_BOE_TX_BASE_ADDRESS                                         0x1105E700
#endif


#define TX_BOE_TX_BOE_P2P_REGISTER_0                                     (HV_BOE_TX_BASE_ADDRESS + 0x00)

#define TX_BOE_TX_BOE_P2P_REGISTER_0_struct                              rs_tx_boe_tx_boe_p2p_register_0

typedef struct _rs_tx_boe_tx_boe_p2p_register_0  rs_tx_boe_tx_boe_p2p_register_0;
struct _rs_tx_boe_tx_boe_p2p_register_0 {
    unsigned int reg_boe_tx_rbg_bit                         : 2;
    unsigned int reg_boe_tx_pair_num                        : 2;
    unsigned int reg_boe_tx_bcc_mode_sel                    : 2;
    unsigned int reg_boe_tx_scram_sel                       : 2;
    unsigned int reg_boe_tx_pulse_1us_prescale              : 8;
    unsigned int reg_boe_tx_reset_stable_time               : 8;
    unsigned int reg_boe_tx_lsp_seq_repeat_times            : 8;
};
#define tx_boe_tx_boe_p2p_register_0(val) ((rs_tx_boe_tx_boe_p2p_register_0*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_1                                     (HV_BOE_TX_BASE_ADDRESS + 0x04)

#define TX_BOE_TX_BOE_P2P_REGISTER_1_struct                              rs_tx_boe_tx_boe_p2p_register_1

typedef struct _rs_tx_boe_tx_boe_p2p_register_1  rs_tx_boe_tx_boe_p2p_register_1;
struct _rs_tx_boe_tx_boe_p2p_register_1 {
    unsigned int reg_boe_tx_bcc_in_filter_num               : 8;
    unsigned int reg_boe_tx_ctrl_f_byte_num                 : 6;
    unsigned int reg_boe_tx_training_mode_sel               : 1;
    unsigned int reg_boe_tx_virtual_dummuy_line_en          : 1;
    unsigned int reg_boe_tx_v_blanking_data                 : 8;
    unsigned int reg_bcc_preamble_num                       : 8;
};
#define tx_boe_tx_boe_p2p_register_1(val) ((rs_tx_boe_tx_boe_p2p_register_1*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_2                                     (HV_BOE_TX_BASE_ADDRESS + 0x08)

#define TX_BOE_TX_BOE_P2P_REGISTER_2_struct                              rs_tx_boe_tx_boe_p2p_register_2

typedef struct _rs_tx_boe_tx_boe_p2p_register_2  rs_tx_boe_tx_boe_p2p_register_2;
struct _rs_tx_boe_tx_boe_p2p_register_2 {
    unsigned int reg_bcc_mode1_bc_trans_cmd_byte0           : 8;
    unsigned int reg_bcc_mode1_bc_trans_cmd_byte1           : 8;
    unsigned int reg_bcc_mode1_bc_trans_cmd_byte2           : 8;
    unsigned int reg_bcc_mode1_bc_trans_cmd_byte3           : 8;
};
#define tx_boe_tx_boe_p2p_register_2(val) ((rs_tx_boe_tx_boe_p2p_register_2*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_3                                     (HV_BOE_TX_BASE_ADDRESS + 0x0C)

#define TX_BOE_TX_BOE_P2P_REGISTER_3_struct                              rs_tx_boe_tx_boe_p2p_register_3

typedef struct _rs_tx_boe_tx_boe_p2p_register_3  rs_tx_boe_tx_boe_p2p_register_3;
struct _rs_tx_boe_tx_boe_p2p_register_3 {
    unsigned int reg_bcc_mode1_bc_trans_cmd_byte4           : 8;
    unsigned int reg_bcc_mode1_bc_trans_cmd_byte5           : 8;
    unsigned int reg_bcc_mode1_ia_trans_cmd_byte0           : 8;
    unsigned int reg_bcc_mode1_dc_trans_cmd_byte0           : 8;
};
#define tx_boe_tx_boe_p2p_register_3(val) ((rs_tx_boe_tx_boe_p2p_register_3*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_4                                     (HV_BOE_TX_BASE_ADDRESS + 0x10)

#define TX_BOE_TX_BOE_P2P_REGISTER_4_struct                              rs_tx_boe_tx_boe_p2p_register_4

typedef struct _rs_tx_boe_tx_boe_p2p_register_4  rs_tx_boe_tx_boe_p2p_register_4;
struct _rs_tx_boe_tx_boe_p2p_register_4 {
    unsigned int reg_bcc_mode1_dc_trans_cmd_byte1           : 8;
    unsigned int reg_bcc_mode1_dc_trans_cmd_byte2           : 8;
    unsigned int reg_bcc_mode1_dc_trans_cmd_byte3           : 8;
    unsigned int reg_bcc_mode1_dc_trans_cmd_byte4           : 8;
};
#define tx_boe_tx_boe_p2p_register_4(val) ((rs_tx_boe_tx_boe_p2p_register_4*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_5                                     (HV_BOE_TX_BASE_ADDRESS + 0x14)

#define TX_BOE_TX_BOE_P2P_REGISTER_5_struct                              rs_tx_boe_tx_boe_p2p_register_5

typedef struct _rs_tx_boe_tx_boe_p2p_register_5  rs_tx_boe_tx_boe_p2p_register_5;
struct _rs_tx_boe_tx_boe_p2p_register_5 {
    unsigned int reg_bcc_auto_checksum                      : 1;
    unsigned int reg_boe_tx_v_total                         :15;
    unsigned int reg_boe_tx_v_scram_reset_cycle             :15;
    unsigned int reg_bcc_mode1_irq_en                       : 1;
};
#define tx_boe_tx_boe_p2p_register_5(val) ((rs_tx_boe_tx_boe_p2p_register_5*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_6                                     (HV_BOE_TX_BASE_ADDRESS + 0x18)

#define TX_BOE_TX_BOE_P2P_REGISTER_6_struct                              rs_tx_boe_tx_boe_p2p_register_6

typedef struct _rs_tx_boe_tx_boe_p2p_register_6  rs_tx_boe_tx_boe_p2p_register_6;
struct _rs_tx_boe_tx_boe_p2p_register_6 {
    unsigned int reg_boe_tx_v_scram_reset_lane0             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane1             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_6(val) ((rs_tx_boe_tx_boe_p2p_register_6*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_7                                     (HV_BOE_TX_BASE_ADDRESS + 0x1C)

#define TX_BOE_TX_BOE_P2P_REGISTER_7_struct                              rs_tx_boe_tx_boe_p2p_register_7

typedef struct _rs_tx_boe_tx_boe_p2p_register_7  rs_tx_boe_tx_boe_p2p_register_7;
struct _rs_tx_boe_tx_boe_p2p_register_7 {
    unsigned int reg_boe_tx_v_scram_reset_lane2             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane3             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_7(val) ((rs_tx_boe_tx_boe_p2p_register_7*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_8                                     (HV_BOE_TX_BASE_ADDRESS + 0x20)

#define TX_BOE_TX_BOE_P2P_REGISTER_8_struct                              rs_tx_boe_tx_boe_p2p_register_8

typedef struct _rs_tx_boe_tx_boe_p2p_register_8  rs_tx_boe_tx_boe_p2p_register_8;
struct _rs_tx_boe_tx_boe_p2p_register_8 {
    unsigned int reg_boe_tx_v_scram_reset_lane4             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane5             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_8(val) ((rs_tx_boe_tx_boe_p2p_register_8*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_9                                     (HV_BOE_TX_BASE_ADDRESS + 0x24)

#define TX_BOE_TX_BOE_P2P_REGISTER_9_struct                              rs_tx_boe_tx_boe_p2p_register_9

typedef struct _rs_tx_boe_tx_boe_p2p_register_9  rs_tx_boe_tx_boe_p2p_register_9;
struct _rs_tx_boe_tx_boe_p2p_register_9 {
    unsigned int reg_boe_tx_v_scram_reset_lane6             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane7             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_9(val) ((rs_tx_boe_tx_boe_p2p_register_9*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_10                                    (HV_BOE_TX_BASE_ADDRESS + 0x28)

#define TX_BOE_TX_BOE_P2P_REGISTER_10_struct                             rs_tx_boe_tx_boe_p2p_register_10

typedef struct _rs_tx_boe_tx_boe_p2p_register_10  rs_tx_boe_tx_boe_p2p_register_10;
struct _rs_tx_boe_tx_boe_p2p_register_10 {
    unsigned int reg_boe_tx_v_scram_reset_lane8             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane9             :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_10(val) ((rs_tx_boe_tx_boe_p2p_register_10*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_11                                    (HV_BOE_TX_BASE_ADDRESS + 0x2C)

#define TX_BOE_TX_BOE_P2P_REGISTER_11_struct                             rs_tx_boe_tx_boe_p2p_register_11

typedef struct _rs_tx_boe_tx_boe_p2p_register_11  rs_tx_boe_tx_boe_p2p_register_11;
struct _rs_tx_boe_tx_boe_p2p_register_11 {
    unsigned int reg_boe_tx_v_scram_reset_lane10            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane11            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_11(val) ((rs_tx_boe_tx_boe_p2p_register_11*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_12                                    (HV_BOE_TX_BASE_ADDRESS + 0x30)

#define TX_BOE_TX_BOE_P2P_REGISTER_12_struct                             rs_tx_boe_tx_boe_p2p_register_12

typedef struct _rs_tx_boe_tx_boe_p2p_register_12  rs_tx_boe_tx_boe_p2p_register_12;
struct _rs_tx_boe_tx_boe_p2p_register_12 {
    unsigned int reg_boe_tx_v_scram_reset_lane12            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane13            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_12(val) ((rs_tx_boe_tx_boe_p2p_register_12*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_13                                    (HV_BOE_TX_BASE_ADDRESS + 0x34)

#define TX_BOE_TX_BOE_P2P_REGISTER_13_struct                             rs_tx_boe_tx_boe_p2p_register_13

typedef struct _rs_tx_boe_tx_boe_p2p_register_13  rs_tx_boe_tx_boe_p2p_register_13;
struct _rs_tx_boe_tx_boe_p2p_register_13 {
    unsigned int reg_boe_tx_v_scram_reset_lane14            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane15            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_13(val) ((rs_tx_boe_tx_boe_p2p_register_13*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_14                                    (HV_BOE_TX_BASE_ADDRESS + 0x38)

#define TX_BOE_TX_BOE_P2P_REGISTER_14_struct                             rs_tx_boe_tx_boe_p2p_register_14

typedef struct _rs_tx_boe_tx_boe_p2p_register_14  rs_tx_boe_tx_boe_p2p_register_14;
struct _rs_tx_boe_tx_boe_p2p_register_14 {
    unsigned int reg_boe_tx_v_scram_reset_lane16            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane17            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_14(val) ((rs_tx_boe_tx_boe_p2p_register_14*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_15                                    (HV_BOE_TX_BASE_ADDRESS + 0x3C)

#define TX_BOE_TX_BOE_P2P_REGISTER_15_struct                             rs_tx_boe_tx_boe_p2p_register_15

typedef struct _rs_tx_boe_tx_boe_p2p_register_15  rs_tx_boe_tx_boe_p2p_register_15;
struct _rs_tx_boe_tx_boe_p2p_register_15 {
    unsigned int reg_boe_tx_v_scram_reset_lane18            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane19            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_15(val) ((rs_tx_boe_tx_boe_p2p_register_15*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_16                                    (HV_BOE_TX_BASE_ADDRESS + 0x40)

#define TX_BOE_TX_BOE_P2P_REGISTER_16_struct                             rs_tx_boe_tx_boe_p2p_register_16

typedef struct _rs_tx_boe_tx_boe_p2p_register_16  rs_tx_boe_tx_boe_p2p_register_16;
struct _rs_tx_boe_tx_boe_p2p_register_16 {
    unsigned int reg_boe_tx_v_scram_reset_lane20            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane21            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_16(val) ((rs_tx_boe_tx_boe_p2p_register_16*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_17                                    (HV_BOE_TX_BASE_ADDRESS + 0x44)

#define TX_BOE_TX_BOE_P2P_REGISTER_17_struct                             rs_tx_boe_tx_boe_p2p_register_17

typedef struct _rs_tx_boe_tx_boe_p2p_register_17  rs_tx_boe_tx_boe_p2p_register_17;
struct _rs_tx_boe_tx_boe_p2p_register_17 {
    unsigned int reg_boe_tx_v_scram_reset_lane22            :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_v_scram_reset_lane23            :15;
    unsigned int reserved_1                                 : 1;
};
#define tx_boe_tx_boe_p2p_register_17(val) ((rs_tx_boe_tx_boe_p2p_register_17*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_0                           (HV_BOE_TX_BASE_ADDRESS + 0x48)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_0_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_0

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_0  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_0;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_0 {
    unsigned int reg_boe_tx_ctrl_l_pol_patt_lane00          : 8;
    unsigned int reg_boe_tx_ctrl_l_pol2_patt_lane00         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol3_patt_lane00         : 8;
    unsigned int reg_boe_tx_ctrl_l_LD_R_lane00              : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_0(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_0*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_1                           (HV_BOE_TX_BASE_ADDRESS + 0x4C)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_1_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_1

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_1  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_1;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_1 {
    unsigned int reg_boe_tx_ctrl_l_LD_W_lane00              : 8;
    unsigned int reg_boe_tx_ctrl_l_CS_lane00                : 2;
    unsigned int reg_boe_tx_ctrl_l_LOAD_lane00              : 2;
    unsigned int reg_boe_tx_ctrl_l_SD_CONDIF_lane00         : 8;
    unsigned int reg_boe_tx_ctrl_f_IMPC_lane00              : 3;
    unsigned int reg_boe_tx_ctrl_f_LS_lane00                : 5;
    unsigned int reg_boe_tx_ctrl_f_PCH_lane00               : 2;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_1(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_1*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_2                           (HV_BOE_TX_BASE_ADDRESS + 0x50)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_2_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_2

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_2  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_2;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_2 {
    unsigned int reg_boe_tx_ctrl_f_PCL_lane00               : 8;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L0_lane00          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L0_lane00          : 3;
    unsigned int reg_boe_tx_ctrl_f_GMA_CHOP_lane00          : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L1_lane00          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L1_lane00          : 3;
    unsigned int reg_boe_tx_ctrl_f_SD_CHOP_lane00           : 3;
    unsigned int reg_boe_tx_ctrl_f_EQ_SW_L2_lane00          : 2;
    unsigned int reg_boe_tx_ctrl_f_EQ_DC_L2_lane00          : 3;
    unsigned int reg_boe_tx_ctrl_f_CH_SEL_lane00            : 3;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_2(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_2*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_3                           (HV_BOE_TX_BASE_ADDRESS + 0x54)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_3_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_3

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_3  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_3;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_3 {
    unsigned int reg_boe_tx_ctrl_f_GMAEN_lane00             : 1;
    unsigned int reg_boe_tx_ctrl_f_SDC_lane00               : 1;
    unsigned int reg_boe_tx_ctrl_f_DPOLINV_lane00           : 1;
    unsigned int reg_boe_tx_ctrl_f_GMASM_lane00             : 2;
    unsigned int reg_boe_tx_ctrl_f_CONFIGB_lane00           : 4;
    unsigned int reg_boe_tx_ctrl_f_RXBIAS_lane00            : 2;
    unsigned int reg_boe_tx_ctrl_f_CSB_MODE_lane00          : 2;
    unsigned int reg_boe_tx_ctrl_f_INV_MODE_lane00          : 2;
    unsigned int reserved                                   : 1;
    unsigned int reg_boe_tx_ctrl_f_HAVDD                    : 8;
    unsigned int reg_boe_tx_ctrl_f_VCOM                     : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_3(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_3*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_4                           (HV_BOE_TX_BASE_ADDRESS + 0x58)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_4_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_4

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_4  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_4;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_4 {
    unsigned int reg_boe_tx_ctrl_f_GMA1                     : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA2                     : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA3                     : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA4                     : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_4(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_4*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_5                           (HV_BOE_TX_BASE_ADDRESS + 0x5C)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_5_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_5

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_5  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_5;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_5 {
    unsigned int reg_boe_tx_ctrl_f_GMA5                     : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA6                     : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA7                     : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA8                     : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_5(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_5*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_6                           (HV_BOE_TX_BASE_ADDRESS + 0x60)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_6_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_6

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_6  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_6;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_6 {
    unsigned int reg_boe_tx_ctrl_f_GMA9                     : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA10                    : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA11                    : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA12                    : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_6(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_6*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_7                           (HV_BOE_TX_BASE_ADDRESS + 0x64)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_7_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_7

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_7  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_7;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_7 {
    unsigned int reg_boe_tx_ctrl_f_GMA13                    : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA14                    : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA15                    : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA16                    : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_7(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_7*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_8                           (HV_BOE_TX_BASE_ADDRESS + 0x68)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_8_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_8

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_8  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_8;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_8 {
    unsigned int reg_boe_tx_ctrl_f_GMA17                    : 8;
    unsigned int reg_boe_tx_ctrl_f_GMA18                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST1                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST2                    : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_8(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_8*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_9                           (HV_BOE_TX_BASE_ADDRESS + 0x6C)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_9_struct                    rs_tx_boe_tx_boe_p2p_ctrl_packet_config_9

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_9  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_9;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_9 {
    unsigned int reg_boe_tx_ctrl_f_TEST3                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST4                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST5                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST6                    : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_9(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_9*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_10                          (HV_BOE_TX_BASE_ADDRESS + 0x70)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_10_struct                   rs_tx_boe_tx_boe_p2p_ctrl_packet_config_10

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_10  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_10;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_10 {
    unsigned int reg_boe_tx_ctrl_f_TEST7                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST8                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST9                    : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST10                   : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_10(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_10*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_11                          (HV_BOE_TX_BASE_ADDRESS + 0x74)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_11_struct                   rs_tx_boe_tx_boe_p2p_ctrl_packet_config_11

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_11  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_11;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_11 {
    unsigned int reg_boe_tx_ctrl_f_TEST11                   : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST12                   : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST13                   : 8;
    unsigned int reg_boe_tx_ctrl_f_TEST14                   : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_11(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_11*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_12                          (HV_BOE_TX_BASE_ADDRESS + 0x78)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_12_struct                   rs_tx_boe_tx_boe_p2p_ctrl_packet_config_12

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_12  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_12;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_12 {
    unsigned int reg_boe_tx_ctrl_f_TEST15                   : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB1                     : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB2                     : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB3                     : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_12(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_12*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_13                          (HV_BOE_TX_BASE_ADDRESS + 0x7C)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_13_struct                   rs_tx_boe_tx_boe_p2p_ctrl_packet_config_13

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_13  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_13;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_13 {
    unsigned int reg_boe_tx_ctrl_f_CSB4                     : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB5                     : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB6                     : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB7                     : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_13(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_13*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_14                          (HV_BOE_TX_BASE_ADDRESS + 0x80)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_14_struct                   rs_tx_boe_tx_boe_p2p_ctrl_packet_config_14

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_14  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_14;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_14 {
    unsigned int reg_boe_tx_ctrl_f_CSB8                     : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB9                     : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB10                    : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB11                    : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_14(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_14*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_15                          (HV_BOE_TX_BASE_ADDRESS + 0x84)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_15_struct                   rs_tx_boe_tx_boe_p2p_ctrl_packet_config_15

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_15  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_15;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_15 {
    unsigned int reg_boe_tx_ctrl_f_CSB12                    : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB13                    : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB14                    : 8;
    unsigned int reg_boe_tx_ctrl_f_CSB15                    : 8;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_15(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_15*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_16                          (HV_BOE_TX_BASE_ADDRESS + 0x88)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_CONFIG_16_struct                   rs_tx_boe_tx_boe_p2p_ctrl_packet_config_16

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_16  rs_tx_boe_tx_boe_p2p_ctrl_packet_config_16;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_config_16 {
    unsigned int reg_boe_tx_ctrl_f_CSB16                    : 8;
    unsigned int reg_boe_tx_PORSD_frame_num                 : 4;
    unsigned int reg_boe_tx_lsp_to_disp_mode_sel            : 1;
    unsigned int reg_boe_tx_v_blanking_dummy_line_num       :15;
    unsigned int reg_boe_tx_ctrl_f_PORSD_dbg_mode           : 1;
    unsigned int reg_boe_tx_ctrl_f_PORSD_dbg_value          : 1;
    unsigned int reg_boe_tx_ctrl_f_vclr_latch_en            : 1;
    unsigned int reserved                                   : 1;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_config_16(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_config_16*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_100                                   (HV_BOE_TX_BASE_ADDRESS + 0x8C)

#define TX_BOE_TX_BOE_P2P_REGISTER_100_struct                            rs_tx_boe_tx_boe_p2p_register_100

typedef struct _rs_tx_boe_tx_boe_p2p_register_100  rs_tx_boe_tx_boe_p2p_register_100;
struct _rs_tx_boe_tx_boe_p2p_register_100 {
    unsigned int reg_boe_tx_lsp_k3_position_lane0           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane1           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane2           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane3           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane4           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane5           : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx_boe_p2p_register_100(val) ((rs_tx_boe_tx_boe_p2p_register_100*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_101                                   (HV_BOE_TX_BASE_ADDRESS + 0x90)

#define TX_BOE_TX_BOE_P2P_REGISTER_101_struct                            rs_tx_boe_tx_boe_p2p_register_101

typedef struct _rs_tx_boe_tx_boe_p2p_register_101  rs_tx_boe_tx_boe_p2p_register_101;
struct _rs_tx_boe_tx_boe_p2p_register_101 {
    unsigned int reg_boe_tx_lsp_k3_position_lane6           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane7           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane8           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane9           : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane10          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane11          : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx_boe_p2p_register_101(val) ((rs_tx_boe_tx_boe_p2p_register_101*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_102                                   (HV_BOE_TX_BASE_ADDRESS + 0x94)

#define TX_BOE_TX_BOE_P2P_REGISTER_102_struct                            rs_tx_boe_tx_boe_p2p_register_102

typedef struct _rs_tx_boe_tx_boe_p2p_register_102  rs_tx_boe_tx_boe_p2p_register_102;
struct _rs_tx_boe_tx_boe_p2p_register_102 {
    unsigned int reg_boe_tx_lsp_k3_position_lane12          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane13          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane14          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane15          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane16          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane17          : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx_boe_p2p_register_102(val) ((rs_tx_boe_tx_boe_p2p_register_102*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_103                                   (HV_BOE_TX_BASE_ADDRESS + 0x98)

#define TX_BOE_TX_BOE_P2P_REGISTER_103_struct                            rs_tx_boe_tx_boe_p2p_register_103

typedef struct _rs_tx_boe_tx_boe_p2p_register_103  rs_tx_boe_tx_boe_p2p_register_103;
struct _rs_tx_boe_tx_boe_p2p_register_103 {
    unsigned int reg_boe_tx_lsp_k3_position_lane18          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane19          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane20          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane21          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane22          : 5;
    unsigned int reg_boe_tx_lsp_k3_position_lane23          : 5;
    unsigned int reserved                                   : 2;
};
#define tx_boe_tx_boe_p2p_register_103(val) ((rs_tx_boe_tx_boe_p2p_register_103*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_104                                   (HV_BOE_TX_BASE_ADDRESS + 0x9C)

#define TX_BOE_TX_BOE_P2P_REGISTER_104_struct                            rs_tx_boe_tx_boe_p2p_register_104

typedef struct _rs_tx_boe_tx_boe_p2p_register_104  rs_tx_boe_tx_boe_p2p_register_104;
struct _rs_tx_boe_tx_boe_p2p_register_104 {
    unsigned int reg_boe_tx_lane_delay_num_lane0            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane1            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane2            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane3            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane4            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane5            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane6            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane7            : 4;
};
#define tx_boe_tx_boe_p2p_register_104(val) ((rs_tx_boe_tx_boe_p2p_register_104*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_105                                   (HV_BOE_TX_BASE_ADDRESS + 0xA0)

#define TX_BOE_TX_BOE_P2P_REGISTER_105_struct                            rs_tx_boe_tx_boe_p2p_register_105

typedef struct _rs_tx_boe_tx_boe_p2p_register_105  rs_tx_boe_tx_boe_p2p_register_105;
struct _rs_tx_boe_tx_boe_p2p_register_105 {
    unsigned int reg_boe_tx_lane_delay_num_lane8            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane9            : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane10           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane11           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane12           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane13           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane14           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane15           : 4;
};
#define tx_boe_tx_boe_p2p_register_105(val) ((rs_tx_boe_tx_boe_p2p_register_105*)&(val))



#define TX_BOE_TX_BOE_P2P_REGISTER_106                                   (HV_BOE_TX_BASE_ADDRESS + 0xA4)

#define TX_BOE_TX_BOE_P2P_REGISTER_106_struct                            rs_tx_boe_tx_boe_p2p_register_106

typedef struct _rs_tx_boe_tx_boe_p2p_register_106  rs_tx_boe_tx_boe_p2p_register_106;
struct _rs_tx_boe_tx_boe_p2p_register_106 {
    unsigned int reg_boe_tx_lane_delay_num_lane16           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane17           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane18           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane19           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane20           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane21           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane22           : 4;
    unsigned int reg_boe_tx_lane_delay_num_lane23           : 4;
};
#define tx_boe_tx_boe_p2p_register_106(val) ((rs_tx_boe_tx_boe_p2p_register_106*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_REGISTER                                  (HV_BOE_TX_BASE_ADDRESS + 0xA8)

#define TX_BOE_TX_BOE_P2P_CTRL_REGISTER_struct                           rs_tx_boe_tx_boe_p2p_ctrl_register

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_register  rs_tx_boe_tx_boe_p2p_ctrl_register;
struct _rs_tx_boe_tx_boe_p2p_ctrl_register {
    unsigned int reg_boe_tx_enable                          : 1;
    unsigned int reg_boe_tx_training_timeout_time           :12;
    unsigned int reg_boe_tx_mode3_auto_det_en               : 1;
    unsigned int reg_boe_tx_lsp_scr_en                      : 1;
    unsigned int reg_boe_tx_ctrl_l_scr_en                   : 1;
    unsigned int reg_boe_tx_ctrl_f_scr_en                   : 1;
    unsigned int reg_boe_tx_idle_scr_en                     : 1;
    unsigned int reg_boe_tx_vbp_scr_en                      : 1;
    unsigned int reg_boe_tx_pack_mode                       : 1;
    unsigned int reserved                                   :12;
};
#define tx_boe_tx_boe_p2p_ctrl_register(val) ((rs_tx_boe_tx_boe_p2p_ctrl_register*)&(val))



#define TX_BOE_TX_BOE_P2P_ABNORMAL_DETECT                                (HV_BOE_TX_BASE_ADDRESS + 0xAC)

#define TX_BOE_TX_BOE_P2P_ABNORMAL_DETECT_struct                         rs_tx_boe_tx_boe_p2p_abnormal_detect

typedef struct _rs_tx_boe_tx_boe_p2p_abnormal_detect  rs_tx_boe_tx_boe_p2p_abnormal_detect;
struct _rs_tx_boe_tx_boe_p2p_abnormal_detect {
    unsigned int reg_boe_tx_abnormal_h_cnt_detect_en        : 1;
    unsigned int reg_boe_tx_abnormal_h_cnt_end              :15;
    unsigned int reg_boe_h_clr_jmp_to_idle_en               : 1;
    unsigned int reserved                                   :15;
};
#define tx_boe_tx_boe_p2p_abnormal_detect(val) ((rs_tx_boe_tx_boe_p2p_abnormal_detect*)&(val))



#define TX_BOE_TX_BOE_P2P_BCC_CTRL_1                                     (HV_BOE_TX_BASE_ADDRESS + 0xB0)

#define TX_BOE_TX_BOE_P2P_BCC_CTRL_1_struct                              rs_tx_boe_tx_boe_p2p_bcc_ctrl_1

typedef struct _rs_tx_boe_tx_boe_p2p_bcc_ctrl_1  rs_tx_boe_tx_boe_p2p_bcc_ctrl_1;
struct _rs_tx_boe_tx_boe_p2p_bcc_ctrl_1 {
    unsigned int reg_bcc_cmd_start_sel                      : 1;
    unsigned int reg_bcc_cmd_start                          : 1;
    unsigned int reg_bcc_cmd_start_delay_time               : 8;
    unsigned int reg_bcc_mode1_dc_read_en                   : 1;
    unsigned int reg_bcc_mode1_ia_pull_low_en               : 1;
    unsigned int reg_boe_tx_bcc_receive_en                  : 1;
    unsigned int reg_boe_tx_bcc_receive_clear               : 1;
    unsigned int reserved                                   :18;
};
#define tx_boe_tx_boe_p2p_bcc_ctrl_1(val) ((rs_tx_boe_tx_boe_p2p_bcc_ctrl_1*)&(val))



#define TX_BOE_TX_BOE_P2P_BCC_CTRL_2                                     (HV_BOE_TX_BASE_ADDRESS + 0xB4)

#define TX_BOE_TX_BOE_P2P_BCC_CTRL_2_struct                              rs_tx_boe_tx_boe_p2p_bcc_ctrl_2

typedef struct _rs_tx_boe_tx_boe_p2p_bcc_ctrl_2  rs_tx_boe_tx_boe_p2p_bcc_ctrl_2;
struct _rs_tx_boe_tx_boe_p2p_bcc_ctrl_2 {
    unsigned int reg_bcc_mode1_ia_pull_low_sel_23to0        :24;
    unsigned int reg_bcc_mode1_ia_pull_low_time             : 8;
};
#define tx_boe_tx_boe_p2p_bcc_ctrl_2(val) ((rs_tx_boe_tx_boe_p2p_bcc_ctrl_2*)&(val))



#define TX_BOE_TX_BOE_P2P_DEBUG_REGISTER_0                               (HV_BOE_TX_BASE_ADDRESS + 0xB8)

#define TX_BOE_TX_BOE_P2P_DEBUG_REGISTER_0_struct                        rs_tx_boe_tx_boe_p2p_debug_register_0

typedef struct _rs_tx_boe_tx_boe_p2p_debug_register_0  rs_tx_boe_tx_boe_p2p_debug_register_0;
struct _rs_tx_boe_tx_boe_p2p_debug_register_0 {
    unsigned int reg_boe_tx_debug_force_bcc_mode3_en        : 1;
    unsigned int reg_boe_tx_debug_force_lock_en             : 1;
    unsigned int reg_boe_tx_debug_force_training_en         : 1;
    unsigned int reg_boe_tx_debug_force_irq_en              : 1;
    unsigned int reg_boe_tx_training_timeout_flag_clr       : 1;
    unsigned int reserved                                   :27;
};
#define tx_boe_tx_boe_p2p_debug_register_0(val) ((rs_tx_boe_tx_boe_p2p_debug_register_0*)&(val))



#define TX_BOE_TX_BOE_P2P_DEBUG_REGISTER_1                               (HV_BOE_TX_BASE_ADDRESS + 0xBC)

#define TX_BOE_TX_BOE_P2P_DEBUG_REGISTER_1_struct                        rs_tx_boe_tx_boe_p2p_debug_register_1

typedef struct _rs_tx_boe_tx_boe_p2p_debug_register_1  rs_tx_boe_tx_boe_p2p_debug_register_1;
struct _rs_tx_boe_tx_boe_p2p_debug_register_1 {
    unsigned int reg_boe_tx_debug_rgb_en                    : 1;
    unsigned int reg_boe_tx_debug_rgb_value_r               :10;
    unsigned int reg_boe_tx_debug_rgb_value_g               :10;
    unsigned int reg_boe_tx_debug_rgb_value_b               :10;
    unsigned int reserved                                   : 1;
};
#define tx_boe_tx_boe_p2p_debug_register_1(val) ((rs_tx_boe_tx_boe_p2p_debug_register_1*)&(val))



#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_POL_CONFIG                         (HV_BOE_TX_BASE_ADDRESS + 0xC0)

#define TX_BOE_TX_BOE_P2P_CTRL_PACKET_POL_CONFIG_struct                  rs_tx_boe_tx_boe_p2p_ctrl_packet_pol_config

typedef struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_pol_config  rs_tx_boe_tx_boe_p2p_ctrl_packet_pol_config;
struct _rs_tx_boe_tx_boe_p2p_ctrl_packet_pol_config {
    unsigned int reg_boe_tx_ctrl_l_polc_patt_lane00         : 8;
    unsigned int reg_boe_tx_ctrl_l_pol_sel                  : 1;
    unsigned int reg_boe_tx_ctrl_l_polc_sel                 : 1;
    unsigned int reg_boe_tx_ctrl_l_pol2_sel                 : 1;
    unsigned int reg_boe_tx_ctrl_l_pol3_sel                 : 1;
    unsigned int reg_boe_tx_LD_dbg_delay                    : 8;
    unsigned int reg_boe_tx_ctrl_use_same_setting           : 1;
    unsigned int reserved                                   :11;
};
#define tx_boe_tx_boe_p2p_ctrl_packet_pol_config(val) ((rs_tx_boe_tx_boe_p2p_ctrl_packet_pol_config*)&(val))



#define TX_BOE_TX_BOE_P2P_BCC_CTRL_3                                     (HV_BOE_TX_BASE_ADDRESS + 0xC4)

#define TX_BOE_TX_BOE_P2P_BCC_CTRL_3_struct                              rs_tx_boe_tx_boe_p2p_bcc_ctrl_3

typedef struct _rs_tx_boe_tx_boe_p2p_bcc_ctrl_3  rs_tx_boe_tx_boe_p2p_bcc_ctrl_3;
struct _rs_tx_boe_tx_boe_p2p_bcc_ctrl_3 {
    unsigned int reg_bcc_mode1_ia_pull_low_sel_47to24       :24;
    unsigned int reserved                                   : 8;
};
#define tx_boe_tx_boe_p2p_bcc_ctrl_3(val) ((rs_tx_boe_tx_boe_p2p_bcc_ctrl_3*)&(val))



#define TX_BOE_TX_BOE_P2P_POL_INV_0                                      (HV_BOE_TX_BASE_ADDRESS + 0xC8)

#define TX_BOE_TX_BOE_P2P_POL_INV_0_struct                               rs_tx_boe_tx_boe_p2p_pol_inv_0

typedef struct _rs_tx_boe_tx_boe_p2p_pol_inv_0  rs_tx_boe_tx_boe_p2p_pol_inv_0;
struct _rs_tx_boe_tx_boe_p2p_pol_inv_0 {
    unsigned int reg_boe_tx_ptg_pol0_inv_lane00             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane01             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane02             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane03             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane04             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane05             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane06             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane07             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane08             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane09             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane10             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane11             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane12             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane13             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane14             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane15             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane16             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane17             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane18             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane19             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane20             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane21             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane22             : 1;
    unsigned int reg_boe_tx_ptg_pol0_inv_lane23             : 1;
    unsigned int reserved                                   : 8;
};
#define tx_boe_tx_boe_p2p_pol_inv_0(val) ((rs_tx_boe_tx_boe_p2p_pol_inv_0*)&(val))



#define TX_BOE_TX_BOE_P2P_POL_INV_1                                      (HV_BOE_TX_BASE_ADDRESS + 0xCC)

#define TX_BOE_TX_BOE_P2P_POL_INV_1_struct                               rs_tx_boe_tx_boe_p2p_pol_inv_1

typedef struct _rs_tx_boe_tx_boe_p2p_pol_inv_1  rs_tx_boe_tx_boe_p2p_pol_inv_1;
struct _rs_tx_boe_tx_boe_p2p_pol_inv_1 {
    unsigned int reg_boe_tx_ptg_pol1_inv_lane00             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane01             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane02             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane03             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane04             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane05             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane06             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane07             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane08             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane09             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane10             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane11             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane12             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane13             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane14             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane15             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane16             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane17             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane18             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane19             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane20             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane21             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane22             : 1;
    unsigned int reg_boe_tx_ptg_pol1_inv_lane23             : 1;
    unsigned int reserved                                   : 8;
};
#define tx_boe_tx_boe_p2p_pol_inv_1(val) ((rs_tx_boe_tx_boe_p2p_pol_inv_1*)&(val))



#define TX_BOE_TX_BOE_P2P_POL_INV_2                                      (HV_BOE_TX_BASE_ADDRESS + 0xD0)

#define TX_BOE_TX_BOE_P2P_POL_INV_2_struct                               rs_tx_boe_tx_boe_p2p_pol_inv_2

typedef struct _rs_tx_boe_tx_boe_p2p_pol_inv_2  rs_tx_boe_tx_boe_p2p_pol_inv_2;
struct _rs_tx_boe_tx_boe_p2p_pol_inv_2 {
    unsigned int reg_boe_tx_ptg_pol2_inv_lane00             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane01             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane02             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane03             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane04             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane05             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane06             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane07             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane08             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane09             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane10             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane11             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane12             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane13             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane14             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane15             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane16             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane17             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane18             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane19             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane20             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane21             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane22             : 1;
    unsigned int reg_boe_tx_ptg_pol2_inv_lane23             : 1;
    unsigned int reserved                                   : 8;
};
#define tx_boe_tx_boe_p2p_pol_inv_2(val) ((rs_tx_boe_tx_boe_p2p_pol_inv_2*)&(val))



#define TX_BOE_TX_BOE_P2P_POL_INV_3                                      (HV_BOE_TX_BASE_ADDRESS + 0xD4)

#define TX_BOE_TX_BOE_P2P_POL_INV_3_struct                               rs_tx_boe_tx_boe_p2p_pol_inv_3

typedef struct _rs_tx_boe_tx_boe_p2p_pol_inv_3  rs_tx_boe_tx_boe_p2p_pol_inv_3;
struct _rs_tx_boe_tx_boe_p2p_pol_inv_3 {
    unsigned int reg_boe_tx_ptg_pol3_inv_lane00             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane01             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane02             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane03             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane04             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane05             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane06             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane07             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane08             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane09             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane10             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane11             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane12             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane13             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane14             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane15             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane16             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane17             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane18             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane19             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane20             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane21             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane22             : 1;
    unsigned int reg_boe_tx_ptg_pol3_inv_lane23             : 1;
    unsigned int reserved                                   : 8;
};
#define tx_boe_tx_boe_p2p_pol_inv_3(val) ((rs_tx_boe_tx_boe_p2p_pol_inv_3*)&(val))



#endif