#ifndef _HV_PAGE_HT7315_SH08_TOP_STBY_H_
#define _HV_PAGE_HT7315_SH08_TOP_STBY_H_

#ifndef HV_SH08_TOP_STBY_BASE_ADDRESS
    #define HV_SH08_TOP_STBY_BASE_ADDRESS                                         0x11008400
#endif


#define STANDBY_SH08_TOP_STBY_CTRL_0                                     (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x00)

#define STANDBY_SH08_TOP_STBY_CTRL_0_struct                              rs_standby_sh08_top_stby_ctrl_0

typedef struct _rs_standby_sh08_top_stby_ctrl_0  rs_standby_sh08_top_stby_ctrl_0;
struct _rs_standby_sh08_top_stby_ctrl_0 {
    unsigned int reg_dbgi2c_scl_func_sel                    : 1;
    unsigned int reg_dbgi2c_sda_func_sel                    : 1;
    unsigned int reg_dp_rx0_cable_func_sel                  : 1;
    unsigned int reg_dp_rx0_hpd_func_sel                    : 1;
    unsigned int reg_dp_rx1_cable_func_sel                  : 1;
    unsigned int reg_stby_gp5_func_sel                      : 1;
    unsigned int reg_hdmi_rx0_cable_det_func_sel            : 1;
    unsigned int reg_hdmi_rx0_cec_func_sel                  : 2;
    unsigned int reg_hdmi_rx0_ddc0_func_sel                 : 1;
    unsigned int reg_hdmi_rx1_cable_det_func_sel            : 1;
    unsigned int reg_hdmi_rx1_cec_func_sel                  : 2;
    unsigned int reg_hdmi_rx1_ddc0_func_sel                 : 1;
    unsigned int reg_mi2c_scl_func_sel                      : 1;
    unsigned int reg_mi2c_sda_func_sel                      : 1;
    unsigned int reg_prog_spi_clk_func_sel                  : 1;
    unsigned int reg_prog_spi_csn_func_sel                  : 1;
    unsigned int reg_prog_spi_hold_func_sel                 : 1;
    unsigned int reg_prog_spi_miso_func_sel                 : 1;
    unsigned int reg_prog_spi_mosi_func_sel                 : 1;
    unsigned int reg_prog_spi_wp_func_sel                   : 1;
    unsigned int reg_stby_gp0_func_sel                      : 1;
    unsigned int reg_stby_gp1_func_sel                      : 1;
    unsigned int reg_stby_gp2_func_sel                      : 1;
    unsigned int reg_stby_gp3_func_sel                      : 2;
    unsigned int reg_stby_gp4_func_sel                      : 1;
    unsigned int reg_dp_rx1_hpd_func_sel                    : 2;
    unsigned int reg_aux_dprx0_gpio_in_in_sel               : 2;
};
#define standby_sh08_top_stby_ctrl_0(val) ((rs_standby_sh08_top_stby_ctrl_0*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_4                                     (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x04)

#define STANDBY_SH08_TOP_STBY_CTRL_4_struct                              rs_standby_sh08_top_stby_ctrl_4

typedef struct _rs_standby_sh08_top_stby_ctrl_4  rs_standby_sh08_top_stby_ctrl_4;
struct _rs_standby_sh08_top_stby_ctrl_4 {
    unsigned int reg_dp0_cable_in_sel                       : 2;
    unsigned int reg_dp1_cable_in_sel                       : 2;
    unsigned int reg_hdmi0_rx_cable_det_in_sel              : 2;
    unsigned int reg_hdmi1_rx_cable_det_in_sel              : 2;
    unsigned int reg_hdmi_rx0_cec_in_in_sel                 : 2;
    unsigned int reg_hdmi_rx0_ddc0_in_in_sel                : 2;
    unsigned int reg_hdmi_rx0_ddc1_in_in_sel                : 2;
    unsigned int reg_hdmi_rx1_cec_in_in_sel                 : 2;
    unsigned int reg_hdmi_rx1_ddc0_in_in_sel                : 2;
    unsigned int reg_hdmi_rx1_ddc1_in_in_sel                : 2;
    unsigned int reg_mi2c_sda_in_in_sel                     : 2;
    unsigned int reg_stby_gpio_i_in_sel                     : 2;
    unsigned int reg_uart_rxd_i_in_sel                      : 2;
    unsigned int reg_aux_dprx1_gpio_in_in_sel               : 2;
    unsigned int reg_uart0_sin_in_sel                       : 2;
    unsigned int reg_other_pin_sel                          : 2;
};
#define standby_sh08_top_stby_ctrl_4(val) ((rs_standby_sh08_top_stby_ctrl_4*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_8                                     (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x08)

#define STANDBY_SH08_TOP_STBY_CTRL_8_struct                              rs_standby_sh08_top_stby_ctrl_8

typedef struct _rs_standby_sh08_top_stby_ctrl_8  rs_standby_sh08_top_stby_ctrl_8;
struct _rs_standby_sh08_top_stby_ctrl_8 {
    unsigned int reg_dbgi2c_scl_io_ctrl                     : 8;
    unsigned int reg_dbgi2c_sda_io_ctrl                     : 8;
    unsigned int reg_dp_rx0_cable_io_ctrl                   : 8;
    unsigned int reg_dp_rx0_hpd_io_ctrl                     : 8;
};
#define standby_sh08_top_stby_ctrl_8(val) ((rs_standby_sh08_top_stby_ctrl_8*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_C                                     (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x0C)

#define STANDBY_SH08_TOP_STBY_CTRL_C_struct                              rs_standby_sh08_top_stby_ctrl_c

typedef struct _rs_standby_sh08_top_stby_ctrl_c  rs_standby_sh08_top_stby_ctrl_c;
struct _rs_standby_sh08_top_stby_ctrl_c {
    unsigned int reg_dp_rx1_cable_io_ctrl                   : 8;
    unsigned int reg_dp_rx1_hpd_io_ctrl                     : 8;
    unsigned int reg_hdmi_rx0_cable_det_io_ctrl             : 5;
    unsigned int reg_hdmi_rx0_cec_io_ctrl                   : 5;
    unsigned int reserved                                   : 6;
};
#define standby_sh08_top_stby_ctrl_c(val) ((rs_standby_sh08_top_stby_ctrl_c*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_10                                    (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x10)

#define STANDBY_SH08_TOP_STBY_CTRL_10_struct                             rs_standby_sh08_top_stby_ctrl_10

typedef struct _rs_standby_sh08_top_stby_ctrl_10  rs_standby_sh08_top_stby_ctrl_10;
struct _rs_standby_sh08_top_stby_ctrl_10 {
    unsigned int reg_hdmi_rx0_ddc0_io_ctrl                  : 5;
    unsigned int reg_hdmi_rx0_ddc1_io_ctrl                  : 5;
    unsigned int reg_hdmi_rx1_cable_det_io_ctrl             : 5;
    unsigned int reg_hdmi_rx1_cec_io_ctrl                   : 5;
    unsigned int reserved                                   :12;
};
#define standby_sh08_top_stby_ctrl_10(val) ((rs_standby_sh08_top_stby_ctrl_10*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_14                                    (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x14)

#define STANDBY_SH08_TOP_STBY_CTRL_14_struct                             rs_standby_sh08_top_stby_ctrl_14

typedef struct _rs_standby_sh08_top_stby_ctrl_14  rs_standby_sh08_top_stby_ctrl_14;
struct _rs_standby_sh08_top_stby_ctrl_14 {
    unsigned int reg_hdmi_rx1_ddc0_io_ctrl                  : 5;
    unsigned int reg_hdmi_rx1_ddc1_io_ctrl                  : 5;
    unsigned int reserved                                   : 6;
    unsigned int reg_mi2c_scl_io_ctrl                       : 8;
    unsigned int reg_mi2c_sda_io_ctrl                       : 8;
};
#define standby_sh08_top_stby_ctrl_14(val) ((rs_standby_sh08_top_stby_ctrl_14*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_18                                    (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x18)

#define STANDBY_SH08_TOP_STBY_CTRL_18_struct                             rs_standby_sh08_top_stby_ctrl_18

typedef struct _rs_standby_sh08_top_stby_ctrl_18  rs_standby_sh08_top_stby_ctrl_18;
struct _rs_standby_sh08_top_stby_ctrl_18 {
    unsigned int reg_prog_spi_clk_io_ctrl                   : 8;
    unsigned int reg_prog_spi_csn_io_ctrl                   : 8;
    unsigned int reg_prog_spi_hold_io_ctrl                  : 8;
    unsigned int reg_prog_spi_miso_io_ctrl                  : 8;
};
#define standby_sh08_top_stby_ctrl_18(val) ((rs_standby_sh08_top_stby_ctrl_18*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_1C                                    (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x1C)

#define STANDBY_SH08_TOP_STBY_CTRL_1C_struct                             rs_standby_sh08_top_stby_ctrl_1c

typedef struct _rs_standby_sh08_top_stby_ctrl_1c  rs_standby_sh08_top_stby_ctrl_1c;
struct _rs_standby_sh08_top_stby_ctrl_1c {
    unsigned int reg_prog_spi_mosi_io_ctrl                  : 8;
    unsigned int reg_prog_spi_wp_io_ctrl                    : 8;
    unsigned int reg_stby_gp0_io_ctrl                       : 8;
    unsigned int reg_stby_gp1_io_ctrl                       : 5;
    unsigned int reserved                                   : 3;
};
#define standby_sh08_top_stby_ctrl_1c(val) ((rs_standby_sh08_top_stby_ctrl_1c*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_20                                    (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x20)

#define STANDBY_SH08_TOP_STBY_CTRL_20_struct                             rs_standby_sh08_top_stby_ctrl_20

typedef struct _rs_standby_sh08_top_stby_ctrl_20  rs_standby_sh08_top_stby_ctrl_20;
struct _rs_standby_sh08_top_stby_ctrl_20 {
    unsigned int reg_stby_gp2_io_ctrl                       : 5;
    unsigned int reg_stby_gp3_io_ctrl                       : 5;
    unsigned int reserved                                   : 6;
    unsigned int reg_stby_gp4_io_ctrl                       : 8;
    unsigned int reg_stby_gp5_io_ctrl                       : 8;
};
#define standby_sh08_top_stby_ctrl_20(val) ((rs_standby_sh08_top_stby_ctrl_20*)&(val))



#define STANDBY_SH08_TOP_STBY_CTRL_24                                    (HV_SH08_TOP_STBY_BASE_ADDRESS + 0x24)

#define STANDBY_SH08_TOP_STBY_CTRL_24_struct                             rs_standby_sh08_top_stby_ctrl_24

typedef struct _rs_standby_sh08_top_stby_ctrl_24  rs_standby_sh08_top_stby_ctrl_24;
struct _rs_standby_sh08_top_stby_ctrl_24 {
    unsigned int reg_stby_gp6_io_ctrl                       : 5;
    unsigned int reg_stby_gp7_io_ctrl                       : 5;
    unsigned int reg_uart_rxd_i_use_sel                     : 2;
    unsigned int reg_uart0_sin_use_sel                      : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_stby_gp6_func_sel                      : 1;
    unsigned int reg_stby_gp7_func_sel                      : 1;
    unsigned int reg_io_user_mode                           : 1;
    unsigned int reg_hdmi_rx0_ddc1_func_sel                 : 2;
    unsigned int reg_hdmi_rx1_ddc1_func_sel                 : 2;
    unsigned int reg_stby_gpio_i2_use_sel                   : 1;
    unsigned int reg_stby_gpio_i3_use_sel                   : 1;
    unsigned int reg_stby_gpio_i4_use_sel                   : 1;
    unsigned int reg_stby_gpio_i5_use_sel                   : 1;
    unsigned int reg_stby_gpio_i6_use_sel                   : 1;
    unsigned int reserved_1                                 : 4;
};
#define standby_sh08_top_stby_ctrl_24(val) ((rs_standby_sh08_top_stby_ctrl_24*)&(val))



#define STANDBY_SH08_TOP_STBY_RO_D0                                      (HV_SH08_TOP_STBY_BASE_ADDRESS + 0xD0)

#define STANDBY_SH08_TOP_STBY_RO_D0_struct                               rs_standby_sh08_top_stby_ro_d0

typedef struct _rs_standby_sh08_top_stby_ro_d0  rs_standby_sh08_top_stby_ro_d0;
struct _rs_standby_sh08_top_stby_ro_d0 {
    unsigned int regr_dbgi2c_scl_di                         : 1;
    unsigned int regr_dbgi2c_sda_di                         : 1;
    unsigned int regr_dp_rx0_cable_di                       : 1;
    unsigned int regr_dp_rx0_hpd_di                         : 1;
    unsigned int regr_dp_rx1_cable_di                       : 1;
    unsigned int regr_dp_rx1_hpd_di                         : 1;
    unsigned int regr_hdmi_rx0_cable_det_di                 : 1;
    unsigned int regr_hdmi_rx0_cec_di                       : 1;
    unsigned int regr_hdmi_rx0_ddc0_di                      : 1;
    unsigned int regr_hdmi_rx0_ddc1_di                      : 1;
    unsigned int regr_hdmi_rx1_cable_det_di                 : 1;
    unsigned int regr_hdmi_rx1_cec_di                       : 1;
    unsigned int regr_hdmi_rx1_ddc0_di                      : 1;
    unsigned int regr_hdmi_rx1_ddc1_di                      : 1;
    unsigned int regr_mi2c_scl_di                           : 1;
    unsigned int regr_mi2c_sda_di                           : 1;
    unsigned int regr_prog_spi_clk_di                       : 1;
    unsigned int regr_prog_spi_csn_di                       : 1;
    unsigned int regr_prog_spi_hold_di                      : 1;
    unsigned int regr_prog_spi_miso_di                      : 1;
    unsigned int regr_prog_spi_mosi_di                      : 1;
    unsigned int regr_prog_spi_wp_di                        : 1;
    unsigned int regr_stby_gp0_di                           : 1;
    unsigned int regr_stby_gp1_di                           : 1;
    unsigned int regr_stby_gp2_di                           : 1;
    unsigned int regr_stby_gp3_di                           : 1;
    unsigned int regr_stby_gp4_di                           : 1;
    unsigned int regr_stby_gp5_di                           : 1;
    unsigned int regr_stby_gp6_di                           : 1;
    unsigned int regr_stby_gp7_di                           : 1;
    unsigned int reserved                                   : 2;
};
#define standby_sh08_top_stby_ro_d0(val) ((rs_standby_sh08_top_stby_ro_d0*)&(val))



#endif