#ifndef _HV_PAGE_HT7315_KTX_PTG_01_H_
#define _HV_PAGE_HT7315_KTX_PTG_01_H_

#ifndef HV_KTX_PTG_01_BASE_ADDRESS
    #define HV_KTX_PTG_01_BASE_ADDRESS                                         0x1105ED00
#endif


#define TX_KTX_PTG_01_00                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x00)

#define TX_KTX_PTG_01_00_struct                                          rs_tx_ktx_ptg_01_00

typedef struct _rs_tx_ktx_ptg_01_00  rs_tx_ktx_ptg_01_00;
struct _rs_tx_ktx_ptg_01_00 {
    unsigned int reg_01_ktx_ptg0_base0_frm_timer            :13;
    unsigned int reg_01_ktx_ptg0_base0_frm_rst_phase_l      :13;
    unsigned int reg_01_ktx_ptg0_base0_frm_limited_width    : 6;
};
#define tx_ktx_ptg_01_00(val) ((rs_tx_ktx_ptg_01_00*)&(val))



#define TX_KTX_PTG_01_04                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x04)

#define TX_KTX_PTG_01_04_struct                                          rs_tx_ktx_ptg_01_04

typedef struct _rs_tx_ktx_ptg_01_04  rs_tx_ktx_ptg_01_04;
struct _rs_tx_ktx_ptg_01_04 {
    unsigned int reg_01_ktx_ptg0_base0_frm_patt             :32;
};
#define tx_ktx_ptg_01_04(val) ((rs_tx_ktx_ptg_01_04*)&(val))



#define TX_KTX_PTG_01_08                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x08)

#define TX_KTX_PTG_01_08_struct                                          rs_tx_ktx_ptg_01_08

typedef struct _rs_tx_ktx_ptg_01_08  rs_tx_ktx_ptg_01_08;
struct _rs_tx_ktx_ptg_01_08 {
    unsigned int reg_01_ktx_ptg0_base0_frm_cnt_enable       : 1;
    unsigned int reg_01_ktx_ptg0_base0_frm_rst_mode         : 1;
    unsigned int reg_01_ktx_ptg0_base0_frm_patt_type        : 5;
    unsigned int reg_01_ktx_ptg0_base0_time_up_phase        : 3;
    unsigned int reg_01_ktx_ptg0_base0_lc_flag_en           : 1;
    unsigned int reg_01_ktx_ptg0_base0_lc_flag1_en          : 1;
    unsigned int reg_01_ktx_ptg0_base0_inside_28s_enable    : 1;
    unsigned int reg_01_ktx_ptg0_base1_frm_cnt_enable       : 1;
    unsigned int reg_01_ktx_ptg0_base1_frm_rst_mode         : 1;
    unsigned int reg_01_ktx_ptg0_base1_frm_patt_type        : 5;
    unsigned int reg_01_ktx_ptg0_base1_time_up_phase        : 3;
    unsigned int reg_01_ktx_ptg0_base1_lc_flag_en           : 1;
    unsigned int reg_01_ktx_ptg0_base1_lc_flag1_en          : 1;
    unsigned int reg_01_ktx_ptg0_base1_inside_28s_enable    : 1;
    unsigned int reserved                                   : 6;
};
#define tx_ktx_ptg_01_08(val) ((rs_tx_ktx_ptg_01_08*)&(val))



#define TX_KTX_PTG_01_0C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x0C)

#define TX_KTX_PTG_01_0C_struct                                          rs_tx_ktx_ptg_01_0c

typedef struct _rs_tx_ktx_ptg_01_0c  rs_tx_ktx_ptg_01_0c;
struct _rs_tx_ktx_ptg_01_0c {
    unsigned int reg_01_ktx_ptg0_base1_frm_timer            :13;
    unsigned int reg_01_ktx_ptg0_base1_frm_rst_phase_l      :13;
    unsigned int reg_01_ktx_ptg0_base1_frm_limited_width    : 6;
};
#define tx_ktx_ptg_01_0c(val) ((rs_tx_ktx_ptg_01_0c*)&(val))



#define TX_KTX_PTG_01_10                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x10)

#define TX_KTX_PTG_01_10_struct                                          rs_tx_ktx_ptg_01_10

typedef struct _rs_tx_ktx_ptg_01_10  rs_tx_ktx_ptg_01_10;
struct _rs_tx_ktx_ptg_01_10 {
    unsigned int reg_01_ktx_ptg0_base1_frm_patt             :32;
};
#define tx_ktx_ptg_01_10(val) ((rs_tx_ktx_ptg_01_10*)&(val))



#define TX_KTX_PTG_01_14                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x14)

#define TX_KTX_PTG_01_14_struct                                          rs_tx_ktx_ptg_01_14

typedef struct _rs_tx_ktx_ptg_01_14  rs_tx_ktx_ptg_01_14;
struct _rs_tx_ktx_ptg_01_14 {
    unsigned int reg_01_ktx_ptg0_u0_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u0_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u0_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u0_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_14(val) ((rs_tx_ktx_ptg_01_14*)&(val))



#define TX_KTX_PTG_01_18                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x18)

#define TX_KTX_PTG_01_18_struct                                          rs_tx_ktx_ptg_01_18

typedef struct _rs_tx_ktx_ptg_01_18  rs_tx_ktx_ptg_01_18;
struct _rs_tx_ktx_ptg_01_18 {
    unsigned int reg_01_ktx_ptg0_u0_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u0_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u0_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u0_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u0_group_sel               : 4;
};
#define tx_ktx_ptg_01_18(val) ((rs_tx_ktx_ptg_01_18*)&(val))



#define TX_KTX_PTG_01_1C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x1C)

#define TX_KTX_PTG_01_1C_struct                                          rs_tx_ktx_ptg_01_1c

typedef struct _rs_tx_ktx_ptg_01_1c  rs_tx_ktx_ptg_01_1c;
struct _rs_tx_ktx_ptg_01_1c {
    unsigned int reg_01_ktx_ptg0_u0_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u0_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u0_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u0_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u0_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u0_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u0_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u0_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u0_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u0_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u0_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u0_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u0_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u0_frm_sel                 : 2;
    unsigned int reg_01_ktx_ptg0_base0_frm_cnt_delay        : 8;
    unsigned int reg_01_ktx_ptg0_base1_frm_cnt_delay        : 8;
};
#define tx_ktx_ptg_01_1c(val) ((rs_tx_ktx_ptg_01_1c*)&(val))



#define TX_KTX_PTG_01_20                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x20)

#define TX_KTX_PTG_01_20_struct                                          rs_tx_ktx_ptg_01_20

typedef struct _rs_tx_ktx_ptg_01_20  rs_tx_ktx_ptg_01_20;
struct _rs_tx_ktx_ptg_01_20 {
    unsigned int reg_01_ktx_ptg0_u0_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u0_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_20(val) ((rs_tx_ktx_ptg_01_20*)&(val))



#define TX_KTX_PTG_01_24                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x24)

#define TX_KTX_PTG_01_24_struct                                          rs_tx_ktx_ptg_01_24

typedef struct _rs_tx_ktx_ptg_01_24  rs_tx_ktx_ptg_01_24;
struct _rs_tx_ktx_ptg_01_24 {
    unsigned int reg_01_ktx_ptg0_u1_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u1_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u1_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u1_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_24(val) ((rs_tx_ktx_ptg_01_24*)&(val))



#define TX_KTX_PTG_01_28                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x28)

#define TX_KTX_PTG_01_28_struct                                          rs_tx_ktx_ptg_01_28

typedef struct _rs_tx_ktx_ptg_01_28  rs_tx_ktx_ptg_01_28;
struct _rs_tx_ktx_ptg_01_28 {
    unsigned int reg_01_ktx_ptg0_u1_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u1_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u1_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u1_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u1_group_sel               : 4;
};
#define tx_ktx_ptg_01_28(val) ((rs_tx_ktx_ptg_01_28*)&(val))



#define TX_KTX_PTG_01_2C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x2C)

#define TX_KTX_PTG_01_2C_struct                                          rs_tx_ktx_ptg_01_2c

typedef struct _rs_tx_ktx_ptg_01_2c  rs_tx_ktx_ptg_01_2c;
struct _rs_tx_ktx_ptg_01_2c {
    unsigned int reg_01_ktx_ptg0_u1_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u1_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u1_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u1_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u1_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u1_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u1_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u1_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u1_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u1_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u1_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u1_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u1_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u1_frm_sel                 : 2;
    unsigned int reg_01_ktx_ptg0_outside_pol_en             :12;
    unsigned int reserved                                   : 4;
};
#define tx_ktx_ptg_01_2c(val) ((rs_tx_ktx_ptg_01_2c*)&(val))



#define TX_KTX_PTG_01_30                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x30)

#define TX_KTX_PTG_01_30_struct                                          rs_tx_ktx_ptg_01_30

typedef struct _rs_tx_ktx_ptg_01_30  rs_tx_ktx_ptg_01_30;
struct _rs_tx_ktx_ptg_01_30 {
    unsigned int reg_01_ktx_ptg0_u1_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u1_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_30(val) ((rs_tx_ktx_ptg_01_30*)&(val))



#define TX_KTX_PTG_01_34                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x34)

#define TX_KTX_PTG_01_34_struct                                          rs_tx_ktx_ptg_01_34

typedef struct _rs_tx_ktx_ptg_01_34  rs_tx_ktx_ptg_01_34;
struct _rs_tx_ktx_ptg_01_34 {
    unsigned int reg_01_ktx_ptg0_u2_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u2_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u2_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u2_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_34(val) ((rs_tx_ktx_ptg_01_34*)&(val))



#define TX_KTX_PTG_01_38                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x38)

#define TX_KTX_PTG_01_38_struct                                          rs_tx_ktx_ptg_01_38

typedef struct _rs_tx_ktx_ptg_01_38  rs_tx_ktx_ptg_01_38;
struct _rs_tx_ktx_ptg_01_38 {
    unsigned int reg_01_ktx_ptg0_u2_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u2_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u2_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u2_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u2_group_sel               : 4;
};
#define tx_ktx_ptg_01_38(val) ((rs_tx_ktx_ptg_01_38*)&(val))



#define TX_KTX_PTG_01_3C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x3C)

#define TX_KTX_PTG_01_3C_struct                                          rs_tx_ktx_ptg_01_3c

typedef struct _rs_tx_ktx_ptg_01_3c  rs_tx_ktx_ptg_01_3c;
struct _rs_tx_ktx_ptg_01_3c {
    unsigned int reg_01_ktx_ptg0_u2_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u2_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u2_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u2_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u2_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u2_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u2_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u2_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u2_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u2_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u2_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u2_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u2_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u2_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_3c(val) ((rs_tx_ktx_ptg_01_3c*)&(val))



#define TX_KTX_PTG_01_40                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x40)

#define TX_KTX_PTG_01_40_struct                                          rs_tx_ktx_ptg_01_40

typedef struct _rs_tx_ktx_ptg_01_40  rs_tx_ktx_ptg_01_40;
struct _rs_tx_ktx_ptg_01_40 {
    unsigned int reg_01_ktx_ptg0_u2_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u2_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_40(val) ((rs_tx_ktx_ptg_01_40*)&(val))



#define TX_KTX_PTG_01_44                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x44)

#define TX_KTX_PTG_01_44_struct                                          rs_tx_ktx_ptg_01_44

typedef struct _rs_tx_ktx_ptg_01_44  rs_tx_ktx_ptg_01_44;
struct _rs_tx_ktx_ptg_01_44 {
    unsigned int reg_01_ktx_ptg0_u3_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u3_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u3_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u3_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_44(val) ((rs_tx_ktx_ptg_01_44*)&(val))



#define TX_KTX_PTG_01_48                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x48)

#define TX_KTX_PTG_01_48_struct                                          rs_tx_ktx_ptg_01_48

typedef struct _rs_tx_ktx_ptg_01_48  rs_tx_ktx_ptg_01_48;
struct _rs_tx_ktx_ptg_01_48 {
    unsigned int reg_01_ktx_ptg0_u3_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u3_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u3_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u3_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u3_group_sel               : 4;
};
#define tx_ktx_ptg_01_48(val) ((rs_tx_ktx_ptg_01_48*)&(val))



#define TX_KTX_PTG_01_4C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x4C)

#define TX_KTX_PTG_01_4C_struct                                          rs_tx_ktx_ptg_01_4c

typedef struct _rs_tx_ktx_ptg_01_4c  rs_tx_ktx_ptg_01_4c;
struct _rs_tx_ktx_ptg_01_4c {
    unsigned int reg_01_ktx_ptg0_u3_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u3_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u3_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u3_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u3_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u3_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u3_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u3_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u3_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u3_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u3_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u3_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u3_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u3_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_4c(val) ((rs_tx_ktx_ptg_01_4c*)&(val))



#define TX_KTX_PTG_01_50                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x50)

#define TX_KTX_PTG_01_50_struct                                          rs_tx_ktx_ptg_01_50

typedef struct _rs_tx_ktx_ptg_01_50  rs_tx_ktx_ptg_01_50;
struct _rs_tx_ktx_ptg_01_50 {
    unsigned int reg_01_ktx_ptg0_u3_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u3_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_50(val) ((rs_tx_ktx_ptg_01_50*)&(val))



#define TX_KTX_PTG_01_54                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x54)

#define TX_KTX_PTG_01_54_struct                                          rs_tx_ktx_ptg_01_54

typedef struct _rs_tx_ktx_ptg_01_54  rs_tx_ktx_ptg_01_54;
struct _rs_tx_ktx_ptg_01_54 {
    unsigned int reg_01_ktx_ptg0_u4_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u4_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u4_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u4_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_54(val) ((rs_tx_ktx_ptg_01_54*)&(val))



#define TX_KTX_PTG_01_58                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x58)

#define TX_KTX_PTG_01_58_struct                                          rs_tx_ktx_ptg_01_58

typedef struct _rs_tx_ktx_ptg_01_58  rs_tx_ktx_ptg_01_58;
struct _rs_tx_ktx_ptg_01_58 {
    unsigned int reg_01_ktx_ptg0_u4_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u4_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u4_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u4_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u4_group_sel               : 4;
};
#define tx_ktx_ptg_01_58(val) ((rs_tx_ktx_ptg_01_58*)&(val))



#define TX_KTX_PTG_01_5C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x5C)

#define TX_KTX_PTG_01_5C_struct                                          rs_tx_ktx_ptg_01_5c

typedef struct _rs_tx_ktx_ptg_01_5c  rs_tx_ktx_ptg_01_5c;
struct _rs_tx_ktx_ptg_01_5c {
    unsigned int reg_01_ktx_ptg0_u4_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u4_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u4_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u4_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u4_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u4_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u4_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u4_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u4_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u4_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u4_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u4_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u4_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u4_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_5c(val) ((rs_tx_ktx_ptg_01_5c*)&(val))



#define TX_KTX_PTG_01_60                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x60)

#define TX_KTX_PTG_01_60_struct                                          rs_tx_ktx_ptg_01_60

typedef struct _rs_tx_ktx_ptg_01_60  rs_tx_ktx_ptg_01_60;
struct _rs_tx_ktx_ptg_01_60 {
    unsigned int reg_01_ktx_ptg0_u4_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u4_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_60(val) ((rs_tx_ktx_ptg_01_60*)&(val))



#define TX_KTX_PTG_01_64                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x64)

#define TX_KTX_PTG_01_64_struct                                          rs_tx_ktx_ptg_01_64

typedef struct _rs_tx_ktx_ptg_01_64  rs_tx_ktx_ptg_01_64;
struct _rs_tx_ktx_ptg_01_64 {
    unsigned int reg_01_ktx_ptg0_u5_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u5_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u5_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u5_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_64(val) ((rs_tx_ktx_ptg_01_64*)&(val))



#define TX_KTX_PTG_01_68                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x68)

#define TX_KTX_PTG_01_68_struct                                          rs_tx_ktx_ptg_01_68

typedef struct _rs_tx_ktx_ptg_01_68  rs_tx_ktx_ptg_01_68;
struct _rs_tx_ktx_ptg_01_68 {
    unsigned int reg_01_ktx_ptg0_u5_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u5_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u5_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u5_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u5_group_sel               : 4;
};
#define tx_ktx_ptg_01_68(val) ((rs_tx_ktx_ptg_01_68*)&(val))



#define TX_KTX_PTG_01_6C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x6C)

#define TX_KTX_PTG_01_6C_struct                                          rs_tx_ktx_ptg_01_6c

typedef struct _rs_tx_ktx_ptg_01_6c  rs_tx_ktx_ptg_01_6c;
struct _rs_tx_ktx_ptg_01_6c {
    unsigned int reg_01_ktx_ptg0_u5_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u5_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u5_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u5_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u5_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u5_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u5_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u5_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u5_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u5_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u5_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u5_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u5_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u5_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_6c(val) ((rs_tx_ktx_ptg_01_6c*)&(val))



#define TX_KTX_PTG_01_70                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x70)

#define TX_KTX_PTG_01_70_struct                                          rs_tx_ktx_ptg_01_70

typedef struct _rs_tx_ktx_ptg_01_70  rs_tx_ktx_ptg_01_70;
struct _rs_tx_ktx_ptg_01_70 {
    unsigned int reg_01_ktx_ptg0_u5_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u5_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_70(val) ((rs_tx_ktx_ptg_01_70*)&(val))



#define TX_KTX_PTG_01_74                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x74)

#define TX_KTX_PTG_01_74_struct                                          rs_tx_ktx_ptg_01_74

typedef struct _rs_tx_ktx_ptg_01_74  rs_tx_ktx_ptg_01_74;
struct _rs_tx_ktx_ptg_01_74 {
    unsigned int reg_01_ktx_ptg0_u6_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u6_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u6_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u6_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_74(val) ((rs_tx_ktx_ptg_01_74*)&(val))



#define TX_KTX_PTG_01_78                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x78)

#define TX_KTX_PTG_01_78_struct                                          rs_tx_ktx_ptg_01_78

typedef struct _rs_tx_ktx_ptg_01_78  rs_tx_ktx_ptg_01_78;
struct _rs_tx_ktx_ptg_01_78 {
    unsigned int reg_01_ktx_ptg0_u6_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u6_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u6_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u6_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u6_group_sel               : 4;
};
#define tx_ktx_ptg_01_78(val) ((rs_tx_ktx_ptg_01_78*)&(val))



#define TX_KTX_PTG_01_7C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x7C)

#define TX_KTX_PTG_01_7C_struct                                          rs_tx_ktx_ptg_01_7c

typedef struct _rs_tx_ktx_ptg_01_7c  rs_tx_ktx_ptg_01_7c;
struct _rs_tx_ktx_ptg_01_7c {
    unsigned int reg_01_ktx_ptg0_u6_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u6_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u6_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u6_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u6_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u6_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u6_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u6_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u6_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u6_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u6_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u6_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u6_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u6_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_7c(val) ((rs_tx_ktx_ptg_01_7c*)&(val))



#define TX_KTX_PTG_01_80                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x80)

#define TX_KTX_PTG_01_80_struct                                          rs_tx_ktx_ptg_01_80

typedef struct _rs_tx_ktx_ptg_01_80  rs_tx_ktx_ptg_01_80;
struct _rs_tx_ktx_ptg_01_80 {
    unsigned int reg_01_ktx_ptg0_u6_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u6_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_80(val) ((rs_tx_ktx_ptg_01_80*)&(val))



#define TX_KTX_PTG_01_84                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x84)

#define TX_KTX_PTG_01_84_struct                                          rs_tx_ktx_ptg_01_84

typedef struct _rs_tx_ktx_ptg_01_84  rs_tx_ktx_ptg_01_84;
struct _rs_tx_ktx_ptg_01_84 {
    unsigned int reg_01_ktx_ptg0_u7_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u7_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u7_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u7_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_84(val) ((rs_tx_ktx_ptg_01_84*)&(val))



#define TX_KTX_PTG_01_88                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x88)

#define TX_KTX_PTG_01_88_struct                                          rs_tx_ktx_ptg_01_88

typedef struct _rs_tx_ktx_ptg_01_88  rs_tx_ktx_ptg_01_88;
struct _rs_tx_ktx_ptg_01_88 {
    unsigned int reg_01_ktx_ptg0_u7_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u7_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u7_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u7_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u7_group_sel               : 4;
};
#define tx_ktx_ptg_01_88(val) ((rs_tx_ktx_ptg_01_88*)&(val))



#define TX_KTX_PTG_01_8C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x8C)

#define TX_KTX_PTG_01_8C_struct                                          rs_tx_ktx_ptg_01_8c

typedef struct _rs_tx_ktx_ptg_01_8c  rs_tx_ktx_ptg_01_8c;
struct _rs_tx_ktx_ptg_01_8c {
    unsigned int reg_01_ktx_ptg0_u7_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u7_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u7_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u7_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u7_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u7_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u7_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u7_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u7_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u7_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u7_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u7_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u7_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u7_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_8c(val) ((rs_tx_ktx_ptg_01_8c*)&(val))



#define TX_KTX_PTG_01_90                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x90)

#define TX_KTX_PTG_01_90_struct                                          rs_tx_ktx_ptg_01_90

typedef struct _rs_tx_ktx_ptg_01_90  rs_tx_ktx_ptg_01_90;
struct _rs_tx_ktx_ptg_01_90 {
    unsigned int reg_01_ktx_ptg0_u7_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u7_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_90(val) ((rs_tx_ktx_ptg_01_90*)&(val))



#define TX_KTX_PTG_01_94                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x94)

#define TX_KTX_PTG_01_94_struct                                          rs_tx_ktx_ptg_01_94

typedef struct _rs_tx_ktx_ptg_01_94  rs_tx_ktx_ptg_01_94;
struct _rs_tx_ktx_ptg_01_94 {
    unsigned int reg_01_ktx_ptg0_u8_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u8_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u8_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u8_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_94(val) ((rs_tx_ktx_ptg_01_94*)&(val))



#define TX_KTX_PTG_01_98                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x98)

#define TX_KTX_PTG_01_98_struct                                          rs_tx_ktx_ptg_01_98

typedef struct _rs_tx_ktx_ptg_01_98  rs_tx_ktx_ptg_01_98;
struct _rs_tx_ktx_ptg_01_98 {
    unsigned int reg_01_ktx_ptg0_u8_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u8_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u8_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u8_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u8_group_sel               : 4;
};
#define tx_ktx_ptg_01_98(val) ((rs_tx_ktx_ptg_01_98*)&(val))



#define TX_KTX_PTG_01_9C                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0x9C)

#define TX_KTX_PTG_01_9C_struct                                          rs_tx_ktx_ptg_01_9c

typedef struct _rs_tx_ktx_ptg_01_9c  rs_tx_ktx_ptg_01_9c;
struct _rs_tx_ktx_ptg_01_9c {
    unsigned int reg_01_ktx_ptg0_u8_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u8_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u8_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u8_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u8_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u8_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u8_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u8_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u8_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u8_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u8_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u8_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u8_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u8_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_9c(val) ((rs_tx_ktx_ptg_01_9c*)&(val))



#define TX_KTX_PTG_01_A0                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xA0)

#define TX_KTX_PTG_01_A0_struct                                          rs_tx_ktx_ptg_01_a0

typedef struct _rs_tx_ktx_ptg_01_a0  rs_tx_ktx_ptg_01_a0;
struct _rs_tx_ktx_ptg_01_a0 {
    unsigned int reg_01_ktx_ptg0_u8_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u8_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_a0(val) ((rs_tx_ktx_ptg_01_a0*)&(val))



#define TX_KTX_PTG_01_A4                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xA4)

#define TX_KTX_PTG_01_A4_struct                                          rs_tx_ktx_ptg_01_a4

typedef struct _rs_tx_ktx_ptg_01_a4  rs_tx_ktx_ptg_01_a4;
struct _rs_tx_ktx_ptg_01_a4 {
    unsigned int reg_01_ktx_ptg0_u9_1st_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u9_1st_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u9_1st_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u9_1st_rp_sub_1_option     : 1;
};
#define tx_ktx_ptg_01_a4(val) ((rs_tx_ktx_ptg_01_a4*)&(val))



#define TX_KTX_PTG_01_A8                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xA8)

#define TX_KTX_PTG_01_A8_struct                                          rs_tx_ktx_ptg_01_a8

typedef struct _rs_tx_ktx_ptg_01_a8  rs_tx_ktx_ptg_01_a8;
struct _rs_tx_ktx_ptg_01_a8 {
    unsigned int reg_01_ktx_ptg0_u9_unit_mode               : 5;
    unsigned int reg_01_ktx_ptg0_u9_1st_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u9_1st_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u9_1st_vclr_disable        : 1;
    unsigned int reg_01_ktx_ptg0_u9_group_sel               : 4;
};
#define tx_ktx_ptg_01_a8(val) ((rs_tx_ktx_ptg_01_a8*)&(val))



#define TX_KTX_PTG_01_AC                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xAC)

#define TX_KTX_PTG_01_AC_struct                                          rs_tx_ktx_ptg_01_ac

typedef struct _rs_tx_ktx_ptg_01_ac  rs_tx_ktx_ptg_01_ac;
struct _rs_tx_ktx_ptg_01_ac {
    unsigned int reg_01_ktx_ptg0_u9_unit_enable             : 1;
    unsigned int reg_01_ktx_ptg0_u9_out_plus_ref_en         : 1;
    unsigned int reg_01_ktx_ptg0_u9_patt_cnt_enable         : 1;
    unsigned int reg_01_ktx_ptg0_u9_1st_vclr_inv            : 1;
    unsigned int reg_01_ktx_ptg0_u9_db_en                   : 1;
    unsigned int reg_01_ktx_ptg0_u9_3rd_bypass_mute         : 1;
    unsigned int reg_01_ktx_ptg0_u9_out_inv                 : 1;
    unsigned int reg_01_ktx_ptg0_u9_pwr_off_bypass          : 1;
    unsigned int reg_01_ktx_ptg0_u9_pwr_off_value           : 1;
    unsigned int reg_01_ktx_ptg0_u9_initial_value           : 1;
    unsigned int reg_01_ktx_ptg0_u9_1st_fp_sub_1_option     : 1;
    unsigned int reg_01_ktx_ptg0_u9_1st_vclr_value          : 1;
    unsigned int reg_01_ktx_ptg0_u9_timer_sel               : 2;
    unsigned int reg_01_ktx_ptg0_u9_frm_sel                 : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_ac(val) ((rs_tx_ktx_ptg_01_ac*)&(val))



#define TX_KTX_PTG_01_B0                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xB0)

#define TX_KTX_PTG_01_B0_struct                                          rs_tx_ktx_ptg_01_b0

typedef struct _rs_tx_ktx_ptg_01_b0  rs_tx_ktx_ptg_01_b0;
struct _rs_tx_ktx_ptg_01_b0 {
    unsigned int reg_01_ktx_ptg0_u9_1st_rp_patt_l           :16;
    unsigned int reg_01_ktx_ptg0_u9_1st_fp_patt_l           :16;
};
#define tx_ktx_ptg_01_b0(val) ((rs_tx_ktx_ptg_01_b0*)&(val))



#define TX_KTX_PTG_01_B4                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xB4)

#define TX_KTX_PTG_01_B4_struct                                          rs_tx_ktx_ptg_01_b4

typedef struct _rs_tx_ktx_ptg_01_b4  rs_tx_ktx_ptg_01_b4;
struct _rs_tx_ktx_ptg_01_b4 {
    unsigned int reg_01_ktx_ptg0_u10_1st_start_line_l       :13;
    unsigned int reg_01_ktx_ptg0_u10_1st_end_line_l         :13;
    unsigned int reg_01_ktx_ptg0_u10_1st_patt_type          : 5;
    unsigned int reg_01_ktx_ptg0_u10_1st_rp_sub_1_option    : 1;
};
#define tx_ktx_ptg_01_b4(val) ((rs_tx_ktx_ptg_01_b4*)&(val))



#define TX_KTX_PTG_01_B8                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xB8)

#define TX_KTX_PTG_01_B8_struct                                          rs_tx_ktx_ptg_01_b8

typedef struct _rs_tx_ktx_ptg_01_b8  rs_tx_ktx_ptg_01_b8;
struct _rs_tx_ktx_ptg_01_b8 {
    unsigned int reg_01_ktx_ptg0_u10_unit_mode              : 5;
    unsigned int reg_01_ktx_ptg0_u10_1st_h_rp               :11;
    unsigned int reg_01_ktx_ptg0_u10_1st_h_fp               :11;
    unsigned int reg_01_ktx_ptg0_u10_1st_vclr_disable       : 1;
    unsigned int reg_01_ktx_ptg0_u10_group_sel              : 4;
};
#define tx_ktx_ptg_01_b8(val) ((rs_tx_ktx_ptg_01_b8*)&(val))



#define TX_KTX_PTG_01_BC                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xBC)

#define TX_KTX_PTG_01_BC_struct                                          rs_tx_ktx_ptg_01_bc

typedef struct _rs_tx_ktx_ptg_01_bc  rs_tx_ktx_ptg_01_bc;
struct _rs_tx_ktx_ptg_01_bc {
    unsigned int reg_01_ktx_ptg0_u10_unit_enable            : 1;
    unsigned int reg_01_ktx_ptg0_u10_out_plus_ref_en        : 1;
    unsigned int reg_01_ktx_ptg0_u10_patt_cnt_enable        : 1;
    unsigned int reg_01_ktx_ptg0_u10_1st_vclr_inv           : 1;
    unsigned int reg_01_ktx_ptg0_u10_db_en                  : 1;
    unsigned int reg_01_ktx_ptg0_u10_3rd_bypass_mute        : 1;
    unsigned int reg_01_ktx_ptg0_u10_out_inv                : 1;
    unsigned int reg_01_ktx_ptg0_u10_pwr_off_bypass         : 1;
    unsigned int reg_01_ktx_ptg0_u10_pwr_off_value          : 1;
    unsigned int reg_01_ktx_ptg0_u10_initial_value          : 1;
    unsigned int reg_01_ktx_ptg0_u10_1st_fp_sub_1_option    : 1;
    unsigned int reg_01_ktx_ptg0_u10_1st_vclr_value         : 1;
    unsigned int reg_01_ktx_ptg0_u10_timer_sel              : 2;
    unsigned int reg_01_ktx_ptg0_u10_frm_sel                : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_bc(val) ((rs_tx_ktx_ptg_01_bc*)&(val))



#define TX_KTX_PTG_01_C0                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xC0)

#define TX_KTX_PTG_01_C0_struct                                          rs_tx_ktx_ptg_01_c0

typedef struct _rs_tx_ktx_ptg_01_c0  rs_tx_ktx_ptg_01_c0;
struct _rs_tx_ktx_ptg_01_c0 {
    unsigned int reg_01_ktx_ptg0_u10_1st_rp_patt_l          :16;
    unsigned int reg_01_ktx_ptg0_u10_1st_fp_patt_l          :16;
};
#define tx_ktx_ptg_01_c0(val) ((rs_tx_ktx_ptg_01_c0*)&(val))



#define TX_KTX_PTG_01_C4                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xC4)

#define TX_KTX_PTG_01_C4_struct                                          rs_tx_ktx_ptg_01_c4

typedef struct _rs_tx_ktx_ptg_01_c4  rs_tx_ktx_ptg_01_c4;
struct _rs_tx_ktx_ptg_01_c4 {
    unsigned int reg_01_ktx_ptg0_u11_1st_start_line_l       :13;
    unsigned int reg_01_ktx_ptg0_u11_1st_end_line_l         :13;
    unsigned int reg_01_ktx_ptg0_u11_1st_patt_type          : 5;
    unsigned int reg_01_ktx_ptg0_u11_1st_rp_sub_1_option    : 1;
};
#define tx_ktx_ptg_01_c4(val) ((rs_tx_ktx_ptg_01_c4*)&(val))



#define TX_KTX_PTG_01_C8                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xC8)

#define TX_KTX_PTG_01_C8_struct                                          rs_tx_ktx_ptg_01_c8

typedef struct _rs_tx_ktx_ptg_01_c8  rs_tx_ktx_ptg_01_c8;
struct _rs_tx_ktx_ptg_01_c8 {
    unsigned int reg_01_ktx_ptg0_u11_unit_mode              : 5;
    unsigned int reg_01_ktx_ptg0_u11_1st_h_rp               :11;
    unsigned int reg_01_ktx_ptg0_u11_1st_h_fp               :11;
    unsigned int reg_01_ktx_ptg0_u11_1st_vclr_disable       : 1;
    unsigned int reg_01_ktx_ptg0_u11_group_sel              : 4;
};
#define tx_ktx_ptg_01_c8(val) ((rs_tx_ktx_ptg_01_c8*)&(val))



#define TX_KTX_PTG_01_CC                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xCC)

#define TX_KTX_PTG_01_CC_struct                                          rs_tx_ktx_ptg_01_cc

typedef struct _rs_tx_ktx_ptg_01_cc  rs_tx_ktx_ptg_01_cc;
struct _rs_tx_ktx_ptg_01_cc {
    unsigned int reg_01_ktx_ptg0_u11_unit_enable            : 1;
    unsigned int reg_01_ktx_ptg0_u11_out_plus_ref_en        : 1;
    unsigned int reg_01_ktx_ptg0_u11_patt_cnt_enable        : 1;
    unsigned int reg_01_ktx_ptg0_u11_1st_vclr_inv           : 1;
    unsigned int reg_01_ktx_ptg0_u11_db_en                  : 1;
    unsigned int reg_01_ktx_ptg0_u11_3rd_bypass_mute        : 1;
    unsigned int reg_01_ktx_ptg0_u11_out_inv                : 1;
    unsigned int reg_01_ktx_ptg0_u11_pwr_off_bypass         : 1;
    unsigned int reg_01_ktx_ptg0_u11_pwr_off_value          : 1;
    unsigned int reg_01_ktx_ptg0_u11_initial_value          : 1;
    unsigned int reg_01_ktx_ptg0_u11_1st_fp_sub_1_option    : 1;
    unsigned int reg_01_ktx_ptg0_u11_1st_vclr_value         : 1;
    unsigned int reg_01_ktx_ptg0_u11_timer_sel              : 2;
    unsigned int reg_01_ktx_ptg0_u11_frm_sel                : 2;
    unsigned int reserved                                   :16;
};
#define tx_ktx_ptg_01_cc(val) ((rs_tx_ktx_ptg_01_cc*)&(val))



#define TX_KTX_PTG_01_D0                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xD0)

#define TX_KTX_PTG_01_D0_struct                                          rs_tx_ktx_ptg_01_d0

typedef struct _rs_tx_ktx_ptg_01_d0  rs_tx_ktx_ptg_01_d0;
struct _rs_tx_ktx_ptg_01_d0 {
    unsigned int reg_01_ktx_ptg0_u11_1st_rp_patt_l          :16;
    unsigned int reg_01_ktx_ptg0_u11_1st_fp_patt_l          :16;
};
#define tx_ktx_ptg_01_d0(val) ((rs_tx_ktx_ptg_01_d0*)&(val))



#define TX_KTX_PTG_01_D4                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xD4)

#define TX_KTX_PTG_01_D4_struct                                          rs_tx_ktx_ptg_01_d4

typedef struct _rs_tx_ktx_ptg_01_d4  rs_tx_ktx_ptg_01_d4;
struct _rs_tx_ktx_ptg_01_d4 {
    unsigned int reg_01_ktx_ptg0_u0_2nd_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u0_2nd_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u0_2nd_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u0_2nd_enable              : 1;
};
#define tx_ktx_ptg_01_d4(val) ((rs_tx_ktx_ptg_01_d4*)&(val))



#define TX_KTX_PTG_01_D8                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xD8)

#define TX_KTX_PTG_01_D8_struct                                          rs_tx_ktx_ptg_01_d8

typedef struct _rs_tx_ktx_ptg_01_d8  rs_tx_ktx_ptg_01_d8;
struct _rs_tx_ktx_ptg_01_d8 {
    unsigned int reg_01_ktx_ptg0_u0_2nd_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u0_2nd_h_fp                :11;
    unsigned int reserved                                   :10;
};
#define tx_ktx_ptg_01_d8(val) ((rs_tx_ktx_ptg_01_d8*)&(val))



#define TX_KTX_PTG_01_DC                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xDC)

#define TX_KTX_PTG_01_DC_struct                                          rs_tx_ktx_ptg_01_dc

typedef struct _rs_tx_ktx_ptg_01_dc  rs_tx_ktx_ptg_01_dc;
struct _rs_tx_ktx_ptg_01_dc {
    unsigned int reg_01_ktx_ptg0_u1_2nd_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u1_2nd_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u1_2nd_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u1_2nd_enable              : 1;
};
#define tx_ktx_ptg_01_dc(val) ((rs_tx_ktx_ptg_01_dc*)&(val))



#define TX_KTX_PTG_01_E0                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xE0)

#define TX_KTX_PTG_01_E0_struct                                          rs_tx_ktx_ptg_01_e0

typedef struct _rs_tx_ktx_ptg_01_e0  rs_tx_ktx_ptg_01_e0;
struct _rs_tx_ktx_ptg_01_e0 {
    unsigned int reg_01_ktx_ptg0_u1_2nd_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u1_2nd_h_fp                :11;
    unsigned int reserved                                   :10;
};
#define tx_ktx_ptg_01_e0(val) ((rs_tx_ktx_ptg_01_e0*)&(val))



#define TX_KTX_PTG_01_E4                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xE4)

#define TX_KTX_PTG_01_E4_struct                                          rs_tx_ktx_ptg_01_e4

typedef struct _rs_tx_ktx_ptg_01_e4  rs_tx_ktx_ptg_01_e4;
struct _rs_tx_ktx_ptg_01_e4 {
    unsigned int reg_01_ktx_ptg0_u2_2nd_start_line_l        :13;
    unsigned int reg_01_ktx_ptg0_u2_2nd_end_line_l          :13;
    unsigned int reg_01_ktx_ptg0_u2_2nd_patt_type           : 5;
    unsigned int reg_01_ktx_ptg0_u2_2nd_enable              : 1;
};
#define tx_ktx_ptg_01_e4(val) ((rs_tx_ktx_ptg_01_e4*)&(val))



#define TX_KTX_PTG_01_E8                                                 (HV_KTX_PTG_01_BASE_ADDRESS + 0xE8)

#define TX_KTX_PTG_01_E8_struct                                          rs_tx_ktx_ptg_01_e8

typedef struct _rs_tx_ktx_ptg_01_e8  rs_tx_ktx_ptg_01_e8;
struct _rs_tx_ktx_ptg_01_e8 {
    unsigned int reg_01_ktx_ptg0_u2_2nd_h_rp                :11;
    unsigned int reg_01_ktx_ptg0_u2_2nd_h_fp                :11;
    unsigned int reg_01_ktx_ptg0_u0_2nd_patt_type_inv       : 1;
    unsigned int reg_01_ktx_ptg0_u1_2nd_patt_type_inv       : 1;
    unsigned int reg_01_ktx_ptg0_u2_2nd_patt_type_inv       : 1;
    unsigned int reg_01_ktx_ptg0_u0_2nd_st_ln_as_frm        : 1;
    unsigned int reg_01_ktx_ptg0_u1_2nd_st_ln_as_frm        : 1;
    unsigned int reg_01_ktx_ptg0_u2_2nd_st_ln_as_frm        : 1;
    unsigned int reg_01_ktx_ptg0_u0_2nd_as_1st_enable       : 1;
    unsigned int reg_01_ktx_ptg0_u1_2nd_as_1st_enable       : 1;
    unsigned int reg_01_ktx_ptg0_u2_2nd_as_1st_enable       : 1;
    unsigned int reserved                                   : 1;
};
#define tx_ktx_ptg_01_e8(val) ((rs_tx_ktx_ptg_01_e8*)&(val))



#endif