#ifndef _HV_PAGE_HT7315_RX_PHY_DFE_01_H_
#define _HV_PAGE_HT7315_RX_PHY_DFE_01_H_

#ifndef HV_RX_PHY_DFE_01_BASE_ADDRESS
    #define HV_RX_PHY_DFE_01_BASE_ADDRESS                                         0x11046500
#endif


#define RX_RX_PHY_DFE_01_00                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x00)

#define RX_RX_PHY_DFE_01_00_struct                                       rs_rx_rx_phy_dfe_01_00

typedef struct _rs_rx_rx_phy_dfe_01_00  rs_rx_rx_phy_dfe_01_00;
struct _rs_rx_rx_phy_dfe_01_00 {
    unsigned int reg_01_rx_phy_ctl_enable                   : 1;
    unsigned int reg_01_rx_phy_ctl_st_init_en               : 1;
    unsigned int reg_01_rx_phy_ctl_st_byp                   : 7;
    unsigned int reg_01_rx_phy_ctl_st_hold                  : 7;
    unsigned int reg_01_rx_phy_ctl_st_eq_en                 : 6;
    unsigned int reg_01_rx_phy_ctl_st_dfe_en                : 6;
    unsigned int reg_01_rx_phy_ctl_cr_done_en               : 1;
    unsigned int reg_01_rx_phy_ctl_eq_init_en               : 1;
    unsigned int reg_01_rx_phy_ctl_dfe_init_en              : 1;
    unsigned int reg_01_rx_phy_ctl_eq_done                  : 1;
};
#define rx_rx_phy_dfe_01_00(val) ((rs_rx_rx_phy_dfe_01_00*)&(val))



#define RX_RX_PHY_DFE_01_04                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x04)

#define RX_RX_PHY_DFE_01_04_struct                                       rs_rx_rx_phy_dfe_01_04

typedef struct _rs_rx_rx_phy_dfe_01_04  rs_rx_rx_phy_dfe_01_04;
struct _rs_rx_rx_phy_dfe_01_04 {
    unsigned int reg_01_rx_phy_ctl_eq_timer                 :32;
};
#define rx_rx_phy_dfe_01_04(val) ((rs_rx_rx_phy_dfe_01_04*)&(val))



#define RX_RX_PHY_DFE_01_08                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x08)

#define RX_RX_PHY_DFE_01_08_struct                                       rs_rx_rx_phy_dfe_01_08

typedef struct _rs_rx_rx_phy_dfe_01_08  rs_rx_rx_phy_dfe_01_08;
struct _rs_rx_rx_phy_dfe_01_08 {
    unsigned int reg_01_rx_phy_ctl_hold_timer               :32;
};
#define rx_rx_phy_dfe_01_08(val) ((rs_rx_rx_phy_dfe_01_08*)&(val))



#define RX_RX_PHY_DFE_01_0C                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x0C)

#define RX_RX_PHY_DFE_01_0C_struct                                       rs_rx_rx_phy_dfe_01_0c

typedef struct _rs_rx_rx_phy_dfe_01_0c  rs_rx_rx_phy_dfe_01_0c;
struct _rs_rx_rx_phy_dfe_01_0c {
    unsigned int reg_01_rx_phy_ctl_hold_mode                : 2;
    unsigned int reg_01_rx_phy_ctl_man_eq_ag_en             : 2;
    unsigned int reg_01_rx_phy_ctl_sw_lane_vld              : 4;
    unsigned int reg_01_rx_phy_ctl_sw_lane_mode             : 1;
    unsigned int reserved                                   :23;
};
#define rx_rx_phy_dfe_01_0c(val) ((rs_rx_rx_phy_dfe_01_0c*)&(val))



#define RX_RX_PHY_DFE_01_10                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x10)

#define RX_RX_PHY_DFE_01_10_struct                                       rs_rx_rx_phy_dfe_01_10

typedef struct _rs_rx_rx_phy_dfe_01_10  rs_rx_rx_phy_dfe_01_10;
struct _rs_rx_rx_phy_dfe_01_10 {
    unsigned int reg_01_rx_phy_ctl_eq_init_val              : 4;
    unsigned int reg_01_rx_phy_ctl_rst_timer                :20;
    unsigned int reg_01_rx_phy_ctl_pol                      : 1;
    unsigned int reg_01_rx_phy_ctl_phy_rst_en               : 1;
    unsigned int reg_01_rx_phy_ctl_man_en                   : 1;
    unsigned int reg_01_rx_phy_ctl_man_loop_en              : 2;
    unsigned int reg_01_rx_phy_ctl_man_init_cha             : 2;
    unsigned int reserved                                   : 1;
};
#define rx_rx_phy_dfe_01_10(val) ((rs_rx_rx_phy_dfe_01_10*)&(val))



#define RX_RX_PHY_DFE_01_14                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x14)

#define RX_RX_PHY_DFE_01_14_struct                                       rs_rx_rx_phy_dfe_01_14

typedef struct _rs_rx_rx_phy_dfe_01_14  rs_rx_rx_phy_dfe_01_14;
struct _rs_rx_rx_phy_dfe_01_14 {
    unsigned int reg_01_rx_phy_dfe_en                       : 3;
    unsigned int reg_01_rx_phy_dfe_rng                      : 3;
    unsigned int reg_01_rx_phy_dfe_swap                     : 2;
    unsigned int reg_01_rx_phy_dfe_owth                     : 8;
    unsigned int reg_01_rx_phy_dfe_win_sel                  : 2;
    unsigned int reg_01_rx_phy_dfe_thd_sel                  : 2;
    unsigned int reg_01_rx_phy_eq_en                        : 1;
    unsigned int reg_01_rx_phy_eq_loop_cnt                  : 4;
    unsigned int reg_01_rx_phy_dfe_rand_det                 : 1;
    unsigned int reg_01_rx_phy_ctl_trn_mode_sw_en           : 2;
    unsigned int reserved                                   : 4;
};
#define rx_rx_phy_dfe_01_14(val) ((rs_rx_rx_phy_dfe_01_14*)&(val))



#define RX_RX_PHY_DFE_01_18                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x18)

#define RX_RX_PHY_DFE_01_18_struct                                       rs_rx_rx_phy_dfe_01_18

typedef struct _rs_rx_rx_phy_dfe_01_18  rs_rx_rx_phy_dfe_01_18;
struct _rs_rx_rx_phy_dfe_01_18 {
    unsigned int reg_01_rx_phy_patt_cdr                     :20;
    unsigned int reserved                                   :12;
};
#define rx_rx_phy_dfe_01_18(val) ((rs_rx_rx_phy_dfe_01_18*)&(val))



#define RX_RX_PHY_DFE_01_64                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x64)

#define RX_RX_PHY_DFE_01_64_struct                                       rs_rx_rx_phy_dfe_01_64

typedef struct _rs_rx_rx_phy_dfe_01_64  rs_rx_rx_phy_dfe_01_64;
struct _rs_rx_rx_phy_dfe_01_64 {
    unsigned int reg_01_rx_phy_vos_flow_start               : 1;
    unsigned int reg_01_rx_phy_vos_rst_timer                :16;
    unsigned int reg_01_rx_phy_vos_enable                   : 1;
    unsigned int reg_01_rx_phy_vos_start_sw_en              : 1;
    unsigned int reg_01_rx_phy_vos_hold_mode                : 1;
    unsigned int reg_01_rx_phy_vos_timer                    : 4;
    unsigned int reg_01_rx_phy_vos_st_byp                   : 5;
    unsigned int reg_01_rx_phy_vos_pll_lock_en              : 1;
    unsigned int reserved                                   : 2;
};
#define rx_rx_phy_dfe_01_64(val) ((rs_rx_rx_phy_dfe_01_64*)&(val))



#define RX_RX_PHY_DFE_01_68                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x68)

#define RX_RX_PHY_DFE_01_68_struct                                       rs_rx_rx_phy_dfe_01_68

typedef struct _rs_rx_rx_phy_dfe_01_68  rs_rx_rx_phy_dfe_01_68;
struct _rs_rx_rx_phy_dfe_01_68 {
    unsigned int reg_01_rx_phy_vos_st_hold                  : 5;
    unsigned int reg_01_rx_phy_vos_st_en                    : 5;
    unsigned int reserved                                   :22;
};
#define rx_rx_phy_dfe_01_68(val) ((rs_rx_rx_phy_dfe_01_68*)&(val))



#define RX_RX_PHY_DFE_01_6C                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x6C)

#define RX_RX_PHY_DFE_01_6C_struct                                       rs_rx_rx_phy_dfe_01_6c

typedef struct _rs_rx_rx_phy_dfe_01_6c  rs_rx_rx_phy_dfe_01_6c;
struct _rs_rx_rx_phy_dfe_01_6c {
    unsigned int reg_01_rx_phy_vos_0_start                  : 1;
    unsigned int reg_01_rx_phy_vos_0_manual_sel             : 1;
    unsigned int reg_01_rx_phy_vos_0_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_rx_phy_vos_0_cycle_delay            : 4;
    unsigned int reg_01_rx_phy_vos_0_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_01_rx_phy_vos_0_lane_sel               : 8;
};
#define rx_rx_phy_dfe_01_6c(val) ((rs_rx_rx_phy_dfe_01_6c*)&(val))



#define RX_RX_PHY_DFE_01_70                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x70)

#define RX_RX_PHY_DFE_01_70_struct                                       rs_rx_rx_phy_dfe_01_70

typedef struct _rs_rx_rx_phy_dfe_01_70  rs_rx_rx_phy_dfe_01_70;
struct _rs_rx_rx_phy_dfe_01_70 {
    unsigned int reg_01_rx_phy_vos_0_lane_vos0              : 4;
    unsigned int reg_01_rx_phy_vos_0_lane_vos1              : 4;
    unsigned int reg_01_rx_phy_vos_0_lane_vos2              : 4;
    unsigned int reg_01_rx_phy_vos_0_lane_vos3              : 4;
    unsigned int reg_01_rx_phy_vos_0_lane_vos4              : 4;
    unsigned int reg_01_rx_phy_vos_0_lane_vos5              : 4;
    unsigned int reg_01_rx_phy_vos_0_lane_vos6              : 4;
    unsigned int reg_01_rx_phy_vos_0_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_01_70(val) ((rs_rx_rx_phy_dfe_01_70*)&(val))



#define RX_RX_PHY_DFE_01_74                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x74)

#define RX_RX_PHY_DFE_01_74_struct                                       rs_rx_rx_phy_dfe_01_74

typedef struct _rs_rx_rx_phy_dfe_01_74  rs_rx_rx_phy_dfe_01_74;
struct _rs_rx_rx_phy_dfe_01_74 {
    unsigned int reg_01_rx_phy_vos_1_start                  : 1;
    unsigned int reg_01_rx_phy_vos_1_manual_sel             : 1;
    unsigned int reg_01_rx_phy_vos_1_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_rx_phy_vos_1_cycle_delay            : 4;
    unsigned int reg_01_rx_phy_vos_1_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_01_rx_phy_vos_1_lane_sel               : 8;
};
#define rx_rx_phy_dfe_01_74(val) ((rs_rx_rx_phy_dfe_01_74*)&(val))



#define RX_RX_PHY_DFE_01_78                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x78)

#define RX_RX_PHY_DFE_01_78_struct                                       rs_rx_rx_phy_dfe_01_78

typedef struct _rs_rx_rx_phy_dfe_01_78  rs_rx_rx_phy_dfe_01_78;
struct _rs_rx_rx_phy_dfe_01_78 {
    unsigned int reg_01_rx_phy_vos_1_lane_vos0              : 4;
    unsigned int reg_01_rx_phy_vos_1_lane_vos1              : 4;
    unsigned int reg_01_rx_phy_vos_1_lane_vos2              : 4;
    unsigned int reg_01_rx_phy_vos_1_lane_vos3              : 4;
    unsigned int reg_01_rx_phy_vos_1_lane_vos4              : 4;
    unsigned int reg_01_rx_phy_vos_1_lane_vos5              : 4;
    unsigned int reg_01_rx_phy_vos_1_lane_vos6              : 4;
    unsigned int reg_01_rx_phy_vos_1_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_01_78(val) ((rs_rx_rx_phy_dfe_01_78*)&(val))



#define RX_RX_PHY_DFE_01_7C                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x7C)

#define RX_RX_PHY_DFE_01_7C_struct                                       rs_rx_rx_phy_dfe_01_7c

typedef struct _rs_rx_rx_phy_dfe_01_7c  rs_rx_rx_phy_dfe_01_7c;
struct _rs_rx_rx_phy_dfe_01_7c {
    unsigned int reg_01_rx_phy_vos_2_start                  : 1;
    unsigned int reg_01_rx_phy_vos_2_manual_sel             : 1;
    unsigned int reg_01_rx_phy_vos_2_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_rx_phy_vos_2_cycle_delay            : 4;
    unsigned int reg_01_rx_phy_vos_2_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_01_rx_phy_vos_2_lane_sel               : 8;
};
#define rx_rx_phy_dfe_01_7c(val) ((rs_rx_rx_phy_dfe_01_7c*)&(val))



#define RX_RX_PHY_DFE_01_80                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x80)

#define RX_RX_PHY_DFE_01_80_struct                                       rs_rx_rx_phy_dfe_01_80

typedef struct _rs_rx_rx_phy_dfe_01_80  rs_rx_rx_phy_dfe_01_80;
struct _rs_rx_rx_phy_dfe_01_80 {
    unsigned int reg_01_rx_phy_vos_2_lane_vos0              : 4;
    unsigned int reg_01_rx_phy_vos_2_lane_vos1              : 4;
    unsigned int reg_01_rx_phy_vos_2_lane_vos2              : 4;
    unsigned int reg_01_rx_phy_vos_2_lane_vos3              : 4;
    unsigned int reg_01_rx_phy_vos_2_lane_vos4              : 4;
    unsigned int reg_01_rx_phy_vos_2_lane_vos5              : 4;
    unsigned int reg_01_rx_phy_vos_2_lane_vos6              : 4;
    unsigned int reg_01_rx_phy_vos_2_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_01_80(val) ((rs_rx_rx_phy_dfe_01_80*)&(val))



#define RX_RX_PHY_DFE_01_84                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x84)

#define RX_RX_PHY_DFE_01_84_struct                                       rs_rx_rx_phy_dfe_01_84

typedef struct _rs_rx_rx_phy_dfe_01_84  rs_rx_rx_phy_dfe_01_84;
struct _rs_rx_rx_phy_dfe_01_84 {
    unsigned int reg_01_rx_phy_vos_3_start                  : 1;
    unsigned int reg_01_rx_phy_vos_3_manual_sel             : 1;
    unsigned int reg_01_rx_phy_vos_3_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_rx_phy_vos_3_cycle_delay            : 4;
    unsigned int reg_01_rx_phy_vos_3_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_01_rx_phy_vos_3_lane_sel               : 8;
};
#define rx_rx_phy_dfe_01_84(val) ((rs_rx_rx_phy_dfe_01_84*)&(val))



#define RX_RX_PHY_DFE_01_88                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x88)

#define RX_RX_PHY_DFE_01_88_struct                                       rs_rx_rx_phy_dfe_01_88

typedef struct _rs_rx_rx_phy_dfe_01_88  rs_rx_rx_phy_dfe_01_88;
struct _rs_rx_rx_phy_dfe_01_88 {
    unsigned int reg_01_rx_phy_vos_3_lane_vos0              : 4;
    unsigned int reg_01_rx_phy_vos_3_lane_vos1              : 4;
    unsigned int reg_01_rx_phy_vos_3_lane_vos2              : 4;
    unsigned int reg_01_rx_phy_vos_3_lane_vos3              : 4;
    unsigned int reg_01_rx_phy_vos_3_lane_vos4              : 4;
    unsigned int reg_01_rx_phy_vos_3_lane_vos5              : 4;
    unsigned int reg_01_rx_phy_vos_3_lane_vos6              : 4;
    unsigned int reg_01_rx_phy_vos_3_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_01_88(val) ((rs_rx_rx_phy_dfe_01_88*)&(val))



#define RX_RX_PHY_DFE_01_8C                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x8C)

#define RX_RX_PHY_DFE_01_8C_struct                                       rs_rx_rx_phy_dfe_01_8c

typedef struct _rs_rx_rx_phy_dfe_01_8c  rs_rx_rx_phy_dfe_01_8c;
struct _rs_rx_rx_phy_dfe_01_8c {
    unsigned int regr_01_rx_phy_vos_0_ds_vos0               : 4;
    unsigned int regr_01_rx_phy_vos_0_ds_vos1               : 4;
    unsigned int regr_01_rx_phy_vos_0_ds_vos2               : 4;
    unsigned int regr_01_rx_phy_vos_0_ds_vos3               : 4;
    unsigned int regr_01_rx_phy_vos_0_ds_vos4               : 4;
    unsigned int regr_01_rx_phy_vos_0_ds_vos5               : 4;
    unsigned int regr_01_rx_phy_vos_0_ds_vos6               : 4;
    unsigned int regr_01_rx_phy_vos_0_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_01_8c(val) ((rs_rx_rx_phy_dfe_01_8c*)&(val))



#define RX_RX_PHY_DFE_01_90                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x90)

#define RX_RX_PHY_DFE_01_90_struct                                       rs_rx_rx_phy_dfe_01_90

typedef struct _rs_rx_rx_phy_dfe_01_90  rs_rx_rx_phy_dfe_01_90;
struct _rs_rx_rx_phy_dfe_01_90 {
    unsigned int regr_01_rx_phy_vos_0_done                  : 8;
    unsigned int regr_01_rx_phy_vos_0_overflow              : 8;
    unsigned int regr_01_rx_phy_vos_0_ds_cnt                :10;
    unsigned int reserved                                   : 6;
};
#define rx_rx_phy_dfe_01_90(val) ((rs_rx_rx_phy_dfe_01_90*)&(val))



#define RX_RX_PHY_DFE_01_94                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x94)

#define RX_RX_PHY_DFE_01_94_struct                                       rs_rx_rx_phy_dfe_01_94

typedef struct _rs_rx_rx_phy_dfe_01_94  rs_rx_rx_phy_dfe_01_94;
struct _rs_rx_rx_phy_dfe_01_94 {
    unsigned int regr_01_rx_phy_vos_1_ds_vos0               : 4;
    unsigned int regr_01_rx_phy_vos_1_ds_vos1               : 4;
    unsigned int regr_01_rx_phy_vos_1_ds_vos2               : 4;
    unsigned int regr_01_rx_phy_vos_1_ds_vos3               : 4;
    unsigned int regr_01_rx_phy_vos_1_ds_vos4               : 4;
    unsigned int regr_01_rx_phy_vos_1_ds_vos5               : 4;
    unsigned int regr_01_rx_phy_vos_1_ds_vos6               : 4;
    unsigned int regr_01_rx_phy_vos_1_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_01_94(val) ((rs_rx_rx_phy_dfe_01_94*)&(val))



#define RX_RX_PHY_DFE_01_98                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x98)

#define RX_RX_PHY_DFE_01_98_struct                                       rs_rx_rx_phy_dfe_01_98

typedef struct _rs_rx_rx_phy_dfe_01_98  rs_rx_rx_phy_dfe_01_98;
struct _rs_rx_rx_phy_dfe_01_98 {
    unsigned int regr_01_rx_phy_vos_1_done                  : 8;
    unsigned int regr_01_rx_phy_vos_1_overflow              : 8;
    unsigned int regr_01_rx_phy_vos_1_ds_cnt                :10;
    unsigned int reserved                                   : 6;
};
#define rx_rx_phy_dfe_01_98(val) ((rs_rx_rx_phy_dfe_01_98*)&(val))



#define RX_RX_PHY_DFE_01_9C                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0x9C)

#define RX_RX_PHY_DFE_01_9C_struct                                       rs_rx_rx_phy_dfe_01_9c

typedef struct _rs_rx_rx_phy_dfe_01_9c  rs_rx_rx_phy_dfe_01_9c;
struct _rs_rx_rx_phy_dfe_01_9c {
    unsigned int regr_01_rx_phy_vos_2_ds_vos0               : 4;
    unsigned int regr_01_rx_phy_vos_2_ds_vos1               : 4;
    unsigned int regr_01_rx_phy_vos_2_ds_vos2               : 4;
    unsigned int regr_01_rx_phy_vos_2_ds_vos3               : 4;
    unsigned int regr_01_rx_phy_vos_2_ds_vos4               : 4;
    unsigned int regr_01_rx_phy_vos_2_ds_vos5               : 4;
    unsigned int regr_01_rx_phy_vos_2_ds_vos6               : 4;
    unsigned int regr_01_rx_phy_vos_2_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_01_9c(val) ((rs_rx_rx_phy_dfe_01_9c*)&(val))



#define RX_RX_PHY_DFE_01_A0                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xA0)

#define RX_RX_PHY_DFE_01_A0_struct                                       rs_rx_rx_phy_dfe_01_a0

typedef struct _rs_rx_rx_phy_dfe_01_a0  rs_rx_rx_phy_dfe_01_a0;
struct _rs_rx_rx_phy_dfe_01_a0 {
    unsigned int regr_01_rx_phy_vos_2_done                  : 8;
    unsigned int regr_01_rx_phy_vos_2_overflow              : 8;
    unsigned int regr_01_rx_phy_vos_2_ds_cnt                :10;
    unsigned int reserved                                   : 6;
};
#define rx_rx_phy_dfe_01_a0(val) ((rs_rx_rx_phy_dfe_01_a0*)&(val))



#define RX_RX_PHY_DFE_01_A4                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xA4)

#define RX_RX_PHY_DFE_01_A4_struct                                       rs_rx_rx_phy_dfe_01_a4

typedef struct _rs_rx_rx_phy_dfe_01_a4  rs_rx_rx_phy_dfe_01_a4;
struct _rs_rx_rx_phy_dfe_01_a4 {
    unsigned int regr_01_rx_phy_vos_3_ds_vos0               : 4;
    unsigned int regr_01_rx_phy_vos_3_ds_vos1               : 4;
    unsigned int regr_01_rx_phy_vos_3_ds_vos2               : 4;
    unsigned int regr_01_rx_phy_vos_3_ds_vos3               : 4;
    unsigned int regr_01_rx_phy_vos_3_ds_vos4               : 4;
    unsigned int regr_01_rx_phy_vos_3_ds_vos5               : 4;
    unsigned int regr_01_rx_phy_vos_3_ds_vos6               : 4;
    unsigned int regr_01_rx_phy_vos_3_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_01_a4(val) ((rs_rx_rx_phy_dfe_01_a4*)&(val))



#define RX_RX_PHY_DFE_01_A8                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xA8)

#define RX_RX_PHY_DFE_01_A8_struct                                       rs_rx_rx_phy_dfe_01_a8

typedef struct _rs_rx_rx_phy_dfe_01_a8  rs_rx_rx_phy_dfe_01_a8;
struct _rs_rx_rx_phy_dfe_01_a8 {
    unsigned int regr_01_rx_phy_vos_3_done                  : 8;
    unsigned int regr_01_rx_phy_vos_3_overflow              : 8;
    unsigned int regr_01_rx_phy_vos_3_ds_cnt                :10;
    unsigned int regr_01_rx_phy_vos_state                   : 3;
    unsigned int reserved                                   : 3;
};
#define rx_rx_phy_dfe_01_a8(val) ((rs_rx_rx_phy_dfe_01_a8*)&(val))



#define RX_RX_PHY_DFE_01_C0                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xC0)

#define RX_RX_PHY_DFE_01_C0_struct                                       rs_rx_rx_phy_dfe_01_c0

typedef struct _rs_rx_rx_phy_dfe_01_c0  rs_rx_rx_phy_dfe_01_c0;
struct _rs_rx_rx_phy_dfe_01_c0 {
    unsigned int regr_01_rx_phy_dfe_lane0_win_cnt           :16;
    unsigned int regr_01_rx_phy_dfe_lane1_win_cnt           :16;
};
#define rx_rx_phy_dfe_01_c0(val) ((rs_rx_rx_phy_dfe_01_c0*)&(val))



#define RX_RX_PHY_DFE_01_C4                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xC4)

#define RX_RX_PHY_DFE_01_C4_struct                                       rs_rx_rx_phy_dfe_01_c4

typedef struct _rs_rx_rx_phy_dfe_01_c4  rs_rx_rx_phy_dfe_01_c4;
struct _rs_rx_rx_phy_dfe_01_c4 {
    unsigned int regr_01_rx_phy_dfe_lane2_win_cnt           :16;
    unsigned int regr_01_rx_phy_dfe_lane3_win_cnt           :16;
};
#define rx_rx_phy_dfe_01_c4(val) ((rs_rx_rx_phy_dfe_01_c4*)&(val))



#define RX_RX_PHY_DFE_01_C8                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xC8)

#define RX_RX_PHY_DFE_01_C8_struct                                       rs_rx_rx_phy_dfe_01_c8

typedef struct _rs_rx_rx_phy_dfe_01_c8  rs_rx_rx_phy_dfe_01_c8;
struct _rs_rx_rx_phy_dfe_01_c8 {
    unsigned int regr_01_rx_phy_dfe_lane0_tap1              : 6;
    unsigned int regr_01_rx_phy_dfe_lane0_tap2              : 5;
    unsigned int regr_01_rx_phy_dfe_lane0_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_01_rx_phy_dfe_lane0_dv1_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane0_dv1_abs           :15;
};
#define rx_rx_phy_dfe_01_c8(val) ((rs_rx_rx_phy_dfe_01_c8*)&(val))



#define RX_RX_PHY_DFE_01_CC                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xCC)

#define RX_RX_PHY_DFE_01_CC_struct                                       rs_rx_rx_phy_dfe_01_cc

typedef struct _rs_rx_rx_phy_dfe_01_cc  rs_rx_rx_phy_dfe_01_cc;
struct _rs_rx_rx_phy_dfe_01_cc {
    unsigned int regr_01_rx_phy_dfe_lane0_dv2_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane0_dv2_abs           :15;
    unsigned int regr_01_rx_phy_dfe_lane0_dv3_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane0_dv3_abs           :15;
};
#define rx_rx_phy_dfe_01_cc(val) ((rs_rx_rx_phy_dfe_01_cc*)&(val))



#define RX_RX_PHY_DFE_01_D0                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xD0)

#define RX_RX_PHY_DFE_01_D0_struct                                       rs_rx_rx_phy_dfe_01_d0

typedef struct _rs_rx_rx_phy_dfe_01_d0  rs_rx_rx_phy_dfe_01_d0;
struct _rs_rx_rx_phy_dfe_01_d0 {
    unsigned int regr_01_rx_phy_dfe_lane1_tap1              : 6;
    unsigned int regr_01_rx_phy_dfe_lane1_tap2              : 5;
    unsigned int regr_01_rx_phy_dfe_lane1_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_01_rx_phy_dfe_lane1_dv1_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane1_dv1_abs           :15;
};
#define rx_rx_phy_dfe_01_d0(val) ((rs_rx_rx_phy_dfe_01_d0*)&(val))



#define RX_RX_PHY_DFE_01_D4                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xD4)

#define RX_RX_PHY_DFE_01_D4_struct                                       rs_rx_rx_phy_dfe_01_d4

typedef struct _rs_rx_rx_phy_dfe_01_d4  rs_rx_rx_phy_dfe_01_d4;
struct _rs_rx_rx_phy_dfe_01_d4 {
    unsigned int regr_01_rx_phy_dfe_lane1_dv2_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane1_dv2_abs           :15;
    unsigned int regr_01_rx_phy_dfe_lane1_dv3_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane1_dv3_abs           :15;
};
#define rx_rx_phy_dfe_01_d4(val) ((rs_rx_rx_phy_dfe_01_d4*)&(val))



#define RX_RX_PHY_DFE_01_D8                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xD8)

#define RX_RX_PHY_DFE_01_D8_struct                                       rs_rx_rx_phy_dfe_01_d8

typedef struct _rs_rx_rx_phy_dfe_01_d8  rs_rx_rx_phy_dfe_01_d8;
struct _rs_rx_rx_phy_dfe_01_d8 {
    unsigned int regr_01_rx_phy_dfe_lane2_tap1              : 6;
    unsigned int regr_01_rx_phy_dfe_lane2_tap2              : 5;
    unsigned int regr_01_rx_phy_dfe_lane2_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_01_rx_phy_dfe_lane2_dv1_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane2_dv1_abs           :15;
};
#define rx_rx_phy_dfe_01_d8(val) ((rs_rx_rx_phy_dfe_01_d8*)&(val))



#define RX_RX_PHY_DFE_01_DC                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xDC)

#define RX_RX_PHY_DFE_01_DC_struct                                       rs_rx_rx_phy_dfe_01_dc

typedef struct _rs_rx_rx_phy_dfe_01_dc  rs_rx_rx_phy_dfe_01_dc;
struct _rs_rx_rx_phy_dfe_01_dc {
    unsigned int regr_01_rx_phy_dfe_lane2_dv2_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane2_dv2_abs           :15;
    unsigned int regr_01_rx_phy_dfe_lane2_dv3_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane2_dv3_abs           :15;
};
#define rx_rx_phy_dfe_01_dc(val) ((rs_rx_rx_phy_dfe_01_dc*)&(val))



#define RX_RX_PHY_DFE_01_E0                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xE0)

#define RX_RX_PHY_DFE_01_E0_struct                                       rs_rx_rx_phy_dfe_01_e0

typedef struct _rs_rx_rx_phy_dfe_01_e0  rs_rx_rx_phy_dfe_01_e0;
struct _rs_rx_rx_phy_dfe_01_e0 {
    unsigned int regr_01_rx_phy_dfe_lane3_tap1              : 6;
    unsigned int regr_01_rx_phy_dfe_lane3_tap2              : 5;
    unsigned int regr_01_rx_phy_dfe_lane3_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_01_rx_phy_dfe_lane3_dv1_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane3_dv1_abs           :15;
};
#define rx_rx_phy_dfe_01_e0(val) ((rs_rx_rx_phy_dfe_01_e0*)&(val))



#define RX_RX_PHY_DFE_01_E4                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xE4)

#define RX_RX_PHY_DFE_01_E4_struct                                       rs_rx_rx_phy_dfe_01_e4

typedef struct _rs_rx_rx_phy_dfe_01_e4  rs_rx_rx_phy_dfe_01_e4;
struct _rs_rx_rx_phy_dfe_01_e4 {
    unsigned int regr_01_rx_phy_dfe_lane3_dv2_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane3_dv2_abs           :15;
    unsigned int regr_01_rx_phy_dfe_lane3_dv3_sig           : 1;
    unsigned int regr_01_rx_phy_dfe_lane3_dv3_abs           :15;
};
#define rx_rx_phy_dfe_01_e4(val) ((rs_rx_rx_phy_dfe_01_e4*)&(val))



#define RX_RX_PHY_DFE_01_E8                                              (HV_RX_PHY_DFE_01_BASE_ADDRESS + 0xE8)

#define RX_RX_PHY_DFE_01_E8_struct                                       rs_rx_rx_phy_dfe_01_e8

typedef struct _rs_rx_rx_phy_dfe_01_e8  rs_rx_rx_phy_dfe_01_e8;
struct _rs_rx_rx_phy_dfe_01_e8 {
    unsigned int regr_01_rx_phy_ctl_state                   : 3;
    unsigned int regr_01_rx_phy_ctl_permit_ca               : 4;
    unsigned int regr_01_rx_phy_ctl_init_val                :16;
    unsigned int reserved                                   : 9;
};
#define rx_rx_phy_dfe_01_e8(val) ((rs_rx_rx_phy_dfe_01_e8*)&(val))



#endif