/**
 * @file hv_pm51_driver_PWM.c
 * @brief HT7135 PM51 PWM Driver.
 * @details 
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20230301
 * @copyright Copyright(c),2023-3, Hiview Software. All rights reserved.
 * @par History: 
 * <table>
 * <tr><th>author                     <th>date           <th>description
 * <tr><td>HiView SoC Software Team   <td>20230301       <td>Create and first Version.
 * </table>
**/

#include "HS_PAGE_HT7315_8051_reg.h"
#include "hv_pm51_Assert.h"
#include "hv_pm51_driver_Reg.h"
#include "hv_pm51_driver_PWM.h"
#include "BoardConfig.h"

void Hv_PM51_Pwm_Init(PwmParam *pstParam)
{
    HV_PM51_ASSERT(pstParam != NULL);

    /* Clock enable */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_pwm_pclk_en_ADDR,
                  HS_Standby__standby_mcu_reg__reg_pwm_pclk_en_BITSTART,
                  HS_Standby__standby_mcu_reg__reg_pwm_pclk_en_BITEND, 0x1);

    Hv_PM51_Pwm_SetPrescaler(pstParam->ucPrescaler);
    Hv_PM51_Pwm_SetPol(pstParam->enPol);
    Hv_PM51_Pwm_SetCntMode(pstParam->enCntMode);
    Hv_PM51_Pwm_SetCntTopVal(pstParam->ucCntTopVal);
    Hv_PM51_Pwm_SetCmpStartVal(pstParam->usCmpStartVal);
    Hv_PM51_Pwm_SetCmpEndVal(pstParam->usCmpEndVal);
    Hv_PM51_Pwm_SetStepVal(pstParam->usCmpStepVal);
    Hv_PM51_Pwm_SetOutputEnable();
}

void Hv_PM51_Pwm_Start(void)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_ch_en_ADDR, 
                      HS_Standby__standby_peri_reg__reg_pwm_ch_en_BITSTART,
                      HS_Standby__standby_peri_reg__reg_pwm_ch_en_BITEND, 0x1);
}

void Hv_PM51_Pwm_Stop(void)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_ch_en_ADDR, 
                      HS_Standby__standby_peri_reg__reg_pwm_ch_en_BITSTART,
                      HS_Standby__standby_peri_reg__reg_pwm_ch_en_BITEND, 0x0);
}

void Hv_PM51_Pwm_SetOutputEnable(void)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_output_mode_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_output_mode_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_output_mode_BITEND, 0x1);
}

void Hv_PM51_Pwm_SetOutputDisable(void)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_output_mode_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_output_mode_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_output_mode_BITEND, 0x0);
}

void Hv_PM51_Pwm_SetPrescaler(UCHAR8 ucPrescaler)
{
    if(ucPrescaler > 0xf)
    {
        return;
    }
    
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_prescaler_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_prescaler_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_prescaler_BITEND, ucPrescaler);
}

void Hv_PM51_Pwm_SetPol(PwmPol enPol)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_pol_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_pol_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_pol_BITEND, enPol);
}

void Hv_PM51_Pwm_SetCntMode(PwmCntMode ucMode)
{
    if(E_PWM_CNT_MODE_UP == ucMode)
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_ADDR, 
                          HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_BITSTART,
                          HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_BITEND, 0x0);
    }
    else
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_ADDR, 
                          HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_BITSTART,
                          HS_Standby__standby_peri_reg__reg_pwm_cnt_mode_BITEND, 0x1);
    }
}

void Hv_PM51_Pwm_SetCntTopVal(USHORT16 usTopVal)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_counter_top_ADDR, 
                      HS_Standby__standby_peri_reg__reg_pwm_counter_top_BITSTART,
                      HS_Standby__standby_peri_reg__reg_pwm_counter_top_BITEND, usTopVal);
}

void Hv_PM51_Pwm_SetCmpStartVal(USHORT16 usStartVal)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_cmp_start_val_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_cmp_start_val_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_cmp_start_val_BITEND, usStartVal);
}

void Hv_PM51_Pwm_SetCmpEndVal(USHORT16 usEndVal)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_cmp_end_val_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_cmp_end_val_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_cmp_end_val_BITEND, usEndVal);
}

void Hv_PM51_Pwm_SetStepVal(USHORT16 usStepVal)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_cmp_step_val_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_cmp_step_val_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_cmp_step_val_BITEND, usStepVal);
}

void Hv_PM51_Pwm_SetCycleNum(USHORT16 usCycleNum)
{
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_pwm_cycle_num_ADDR,
                    HS_Standby__standby_peri_reg__reg_pwm_cycle_num_BITSTART,
                    HS_Standby__standby_peri_reg__reg_pwm_cycle_num_BITEND, usCycleNum);
}
