#ifndef _HV_PAGE_HT7315_HDMI21_RX_SCDC_00_H_
#define _HV_PAGE_HT7315_HDMI21_RX_SCDC_00_H_

#ifndef HV_HDMI21_RX_SCDC_00_BASE_ADDRESS
    #define HV_HDMI21_RX_SCDC_00_BASE_ADDRESS                                         0x1104D000
#endif


#define RX_HDMI21_RX_SCDC_00_00                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX_SCDC_00_00_struct                                   rs_rx_hdmi21_rx_scdc_00_00

typedef struct _rs_rx_hdmi21_rx_scdc_00_00  rs_rx_hdmi21_rx_scdc_00_00;
struct _rs_rx_hdmi21_rx_scdc_00_00 {
    unsigned int reg_00_SCRAMBEN_SEL                        : 2;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_SCDC_ENABLE                         : 1;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_CTRLCHECKEN                         : 1;
    unsigned int reg_00_PREAMBCHECKEN                       : 1;
    unsigned int reg_00_GBCHECKEN                           : 1;
    unsigned int reg_00_DATAISCHECKEN                       : 1;
    unsigned int reg_00_VIDDATACHECKEN                      : 1;
    unsigned int reg_00_hd21rx_check_vld_sel                : 1;
    unsigned int reserved_2                                 :18;
};
#define rx_hdmi21_rx_scdc_00_00(val) ((rs_rx_hdmi21_rx_scdc_00_00*)&(val))



#define RX_HDMI21_RX_SCDC_00_04                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX_SCDC_00_04_struct                                   rs_rx_hdmi21_rx_scdc_00_04

typedef struct _rs_rx_hdmi21_rx_scdc_00_04  rs_rx_hdmi21_rx_scdc_00_04;
struct _rs_rx_hdmi21_rx_scdc_00_04 {
    unsigned int reg_00_I2CTIMOUTCNT                        :20;
    unsigned int reg_00_2CTIMOUTEN                          : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_00_I2CSPIKESUPPR                       : 2;
    unsigned int reserved_1                                 : 6;
};
#define rx_hdmi21_rx_scdc_00_04(val) ((rs_rx_hdmi21_rx_scdc_00_04*)&(val))



#define RX_HDMI21_RX_SCDC_00_08                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX_SCDC_00_08_struct                                   rs_rx_hdmi21_rx_scdc_00_08

typedef struct _rs_rx_hdmi21_rx_scdc_00_08  rs_rx_hdmi21_rx_scdc_00_08;
struct _rs_rx_hdmi21_rx_scdc_00_08 {
    unsigned int reg_00_POWERPROVIDED                       : 1;
    unsigned int reg_00_HPDLOW                              : 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_RR_IFFLAGS_ALREADYSET               : 1;
    unsigned int reserved_1                                 :27;
};
#define rx_hdmi21_rx_scdc_00_08(val) ((rs_rx_hdmi21_rx_scdc_00_08*)&(val))



#define RX_HDMI21_RX_SCDC_00_0C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x0C)

#define RX_HDMI21_RX_SCDC_00_0C_struct                                   rs_rx_hdmi21_rx_scdc_00_0c

typedef struct _rs_rx_hdmi21_rx_scdc_00_0c  rs_rx_hdmi21_rx_scdc_00_0c;
struct _rs_rx_hdmi21_rx_scdc_00_0c {
    unsigned int reg_00_MILISECTIMERLIMIT                   :16;
    unsigned int reg_00_hd_rx_scdc_errdet_clr               : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_00_CHLOCKMAXER                         :10;
    unsigned int reserved_1                                 : 2;
};
#define rx_hdmi21_rx_scdc_00_0c(val) ((rs_rx_hdmi21_rx_scdc_00_0c*)&(val))



#define RX_HDMI21_RX_SCDC_00_10                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x10)

#define RX_HDMI21_RX_SCDC_00_10_struct                                   rs_rx_hdmi21_rx_scdc_00_10

typedef struct _rs_rx_hdmi21_rx_scdc_00_10  rs_rx_hdmi21_rx_scdc_00_10;
struct _rs_rx_hdmi21_rx_scdc_00_10 {
    unsigned int regr_00_SCDC_SOURCEREVISION                : 8;
    unsigned int regr_00_SCDC_STATUSUPDATE                  : 1;
    unsigned int regr_00_SCDC_CEDUPDATE                     : 1;
    unsigned int regr_00_SCDC_RRTEST                        : 1;
    unsigned int regr_00_scdc_source_test_update            : 1;
    unsigned int regr_00_scdc_frl_start                     : 1;
    unsigned int regr_00_scdc_flt_update                    : 1;
    unsigned int regr_00_scdc_rsed_update                   : 1;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_SCDC_SCRAMBEN                      : 1;
    unsigned int regr_00_SCDC_TMDSBITCLKRATIO               : 1;
    unsigned int reserved_1                                 : 6;
    unsigned int regr_00_SCDC_SCRAMBSTATUS                  : 1;
    unsigned int reserved_2                                 : 7;
};
#define rx_hdmi21_rx_scdc_00_10(val) ((rs_rx_hdmi21_rx_scdc_00_10*)&(val))



#define RX_HDMI21_RX_SCDC_00_14                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x14)

#define RX_HDMI21_RX_SCDC_00_14_struct                                   rs_rx_hdmi21_rx_scdc_00_14

typedef struct _rs_rx_hdmi21_rx_scdc_00_14  rs_rx_hdmi21_rx_scdc_00_14;
struct _rs_rx_hdmi21_rx_scdc_00_14 {
    unsigned int regr_00_SCDC_RRENABLE                      : 1;
    unsigned int regr_00_hd21rx_flt_no_retrain              : 1;
    unsigned int regr_00_scdc_frl_rate                      : 4;
    unsigned int regr_00_scdc_ffe_levels                    : 4;
    unsigned int regr_00_SCDC_CLOCKDETECTED                 : 1;
    unsigned int regr_00_SCDC_CH0LOCKED                     : 1;
    unsigned int regr_00_SCDC_CH1LOCKED                     : 1;
    unsigned int regr_00_SCDC_CH2LOCKED                     : 1;
    unsigned int reserved                                   : 2;
    unsigned int regr_00_SCDC_ERRDET0                       :15;
    unsigned int regr_00_SCDC_ERRDET0_VALID                 : 1;
};
#define rx_hdmi21_rx_scdc_00_14(val) ((rs_rx_hdmi21_rx_scdc_00_14*)&(val))



#define RX_HDMI21_RX_SCDC_00_18                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX_SCDC_00_18_struct                                   rs_rx_hdmi21_rx_scdc_00_18

typedef struct _rs_rx_hdmi21_rx_scdc_00_18  rs_rx_hdmi21_rx_scdc_00_18;
struct _rs_rx_hdmi21_rx_scdc_00_18 {
    unsigned int regr_00_SCDC_ERRDET1                       :15;
    unsigned int regr_00_SCDC_ERRDET1_VALID                 : 1;
    unsigned int regr_00_SCDC_ERRDET2                       :15;
    unsigned int regr_00_SCDC_ERRDET2_VALID                 : 1;
};
#define rx_hdmi21_rx_scdc_00_18(val) ((rs_rx_hdmi21_rx_scdc_00_18*)&(val))



#define RX_HDMI21_RX_SCDC_00_1C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX_SCDC_00_1C_struct                                   rs_rx_hdmi21_rx_scdc_00_1c

typedef struct _rs_rx_hdmi21_rx_scdc_00_1c  rs_rx_hdmi21_rx_scdc_00_1c;
struct _rs_rx_hdmi21_rx_scdc_00_1c {
    unsigned int regr_00_SCDC_ERRDET3                       :15;
    unsigned int regr_00_SCDC_ERRDET3_VALID                 : 1;
    unsigned int regr_00_SCDC_RS_ERRCNT                     :15;
    unsigned int regr_00_SCDC_RS_VALID                      : 1;
};
#define rx_hdmi21_rx_scdc_00_1c(val) ((rs_rx_hdmi21_rx_scdc_00_1c*)&(val))



#define RX_HDMI21_RX_SCDC_00_20                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x20)

#define RX_HDMI21_RX_SCDC_00_20_struct                                   rs_rx_hdmi21_rx_scdc_00_20

typedef struct _rs_rx_hdmi21_rx_scdc_00_20  rs_rx_hdmi21_rx_scdc_00_20;
struct _rs_rx_hdmi21_rx_scdc_00_20 {
    unsigned int regr_00_MANUFACTURSPECIFICWR0              :32;
};
#define rx_hdmi21_rx_scdc_00_20(val) ((rs_rx_hdmi21_rx_scdc_00_20*)&(val))



#define RX_HDMI21_RX_SCDC_00_24                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x24)

#define RX_HDMI21_RX_SCDC_00_24_struct                                   rs_rx_hdmi21_rx_scdc_00_24

typedef struct _rs_rx_hdmi21_rx_scdc_00_24  rs_rx_hdmi21_rx_scdc_00_24;
struct _rs_rx_hdmi21_rx_scdc_00_24 {
    unsigned int regr_00_MANUFACTURSPECIFICWR1              :32;
};
#define rx_hdmi21_rx_scdc_00_24(val) ((rs_rx_hdmi21_rx_scdc_00_24*)&(val))



#define RX_HDMI21_RX_SCDC_00_28                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x28)

#define RX_HDMI21_RX_SCDC_00_28_struct                                   rs_rx_hdmi21_rx_scdc_00_28

typedef struct _rs_rx_hdmi21_rx_scdc_00_28  rs_rx_hdmi21_rx_scdc_00_28;
struct _rs_rx_hdmi21_rx_scdc_00_28 {
    unsigned int regr_00_MANUFACTURSPECIFICWR2              :32;
};
#define rx_hdmi21_rx_scdc_00_28(val) ((rs_rx_hdmi21_rx_scdc_00_28*)&(val))



#define RX_HDMI21_RX_SCDC_00_2C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x2C)

#define RX_HDMI21_RX_SCDC_00_2C_struct                                   rs_rx_hdmi21_rx_scdc_00_2c

typedef struct _rs_rx_hdmi21_rx_scdc_00_2c  rs_rx_hdmi21_rx_scdc_00_2c;
struct _rs_rx_hdmi21_rx_scdc_00_2c {
    unsigned int regr_00_MANUFACTURSPECIFICWR3              :32;
};
#define rx_hdmi21_rx_scdc_00_2c(val) ((rs_rx_hdmi21_rx_scdc_00_2c*)&(val))



#define RX_HDMI21_RX_SCDC_00_30                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x30)

#define RX_HDMI21_RX_SCDC_00_30_struct                                   rs_rx_hdmi21_rx_scdc_00_30

typedef struct _rs_rx_hdmi21_rx_scdc_00_30  rs_rx_hdmi21_rx_scdc_00_30;
struct _rs_rx_hdmi21_rx_scdc_00_30 {
    unsigned int regr_00_MANUFACTURSPECIFICWR4              :16;
    unsigned int regr_00_SCDC_TESTREADREQDELAY              : 7;
    unsigned int regr_00_SCDC_TESTREADREQ                   : 1;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_scdc_00_30(val) ((rs_rx_hdmi21_rx_scdc_00_30*)&(val))



#define RX_HDMI21_RX_SCDC_00_34                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX_SCDC_00_34_struct                                   rs_rx_hdmi21_rx_scdc_00_34

typedef struct _rs_rx_hdmi21_rx_scdc_00_34  rs_rx_hdmi21_rx_scdc_00_34;
struct _rs_rx_hdmi21_rx_scdc_00_34 {
    unsigned int reg_00_SINKVERSION                         : 8;
    unsigned int reg_00_MANUFACTUREROUI                     :24;
};
#define rx_hdmi21_rx_scdc_00_34(val) ((rs_rx_hdmi21_rx_scdc_00_34*)&(val))



#define RX_HDMI21_RX_SCDC_00_38                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX_SCDC_00_38_struct                                   rs_rx_hdmi21_rx_scdc_00_38

typedef struct _rs_rx_hdmi21_rx_scdc_00_38  rs_rx_hdmi21_rx_scdc_00_38;
struct _rs_rx_hdmi21_rx_scdc_00_38 {
    unsigned int reg_00_DEVICEID_STRING0                    :32;
};
#define rx_hdmi21_rx_scdc_00_38(val) ((rs_rx_hdmi21_rx_scdc_00_38*)&(val))



#define RX_HDMI21_RX_SCDC_00_3C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX_SCDC_00_3C_struct                                   rs_rx_hdmi21_rx_scdc_00_3c

typedef struct _rs_rx_hdmi21_rx_scdc_00_3c  rs_rx_hdmi21_rx_scdc_00_3c;
struct _rs_rx_hdmi21_rx_scdc_00_3c {
    unsigned int reg_00_DEVICEID_STRING1                    :32;
};
#define rx_hdmi21_rx_scdc_00_3c(val) ((rs_rx_hdmi21_rx_scdc_00_3c*)&(val))



#define RX_HDMI21_RX_SCDC_00_40                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x40)

#define RX_HDMI21_RX_SCDC_00_40_struct                                   rs_rx_hdmi21_rx_scdc_00_40

typedef struct _rs_rx_hdmi21_rx_scdc_00_40  rs_rx_hdmi21_rx_scdc_00_40;
struct _rs_rx_hdmi21_rx_scdc_00_40 {
    unsigned int reg_00_DEVICEID_MINORREV                   : 4;
    unsigned int reg_00_DEVICEID_MAJORREV                   : 4;
    unsigned int reg_00_DEVICEID_SWMAJORREV                 : 8;
    unsigned int reg_00_DEVICEID_SWMINORREV                 : 8;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_scdc_00_40(val) ((rs_rx_hdmi21_rx_scdc_00_40*)&(val))



#define RX_HDMI21_RX_SCDC_00_44                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x44)

#define RX_HDMI21_RX_SCDC_00_44_struct                                   rs_rx_hdmi21_rx_scdc_00_44

typedef struct _rs_rx_hdmi21_rx_scdc_00_44  rs_rx_hdmi21_rx_scdc_00_44;
struct _rs_rx_hdmi21_rx_scdc_00_44 {
    unsigned int reg_00_MANUFACTURSPECIFIC0                 :32;
};
#define rx_hdmi21_rx_scdc_00_44(val) ((rs_rx_hdmi21_rx_scdc_00_44*)&(val))



#define RX_HDMI21_RX_SCDC_00_48                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x48)

#define RX_HDMI21_RX_SCDC_00_48_struct                                   rs_rx_hdmi21_rx_scdc_00_48

typedef struct _rs_rx_hdmi21_rx_scdc_00_48  rs_rx_hdmi21_rx_scdc_00_48;
struct _rs_rx_hdmi21_rx_scdc_00_48 {
    unsigned int reg_00_MANUFACTURSPECIFIC1                 :32;
};
#define rx_hdmi21_rx_scdc_00_48(val) ((rs_rx_hdmi21_rx_scdc_00_48*)&(val))



#define RX_HDMI21_RX_SCDC_00_4C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x4C)

#define RX_HDMI21_RX_SCDC_00_4C_struct                                   rs_rx_hdmi21_rx_scdc_00_4c

typedef struct _rs_rx_hdmi21_rx_scdc_00_4c  rs_rx_hdmi21_rx_scdc_00_4c;
struct _rs_rx_hdmi21_rx_scdc_00_4c {
    unsigned int reg_00_MANUFACTURSPECIFIC2                 :32;
};
#define rx_hdmi21_rx_scdc_00_4c(val) ((rs_rx_hdmi21_rx_scdc_00_4c*)&(val))



#define RX_HDMI21_RX_SCDC_00_50                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x50)

#define RX_HDMI21_RX_SCDC_00_50_struct                                   rs_rx_hdmi21_rx_scdc_00_50

typedef struct _rs_rx_hdmi21_rx_scdc_00_50  rs_rx_hdmi21_rx_scdc_00_50;
struct _rs_rx_hdmi21_rx_scdc_00_50 {
    unsigned int reg_00_MANUFACTURSPECIFIC3                 :32;
};
#define rx_hdmi21_rx_scdc_00_50(val) ((rs_rx_hdmi21_rx_scdc_00_50*)&(val))



#define RX_HDMI21_RX_SCDC_00_54                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x54)

#define RX_HDMI21_RX_SCDC_00_54_struct                                   rs_rx_hdmi21_rx_scdc_00_54

typedef struct _rs_rx_hdmi21_rx_scdc_00_54  rs_rx_hdmi21_rx_scdc_00_54;
struct _rs_rx_hdmi21_rx_scdc_00_54 {
    unsigned int regr_00_SCRAMBDET                          : 1;
    unsigned int reserved                                   :31;
};
#define rx_hdmi21_rx_scdc_00_54(val) ((rs_rx_hdmi21_rx_scdc_00_54*)&(val))



#define RX_HDMI21_RX_SCDC_00_58                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x58)

#define RX_HDMI21_RX_SCDC_00_58_struct                                   rs_rx_hdmi21_rx_scdc_00_58

typedef struct _rs_rx_hdmi21_rx_scdc_00_58  rs_rx_hdmi21_rx_scdc_00_58;
struct _rs_rx_hdmi21_rx_scdc_00_58 {
    unsigned int reserved                                   : 2;
    unsigned int reg_00_hd21rx_ffe_pre_shoot_only           : 1;
    unsigned int reg_00_hd21rx_ffe_de_emphasis_only         : 1;
    unsigned int reg_00_hd21rx_ffe_no_ffe                   : 1;
    unsigned int reg_00_hd21rx_flt_no_timeout               : 1;
    unsigned int reg_00_hd21rx_dsc_frl_max                  : 1;
    unsigned int reg_00_hd21rx_frl_max                      : 1;
    unsigned int reg_00_hd21rx_frl_mode_on                  : 1;
    unsigned int reg_00_hd21rx_flt_ready                    : 1;
    unsigned int reg_00_hd21rx_flt_update_swset             : 1;
    unsigned int reg_00_hd21rx_frl_start_swset              : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int regr_00_hd21rx_daisy_err                   : 1;
    unsigned int regr_00_hd21rx_mono_dir_on                 : 1;
    unsigned int regr_00_hd21rx_mono_dir_err                : 1;
    unsigned int regr_00_hd21rx_ca_pwr_err                  : 1;
    unsigned int reg_00_hd21rx_cable_status                 : 1;
    unsigned int reserved_2                                 :14;
};
#define rx_hdmi21_rx_scdc_00_58(val) ((rs_rx_hdmi21_rx_scdc_00_58*)&(val))



#define RX_HDMI21_RX_SCDC_00_5C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x5C)

#define RX_HDMI21_RX_SCDC_00_5C_struct                                   rs_rx_hdmi21_rx_scdc_00_5c

typedef struct _rs_rx_hdmi21_rx_scdc_00_5c  rs_rx_hdmi21_rx_scdc_00_5c;
struct _rs_rx_hdmi21_rx_scdc_00_5c {
    unsigned int regr_00_hd21rx_scdc_offset10               : 8;
    unsigned int regr_00_hd21rx_scdc_offset31               : 8;
    unsigned int regr_00_hd21rx_scdc_offset40               : 8;
    unsigned int regr_00_hd21rx_scdc_offset41               : 8;
};
#define rx_hdmi21_rx_scdc_00_5c(val) ((rs_rx_hdmi21_rx_scdc_00_5c*)&(val))



#define RX_HDMI21_RX_SCDC_00_60                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x60)

#define RX_HDMI21_RX_SCDC_00_60_struct                                   rs_rx_hdmi21_rx_scdc_00_60

typedef struct _rs_rx_hdmi21_rx_scdc_00_60  rs_rx_hdmi21_rx_scdc_00_60;
struct _rs_rx_hdmi21_rx_scdc_00_60 {
    unsigned int regr_00_hd21rx_scdc_offset42               : 8;
    unsigned int regr_00_i2c_h2_h14_sel                     : 1;
    unsigned int regr_00_i2c_short_upd_rd                   : 1;
    unsigned int regr_00_ddc_rcurstate                      : 4;
    unsigned int reserved                                   :18;
};
#define rx_hdmi21_rx_scdc_00_60(val) ((rs_rx_hdmi21_rx_scdc_00_60*)&(val))



#define RX_HDMI21_RX_SCDC_00_6C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x6C)

#define RX_HDMI21_RX_SCDC_00_6C_struct                                   rs_rx_hdmi21_rx_scdc_00_6c

typedef struct _rs_rx_hdmi21_rx_scdc_00_6c  rs_rx_hdmi21_rx_scdc_00_6c;
struct _rs_rx_hdmi21_rx_scdc_00_6c {
    unsigned int reg_00_frl_start_time_th                   :16;
    unsigned int reg_00_frl_start_chk_gap                   : 1;
    unsigned int reg_00_frl_start_chk_blk                   : 1;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx_scdc_00_6c(val) ((rs_rx_hdmi21_rx_scdc_00_6c*)&(val))



#define RX_HDMI21_RX_SCDC_00_70                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x70)

#define RX_HDMI21_RX_SCDC_00_70_struct                                   rs_rx_hdmi21_rx_scdc_00_70

typedef struct _rs_rx_hdmi21_rx_scdc_00_70  rs_rx_hdmi21_rx_scdc_00_70;
struct _rs_rx_hdmi21_rx_scdc_00_70 {
    unsigned int reg_00_ED_MILISECTIMERLIMIT                :19;
    unsigned int reserved                                   :13;
};
#define rx_hdmi21_rx_scdc_00_70(val) ((rs_rx_hdmi21_rx_scdc_00_70*)&(val))



#define RX_HDMI21_RX_SCDC_00_74                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x74)

#define RX_HDMI21_RX_SCDC_00_74_struct                                   rs_rx_hdmi21_rx_scdc_00_74

typedef struct _rs_rx_hdmi21_rx_scdc_00_74  rs_rx_hdmi21_rx_scdc_00_74;
struct _rs_rx_hdmi21_rx_scdc_00_74 {
    unsigned int reg_00_err_cnt_update_mode                 : 1;
    unsigned int reg_00_err_cnt_sw_mode                     : 1;
    unsigned int reg_00_cedupd_sw                           : 1;
    unsigned int reg_00_rsedupd_sw                          : 1;
    unsigned int reg_00_err0_cnt_sw                         :16;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_scdc_00_74(val) ((rs_rx_hdmi21_rx_scdc_00_74*)&(val))



#define RX_HDMI21_RX_SCDC_00_78                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x78)

#define RX_HDMI21_RX_SCDC_00_78_struct                                   rs_rx_hdmi21_rx_scdc_00_78

typedef struct _rs_rx_hdmi21_rx_scdc_00_78  rs_rx_hdmi21_rx_scdc_00_78;
struct _rs_rx_hdmi21_rx_scdc_00_78 {
    unsigned int reg_00_err1_cnt_sw                         :16;
    unsigned int reg_00_err2_cnt_sw                         :16;
};
#define rx_hdmi21_rx_scdc_00_78(val) ((rs_rx_hdmi21_rx_scdc_00_78*)&(val))



#define RX_HDMI21_RX_SCDC_00_7C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x7C)

#define RX_HDMI21_RX_SCDC_00_7C_struct                                   rs_rx_hdmi21_rx_scdc_00_7c

typedef struct _rs_rx_hdmi21_rx_scdc_00_7c  rs_rx_hdmi21_rx_scdc_00_7c;
struct _rs_rx_hdmi21_rx_scdc_00_7c {
    unsigned int reg_00_err3_cnt_sw                         :16;
    unsigned int reg_00_rserr_cnt_sw                        :16;
};
#define rx_hdmi21_rx_scdc_00_7c(val) ((rs_rx_hdmi21_rx_scdc_00_7c*)&(val))



#define RX_HDMI21_RX_SCDC_00_80                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x80)

#define RX_HDMI21_RX_SCDC_00_80_struct                                   rs_rx_hdmi21_rx_scdc_00_80

typedef struct _rs_rx_hdmi21_rx_scdc_00_80  rs_rx_hdmi21_rx_scdc_00_80;
struct _rs_rx_hdmi21_rx_scdc_00_80 {
    unsigned int reg_00_rstatus_sw_mode                     : 1;
    unsigned int reg_00_ln0_locked_sw                       : 1;
    unsigned int reg_00_ln1_locked_sw                       : 1;
    unsigned int reg_00_ln2_locked_sw                       : 1;
    unsigned int reg_00_ln3_locked_sw                       : 1;
    unsigned int reg_00_clock_det_sw                        : 1;
    unsigned int reg_00_dsc_decoderfail_sw                  : 1;
    unsigned int reg_00_rstatus12_sw_mode                   : 1;
    unsigned int reg_00_ln0_ltp_req_sw                      : 4;
    unsigned int reg_00_ln1_ltp_req_sw                      : 4;
    unsigned int reg_00_ln2_ltp_req_sw                      : 4;
    unsigned int reg_00_ln3_ltp_req_sw                      : 4;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_scdc_00_80(val) ((rs_rx_hdmi21_rx_scdc_00_80*)&(val))



#define RX_HDMI21_RX_SCDC_00_88                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x88)

#define RX_HDMI21_RX_SCDC_00_88_struct                                   rs_rx_hdmi21_rx_scdc_00_88

typedef struct _rs_rx_hdmi21_rx_scdc_00_88  rs_rx_hdmi21_rx_scdc_00_88;
struct _rs_rx_hdmi21_rx_scdc_00_88 {
    unsigned int reg_00_errcnt_rd_timer_cnt                 :18;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx_scdc_00_88(val) ((rs_rx_hdmi21_rx_scdc_00_88*)&(val))



#define RX_HDMI21_RX_SCDC_00_8C                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0x8C)

#define RX_HDMI21_RX_SCDC_00_8C_struct                                   rs_rx_hdmi21_rx_scdc_00_8c

typedef struct _rs_rx_hdmi21_rx_scdc_00_8c  rs_rx_hdmi21_rx_scdc_00_8c;
struct _rs_rx_hdmi21_rx_scdc_00_8c {
    unsigned int reg_00_flt_update_hwset_cnt_clr            : 1;
    unsigned int reserved                                   : 3;
    unsigned int regr_00_flt_update_hwset_cnt               : 4;
    unsigned int reserved_1                                 :24;
};
#define rx_hdmi21_rx_scdc_00_8c(val) ((rs_rx_hdmi21_rx_scdc_00_8c*)&(val))



#define RX_HDMI21_RX_SCDC_00_A0                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0xA0)

#define RX_HDMI21_RX_SCDC_00_A0_struct                                   rs_rx_hdmi21_rx_scdc_00_a0

typedef struct _rs_rx_hdmi21_rx_scdc_00_a0  rs_rx_hdmi21_rx_scdc_00_a0;
struct _rs_rx_hdmi21_rx_scdc_00_a0 {
    unsigned int reserved                                   : 1;
    unsigned int reg_00_MODET_SWRESET                       : 1;
    unsigned int reg_00_HDMI_SWRESET                        : 1;
    unsigned int reg_00_BUS_SWRESET                         : 1;
    unsigned int reg_00_AUD_SWRESET                         : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_00_PIXEL_SWRESET                       : 1;
    unsigned int reg_00_VID_SWRESET                         : 1;
    unsigned int reg_00_SCDC_SWRESET                        : 1;
    unsigned int reg_00_CFG_SWRESET                         : 1;
    unsigned int reg_00_LTP_SWRESET                         : 1;
    unsigned int reserved_2                                 : 5;
    unsigned int reg_00_TMDS_SWRESET                        : 1;
    unsigned int reg_00_hd_mac_dbg_mux                      : 4;
    unsigned int reserved_3                                 :11;
};
#define rx_hdmi21_rx_scdc_00_a0(val) ((rs_rx_hdmi21_rx_scdc_00_a0*)&(val))



#define RX_HDMI21_RX_SCDC_00_A4                                          (HV_HDMI21_RX_SCDC_00_BASE_ADDRESS + 0xA4)

#define RX_HDMI21_RX_SCDC_00_A4_struct                                   rs_rx_hdmi21_rx_scdc_00_a4

typedef struct _rs_rx_hdmi21_rx_scdc_00_a4  rs_rx_hdmi21_rx_scdc_00_a4;
struct _rs_rx_hdmi21_rx_scdc_00_a4 {
    unsigned int reg_00_hd_rx_auto_rst_mac                  : 1;
    unsigned int reg_00_5v_det_sw_sel                       : 1;
    unsigned int reg_00_5v_det_sw_value                     : 1;
    unsigned int reg_00_HPD_to_eARC                         : 1;
    unsigned int reg_00_hdcp_ddc_enable                     : 1;
    unsigned int reserved                                   :27;
};
#define rx_hdmi21_rx_scdc_00_a4(val) ((rs_rx_hdmi21_rx_scdc_00_a4*)&(val))



#endif