/**
 * @file hv_cal_DpuSubScaler.h
 * @brief Header file of mute module.
 *
 * @verbatim
 * ==============================================================================
 *                        ##### How to use #####
 * ==============================================================================
 *
 * @endverbatim
 *
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-22
 */

#ifndef __HV_CAL_DPU_SUB_SCALER_H__
#define __HV_CAL_DPU_SUB_SCALER_H__

#include "hv_comm_DataType.h"

#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Define.h"

VOID Hv_Cal_DpuScaler_SubInit(VOID);

#ifdef HV_SCALER_DEBUG_VERSION
/*sub patt start*/
VOID Hv_Cal_DpuScaler_CapVgsfPattSettingsSub(const VideoConfigParams* pstVideoConfigParams);
/*sub patt end*/
#endif
VOID Hv_Cal_DpuScaler_CapVgsfSubInOutSize(const VideoConfigParams* pstVideoConfigParams);
/***********Dpu cap vgsf settings begin*********************/
/*cap vgsf c02 setting start*/
/*cap vgsf scf down setting start*/
/*****************sub*************************************/
/*cap vgsf mask setting start*/
USHORT16 Hv_Cal_DpuScaler_GetSubCuVsize(VOID);
VOID Hv_Cal_DpuScaler_SetCapVgsfSubCutParam(DpuCapCutParam* pstDpuCapCutParam);
/*cap vgsf mask setting end*/

/*cap vgsf c02 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC02ClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubC02Enable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubC02DeEnable(UINT32 uiValue);
/*cap vgsf c02 setting end*/

/*cap vgsf c24 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC24ClkEn(UINT32 uiValue);
/*cap vgsf c24 setting end*/

/*cap vgsf csc1 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubCsc1Config(const VideoConfigParams* pstVideoConfigParams);
BOOL Hv_Cal_DpuScaler_GetCapVgsfSubCsc1FunctionOn();
/*cap vgsf csc1 setting end*/

/*cap vgsf csc2 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfSubCsc2ClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCsc2ConvertOn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCsc2ConvertMode(UINT32 uiValue);
/*cap vgsf csc2 setting end*/

/*C42 begin*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC42FuncClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubC42On(UINT32 uiValue);
/*C42 end*/

/*C20 begin*/
VOID Hv_Cal_DpuScaler_CapVgsfSubC20FuncClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubC20Enable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubC20CbCrPosAdjEnable(BOOL bEn);

/*C20 end*/

/*cap vgsf scf down setting start*/

VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgMsfYhMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgMsfYvMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgHsfInSize(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgHsfOutSize(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCaVghfilbase(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgVsfInSize(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgVsfOutSize(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubCaVgVfilbase(UINT32 uiValue);
/*cap vgsf scf down setting end*/
/***********Dpu cap vgsf settings end*********************/

/*****************dpc srp  settings begin*****************/
VOID Hv_Cal_DpuScaler_SetSubWindowConifg(DpuWindowParam* pstSubChannelWindowParam);
VOID Hv_Cal_DpuScaler_LdgSubBorderEn(BOOL bEn);
/*Sub*/
VOID Hv_Cal_DpuScaler_DpcSrpSubUnpackClkEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpSubUpHbp(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpSubUpLastMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpSubDataMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpSubDataWidth(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcSrpSubFrcFrameSyncSel(UINT32 uiValue);
/*****************dpc srp  settings end*****************/
VOID Hv_Cal_DpuScaler_DtcSubWindowEn(UINT32 uiValue);



/***********dpc cap settings begin*********************/

VOID Hv_Cal_DpuScaler_DpcCapSubVmDataMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcCapSubVmDataBitWidth(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpcCapSubEncPackWork(UINT32 uiValue);
/***********dpc cap settings begin*********************/

/***********srp top main settings begin*********************/

/*sub*/
VOID Hv_Cal_DpuScaler_SrpTopSubSrPassthrough(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubSrSpatOn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubSrSpatMode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubSrSpatWith(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubC02Config(const VideoConfigParams* pstVideoConfigParams);
VOID Hv_Cal_DpuScaler_SrpTopSubSrC24Config(const VideoConfigParams* pstVideoConfigParams);

VOID Hv_Cal_DpuScaler_SrpTopSubSrCbScfOn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScThrouSw(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScCvmode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScChmode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScYvmode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScYhmode(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScUpClkEn(BOOL bEn);
VOID Hv_Cal_DpuScaler_SrpTopSubScHfilbase(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScVfilbase(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_SrpTopSubSrScfTableId(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubCtSrCbMtxOn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubScHflip(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_SrpTopSubMtxCtEnUsrmxThrough(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubSrCs1ConvertOn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SrpTopSubSrCs1ConvertMode(UINT32 uiValue);
/***********srp top settings end*********************/


/*****************vdm settings begin**************************/
/*WDMA line Mode Setting*/
VOID Hv_Cal_DpuScaler_DpuWvdm01WrEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpuRvdm01LineRdEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpuVdmSubConfig(const DpuVdmConfigSettings *pstDpuVdmConfigSettings);
VOID Hv_Cal_DpuScaler_SetSubVdmReadAddr0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SetSubVdmReadAddr1(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SetSubVdmWirteAddr0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SetSubVdmWirteAddr1(UINT32 uiValue);
UINT32 Hv_Cal_DpuScaler_GetSubVdmReadAddr0(VOID);
UINT32 Hv_Cal_DpuScaler_GetSubVdmReadAddr1(VOID);
/*****************vdm settings end*****************************/

/*****************sub ldg top settings begin***************************/

/*sub*/
VOID Hv_Cal_DpuScaler_SubLdgTopSubCscEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SubLdgTopSubBlendEn(UINT32 uiValue);

/*****************sub ldg top settings end***************************/


VOID Hv_Cal_DpuScaler_ScSubPvosPs0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScSubPvosPs1(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScSubFeildSel(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScSubFeildPolar(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_CapVgsfSubHdrPassthrough(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubHdrGmiEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubHdrGmdEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubHdrLutGmiEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubHdrLutOotfEn(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubHdrLutGmdEn(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_DpuVdmTblRdSubEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_DpuVdmTblRdSubTblTblEnable(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_CapVgsfSubHdrOotfEnable(UINT32 uiValue);

VOID Hv_Cal_DpuScaler_ScSubPhosPsA0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScSubPhosPsB0(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScSubOrfCrlev(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScSubOrfCblev(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_ScSubOrfYlev(UINT32 uiValue);
VOID Hv_Cal_DpuScaler_SetSubFrcIndex(BOOL bStart);
VOID Hv_Cal_DpuScaler_SetSubSrpLatch(BOOL bEn);
VOID Hv_Cal_DpuScaler_DpuDtcSubReadFreeze(BOOL bEn);
VOID Hv_Cal_DpuScaler_DpuDtcSubRx2ClkEn(BOOL bEn);

#endif
