#ifndef _HV_PAGE_HT7315_DPU_LDG_SYNC_H_
#define _HV_PAGE_HT7315_DPU_LDG_SYNC_H_

#ifndef HV_DPU_LDG_SYNC_BASE_ADDRESS
    #define HV_DPU_LDG_SYNC_BASE_ADDRESS                                         0x11028800
#endif


#define DISP_TOP_DPU_LDG_SYNC_00                                         (HV_DPU_LDG_SYNC_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_LDG_SYNC_00_struct                                  rs_disp_top_dpu_ldg_sync_00

typedef struct _rs_disp_top_dpu_ldg_sync_00  rs_disp_top_dpu_ldg_sync_00;
struct _rs_disp_top_dpu_ldg_sync_00 {
    unsigned int reg_ld_htotal                              :14;
    unsigned int reg_ld_vact                                :14;
    unsigned int reg_en                                     : 1;
    unsigned int reg_en_no_latch                            : 1;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_ldg_sync_00(val) ((rs_disp_top_dpu_ldg_sync_00*)&(val))



#define DISP_TOP_DPU_LDG_SYNC_04                                         (HV_DPU_LDG_SYNC_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_LDG_SYNC_04_struct                                  rs_disp_top_dpu_ldg_sync_04

typedef struct _rs_disp_top_dpu_ldg_sync_04  rs_disp_top_dpu_ldg_sync_04;
struct _rs_disp_top_dpu_ldg_sync_04 {
    unsigned int reg_ld_ref_vdly                            :14;
    unsigned int reg_ld_ref_hdly                            :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ldg_sync_04(val) ((rs_disp_top_dpu_ldg_sync_04*)&(val))



#define DISP_TOP_DPU_LDG_SYNC_08                                         (HV_DPU_LDG_SYNC_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_LDG_SYNC_08_struct                                  rs_disp_top_dpu_ldg_sync_08

typedef struct _rs_disp_top_dpu_ldg_sync_08  rs_disp_top_dpu_ldg_sync_08;
struct _rs_disp_top_dpu_ldg_sync_08 {
    unsigned int reg_ld_osd_ref_vdly                        :14;
    unsigned int reg_ld_osd_ref_hdly                        :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ldg_sync_08(val) ((rs_disp_top_dpu_ldg_sync_08*)&(val))



#define DISP_TOP_DPU_LDG_SYNC_10                                         (HV_DPU_LDG_SYNC_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_LDG_SYNC_10_struct                                  rs_disp_top_dpu_ldg_sync_10

typedef struct _rs_disp_top_dpu_ldg_sync_10  rs_disp_top_dpu_ldg_sync_10;
struct _rs_disp_top_dpu_ldg_sync_10 {
    unsigned int reg_ld_tbl_ref_vdly                        :14;
    unsigned int reg_ld_tbl_ref_hdly                        :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_ldg_sync_10(val) ((rs_disp_top_dpu_ldg_sync_10*)&(val))



#define DISP_TOP_DPU_LDG_SYNC_14                                         (HV_DPU_LDG_SYNC_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_LDG_SYNC_14_struct                                  rs_disp_top_dpu_ldg_sync_14

typedef struct _rs_disp_top_dpu_ldg_sync_14  rs_disp_top_dpu_ldg_sync_14;
struct _rs_disp_top_dpu_ldg_sync_14 {
    unsigned int reg_osd_wdma_height                        :12;
    unsigned int reg_osd_vs_div_num                         : 4;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_ldg_sync_14(val) ((rs_disp_top_dpu_ldg_sync_14*)&(val))



#define DISP_TOP_DPU_LDG_SYNC_18                                         (HV_DPU_LDG_SYNC_BASE_ADDRESS + 0x18)

#define DISP_TOP_DPU_LDG_SYNC_18_struct                                  rs_disp_top_dpu_ldg_sync_18

typedef struct _rs_disp_top_dpu_ldg_sync_18  rs_disp_top_dpu_ldg_sync_18;
struct _rs_disp_top_dpu_ldg_sync_18 {
    unsigned int reg_osd_sw_trig_en                         : 1;
    unsigned int reg_osd_sw_trig                            : 1;
    unsigned int reg_ld_tbl_sw_trig_en                      : 1;
    unsigned int reg_ld_tbl_trig_sel                        : 2;
    unsigned int reg_osd_tbl_sw_trig_en                     : 1;
    unsigned int reg_osd_tbl_trig_sel                       : 2;
    unsigned int reserved                                   :24;
};
#define disp_top_dpu_ldg_sync_18(val) ((rs_disp_top_dpu_ldg_sync_18*)&(val))



#define DISP_TOP_DPU_LDG_SYNC_1C                                         (HV_DPU_LDG_SYNC_BASE_ADDRESS + 0x1C)

#define DISP_TOP_DPU_LDG_SYNC_1C_struct                                  rs_disp_top_dpu_ldg_sync_1c

typedef struct _rs_disp_top_dpu_ldg_sync_1c  rs_disp_top_dpu_ldg_sync_1c;
struct _rs_disp_top_dpu_ldg_sync_1c {
    unsigned int reg_ld_sw_kspi_go                          : 1;
    unsigned int reg_ld_kspi_go_sel                         : 2;
    unsigned int reserved                                   :29;
};
#define disp_top_dpu_ldg_sync_1c(val) ((rs_disp_top_dpu_ldg_sync_1c*)&(val))



#endif