#ifndef _HV_PAGE_HT7315_EDP_RX_DPCD_7_REG_00_H_
#define _HV_PAGE_HT7315_EDP_RX_DPCD_7_REG_00_H_

#ifndef HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS
    #define HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS                                         0x11048400
#endif


#define RX_EDP_RX_DPCD_7_REG_00_00                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_DPCD_7_REG_00_00_struct                                rs_rx_edp_rx_dpcd_7_reg_00_00

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_00  rs_rx_edp_rx_dpcd_7_reg_00_00;
struct _rs_rx_edp_rx_dpcd_7_reg_00_00 {
    unsigned int reg_00_dprx_dpcd_edp_dpcd_rev              : 8;
    unsigned int reg_00_dprx_dpcd_disp_ctrl_backlight_adjustment_capable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_pin_enable_capable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_aux_enable_capable: 1;
    unsigned int reg_00_dprx_dpcd_panel_self_test_pin_enable_capable: 1;
    unsigned int reg_00_dprx_dpcd_pannel_self_test_aux__enable_capable: 1;
    unsigned int reg_00_dprx_dpcd_frc_enable_capable        : 1;
    unsigned int reg_00_dprx_dpcd_color_engine_capable      : 1;
    unsigned int reg_00_dprx_dpcd_set_power_capable         : 1;
    unsigned int reg_00_dprx_dpcd_backlight_brightness_pwm_pin_capable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_brightness_aux_set_capable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_brightness_byte_count: 1;
    unsigned int reg_00_dprx_dpcd_backlight_aux_pwm_product_capable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_freq_pwm_pin_pass_thru_capable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_freq_aux_set_capable: 1;
    unsigned int reg_00_dprx_dpcd_dynamic_backlight_capable : 1;
    unsigned int reg_00_dprx_dpcd_vblank_backlight_update_capable: 1;
    unsigned int reg_00_dprx_dpcd_overdrive_engine_enabled  : 1;
    unsigned int reserved                                   : 7;
};
#define rx_edp_rx_dpcd_7_reg_00_00(val) ((rs_rx_edp_rx_dpcd_7_reg_00_00*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_04                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_DPCD_7_REG_00_04_struct                                rs_rx_edp_rx_dpcd_7_reg_00_04

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_04  rs_rx_edp_rx_dpcd_7_reg_00_04;
struct _rs_rx_edp_rx_dpcd_7_reg_00_04 {
    unsigned int reg_00_dprx_dpcd_x_region_cap              : 4;
    unsigned int reg_00_dprx_dpcd_y_region_cap              : 4;
    unsigned int reserved                                   :24;
};
#define rx_edp_rx_dpcd_7_reg_00_04(val) ((rs_rx_edp_rx_dpcd_7_reg_00_04*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_20                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_DPCD_7_REG_00_20_struct                                rs_rx_edp_rx_dpcd_7_reg_00_20

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_20  rs_rx_edp_rx_dpcd_7_reg_00_20;
struct _rs_rx_edp_rx_dpcd_7_reg_00_20 {
    unsigned int reg_00_dprx_dpcd_backlight_enable          : 1;
    unsigned int reg_00_dprx_dpcd_black_video_enable        : 1;
    unsigned int reg_00_dprx_dpcd_frc_enable                : 1;
    unsigned int reg_00_dprx_dpcd_color_engine_enable       : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_00_dprx_dpcd_vblank_backlight_update_enable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_mode_set        : 2;
    unsigned int reg_00_dprx_dpcd_backlight_freq_pwm_pin_pass_thru_enable: 1;
    unsigned int reg_00_dprx_dpcd_backlight_freq_aux_set_enable: 1;
    unsigned int reg_00_dprx_dpcd_dynamic_backlight_enable  : 1;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_dprx_dpcd_backlight_brightness_msb  : 8;
    unsigned int reg_00_dprx_dpcd_backlight_brightness_lsb  : 8;
};
#define rx_edp_rx_dpcd_7_reg_00_20(val) ((rs_rx_edp_rx_dpcd_7_reg_00_20*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_24                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_DPCD_7_REG_00_24_struct                                rs_rx_edp_rx_dpcd_7_reg_00_24

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_24  rs_rx_edp_rx_dpcd_7_reg_00_24;
struct _rs_rx_edp_rx_dpcd_7_reg_00_24 {
    unsigned int reg_00_dprx_dpcd_pwmgen_bit_count          : 5;
    unsigned int reserved                                   : 3;
    unsigned int reg_00_dprx_pwmgen_bit_count_cap_min       : 5;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_dprx_pwmgen_bit_count_cap_max       : 5;
    unsigned int reserved_2                                 : 3;
    unsigned int reg_00_dprx_dpcd_backlight_control_status  : 1;
    unsigned int reserved_3                                 : 7;
};
#define rx_edp_rx_dpcd_7_reg_00_24(val) ((rs_rx_edp_rx_dpcd_7_reg_00_24*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_28                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_DPCD_7_REG_00_28_struct                                rs_rx_edp_rx_dpcd_7_reg_00_28

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_28  rs_rx_edp_rx_dpcd_7_reg_00_28;
struct _rs_rx_edp_rx_dpcd_7_reg_00_28 {
    unsigned int reg_00_dprx_dpcd_backlight_freq_set        : 8;
    unsigned int reserved                                   : 8;
    unsigned int reg_00_dprx_dpcd_backlight_freq_min_msb    : 8;
    unsigned int reg_00_dprx_dpcd_backlight_freq_min_mid    : 8;
};
#define rx_edp_rx_dpcd_7_reg_00_28(val) ((rs_rx_edp_rx_dpcd_7_reg_00_28*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_2C                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x2C)

#define RX_EDP_RX_DPCD_7_REG_00_2C_struct                                rs_rx_edp_rx_dpcd_7_reg_00_2c

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_2c  rs_rx_edp_rx_dpcd_7_reg_00_2c;
struct _rs_rx_edp_rx_dpcd_7_reg_00_2c {
    unsigned int reg_00_dprx_dpcd_backlight_freq_min_lsb    : 2;
    unsigned int reserved                                   : 6;
    unsigned int reg_00_dprx_dpcd_backlight_freq_max_msb    : 8;
    unsigned int reg_00_dprx_dpcd_backlight_freq_max_mid    : 8;
    unsigned int reg_00_dprx_dpcd_backlight_freq_max_lsb    : 2;
    unsigned int reserved_1                                 : 6;
};
#define rx_edp_rx_dpcd_7_reg_00_2c(val) ((rs_rx_edp_rx_dpcd_7_reg_00_2c*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_30                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x30)

#define RX_EDP_RX_DPCD_7_REG_00_30_struct                                rs_rx_edp_rx_dpcd_7_reg_00_30

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_30  rs_rx_edp_rx_dpcd_7_reg_00_30;
struct _rs_rx_edp_rx_dpcd_7_reg_00_30 {
    unsigned int reserved                                   :16;
    unsigned int reg_00_dprx_dpcd_dbc_minimum_brightness_set: 5;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_dprx_dpcd_dbc_maximum_brightness_set: 5;
    unsigned int reserved_2                                 : 3;
};
#define rx_edp_rx_dpcd_7_reg_00_30(val) ((rs_rx_edp_rx_dpcd_7_reg_00_30*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_34                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x34)

#define RX_EDP_RX_DPCD_7_REG_00_34_struct                                rs_rx_edp_rx_dpcd_7_reg_00_34

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_34  rs_rx_edp_rx_dpcd_7_reg_00_34;
struct _rs_rx_edp_rx_dpcd_7_reg_00_34 {
    unsigned int reg_00_dprx_dpcd_kgdc_5                    :32;
};
#define rx_edp_rx_dpcd_7_reg_00_34(val) ((rs_rx_edp_rx_dpcd_7_reg_00_34*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_38                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x38)

#define RX_EDP_RX_DPCD_7_REG_00_38_struct                                rs_rx_edp_rx_dpcd_7_reg_00_38

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_38  rs_rx_edp_rx_dpcd_7_reg_00_38;
struct _rs_rx_edp_rx_dpcd_7_reg_00_38 {
    unsigned int reg_00_dprx_dpcd_kgdc_6                    :32;
};
#define rx_edp_rx_dpcd_7_reg_00_38(val) ((rs_rx_edp_rx_dpcd_7_reg_00_38*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_3C                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x3C)

#define RX_EDP_RX_DPCD_7_REG_00_3C_struct                                rs_rx_edp_rx_dpcd_7_reg_00_3c

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_3c  rs_rx_edp_rx_dpcd_7_reg_00_3c;
struct _rs_rx_edp_rx_dpcd_7_reg_00_3c {
    unsigned int reg_00_dprx_dpcd_kgdc_7                    :32;
};
#define rx_edp_rx_dpcd_7_reg_00_3c(val) ((rs_rx_edp_rx_dpcd_7_reg_00_3c*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_40                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_DPCD_7_REG_00_40_struct                                rs_rx_edp_rx_dpcd_7_reg_00_40

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_40  rs_rx_edp_rx_dpcd_7_reg_00_40;
struct _rs_rx_edp_rx_dpcd_7_reg_00_40 {
    unsigned int reg_00_dprx_dpcd_kgdc_8                    :32;
};
#define rx_edp_rx_dpcd_7_reg_00_40(val) ((rs_rx_edp_rx_dpcd_7_reg_00_40*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_44                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_DPCD_7_REG_00_44_struct                                rs_rx_edp_rx_dpcd_7_reg_00_44

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_44  rs_rx_edp_rx_dpcd_7_reg_00_44;
struct _rs_rx_edp_rx_dpcd_7_reg_00_44 {
    unsigned int reg_00_dprx_dpcd_kgdc_9                    :32;
};
#define rx_edp_rx_dpcd_7_reg_00_44(val) ((rs_rx_edp_rx_dpcd_7_reg_00_44*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_48                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_DPCD_7_REG_00_48_struct                                rs_rx_edp_rx_dpcd_7_reg_00_48

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_48  rs_rx_edp_rx_dpcd_7_reg_00_48;
struct _rs_rx_edp_rx_dpcd_7_reg_00_48 {
    unsigned int reg_00_dprx_dpcd_kgdc_10                   :32;
};
#define rx_edp_rx_dpcd_7_reg_00_48(val) ((rs_rx_edp_rx_dpcd_7_reg_00_48*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_4C                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0x4C)

#define RX_EDP_RX_DPCD_7_REG_00_4C_struct                                rs_rx_edp_rx_dpcd_7_reg_00_4c

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_4c  rs_rx_edp_rx_dpcd_7_reg_00_4c;
struct _rs_rx_edp_rx_dpcd_7_reg_00_4c {
    unsigned int reg_00_dprx_dpcd_kgdc_11                   :32;
};
#define rx_edp_rx_dpcd_7_reg_00_4c(val) ((rs_rx_edp_rx_dpcd_7_reg_00_4c*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_A4                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0xA4)

#define RX_EDP_RX_DPCD_7_REG_00_A4_struct                                rs_rx_edp_rx_dpcd_7_reg_00_a4

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_a4  rs_rx_edp_rx_dpcd_7_reg_00_a4;
struct _rs_rx_edp_rx_dpcd_7_reg_00_a4 {
    unsigned int reg_00_dprx_dpcd_mso_number_of_links       : 3;
    unsigned int reg_00_dprx_dpcd_independent_link_bit      : 1;
    unsigned int reserved                                   : 4;
    unsigned int regr_00_dprx_dpcd_test_crc_r_cr_mso_2      :16;
    unsigned int regr_00_dprx_dpcd_test_crc_g_y_mso_2_l     : 8;
};
#define rx_edp_rx_dpcd_7_reg_00_a4(val) ((rs_rx_edp_rx_dpcd_7_reg_00_a4*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_A8                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0xA8)

#define RX_EDP_RX_DPCD_7_REG_00_A8_struct                                rs_rx_edp_rx_dpcd_7_reg_00_a8

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_a8  rs_rx_edp_rx_dpcd_7_reg_00_a8;
struct _rs_rx_edp_rx_dpcd_7_reg_00_a8 {
    unsigned int regr_00_dprx_dpcd_test_crc_g_y_mso_2_h     : 8;
    unsigned int regr_00_dprx_dpcd_test_crc_b_cb_mso_2      :16;
    unsigned int regr_00_dprx_dpcd_test_crc_count_mso_2     : 4;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dprd_test_crc_supported_mso_2  : 1;
    unsigned int reserved_1                                 : 2;
};
#define rx_edp_rx_dpcd_7_reg_00_a8(val) ((rs_rx_edp_rx_dpcd_7_reg_00_a8*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_AC                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0xAC)

#define RX_EDP_RX_DPCD_7_REG_00_AC_struct                                rs_rx_edp_rx_dpcd_7_reg_00_ac

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_ac  rs_rx_edp_rx_dpcd_7_reg_00_ac;
struct _rs_rx_edp_rx_dpcd_7_reg_00_ac {
    unsigned int regr_00_dprx_dpcd_test_crc_r_cr_mso_3      :16;
    unsigned int regr_00_dprx_dpcd_test_crc_g_y_mso_3       :16;
};
#define rx_edp_rx_dpcd_7_reg_00_ac(val) ((rs_rx_edp_rx_dpcd_7_reg_00_ac*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_B0                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0xB0)

#define RX_EDP_RX_DPCD_7_REG_00_B0_struct                                rs_rx_edp_rx_dpcd_7_reg_00_b0

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_b0  rs_rx_edp_rx_dpcd_7_reg_00_b0;
struct _rs_rx_edp_rx_dpcd_7_reg_00_b0 {
    unsigned int regr_00_dprx_dpcd_test_crc_b_cb_mso_3      :16;
    unsigned int regr_00_dprx_dpcd_test_crc_count_mso_3     : 4;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dprd_test_crc_supported_mso_3  : 1;
    unsigned int reserved_1                                 : 2;
    unsigned int regr_00_dprx_dpcd_test_crc_r_cr_mso_4_l    : 8;
};
#define rx_edp_rx_dpcd_7_reg_00_b0(val) ((rs_rx_edp_rx_dpcd_7_reg_00_b0*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_B4                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0xB4)

#define RX_EDP_RX_DPCD_7_REG_00_B4_struct                                rs_rx_edp_rx_dpcd_7_reg_00_b4

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_b4  rs_rx_edp_rx_dpcd_7_reg_00_b4;
struct _rs_rx_edp_rx_dpcd_7_reg_00_b4 {
    unsigned int regr_00_dprx_dpcd_test_crc_r_cr_mso_4_h    : 8;
    unsigned int regr_00_dprx_dpcd_test_crc_g_y_mso_4       :16;
    unsigned int regr_00_dprx_dpcd_test_crc_b_cb_mso_4_l    : 8;
};
#define rx_edp_rx_dpcd_7_reg_00_b4(val) ((rs_rx_edp_rx_dpcd_7_reg_00_b4*)&(val))



#define RX_EDP_RX_DPCD_7_REG_00_B8                                       (HV_EDP_RX_DPCD_7_REG_00_BASE_ADDRESS + 0xB8)

#define RX_EDP_RX_DPCD_7_REG_00_B8_struct                                rs_rx_edp_rx_dpcd_7_reg_00_b8

typedef struct _rs_rx_edp_rx_dpcd_7_reg_00_b8  rs_rx_edp_rx_dpcd_7_reg_00_b8;
struct _rs_rx_edp_rx_dpcd_7_reg_00_b8 {
    unsigned int regr_00_dprx_dpcd_test_crc_b_cb_mso_4_h    : 8;
    unsigned int regr_00_dprx_dpcd_test_crc_count_mso_4     : 4;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dprd_test_crc_supported_mso_4  : 1;
    unsigned int reserved_1                                 :18;
};
#define rx_edp_rx_dpcd_7_reg_00_b8(val) ((rs_rx_edp_rx_dpcd_7_reg_00_b8*)&(val))



#endif