#ifndef _HV_PAGE_HT7315_EDP_RX_MAC_BP_REG_01_H_
#define _HV_PAGE_HT7315_EDP_RX_MAC_BP_REG_01_H_

#ifndef HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS
    #define HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS                                         0x1104AA00
#endif


#define RX_EDP_RX_MAC_BP_REG_01_00                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_MAC_BP_REG_01_00_struct                                rs_rx_edp_rx_mac_bp_reg_01_00

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_00  rs_rx_edp_rx_mac_bp_reg_01_00;
struct _rs_rx_edp_rx_mac_bp_reg_01_00 {
    unsigned int reg_01_dprx_unpacker_hact_src_sel          : 1;
    unsigned int reg_01_dprx_unpacker_hact_use_en           : 1;
    unsigned int reg_01_dprx_sw_color_format                : 6;
    unsigned int reg_01_dprx_sw_color_fmt_en                : 1;
    unsigned int reg_01_dprx_sw_pixel_bpc                   : 7;
    unsigned int reg_01_dprx_regen_frm_trig_pos             :16;
};
#define rx_edp_rx_mac_bp_reg_01_00(val) ((rs_rx_edp_rx_mac_bp_reg_01_00*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_04                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_MAC_BP_REG_01_04_struct                                rs_rx_edp_rx_mac_bp_reg_01_04

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_04  rs_rx_edp_rx_mac_bp_reg_01_04;
struct _rs_rx_edp_rx_mac_bp_reg_01_04 {
    unsigned int reg_01_dprx_regen_vs_pos                   : 8;
    unsigned int reg_01_dprx_otg_src_sel                    : 8;
    unsigned int reg_01_dprx_otg_hact_auto                  : 2;
    unsigned int reg_01_dprx_otg_htotal_auto                : 1;
    unsigned int reg_01_dprx_remap_cut_en                   : 1;
    unsigned int reg_01_dprx_rgb_swap                       : 4;
    unsigned int reg_01_dprx_line_clr_en                    : 2;
    unsigned int reg_01_dprx_frm_clr_en                     : 3;
    unsigned int reg_01_dprx_remap_sel                      : 1;
    unsigned int reg_01_dprx_be2bebs_cnt_lane_sel           : 2;
};
#define rx_edp_rx_mac_bp_reg_01_04(val) ((rs_rx_edp_rx_mac_bp_reg_01_04*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_08                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_MAC_BP_REG_01_08_struct                                rs_rx_edp_rx_mac_bp_reg_01_08

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_08  rs_rx_edp_rx_mac_bp_reg_01_08;
struct _rs_rx_edp_rx_mac_bp_reg_01_08 {
    unsigned int reg_01_dprx_frm_clr_thro                   :32;
};
#define rx_edp_rx_mac_bp_reg_01_08(val) ((rs_rx_edp_rx_mac_bp_reg_01_08*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_0C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x0C)

#define RX_EDP_RX_MAC_BP_REG_01_0C_struct                                rs_rx_edp_rx_mac_bp_reg_01_0c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_0c  rs_rx_edp_rx_mac_bp_reg_01_0c;
struct _rs_rx_edp_rx_mac_bp_reg_01_0c {
    unsigned int reg_01_dprx_remap_htotal_min_thro          :16;
    unsigned int reg_01_dprx_remap_afifo_empty_timeout_thro : 8;
    unsigned int reg_01_dprx_remap_afifo_wr_cnt_diff_thro   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_0c(val) ((rs_rx_edp_rx_mac_bp_reg_01_0c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_10                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x10)

#define RX_EDP_RX_MAC_BP_REG_01_10_struct                                rs_rx_edp_rx_mac_bp_reg_01_10

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_10  rs_rx_edp_rx_mac_bp_reg_01_10;
struct _rs_rx_edp_rx_mac_bp_reg_01_10 {
    unsigned int reg_01_dprx_otg_hact                       :16;
    unsigned int reg_01_dprx_otg_vact                       :16;
};
#define rx_edp_rx_mac_bp_reg_01_10(val) ((rs_rx_edp_rx_mac_bp_reg_01_10*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_14                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x14)

#define RX_EDP_RX_MAC_BP_REG_01_14_struct                                rs_rx_edp_rx_mac_bp_reg_01_14

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_14  rs_rx_edp_rx_mac_bp_reg_01_14;
struct _rs_rx_edp_rx_mac_bp_reg_01_14 {
    unsigned int reg_01_dprx_otg_htotal                     :16;
    unsigned int reg_01_dprx_otg_vtotal                     :16;
};
#define rx_edp_rx_mac_bp_reg_01_14(val) ((rs_rx_edp_rx_mac_bp_reg_01_14*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_18                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x18)

#define RX_EDP_RX_MAC_BP_REG_01_18_struct                                rs_rx_edp_rx_mac_bp_reg_01_18

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_18  rs_rx_edp_rx_mac_bp_reg_01_18;
struct _rs_rx_edp_rx_mac_bp_reg_01_18 {
    unsigned int reg_01_dprx_otg_hbp                        :16;
    unsigned int reg_01_dprx_otg_vbp                        :16;
};
#define rx_edp_rx_mac_bp_reg_01_18(val) ((rs_rx_edp_rx_mac_bp_reg_01_18*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_1C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x1C)

#define RX_EDP_RX_MAC_BP_REG_01_1C_struct                                rs_rx_edp_rx_mac_bp_reg_01_1c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_1c  rs_rx_edp_rx_mac_bp_reg_01_1c;
struct _rs_rx_edp_rx_mac_bp_reg_01_1c {
    unsigned int reg_01_dprx_otg_hsw                        :16;
    unsigned int reg_01_dprx_otg_vsw                        :16;
};
#define rx_edp_rx_mac_bp_reg_01_1c(val) ((rs_rx_edp_rx_mac_bp_reg_01_1c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_20                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_MAC_BP_REG_01_20_struct                                rs_rx_edp_rx_mac_bp_reg_01_20

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_20  rs_rx_edp_rx_mac_bp_reg_01_20;
struct _rs_rx_edp_rx_mac_bp_reg_01_20 {
    unsigned int reg_01_dprx_mvid_chg_thd                   :24;
    unsigned int reg_01_dprx_out_patt                       : 3;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_dprx_post_de_gen_start_pulse_dly    : 4;
};
#define rx_edp_rx_mac_bp_reg_01_20(val) ((rs_rx_edp_rx_mac_bp_reg_01_20*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_24                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_MAC_BP_REG_01_24_struct                                rs_rx_edp_rx_mac_bp_reg_01_24

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_24  rs_rx_edp_rx_mac_bp_reg_01_24;
struct _rs_rx_edp_rx_mac_bp_reg_01_24 {
    unsigned int reg_01_dprx_regen_de_dly                   :16;
    unsigned int reg_01_dprx_remap_de_gen_start_dly_thro    : 4;
    unsigned int reg_01_dprx_enhanced_symbol_mask           : 2;
    unsigned int reg_01_dprx_unpacker_clr_dly               : 4;
    unsigned int reserved                                   : 6;
};
#define rx_edp_rx_mac_bp_reg_01_24(val) ((rs_rx_edp_rx_mac_bp_reg_01_24*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_28                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_MAC_BP_REG_01_28_struct                                rs_rx_edp_rx_mac_bp_reg_01_28

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_28  rs_rx_edp_rx_mac_bp_reg_01_28;
struct _rs_rx_edp_rx_mac_bp_reg_01_28 {
    unsigned int reg_01_dprx_line_clr_thro                  : 8;
    unsigned int reg_01_dprx_de_pulse_gen_dly               :24;
};
#define rx_edp_rx_mac_bp_reg_01_28(val) ((rs_rx_edp_rx_mac_bp_reg_01_28*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_2C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x2C)

#define RX_EDP_RX_MAC_BP_REG_01_2C_struct                                rs_rx_edp_rx_mac_bp_reg_01_2c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_2c  rs_rx_edp_rx_mac_bp_reg_01_2c;
struct _rs_rx_edp_rx_mac_bp_reg_01_2c {
    unsigned int reg_01_dprx_remap_de_gen_sel               : 1;
    unsigned int reg_01_dprx_de_first_gen_dly               :17;
    unsigned int reserved                                   :14;
};
#define rx_edp_rx_mac_bp_reg_01_2c(val) ((rs_rx_edp_rx_mac_bp_reg_01_2c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_30                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x30)

#define RX_EDP_RX_MAC_BP_REG_01_30_struct                                rs_rx_edp_rx_mac_bp_reg_01_30

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_30  rs_rx_edp_rx_mac_bp_reg_01_30;
struct _rs_rx_edp_rx_mac_bp_reg_01_30 {
    unsigned int reg_01_dprx_otg_hs_pol                     : 1;
    unsigned int reg_01_dprx_otg_vs_pol                     : 1;
    unsigned int reg_01_dprx_dpll_lock_afifo_clr_en         : 1;
    unsigned int reg_01_dprx_remap_wr_afifo_comp_en         : 1;
    unsigned int reg_01_dprx_remap_comp_pixel_num0          : 4;
    unsigned int reg_01_dprx_remap_comp_pixel_num1          : 4;
    unsigned int reg_01_dprx_remap_comp_pixel_num2          : 4;
    unsigned int reg_01_dprx_remap_comp_pixel_num3          : 4;
    unsigned int reg_01_dprx_remap_comp_pixel_sw_en         : 1;
    unsigned int reg_01_dprx_remap_comp_pixel_sw_en1        : 1;
    unsigned int reg_01_dprx_remap_comp_pixel_hact          :10;
};
#define rx_edp_rx_mac_bp_reg_01_30(val) ((rs_rx_edp_rx_mac_bp_reg_01_30*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_34                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x34)

#define RX_EDP_RX_MAC_BP_REG_01_34_struct                                rs_rx_edp_rx_mac_bp_reg_01_34

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_34  rs_rx_edp_rx_mac_bp_reg_01_34;
struct _rs_rx_edp_rx_mac_bp_reg_01_34 {
    unsigned int reg_01_dprx_remap_dbg_clr                  : 1;
    unsigned int reg_01_dprx_field_id_reverse               : 1;
    unsigned int reg_01_dprx_remap_afifo_clr                : 1;
    unsigned int reg_01_dprx_video_flag_mask                : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_01_dprx_audio_ts_header_mask           : 1;
    unsigned int reg_01_dprx_remap_lane_swap_mode           : 8;
    unsigned int reserved_1                                 : 7;
    unsigned int reg_01_dprx_port_swap                      : 1;
    unsigned int reg_01_dprx_remap_wr_mask_mode             : 2;
    unsigned int reg_01_dprx_remap_afifo_force_val          : 4;
    unsigned int reserved_2                                 : 2;
};
#define rx_edp_rx_mac_bp_reg_01_34(val) ((rs_rx_edp_rx_mac_bp_reg_01_34*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_38                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x38)

#define RX_EDP_RX_MAC_BP_REG_01_38_struct                                rs_rx_edp_rx_mac_bp_reg_01_38

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_38  rs_rx_edp_rx_mac_bp_reg_01_38;
struct _rs_rx_edp_rx_mac_bp_reg_01_38 {
    unsigned int reg_01_dprx_nvid_chg_thd                   :24;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_38(val) ((rs_rx_edp_rx_mac_bp_reg_01_38*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_3C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x3C)

#define RX_EDP_RX_MAC_BP_REG_01_3C_struct                                rs_rx_edp_rx_mac_bp_reg_01_3c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_3c  rs_rx_edp_rx_mac_bp_reg_01_3c;
struct _rs_rx_edp_rx_mac_bp_reg_01_3c {
    unsigned int reg_01_dprx_sw_vb_id                       :14;
    unsigned int reg_01_dprx_yuv420_2p_sel                  : 2;
    unsigned int reg_01_dprx_de_pulse_gen_thro              :16;
};
#define rx_edp_rx_mac_bp_reg_01_3c(val) ((rs_rx_edp_rx_mac_bp_reg_01_3c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_40                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_MAC_BP_REG_01_40_struct                                rs_rx_edp_rx_mac_bp_reg_01_40

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_40  rs_rx_edp_rx_mac_bp_reg_01_40;
struct _rs_rx_edp_rx_mac_bp_reg_01_40 {
    unsigned int reserved                                   : 4;
    unsigned int reg_01_dprx_msa_htotal_chg_en              : 1;
    unsigned int reg_01_dprx_msa_vtotal_chg_en              : 1;
    unsigned int reg_01_dprx_rw_htotal_chg_en               : 1;
    unsigned int reg_01_dprx_rw_vtotal_chg_en               : 1;
    unsigned int reg_01_dprx_msa_time_stable_thd            : 3;
    unsigned int reg_01_dprx_msa_time_stable_en             : 1;
    unsigned int reserved_1                                 :20;
};
#define rx_edp_rx_mac_bp_reg_01_40(val) ((rs_rx_edp_rx_mac_bp_reg_01_40*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_44                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_MAC_BP_REG_01_44_struct                                rs_rx_edp_rx_mac_bp_reg_01_44

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_44  rs_rx_edp_rx_mac_bp_reg_01_44;
struct _rs_rx_edp_rx_mac_bp_reg_01_44 {
    unsigned int reg_01_dprx_sw_maud_valid                  : 2;
    unsigned int reg_01_dprx_sw_maud                        :25;
    unsigned int reg_01_dprx_sdp_split_en                   : 1;
    unsigned int reg_01_dprx_desteer_key_thro               : 3;
    unsigned int reserved                                   : 1;
};
#define rx_edp_rx_mac_bp_reg_01_44(val) ((rs_rx_edp_rx_mac_bp_reg_01_44*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_48                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_MAC_BP_REG_01_48_struct                                rs_rx_edp_rx_mac_bp_reg_01_48

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_48  rs_rx_edp_rx_mac_bp_reg_01_48;
struct _rs_rx_edp_rx_mac_bp_reg_01_48 {
    unsigned int reg_01_dprx_sw_naud                        :25;
    unsigned int reserved                                   : 7;
};
#define rx_edp_rx_mac_bp_reg_01_48(val) ((rs_rx_edp_rx_mac_bp_reg_01_48*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_4C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x4C)

#define RX_EDP_RX_MAC_BP_REG_01_4C_struct                                rs_rx_edp_rx_mac_bp_reg_01_4c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_4c  rs_rx_edp_rx_mac_bp_reg_01_4c;
struct _rs_rx_edp_rx_mac_bp_reg_01_4c {
    unsigned int reg_01_dprx_video_sync_thro                :32;
};
#define rx_edp_rx_mac_bp_reg_01_4c(val) ((rs_rx_edp_rx_mac_bp_reg_01_4c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_50                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x50)

#define RX_EDP_RX_MAC_BP_REG_01_50_struct                                rs_rx_edp_rx_mac_bp_reg_01_50

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_50  rs_rx_edp_rx_mac_bp_reg_01_50;
struct _rs_rx_edp_rx_mac_bp_reg_01_50 {
    unsigned int reserved                                   :30;
    unsigned int reg_01_dprx_desteer_judge_en               : 2;
};
#define rx_edp_rx_mac_bp_reg_01_50(val) ((rs_rx_edp_rx_mac_bp_reg_01_50*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_54                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x54)

#define RX_EDP_RX_MAC_BP_REG_01_54_struct                                rs_rx_edp_rx_mac_bp_reg_01_54

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_54  rs_rx_edp_rx_mac_bp_reg_01_54;
struct _rs_rx_edp_rx_mac_bp_reg_01_54 {
    unsigned int reg_01_dprx_rw_htotal_chg_thd              :16;
    unsigned int reg_01_dprx_rw_vtotal_chg_thd              :16;
};
#define rx_edp_rx_mac_bp_reg_01_54(val) ((rs_rx_edp_rx_mac_bp_reg_01_54*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_58                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x58)

#define RX_EDP_RX_MAC_BP_REG_01_58_struct                                rs_rx_edp_rx_mac_bp_reg_01_58

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_58  rs_rx_edp_rx_mac_bp_reg_01_58;
struct _rs_rx_edp_rx_mac_bp_reg_01_58 {
    unsigned int reg_01_dprx_desteer_symbol_mask            : 8;
    unsigned int reg_01_dprx_bs_enhance_mst_en              : 1;
    unsigned int reserved                                   : 6;
    unsigned int reg_01_dprx_video_mst_en                   : 2;
    unsigned int reserved_1                                 : 2;
    unsigned int reg_01_dprx_desteer_mst_en                 : 2;
    unsigned int reserved_2                                 :11;
};
#define rx_edp_rx_mac_bp_reg_01_58(val) ((rs_rx_edp_rx_mac_bp_reg_01_58*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_5C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x5C)

#define RX_EDP_RX_MAC_BP_REG_01_5C_struct                                rs_rx_edp_rx_mac_bp_reg_01_5c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_5c  rs_rx_edp_rx_mac_bp_reg_01_5c;
struct _rs_rx_edp_rx_mac_bp_reg_01_5c {
    unsigned int reg_01_dprx_cursor_en                      : 1;
    unsigned int reg_01_dprx_cursor_color                   : 3;
    unsigned int reg_01_dprx_cursor_hwidth                  : 4;
    unsigned int reg_01_dprx_cursor_vwidth                  : 4;
    unsigned int reserved                                   :20;
};
#define rx_edp_rx_mac_bp_reg_01_5c(val) ((rs_rx_edp_rx_mac_bp_reg_01_5c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_60                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_MAC_BP_REG_01_60_struct                                rs_rx_edp_rx_mac_bp_reg_01_60

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_60  rs_rx_edp_rx_mac_bp_reg_01_60;
struct _rs_rx_edp_rx_mac_bp_reg_01_60 {
    unsigned int reg_01_dprx_cursor_hcnt                    :16;
    unsigned int reg_01_dprx_cursor_vcnt                    :16;
};
#define rx_edp_rx_mac_bp_reg_01_60(val) ((rs_rx_edp_rx_mac_bp_reg_01_60*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_64                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x64)

#define RX_EDP_RX_MAC_BP_REG_01_64_struct                                rs_rx_edp_rx_mac_bp_reg_01_64

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_64  rs_rx_edp_rx_mac_bp_reg_01_64;
struct _rs_rx_edp_rx_mac_bp_reg_01_64 {
    unsigned int regr_01_dprx_cursor_r                      :12;
    unsigned int regr_01_dprx_cursor_g                      :12;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_64(val) ((rs_rx_edp_rx_mac_bp_reg_01_64*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_68                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x68)

#define RX_EDP_RX_MAC_BP_REG_01_68_struct                                rs_rx_edp_rx_mac_bp_reg_01_68

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_68  rs_rx_edp_rx_mac_bp_reg_01_68;
struct _rs_rx_edp_rx_mac_bp_reg_01_68 {
    unsigned int regr_01_dprx_cursor_b                      :12;
    unsigned int reserved                                   :20;
};
#define rx_edp_rx_mac_bp_reg_01_68(val) ((rs_rx_edp_rx_mac_bp_reg_01_68*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_70                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x70)

#define RX_EDP_RX_MAC_BP_REG_01_70_struct                                rs_rx_edp_rx_mac_bp_reg_01_70

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_70  rs_rx_edp_rx_mac_bp_reg_01_70;
struct _rs_rx_edp_rx_mac_bp_reg_01_70 {
    unsigned int regr_01_dprx_mvid                          :24;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_70(val) ((rs_rx_edp_rx_mac_bp_reg_01_70*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_74                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x74)

#define RX_EDP_RX_MAC_BP_REG_01_74_struct                                rs_rx_edp_rx_mac_bp_reg_01_74

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_74  rs_rx_edp_rx_mac_bp_reg_01_74;
struct _rs_rx_edp_rx_mac_bp_reg_01_74 {
    unsigned int regr_01_dprx_nvid                          :24;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_74(val) ((rs_rx_edp_rx_mac_bp_reg_01_74*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_78                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x78)

#define RX_EDP_RX_MAC_BP_REG_01_78_struct                                rs_rx_edp_rx_mac_bp_reg_01_78

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_78  rs_rx_edp_rx_mac_bp_reg_01_78;
struct _rs_rx_edp_rx_mac_bp_reg_01_78 {
    unsigned int regr_01_dprx_maud                          :24;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_78(val) ((rs_rx_edp_rx_mac_bp_reg_01_78*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_7C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x7C)

#define RX_EDP_RX_MAC_BP_REG_01_7C_struct                                rs_rx_edp_rx_mac_bp_reg_01_7c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_7c  rs_rx_edp_rx_mac_bp_reg_01_7c;
struct _rs_rx_edp_rx_mac_bp_reg_01_7c {
    unsigned int regr_01_dprx_naud                          :24;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_7c(val) ((rs_rx_edp_rx_mac_bp_reg_01_7c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_80                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x80)

#define RX_EDP_RX_MAC_BP_REG_01_80_struct                                rs_rx_edp_rx_mac_bp_reg_01_80

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_80  rs_rx_edp_rx_mac_bp_reg_01_80;
struct _rs_rx_edp_rx_mac_bp_reg_01_80 {
    unsigned int regr_01_dprx_sdp_maud                      :24;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_80(val) ((rs_rx_edp_rx_mac_bp_reg_01_80*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_84                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x84)

#define RX_EDP_RX_MAC_BP_REG_01_84_struct                                rs_rx_edp_rx_mac_bp_reg_01_84

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_84  rs_rx_edp_rx_mac_bp_reg_01_84;
struct _rs_rx_edp_rx_mac_bp_reg_01_84 {
    unsigned int regr_01_dprx_sdp_naud                      :24;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_bp_reg_01_84(val) ((rs_rx_edp_rx_mac_bp_reg_01_84*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_88                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x88)

#define RX_EDP_RX_MAC_BP_REG_01_88_struct                                rs_rx_edp_rx_mac_bp_reg_01_88

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_88  rs_rx_edp_rx_mac_bp_reg_01_88;
struct _rs_rx_edp_rx_mac_bp_reg_01_88 {
    unsigned int regr_01_dprx_be2bs_cnt                     :32;
};
#define rx_edp_rx_mac_bp_reg_01_88(val) ((rs_rx_edp_rx_mac_bp_reg_01_88*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_8C                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x8C)

#define RX_EDP_RX_MAC_BP_REG_01_8C_struct                                rs_rx_edp_rx_mac_bp_reg_01_8c

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_8c  rs_rx_edp_rx_mac_bp_reg_01_8c;
struct _rs_rx_edp_rx_mac_bp_reg_01_8c {
    unsigned int regr_01_dprx_be2be_cnt                     :32;
};
#define rx_edp_rx_mac_bp_reg_01_8c(val) ((rs_rx_edp_rx_mac_bp_reg_01_8c*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_90                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0x90)

#define RX_EDP_RX_MAC_BP_REG_01_90_struct                                rs_rx_edp_rx_mac_bp_reg_01_90

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_90  rs_rx_edp_rx_mac_bp_reg_01_90;
struct _rs_rx_edp_rx_mac_bp_reg_01_90 {
    unsigned int regr_01_dprx_desteer_eoc_cnt               :32;
};
#define rx_edp_rx_mac_bp_reg_01_90(val) ((rs_rx_edp_rx_mac_bp_reg_01_90*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_A0                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xA0)

#define RX_EDP_RX_MAC_BP_REG_01_A0_struct                                rs_rx_edp_rx_mac_bp_reg_01_a0

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_a0  rs_rx_edp_rx_mac_bp_reg_01_a0;
struct _rs_rx_edp_rx_mac_bp_reg_01_a0 {
    unsigned int regr_01_dprx_desteer_chunk_size            :14;
    unsigned int reserved                                   :18;
};
#define rx_edp_rx_mac_bp_reg_01_a0(val) ((rs_rx_edp_rx_mac_bp_reg_01_a0*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_A4                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xA4)

#define RX_EDP_RX_MAC_BP_REG_01_A4_struct                                rs_rx_edp_rx_mac_bp_reg_01_a4

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_a4  rs_rx_edp_rx_mac_bp_reg_01_a4;
struct _rs_rx_edp_rx_mac_bp_reg_01_a4 {
    unsigned int reserved                                   :28;
    unsigned int regr_01_dprx_remap_afifo_underflow         : 4;
};
#define rx_edp_rx_mac_bp_reg_01_a4(val) ((rs_rx_edp_rx_mac_bp_reg_01_a4*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_A8                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xA8)

#define RX_EDP_RX_MAC_BP_REG_01_A8_struct                                rs_rx_edp_rx_mac_bp_reg_01_a8

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_a8  rs_rx_edp_rx_mac_bp_reg_01_a8;
struct _rs_rx_edp_rx_mac_bp_reg_01_a8 {
    unsigned int reserved                                   :28;
    unsigned int regr_01_dprx_remap_afifo_overflow          : 4;
};
#define rx_edp_rx_mac_bp_reg_01_a8(val) ((rs_rx_edp_rx_mac_bp_reg_01_a8*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_AC                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xAC)

#define RX_EDP_RX_MAC_BP_REG_01_AC_struct                                rs_rx_edp_rx_mac_bp_reg_01_ac

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_ac  rs_rx_edp_rx_mac_bp_reg_01_ac;
struct _rs_rx_edp_rx_mac_bp_reg_01_ac {
    unsigned int regr_01_dprx_remap_lane0_afifo_wr_cnt      :16;
    unsigned int regr_01_dprx_remap_lane1_afifo_wr_cnt      :16;
};
#define rx_edp_rx_mac_bp_reg_01_ac(val) ((rs_rx_edp_rx_mac_bp_reg_01_ac*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_B0                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xB0)

#define RX_EDP_RX_MAC_BP_REG_01_B0_struct                                rs_rx_edp_rx_mac_bp_reg_01_b0

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_b0  rs_rx_edp_rx_mac_bp_reg_01_b0;
struct _rs_rx_edp_rx_mac_bp_reg_01_b0 {
    unsigned int regr_01_dprx_remap_lane2_afifo_wr_cnt      :16;
    unsigned int regr_01_dprx_remap_lane3_afifo_wr_cnt      :16;
};
#define rx_edp_rx_mac_bp_reg_01_b0(val) ((rs_rx_edp_rx_mac_bp_reg_01_b0*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_B4                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xB4)

#define RX_EDP_RX_MAC_BP_REG_01_B4_struct                                rs_rx_edp_rx_mac_bp_reg_01_b4

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_b4  rs_rx_edp_rx_mac_bp_reg_01_b4;
struct _rs_rx_edp_rx_mac_bp_reg_01_b4 {
    unsigned int regr_01_dprx_rw_video_htotal               :16;
    unsigned int regr_01_dprx_rw_video_hact                 :16;
};
#define rx_edp_rx_mac_bp_reg_01_b4(val) ((rs_rx_edp_rx_mac_bp_reg_01_b4*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_B8                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xB8)

#define RX_EDP_RX_MAC_BP_REG_01_B8_struct                                rs_rx_edp_rx_mac_bp_reg_01_b8

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_b8  rs_rx_edp_rx_mac_bp_reg_01_b8;
struct _rs_rx_edp_rx_mac_bp_reg_01_b8 {
    unsigned int regr_01_dprx_rw_video_vact                 :16;
    unsigned int regr_01_dprx_rw_video_vtotal               :16;
};
#define rx_edp_rx_mac_bp_reg_01_b8(val) ((rs_rx_edp_rx_mac_bp_reg_01_b8*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_BC                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xBC)

#define RX_EDP_RX_MAC_BP_REG_01_BC_struct                                rs_rx_edp_rx_mac_bp_reg_01_bc

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_bc  rs_rx_edp_rx_mac_bp_reg_01_bc;
struct _rs_rx_edp_rx_mac_bp_reg_01_bc {
    unsigned int regr_01_dprx_rw_video_vtotal_cnt           :32;
};
#define rx_edp_rx_mac_bp_reg_01_bc(val) ((rs_rx_edp_rx_mac_bp_reg_01_bc*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_C0                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xC0)

#define RX_EDP_RX_MAC_BP_REG_01_C0_struct                                rs_rx_edp_rx_mac_bp_reg_01_c0

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_c0  rs_rx_edp_rx_mac_bp_reg_01_c0;
struct _rs_rx_edp_rx_mac_bp_reg_01_c0 {
    unsigned int regr_01_dprx_vb_id                         : 8;
    unsigned int regr_01_dprx_vid_pxl_format                : 6;
    unsigned int regr_01_dprx_vid_bpc                       : 7;
    unsigned int regr_01_dprx_vid_colorimety_format         : 4;
    unsigned int regr_01_dprx_msa_clk_sync_status           : 1;
    unsigned int regr_01_dprx_msa_vsc_sel                   : 1;
    unsigned int regr_01_dprx_msa_update_cnt                : 4;
    unsigned int reserved                                   : 1;
};
#define rx_edp_rx_mac_bp_reg_01_c0(val) ((rs_rx_edp_rx_mac_bp_reg_01_c0*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_C4                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xC4)

#define RX_EDP_RX_MAC_BP_REG_01_C4_struct                                rs_rx_edp_rx_mac_bp_reg_01_c4

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_c4  rs_rx_edp_rx_mac_bp_reg_01_c4;
struct _rs_rx_edp_rx_mac_bp_reg_01_c4 {
    unsigned int regr_01_dprx_msa_htotal                    :16;
    unsigned int regr_01_dprx_msa_vtotal                    :16;
};
#define rx_edp_rx_mac_bp_reg_01_c4(val) ((rs_rx_edp_rx_mac_bp_reg_01_c4*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_C8                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xC8)

#define RX_EDP_RX_MAC_BP_REG_01_C8_struct                                rs_rx_edp_rx_mac_bp_reg_01_c8

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_c8  rs_rx_edp_rx_mac_bp_reg_01_c8;
struct _rs_rx_edp_rx_mac_bp_reg_01_c8 {
    unsigned int regr_01_dprx_msa_hact                      :16;
    unsigned int regr_01_dprx_msa_vact                      :16;
};
#define rx_edp_rx_mac_bp_reg_01_c8(val) ((rs_rx_edp_rx_mac_bp_reg_01_c8*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_CC                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xCC)

#define RX_EDP_RX_MAC_BP_REG_01_CC_struct                                rs_rx_edp_rx_mac_bp_reg_01_cc

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_cc  rs_rx_edp_rx_mac_bp_reg_01_cc;
struct _rs_rx_edp_rx_mac_bp_reg_01_cc {
    unsigned int regr_01_dprx_msa_hstart                    :16;
    unsigned int regr_01_dprx_msa_vstart                    :16;
};
#define rx_edp_rx_mac_bp_reg_01_cc(val) ((rs_rx_edp_rx_mac_bp_reg_01_cc*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_D0                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xD0)

#define RX_EDP_RX_MAC_BP_REG_01_D0_struct                                rs_rx_edp_rx_mac_bp_reg_01_d0

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_d0  rs_rx_edp_rx_mac_bp_reg_01_d0;
struct _rs_rx_edp_rx_mac_bp_reg_01_d0 {
    unsigned int regr_01_dprx_msa_hsw                       :15;
    unsigned int regr_01_dprx_msa_hsp                       : 1;
    unsigned int regr_01_dprx_msa_vsw                       :15;
    unsigned int regr_01_dprx_msa_vsp                       : 1;
};
#define rx_edp_rx_mac_bp_reg_01_d0(val) ((rs_rx_edp_rx_mac_bp_reg_01_d0*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_D4                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xD4)

#define RX_EDP_RX_MAC_BP_REG_01_D4_struct                                rs_rx_edp_rx_mac_bp_reg_01_d4

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_d4  rs_rx_edp_rx_mac_bp_reg_01_d4;
struct _rs_rx_edp_rx_mac_bp_reg_01_d4 {
    unsigned int regr_01_dprx_msa_mvid                      :24;
    unsigned int regr_01_dprx_msa_misc0                     : 8;
};
#define rx_edp_rx_mac_bp_reg_01_d4(val) ((rs_rx_edp_rx_mac_bp_reg_01_d4*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_D8                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xD8)

#define RX_EDP_RX_MAC_BP_REG_01_D8_struct                                rs_rx_edp_rx_mac_bp_reg_01_d8

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_d8  rs_rx_edp_rx_mac_bp_reg_01_d8;
struct _rs_rx_edp_rx_mac_bp_reg_01_d8 {
    unsigned int regr_01_dprx_msa_nvid                      :24;
    unsigned int regr_01_dprx_msa_misc1                     : 8;
};
#define rx_edp_rx_mac_bp_reg_01_d8(val) ((rs_rx_edp_rx_mac_bp_reg_01_d8*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_DC                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xDC)

#define RX_EDP_RX_MAC_BP_REG_01_DC_struct                                rs_rx_edp_rx_mac_bp_reg_01_dc

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_dc  rs_rx_edp_rx_mac_bp_reg_01_dc;
struct _rs_rx_edp_rx_mac_bp_reg_01_dc {
    unsigned int regr_01_dprx_be_cnt                        :16;
    unsigned int regr_01_dprx_bs_cnt                        :16;
};
#define rx_edp_rx_mac_bp_reg_01_dc(val) ((rs_rx_edp_rx_mac_bp_reg_01_dc*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_E0                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xE0)

#define RX_EDP_RX_MAC_BP_REG_01_E0_struct                                rs_rx_edp_rx_mac_bp_reg_01_e0

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_e0  rs_rx_edp_rx_mac_bp_reg_01_e0;
struct _rs_rx_edp_rx_mac_bp_reg_01_e0 {
    unsigned int reserved                                   :20;
    unsigned int regr_01_dprx_bp_key_lane0                  : 2;
    unsigned int regr_01_dprx_bp_key_lane1                  : 2;
    unsigned int regr_01_dprx_bp_key_lane2                  : 2;
    unsigned int regr_01_dprx_bp_key_lane3                  : 2;
    unsigned int reserved_1                                 : 4;
};
#define rx_edp_rx_mac_bp_reg_01_e0(val) ((rs_rx_edp_rx_mac_bp_reg_01_e0*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_E4                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xE4)

#define RX_EDP_RX_MAC_BP_REG_01_E4_struct                                rs_rx_edp_rx_mac_bp_reg_01_e4

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_e4  rs_rx_edp_rx_mac_bp_reg_01_e4;
struct _rs_rx_edp_rx_mac_bp_reg_01_e4 {
    unsigned int regr_01_dprx_bp_data_lane0                 :16;
    unsigned int regr_01_dprx_bp_data_lane1                 :16;
};
#define rx_edp_rx_mac_bp_reg_01_e4(val) ((rs_rx_edp_rx_mac_bp_reg_01_e4*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_E8                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xE8)

#define RX_EDP_RX_MAC_BP_REG_01_E8_struct                                rs_rx_edp_rx_mac_bp_reg_01_e8

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_e8  rs_rx_edp_rx_mac_bp_reg_01_e8;
struct _rs_rx_edp_rx_mac_bp_reg_01_e8 {
    unsigned int regr_01_dprx_bp_data_lane2                 :16;
    unsigned int regr_01_dprx_bp_data_lane3                 :16;
};
#define rx_edp_rx_mac_bp_reg_01_e8(val) ((rs_rx_edp_rx_mac_bp_reg_01_e8*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_EC                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xEC)

#define RX_EDP_RX_MAC_BP_REG_01_EC_struct                                rs_rx_edp_rx_mac_bp_reg_01_ec

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_ec  rs_rx_edp_rx_mac_bp_reg_01_ec;
struct _rs_rx_edp_rx_mac_bp_reg_01_ec {
    unsigned int regr_01_dprx_sst_tu_size                   :32;
};
#define rx_edp_rx_mac_bp_reg_01_ec(val) ((rs_rx_edp_rx_mac_bp_reg_01_ec*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_F0                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xF0)

#define RX_EDP_RX_MAC_BP_REG_01_F0_struct                                rs_rx_edp_rx_mac_bp_reg_01_f0

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_f0  rs_rx_edp_rx_mac_bp_reg_01_f0;
struct _rs_rx_edp_rx_mac_bp_reg_01_f0 {
    unsigned int regr_01_dprx_sst_tu_valid                  :32;
};
#define rx_edp_rx_mac_bp_reg_01_f0(val) ((rs_rx_edp_rx_mac_bp_reg_01_f0*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_F4                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xF4)

#define RX_EDP_RX_MAC_BP_REG_01_F4_struct                                rs_rx_edp_rx_mac_bp_reg_01_f4

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_f4  rs_rx_edp_rx_mac_bp_reg_01_f4;
struct _rs_rx_edp_rx_mac_bp_reg_01_f4 {
    unsigned int regr_01_dprx_desteer_video_cnt             :16;
    unsigned int regr_01_dprx_desteer_msa_cnt               :16;
};
#define rx_edp_rx_mac_bp_reg_01_f4(val) ((rs_rx_edp_rx_mac_bp_reg_01_f4*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_F8                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xF8)

#define RX_EDP_RX_MAC_BP_REG_01_F8_struct                                rs_rx_edp_rx_mac_bp_reg_01_f8

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_f8  rs_rx_edp_rx_mac_bp_reg_01_f8;
struct _rs_rx_edp_rx_mac_bp_reg_01_f8 {
    unsigned int regr_01_dprx_desteer_sdp_cnt               :16;
    unsigned int regr_01_dprx_desteer_vbid_cnt              :16;
};
#define rx_edp_rx_mac_bp_reg_01_f8(val) ((rs_rx_edp_rx_mac_bp_reg_01_f8*)&(val))



#define RX_EDP_RX_MAC_BP_REG_01_FC                                       (HV_EDP_RX_MAC_BP_REG_01_BASE_ADDRESS + 0xFC)

#define RX_EDP_RX_MAC_BP_REG_01_FC_struct                                rs_rx_edp_rx_mac_bp_reg_01_fc

typedef struct _rs_rx_edp_rx_mac_bp_reg_01_fc  rs_rx_edp_rx_mac_bp_reg_01_fc;
struct _rs_rx_edp_rx_mac_bp_reg_01_fc {
    unsigned int regr_01_dprx_desteer_sr_cnt                :16;
    unsigned int regr_01_dprx_desteer_cp_cnt                :16;
};
#define rx_edp_rx_mac_bp_reg_01_fc(val) ((rs_rx_edp_rx_mac_bp_reg_01_fc*)&(val))



#endif