/**
 * @file hv_cal_DpuCprConfig.c
 * @brief cal dpu cpr c file.
 * @details This file provides the following functions: \n
 *          (1) Initialization and reset functions \n
 *
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-23
 * @copyright Copyright(c),2022-8, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                        <th>Date         <th>Change Description
 * <tr><td>HiView SoC Software Team      <td>2022-08-23   <td>init
 * </table>
*/

#include "hv_cal_DpuCprConfig.h"
#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Define.h"
#include "hv_comm_MemoryConfig.h"
#include "hv_comm_Assert.h"
#include "hv_comm_MemParser.h"
#include "hv_comm_DataBase.h"
#include "hv_cal_DpuMainScaler.h"

VOID Hv_Cal_DpuScaler_VdmCprMainInitfig(VOID)
{
    HV_W32_FIELD(DISP_TOP_DPU_LDG_SYNC_10, reg_ld_tbl_ref_vdly, 1);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_20, reg_00_dm_rd_total_line_num, 1);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_04, reg_00_dm_rd_outstanding, 2);
    Hv_Cal_DpuScaler_DpcSrpMainUnpackClkEn(1);
}

/*dpc/vdm ip enable start*/

VOID Hv_Cal_DpuScaler_DpuEncVdmWriteEnable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_44, reg_00_enc_write_enable, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_DpuDecVdmReadEnable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_read_enable, bEn);
    return;
}
/*dpc/vdm ip enable end*/


/*dpc/vdm ip dynamic config start*/

VOID Hv_Cal_DpuScaler_DpcSrpMainSettings(DpuDpcCapSrpParam* pstDpuDpcCapSrpParam)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_00_04, reg_00_ca_data_mode, pstDpuDpcCapSrpParam->ucCaDataMode);
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_00_04, reg_00_ca_data_bitwidth, pstDpuDpcCapSrpParam->ucCaDataBitwidth);
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_00_04, reg_00_ca_enc_pack_work, pstDpuDpcCapSrpParam->ucCaEncPackWork);
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_04, reg_m_dec_unpack_sel, pstDpuDpcCapSrpParam->ucDecUnpackSel);
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_08, reg_m_data_mode, pstDpuDpcCapSrpParam->ucDataMode);
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_08, reg_m_data_width, pstDpuDpcCapSrpParam->ucDataWidth);
    return;
}

/*dpc/vdm ip dynamic config end*/
VOID Hv_Cal_DpuScaler_DpcSrpMainEnc1ClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_00, reg_enc1_clk_en, bEn);   /*Main cpr*/
    return;
}

VOID Hv_Cal_DpuScaler_DpcSrpMainDecClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_08, reg_m_dec_clk_en, uiValue);  /*main cpr*/
    return;
}

VOID Hv_Cal_DpuScaler_DpcSrpMainEncClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_00_04, reg_00_ca_enc_clk_en, uiValue);  /*Main cpr*/
    return;
}

VOID Hv_Cal_DpuScaler_DpcSrpMainUnpackClkEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_08, reg_m_unpack_clk_en, uiValue);  /*main throuth*/
    return;
}

VOID Hv_Cal_DpuScaler_DpcSrpMainFrcFrameSyncSel(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_08, reg_m_frc_framesync_sel, uiValue);
    return;
}

/*cpr不支持奇数行压缩，需要scaler down多给一行数据*/
static UINT32  HandleVactiveOddToEven(UINT32 uiVactive)
{
    if (uiVactive % 2 != 0)
    {
        return uiVactive + 1;
    }
    else
    {
        return uiVactive;
    }
}

/*cpr只支持8的整数倍列，不是的情况下需要配置自动补点*/
static UINT32 HandleHactiveToMultEight(UINT32 uiHactive)
{
    if (uiHactive % 8 == 0)
    {
        return uiHactive; // 如果已经是8的倍数，直接返回
    }
    else
    {
        return uiHactive + (8 - (uiHactive % 8)); // 否则，增加到下一个8的倍数
    }
}



Status Hv_Cal_DpuScaler_MainCprEncodeConfig(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR(pstVideoConfigParams);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_00, reg_00_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_04, reg_00_hact, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_04, reg_00_vact, HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight));
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP1_DEC_00_28, reg_00_ksoc_cpr_pre_hact, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP1_DEC_00_28, reg_00_ksoc_cpr_pre_rstart, pstVideoConfigParams->uiDdrOrWtrVideoWidth / 2 + 20);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_00, reg_00_bypass_mode, 0);

    if ((DATA_PATH_MODE_COMPRESS_COLORFORMAT_YUV422 == pstVideoConfigParams->enDataPathMode)
     || (DATA_PATH_MODE_COMPRESS_RATIO_3_COLORFORMAT_YUV422 == pstVideoConfigParams->enDataPathMode))
    {
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_00, reg_00_422_mode, 1);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_00, reg_00_422_mode, 0);
    }
    /*Vflip 打开需要关闭lastline*/
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_00, reg_00_lastline_en, !pstVideoConfigParams->bVflipEnable);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_00, reg_00_vflip, pstVideoConfigParams->bVflipEnable);

    if (COMPRESS_RATIO_ONE_POINT_SIX == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /*Nvidia显卡低分辨率下字体抖动,降低到1.6倍*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_14, reg_00_lf_budget_packet, 120);
    }
    else if (COMPRESS_RATIO_TWO_POINT_FIVE == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /*IP给的标准2.5比例配置*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_14, reg_00_lf_budget_packet, 78);
    }
    else if (COMPRESS_RATIO_THREE == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /* 8 * 24bit / 3 ???待定配置需要根据效果调整*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_14, reg_00_lf_budget_packet, 64);
    }
    else if (COMPRESS_RATIO_FOUR == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /* 8 * 24 / 4 ???待定配置需要根据效果调整*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_14, reg_00_lf_budget_packet, 48);
    }
    else
    {
        return HV_FAILURE;
    }
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_E4, reg_00_delay_num, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_MainCprDecodeConfig(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR(pstVideoConfigParams);
    
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_04, reg_02_hact, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_04, reg_02_vact, HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight));
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP1_DEC_02_28, reg_02_ksoc_cpr_pre_hact, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP1_DEC_02_28, reg_02_ksoc_cpr_pre_rstart, pstVideoConfigParams->uiDdrOrWtrVideoWidth / 2 + 20);

    if ((DATA_PATH_MODE_COMPRESS_COLORFORMAT_YUV422 == pstVideoConfigParams->enDataPathMode)
     || (DATA_PATH_MODE_COMPRESS_RATIO_3_COLORFORMAT_YUV422 == pstVideoConfigParams->enDataPathMode))
    {
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_00, reg_02_422_mode, 1);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_00, reg_02_422_mode, 0);
    }
    /*Vflip 打开需要关闭lastline*/
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_00, reg_02_lastline_en, !pstVideoConfigParams->bVflipEnable);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_00, reg_02_vflip, pstVideoConfigParams->bVflipEnable);

    if (COMPRESS_RATIO_ONE_POINT_SIX == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /*Nvidia显卡低分辨率下字体抖动,降低到1.6倍*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_14, reg_02_lf_budget_packet, 120);
    }
    else if (COMPRESS_RATIO_TWO_POINT_FIVE == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /*IP给的标准2.5比例配置*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_14, reg_02_lf_budget_packet, 78);
    }
    else if (COMPRESS_RATIO_THREE == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /* 8 * 24bit / 3 ???待定配置需要根据效果调整*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_14, reg_02_lf_budget_packet, 64);
    }
    else if (COMPRESS_RATIO_FOUR == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        /* 8 * 24 / 4 ???待定配置需要根据效果调整*/
        HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_14, reg_02_lf_budget_packet, 48);
    }
    else
    {
        return HV_FAILURE;
    }

    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_E4, reg_02_delay_num, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    return HV_SUCCESS;
}



BOOL Hv_Cal_DpuScaler_MainCprDdrAddr(const VideoConfigParams* pstVideoConfigParams, MainCprDrrAddr* pstMainCprDrrAddr)
{
    HV_ASSERT_VALID_PTR(pstVideoConfigParams);
    UINT32 uiStartAddress0  = 0;
    UINT32 uiStartAddress1  = 0;
    UINT32 uiStartAddress2  = 0;
    UINT32 uiEndAddress0    = 0;
    UINT32 uiEndAddress1    = 0;
    UINT32 uiEndAddress2  = 0;
    USHORT16 usCprFactor    = 20;      // 20=除以8，再除以2.5倍压缩,(/8/2.5倍压缩)
#ifdef CONFIG_USER_DOUBLE_CHANNEL_ON
    //TODO:优化预留sub ddr size
    uiStartAddress0 = Hv_Board_Memory_FRCStart() + pstVideoConfigParams->uiSubChannelUsedMemory;
#else
    uiStartAddress0 = Hv_Board_Memory_FRCStart();
#endif

    if (COMPRESS_RATIO_ONE_POINT_SIX == pstVideoConfigParams->stFrameBufferCfg.enCompressRatio)
    {
        usCprFactor = 12;       // 12=除以8，再除以1.6倍压缩,(/8/1.6倍压缩)
    }
    
    UINT32 uiLineOffsetAddr = pstVideoConfigParams->uiDdrOrWtrVideoWidth * 2 * 30 / usCprFactor;        // 20=除以8，再除以2.5倍压缩

    if(pstVideoConfigParams->bInterlacedMode)
    {
        /*hactive*vactive*1frame*(bit*3))/8/2最小压缩率*/
        uiStartAddress1 = uiStartAddress0 + pstVideoConfigParams->uiDdrOrWtrVideoWidth * HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) * 30 / usCprFactor;
        /*interlace模式有第三帧,普通2帧配置上也无影响,未使用*/
        uiStartAddress2 = uiStartAddress1 + pstVideoConfigParams->uiDdrOrWtrVideoWidth*HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) * 30 / usCprFactor;
        uiEndAddress0 = uiStartAddress0 + (HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) / 2) * uiLineOffsetAddr;
        uiEndAddress1 = uiStartAddress1 + (HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) / 2) * uiLineOffsetAddr;
        uiEndAddress2 = uiStartAddress2 + (HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) / 2) * uiLineOffsetAddr;
        HV_LOG_DEBUG(VIDEO,"uiStartAddress2=0x%x,uiEndAddress2=0x%x",uiStartAddress2,uiEndAddress2);
        if((uiStartAddress2 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)) || (uiEndAddress2 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)))
        {
            HV_LOG_INFO(VIDEO,"Encode Interlace exceed ddr size uiEndAddress2=0x%x, FRCStart=0x%x",uiEndAddress2, Hv_Board_Memory_FRCStart());
            return HV_FALSE;
        }
    }
    else
    {
         /*hactive*vactive*1frame*(bit*3))/8/2最小压缩率*/
        uiStartAddress1 = uiStartAddress0 + pstVideoConfigParams->uiDdrOrWtrVideoWidth * HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) * 30 / usCprFactor;
        uiEndAddress0 = uiStartAddress0 + (HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) / 2) * uiLineOffsetAddr;
        uiEndAddress1 = uiStartAddress1 + (HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight) / 2) * uiLineOffsetAddr;
        HV_LOG_DEBUG(VIDEO,"FRC Start=0x%x,uiSubChannelUsedMemory=0x%x,uiStartAddress0=0x%x",Hv_Board_Memory_FRCStart(),pstVideoConfigParams->uiSubChannelUsedMemory,uiStartAddress0);
        HV_LOG_DEBUG(VIDEO,"uiStartAddress1=0x%x,uiEndAddress1=0x%x",uiStartAddress1,uiEndAddress1);
#if (HV_CONFIG_ON == HV_PROJECT_CONFIG_DPU_BRIGHT_FRAME)  // bright frame main使用1buf
        if ((HV_TRUE == HV_COMMON_DATABASE_GET(UserData, bBrightFrameEn)) && (HV_TRUE == Hv_Cal_DpuScaler_GetBrightFrameLowLatency()))
        {
            if((uiStartAddress1 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)) || (uiEndAddress0 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)))
            {
                HV_LOG_INFO(VIDEO,"Encode exceed ddr size uiEndAddress0=0x%x",uiEndAddress0);
                return HV_FALSE;
            }
        }
        else
        {
            if((uiStartAddress1 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)) || (uiEndAddress1 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)))
            {
                HV_LOG_INFO(VIDEO,"Encode exceed ddr size uiEndAddress1=0x%x",uiEndAddress1);
                return HV_FALSE;
            }
        }
#else
        if((uiStartAddress1 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)) || (uiEndAddress1 >= (0x80000000 + HV_MEMORY_CONFIG_DDR_SIZE)))
        {
            HV_LOG_INFO(VIDEO,"Encode exceed ddr size uiEndAddress1=0x%x",uiEndAddress1);
            return HV_FALSE;
        }
#endif
    }
    pstMainCprDrrAddr->uiStartAddress0  = uiStartAddress0;
    pstMainCprDrrAddr->uiStartAddress1  = uiStartAddress1;
    pstMainCprDrrAddr->uiStartAddress2  = uiStartAddress2;
    pstMainCprDrrAddr->uiEndAddress0    = uiEndAddress0;
    pstMainCprDrrAddr->uiEndAddress1    = uiEndAddress1;
    pstMainCprDrrAddr->uiEndAddress2    = uiEndAddress2;
    pstMainCprDrrAddr->uiLineOffsetAddr = uiLineOffsetAddr;
    return HV_TRUE;
}

Status Hv_Cal_DpuScaler_MainCprEncodeVdmConfig(const VideoConfigParams* pstVideoConfigParams)
{
    BOOL bDdrSizePass = 0;

    MainCprDrrAddr stMainCprDrrAddr = {0};
    bDdrSizePass = Hv_Cal_DpuScaler_MainCprDdrAddr(pstVideoConfigParams, &stMainCprDrrAddr);
    if (!bDdrSizePass)
    {
        return HV_FAILURE;
    }

    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_00, reg_00_enc_start_address0, stMainCprDrrAddr.uiStartAddress0);
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_04, reg_00_enc_start_address1, stMainCprDrrAddr.uiStartAddress1);
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_08, reg_00_enc_start_address2, stMainCprDrrAddr.uiStartAddress2);
    
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_20, reg_00_enc_end_address0, stMainCprDrrAddr.uiEndAddress0);
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_24, reg_00_enc_end_address1, stMainCprDrrAddr.uiEndAddress1);
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_28, reg_00_enc_end_address2, stMainCprDrrAddr.uiEndAddress2);
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_40, reg_00_enc_line_offset_addr, stMainCprDrrAddr.uiLineOffsetAddr);
    Hv_Cal_DpuScaler_DpuEncVdmWriteEnable(1);
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_54, reg_00_enc_vtotal, HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight));

    /*VDM cpr模式下不关注422 444 和IP确认固定配置成0*/
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_58, reg_00_enc_mode422_enable, 0);
    return HV_SUCCESS;
}

Status Hv_Cal_DpuScaler_MainCprDecodeVdmConfig(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR(pstVideoConfigParams);
    BOOL bDdrSizePass = 0;

    MainCprDrrAddr stMainCprDrrAddr = {0};
    bDdrSizePass = Hv_Cal_DpuScaler_MainCprDdrAddr(pstVideoConfigParams, &stMainCprDrrAddr);
    if (!bDdrSizePass)
    {
        return HV_FAILURE;
    }

    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_00, reg_00_dec_start_address0, stMainCprDrrAddr.uiStartAddress0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_04, reg_00_dec_start_address1, stMainCprDrrAddr.uiStartAddress1);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_08, reg_00_dec_start_address2, stMainCprDrrAddr.uiStartAddress2);

    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_20, reg_00_dec_end_address0, stMainCprDrrAddr.uiEndAddress0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_24, reg_00_dec_end_address1, stMainCprDrrAddr.uiEndAddress1);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_28, reg_00_dec_end_address2, stMainCprDrrAddr.uiEndAddress2);

    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_40, reg_00_dec_line_offset_addr, stMainCprDrrAddr.uiLineOffsetAddr);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_alen, 0x1f);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_qos, 0x10);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_cmdlen, 1);
    Hv_Cal_DpuScaler_DpuDecVdmReadEnable(1);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_mode, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_disable_frame_hold, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_read_err_clr, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_en, 1);

    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_dec_dynamic_crc_enable, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_48, reg_00_dec_threshold_m, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_48, reg_00_dec_threshold_n, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_4C, reg_00_dec_vtotal, HandleVactiveOddToEven(pstVideoConfigParams->uiDdrOrWtrVideoHight));
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_4C, reg_00_dec_vflip_enable, pstVideoConfigParams->bVflipEnable);

    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_4C, reg_00_dec_mode422_enable, 0);

    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_4C, reg_00_dec_4k_proc_enable, 1);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_4C, reg_00_dec_cmdlength_enable, 1);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_4C, reg_00_dec_sram_ls_en, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_4C, reg_00_dec_sram_ls_value, 0);

    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_50, reg_00_dec_dm_frmbuf_num, 2);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_50, reg_00_dec_dm_frmbuf_gap, 2);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_50, reg_00_dec_dm_frmbuf_mode, 1);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_50, reg_00_dec_dm_frmbuf_hold_en, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_50, reg_00_dec_dm_frmbuf_hold_idx, 0);
    return HV_SUCCESS;
}


