/**
 * @file hv_cal_DpuScaler.h.c
 * @brief DpuScaler CAL module driver
 * @details This module provide interfaces for DRV level.
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20220903
 * @copyright Copyright(c),2022-9, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date             <th>Details
 * <tr><td>HiView SoC Software Team       <td>20220903         <td>Create and first Version.
 * </table>
 **/


#include "HV_REGS_HT7315.h"
#include "hv_vos_Comm.h"
#include "hv_comm_Log.h"
#include "hv_comm_Assert.h"
#include "hv_cal_DpuMainScaler.h"
#include "hv_cal_PLL.h"
#include "PanelConfig.h"
#include "hv_chip_Clk.h"
#include "hv_comm_DataBase.h"
#include "hv_cal_DpuSubScaler.h"
#include "hv_cal_DpuCprConfig.h"
#include "hv_cal_SubMute.h"

static UINT32 s_uiLineIntEn = 0xFFFFFE;//

extern VOID Hv_Cal_DpuPQ_DpuMainPqInitConfig(UINT32 uiHactive, UINT32 uiVactive, UINT32 uiHtotalTyp);

extern BOOL Hv_Cal_DpuPQ_RdSharpnessEn(VOID);

static VOID Hv_Cal_DpuScaler_DpuMainPqInitConfig(UINT32 uiHactive, UINT32 uiVactive, UINT32 uiHtotalTyp)
{
    Hv_Cal_DpuPQ_DpuMainPqInitConfig(uiHactive, uiVactive, uiHtotalTyp);
}

VOID Hv_Cal_DpuScaler_Init(const PanelParam stPanelParam)
{
    /*cap vgsf pair map setting start*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_24, reg_00_ca_vg_pair_mapping_func_clk_en, 1);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_24, reg_00_ca_vg_pair_mapping_en, 1);
    /*10 01 00*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_24, reg_00_ca_vg_pair_mapping_patt, 36);

    /*C24 convert coef*//*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_28, reg_00_ca_vg_ch_coef_2tap, 0x2020);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_2C, reg_00_ca_vg_ch_coef_4tap, 0xf82828f8);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_28, reg_01_ca_vg_ch_coef_2tap, 0x2020);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_2C, reg_01_ca_vg_ch_coef_4tap, 0xf82828f8);
    /*C20 coef*//*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_C422_420_00_04, reg_00_422_420_3coef_0, 0x40);
    HV_W32_FIELD(DISP_TOP_C422_420_00_04, reg_00_422_420_3coef_1, 0x20);
    HV_W32_FIELD(DISP_TOP_C422_420_00_04, reg_00_422_420_3coef_2, 0x20);
    HV_W32_FIELD(DISP_TOP_C422_420_01_04, reg_01_422_420_3coef_0, 0x40);
    HV_W32_FIELD(DISP_TOP_C422_420_01_04, reg_01_422_420_3coef_1, 0x20);
    HV_W32_FIELD(DISP_TOP_C422_420_01_04, reg_01_422_420_3coef_2, 0x20);
#if (CONFIG_USER_PANEL_RESOLUTION_TYPE == PANEL_RESOLUTION_TYPE_UHD)
    HV_W32_FIELD(DISP_TOP_C422_420_00_08, reg_00_de_en, 0);
#endif

    /*配置4096 做scaler down时会参考上下2行 求平均*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_70, reg_00_ca_vg_phos_ps, 4096);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_74, reg_00_ca_vg_pvos_ps, 4096);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_70, reg_01_ca_vg_phos_ps, 4096);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_74, reg_01_ca_vg_pvos_ps, 4096);

    /*#sub ldg init start#*/
    HV_W32_FIELD(DISP_TOP_SUB_LDG_04, reg_main_csc_en, 1);
    /*#sub ldg init end#*/

    /*inp pattern apb clk en*/
    HV_W32_FIELD(RX_HSRX_CH_00_00, reg_00_hsrx_patt_apb_clk_en, 1);

    /*freeRunmode 1 default config*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_freerun1_tg_fw_frm_wdone, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_freerun1_tg_start_db_en, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_freerun1_tg_start, 1);

    /*上电之后关闭所有的DPU相关的latch，OSD除外*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_00, reg_00_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_00, reg_01_en_no_latch, 0); 
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_en_no_latch, 0); 
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_01_00, reg_01_en_no_latch, 0); 
    /* DISP_TOP_DPU_LDG_DPC_00 reg_en_no_latch的设置由ldc或者osd控制，此处不做处理 */
    //HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_00, reg_en_no_latch, 0); 
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_00, reg_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_SRP_CPS_00, reg_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_SRP_TOP_00, reg_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_SRP_S_TOP_00, reg_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_00, reg_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_00, reg_00_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_DPU_DEC_VDM_TOP_00_44, reg_00_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_DPU_ENC_VDM_TOP_00_44, reg_00_en_no_latch, 0);

    /*enc dec init*/
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_00_00, reg_00_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP0_DEC_02_00, reg_02_en_no_latch, 0);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP1_DEC_00_1C, reg_00_delay_gap, 38);
    HV_W32_FIELD(DISP_TOP_KOSD_CPR_TOP1_DEC_02_1C, reg_02_delay_gap, 38);

    HV_W32_FIELD(DISP_TOP_DTC_TOP_10, reg_tx_htotal_framesync, stPanelParam.usPanelHtotalType);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_14, reg_tx_vtotal_framesync_manual, stPanelParam.usPanelVtotalType);

    /*为了支持HDR效果OSD菜单动态修改，即修改HDR效果时动态修改个别寄存器即可，在配置链路时固定配置HDR寄存器*/
    Hv_Cal_DpuScaler_CapVgsfMainHdrPassthrough(0);
    Hv_Cal_DpuScaler_CapVgsfMainHdrLutGmiEn(1);
    Hv_Cal_DpuScaler_CapVgsfMainHdrLutOotfEn(1);/*TODO Use only GMI for Now*/
    Hv_Cal_DpuScaler_CapVgsfMainHdrLutGmdEn(1); /*TODO Use only GMI for Now*/
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_04, reg_00_dm_rd_access_mode, 0);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_04, reg_00_dm_rd_burst_rmd, 0);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_08, reg_00_dm_rd_burst_num, 0);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_0C, reg_00_dm_rd_col_step, 0x8000);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_10, reg_00_dm_rd_line_step, 0x8000);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_18, reg_00_dm_rd_col_dat_num, 0);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_20, reg_00_dm_rd_total_col_num, 1);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_20, reg_00_dm_rd_total_line_num, 1);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_68, reg_00_tbl_id_gmi, 4);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_68, reg_00_tbl_id_ootf, 5);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_68, reg_00_tbl_id_gmd, 6);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_6C, reg_00_dm_tbl_byte_len4, 0x4800);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_74, reg_00_dm_tbl_byte_len5, 0x800);
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_7C, reg_00_dm_tbl_byte_len6, 0x6180);
    
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_C8, reg_00_dm_tbl_burst_len, 0x1f);
    Hv_Cal_DpuScaler_DpuVdmTblRdMainEnable(1);
    Hv_Cal_DpuScaler_DpuVdmTblRdMainTblTblEnable(0x70);//TODO 0x70 == 01110000 = enable 4 5 6
    Hv_Cal_DpuScaler_DpuMainPqInitConfig(stPanelParam.usPanelHactive, stPanelParam.usPanelVactive, stPanelParam.usPanelHtotalType);

    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_08, reg_m_upk_hbp, 4);

    /*固定画背景*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_50, reg_dtc_ch0_en, 1);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_48, reg_dtc_ch0_hsta, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_48, reg_dtc_ch0_hend, (stPanelParam.usPanelHactive - 1));
    HV_W32_FIELD(DISP_TOP_DTC_TOP_4C, reg_dtc_ch0_vsta, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_4C, reg_dtc_ch0_vend, (stPanelParam.usPanelVactive - 1));
    /*Main channel 固定开*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_5C, reg_dtc_ch1_en, 1);

    /*PTCD PLL固定开启小数,设置default时钟*/
    Hv_Cal_PLL_PtcdpllInit();

    /*dtc meter clk select, 0: osc; 1: apb; 2:ip1_clk,3:ip2_clk,优先使用apb时钟*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_04, reg_dtc_ref_clk_sel, 1);

    /*写入ref_clk的频率值，用来参与计算，例如ref_clk时166.667MHz，那么整数部分设166，小数部分设667*1.024=683*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_00, reg_freq_refclk_int, HV_CHIP_CLK_APB_INT_ACTUAL);
    
    //UINT32 uiRefClkFrac = ((HV_CHIP_CLK_APB - (HV_CHIP_CLK_APB / 1000000) * 1000000) / 1000)  * 1024 / 1000;
    HV_W32_FIELD(DISP_TOP_DTC_TOP_04, reg_freq_refclk_frac, HV_CHIP_CLK_APB_FRAC_ACTUAL);

    /*Frame Sync的计算模式选择选0：根据当前值按比例调整1：直接计算*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_framesync_calc_mode, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_04, reg_pll_pre_div, 1);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_pll_fbdiv_int_prot_en, 1);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_frame_sync_restart_cnt, 2);

    /*fbdiv的结果选择：
    0：计算结果四舍五入
    1：计算结果向上取整
    2：计算结果向下取整
    3：使用手动设定值代替计算结果*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_08, reg_pll_fbdiv_sel, 0);
    /*
    Frame Sync模式下tx_vtotal的结果选择：
    0：计算结果四舍五入
    1：计算结果向上取整
    2：计算结果向下取整
    3：使用手动设定值代替计算结果*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_tx_vtotal_framesync_sel, 0);

    /*1 代表锁RX de*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_dtc_mon_timing_sel, 1);

    /*选择dtc输入的mute信号，mute的时候dtc framesync保持mute之前的timing
    0：hs_rx_ch0
    1：hs_rx_ch1
    2：强制为非mute
    3：强制为mute*/

    Hv_Cal_DpuScaler_DtcTimingSel(1);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_dtc_mute_en_sel, 0);
    Hv_Cal_DpuScaler_DtcDynamicPllEn(0);
    Hv_Cal_DpuScaler_DtcFrameSyncVrrModeEn(0);  
    /*seamless enable*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_seamless_en, 1);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_seamless_apply, 1);

    HV_W32_FIELD(SYS_BLK3_TOP_REG_00, reg_int_disp_vtotal_0, (stPanelParam.usPanelVactive + 2));
    HV_W32_FIELD(SYS_BLK3_TOP_REG_30, reg_int_disp_wclr_hs_24, 0xFFFFFE);
    /* set ldg rst and spi rst before local dimming init */
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_ldg_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_spi_rst_n, 1);
    /* set cap srp rst before PQ dma enable (rmove in cal_pll.c)*/
    //HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_cap_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_srp_rst_n, 1);

    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_tx_htotal_freerun, stPanelParam.usPanelHtotalType);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_10, reg_tx_vtotal_freerun, stPanelParam.usPanelVtotalType);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_14, reg_tx_hact, stPanelParam.usPanelHactive);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_1C, reg_tx_vact, stPanelParam.usPanelVactive);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_1C, reg_tx_vs_front, 8);

    HV_W32_FIELD(DISP_TOP_DPU_SR_SYNC_RW4, reg_sr_sync_tbl_trig_vdly, 1);
    HV_W32_FIELD(DISP_TOP_DPU_LDG_SYNC_10, reg_ld_tbl_ref_vdly, 1);
    HV_W32_FIELD(DISP_TOP_DPU_CA_SYNC_00_10, reg_00_ca_sync_tbl_trig_vdly, 1);

    Hv_Cal_DpuScaler_SetMainFrcIndexStart(1);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_init_r_index, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_init_w_index, 1);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_A0, reg_frc_s_init_r_index, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_A0, reg_frc_s_init_w_index, 1);

    /*cap vgsf pair map setting start*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_24, reg_01_ca_vg_pair_mapping_func_clk_en, 1);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_24, reg_01_ca_vg_pair_mapping_en, 1);
    /*10 01 00*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_01_24, reg_01_ca_vg_pair_mapping_patt, 36);
    /*cap vgsf pair map setting end*/
    HV_W32_FIELD(DISP_TOP_SRP_TOP_04, reg_sr_cb_scf_on, 1);
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_throu_sw, 0);
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_A0, reg_00_sr_scf_table_id, 9);
    /*srp数据要求必须是YUV444，LDG数据一定是RGB固定开CSC1*/
    /*Haocaiyan PQ modified, CSC must be off*/
    HV_W32_FIELD(DISP_TOP_SRP_TOP_14, reg_sr_cs1_convert_on, 0);
    HV_W32_FIELD(DISP_TOP_SRP_TOP_14, reg_sr_cs1_convert_mode, 7);

    HV_W32_FIELD(DISP_TOP_SUB_LDG_00, reg_main_mapping_en, 1);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_00, reg_main_mapping_patt, 0x12);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_88, reg_pip_alpha, 0);

    /*关闭不需要模块，优化功耗*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_10, reg_00_ca_in_pat_func_clk_en, 0);
    HV_W32_FIELD(DISP_TOP_DPU_CA_DPC_01_04, reg_01_ca_enc_clk_en, 0);   /*no used*/
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_00, reg_ana_osc_clk_en, 0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_00, reg_enc2_clk_en, 0);             /*no used*/
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_10, reg_s_dec_clk_en, 0);          /*no used*/
    HV_W32_FIELD(RX_HSRX_CH_01_00, reg_01_hsrx_patt_apb_clk_en, 0);     /*功能未使用*/
    Hv_Cal_DpuScaler_DpcSrpSubUnpackClkEn(0);                           /*默认设0*/
    Hv_Cal_DpuScaler_DpcSrpMainEnc1ClkEn(0);
    Hv_Cal_DpuScaler_DpcSrpMainDecClkEn(0);
    Hv_Cal_DpuScaler_DpcSrpMainUnpackClkEn(0);
    Hv_Cal_DpuScaler_DpcSrpMainEncClkEn(0);
    Hv_Cal_DpuScaler_DpuDtcSubRx2ClkEn(0);
    Hv_Cal_DpuScaler_SetSubMuteClkEn(0);
    Hv_Cal_DpuScaler_SrpTopSubScUpClkEn(0);
    return;
}

VOID Hv_Cal_DpuScaler_ResetClock_Enable(VOID)
{
    /*reset and clk en*/
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_osd_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_srp_div2_rst_n, 1);

    HV_W32_FIELD(SYS_SH06_TOP_08, reg_disp_ldg_div2_rst_n, 1);

    HV_W32_FIELD(SYS_SH06_TOP_04, reg_ip_rst_n, 3);

    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_spi_src_sel, 3);
    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_spi_div_num, 2);
    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_ip_clk_en, 1);
    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_axi_clk_en, 1);
    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_spi_clk_en, 1);
    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_pix_clk_en, 1);
    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_pix_clk_div_en, 0);
    HV_W32_FIELD(SYS_SH06_TOP_0C, reg_disp_pix_div_num, 1);
    
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_rx_deslice_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_rx_hdmi21_0_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_rx_hdmi21_1_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_usb_axi_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_hdrx_axi_rst_n, 1);
    HV_W32_FIELD(SYS_SH06_TOP_04, reg_dpu_axi_rst_n, 1);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_00, reg_en, 1);
}

VOID Hv_Cal_DpuScaler_DtcTopTimingParam(const DpuDtcTopTimingParam* pstDpuDtcTopTimingParam)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_04, reg_dtc_rbuf_clk_sel, pstDpuDtcTopTimingParam->ucDtcRbufClkSel);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_24, reg_cycle_refclk_delay, pstDpuDtcTopTimingParam->uiCycleRefclkDelay);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_2C, reg_cycle_refclk_framesync_range_min, pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRangeMin);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_28, reg_cycle_refclk_framesync_range_max, pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRangeMax);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_30, reg_cycle_refclk_framesync_restart_th,  pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRestartTh);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_34, reg_rx_vact, pstDpuDtcTopTimingParam->usRxVact);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_buf_num, pstDpuDtcTopTimingParam->ucFrcMainBufNum);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_98, reg_frc_m_rd_done_th, pstDpuDtcTopTimingParam->usFrcMainRdDoneTh);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_98, reg_frc_m_wr_done_th, pstDpuDtcTopTimingParam->usFrcMainWrDoneTh);
    return;
}

VOID Hv_Cal_DpuScaler_DtcFrameSyncHtotal(USHORT16 usHtotal)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_10, reg_tx_htotal_framesync, usHtotal);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_tx_htotal_freerun, usHtotal);
    return;
}


VOID Hv_Cal_DpuScaler_DtcTimingSel(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_dtc_timing_sel, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcFrameSyncVrrModeEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_framesync_vrr_mode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcTxVdeDummyNum(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_34, reg_tx_vde_dummy_num, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcMainWindowHstart(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_54, reg_dtc_ch1_hsta, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcMainWindowHend(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_54, reg_dtc_ch1_hend, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcMainWindowVstart(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_58, reg_dtc_ch1_vsta, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcMainWindowVend(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_58, reg_dtc_ch1_vend, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcFrcBufNum01(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_A0, reg_frc_s_buf_num, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcFrcRdDoneTh01(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_A4, reg_frc_s_rd_done_th, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_DtcFrcWrDoneTh01(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_A4, reg_frc_s_wr_done_th, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DtcDelayMode(UCHAR8 ucValue)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_0C, reg_dtc_delay_mode, ucValue);
    return;
}

/***********Dpu cap vgsf settings begin*********************/
#ifdef HV_SCALER_DEBUG_VERSION
VOID Hv_Cal_DpuScaler_CapVgsfPattSettingsMain(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_14, reg_00_ca_in_pat_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_1C, reg_00_ca_in_pat_vtotal, pstVideoConfigParams->uiInputVideoVtotal);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_14, reg_00_ca_in_pat_hact, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_1C, reg_00_ca_in_pat_vact, pstVideoConfigParams->uiInputVideoHight);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_18, reg_00_ca_in_pat_hwdth, 1);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_20, reg_00_ca_in_pat_vwdth, 1);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_18, reg_00_ca_in_pat_hbp, 10);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_20, reg_00_ca_in_pat_vbp, 10);
    return;
}
#endif

/*cap ip enable start*/

VOID Hv_Cal_DpuScaler_CapVgsfMainInCutEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_08, reg_00_ca_in_mask_on, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainOutCutEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_88, reg_00_ca_out_mask_on, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC02ClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_24, reg_00_ca_vg_c02_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC02Enable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_C420_422_00_00, reg_00_420_422_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC02DeEnable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_C420_422_00_08, reg_00_de_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC24ClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_28, reg_00_ca_vg_yuv422to444_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCs1FuncClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_cs1_convert_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCs1En(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_csc1_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrSwitch(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_50, reg_00_ca_vg_hdr_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCsc2ClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_50, reg_00_ca_vg_cs2_convert_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCsc2ConvertOn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_50, reg_00_ca_vg_cs2_convert_on, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapMsfFuncClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_68, reg_00_ca_msf_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC42FuncClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_90, reg_00_ca_vg_c42_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC42On(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_90, reg_00_ca_vg_c42_on, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC20FuncClkEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_90, reg_00_ca_vg_c20_func_clk_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC20Enable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_C422_420_00_00, reg_00_422_420_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainC20CbCrPosAdjEnable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_C422_420_00_04, reg_00_cbcr_pos_adj, bEn);
    return;
}

/*cap ip enable end*/

/*cap ip dynamic config start*/
VOID Hv_Cal_DpuScaler_SetCapVgsfMainInCutParam(DpuCapCutParam* pstDpuCapCutParam)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_08, reg_00_ca_in_cut_hstart, pstDpuCapCutParam->usCutHstart);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_0C, reg_00_ca_in_cut_hend, pstDpuCapCutParam->usCutHend);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_0C, reg_00_ca_in_cut_vstart, pstDpuCapCutParam->usCutVstart);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_10, reg_00_ca_in_cut_vend, pstDpuCapCutParam->usCutVend);
    return;
}

VOID Hv_Cal_DpuScaler_SetCapVgsfMainOutCutParam(DpuCapCutParam* pstDpuCapCutParam)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_88, reg_00_ca_out_cut_hstart, pstDpuCapCutParam->usCutHstart);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_88, reg_00_ca_out_cut_hend, pstDpuCapCutParam->usCutHend);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_8C, reg_00_ca_out_cut_vstart, pstDpuCapCutParam->usCutVstart);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_8C, reg_00_ca_out_cut_vend, pstDpuCapCutParam->usCutVend);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCapInSize(UINT32 uiRxInHact, UINT32 uiRxInVact)
{
    /*需要在过cap in cut之前设置，不能设cut之后的size*/
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_04, reg_00_ca_in_hsize, uiRxInHact);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_04, reg_00_ca_in_vsize, uiRxInVact);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainInOutSize(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_90, reg_00_ca_out_hsize, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_90, reg_00_ca_out_vsize, pstVideoConfigParams->uiDdrOrWtrVideoHight);

    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_28, reg_00_hdr_act_hsize, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_28, reg_00_hdr_act_vsize, pstVideoConfigParams->uiInputVideoHight);

    HV_W32_FIELD(DISP_TOP_C420_422_00_08, reg_00_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    /*C02 size*/
    HV_W32_FIELD(DISP_TOP_C420_422_00_0C, reg_00_hact, pstVideoConfigParams->uiInputVideoWidth);

#if (CONFIG_USER_PANEL_RESOLUTION_TYPE == PANEL_RESOLUTION_TYPE_UHD)
    HV_R32_DECL_VAR();
    /*Need to Add dummy_num*/
    UCHAR8 ucDenum = HV_R32_FIELD(RX_SH12_TOP_00_18, reg_00_mute_dummy_de_num);
    HV_W32_FIELD(DISP_TOP_C420_422_00_0C, reg_00_vact, pstVideoConfigParams->uiInputVideoHight+ ucDenum);
#else
    HV_W32_FIELD(DISP_TOP_C420_422_00_0C, reg_00_vact, pstVideoConfigParams->uiInputVideoHight);
#endif

    /*C20 size 是scaler down之后的和ddr的size保持一致,scaler down之后的de enable默认关掉所以不关注htotal配置，scalerdown之前打开de enable 关注htotal*/
    HV_W32_FIELD(DISP_TOP_C422_420_00_08, reg_00_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_C422_420_00_0C, reg_00_hact, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_C422_420_00_0C, reg_00_vact, pstVideoConfigParams->uiDdrOrWtrVideoHight);

    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_04, reg_m_upk_width, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_04, reg_m_upk_height, pstVideoConfigParams->uiDdrOrWtrVideoHight);

    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCsc2ConvertMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_50, reg_00_ca_vg_cs2_convert_mode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCaVgMsfYhMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_6C, reg_00_ca_vg_msf_yhmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainCaVgMsfYvMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_6C, reg_00_ca_vg_msf_yvmode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainScfDown(BOOL bCprMode, const DpucScalerParam* pstDpucScalerParam)
{
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_78, reg_00_ca_vg_hsf_in_size, pstDpucScalerParam->usHsfInize);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_78, reg_00_ca_vg_vsf_in_size, pstDpucScalerParam->usVsfInize);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_7C, reg_00_ca_vg_hsf_out_size, pstDpucScalerParam->usHsfOutsize);
    /*cpr模式不支持奇数，需要多送一行*/
    if ((HV_TRUE == bCprMode) && (0 != pstDpucScalerParam->usVsfOutsize%2))
    {
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_7C, reg_00_ca_vg_vsf_out_size, (pstDpucScalerParam->usVsfOutsize + pstDpucScalerParam->usVsfOutsize%2));
        Hv_Cal_DpuScaler_CapVgsfMainCaVgMsfYvMode(1);  //打开缩放模式
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_7C, reg_00_ca_vg_vsf_out_size, pstDpucScalerParam->usVsfOutsize);
    }
     
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_80, reg_00_ca_vg_hfilbase, pstDpucScalerParam->uiHfilbase);
    HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_84, reg_00_ca_vg_vfilbase, pstDpucScalerParam->uiVfilbase);
    return;
}

/*cap vgsf csc1 setting start*/
VOID Hv_Cal_DpuScaler_CapVgsfMainCsc1Config(const VideoConfigParams* pstVideoConfigParams)
{

    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    if (ColorFormatType_RGB != pstVideoConfigParams->stColor.eClrFormat)
    {
        /*YUV444格式固定转化为RGB*/
        Hv_Cal_DpuScaler_CapVgsfMainCs1FuncClkEn(1);
        Hv_Cal_DpuScaler_CapVgsfMainCs1En(1);
        if(pstVideoConfigParams->stColor.eClrRange == ColorRangeType_Full_Range)
        {
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_csc1_mode_mux, 0);
        }
        else
        {
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_csc1_mode_mux, 1);
        }

        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_hdr_csc1_ofs_in_v, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_3C, reg_00_ca_vg_hdr_csc1_ofs_in_y, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_48, reg_00_ca_vg_hdr_csc1_ofs_in_u, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_38, reg_00_ca_vg_csc1_y_r_coef, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_40, reg_00_ca_vg_csc1_u_g_coef, 0);
        HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_48, reg_00_ca_vg_csc1_v_b_coef, 0);
    }
    else /*RGB*/
    {
        /*RGB limited需要转化成RGB full 颜色才正确，否则会偏白色*/
        if (ColorRangeType_Limited_Range == pstVideoConfigParams->stColor.eClrRange)
        {
            Hv_Cal_DpuScaler_CapVgsfMainCs1FuncClkEn(1);
            Hv_Cal_DpuScaler_CapVgsfMainCs1En(1);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_csc1_mode_mux, 7);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_hdr_csc1_ofs_in_v, 0xF00);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_3C, reg_00_ca_vg_hdr_csc1_ofs_in_y, 0xF00);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_48, reg_00_ca_vg_hdr_csc1_ofs_in_u, 0xF00);

            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_38, reg_00_ca_vg_csc1_y_r_coef, 0x12A1);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_40, reg_00_ca_vg_csc1_u_g_coef, 0x12A1);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_48, reg_00_ca_vg_csc1_v_b_coef, 0x12A1);
        }
        else /*RGB full 不必做转化关闭CSC1*/
        {
            Hv_Cal_DpuScaler_CapVgsfMainCs1FuncClkEn(0);
            Hv_Cal_DpuScaler_CapVgsfMainCs1En(0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_csc1_mode_mux, 0);

            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_hdr_csc1_ofs_in_v, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_3C, reg_00_ca_vg_hdr_csc1_ofs_in_y, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_48, reg_00_ca_vg_hdr_csc1_ofs_in_u, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_38, reg_00_ca_vg_csc1_y_r_coef, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_40, reg_00_ca_vg_csc1_u_g_coef, 0);
            HV_W32_FIELD(DISP_TOP_DPU_CA_VGSF_00_48, reg_00_ca_vg_csc1_v_b_coef, 0);
        }
    }
    return;
}

BOOL Hv_Cal_DpuScaler_GetCapVgsfMainCsc1FunctionOn()
{
    UINT32 uiValueClkEn = 0;
    UINT32 uiValueCsc1En = 0;
    HV_R32_DECL_VAR();
    uiValueClkEn = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_cs1_convert_func_clk_en);
    uiValueCsc1En = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_00_30, reg_00_ca_vg_csc1_en);
    return (1 == uiValueClkEn) && (1 == uiValueCsc1En);
}

/***********dpc cap settings begin*********************/
UINT32 Hv_Cal_DpuScaler_GetDpcCapMainSyncHtotal()
{
    UINT32 uiValue = 0;
    HV_R32_DECL_VAR();
    uiValue = HV_R32_FIELD(DISP_TOP_DPU_CA_SYNC_00_04, reg_00_ca_htotal);
    return uiValue;
}

/*****************dpc srp  settings begin*****************/

VOID Hv_Cal_DpuScaler_DpcSrpMainUpkWidth(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_04, reg_m_upk_width, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpcSrpMainUpkHeight(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_04, reg_m_upk_height, uiValue);
    return;
}

/*****************dpc srp  settings end*****************/

/***********srp top main settings begin*********************/
VOID Hv_Cal_DpuScaler_SrpTopMainSrPassthrough(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_TOP_04, reg_sr_passthrough, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainSrSpatOn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_TOP_48, reg_sr_spat_on, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainSrSpatMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_TOP_48, reg_sr_spat_mode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainSrSpatWith(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SRP_TOP_48, reg_sr_spat_width, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainC02Config(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    UINT32 uiWidthScf  = pstVideoConfigParams->uiDdrOrWtrVideoWidth;
    UINT32 uiHeightScf = pstVideoConfigParams->uiDdrOrWtrVideoHight;
    /*数据使用water buffer模式跳过了 cap后面的C42 C20,SRP不能重复开启C02*/
    if ((ColorFormatType_YCbCr420 != pstVideoConfigParams->stFrameBufferCfg.enFBColorFormat)
        || (DATA_PATH_MODE_FRAMESYNC == pstVideoConfigParams->enDataPathMode))
    {
        HV_W32_FIELD(DISP_TOP_C420_422_02_00, reg_02_420_422_en, 0);
        HV_W32_FIELD(DISP_TOP_C420_422_02_08, reg_02_cbcr_pos_adj, 0);
    }
    else /*ddr 或者waterbuffer中配置的颜色格式是YUV420*/
    {
        HV_W32_FIELD(DISP_TOP_C420_422_02_00, reg_02_420_422_en, 1);
        HV_W32_FIELD(DISP_TOP_C420_422_02_08, reg_02_cbcr_pos_adj, 1);
    }
    HV_W32_FIELD(DISP_TOP_C420_422_02_08, reg_02_htotal, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(DISP_TOP_C420_422_02_08, reg_02_de_en, 0);
    HV_W32_FIELD(DISP_TOP_C420_422_02_0C, reg_02_hact, uiWidthScf);
    HV_W32_FIELD(DISP_TOP_C420_422_02_0C, reg_02_vact, uiHeightScf);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainSrC24Config(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    UINT32 uiWidthScf  = pstVideoConfigParams->uiDdrOrWtrVideoWidth;
    UINT32 uiHeightScf = pstVideoConfigParams->uiDdrOrWtrVideoHight;

    /*数据使用water buffer模式跳过了 cap后面的C42 C20,SRP不能重复开启C24*/
    if (((ColorFormatType_YCbCr420 == pstVideoConfigParams->stFrameBufferCfg.enFBColorFormat)
        || (ColorFormatType_YCbCr422 == pstVideoConfigParams->stFrameBufferCfg.enFBColorFormat))
        && (DATA_PATH_MODE_FRAMESYNC != pstVideoConfigParams->enDataPathMode))
    {
        HV_W32_FIELD(DISP_TOP_SRP_TOP_08, reg_sr_c24_on, 1);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_SRP_TOP_08, reg_sr_c24_on, 0);
    }

    HV_W32_FIELD(DISP_TOP_SRP_TOP_08, reg_sr_c24_mode, 1);/*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_SRP_TOP_08, reg_sr_c24_htap1, 0x48);/*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_SRP_TOP_08, reg_sr_c24_htap2, 0xF8);/*ALG Golden Setting*/
    HV_W32_FIELD(DISP_TOP_SRP_TOP_0C, reg_sr_c24_hsize, uiWidthScf);
    HV_W32_FIELD(DISP_TOP_SRP_TOP_0C, reg_sr_c24_vsize, uiHeightScf);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainConfig(const VideoConfigParams* pstVideoConfigParams)
{
    HV_W32_FIELD(DISP_TOP_SRP_TOP_3C,reg_sr_hcb_pre_hsize, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_SRP_TOP_3C, reg_sr_hcb_pre_vsize, pstVideoConfigParams->uiDdrOrWtrVideoHight);
    HV_W32_FIELD(DISP_TOP_SRP_TOP_58, reg_sr_hcb_hsize, pstVideoConfigParams->uiOutputVideoWidth);
    HV_W32_FIELD(DISP_TOP_SRP_TOP_58, reg_sr_hcb_vsize, pstVideoConfigParams->uiOutputVideoHight);

    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_04, reg_00_sc_hszin, pstVideoConfigParams->uiDdrOrWtrVideoWidth);
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_08, reg_00_sc_vszin, pstVideoConfigParams->uiDdrOrWtrVideoHight);
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_10, reg_00_sc_hszout, pstVideoConfigParams->uiOutputVideoWidth);
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_14 , reg_00_sc_vszout, pstVideoConfigParams->uiOutputVideoHight);

    if(pstVideoConfigParams->uiDdrOrWtrVideoHight == pstVideoConfigParams->uiOutputVideoHight)
    {
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_cvmode, 2);
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_yvmode, 2);
    }   
    else
    {
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_cvmode, 0);
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_yvmode, 0);
    }
    if(pstVideoConfigParams->uiDdrOrWtrVideoWidth == pstVideoConfigParams->uiOutputVideoWidth)
    {
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_chmode, 2);
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_yhmode, 2);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_chmode, 0);
        HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_yhmode, 0);
    }

    /*scaler up config*/
    HV_ASSERT_TRUE_VOID(pstVideoConfigParams->uiOutputVideoWidth > 0);
    HV_ASSERT_TRUE_VOID(pstVideoConfigParams->uiOutputVideoHight > 0);
    Hv_Cal_DpuScaler_SrpTopMainScHfilbase(8192 * pstVideoConfigParams->uiDdrOrWtrVideoWidth / pstVideoConfigParams->uiOutputVideoWidth);
    Hv_Cal_DpuScaler_SrpTopMainScVfilbase(8192 *  pstVideoConfigParams->uiDdrOrWtrVideoHight / pstVideoConfigParams->uiOutputVideoHight);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainScHfilbase(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_2C, reg_00_sc_hfilbase, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainScVfilbase(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_30, reg_00_sc_vfilbase, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SrpTopMainScHflip(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_00, reg_00_sc_h_flip, uiValue);
    return;
}

/*****************vdm settings begin**************************/
VOID Hv_Cal_DpuScaler_DpuRvdm00RdEnable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_04, reg_00_dm_rd_enable, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_DpuWvdm00WrEnable(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_08, reg_00_dm_wr_enable, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_DpuVdmMainConfig(const DpuVdmConfigSettings *pstDpuVdmConfigSettings)
{
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_04, reg_00_dm_rd_col_step_dir, pstDpuVdmConfigSettings->ucDmRdColStepDir);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_04, reg_00_dm_rd_line_step_dir, pstDpuVdmConfigSettings->ucDmRdLineStepDir);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_2C, reg_00_dm_start_adr2, pstDpuVdmConfigSettings->uiDmRdStartAdr2);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_2C, reg_00_dm_start_adr2, pstDpuVdmConfigSettings->uiDmWrStartAdr2);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_0C, reg_00_dm_rd_col_step, pstDpuVdmConfigSettings->uiDmColStep);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_18, reg_00_dm_rd_col_dat_num, pstDpuVdmConfigSettings->usDmRdColDatNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_20, reg_00_dm_rd_total_col_num, pstDpuVdmConfigSettings->usDmTotalColNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_04, reg_00_dm_rd_burst_len, pstDpuVdmConfigSettings->ucDmBurstLen);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_08, reg_00_dm_rd_burst_num, pstDpuVdmConfigSettings->uiDmBurstNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_04, reg_00_dm_rd_burst_rmd, pstDpuVdmConfigSettings->ucDmBurstRmd);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_10, reg_00_dm_rd_line_step, pstDpuVdmConfigSettings->uiDmLineStep);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_20, reg_00_dm_rd_total_line_num, pstDpuVdmConfigSettings->usDmTotalLineNum);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_04, reg_00_dm_rd_outstanding, pstDpuVdmConfigSettings->ucDmOutstanding);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_14, reg_00_dm_rd_start_adr, pstDpuVdmConfigSettings->uiDmRdStartAdr);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_24, reg_00_dm_start_adr0, pstDpuVdmConfigSettings->uiDmRdStartAdr0);
    HV_W32_FIELD(DISP_TOP_DPU_RVDM_00_28, reg_00_dm_start_adr1, pstDpuVdmConfigSettings->uiDmRdStartAdr1);

    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_10, reg_00_dm_wr_col_step, pstDpuVdmConfigSettings->uiDmColStep);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_1C, reg_00_dm_wr_total_col_num, pstDpuVdmConfigSettings->usDmTotalColNum);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_08, reg_00_dm_wr_burst_len, pstDpuVdmConfigSettings->ucDmBurstLen);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_0C, reg_00_dm_wr_burst_num, pstDpuVdmConfigSettings->uiDmBurstNum);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_08, reg_00_dm_wr_burst_rmd, pstDpuVdmConfigSettings->ucDmBurstRmd);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_14, reg_00_dm_wr_line_step, pstDpuVdmConfigSettings->uiDmLineStep);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_1C, reg_00_dm_wr_total_line_num, pstDpuVdmConfigSettings->usDmTotalLineNum);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_08, reg_00_dm_wr_outstanding, pstDpuVdmConfigSettings->ucDmOutstanding);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_18, reg_00_dm_wr_start_adr, pstDpuVdmConfigSettings->uiDmWrStartAdr);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_24, reg_00_dm_start_adr0, pstDpuVdmConfigSettings->uiDmWrStartAdr0);
    HV_W32_FIELD(DISP_TOP_DPU_WVDM_00_28, reg_00_dm_start_adr1, pstDpuVdmConfigSettings->uiDmWrStartAdr1);
    return;
}

VOID Hv_Cal_DpuScaler_MainReadFreezeEn(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_9C, reg_frc_m_read_freeze, bEn);
    return;
}
/*****************vdm settings end*****************************/

/*****************sub ldg top settings begin***************************/
VOID Hv_Cal_DpuScaler_SubLdgTopByPass(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_00, reg_ldg_top_bypass, uiValue);
    return;
}

/*main*/
VOID Hv_Cal_DpuScaler_SubLdgTopMainCscEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_04, reg_main_csc_en, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_SubLdgTopMainBlendEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_68, reg_main_blend_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopMainBorderEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_68, reg_main_border_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopBorderMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_84, reg_border_mode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopVsReleaseBlackEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F8, reg_black_insert_vs_release_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertColor(UCHAR8 ucR, UCHAR8 ucG, UCHAR8 ucB)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_68, reg_black_insert_color_r, ucR);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_68, reg_black_insert_color_g, ucG);
    HV_W32_FIELD(DISP_TOP_SUB_LDG_6C, reg_black_insert_color_b, ucB);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_00, reg_black_insert_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopldgMtxThrough(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_D0, reg_en_ldg_mtx_through, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertFwMode(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F0, reg_black_insert_fw_mode, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_SubLdgTopBlackInsertFwEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_F0, reg_fw_black_insert_enable, uiValue);
    return;
}

UINT32 Hv_Cal_DpuScaler_GetSubLdgTopBlackInsertFwMode()
{
    UINT32 uiValue = 0;
    HV_R32_DECL_VAR();
    uiValue = HV_R32_FIELD(DISP_TOP_SUB_LDG_F0, reg_black_insert_fw_mode);
    return uiValue;
}

UINT32 Hv_Cal_DpuScaler_GetSubLdgTopBlackInsertFwEnable()
{
    UINT32 uiValue = 0;
    HV_R32_DECL_VAR();
    uiValue = HV_R32_FIELD(DISP_TOP_SUB_LDG_F0, reg_fw_black_insert_enable);
    return uiValue;
}

/*****************sub ldg top settings end***************************/

VOID Hv_Cal_DpuScaler_SetPortMux(UINT32 uiValue)
{
    HV_W32_FIELD(RX_HSRX_TOP_00, reg_hsrx_out_sel, uiValue);
    return;
}

UINT32 Hv_Cal_DpuScaler_GetPortMux()
{
    UINT32 uiValue = 0;
    HV_R32_DECL_VAR();
    uiValue = HV_R32_FIELD(RX_HSRX_TOP_00, reg_hsrx_out_sel);
    return uiValue;
}

VOID Hv_Cal_DpuScaler_ScMainPvosPs0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_20, reg_00_sc_pvos_ps0, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScMainPhosPsA0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_24, reg_00_sc_phos_ps_A, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_ScMainPhosPsB0(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_28, reg_00_sc_phos_ps_B, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_ScMainOrfCrlev(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_38, reg_00_sc_orf_crlev, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_ScMainOrfCblev(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_38, reg_00_sc_orf_cblev, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_ScMainOrfYlev(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_38, reg_00_sc_orf_ylev, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_ScMainPvosPs1(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_A0, reg_00_sc_pvos_ps1, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScMainFeildSel(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_A0, reg_00_sc_field_sel, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_ScMainFeildPolar(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_REG_VIDEO_CUBIC_SCALER_V2_00_A0, reg_00_sc_field_polar, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrPassthrough(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_00, reg_00_ct_ldg_hdr_passthrough, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrGmiEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_00, reg_00_ct_en_gmi_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrOotfEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_04, reg_00_ct_en_ootf_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrGmdEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_14, reg_00_ct_en_gmd_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrLutGmiEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_58, reg_00_lut_hdr_gmi_en, uiValue);
    return;
}
VOID Hv_Cal_DpuScaler_CapVgsfMainHdrLutOotfEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_58, reg_00_lut_hdr_ootf_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrLutGmdEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_58, reg_00_lut_hdr_gmd_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrGmiPatternEn(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_48, reg_00_ldg_hdr_gmi_pattern_en, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_CapVgsfMainHdrPattern(UINT32 uiR, UINT32 uiG, UINT32 uiB)
{
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_4C, reg_00_ldg_hdr_pattern_rdata, uiR);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_50, reg_00_ldg_hdr_pattern_gdata, uiG);
    HV_W32_FIELD(DISP_TOP_LDG_HDR_REG_00_54, reg_00_ldg_hdr_pattern_bdata, uiB);
    return;
}

VOID Hv_Cal_DpuScaler_DpuVdmTblRdMainEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_04, reg_00_dm_rd_enable, uiValue);
    return;
}

VOID Hv_Cal_DpuScaler_DpuVdmTblRdMainTblTblEnable(UINT32 uiValue)
{
    HV_W32_FIELD(DISP_TOP_DPU_VDM_TBL_RD_00_C8, reg_00_dm_tbl_enable, uiValue);
    return;
}

#define KSPI_SEND_BYTE_PER_TIMES      100
USHORT16 s_usDataSizeToBeSend = 0;
VOID Hv_Cal_DpuScaler_SendKspiData(UCHAR8* pucData, USHORT16 usDataSize)
{
    s_usDataSizeToBeSend = usDataSize;
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_sw_init_en, 0);
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_sw_init_en, 1);
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_44, reg_kspi_wrbuf_sel, 0);

    if (KSPI_SEND_BYTE_PER_TIMES >= KSPI_SEND_BYTE_PER_TIMES)
    {
        HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_vld_num, KSPI_SEND_BYTE_PER_TIMES);
        s_usDataSizeToBeSend = s_usDataSizeToBeSend - KSPI_SEND_BYTE_PER_TIMES;
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_vld_num, s_usDataSizeToBeSend);
    }
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_set_vld, 0);
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_set_vld, 1);

    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_44, reg_kspi_sw_start_en, 0);
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_44, reg_kspi_sw_start_en, 1);

    HV_W32_FIELD(DISP_TOP_KSPI_01_REGISTER_70, reg_kspi_int_en, 1);

    return;
}

VOID Hv_Cal_DpuScaler_SendRemainKspiDataInISR()
{
    if (s_usDataSizeToBeSend >= KSPI_SEND_BYTE_PER_TIMES)
    {
        HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_vld_num, KSPI_SEND_BYTE_PER_TIMES);
        s_usDataSizeToBeSend = s_usDataSizeToBeSend - KSPI_SEND_BYTE_PER_TIMES;
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_vld_num, s_usDataSizeToBeSend);
        /*关闭中断*/
        HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_sw_init_en, 0);
        HV_W32_FIELD(DISP_TOP_KSPI_01_REGISTER_70, reg_kspi_int_en, 0);
        s_usDataSizeToBeSend = 0;
    }
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_set_vld, 0);
    HV_W32_FIELD(DISP_TOP_KSPI_00_REGISTER_04, reg_kspi_00_sbuf_set_vld, 1);
}

VOID Hv_Cal_DpuScaler_GetDpuInt(DpuInterruptDefine* pstDpuInterrupt)
{    
    HV_ASSERT_VALID_PTR_VOID(pstDpuInterrupt);
    HV_R32_DECL_VAR();
    UINT32 uiValue = HV_R32_FIELD(DISP_TOP_DPU_LDG_DPC_FC, regr_ldg_int_with_mask);
    /*ldg_int*/
    pstDpuInterrupt->uiKspiVs           = (uiValue & BIT_0) > 0 ? 1 : 0;
    pstDpuInterrupt->uiKspiTconVsL      = (uiValue & BIT_1) > 0 ? 1 : 0;
    pstDpuInterrupt->uiKspiTconVsH      = (uiValue & BIT_2) > 0 ? 1 : 0;
    pstDpuInterrupt->uiLdgTblGo         = (uiValue & BIT_3) > 0 ? 1 : 0;
    pstDpuInterrupt->uiKspiIntRdma      = (uiValue & BIT_4) > 0 ? 1 : 0;
    pstDpuInterrupt->uiKspiIntWbuf      = (uiValue & BIT_4) > 0 ? 1 : 0;
    /*cap_int*/
    uiValue = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_00_F4, regr_00_cap_int_with_mask);
    pstDpuInterrupt->uiMainVdmTblCaGo   = (uiValue & BIT_0) > 0 ? 1 : 0;
    pstDpuInterrupt->uiMainSpchVendIrq  = (uiValue & BIT_1) > 0 ? 1 : 0;
    uiValue = HV_R32_FIELD(DISP_TOP_DPU_CA_VGSF_01_F4, regr_01_cap_int_with_mask);
    pstDpuInterrupt->uiSubVdmTblCaGo    = (uiValue & BIT_0) > 0 ? 1 : 0;
    pstDpuInterrupt->uiSubSpchVendIrq   = (uiValue & BIT_1) > 0 ? 1 : 0;

    /*srp_int*/
    uiValue = HV_R32_FIELD(DISP_TOP_DPU_SR_DPC_E0, regr_srp_mhi_int_with_mask);
    pstDpuInterrupt->uiSrTblGo          = (uiValue & BIT_0) > 0 ? 1 : 0;
    pstDpuInterrupt->uiSrCtMhiHibEndIrq = (uiValue & BIT_1) > 0 ? 1 : 0;
    pstDpuInterrupt->uiSrCtMhiHiaEndIrq = (uiValue & BIT_2) > 0 ? 1 : 0;
    return;
}

VOID Hv_Cal_DpuScaler_SetDpuInt(UCHAR8 ucEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_28, reg_ldg_int_en, ucEn);
    return;
}


VOID Hv_Cal_DpuScaler_ClearDpuInt()
{
    HV_W32_FIELD(DISP_TOP_KSPI_01_REGISTER_70, reg_kspi_clr_rdma_addr_req, 1);

    HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_28, reg_ldg_int_clr, BIT_0|BIT_1|BIT_2|BIT_3|BIT_4);
    HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_28, reg_ldg_int_clr, 0);

    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_14, reg_srp_mhi_hib_int_clr, BIT_0|BIT_1|BIT_2);
    HV_W32_FIELD(DISP_TOP_DPU_SR_DPC_14, reg_srp_mhi_hib_int_clr, 0);
    return;
}

VOID Hv_Cal_DpuScaler_GetDtcInt(DtcInterruptDefine* pstDtcInterrupt)
{
    HV_ASSERT_VALID_PTR_VOID(pstDtcInterrupt);    
    HV_R32_DECL_VAR();
    UINT32 uiValue = HV_R32_FIELD(DISP_TOP_DTC_TOP_D8, regr_frc_m_abnorm_conflict);
    pstDtcInterrupt->uiMainFrcAbnormConflict = (uiValue & BIT_0) > 0 ? 1 : 0;

    uiValue = HV_R32_FIELD(DISP_TOP_DTC_TOP_D8, regr_frc_s_abnorm_conflict);
    pstDtcInterrupt->uiSubFrcAbnormConflict = (uiValue & BIT_0) > 0 ? 1 : 0;

    uiValue = HV_R32_FIELD(DISP_TOP_DTC_TOP_F8, regr_dtc_buffer_overflow);
    pstDtcInterrupt->uiBufferOverflow = (uiValue & BIT_0) > 0 ? 1 : 0;

    uiValue = HV_R32_FIELD(DISP_TOP_DTC_TOP_F8, regr_dtc_buffer_underflow);
    pstDtcInterrupt->uiBufferUnderflow = (uiValue & BIT_0) > 0 ? 1 : 0;

    uiValue = HV_R32_FIELD(DISP_TOP_DTC_TOP1_EC, regr_dtc_buffer_high_depth);
    pstDtcInterrupt->uiBufferHigh = uiValue;

    uiValue = HV_R32_FIELD(DISP_TOP_DTC_TOP1_EC, regr_dtc_buffer_low_depth);
    pstDtcInterrupt->uiBufferLow = uiValue;
    return ;
}

VOID Hv_Cal_DpuScaler_ClearDtcInt()
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_abnorm_conflict_clr, BIT_0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_abnorm_conflict_clr, 0);

    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_s_abnorm_conflict_clr, BIT_0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_s_abnorm_conflict_clr, 0);

    HV_W32_FIELD(DISP_TOP_DTC_TOP_30, reg_dtc_buffer_overflow_clr, BIT_0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_30, reg_dtc_buffer_overflow_clr, 0);

    HV_W32_FIELD(DISP_TOP_DTC_TOP_30, reg_dtc_buffer_underflow_clr, BIT_0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_30, reg_dtc_buffer_underflow_clr, 0);

    HV_W32_FIELD(DISP_TOP_DTC_TOP1_18, reg_dtc_buffer_high_clr, BIT_0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_18, reg_dtc_buffer_high_clr, 0);

    HV_W32_FIELD(DISP_TOP_DTC_TOP1_18, reg_dtc_buffer_low_clr, BIT_0);
    HV_W32_FIELD(DISP_TOP_DTC_TOP1_18, reg_dtc_buffer_low_clr, 0);

    return;
}

VOID Hv_Cal_DpuScaler_GetHsIpInt(DisplayInterruptType enType, HsIpInterruptDefine* pstHsIpInterrupt)
{
    HV_ASSERT_VALID_PTR_VOID(pstHsIpInterrupt);
    UINT32 uiValue = 0;
    HV_R32_DECL_VAR();
    if (DisplayInterruptType_HsIp0 == enType)
    {
        uiValue = HV_R32_FIELD(RX_HSRX_CH_00_74, regr_00_hsrx_int_pending_hs_24);
    }
    else if  (DisplayInterruptType_HsIp1 == enType)
    {
        uiValue = HV_R32_FIELD(RX_HSRX_CH_01_74, regr_01_hsrx_int_pending_hs_24);
    }
    else
    {
        uiValue = HV_R32_FIELD(SYS_BLK3_TOP_REG_38, regr_int_disp_pending_hs_24);
    }
    pstHsIpInterrupt->uiHsIntSource0  = (uiValue & BIT_0) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource1  = (uiValue & BIT_1) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource2  = (uiValue & BIT_2) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource3  = (uiValue & BIT_3) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource4  = (uiValue & BIT_4) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource5  = (uiValue & BIT_5) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource6  = (uiValue & BIT_6) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource7  = (uiValue & BIT_7) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource8  = (uiValue & BIT_8) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource9  = (uiValue & BIT_9) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource10 = (uiValue & BIT_10) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource11 = (uiValue & BIT_11) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource12 = (uiValue & BIT_12) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource13 = (uiValue & BIT_13) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource14 = (uiValue & BIT_14) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource15 = (uiValue & BIT_15) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource16 = (uiValue & BIT_16) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource17 = (uiValue & BIT_17) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource18 = (uiValue & BIT_18) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource19 = (uiValue & BIT_19) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource20 = (uiValue & BIT_20) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource21 = (uiValue & BIT_21) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource22 = (uiValue & BIT_22) > 0 ? 1 : 0;
    pstHsIpInterrupt->uiHsIntSource23 = (uiValue & BIT_23) > 0 ? 1 : 0;
    return;
}

VOID Hv_Cal_DpuScaler_ClearHsIpInt(DisplayInterruptType enType)
{
    if (DisplayInterruptType_HsIp0 == enType)
    {
        HV_W32_FIELD(RX_HSRX_CH_00_6C, reg_00_hsrx_int_wclr_hs_24, 0xFFFFFF);
        HV_W32_FIELD(RX_HSRX_CH_00_6C, reg_00_hsrx_int_wclr_hs_24, 0);
    }
    else if (DisplayInterruptType_HsIp1 == enType)
    {
        HV_W32_FIELD(RX_HSRX_CH_01_6C, reg_01_hsrx_int_wclr_hs_24, 0xFFFFFF);
        HV_W32_FIELD(RX_HSRX_CH_01_6C, reg_01_hsrx_int_wclr_hs_24, 0);
    }
    else
    {
        HV_W32_FIELD(SYS_BLK3_TOP_REG_30, reg_int_disp_wclr_hs_24, 0xFFFFFF);
        HV_W32_FIELD(SYS_BLK3_TOP_REG_30, reg_int_disp_wclr_hs_24, s_uiLineIntEn);
    }
    return;
}

static UINT32 CalcRefDelayClkTickFromTheory(const VideoConfigParams* pstVideoConfigParams)
{
    UINT32 uiCycleRefclkVtotal = 1592325;
    UINT32 uiRefDelayClkTick = 1043;
    HV_ASSERT_VALID_PTR(pstVideoConfigParams);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_00, reg_00_edptx_pps_0, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_04, reg_00_edptx_pps_1, pstVideoConfigParams->uiInputVideoVtotal);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_08, reg_00_edptx_pps_2, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_0C, reg_00_edptx_pps_3, pstVideoConfigParams->uiInputVideoHight);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_10, reg_00_edptx_pps_4, pstVideoConfigParams->uiInputFrameRate);

    if ((pstVideoConfigParams->uiInputFrameRate > 0) && (pstVideoConfigParams->uiInputVideoVtotal > 0))
    {
        uiCycleRefclkVtotal = HV_CHIP_CLK_APB / pstVideoConfigParams->uiInputFrameRate;
        uiRefDelayClkTick = uiCycleRefclkVtotal / pstVideoConfigParams->uiInputVideoVtotal;
    }
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_18, reg_00_edptx_pps_6, uiRefDelayClkTick);

    return uiRefDelayClkTick;
}

static UINT32 CalcRefDelayClkTickFromReg(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR(pstVideoConfigParams);
    HV_R32_DECL_VAR();
    UINT32 uiMonRxVact = 0;
    UINT32 uiDelay = (1000 / pstVideoConfigParams->uiInputFrameRate) * 1000;
    UINT32 uiMonCyclRefClkVtotal = 1;
    UINT32 uiCheckCount = 0;

    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_00, reg_00_edptx_pps_0, pstVideoConfigParams->uiInputVideoHtotal);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_04, reg_00_edptx_pps_1, pstVideoConfigParams->uiInputVideoVtotal);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_08, reg_00_edptx_pps_2, pstVideoConfigParams->uiInputVideoWidth);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_0C, reg_00_edptx_pps_3, pstVideoConfigParams->uiInputVideoHight);
    HV_W32_FIELD(TX_EDPTX_PPS_REG_00_10, reg_00_edptx_pps_4, pstVideoConfigParams->uiInputFrameRate);

    for(UCHAR8 ucLoop = 0; ucLoop < 20; ucLoop++)
    {
        uiMonCyclRefClkVtotal = HV_R32_FIELD(DISP_TOP_DTC_TOP_BC, regr_mon_cycle_refclk_vtotal);
        uiMonRxVact = HV_R32_FIELD(DISP_TOP_DTC_TOP_C4, regr_mon_rx_vact);
        if((uiMonRxVact != pstVideoConfigParams->uiInputVideoHight) || (0 == uiMonCyclRefClkVtotal))
        {
            HV_LOG_INFO(VIDEO,"DTC mon vact is unstable or RefClkVtotal=0,Vact=%u", uiMonRxVact);
            Hv_Vos_Delayus(uiDelay);
        }
        else
        {
            uiCheckCount++;
            if (uiCheckCount > 10)
            {
                uiCheckCount = 0;
                break;
            }
            else
            {
                Hv_Vos_Delayus(uiDelay);
            }
        }
    }

    UINT32 uiDtcFrameRate = 0;
    for(UCHAR8 ucLoop = 0; ucLoop < 20; ucLoop++)
    {
        uiMonCyclRefClkVtotal = HV_R32_FIELD(DISP_TOP_DTC_TOP_BC, regr_mon_cycle_refclk_vtotal);
        HV_ASSERT_TRUE(uiMonCyclRefClkVtotal > 0);
        uiDtcFrameRate = HV_CHIP_CLK_APB / uiMonCyclRefClkVtotal;
        BOOL bFrameRateDiff = uiDtcFrameRate > pstVideoConfigParams->uiInputFrameRate ? uiDtcFrameRate - pstVideoConfigParams->uiInputFrameRate : pstVideoConfigParams->uiInputFrameRate - uiDtcFrameRate;
        if(bFrameRateDiff > 2)
        {
            HV_LOG_INFO(VIDEO,"DTC frame rate is unstable,FrameRateDiff=%u", bFrameRateDiff);
            Hv_Vos_Delayus(uiDelay);
        }
        else
        {
            break;
        }
    }

    UINT32 uiMonCyclRefClkVblank = HV_R32_FIELD(DISP_TOP_DTC_TOP_B8, regr_mon_cycle_refclk_vblank);
    UINT32 uiMonCyclRefClkHact = HV_R32_FIELD(DISP_TOP_DTC_TOP_B4, regr_mon_cycle_refclk_hact);
    uiMonRxVact = HV_R32_FIELD(DISP_TOP_DTC_TOP_C4, regr_mon_rx_vact);
    /*T*/
    UINT32 uiDelayTick = (uiMonCyclRefClkVtotal - uiMonCyclRefClkVblank - uiMonCyclRefClkHact) / (uiMonRxVact - 1);
    HV_LOG_DEBUG(VIDEO,"DTC Monitor Ref Clock Vtotal=%u,Vblank=%u,uiMonCyclRefClkHact=%u,Vact=%u", uiMonCyclRefClkVtotal,uiMonCyclRefClkVblank,uiMonCyclRefClkHact,uiMonRxVact);
    return uiDelayTick;
}

/*( regr_mon_cycle_refclk_vtotal - regr_mon_cycle_refclk_vblank - regr_mon_cycle_refclk_hact ) / ( regr_mon_rx_vact – 1 )*/
/*  X 4096*3/rx_hact*/
static UINT32 CalcDtcCycleRefClkDelay(const VideoConfigParams* pstVideoConfigParams)
{
    HV_ASSERT_VALID_PTR(pstVideoConfigParams);
    HV_R32_DECL_VAR();
    UINT32 uiDelayTick = CalcRefDelayClkTickFromTheory(pstVideoConfigParams);
    if (pstVideoConfigParams->uiInputVideoHight > 0)
    {
        BOOL  bPictureScalerUpFlag = (pstVideoConfigParams->uiInputVideoWidth < pstVideoConfigParams->uiOutputVideoWidth \
                            || pstVideoConfigParams->uiInputVideoHight < pstVideoConfigParams->uiOutputVideoHight) ? 1 : 0;

        BOOL  bScalerUpIPFlag = 1;//!(pstVideoConfigParams->bYHNeedScaler || pstVideoConfigParams->bYVNeedScaler);
        BOOL  bSharpnessOnFlag = HV_TRUE;
        if ((HV_FALSE == pstVideoConfigParams->bMainFakeSwitch)
            && (PXP_MODE_CLOSE != pstVideoConfigParams->enPxpMode))
        {
            bSharpnessOnFlag = HV_FALSE;
        }
        else
        {
            bSharpnessOnFlag = HV_TRUE;
        }
        BOOL  bColorC02 = HV_FALSE;
        if (ColorFormatType_YCbCr420 == pstVideoConfigParams->stColor.eClrFormat)
        {
            bColorC02 = HV_TRUE;
        }

        /*input line delay*/
        FLOAT32 fColorC02_IntputLineDelay = bColorC02 ? 2 : 0 ;   /*YUC20格式，c02会有2行delay*/
        FLOAT32 fScalerUp_IntputLineDelay = bScalerUpIPFlag ? 4 : 0 ;
        FLOAT32 fDtcIntputLineDelay = bPictureScalerUpFlag ? ((FLOAT32)(4096 * 3) / pstVideoConfigParams->uiInputVideoWidth) : 0;
        fDtcIntputLineDelay = fDtcIntputLineDelay > 10 ? 10 : fDtcIntputLineDelay;
        FLOAT32 fInputLineDelaySum = fColorC02_IntputLineDelay + fScalerUp_IntputLineDelay + fDtcIntputLineDelay;

        /*output line delay*/
        FLOAT32 fScalerUp_OutputLineDelay = bSharpnessOnFlag ? 4 : 0 ;
        FLOAT32 fDtc_OutputLineDelay = bPictureScalerUpFlag ? 0 : ((FLOAT32)(4096 * 3) / pstVideoConfigParams->usVideoPanelHactive);
        FLOAT32 fHsToDe_OutputLineDelay = (FLOAT32)4096 / pstVideoConfigParams->usVideoPanelHactive;
        FLOAT32 fOutputLineDelaySum = (FLOAT32)fScalerUp_OutputLineDelay + fDtc_OutputLineDelay + fHsToDe_OutputLineDelay;

        /*line delay sum*/
        FLOAT32 fLineDelaySum = (FLOAT32)fInputLineDelaySum + (fOutputLineDelaySum * pstVideoConfigParams->uiInputVideoHight / pstVideoConfigParams->usVideoPanelVactive);
        HV_W32_FIELD(TX_EDPTX_PPS_REG_00_14, reg_00_edptx_pps_5, fLineDelaySum);
        /*delay*/
        UINT32 uiCycleRefclkDelay = uiDelayTick * fLineDelaySum;
        USHORT16 usTxVsWidth = HV_R32_FIELD(DISP_TOP_DTC_TOP_20, reg_tx_vs_width);
        USHORT16 usTxVsFront = HV_R32_FIELD(DISP_TOP_DTC_TOP_1C, reg_tx_vs_front);
        UINT32 uiCheckRefclkDelay = uiCycleRefclkDelay + (((usTxVsWidth + usTxVsFront) * pstVideoConfigParams->uiInputVideoHight / pstVideoConfigParams->usVideoPanelVactive) * uiDelayTick);
        // UINT32 uiMonCyclRefClkVblank = HV_R32_FIELD(DISP_TOP_DTC_TOP_B8, regr_mon_cycle_refclk_vblank);
        // if (uiCheckRefclkDelay >= uiMonCyclRefClkVblank)
        // {
        //     HV_LOG_INFO(VIDEO,"##DTC uiCycleRefclkDelay is too large, reduce!");
        //     if (uiCycleRefclkDelay > uiCheckRefclkDelay - uiMonCyclRefClkVblank)
        //     {
        //         uiCycleRefclkDelay -= (uiCheckRefclkDelay - uiMonCyclRefClkVblank);
        //     }
        // }
        return (UINT32)uiCycleRefclkDelay;
    }
    return 2400;
}

VOID Hv_Cal_DpuScaler_DtcClockConfig(VOID)
{
    UINT32 uiDtcFbdivMax = 0;
    UINT32 uiPostDiv = Hv_Cal_PLL_GetPtcdpllPostdiv0();

    HV_W32_FIELD(DISP_TOP_DTC_TOP_04, reg_pll_post_div, uiPostDiv);
    HV_R32_DECL_VAR();
    UINT32 uiFbDiv = HV_R32_FIELD(SYS_SH06_TOP_64, reg_ptcdpll_ssc_plln_int);
    HV_W32_FIELD(DISP_TOP_DTC_TOP_08, reg_pll_fbdiv_int_manual, uiFbDiv);

    /*uiFrac 范围0~0xffff代表0~1,所以小数部分为 (uiFrac / 0xFFFF)*/
    UINT32 uiFrac = HV_R32_FIELD(SYS_SH06_TOP_64, reg_ptcdpll_ssc_plln_frac);
    uiFrac = ((UINT64)uiFrac  * 1024) / 0xFFFF;
    HV_W32_FIELD(DISP_TOP_DTC_TOP_08, reg_pll_fbdiv_frac_manual, uiFrac);

    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_pll_fbdiv_int_min, (UINT32)(uiFbDiv * 70 / 100));
    if((UINT32)(uiFbDiv * 120 / 100) > 111)
    {
        uiDtcFbdivMax = 111;
    }
    else
    {
        uiDtcFbdivMax = (UINT32)(uiFbDiv * 120 / 100);
    }

    HV_W32_FIELD(DISP_TOP_DTC_TOP_84, reg_pll_fbdiv_int_max, uiDtcFbdivMax);
    return;
}

VOID Hv_Cal_DpuScaler_DtcClkDelayConfig(const VideoConfigParams* pstVideoConfigParams, DpuDtcTopTimingParam* pstDpuDtcTopTimingParam)
{
    HV_ASSERT_VALID_PTR_VOID(pstVideoConfigParams);
    if(pstVideoConfigParams->bConfigValid == HV_TRUE)
    {
        HV_R32_DECL_VAR();
        pstDpuDtcTopTimingParam->uiCycleRefclkDelay = CalcDtcCycleRefClkDelay(pstVideoConfigParams);
        HV_W32_FIELD(TX_EDPTX_PPS_REG_00_1C, reg_00_edptx_pps_7, pstDpuDtcTopTimingParam->uiCycleRefclkDelay);
        UINT32 uiMonCyclRefClkVblank = HV_R32_FIELD(DISP_TOP_DTC_TOP_B8, regr_mon_cycle_refclk_vblank);
        HV_W32_FIELD(TX_EDPTX_PPS_REG_00_20, reg_00_edptx_pps_8, uiMonCyclRefClkVblank);
        uiMonCyclRefClkVblank = uiMonCyclRefClkVblank * 0.75f;
        /*使用理论值计算不需要判断，再开启vrr时会有误判*/
        // if ((pstDpuDtcTopTimingParam->uiCycleRefclkDelay > uiMonCyclRefClkVblank) && (0 != uiMonCyclRefClkVblank))
        // {
        //     pstDpuDtcTopTimingParam->uiCycleRefclkDelay = uiMonCyclRefClkVblank;
        // }
        if (pstDpuDtcTopTimingParam->uiCycleRefclkDelay < 1000)
        {
            HV_LOG_INFO(VIDEO,"### DtcRefclkDelay=%u, too small, set default 2400", pstDpuDtcTopTimingParam->uiCycleRefclkDelay);
            pstDpuDtcTopTimingParam->uiCycleRefclkDelay = 2401; /*防止rx不稳定时，导致dtc不稳定，delay算出是1的情况*/
        }
    }
    else
    {
        pstDpuDtcTopTimingParam->uiCycleRefclkDelay = 2402;
    }

    if(pstVideoConfigParams->bInterlacedMode)
    {
        UINT32 uiRange = pstVideoConfigParams->uiInputVideoHtotal * ((HV_CHIP_CLK_APB / 1000) / pstVideoConfigParams->uiRxDpllFreq);
        HV_LOG_DEBUG(VIDEO,"###uiRange=%u", uiRange);
        pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRangeMin = uiRange - 100;
        pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRangeMax = uiRange + 100;
    }
    else
    {
        pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRangeMin = pstVideoConfigParams->usVideoPanelVtotalType - 100;
        pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRangeMax = pstVideoConfigParams->usVideoPanelVtotalType + 100;
    }
    /*建议的寄存器设置是rx_htotal时长的一半*/
    pstDpuDtcTopTimingParam->uiCycleRefclkFramesyncRestartTh = pstVideoConfigParams->uiInputVideoHtotal / 2;
    return;
}

VOID Hv_Cal_DpuScaler_SetIntDispEnHs24(UINT32 uiValue)
{
    HV_W32_FIELD(SYS_BLK3_TOP_REG_34, reg_int_disp_en_hs_24, uiValue);
    return;
}

UINT32 Hv_Cal_DpuScaler_GetFrmsyncState(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DTC_TOP_D0, regr_frmsync_state);
}

UINT32 Hv_Cal_DpuScaler_GetDtcState(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DTC_TOP_FC, regr_dtc_state);
}

UINT32 Hv_Cal_DpuScaler_GetFrcWindex(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DTC_TOP_DC, regr_frc_m_windex);
}

UINT32 Hv_Cal_DpuScaler_GetFrcRindex(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DTC_TOP_DC, regr_frc_m_rindex);
}

UINT32 Hv_Cal_DpuScaler_GetFrcBufStatus(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DTC_TOP_D8, regr_frc_m_buf_status);
}

VOID Hv_Cal_DpuScaler_SetMainFrcIndexStart(BOOL bStart)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_index_start, bStart);
    return;
}

VOID Hv_Cal_DpuScaler_SetMainFrcOverWrite(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_overwrite_en, bEn);
    return;
}

VOID Hv_Cal_DpuScaler_SetLineInt(UCHAR8 ucIndex, USHORT16 usLine)
{
    UCHAR8 ucOffset = 0;
    ucOffset = ucIndex/2;
    UINT32 uiAddr = 0;
    uiAddr = SYS_BLK3_TOP_REG_00 + ucOffset*4;
    UINT32 uiTmp = HV_R32(uiAddr);
    if(ucIndex%2 == 0)
    {
        uiTmp &= 0xFFFF0000;
        uiTmp |= usLine;    
        HV_W32(uiAddr, uiTmp);
    }
    else
    {
        uiTmp &= 0x0000FFFF;
        uiTmp |= usLine<<16;    
        HV_W32(uiAddr, uiTmp);
    }

    return;
}

VOID Hv_Cal_DpuScaler_SetLineIntEn(UINT32 uiEn)
{
    HV_W32_FIELD(SYS_BLK3_TOP_REG_34, reg_int_disp_en_hs_24, uiEn);
    s_uiLineIntEn = ~uiEn;
    HV_W32_FIELD(SYS_BLK3_TOP_REG_30, reg_int_disp_wclr_hs_24, s_uiLineIntEn);
    
    return;
}

USHORT16 Hv_Cal_DpuScaler_GetDtcVtotal(VOID)
{
    HV_R32_DECL_VAR();
    return HV_R32_FIELD(DISP_TOP_DTC_TOP_D4, regr_tx_vtotal);
}

VOID Hv_Cal_DpuScaler_SetLdgLatch(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_SUB_LDG_00, reg_en_no_latch, bEn);
    return;
}

/*调试工具*/
VOID Hv_Cal_DpuScaler_SetMainChannelState(USHORT16 usState)
{
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_0, reg_pif_tg_1_packet_dh_den_sta, usState);
    return;
}

VOID Hv_Cal_DpuScaler_SetSubChannelState(USHORT16 usState)
{
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_GRP_1_REG_0, reg_pif_tg_1_packet_dh_den_end, usState);
    return;
}

VOID Hv_Cal_DpuScaler_SetMianFrcIndexFwMode(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_index_fw_mode, bEn);
    return;
}

static BOOL bSeamlessSwitchFlag = 0;
VOID Hv_Cal_DpuScaler_SetSeamlessSwitchFlag(BOOL bEn)
{
    bSeamlessSwitchFlag = bEn;
    return;
}

VOID Hv_Cal_DpuScaler_ToggleMainFrcReadIndex(VOID)
{
    if (1 == bSeamlessSwitchFlag)  //保证如果来了多次遮黑中断，只处理一次
    {
        Hv_Cal_DpuScaler_SetMianFrcIndexFwMode(1);
        bSeamlessSwitchFlag = 0;
        HV_R32_DECL_VAR();
        UCHAR8 ucIndex = HV_R32_FIELD(DISP_TOP_DTC_TOP_DC, regr_frc_m_windex);
        //HV_LOG_INFO(VIDEO,"##%u", ucIndex);
        if (0 == ucIndex)
        {
            ucIndex = 1;
        }
        else
        {
            ucIndex = 0;
        }
        HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_r_index_fw_value, ucIndex);
        //HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_init_r_index, ucIndex);
    }

    return;
}

#if (HV_CONFIG_ON == HV_PROJECT_CONFIG_DPU_BRIGHT_FRAME)
VOID Hv_Cal_DpuScaler_MainFrcLowLatencyMode(BOOL bEn, UINT32 uiVact)
{
    if (1 == bEn)
    {
        HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_buf_num, 1);
        Hv_Cal_DpuScaler_SetMainFrcIndexStart(0);
        HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_init_r_index, 0);
        HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_init_w_index, 0);
        HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_overwrite_en, 1);
        HV_W32_FIELD(DISP_TOP_DTC_TOP_98, reg_frc_m_rd_done_th, uiVact);
        HV_W32_FIELD(DISP_TOP_DTC_TOP_98, reg_frc_m_wr_done_th, uiVact);
        HV_W32_FIELD(DISP_TOP_DTC_TOP_24, reg_cycle_refclk_delay, 2300); //可能需要根据实际timing调试,QHD 1500; UHD 2300
        //Hv_Cal_DpuScaler_DtcDynamicPllEn(0);
        //Hv_Cal_DpuScaler_DtcTimingSel(3);
        //Hv_Cal_DpuScaler_DtcDynamicPllEn(1);  /*在channel config check中切换*/
        Hv_Vos_Delayus(20000);
        Hv_Cal_DpuScaler_SetMainFrcIndexStart(1);
    }
    else
    {
        HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_init_w_index, 1);
        HV_W32_FIELD(DISP_TOP_DTC_TOP_94, reg_frc_m_overwrite_en, 0);
    }
    return;
}

static BOOL s_bBFLowLatency = HV_FALSE;   /*BF下timing分两种，一种可以走frame进入low lactency，另外是只能通过frc实现*/
BOOL Hv_Cal_DpuScaler_GetBrightFrameLowLatency(VOID)
{
    return s_bBFLowLatency;
}

VOID Hv_Cal_DpuScaler_SetBrightFrameLowLatency(BOOL bEn)
{
    s_bBFLowLatency = bEn;
}
#endif






    
