#ifndef _HV_PAGE_HT7315_EDP_RX_DPCD_0_REG_00_H_
#define _HV_PAGE_HT7315_EDP_RX_DPCD_0_REG_00_H_

#ifndef HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS
    #define HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS                                         0x11048000
#endif


#define RX_EDP_RX_DPCD_0_REG_00_00                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_DPCD_0_REG_00_00_struct                                rs_rx_edp_rx_dpcd_0_reg_00_00

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_00  rs_rx_edp_rx_dpcd_0_reg_00_00;
struct _rs_rx_edp_rx_dpcd_0_reg_00_00 {
    unsigned int reg_00_dprx_dpcd_dpcd_rev                  : 8;
    unsigned int reg_00_dprx_dpcd_max_link_rate             : 8;
    unsigned int reg_00_dprx_dpcd_max_lane_count            : 5;
    unsigned int reg_00_dprx_dpcd_post_lt_adj_req_supported : 1;
    unsigned int reg_00_dprx_dpcd_tps3_supported            : 1;
    unsigned int reg_00_dprx_dpcd_enhanced_frame_cap        : 1;
    unsigned int reg_00_dprx_dpcd_max_downspread            : 1;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_no_aux_transaction_link_training: 1;
    unsigned int reg_00_dprx_dpcd_tps4_supported            : 1;
};
#define rx_edp_rx_dpcd_0_reg_00_00(val) ((rs_rx_edp_rx_dpcd_0_reg_00_00*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_04                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_DPCD_0_REG_00_04_struct                                rs_rx_edp_rx_dpcd_0_reg_00_04

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_04  rs_rx_edp_rx_dpcd_0_reg_00_04;
struct _rs_rx_edp_rx_dpcd_0_reg_00_04 {
    unsigned int reg_00_dprx_dpcd_norp                      : 1;
    unsigned int reserved                                   : 4;
    unsigned int reg_00_dprx_dpcd_5v_dp_pwr_cap             : 1;
    unsigned int reg_00_dprx_dpcd_12v_dp_pwr_cap            : 1;
    unsigned int reg_00_dprx_dpcd_18v_dp_pwr_cap            : 1;
    unsigned int reg_00_dprx_dpcd_dfp_present               : 1;
    unsigned int reg_00_dprx_dpcd_dfp_type                  : 2;
    unsigned int reg_00_dprx_dpcd_format_conversion         : 1;
    unsigned int reg_00_dprx_dpcd_detailed_cap_info_available: 1;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_dprx_dpcd_ansi_8b10b                : 1;
    unsigned int reserved_2                                 : 7;
    unsigned int reg_00_dprx_dpcd_dfp_count                 : 4;
    unsigned int reserved_3                                 : 2;
    unsigned int reg_00_dprx_dpcd_msa_timing_par_ignored    : 1;
    unsigned int reg_00_dprx_dpcd_oui_support               : 1;
};
#define rx_edp_rx_dpcd_0_reg_00_04(val) ((rs_rx_edp_rx_dpcd_0_reg_00_04*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_08                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_DPCD_0_REG_00_08_struct                                rs_rx_edp_rx_dpcd_0_reg_00_08

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_08  rs_rx_edp_rx_dpcd_0_reg_00_08;
struct _rs_rx_edp_rx_dpcd_0_reg_00_08 {
    unsigned int reg_00_dprx_dpcd_reserved_0x08             : 1;
    unsigned int reg_00_dprx_dpcd_receive_port0_local_edid_present: 1;
    unsigned int reg_00_dprx_dpcd_receive_port0_associated_to_preceding_port: 1;
    unsigned int reg_00_dprx_dpcd_receive_port0_hblank_expansion_capable: 1;
    unsigned int reg_00_dprx_dpcd_receive_port0_buffer_size_unit: 1;
    unsigned int reg_00_dprx_dpcd_receive_port0_buffer_size_per_port: 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_dprx_dpcd_receive_port0_buffer_size : 8;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_00_dprx_dpcd_receive_port1_local_edid_present: 1;
    unsigned int reg_00_dprx_dpcd_receive_port1_associated_to_preceding_port: 1;
    unsigned int reg_00_dprx_dpcd_receive_port1_hblank_expansion_capable: 1;
    unsigned int reg_00_dprx_dpcd_receive_port1_buffer_size_unit: 1;
    unsigned int reg_00_dprx_dpcd_receive_port1_buffer_size_per_port: 1;
    unsigned int reserved_2                                 : 2;
    unsigned int reg_00_dprx_dpcd_receive_port1_buffer_size : 8;
};
#define rx_edp_rx_dpcd_0_reg_00_08(val) ((rs_rx_edp_rx_dpcd_0_reg_00_08*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_0C                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x0C)

#define RX_EDP_RX_DPCD_0_REG_00_0C_struct                                rs_rx_edp_rx_dpcd_0_reg_00_0c

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_0c  rs_rx_edp_rx_dpcd_0_reg_00_0c;
struct _rs_rx_edp_rx_dpcd_0_reg_00_0c {
    unsigned int reg_00_dprx_dpcd_i2c_speed_control_capabilites: 8;
    unsigned int reg_00_dprx_dpcd_alternate_scrambler_reset_capable: 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dpcd_display_control_capable   : 1;
    unsigned int reserved_1                                 : 5;
    unsigned int reg_00_dprx_dpcd_training_aux_rd_interval  : 7;
    unsigned int reg_00_dprx_dpcd_ext_receiver_cap_field_resent: 1;
    unsigned int reg_00_dprx_dpcd_force_load_sense_cap      : 1;
    unsigned int reg_00_dprx_dpcd_alternate_i2c_pattern_cap : 1;
    unsigned int reserved_2                                 : 6;
};
#define rx_edp_rx_dpcd_0_reg_00_0c(val) ((rs_rx_edp_rx_dpcd_0_reg_00_0c*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_10                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x10)

#define RX_EDP_RX_DPCD_0_REG_00_10_struct                                rs_rx_edp_rx_dpcd_0_reg_00_10

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_10  rs_rx_edp_rx_dpcd_0_reg_00_10;
struct _rs_rx_edp_rx_dpcd_0_reg_00_10 {
    unsigned int reg_00_dprx_dpcd_supported_link_rates0     :16;
    unsigned int reg_00_dprx_dpcd_supported_link_rates1     :16;
};
#define rx_edp_rx_dpcd_0_reg_00_10(val) ((rs_rx_edp_rx_dpcd_0_reg_00_10*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_14                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x14)

#define RX_EDP_RX_DPCD_0_REG_00_14_struct                                rs_rx_edp_rx_dpcd_0_reg_00_14

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_14  rs_rx_edp_rx_dpcd_0_reg_00_14;
struct _rs_rx_edp_rx_dpcd_0_reg_00_14 {
    unsigned int reg_00_dprx_dpcd_supported_link_rates2     :16;
    unsigned int reg_00_dprx_dpcd_supported_link_rates3     :16;
};
#define rx_edp_rx_dpcd_0_reg_00_14(val) ((rs_rx_edp_rx_dpcd_0_reg_00_14*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_18                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x18)

#define RX_EDP_RX_DPCD_0_REG_00_18_struct                                rs_rx_edp_rx_dpcd_0_reg_00_18

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_18  rs_rx_edp_rx_dpcd_0_reg_00_18;
struct _rs_rx_edp_rx_dpcd_0_reg_00_18 {
    unsigned int reg_00_dprx_dpcd_supported_link_rates4     :16;
    unsigned int reg_00_dprx_dpcd_supported_link_rates5     :16;
};
#define rx_edp_rx_dpcd_0_reg_00_18(val) ((rs_rx_edp_rx_dpcd_0_reg_00_18*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_1C                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x1C)

#define RX_EDP_RX_DPCD_0_REG_00_1C_struct                                rs_rx_edp_rx_dpcd_0_reg_00_1c

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_1c  rs_rx_edp_rx_dpcd_0_reg_00_1c;
struct _rs_rx_edp_rx_dpcd_0_reg_00_1c {
    unsigned int reg_00_dprx_dpcd_supported_link_rates6     :16;
    unsigned int reg_00_dprx_dpcd_supported_link_rates7     :16;
};
#define rx_edp_rx_dpcd_0_reg_00_1c(val) ((rs_rx_edp_rx_dpcd_0_reg_00_1c*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_20                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_DPCD_0_REG_00_20_struct                                rs_rx_edp_rx_dpcd_0_reg_00_20

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_20  rs_rx_edp_rx_dpcd_0_reg_00_20;
struct _rs_rx_edp_rx_dpcd_0_reg_00_20 {
    unsigned int reg_00_dprx_dpcd_reserved_0x20             : 8;
    unsigned int reg_00_dprx_dpcd_mst_cap                   : 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_dpcd_number_of_audio_endpoints : 8;
    unsigned int reg_00_dprx_dpcd_av_sync_ag_factor         : 4;
    unsigned int reg_00_dprx_dpcd_av_sync_vg_factor         : 4;
};
#define rx_edp_rx_dpcd_0_reg_00_20(val) ((rs_rx_edp_rx_dpcd_0_reg_00_20*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_24                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_DPCD_0_REG_00_24_struct                                rs_rx_edp_rx_dpcd_0_reg_00_24

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_24  rs_rx_edp_rx_dpcd_0_reg_00_24;
struct _rs_rx_edp_rx_dpcd_0_reg_00_24 {
    unsigned int reg_00_dprx_dpcd_av_sync_aud_lat           :16;
    unsigned int reg_00_dprx_dpcd_av_sync_pp_lat            :16;
};
#define rx_edp_rx_dpcd_0_reg_00_24(val) ((rs_rx_edp_rx_dpcd_0_reg_00_24*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_28                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_DPCD_0_REG_00_28_struct                                rs_rx_edp_rx_dpcd_0_reg_00_28

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_28  rs_rx_edp_rx_dpcd_0_reg_00_28;
struct _rs_rx_edp_rx_dpcd_0_reg_00_28 {
    unsigned int reg_00_dprx_dpcd_av_sync_inter_lat         : 8;
    unsigned int reg_00_dprx_dpcd_av_sync_vid_prog_lat      : 8;
    unsigned int reg_00_dprx_dpcd_av_sync_rep_lat           : 8;
    unsigned int reg_00_dprx_dpcd_av_sync_aud_del_ins0      : 8;
};
#define rx_edp_rx_dpcd_0_reg_00_28(val) ((rs_rx_edp_rx_dpcd_0_reg_00_28*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_2C                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x2C)

#define RX_EDP_RX_DPCD_0_REG_00_2C_struct                                rs_rx_edp_rx_dpcd_0_reg_00_2c

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_2c  rs_rx_edp_rx_dpcd_0_reg_00_2c;
struct _rs_rx_edp_rx_dpcd_0_reg_00_2c {
    unsigned int reg_00_dprx_dpcd_av_sync_aud_del_ins1      :16;
    unsigned int reg_00_dprx_dpcd_alpm_alpm_cap             : 1;
    unsigned int reg_00_dprx_dpcd_alpm_pm_state_2a_support  : 1;
    unsigned int reg_00_dprx_dpcd_alpm_aux_less_alpm_cap    : 1;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_aux_frame_sync_cap        : 1;
    unsigned int reserved_1                                 : 7;
};
#define rx_edp_rx_dpcd_0_reg_00_2c(val) ((rs_rx_edp_rx_dpcd_0_reg_00_2c*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_30                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x30)

#define RX_EDP_RX_DPCD_0_REG_00_30_struct                                rs_rx_edp_rx_dpcd_0_reg_00_30

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_30  rs_rx_edp_rx_dpcd_0_reg_00_30;
struct _rs_rx_edp_rx_dpcd_0_reg_00_30 {
    unsigned int reg_00_dprx_dpcd_guid0                     :32;
};
#define rx_edp_rx_dpcd_0_reg_00_30(val) ((rs_rx_edp_rx_dpcd_0_reg_00_30*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_34                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x34)

#define RX_EDP_RX_DPCD_0_REG_00_34_struct                                rs_rx_edp_rx_dpcd_0_reg_00_34

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_34  rs_rx_edp_rx_dpcd_0_reg_00_34;
struct _rs_rx_edp_rx_dpcd_0_reg_00_34 {
    unsigned int reg_00_dprx_dpcd_guid1                     :32;
};
#define rx_edp_rx_dpcd_0_reg_00_34(val) ((rs_rx_edp_rx_dpcd_0_reg_00_34*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_38                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x38)

#define RX_EDP_RX_DPCD_0_REG_00_38_struct                                rs_rx_edp_rx_dpcd_0_reg_00_38

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_38  rs_rx_edp_rx_dpcd_0_reg_00_38;
struct _rs_rx_edp_rx_dpcd_0_reg_00_38 {
    unsigned int reg_00_dprx_dpcd_guid2                     :32;
};
#define rx_edp_rx_dpcd_0_reg_00_38(val) ((rs_rx_edp_rx_dpcd_0_reg_00_38*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_3C                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x3C)

#define RX_EDP_RX_DPCD_0_REG_00_3C_struct                                rs_rx_edp_rx_dpcd_0_reg_00_3c

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_3c  rs_rx_edp_rx_dpcd_0_reg_00_3c;
struct _rs_rx_edp_rx_dpcd_0_reg_00_3c {
    unsigned int reg_00_dprx_dpcd_guid3                     :32;
};
#define rx_edp_rx_dpcd_0_reg_00_3c(val) ((rs_rx_edp_rx_dpcd_0_reg_00_3c*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_54                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x54)

#define RX_EDP_RX_DPCD_0_REG_00_54_struct                                rs_rx_edp_rx_dpcd_0_reg_00_54

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_54  rs_rx_edp_rx_dpcd_0_reg_00_54;
struct _rs_rx_edp_rx_dpcd_0_reg_00_54 {
    unsigned int regr_00_dprx_dpcd_rx_gtc_value             :32;
};
#define rx_edp_rx_dpcd_0_reg_00_54(val) ((rs_rx_edp_rx_dpcd_0_reg_00_54*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_58                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x58)

#define RX_EDP_RX_DPCD_0_REG_00_58_struct                                rs_rx_edp_rx_dpcd_0_reg_00_58

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_58  rs_rx_edp_rx_dpcd_0_reg_00_58;
struct _rs_rx_edp_rx_dpcd_0_reg_00_58 {
    unsigned int reg_00_dprx_dpcd_rx_gtc_mstr_req           : 1;
    unsigned int reg_00_dprx_dpcd_tx_gtc_value_phase_skew_en: 1;
    unsigned int reserved                                   : 6;
    unsigned int regr_00_dprx_dpcd_rx_gtc_freq_lock_done    : 1;
    unsigned int reserved_1                                 : 7;
    unsigned int reg_00_dprx_dpcd_rx_gtc_phase_skew_offset  :16;
};
#define rx_edp_rx_dpcd_0_reg_00_58(val) ((rs_rx_edp_rx_dpcd_0_reg_00_58*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_60                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_DPCD_0_REG_00_60_struct                                rs_rx_edp_rx_dpcd_0_reg_00_60

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_60  rs_rx_edp_rx_dpcd_0_reg_00_60;
struct _rs_rx_edp_rx_dpcd_0_reg_00_60 {
    unsigned int reg_00_dprx_dpcd_dsc_support               : 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_dpcd_dsc_version               : 8;
    unsigned int reg_00_dprx_dpcd_dsc_rx_buffer_block_size  : 2;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_00_dprx_dpcd_dsc_each_rate_buffer_size_in_units: 8;
};
#define rx_edp_rx_dpcd_0_reg_00_60(val) ((rs_rx_edp_rx_dpcd_0_reg_00_60*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_64                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x64)

#define RX_EDP_RX_DPCD_0_REG_00_64_struct                                rs_rx_edp_rx_dpcd_0_reg_00_64

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_64  rs_rx_edp_rx_dpcd_0_reg_00_64;
struct _rs_rx_edp_rx_dpcd_0_reg_00_64 {
    unsigned int reg_00_dprx_dpcd_dsc_1_slice_per_line      : 1;
    unsigned int reg_00_dprx_dpcd_dsc_2_slice_per_line      : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dpcd_dsc_4_slice_per_line      : 1;
    unsigned int reg_00_dprx_dpcd_dsc_6_slice_per_line      : 1;
    unsigned int reg_00_dprx_dpcd_dsc_8_slice_per_line      : 1;
    unsigned int reg_00_dprx_dpcd_dsc_10_slice_per_line     : 1;
    unsigned int reg_00_dprx_dpcd_dsc_12_slice_per_line     : 1;
    unsigned int reg_00_dprx_dpcd_dsc_line_buffer_bit_depth : 3;
    unsigned int reserved_1                                 : 5;
    unsigned int reg_00_dprx_dpcd_dsc_block_prediction_support: 1;
    unsigned int reserved_2                                 : 7;
    unsigned int reg_00_dprx_dpcd_dsc_max_bps_supported0    : 8;
};
#define rx_edp_rx_dpcd_0_reg_00_64(val) ((rs_rx_edp_rx_dpcd_0_reg_00_64*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_68                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x68)

#define RX_EDP_RX_DPCD_0_REG_00_68_struct                                rs_rx_edp_rx_dpcd_0_reg_00_68

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_68  rs_rx_edp_rx_dpcd_0_reg_00_68;
struct _rs_rx_edp_rx_dpcd_0_reg_00_68 {
    unsigned int reg_00_dprx_dpcd_dsc_max_bps_supported1    : 2;
    unsigned int reserved                                   : 6;
    unsigned int reg_00_dprx_dpcd_dsc_rgb_support           : 1;
    unsigned int reg_00_dprx_dpcd_dsc_yuv444_support        : 1;
    unsigned int reg_00_dprx_dpcd_dsc_yuv422_support        : 1;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_00_dprx_dpcd_dsc_8bits_support         : 1;
    unsigned int reg_00_dprx_dpcd_dsc_10bits_support        : 1;
    unsigned int reg_00_dprx_dpcd_dsc_12bits_support        : 1;
    unsigned int reserved_2                                 : 1;
    unsigned int reg_00_dprx_dpcd_dsc_16bits_support        : 1;
    unsigned int reserved_3                                 : 2;
    unsigned int reg_00_dprx_dpcd_dsc_throughput_mode_0     : 4;
    unsigned int reg_00_dprx_dpcd_dsc_throughput_mode_1     : 4;
};
#define rx_edp_rx_dpcd_0_reg_00_68(val) ((rs_rx_edp_rx_dpcd_0_reg_00_68*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_6C                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x6C)

#define RX_EDP_RX_DPCD_0_REG_00_6C_struct                                rs_rx_edp_rx_dpcd_0_reg_00_6c

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_6c  rs_rx_edp_rx_dpcd_0_reg_00_6c;
struct _rs_rx_edp_rx_dpcd_0_reg_00_6c {
    unsigned int reg_00_dprx_dpcd_dsc_max_slice_width       : 8;
    unsigned int reg_00_dprx_dpcd_dsc_16_slice_per_line     : 1;
    unsigned int reg_00_dprx_dpcd_dsc_20_slice_per_line     : 1;
    unsigned int reg_00_dprx_dpcd_dsc_24_slice_per_line     : 1;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_dsc_min_bps_supported     :10;
    unsigned int reserved_1                                 : 2;
    unsigned int reg_00_dprx_dpcd_dsc_incr_bps_supported    : 3;
    unsigned int reserved_2                                 : 1;
};
#define rx_edp_rx_dpcd_0_reg_00_6c(val) ((rs_rx_edp_rx_dpcd_0_reg_00_6c*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_70                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x70)

#define RX_EDP_RX_DPCD_0_REG_00_70_struct                                rs_rx_edp_rx_dpcd_0_reg_00_70

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_70  rs_rx_edp_rx_dpcd_0_reg_00_70;
struct _rs_rx_edp_rx_dpcd_0_reg_00_70 {
    unsigned int reg_00_dprx_dpcd_psr_support_and_version   : 8;
    unsigned int reg_00_dprx_dpcd_link_training_req_of_sink_on_psr_exit_when_main_link_off: 1;
    unsigned int reg_00_dprx_dpcd_psr_setup_time            : 3;
    unsigned int reg_00_dprx_dpcd_y_coordinate_req_of_sink_on_psr2_select_update: 1;
    unsigned int reg_00_dprx_dpcd_panel_self_refresh_2_selective_update_granularity_required: 1;
    unsigned int reg_00_dprx_dpcd_frame_sync_function_is_not_needed_for_selective_update: 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dpcd_su_x_granularity          :16;
};
#define rx_edp_rx_dpcd_0_reg_00_70(val) ((rs_rx_edp_rx_dpcd_0_reg_00_70*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_74                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x74)

#define RX_EDP_RX_DPCD_0_REG_00_74_struct                                rs_rx_edp_rx_dpcd_0_reg_00_74

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_74  rs_rx_edp_rx_dpcd_0_reg_00_74;
struct _rs_rx_edp_rx_dpcd_0_reg_00_74 {
    unsigned int reg_00_dprx_dpcd_su_y_granularity          : 8;
    unsigned int reserved                                   :24;
};
#define rx_edp_rx_dpcd_0_reg_00_74(val) ((rs_rx_edp_rx_dpcd_0_reg_00_74*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_80                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x80)

#define RX_EDP_RX_DPCD_0_REG_00_80_struct                                rs_rx_edp_rx_dpcd_0_reg_00_80

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_80  rs_rx_edp_rx_dpcd_0_reg_00_80;
struct _rs_rx_edp_rx_dpcd_0_reg_00_80 {
    unsigned int reg_00_dprx_dpcd_dfp0_type                 : 3;
    unsigned int reg_00_dprx_dpcd_dfp0_hpd                  : 1;
    unsigned int reg_00_dprx_dpcd_non_edid_dfp0_attribute   : 4;
    unsigned int reg_00_dprx_dpcd_dfp0_byte1                : 8;
    unsigned int reg_00_dprx_dpcd_dfp0_byte2                : 8;
    unsigned int reg_00_dprx_dpcd_dfp0_byte3                : 8;
};
#define rx_edp_rx_dpcd_0_reg_00_80(val) ((rs_rx_edp_rx_dpcd_0_reg_00_80*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_84                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x84)

#define RX_EDP_RX_DPCD_0_REG_00_84_struct                                rs_rx_edp_rx_dpcd_0_reg_00_84

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_84  rs_rx_edp_rx_dpcd_0_reg_00_84;
struct _rs_rx_edp_rx_dpcd_0_reg_00_84 {
    unsigned int reg_00_dprx_dpcd_dfp1_type                 : 3;
    unsigned int reg_00_dprx_dpcd_dfp1_hpd                  : 1;
    unsigned int reg_00_dprx_dpcd_non_edid_dfp1_attribute   : 4;
    unsigned int reg_00_dprx_dpcd_dfp1_byte1                : 8;
    unsigned int reg_00_dprx_dpcd_dfp1_byte2                : 8;
    unsigned int reg_00_dprx_dpcd_dfp1_byte3                : 8;
};
#define rx_edp_rx_dpcd_0_reg_00_84(val) ((rs_rx_edp_rx_dpcd_0_reg_00_84*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_88                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x88)

#define RX_EDP_RX_DPCD_0_REG_00_88_struct                                rs_rx_edp_rx_dpcd_0_reg_00_88

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_88  rs_rx_edp_rx_dpcd_0_reg_00_88;
struct _rs_rx_edp_rx_dpcd_0_reg_00_88 {
    unsigned int reg_00_dprx_dpcd_dfp2_type                 : 3;
    unsigned int reg_00_dprx_dpcd_dfp2_hpd                  : 1;
    unsigned int reg_00_dprx_dpcd_non_edid_dfp2_attribute   : 4;
    unsigned int reg_00_dprx_dpcd_dfp2_byte1                : 8;
    unsigned int reg_00_dprx_dpcd_dfp2_byte2                : 8;
    unsigned int reg_00_dprx_dpcd_dfp2_byte3                : 8;
};
#define rx_edp_rx_dpcd_0_reg_00_88(val) ((rs_rx_edp_rx_dpcd_0_reg_00_88*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_8C                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x8C)

#define RX_EDP_RX_DPCD_0_REG_00_8C_struct                                rs_rx_edp_rx_dpcd_0_reg_00_8c

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_8c  rs_rx_edp_rx_dpcd_0_reg_00_8c;
struct _rs_rx_edp_rx_dpcd_0_reg_00_8c {
    unsigned int reg_00_dprx_dpcd_dfp3_type                 : 3;
    unsigned int reg_00_dprx_dpcd_dfp3_hpd                  : 1;
    unsigned int reg_00_dprx_dpcd_non_edid_dfp3_attribute   : 4;
    unsigned int reg_00_dprx_dpcd_dfp3_byte1                : 8;
    unsigned int reg_00_dprx_dpcd_dfp3_byte2                : 8;
    unsigned int reg_00_dprx_dpcd_dfp3_byte3                : 8;
};
#define rx_edp_rx_dpcd_0_reg_00_8c(val) ((rs_rx_edp_rx_dpcd_0_reg_00_8c*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_90                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0x90)

#define RX_EDP_RX_DPCD_0_REG_00_90_struct                                rs_rx_edp_rx_dpcd_0_reg_00_90

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_90  rs_rx_edp_rx_dpcd_0_reg_00_90;
struct _rs_rx_edp_rx_dpcd_0_reg_00_90 {
    unsigned int reg_00_dprx_dpcd_fec_capable               : 1;
    unsigned int reg_00_dprx_dpcd_fec_uncorrected_block_error_count_capable: 1;
    unsigned int reg_00_dprx_dpcd_fec_corrected_block_error_count_capable: 1;
    unsigned int reg_00_dprx_dpcd_fec_bit_error_count_capable: 1;
    unsigned int reg_00_dprx_dpcd_fec_parity_block_error_count_capable: 1;
    unsigned int reg_00_dprx_dpcd_fec_parity_error_count_capable: 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dpcd_fec_error_reporting_policy_supported: 1;
    unsigned int reserved_1                                 :24;
};
#define rx_edp_rx_dpcd_0_reg_00_90(val) ((rs_rx_edp_rx_dpcd_0_reg_00_90*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_A0                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xA0)

#define RX_EDP_RX_DPCD_0_REG_00_A0_struct                                rs_rx_edp_rx_dpcd_0_reg_00_a0

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_a0  rs_rx_edp_rx_dpcd_0_reg_00_a0;
struct _rs_rx_edp_rx_dpcd_0_reg_00_a0 {
    unsigned int reg_00_dprx_dpcd_reserved_0x00             :16;
    unsigned int reg_00_dprx_dpcd_mst_sink_count            : 6;
    unsigned int reg_00_dprx_dpcd_mst_cp_ready              : 1;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_dprx_dpcd_mst_remote_control_command_pending: 1;
    unsigned int regr_00_dprx_dpcd_mst_touch_interrupt      : 1;
    unsigned int regr_00_dprx_dpcd_mst_cp_irq               : 1;
    unsigned int regr_00_dprx_dpcd_mst_mccs_irq             : 1;
    unsigned int regr_00_dprx_dpcd_mst_down_rep_msg_rdy     : 1;
    unsigned int regr_00_dprx_dpcd_mst_up_req_msg_rdy       : 1;
    unsigned int regr_00_dprx_dpcd_mst_sink_specific_irq    : 1;
    unsigned int reserved_1                                 : 1;
};
#define rx_edp_rx_dpcd_0_reg_00_a0(val) ((rs_rx_edp_rx_dpcd_0_reg_00_a0*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_A4                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xA4)

#define RX_EDP_RX_DPCD_0_REG_00_A4_struct                                rs_rx_edp_rx_dpcd_0_reg_00_a4

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_a4  rs_rx_edp_rx_dpcd_0_reg_00_a4;
struct _rs_rx_edp_rx_dpcd_0_reg_00_a4 {
    unsigned int reg_00_dprx_dpcd_mst_rx_gtc_mstr_req_status_change: 1;
    unsigned int reg_00_dprx_dpcd_mst_lock_acquisition_request: 1;
    unsigned int reg_00_dprx_dpcd_mst_cec_irq               : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_dprx_dpcd_mst_dsc_error_status      : 1;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_dprx_dpcd_mst_px_cap_changed        : 1;
    unsigned int reg_00_dprx_dpcd_mst_link_status_changed   : 1;
    unsigned int reg_00_dprx_dpcd_mst_stream_status_changed : 1;
    unsigned int reg_00_dprx_dpcd_mst_hdmi_link_status_changed: 1;
    unsigned int reg_00_dprx_dpcd_mst_connected_off_entry_requested: 1;
    unsigned int reserved_2                                 : 3;
    unsigned int regr_00_dprx_dpcd_psr2_link_crc_error      : 1;
    unsigned int regr_00_dprx_dpcd_rfb_storage_error        : 1;
    unsigned int regr_00_dprx_dpcd_vsc_sdp_uncorrectable_error: 1;
    unsigned int reserved_3                                 : 5;
    unsigned int regr_00_dprx_dpcd_sink_device_psr_capability_change: 1;
    unsigned int reserved_4                                 : 7;
};
#define rx_edp_rx_dpcd_0_reg_00_a4(val) ((rs_rx_edp_rx_dpcd_0_reg_00_a4*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_A8                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xA8)

#define RX_EDP_RX_DPCD_0_REG_00_A8_struct                                rs_rx_edp_rx_dpcd_0_reg_00_a8

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_a8  rs_rx_edp_rx_dpcd_0_reg_00_a8;
struct _rs_rx_edp_rx_dpcd_0_reg_00_a8 {
    unsigned int regr_00_dprx_dpcd_sink_device_psr_status   : 3;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_psr_max_resync_frame_count: 4;
    unsigned int reg_00_dprx_dpcd_last_actual_sync_latency_in_sink: 4;
    unsigned int regr_00_dprx_dpcd_psr_state                : 1;
    unsigned int regr_00_dprx_dpcd_psr_upate_rfb            : 1;
    unsigned int regr_00_dprx_dpcd_psr_crc_valid            : 1;
    unsigned int regr_00_dprx_dpcd_psr_su_valid             : 1;
    unsigned int regr_00_dprx_dpcd_psr_first_scan_line_of_the_su_region: 1;
    unsigned int regr_00_dprx_dpcd_psr_last_scan_line_of_the_su_region: 1;
    unsigned int regr_00_dprx_dpcd_psr_y_coordinate_valid   : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int regr_00_dprx_dpcd_alpm_lock_timeout_error_status: 1;
    unsigned int regr_00_dprx_dpcd_arp_screen_refresh_irq   : 1;
    unsigned int regr_00_dprx_dpcd_alpm_aux_less_alpm_lock_timeout_error_status: 1;
    unsigned int reserved_2                                 : 5;
};
#define rx_edp_rx_dpcd_0_reg_00_a8(val) ((rs_rx_edp_rx_dpcd_0_reg_00_a8*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_AC                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xAC)

#define RX_EDP_RX_DPCD_0_REG_00_AC_struct                                rs_rx_edp_rx_dpcd_0_reg_00_ac

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_ac  rs_rx_edp_rx_dpcd_0_reg_00_ac;
struct _rs_rx_edp_rx_dpcd_0_reg_00_ac {
    unsigned int regr_00_dprx_dpcd_lane0_cr_done            : 1;
    unsigned int regr_00_dprx_dpcd_lane0_channel_eq_done    : 1;
    unsigned int regr_00_dprx_dpcd_lane0_symbol_locked      : 1;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_dprx_dpcd_lane1_cr_done            : 1;
    unsigned int regr_00_dprx_dpcd_lane1_channel_eq_done    : 1;
    unsigned int regr_00_dprx_dpcd_lane1_symbol_locked      : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int regr_00_dprx_dpcd_lane2_cr_done            : 1;
    unsigned int regr_00_dprx_dpcd_lane2_channel_eq_done    : 1;
    unsigned int regr_00_dprx_dpcd_lane2_symbol_locked      : 1;
    unsigned int reserved_2                                 : 1;
    unsigned int regr_00_dprx_dpcd_lane3_cr_done            : 1;
    unsigned int regr_00_dprx_dpcd_lane3_channel_eq_done    : 1;
    unsigned int regr_00_dprx_dpcd_lane3_symbol_locked      : 1;
    unsigned int reserved_3                                 : 1;
    unsigned int regr_00_dprx_dpcd_interlane_align_done     : 1;
    unsigned int regr_00_dprx_dpcd_post_lt_adj_reg_in_process: 1;
    unsigned int reserved_4                                 : 4;
    unsigned int regr_00_dprx_dpcd_downstream_port_status_changed: 1;
    unsigned int regr_00_dprx_dpcd_link_status_updated      : 1;
    unsigned int regr_00_dprx_dpcd_receive_port_0_status    : 1;
    unsigned int regr_00_dprx_dpcd_receive_port_1_status    : 1;
    unsigned int reserved_5                                 : 6;
};
#define rx_edp_rx_dpcd_0_reg_00_ac(val) ((rs_rx_edp_rx_dpcd_0_reg_00_ac*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_B0                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xB0)

#define RX_EDP_RX_DPCD_0_REG_00_B0_struct                                rs_rx_edp_rx_dpcd_0_reg_00_b0

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_b0  rs_rx_edp_rx_dpcd_0_reg_00_b0;
struct _rs_rx_edp_rx_dpcd_0_reg_00_b0 {
    unsigned int regr_00_dprx_dpcd_aux_frame_sync_lock_error: 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_00_dprx_dpcd_dsc_rc_buffer_underrun    : 1;
    unsigned int reg_00_dprx_dpcd_dsc_rc_buffer_overflow    : 1;
    unsigned int regr_00_dprx_dpcd_dsc_chunk_length_error   : 1;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_00_dprx_dpcd_touch_interrupt           : 1;
    unsigned int reserved_2                                 :14;
};
#define rx_edp_rx_dpcd_0_reg_00_b0(val) ((rs_rx_edp_rx_dpcd_0_reg_00_b0*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_C0                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xC0)

#define RX_EDP_RX_DPCD_0_REG_00_C0_struct                                rs_rx_edp_rx_dpcd_0_reg_00_c0

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_c0  rs_rx_edp_rx_dpcd_0_reg_00_c0;
struct _rs_rx_edp_rx_dpcd_0_reg_00_c0 {
    unsigned int reg_00_dprx_dpcd_ext_dpcd_ext_rev          : 8;
    unsigned int reg_00_dprx_dpcd_ext_max_link_rate         : 8;
    unsigned int reg_00_dprx_dpcd_ext_max_lane_count        : 5;
    unsigned int reg_00_dprx_dpcd_ext_post_lt_adj_req_supported: 1;
    unsigned int reg_00_dprx_dpcd_ext_tps3_supported        : 1;
    unsigned int reg_00_dprx_dpcd_ext_enhanced_frame_cap    : 1;
    unsigned int reg_00_dprx_dpcd_ext_max_downspread        : 1;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_ext_no_aux_transaction_link_training: 1;
    unsigned int reg_00_dprx_dpcd_ext_tps4_supported        : 1;
};
#define rx_edp_rx_dpcd_0_reg_00_c0(val) ((rs_rx_edp_rx_dpcd_0_reg_00_c0*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_C4                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xC4)

#define RX_EDP_RX_DPCD_0_REG_00_C4_struct                                rs_rx_edp_rx_dpcd_0_reg_00_c4

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_c4  rs_rx_edp_rx_dpcd_0_reg_00_c4;
struct _rs_rx_edp_rx_dpcd_0_reg_00_c4 {
    unsigned int reg_00_dprx_dpcd_ext_norp                  : 1;
    unsigned int reserved                                   : 4;
    unsigned int reg_00_dprx_dpcd_ext_5v_dp_pwr_cap         : 1;
    unsigned int reg_00_dprx_dpcd_ext_12v_dp_pwr_cap        : 1;
    unsigned int reg_00_dprx_dpcd_ext_18v_dp_pwr_cap        : 1;
    unsigned int reg_00_dprx_dpcd_ext_dfp_present           : 1;
    unsigned int reg_00_dprx_dpcd_ext_dfp_type              : 2;
    unsigned int reg_00_dprx_dpcd_ext_format_conversion     : 1;
    unsigned int reg_00_dprx_dpcd_ext_detailed_cap_info_available: 1;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_dprx_dpcd_ext_ansi_8b10b            : 1;
    unsigned int reserved_2                                 : 7;
    unsigned int reg_00_dprx_dpcd_ext_dfp_count             : 4;
    unsigned int reserved_3                                 : 2;
    unsigned int reg_00_dprx_dpcd_ext_msa_timing_par_ignored: 1;
    unsigned int reg_00_dprx_dpcd_ext_oui_support           : 1;
};
#define rx_edp_rx_dpcd_0_reg_00_c4(val) ((rs_rx_edp_rx_dpcd_0_reg_00_c4*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_C8                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xC8)

#define RX_EDP_RX_DPCD_0_REG_00_C8_struct                                rs_rx_edp_rx_dpcd_0_reg_00_c8

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_c8  rs_rx_edp_rx_dpcd_0_reg_00_c8;
struct _rs_rx_edp_rx_dpcd_0_reg_00_c8 {
    unsigned int reg_00_dprx_dpcd_ext_reserved_0x08         : 1;
    unsigned int reg_00_dprx_dpcd_ext_receive_port0_local_edid_present: 1;
    unsigned int reg_00_dprx_dpcd_ext_receive_port0_associated_to_preceding_port: 1;
    unsigned int reserved                                   : 5;
    unsigned int reg_00_dprx_dpcd_ext_receive_port0_buffer_size: 8;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_00_dprx_dpcd_ext_receive_port1_local_edid_present: 1;
    unsigned int reg_00_dprx_dpcd_ext_receive_port1_associated_to_preceding_port: 1;
    unsigned int reserved_2                                 : 5;
    unsigned int reg_00_dprx_dpcd_ext_receive_port1_buffer_size: 8;
};
#define rx_edp_rx_dpcd_0_reg_00_c8(val) ((rs_rx_edp_rx_dpcd_0_reg_00_c8*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_CC                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xCC)

#define RX_EDP_RX_DPCD_0_REG_00_CC_struct                                rs_rx_edp_rx_dpcd_0_reg_00_cc

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_cc  rs_rx_edp_rx_dpcd_0_reg_00_cc;
struct _rs_rx_edp_rx_dpcd_0_reg_00_cc {
    unsigned int reg_00_dprx_dpcd_ext_i2c_speed_control_capabilites: 8;
    unsigned int reg_00_dprx_dpcd_ext_alternate_scrambler_reset_capable: 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_00_dprx_dpcd_ext_display_control_capable: 1;
    unsigned int reserved_1                                 : 4;
    unsigned int reg_00_dprx_dpcd_ext_training_aux_rd_interval: 7;
    unsigned int reg_00_dprx_dpcd_ext_ext_receiver_cap_field_resent: 1;
    unsigned int reg_00_dprx_dpcd_ext_force_load_sense_cap  : 1;
    unsigned int reg_00_dprx_dpcd_ext_alternate_i2c_pattern_cap: 1;
    unsigned int reserved_2                                 : 6;
};
#define rx_edp_rx_dpcd_0_reg_00_cc(val) ((rs_rx_edp_rx_dpcd_0_reg_00_cc*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_D0                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xD0)

#define RX_EDP_RX_DPCD_0_REG_00_D0_struct                                rs_rx_edp_rx_dpcd_0_reg_00_d0

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_d0  rs_rx_edp_rx_dpcd_0_reg_00_d0;
struct _rs_rx_edp_rx_dpcd_0_reg_00_d0 {
    unsigned int reg_00_dprx_dpcd_ext_gtc_cap               : 1;
    unsigned int reg_00_dprx_dpcd_sst_split_sdp_cap         : 1;
    unsigned int reg_00_dprx_dpcd_ext_av_sync_cap           : 1;
    unsigned int reg_00_dprx_dpcd_ext_vsc_sdp_ext_for_colorimetry_supported: 1;
    unsigned int reg_00_dprx_dpcd_vsc_ext_vesa_sdp_supported: 1;
    unsigned int reg_00_dprx_dpcd_vsc_ext_vesa_sdp_chaining_supported: 1;
    unsigned int reg_00_dprx_dpcd_vsc_ext_cta_sdp_supported : 1;
    unsigned int reg_00_dprx_dpcd_vsc_ext_cta_sdp_chaining_supported: 1;
    unsigned int reg_00_dprx_dpcd_ext_dprx_sleep_wake_timeout_period: 8;
    unsigned int reg_00_dprx_vsc_ext_vesa_sdp_max_chaining_count: 8;
    unsigned int reg_00_dprx_vsc_ext_cta_sdp_max_chaining_count: 8;
};
#define rx_edp_rx_dpcd_0_reg_00_d0(val) ((rs_rx_edp_rx_dpcd_0_reg_00_d0*)&(val))



#define RX_EDP_RX_DPCD_0_REG_00_D4                                       (HV_EDP_RX_DPCD_0_REG_00_BASE_ADDRESS + 0xD4)

#define RX_EDP_RX_DPCD_0_REG_00_D4_struct                                rs_rx_edp_rx_dpcd_0_reg_00_d4

typedef struct _rs_rx_edp_rx_dpcd_0_reg_00_d4  rs_rx_edp_rx_dpcd_0_reg_00_d4;
struct _rs_rx_edp_rx_dpcd_0_reg_00_d4 {
    unsigned int reg_00_dprx_adaptive_sync_sdp_supported    : 1;
    unsigned int reg_00_dprx_as_sdp_first_half_line_or_3840_pixel_cycle_window_not_supported: 1;
    unsigned int reserved                                   :12;
    unsigned int reg_00_dprx_adaptive_sync_sdp_t2_supported_in_all_pr_active_states: 1;
    unsigned int reserved_1                                 :17;
};
#define rx_edp_rx_dpcd_0_reg_00_d4(val) ((rs_rx_edp_rx_dpcd_0_reg_00_d4*)&(val))



#endif