#ifndef _HV_PAGE_HT7315_SH01_PLL_H_
#define _HV_PAGE_HT7315_SH01_PLL_H_

#ifndef HV_SH01_PLL_BASE_ADDRESS
    #define HV_SH01_PLL_BASE_ADDRESS                                         0x1101C000
#endif


#define SYS_SH01_PLL_FNPLL_00                                            (HV_SH01_PLL_BASE_ADDRESS + 0x00)

#define SYS_SH01_PLL_FNPLL_00_struct                                     rs_sys_sh01_pll_fnpll_00

typedef struct _rs_sys_sh01_pll_fnpll_00  rs_sys_sh01_pll_fnpll_00;
struct _rs_sys_sh01_pll_fnpll_00 {
    unsigned int reg_fnpll_en                               : 1;
    unsigned int reg_fnpll_stb_en                           : 1;
    unsigned int reg_fnpll_rstn                             : 1;
    unsigned int reg_fnpll_div_mode                         : 1;
    unsigned int reg_fnpll_ib5u_sel                         : 1;
    unsigned int reg_fnpll_test_mode                        : 1;
    unsigned int reg_fnpll_free_run                         : 1;
    unsigned int reg_fnpll_overflow_rst_en                  : 1;
    unsigned int reg_fnpll_lock_force                       : 1;
    unsigned int reg_fnpll_lock_cnt_sel                     : 1;
    unsigned int reg_fnpll_lock_wd_sel                      : 2;
    unsigned int reg_fnpll_ana_test_sel                     : 4;
    unsigned int reg_fnpll_dummy                            : 8;
    unsigned int reg_fnpll_rnd_mode                         : 1;
    unsigned int reg_fnpll_dac_en                           : 1;
    unsigned int reserved                                   : 6;
};
#define sys_sh01_pll_fnpll_00(val) ((rs_sys_sh01_pll_fnpll_00*)&(val))



#define SYS_SH01_PLL_FNPLL_01                                            (HV_SH01_PLL_BASE_ADDRESS + 0x04)

#define SYS_SH01_PLL_FNPLL_01_struct                                     rs_sys_sh01_pll_fnpll_01

typedef struct _rs_sys_sh01_pll_fnpll_01  rs_sys_sh01_pll_fnpll_01;
struct _rs_sys_sh01_pll_fnpll_01 {
    unsigned int reg_fnpll_dly_ctrl                         : 3;
    unsigned int reg_fnpll_icp_bias_tune                    : 3;
    unsigned int reg_fnpll_icp_ctrl1                        : 4;
    unsigned int reg_fnpll_icp_ctrl2                        : 3;
    unsigned int reg_fnpll_lpf_ctrl                         : 4;
    unsigned int reg_fnpll_kvco_ctrl                        : 6;
    unsigned int reg_fnpll_ckref_sel                        : 2;
    unsigned int reg_fnpll_prediv                           : 6;
    unsigned int reserved                                   : 1;
};
#define sys_sh01_pll_fnpll_01(val) ((rs_sys_sh01_pll_fnpll_01*)&(val))



#define SYS_SH01_PLL_FNPLL_02                                            (HV_SH01_PLL_BASE_ADDRESS + 0x08)

#define SYS_SH01_PLL_FNPLL_02_struct                                     rs_sys_sh01_pll_fnpll_02

typedef struct _rs_sys_sh01_pll_fnpll_02  rs_sys_sh01_pll_fnpll_02;
struct _rs_sys_sh01_pll_fnpll_02 {
    unsigned int reg_fnpll_postdiv0                         :10;
    unsigned int reg_fnpll_postdiv1                         :10;
    unsigned int reg_fnpll_postdiv2                         :10;
    unsigned int reserved                                   : 2;
};
#define sys_sh01_pll_fnpll_02(val) ((rs_sys_sh01_pll_fnpll_02*)&(val))



#define SYS_SH01_PLL_FNPLL_03                                            (HV_SH01_PLL_BASE_ADDRESS + 0x0C)

#define SYS_SH01_PLL_FNPLL_03_struct                                     rs_sys_sh01_pll_fnpll_03

typedef struct _rs_sys_sh01_pll_fnpll_03  rs_sys_sh01_pll_fnpll_03;
struct _rs_sys_sh01_pll_fnpll_03 {
    unsigned int reg_fnpll_postdiv0_div2                    : 1;
    unsigned int reg_fnpll_postdiv0_0                       : 6;
    unsigned int reg_fnpll_postdiv0_1                       : 6;
    unsigned int reg_fnpll_postdiv_lvds                     : 2;
    unsigned int reg_fnpll_cklvds_al_skew                   : 4;
    unsigned int reg_fnpll_cklvds_ar_skew                   : 4;
    unsigned int reg_fnpll_cklvds_en                        : 1;
    unsigned int reg_fnpll_cklvds_lr_sel                    : 2;
    unsigned int reserved                                   : 6;
};
#define sys_sh01_pll_fnpll_03(val) ((rs_sys_sh01_pll_fnpll_03*)&(val))



#define SYS_SH01_PLL_FNPLL_SSCG_0                                        (HV_SH01_PLL_BASE_ADDRESS + 0x24)

#define SYS_SH01_PLL_FNPLL_SSCG_0_struct                                 rs_sys_sh01_pll_fnpll_sscg_0

typedef struct _rs_sys_sh01_pll_fnpll_sscg_0  rs_sys_sh01_pll_fnpll_sscg_0;
struct _rs_sys_sh01_pll_fnpll_sscg_0 {
    unsigned int reg_sh1_sscg_sscg_en                       : 1;
    unsigned int reg_sh1_sscg_mode                          : 2;
    unsigned int reserved                                   :13;
    unsigned int reg_sh1_sscg_step                          :16;
};
#define sys_sh01_pll_fnpll_sscg_0(val) ((rs_sys_sh01_pll_fnpll_sscg_0*)&(val))



#define SYS_SH01_PLL_FNPLL_SSSCG_1                                       (HV_SH01_PLL_BASE_ADDRESS + 0x28)

#define SYS_SH01_PLL_FNPLL_SSSCG_1_struct                                rs_sys_sh01_pll_fnpll_ssscg_1

typedef struct _rs_sys_sh01_pll_fnpll_ssscg_1  rs_sys_sh01_pll_fnpll_ssscg_1;
struct _rs_sys_sh01_pll_fnpll_ssscg_1 {
    unsigned int reg_sh1_sscg_period0                       :12;
    unsigned int reserved                                   : 4;
    unsigned int reg_sh1_sscg_period1                       :12;
    unsigned int reserved_1                                 : 4;
};
#define sys_sh01_pll_fnpll_ssscg_1(val) ((rs_sys_sh01_pll_fnpll_ssscg_1*)&(val))



#define SYS_SH01_PLL_FNPLL_SSSCG_2                                       (HV_SH01_PLL_BASE_ADDRESS + 0x2C)

#define SYS_SH01_PLL_FNPLL_SSSCG_2_struct                                rs_sys_sh01_pll_fnpll_ssscg_2

typedef struct _rs_sys_sh01_pll_fnpll_ssscg_2  rs_sys_sh01_pll_fnpll_ssscg_2;
struct _rs_sys_sh01_pll_fnpll_ssscg_2 {
    unsigned int reg_sh1_sscg_fbdiv_int                     :10;
    unsigned int reserved                                   : 6;
    unsigned int reg_sh1_sscg_fbdiv_frac                    :16;
};
#define sys_sh01_pll_fnpll_ssscg_2(val) ((rs_sys_sh01_pll_fnpll_ssscg_2*)&(val))



#define SYS_SH01_PLL_FNPLL_LOCK_DET_0                                    (HV_SH01_PLL_BASE_ADDRESS + 0x30)

#define SYS_SH01_PLL_FNPLL_LOCK_DET_0_struct                             rs_sys_sh01_pll_fnpll_lock_det_0

typedef struct _rs_sys_sh01_pll_fnpll_lock_det_0  rs_sys_sh01_pll_fnpll_lock_det_0;
struct _rs_sys_sh01_pll_fnpll_lock_det_0 {
    unsigned int reg_sh1_pll_lock_det_lock_fw_mode          : 1;
    unsigned int reg_sh1_pll_lock_det_lock_fw_value         : 1;
    unsigned int reg_sh1_pll_lock_det_det_win               : 3;
    unsigned int reg_sh1_pll_lock_det_locked_num            : 4;
    unsigned int reg_sh1_pll_lock_det_unlocked_num          : 4;
    unsigned int reg_sh1_pll_lock_det_lock_err_range        : 8;
    unsigned int reg_sh1_pll_lock_det_fast_err_range        : 8;
    unsigned int reserved                                   : 3;
};
#define sys_sh01_pll_fnpll_lock_det_0(val) ((rs_sys_sh01_pll_fnpll_lock_det_0*)&(val))



#define SYS_SH01_PLL_FNPLL_LOCK_DET_1                                    (HV_SH01_PLL_BASE_ADDRESS + 0x34)

#define SYS_SH01_PLL_FNPLL_LOCK_DET_1_struct                             rs_sys_sh01_pll_fnpll_lock_det_1

typedef struct _rs_sys_sh01_pll_fnpll_lock_det_1  rs_sys_sh01_pll_fnpll_lock_det_1;
struct _rs_sys_sh01_pll_fnpll_lock_det_1 {
    unsigned int reg_sh1_pll_lock_det_no_clk_th             : 8;
    unsigned int reserved                                   :24;
};
#define sys_sh01_pll_fnpll_lock_det_1(val) ((rs_sys_sh01_pll_fnpll_lock_det_1*)&(val))



#define SYS_SH01_PLL_CLKGEN_0                                            (HV_SH01_PLL_BASE_ADDRESS + 0x38)

#define SYS_SH01_PLL_CLKGEN_0_struct                                     rs_sys_sh01_pll_clkgen_0

typedef struct _rs_sys_sh01_pll_clkgen_0  rs_sys_sh01_pll_clkgen_0;
struct _rs_sys_sh01_pll_clkgen_0 {
    unsigned int reg_ddr_clk_sel                            : 1;
    unsigned int reg_ddr1x_clk_en                           : 1;
    unsigned int reserved                                   : 2;
    unsigned int reg_ddraxi_clk_en                          : 8;
    unsigned int reserved_1                                 :20;
};
#define sys_sh01_pll_clkgen_0(val) ((rs_sys_sh01_pll_clkgen_0*)&(val))



#define SYS_SH01_PLL_RSTGEN_0                                            (HV_SH01_PLL_BASE_ADDRESS + 0x3C)

#define SYS_SH01_PLL_RSTGEN_0_struct                                     rs_sys_sh01_pll_rstgen_0

typedef struct _rs_sys_sh01_pll_rstgen_0  rs_sys_sh01_pll_rstgen_0;
struct _rs_sys_sh01_pll_rstgen_0 {
    unsigned int reg_sh1_fnpll_rst_n                        : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_sh1_ddrmc_rst_n                        : 1;
    unsigned int reg_sh1_phy_rst_n                          : 1;
    unsigned int reg_sh1_ddr_axi_rst_n                      : 8;
    unsigned int reserved_1                                 :20;
};
#define sys_sh01_pll_rstgen_0(val) ((rs_sys_sh01_pll_rstgen_0*)&(val))



#define SYS_SH01_PLL_RSTGEN_1                                            (HV_SH01_PLL_BASE_ADDRESS + 0x40)

#define SYS_SH01_PLL_RSTGEN_1_struct                                     rs_sys_sh01_pll_rstgen_1

typedef struct _rs_sys_sh01_pll_rstgen_1  rs_sys_sh01_pll_rstgen_1;
struct _rs_sys_sh01_pll_rstgen_1 {
    unsigned int reg_sh1_ddrmc_apb_rst_n                    : 1;
    unsigned int reg_sh1_ddrphy_apb_rst_n                   : 1;
    unsigned int reserved                                   :30;
};
#define sys_sh01_pll_rstgen_1(val) ((rs_sys_sh01_pll_rstgen_1*)&(val))



#define SYS_SH01_PLL_FNPLL_READBACK_00                                   (HV_SH01_PLL_BASE_ADDRESS + 0xEC)

#define SYS_SH01_PLL_FNPLL_READBACK_00_struct                            rs_sys_sh01_pll_fnpll_readback_00

typedef struct _rs_sys_sh01_pll_fnpll_readback_00  rs_sys_sh01_pll_fnpll_readback_00;
struct _rs_sys_sh01_pll_fnpll_readback_00 {
    unsigned int regr_fnpll_test                            :10;
    unsigned int regr_fnpll_lock_cnt_en                     : 1;
    unsigned int regr_fnpll_lock_flag                       : 1;
    unsigned int regr_fnpll_overflow_flag                   : 1;
    unsigned int regr_fnpll_phase_error_flag                : 1;
    unsigned int reserved                                   :18;
};
#define sys_sh01_pll_fnpll_readback_00(val) ((rs_sys_sh01_pll_fnpll_readback_00*)&(val))



#define SYS_SH01_PLL_FNPLL_SSCG_RO_0                                     (HV_SH01_PLL_BASE_ADDRESS + 0xF0)

#define SYS_SH01_PLL_FNPLL_SSCG_RO_0_struct                              rs_sys_sh01_pll_fnpll_sscg_ro_0

typedef struct _rs_sys_sh01_pll_fnpll_sscg_ro_0  rs_sys_sh01_pll_fnpll_sscg_ro_0;
struct _rs_sys_sh01_pll_fnpll_sscg_ro_0 {
    unsigned int regr_sh1_sscg_triwave_31_00                :32;
};
#define sys_sh01_pll_fnpll_sscg_ro_0(val) ((rs_sys_sh01_pll_fnpll_sscg_ro_0*)&(val))



#define SYS_SH01_PLL_FNPLL_SSCG_RO_1                                     (HV_SH01_PLL_BASE_ADDRESS + 0xF4)

#define SYS_SH01_PLL_FNPLL_SSCG_RO_1_struct                              rs_sys_sh01_pll_fnpll_sscg_ro_1

typedef struct _rs_sys_sh01_pll_fnpll_sscg_ro_1  rs_sys_sh01_pll_fnpll_sscg_ro_1;
struct _rs_sys_sh01_pll_fnpll_sscg_ro_1 {
    unsigned int regr_sh1_sscg_triwave_43_32                :12;
    unsigned int reserved                                   :20;
};
#define sys_sh01_pll_fnpll_sscg_ro_1(val) ((rs_sys_sh01_pll_fnpll_sscg_ro_1*)&(val))



#define SYS_SH01_PLL_FNPLL_LOCK_DET_RO_0                                 (HV_SH01_PLL_BASE_ADDRESS + 0xF8)

#define SYS_SH01_PLL_FNPLL_LOCK_DET_RO_0_struct                          rs_sys_sh01_pll_fnpll_lock_det_ro_0

typedef struct _rs_sys_sh01_pll_fnpll_lock_det_ro_0  rs_sys_sh01_pll_fnpll_lock_det_ro_0;
struct _rs_sys_sh01_pll_fnpll_lock_det_ro_0 {
    unsigned int regr_sh1_pll_lock_det_ref_int_value        :16;
    unsigned int regr_sh1_pll_lock_det_vco_int_value        :16;
};
#define sys_sh01_pll_fnpll_lock_det_ro_0(val) ((rs_sys_sh01_pll_fnpll_lock_det_ro_0*)&(val))



#define SYS_SH01_PLL_FNPLL_LOCK_DET_RO_1                                 (HV_SH01_PLL_BASE_ADDRESS + 0xFC)

#define SYS_SH01_PLL_FNPLL_LOCK_DET_RO_1_struct                          rs_sys_sh01_pll_fnpll_lock_det_ro_1

typedef struct _rs_sys_sh01_pll_fnpll_lock_det_ro_1  rs_sys_sh01_pll_fnpll_lock_det_ro_1;
struct _rs_sys_sh01_pll_fnpll_lock_det_ro_1 {
    unsigned int regr_sh1_pll_lock_det_pll_lock             : 1;
    unsigned int regr_sh1_pll_lock_det_ref_clk_fast         : 1;
    unsigned int regr_sh1_pll_lock_det_vco_clk_fast         : 1;
    unsigned int regr_sh1_pll_lock_det_ref_no_clk           : 1;
    unsigned int regr_sh1_pll_lock_det_vco_no_clk           : 1;
    unsigned int regr_ddrphy_plllock                        : 1;
    unsigned int regr_phase                                 : 4;
    unsigned int reserved                                   :16;
    unsigned int regr_fpga_dbg_axi_reset                    : 1;
    unsigned int regr_fpga_dbg_emif_reset_req               : 1;
    unsigned int regr_fpga_dbg_emif_reset_done              : 1;
    unsigned int regr_fpga_dbg_emif_pll_locked              : 1;
    unsigned int regr_fpga_dbg_emif_cal_success             : 1;
    unsigned int regr_fpga_dbg_emif_cal_fail                : 1;
};
#define sys_sh01_pll_fnpll_lock_det_ro_1(val) ((rs_sys_sh01_pll_fnpll_lock_det_ro_1*)&(val))



#endif