/**
 * @file hv_cal_Dprx.h
 * @brief Header file of DpRx Cal module.
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-10
 */
#ifndef __HV_CAL_DPRX_H__
#define __HV_CAL_DPRX_H__

#include "Common/hv_comm_DataType.h"
#include "hv_comm_Define.h"
#include "hv_comm_Event.h"
#include "BoardConfig.h"

/**********Timing info from MSA***********/
typedef struct _DpMsaParam
{
    USHORT16 usHTotal;
    USHORT16 usVTotal;
    USHORT16 usHActive;
    USHORT16 usVActive;
    USHORT16 usHStart;
    USHORT16 usVStart;
    USHORT16 usHSW;
    USHORT16 usVSW;
    UCHAR8   ucHSP;
    UCHAR8   ucVSP;
    UCHAR8   ucMisc0;
    UCHAR8   ucMisc1;
    UINT32   uiMvid;
    UINT32   uiNvid;
    UINT32   uiMaud;
    UINT32   uiNaud;
} DpMsaParam;

typedef struct _MeasureTiming
{
    USHORT16 usHTotal;
    USHORT16 usVTotal;
    USHORT16 usHActive;
    USHORT16 usVActive;
    UINT32   uiFrameTotal;
} MeasureTiming;

typedef struct _DpRxVscColor
{
    UCHAR8 ucColorFormat;
    UCHAR8 ucBitDepth;
    UCHAR8 ucColorSpace;
    UCHAR8 ucColorRange;
    UCHAR8 ucColorContent;
} DpRxVscClolor;

typedef struct _DpRxIntReg
{
    UCHAR8 ucDpRxRegType : 7;
    UCHAR8 ucDpRxRegEn : 1;
} DpRxIntReg;

typedef enum _DpRxIntTypeL
{
    DPRX_AUX_RD_DPCD_EN_17     = 0,    /* write dpcd 00101 */
    DPRX_AUX_RD_DPCD_EN_1_4    = 1,    /* read dpcd 00211~00217 */
    DPRX_AUX_RD_DPCD_EN_5      = 2,    /* write dpcd 00600 */
    DPRX_AUX_RD_DPCD_EN_6      = 3,    /* write dpcd 00102 */
    DPRX_AUX_RD_DPCD_EN_7      = 4,    /* write dpcd 00100 */
    DPRX_AUX_RD_DPCD_EN_8      = 5,    /* write dpcd 00115 */
    DPRX_AUX_RD_DPCD_EN_18     = 6,    /* dpcd write/read ack */
    DPRX_AUX_RESERVED_1        = 7,    /* reserved */
    DPRX_AUX_RESERVED_2        = 8,    /* reserved */
    O_DPRX_FT_IRQ_7            = 9,    /* lane_deskew change */
    O_DPRX_FT_IRQ_0            = 10,   /* dprx will training done */
    O_DPRX_FT_IRQ_1            = 11,   /* dprx will training fail */
    VB_ID_IRQ_0                = 12,   /* vblank end */
    VB_ID_IRQ_1                = 13,   /* interlaced flag change */
    VB_ID_IRQ_2                = 14,   /* no_video flag change */
    VB_ID_IRQ_3                = 15,   /* audio_mute flag change */
    PM_INT_0                   = 16,   /* pm fsm change */
    PM_INT_1                   = 17,   /* alpm lock timeout */
    O_DPRX_FT_IRQ_5            = 18,   /* actual link rate change */
    O_DPRX_FT_IRQ_6            = 19,   /* actual lane count change */
    PSR_IRQ_INT_0              = 20,   /* psr_crc_error */
    PSR_IRQ_INT_1              = 21,   /* psr ml loss */
    PSR_IRQ_INT_2              = 22,   /* psr_fsm_change */
    DPRX_DSC_INT               = 23,   /* dsc int, see spec */
    GTC_INT_0                  = 24,   /* aux wr dpcd 00155 */
    GTC_INT_1                  = 25,   /* gtc unlock cnt > thro */
    GTC_INT_2                  = 26,   /* aux wr dpcd 00155 frame_sync val */
    GTC_INT_3                  = 27,   /* reg_dprx_frame_sync_irq_hpd_en by fw */
    DPRX_COLOR_CHANGE          = 28,   /* Color change */
    DPRX_MNVID_CHANGE          = 29,   /* dprx mvid,nvid change */
    DPRX_RESOLUTION_CHANGE     = 30,   /* dprx resolution chg */
    O_DPRX_FT_IRQ_2            = 31,   /* dpcd link rate change */
    DP_RX_INT_L_NUM            = 32,
} DpRxIntTypeL;

typedef enum _DpRxIntTypeH
{
    DPRX_AUX_MSG_1000          = 0,    /* Write down req buffer (0x01000) */
    DPRX_AUX_MSG_1200          = 1,    /* Write up rep buffer   (0x01200) */
    DPRX_AUX_MSG_1400          = 2,    /* read down rep buffer  (0x01400) */
    DPRX_AUX_MSG_1600          = 3,    /* Read down req buffer (0x01600) */
    DPRX_SW_IRQ                = 4,    /* Reg_dprx_sw_irq */
    SDP_IRQ_0                  = 5,    /* Audio stream sdp irq */
    SDP_IRQ_1                  = 6,    /* sdp fifo depth irq */
    SDP_IRQ_2                  = 7,    /* sdp hdr update irq */
    SDP_IRQ_3                  = 8,    /* sdp fifo depth full irq */
    DP_RX_MCCS                 = 9,    /* Mccs irq */
    O_DPRX_FT_IRQ_3            = 10,   /* dpcd lane count change */
    O_DPRX_FT_IRQ_4            = 11,   /* training timeout */
    DPRX_AUX_RD_DPCD_EN_13     = 12,   /* wr/rd any dpcd addr range0 */
    DPRX_AUX_RD_DPCD_EN_14     = 13,   /* wr/rd any dpcd addr range1 */
    DPRX_AUX_RD_DPCD_EN_15     = 14,   /* wr/rd any dpcd addr range2 */
    DPRX_AUX_RD_DPCD_EN_16     = 15,   /* wr/rd any dpcd addr range3 */
    HDCP_1X_0                  = 16,   /* Wirite 0x68xxx done */
    HDCP_1X_1                  = 17,   /* read 0x68xxx done */
    HDCP_1X_2                  = 18,   /* Write aksv done (0x68007+5) */
    HDCP_1X_3                  = 19,   /* Write ainfo done (0x6803B+1) */
    HDCP_2X_0                  = 20,   /* Wirite 0x69xxx done */
    HDCP_2X_1                  = 21,   /* read 0x69xxx done */
    HDCP_2X_2                  = 22,   /* Write txcap done (0x69008+3) */
    HDCP_2X_3                  = 23,   /* Write Ekpub_km done (0x69220+128) */
    HDCP_2X_4                  = 24,   /* Write m done (0x692B0+16) */
    HDCP_2X_5                  = 25,   /* Write Rn done (0x692f0+8) */
    HDCP_2X_6                  = 26,   /* Write Riv done (0x69328+8) */
    HDCP_2X_7                  = 27,   /* Write V done (0x693f0+3) */
    HDCP_2X_8                  = 28,   /* Write stream_ID_Type done */
    HDCP_2X_9                  = 29,   /* read H’ done (0x692c0+32) done */
    HDCP_2X_10                 = 30,   /* read Ekh_km done (0x692e0+16) done */
    HDCP_2X_11                 = 31,   /* read 0x69494+1 done */
    DP_RX_INT_H_NUM            = 32,
} DpRxIntTypeH;

typedef enum _DpRxIntTypeL1
{
    DPRX_VRR_UPDATE_IRQ        = 0,    /* VRR Update Irq */
    DPRX_ADPT_START_IRQ        = 1,    /* Adaptive sync start Irq */
    DPRX_ADPT_END_IRQ          = 2,    /* Adaptive sync End Irq */
    DPRX_AUDO_DEPTH_HIGH       = 3,
    DPRX_AUDO_DEPTH_LOW        = 4,
    DPRX_RWTOTAL_CHG           = 5,
    DPRX_MSATOTAL_CHG          = 6,
    DP_RX_INT_L1_NUM           = 7,
} DpRxIntTypeL1;

#define AUDIO_L_L              10      /* Audio lowest threshold */
#define AUDIO_L_H              150     /* Audio lower threshold */
#define AUDIO_H_L              250     /* Audio higher threshold */
#define AUDIO_H_H              350     /* Audio highest threshold */
#define AUDIO_START            400     /* Audio start threshold */

/**
 * @brief DP CableDet init.
 * @param[in] ucPortId: port index 0 or 1
 * @param[ucDp0Mode] DP0 Mode: Standard or Alt
 * @param[ucDp1Mode] DP1 Mode: Standard or Alt
 * @return VOID.
 */
VOID Hv_Cal_DpRx_CableInit(UCHAR8 ucPortId, UCHAR8 ucDp0Mode, UCHAR8 ucDp1Mode);

/**
 * @brief DP HPD init.
 * @param[in] ucPortId: port index 0 or 1
 * @param[ucDp0Mode] DP0 Mode: Standard or Alt
 * @param[ucDp1Mode] DP1 Mode: Standard or Alt
 * @return VOID.
 */
VOID Hv_Cal_DpRx_HpdInit(UCHAR8 ucPortId, UCHAR8 ucDp0Mode, UCHAR8 ucDp1Mode, UCHAR8 ucHpd0IoCtrl);

/**
 * @brief DP Standby Aux init.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] bCtsOn: Cts config
 * @return VOID.
 */
VOID Hv_Cal_DpRx_StandbyAuxInit(UCHAR8 ucPortId, BOOL bCtsOn);

/**
 * @brief DP Standby Aux init.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] bCtsOn: Cts config
 * @param[uiApbClk] APB clock
 * @return VOID.
 */
VOID Hv_Cal_DpRx_AuxInit(UCHAR8 ucPortId, BOOL bCtsOn, UINT32 uiApbClk);

/**
 * @brief DP DPCD init.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] bCtsOn: Cts config
 * @return VOID.
 */
VOID Hv_Cal_DpRx_DpcdInit(UCHAR8 ucPortId, BOOL bCtsOn);

/**
 * @brief Set Sink OUI.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetSinkOui(UCHAR8 ucPortId, UINT32 uiOui, UCHAR8 ucStr0, UINT32 uiStr1, UCHAR8 ucStr2,
                                     UCHAR8 ucHwMaj, UCHAR8 ucHwMin, UCHAR8 ucFwMaj, UCHAR8 ucFwMin);

/**
 * @brief Set GUID.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetGuid(UCHAR8 ucPortId, UINT32 uiGuid0, UINT32 uiGuid1, UINT32 uiGuid2, UINT32 uiGuid3);

/**
 * @brief Set DP version.
 * @param[in] ucPortId: port index 0 or 1
 * @param[ucDpVer] DP Version 1.2 or 1.4
 * @return Status.
 */
Status Hv_Cal_DpRx_SetDpVer(UCHAR8 ucPortId, UCHAR8 ucDpVer);

/**
 * @brief Get DP version.
 * @param[in] ucPortId: port index 0 or 1
 * @return DP version.
 */
UCHAR8 Hv_Cal_DpRx_GetDpVer(UCHAR8 ucPortId);

/**
 * @brief Reset DPCD control and configuration.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_ResetDpcd(UCHAR8 ucPortId);

/**
 * @brief DP Mac init.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MacInit(UCHAR8 ucPortId, BOOL bCtsOn, UINT32 uiApbClk);

/**
 * @brief DP lane swap.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetLaneSwap(UCHAR8 ucPortId, UCHAR8 ucDpLane0, UCHAR8 ucDpLane1, UCHAR8 ucDpLane2, UCHAR8 ucDpLane3, UCHAR8 ucLanePol);

/**
 * @brief DP max lane count.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] ucDpLaneCount: 1 or 2 or 4
 * @return Status.
 */
Status Hv_Cal_DpRx_SetMaxLaneCount(UCHAR8 ucPortId, UCHAR8 ucDpLaneCount);

/**
 * @brief Init DP Training settings.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_TrainingInit(UCHAR8 ucPortId, BOOL bCtsOn);

/**
 * @brief Init DP SDP settings.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SdpInit(UCHAR8 ucPortId);

/**
 * @brief Init DP Sys settings.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SysInit(UCHAR8 ucPortId);

/**
 * @brief Get cable connect status.
 * @param[in] ucPortId: port index 0 or 1
 * @return HV_TRUE or HV_FALSE.
 */
BOOL Hv_Cal_DpRx_DetectCable(UCHAR8 ucPortId);

/**
 * @brief Set cable connect status, used for debug tool.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetCableStatus(UCHAR8 ucPortId, BOOL bPlugIn);

/**
 * @brief Set hpd status, used for debug tool.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetHPDStatus(UCHAR8 ucPortId, BOOL bHigh);

/**
 * @brief Generate irq hpd.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_IrqHpd(UCHAR8 ucPortId);

/**
 * @brief DpRx hpd control.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] bSwitch: HV_FALSE:low; HV_TRUE:high
 * @return VOID.
 */
VOID Hv_Cal_DpRx_EvtHpd(UCHAR8 ucPortId, BOOL bSwitch);

/**
 * @brief Get Link rate.
 * @param[in] ucPortId: port index 0 or 1
 * @return UCHAR8, 6/10/20.
 */
UCHAR8 Hv_Cal_DpRx_GetLinkRate(UCHAR8 ucPortId);

/**
 * @brief Get Lane Clock.
 * @param[in] ucPortId: port index 0 or 1
 * @return UINT32, symbol clock.
 */
UINT32 Hv_Cal_DpRx_GetLaneClk(UCHAR8 ucPortId);

/**
 * @brief Get Timing Ignore.
 * @param[in] ucPortId: port index 0 or 1
 * @return HV_TRUE or HV_FALSE.
 */
BOOL Hv_Cal_DpRx_GetTimIgnore(UCHAR8 ucPortId);

/**
 * @brief Set Timing Ignore.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] bIgnore: ignore msa timing or not
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetTimIgnore(UCHAR8 ucPortId, BOOL bIgnore);

/**
 * @brief Get Source OUI.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_GetSrcOui(UCHAR8 ucPortId, UINT32 *puiOui, UCHAR8 *pucIdentification);

/**
 * @brief Get Power state.
 * @param[in] ucPortId: port index 0 or 1
 * @return 1:power on; 2:power off.
 */
UCHAR8 Hv_Cal_DpRx_GetPowerState(UCHAR8 ucPortId);

/**
 * @brief Get Link state.
 * @param[in] ucPortId: port index 0 or 1
 * @param[out] pucLTState:1:training done; 0:training fail.
 * @return HV_TRUE or HV_FALSE.
 */
BOOL Hv_Cal_DpRx_GetLtState(UCHAR8 ucPortId);

/**
 * @brief Dump Training NG reason.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_DumpFailStatus(UCHAR8 ucPortId);

/**
 * @brief Detect the Video Timing
 * @param[in] ucPortId: port index 0 or 1
 * @param[out] ptMsa point to Video Timing.
 * @return VOID.
 */
VOID Hv_Cal_DpRx_GetMsa(UCHAR8 ucPortId, DpMsaParam *pstMsa);


/**
 * @brief Detect the Video BsCount & BeCount
 * @param[in] ucPortId: port index 0 or 1
 * @param[out] usBsCnt, usBeCnt.
 * @return VOID.
 */
VOID Hv_Cal_DpRx_GetBsBe(UCHAR8 ucPortId, USHORT16 *usBsCnt, USHORT16 *usBeCnt);

/**
 * @brief Get IRQ ID
 * @param[in] ucPortId: port index 0 or 1
 * @return UCHAR8, IRQ ID.
 */
UCHAR8 Hv_Cal_DpRx_GetIrqId(UCHAR8 ucPortId);

/**
 * @brief Get IRQ ID
 * @param[in] ucPortId: port index 0 or 1
 * @return UCHAR8, IRQ ID.
 */
UCHAR8 Hv_Cal_DpRx_GetCableIrqId(UCHAR8 ucPortId);

/**
 * @brief Dp Rx interupt enable.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetIntEnable(UCHAR8 ucPortId);

/**
 * @brief Dp Rx ErrorCount interupt enable.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_ErrIntEnable(UCHAR8 ucPortId);

/**
 * @brief Dp Rx SDP interupt mask.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MaskSdpInt(UCHAR8 ucPortId, BOOL bSwitch);

/**
 * @brief Dp Rx Color Change interupt mask.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID  Hv_Cal_DpRx_MaskColorInt(UCHAR8 ucPortId, BOOL bSwitch);

/**
 * @brief Dp Rx Timing interupt mask.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MaskTimingInt(UCHAR8 ucPortId, BOOL bSwitch);

/**
 * @brief Dp Rx Htotal interupt mask.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MaskRxHtotalInt(UCHAR8 ucPortId, BOOL bSwitch);

/**
 * @brief Dp Rx MSA interupt mask.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MaskMSAInt(UCHAR8 ucPortId, BOOL bSwitch);

/**
 * @brief Dp Rx Audio depth interupt mask.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MaskAudioDepthInt(UCHAR8 ucPortId, BOOL bSwitch);
/**
 * @brief Get Interrupt Flags
 * @param[in] ucPortId: port index 0 or 1
 * @param[out] puiDpIntFlag point to the Interrupt Flags that don't belong to hdcp.
 * @param[out] puiHdcpIntFlag point to the Interrupt Flags that belong to hdcp.
 * @return VOID.
 */
VOID Hv_Cal_DpRx_GetIntFlag(UCHAR8 ucPortId, BOOL bCtsOn, UINT32 *puiDpIntFlag, UINT32 *puiHdcpIntFlag, UCHAR8 ucDpLane0, UCHAR8 ucDpLane1, UCHAR8 ucDpLane2, UCHAR8 ucDpLane3);

/**
 * @brief Clear Interrupt Flags
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] puiNoHdcpIntFlag point to the Interrupt Flags that don't belong to hdcp.
 * @param[in] puiHdcpIntFlag point to the Interrupt Flags that belong to hdcp.
 * @return VOID.
 */
VOID Hv_Cal_DpRx_ClrIntFlag(UCHAR8 ucPortId, UINT32 *puiNoHdcpIntFlag, UINT32 *puiHdcpIntFlag);

/**
 * @brief Dp Rx Link Bandwidth changed.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_LinkBwChanged(UCHAR8 ucPortId);

/**
 * @brief Dp Rx Link Count changed.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_LinkCountChanged(UCHAR8 ucPortId, UCHAR8 ucDpLane0, UCHAR8 ucDpLane1, UCHAR8 ucDpLane2, UCHAR8 ucDpLane3, UCHAR8 ucAuxPol);

/**
 * @brief Dp Rx generate EQ Permit.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_EqPermit(UCHAR8 ucPortId, BOOL bCtsOn);

/**
 * @brief Dp Rx Training Done.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_TrainingDone(UCHAR8 ucPortId);

/**
 * @brief Dp Rx Training Failed.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_TrainingFail(UCHAR8 ucPortId, BOOL bCtsOn);

/**
 * @brief Dp Rx select training mode.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] ucTrainMode: auto/no-link/full-link
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetTrainMode(UCHAR8 ucPortId, UCHAR8 ucTrainMode);

/**
 * @brief Dp Rx audio fifo OnOff.
 * @param[in] ucPortId: port index 0 or 1
 * @return Status.
 */
Status Hv_Cal_DpRx_AudioFifoOnOff(UCHAR8 ucPortId, BOOL bEn);

/**
 * @brief Dp Rx reshape audio data.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_AudioReshape(UCHAR8 ucPortId);

/**
 * @brief Dp Rx re-do deskew.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_ToggleDeskew(UCHAR8 ucPortId);

/**
 * @brief Dp Rx recieve sw irq.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SwIrq(UCHAR8 ucPortId);

/**
 * @brief Clear cable Interrupt Flags
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_ClrCableIntFlag(UCHAR8 ucPortId);

/**
 * @brief Get mccs command.
 * @param[in] ucPortId: port index 0 or 1
 * @param[out] pucMccsContent point to the mccs command;
 * @param[in] uclen command len.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Cal_DpRx_GetMccsCommand(UCHAR8 ucPortId, UCHAR8 *pucMccsContent, UCHAR8 uclen);

/**
 * @brief Get vsc value.
 * @param[in] ucPortId: port index 0 or 1
 * @param[out] ptColor point to the color info;
 * @return VOID.
 */
VOID Hv_Cal_DpRx_GetVscValue(UCHAR8 ucPortId, DpRxVscClolor *pstVscColor);

/**
 * @brief Get SDP status.
 * @param[in] ucPortId: port index 0 or 1
 * @return BOOL: HV_TRUE good, HV_FALSE error.
 */
BOOL Hv_Cal_DpRx_GetSdpStatus(UCHAR8 ucPortId);

/**
 * @brief Set default color.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] bDefaultColor: True or False
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetDefaultColor(UCHAR8 ucPortId, BOOL bDefaultColor);

/**
 * @brief Set Rx configration when timng stable.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] uwFreqKHz piexl clock;
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetTriggerPos(UCHAR8 ucPortId, UINT32 uiFreqKHz);

/**
 * @brief Get audio state.
 * @param[in] ucPortId: port index 0 or 1
 * @return BOOL, HV_TRUE:audio state ok,HV_FALSE:audio state abnormal.
 */
BOOL Hv_Cal_DpRx_GetAudioSta(UCHAR8 ucPortId);

/**
 * @brief Get sdp fifo packet count.
 * @param[in] ucPortId: port index 0 or 1
 * @return UCHAR8, packet count.
 */
UCHAR8 Hv_Cal_DpRx_GetFifoDepth(UCHAR8 ucPortId);

/**
 * @brief Read fifo once.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_ReadFifo(UCHAR8 ucPortId);

/**
 * @brief Get sdp type.
 * @param[in] ucPortId: port index 0 or 1
 * @return UCHAR8, sdp type(HDR/SPD).
 */
UCHAR8 Hv_Cal_DpRx_GetSdpType(UCHAR8 ucPortId);

/**
 * @brief Get audio state.
 * @param[in] ucPortId: port index 0 or 1
 * @return BOOL, HV_TRUE:audio state ok,HV_FALSE:audio state abnormal.
 */
VOID Hv_Cal_DpRx_ClrSdpFifo(UCHAR8 ucPortId);

/**
 * @brief Get interlace flag.
 * @param[in] ucPortId: port index 0 or 1
 * @return HV_TRUE: interlace, HV_FALSE:progress.
 */
BOOL Hv_Cal_DpRx_GetInterlaceFlag(UCHAR8 ucPortId);

/**
 * @brief Get video flag.
 * @param[in] ucPortId: port index 0 or 1
 * @return HV_TRUE: video, HV_FALSE: no video.
 */
BOOL Hv_Cal_DpRx_GetVideoFlag(UCHAR8 ucPortId);

/**
 * @brief Get Audio flag.
 * @param[in] ucPortId: port index 0 or 1
 * @return HV_TRUE: Audio, HV_FALSE: no Audio.
 */
BOOL Hv_Cal_DpRx_GetAudioFlag(UCHAR8 ucPortId);
/**
 * @brief Get port mux.
 * @param[in] ucPortId: port index 0 or 1
 * @param[out] ptColor point to the port mux;
 * @return MuxMatrix.
 */
UCHAR8 Hv_Cal_DpRx_GetPortMux(VOID);

/**
 * @brief Set audio valid thro.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] uiAudVld: audio vld value
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetAudVldThro(UCHAR8 ucPortId, UINT32 uiAudVld);

/**
 * @brief Get audio information.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] *uiVtotalCnt: vtotal by lane clk
 * @param[in] *uiStreamCnt: pcm cnt per frame
 * @param[in] *ucAudioCh: audio channel
 * @return VOID.
 */
VOID Hv_Cal_DpRx_GetAudioInfo(UCHAR8 ucPortId, UINT32 *uiVtotalCnt, UINT32 *uiStreamCnt, UCHAR8 *ucAudioCh);

/**
 * @brief Set audio channel.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] ucAudioCh: audio channel
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetAudioCh(UCHAR8 ucPortId, UCHAR8 ucAudioCh);

/**
 * @brief mccs on/off.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] 1: enable, 0 disable
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MccsEnable(UCHAR8 ucPortId, BOOL bEnable);

/**
 * @brief mccs command prepared.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] len reply data length
 * @return VOID.
 */
VOID Hv_Cal_DpRx_MccsReady(UCHAR8 ucPortId, UCHAR8 ucLen);

/**
 * @brief Config DPRX Aux polarity and Lane polarity.
 * @param[in] ucPortId: port index 0 or 1
 * @param[in] ucOrientation: 0 Norm, 1 Reverse
 * @param[in] ucPinAssignment: C for 0, 1 for D, E for 2
 * @param[in] ucDpLane0: real lane num for lane0
 * @param[in] ucDpLane1: real lane num for lane1
 * @param[in] ucDpLane2: real lane num for lane2
 * @param[in] ucDpLane3: real lane num for lane3
 * @param[in] ucAuxPol: 0 Norm, 1 Reverse
 * @param[in] ucLanePol
 * @return VOID.
 */
VOID Hv_Cal_DpRx_SetTypecOrientation(UCHAR8 ucPortId, UCHAR8 ucOrientation, UCHAR8 ucPinAssignment,
            UCHAR8 ucDpLane0, UCHAR8 ucDpLane1, UCHAR8 ucDpLane2, UCHAR8 ucDpLane3, UCHAR8 ucAuxPol, UCHAR8 ucLanePol);

/**
 * @brief Config DPRX Audio Stop.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_AudioStop(UCHAR8 ucPortId);

/**
 * @brief Config DPRX Audio Start.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_AudioStart(UCHAR8 ucPortId);

/**
 * @brief Check DPRX Audio ready.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_AudioCheck(UCHAR8 ucPortId);

/**
 * @brief Get frame count.
 * @param[in] ucPortId: port index 0 or 1
 * @return UINT32, frame count.
 */
UINT32 Hv_Cal_DpRx_GetFrameCnt(UCHAR8 ucPortId);

/**
 * @brief Reset DP.
 * @param[in] ucPortId: port index 0 or 1
 * @return VOID.
 */
VOID Hv_Cal_DpRx_Reset(UCHAR8 ucPortId, BOOL bEn);

/**
 * @brief Enable DP Aux write.
 * @param[in] bEn
 * @return VOID.
 */
VOID Hv_Cal_DpRx_EnableApbWr(BOOL bEn);

/**
 * @brief Get Dp AuxN State.
 * @param[in] ucBit: GPIO bit
 * @return BOOL, HV_TRUE for level high
 */
BOOL Hv_Cal_DpRx_GetAuxState(UCHAR8 ucBit);

#endif /* __HV_CAL_DPRX_H__ */

