#ifndef _HV_PAGE_HT7315_HDMI_RX_HDCP1X2X_01_H_
#define _HV_PAGE_HT7315_HDMI_RX_HDCP1X2X_01_H_

#ifndef HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS
    #define HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS                                         0x1104E600
#endif


#define RX_HDMI_RX_HDCP1X2X_01_00                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x00)

#define RX_HDMI_RX_HDCP1X2X_01_00_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_00

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_00  rs_rx_hdmi_rx_hdcp1x2x_01_00;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_00 {
    unsigned int reg_01_hdmirx_hdcp1x_bksv_0                : 8;
    unsigned int reg_01_hdmirx_hdcp1x_bksv_1                : 8;
    unsigned int reg_01_hdmirx_hdcp1x_bksv_2                : 8;
    unsigned int reg_01_hdmirx_hdcp1x_bksv_3                : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_00(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_00*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_04                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x04)

#define RX_HDMI_RX_HDCP1X2X_01_04_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_04

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_04  rs_rx_hdmi_rx_hdcp1x2x_01_04;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_04 {
    unsigned int reg_01_hdmirx_hdcp1x_bksv_4                : 8;
    unsigned int reserved                                   :24;
};
#define rx_hdmi_rx_hdcp1x2x_01_04(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_04*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_08                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x08)

#define RX_HDMI_RX_HDCP1X2X_01_08_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_08

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_08  rs_rx_hdmi_rx_hdcp1x2x_01_08;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_08 {
    unsigned int reg_01_hdmirx_hdcp1x_r0_0                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_r0_1                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_rj_0                  : 8;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_08(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_08*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_10                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x10)

#define RX_HDMI_RX_HDCP1X2X_01_10_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_10

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_10  rs_rx_hdmi_rx_hdcp1x2x_01_10;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_10 {
    unsigned int reg_01_hdmirx_hdcp1x_aksv_0                : 8;
    unsigned int reg_01_hdmirx_hdcp1x_aksv_1                : 8;
    unsigned int reg_01_hdmirx_hdcp1x_aksv_2                : 8;
    unsigned int reg_01_hdmirx_hdcp1x_aksv_3                : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_10(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_10*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_14                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x14)

#define RX_HDMI_RX_HDCP1X2X_01_14_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_14

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_14  rs_rx_hdmi_rx_hdcp1x2x_01_14;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_14 {
    unsigned int reg_01_hdmirx_hdcp1x_aksv_4                : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ainfo                 : 8;
    unsigned int reserved                                   :16;
};
#define rx_hdmi_rx_hdcp1x2x_01_14(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_14*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_18                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x18)

#define RX_HDMI_RX_HDCP1X2X_01_18_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_18

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_18  rs_rx_hdmi_rx_hdcp1x2x_01_18;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_18 {
    unsigned int reg_01_hdmirx_hdcp1x_an_0                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_an_1                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_an_2                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_an_3                  : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_18(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_18*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_1C                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x1C)

#define RX_HDMI_RX_HDCP1X2X_01_1C_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_1c

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_1c  rs_rx_hdmi_rx_hdcp1x2x_01_1c;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_1c {
    unsigned int reg_01_hdmirx_hdcp1x_an_4                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_an_5                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_an_6                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_an_7                  : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_1c(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_1c*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_20                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x20)

#define RX_HDMI_RX_HDCP1X2X_01_20_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_20

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_20  rs_rx_hdmi_rx_hdcp1x2x_01_20;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_20 {
    unsigned int reg_01_hdmirx_hdcp1x_vh_0                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_1                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_2                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_3                  : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_20(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_20*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_24                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x24)

#define RX_HDMI_RX_HDCP1X2X_01_24_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_24

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_24  rs_rx_hdmi_rx_hdcp1x2x_01_24;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_24 {
    unsigned int reg_01_hdmirx_hdcp1x_vh_4                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_5                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_6                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_7                  : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_24(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_24*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_28                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x28)

#define RX_HDMI_RX_HDCP1X2X_01_28_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_28

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_28  rs_rx_hdmi_rx_hdcp1x2x_01_28;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_28 {
    unsigned int reg_01_hdmirx_hdcp1x_vh_8                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_9                  : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_10                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_11                 : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_28(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_28*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_2C                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x2C)

#define RX_HDMI_RX_HDCP1X2X_01_2C_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_2c

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_2c  rs_rx_hdmi_rx_hdcp1x2x_01_2c;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_2c {
    unsigned int reg_01_hdmirx_hdcp1x_vh_12                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_13                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_14                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_15                 : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_2c(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_2c*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_30                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x30)

#define RX_HDMI_RX_HDCP1X2X_01_30_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_30

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_30  rs_rx_hdmi_rx_hdcp1x2x_01_30;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_30 {
    unsigned int reg_01_hdmirx_hdcp1x_vh_16                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_17                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_18                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_vh_19                 : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_30(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_30*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_40                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x40)

#define RX_HDMI_RX_HDCP1X2X_01_40_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_40

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_40  rs_rx_hdmi_rx_hdcp1x2x_01_40;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_40 {
    unsigned int reg_01_hdmirx_hdcp1x_bcaps                 : 8;
    unsigned int reg_01_hdmirx_hdcp1x_bstatus_0             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_bstatus_1             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_0             : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_40(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_40*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_44                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x44)

#define RX_HDMI_RX_HDCP1X2X_01_44_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_44

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_44  rs_rx_hdmi_rx_hdcp1x2x_01_44;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_44 {
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_1             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_2             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_3             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_4             : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_44(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_44*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_48                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x48)

#define RX_HDMI_RX_HDCP1X2X_01_48_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_48

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_48  rs_rx_hdmi_rx_hdcp1x2x_01_48;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_48 {
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_5             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_6             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_7             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_8             : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_48(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_48*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_4C                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x4C)

#define RX_HDMI_RX_HDCP1X2X_01_4C_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_4c

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_4c  rs_rx_hdmi_rx_hdcp1x2x_01_4c;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_4c {
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_9             : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_10            : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_11            : 8;
    unsigned int reg_01_hdmirx_hdcp1x_ksvfifo_12            : 8;
};
#define rx_hdmi_rx_hdcp1x2x_01_4c(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_4c*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_50                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x50)

#define RX_HDMI_RX_HDCP1X2X_01_50_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_50

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_50  rs_rx_hdmi_rx_hdcp1x2x_01_50;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_50 {
    unsigned int reg_01_hdmirx_hdcp2x_version               : 8;
    unsigned int reserved                                   :24;
};
#define rx_hdmi_rx_hdcp1x2x_01_50(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_50*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_60                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x60)

#define RX_HDMI_RX_HDCP1X2X_01_60_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_60

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_60  rs_rx_hdmi_rx_hdcp1x2x_01_60;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_60 {
    unsigned int reg_01_hdmirx_hdcp2x_write_message         : 8;
    unsigned int reg_01_hw_auto_update_70_en                : 1;
    unsigned int reg_01_1x_ri_sel                           : 1;
    unsigned int reserved                                   :22;
};
#define rx_hdmi_rx_hdcp1x2x_01_60(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_60*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_70                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x70)

#define RX_HDMI_RX_HDCP1X2X_01_70_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_70

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_70  rs_rx_hdmi_rx_hdcp1x2x_01_70;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_70 {
    unsigned int reg_01_hdmirx_hdcp2x_rxstatus              :16;
    unsigned int reserved                                   :16;
};
#define rx_hdmi_rx_hdcp1x2x_01_70(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_70*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_80                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x80)

#define RX_HDMI_RX_HDCP1X2X_01_80_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_80

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_80  rs_rx_hdmi_rx_hdcp1x2x_01_80;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_80 {
    unsigned int reg_01_hdmirx_hdcp2x_read_message          : 8;
    unsigned int reserved                                   :24;
};
#define rx_hdmi_rx_hdcp1x2x_01_80(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_80*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_84                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0x84)

#define RX_HDMI_RX_HDCP1X2X_01_84_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_84

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_84  rs_rx_hdmi_rx_hdcp1x2x_01_84;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_84 {
    unsigned int reg_01_hdmirx_hdcp2x_message_id            : 8;
    unsigned int reserved                                   :24;
};
#define rx_hdmi_rx_hdcp1x2x_01_84(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_84*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_C0                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xC0)

#define RX_HDMI_RX_HDCP1X2X_01_C0_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_c0

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_c0  rs_rx_hdmi_rx_hdcp1x2x_01_c0;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_c0 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg0                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_c0(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_c0*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_C4                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xC4)

#define RX_HDMI_RX_HDCP1X2X_01_C4_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_c4

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_c4  rs_rx_hdmi_rx_hdcp1x2x_01_c4;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_c4 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg1                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_c4(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_c4*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_C8                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xC8)

#define RX_HDMI_RX_HDCP1X2X_01_C8_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_c8

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_c8  rs_rx_hdmi_rx_hdcp1x2x_01_c8;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_c8 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg2                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_c8(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_c8*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_CC                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xCC)

#define RX_HDMI_RX_HDCP1X2X_01_CC_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_cc

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_cc  rs_rx_hdmi_rx_hdcp1x2x_01_cc;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_cc {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg3                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_cc(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_cc*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_D0                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xD0)

#define RX_HDMI_RX_HDCP1X2X_01_D0_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_d0

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_d0  rs_rx_hdmi_rx_hdcp1x2x_01_d0;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_d0 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg4                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_d0(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_d0*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_D4                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xD4)

#define RX_HDMI_RX_HDCP1X2X_01_D4_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_d4

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_d4  rs_rx_hdmi_rx_hdcp1x2x_01_d4;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_d4 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg5                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_d4(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_d4*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_D8                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xD8)

#define RX_HDMI_RX_HDCP1X2X_01_D8_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_d8

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_d8  rs_rx_hdmi_rx_hdcp1x2x_01_d8;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_d8 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg6                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_d8(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_d8*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_DC                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xDC)

#define RX_HDMI_RX_HDCP1X2X_01_DC_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_dc

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_dc  rs_rx_hdmi_rx_hdcp1x2x_01_dc;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_dc {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg7                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_dc(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_dc*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_E0                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xE0)

#define RX_HDMI_RX_HDCP1X2X_01_E0_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_e0

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_e0  rs_rx_hdmi_rx_hdcp1x2x_01_e0;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_e0 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg8                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_e0(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_e0*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_E4                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xE4)

#define RX_HDMI_RX_HDCP1X2X_01_E4_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_e4

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_e4  rs_rx_hdmi_rx_hdcp1x2x_01_e4;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_e4 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg9                :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_e4(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_e4*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_E8                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xE8)

#define RX_HDMI_RX_HDCP1X2X_01_E8_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_e8

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_e8  rs_rx_hdmi_rx_hdcp1x2x_01_e8;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_e8 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg10               :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_e8(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_e8*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_EC                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xEC)

#define RX_HDMI_RX_HDCP1X2X_01_EC_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_ec

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_ec  rs_rx_hdmi_rx_hdcp1x2x_01_ec;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_ec {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg11               :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_ec(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_ec*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_F0                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xF0)

#define RX_HDMI_RX_HDCP1X2X_01_F0_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_f0

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_f0  rs_rx_hdmi_rx_hdcp1x2x_01_f0;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_f0 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg12               :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_f0(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_f0*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_F4                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xF4)

#define RX_HDMI_RX_HDCP1X2X_01_F4_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_f4

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_f4  rs_rx_hdmi_rx_hdcp1x2x_01_f4;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_f4 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg13               :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_f4(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_f4*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_F8                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xF8)

#define RX_HDMI_RX_HDCP1X2X_01_F8_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_f8

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_f8  rs_rx_hdmi_rx_hdcp1x2x_01_f8;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_f8 {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg14               :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_f8(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_f8*)&(val))



#define RX_HDMI_RX_HDCP1X2X_01_FC                                        (HV_HDMI_RX_HDCP1X2X_01_BASE_ADDRESS + 0xFC)

#define RX_HDMI_RX_HDCP1X2X_01_FC_struct                                 rs_rx_hdmi_rx_hdcp1x2x_01_fc

typedef struct _rs_rx_hdmi_rx_hdcp1x2x_01_fc  rs_rx_hdmi_rx_hdcp1x2x_01_fc;
struct _rs_rx_hdmi_rx_hdcp1x2x_01_fc {
    unsigned int reg_01_hdmirx_hdcp1x2x_dbg15               :32;
};
#define rx_hdmi_rx_hdcp1x2x_01_fc(val) ((rs_rx_hdmi_rx_hdcp1x2x_01_fc*)&(val))



#endif