#ifndef _HV_PAGE_HT7315_GPIO0_H_
#define _HV_PAGE_HT7315_GPIO0_H_

#ifndef HV_GPIO0_BASE_ADDRESS
    #define HV_GPIO0_BASE_ADDRESS                                         0x11086000
#endif


#define CPU_SYS_GPIO0_GPIO_TRG_MODE_0                                    (HV_GPIO0_BASE_ADDRESS + 0x000)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_0_struct                             rs_cpu_sys_gpio0_gpio_trg_mode_0

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_0  rs_cpu_sys_gpio0_gpio_trg_mode_0;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_0 {
    unsigned int gpio_trg_mode_0                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_0(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_0*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_1                                    (HV_GPIO0_BASE_ADDRESS + 0x004)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_1_struct                             rs_cpu_sys_gpio0_gpio_trg_mode_1

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_1  rs_cpu_sys_gpio0_gpio_trg_mode_1;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_1 {
    unsigned int gpio_trg_mode_1                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_1(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_1*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_2                                    (HV_GPIO0_BASE_ADDRESS + 0x008)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_2_struct                             rs_cpu_sys_gpio0_gpio_trg_mode_2

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_2  rs_cpu_sys_gpio0_gpio_trg_mode_2;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_2 {
    unsigned int gpio_trg_mode_2                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_2(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_2*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_3                                    (HV_GPIO0_BASE_ADDRESS + 0x00C)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_3_struct                             rs_cpu_sys_gpio0_gpio_trg_mode_3

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_3  rs_cpu_sys_gpio0_gpio_trg_mode_3;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_3 {
    unsigned int gpio_trg_mode_3                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_3(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_3*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_4                                    (HV_GPIO0_BASE_ADDRESS + 0x010)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_4_struct                             rs_cpu_sys_gpio0_gpio_trg_mode_4

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_4  rs_cpu_sys_gpio0_gpio_trg_mode_4;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_4 {
    unsigned int gpio_trg_mode_4                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_4(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_4*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_5                                    (HV_GPIO0_BASE_ADDRESS + 0x014)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_5_struct                             rs_cpu_sys_gpio0_gpio_trg_mode_5

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_5  rs_cpu_sys_gpio0_gpio_trg_mode_5;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_5 {
    unsigned int gpio_trg_mode_5                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_5(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_5*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE0_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x018)

#define CPU_SYS_GPIO0_GPIO_OE0_SET_struct                                rs_cpu_sys_gpio0_gpio_oe0_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe0_set  rs_cpu_sys_gpio0_gpio_oe0_set;
struct _rs_cpu_sys_gpio0_gpio_oe0_set {
    unsigned int gpio0_oe_set                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe0_set(val) ((rs_cpu_sys_gpio0_gpio_oe0_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE1_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x01C)

#define CPU_SYS_GPIO0_GPIO_OE1_SET_struct                                rs_cpu_sys_gpio0_gpio_oe1_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe1_set  rs_cpu_sys_gpio0_gpio_oe1_set;
struct _rs_cpu_sys_gpio0_gpio_oe1_set {
    unsigned int gpio1_oe_set                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe1_set(val) ((rs_cpu_sys_gpio0_gpio_oe1_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT0_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x020)

#define CPU_SYS_GPIO0_GPIO_OUT0_SET_struct                               rs_cpu_sys_gpio0_gpio_out0_set

typedef struct _rs_cpu_sys_gpio0_gpio_out0_set  rs_cpu_sys_gpio0_gpio_out0_set;
struct _rs_cpu_sys_gpio0_gpio_out0_set {
    unsigned int gpio0_out_set                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out0_set(val) ((rs_cpu_sys_gpio0_gpio_out0_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT1_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x024)

#define CPU_SYS_GPIO0_GPIO_OUT1_SET_struct                               rs_cpu_sys_gpio0_gpio_out1_set

typedef struct _rs_cpu_sys_gpio0_gpio_out1_set  rs_cpu_sys_gpio0_gpio_out1_set;
struct _rs_cpu_sys_gpio0_gpio_out1_set {
    unsigned int gpio1_out_set                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out1_set(val) ((rs_cpu_sys_gpio0_gpio_out1_set*)&(val))



#define CPU_SYS_GPIO0_IN                                                 (HV_GPIO0_BASE_ADDRESS + 0x028)

#define CPU_SYS_GPIO0_IN_struct                                          rs_cpu_sys_gpio0_in

typedef struct _rs_cpu_sys_gpio0_in  rs_cpu_sys_gpio0_in;
struct _rs_cpu_sys_gpio0_in {
    unsigned int gpio0_in                                   :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_in(val) ((rs_cpu_sys_gpio0_in*)&(val))



#define CPU_SYS_GPIO0_GPIO1_IN                                           (HV_GPIO0_BASE_ADDRESS + 0x02C)

#define CPU_SYS_GPIO0_GPIO1_IN_struct                                    rs_cpu_sys_gpio0_gpio1_in

typedef struct _rs_cpu_sys_gpio0_gpio1_in  rs_cpu_sys_gpio0_gpio1_in;
struct _rs_cpu_sys_gpio0_gpio1_in {
    unsigned int gpio1_in                                   :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio1_in(val) ((rs_cpu_sys_gpio0_gpio1_in*)&(val))



#define CPU_SYS_GPIO0_INT_MASK                                           (HV_GPIO0_BASE_ADDRESS + 0x030)

#define CPU_SYS_GPIO0_INT_MASK_struct                                    rs_cpu_sys_gpio0_int_mask

typedef struct _rs_cpu_sys_gpio0_int_mask  rs_cpu_sys_gpio0_int_mask;
struct _rs_cpu_sys_gpio0_int_mask {
    unsigned int gpio0_int_mask                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_int_mask(val) ((rs_cpu_sys_gpio0_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO1_INT_MASK                                     (HV_GPIO0_BASE_ADDRESS + 0x034)

#define CPU_SYS_GPIO0_GPIO1_INT_MASK_struct                              rs_cpu_sys_gpio0_gpio1_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio1_int_mask  rs_cpu_sys_gpio0_gpio1_int_mask;
struct _rs_cpu_sys_gpio0_gpio1_int_mask {
    unsigned int gpio1_int_mask                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio1_int_mask(val) ((rs_cpu_sys_gpio0_gpio1_int_mask*)&(val))



#define CPU_SYS_GPIO0_INT_CLR                                            (HV_GPIO0_BASE_ADDRESS + 0x038)

#define CPU_SYS_GPIO0_INT_CLR_struct                                     rs_cpu_sys_gpio0_int_clr

typedef struct _rs_cpu_sys_gpio0_int_clr  rs_cpu_sys_gpio0_int_clr;
struct _rs_cpu_sys_gpio0_int_clr {
    unsigned int gpio0_int_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_int_clr(val) ((rs_cpu_sys_gpio0_int_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO1_INT_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x03C)

#define CPU_SYS_GPIO0_GPIO1_INT_CLR_struct                               rs_cpu_sys_gpio0_gpio1_int_clr

typedef struct _rs_cpu_sys_gpio0_gpio1_int_clr  rs_cpu_sys_gpio0_gpio1_int_clr;
struct _rs_cpu_sys_gpio0_gpio1_int_clr {
    unsigned int gpio1_int_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio1_int_clr(val) ((rs_cpu_sys_gpio0_gpio1_int_clr*)&(val))



#define CPU_SYS_GPIO0_PULSE_DETECT_INT_STATE                             (HV_GPIO0_BASE_ADDRESS + 0x040)

#define CPU_SYS_GPIO0_PULSE_DETECT_INT_STATE_struct                      rs_cpu_sys_gpio0_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_pulse_detect_int_state  rs_cpu_sys_gpio0_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_pulse_detect_int_state {
    unsigned int gpio0_pulse_detect_int_state               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO1_PULSE_DETECT_INT_STATE                       (HV_GPIO0_BASE_ADDRESS + 0x044)

#define CPU_SYS_GPIO0_GPIO1_PULSE_DETECT_INT_STATE_struct                rs_cpu_sys_gpio0_gpio1_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_gpio1_pulse_detect_int_state  rs_cpu_sys_gpio0_gpio1_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_gpio1_pulse_detect_int_state {
    unsigned int gpio1_pulse_detect_int_state               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio1_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_gpio1_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO_ALL_INT_MASK                                  (HV_GPIO0_BASE_ADDRESS + 0x048)

#define CPU_SYS_GPIO0_GPIO_ALL_INT_MASK_struct                           rs_cpu_sys_gpio0_gpio_all_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio_all_int_mask  rs_cpu_sys_gpio0_gpio_all_int_mask;
struct _rs_cpu_sys_gpio0_gpio_all_int_mask {
    unsigned int gpio_all_int_mask                          : 1;
    unsigned int gpio_all_int_clr_en                        : 1;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_all_int_mask(val) ((rs_cpu_sys_gpio0_gpio_all_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE0_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x04C)

#define CPU_SYS_GPIO0_GPIO_OE0_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe0_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe0_clr  rs_cpu_sys_gpio0_gpio_oe0_clr;
struct _rs_cpu_sys_gpio0_gpio_oe0_clr {
    unsigned int gpio0_oe_clr                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe0_clr(val) ((rs_cpu_sys_gpio0_gpio_oe0_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE1_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x050)

#define CPU_SYS_GPIO0_GPIO_OE1_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe1_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe1_clr  rs_cpu_sys_gpio0_gpio_oe1_clr;
struct _rs_cpu_sys_gpio0_gpio_oe1_clr {
    unsigned int gpio1_oe_clr                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe1_clr(val) ((rs_cpu_sys_gpio0_gpio_oe1_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT0_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x054)

#define CPU_SYS_GPIO0_GPIO_OUT0_CLR_struct                               rs_cpu_sys_gpio0_gpio_out0_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out0_clr  rs_cpu_sys_gpio0_gpio_out0_clr;
struct _rs_cpu_sys_gpio0_gpio_out0_clr {
    unsigned int gpio0_out_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out0_clr(val) ((rs_cpu_sys_gpio0_gpio_out0_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT1_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x058)

#define CPU_SYS_GPIO0_GPIO_OUT1_CLR_struct                               rs_cpu_sys_gpio0_gpio_out1_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out1_clr  rs_cpu_sys_gpio0_gpio_out1_clr;
struct _rs_cpu_sys_gpio0_gpio_out1_clr {
    unsigned int gpio1_out_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out1_clr(val) ((rs_cpu_sys_gpio0_gpio_out1_clr*)&(val))



#define CPU_SYS_GPIO0_OUT_STATE                                          (HV_GPIO0_BASE_ADDRESS + 0x060)

#define CPU_SYS_GPIO0_OUT_STATE_struct                                   rs_cpu_sys_gpio0_out_state

typedef struct _rs_cpu_sys_gpio0_out_state  rs_cpu_sys_gpio0_out_state;
struct _rs_cpu_sys_gpio0_out_state {
    unsigned int gpio0_out_state                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_out_state(val) ((rs_cpu_sys_gpio0_out_state*)&(val))



#define CPU_SYS_GPIO0_GPIO1_OUT_STATE                                    (HV_GPIO0_BASE_ADDRESS + 0x064)

#define CPU_SYS_GPIO0_GPIO1_OUT_STATE_struct                             rs_cpu_sys_gpio0_gpio1_out_state

typedef struct _rs_cpu_sys_gpio0_gpio1_out_state  rs_cpu_sys_gpio0_gpio1_out_state;
struct _rs_cpu_sys_gpio0_gpio1_out_state {
    unsigned int gpio1_out_state                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio1_out_state(val) ((rs_cpu_sys_gpio0_gpio1_out_state*)&(val))



#define CPU_SYS_GPIO0_OE_STATE                                           (HV_GPIO0_BASE_ADDRESS + 0x068)

#define CPU_SYS_GPIO0_OE_STATE_struct                                    rs_cpu_sys_gpio0_oe_state

typedef struct _rs_cpu_sys_gpio0_oe_state  rs_cpu_sys_gpio0_oe_state;
struct _rs_cpu_sys_gpio0_oe_state {
    unsigned int gpio0_oe_state                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_oe_state(val) ((rs_cpu_sys_gpio0_oe_state*)&(val))



#define CPU_SYS_GPIO0_GPIO1_OE_STATE                                     (HV_GPIO0_BASE_ADDRESS + 0x06C)

#define CPU_SYS_GPIO0_GPIO1_OE_STATE_struct                              rs_cpu_sys_gpio0_gpio1_oe_state

typedef struct _rs_cpu_sys_gpio0_gpio1_oe_state  rs_cpu_sys_gpio0_gpio1_oe_state;
struct _rs_cpu_sys_gpio0_gpio1_oe_state {
    unsigned int gpio1_oe_state                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio1_oe_state(val) ((rs_cpu_sys_gpio0_gpio1_oe_state*)&(val))



#define CPU_SYS_GPIO0_DEBOUNCE_EN                                        (HV_GPIO0_BASE_ADDRESS + 0x0FC)

#define CPU_SYS_GPIO0_DEBOUNCE_EN_struct                                 rs_cpu_sys_gpio0_debounce_en

typedef struct _rs_cpu_sys_gpio0_debounce_en  rs_cpu_sys_gpio0_debounce_en;
struct _rs_cpu_sys_gpio0_debounce_en {
    unsigned int debounce_en                                : 1;
    unsigned int reserved                                   : 3;
    unsigned int deglitch_capacity                          :20;
    unsigned int reserved_1                                 : 8;
};
#define cpu_sys_gpio0_debounce_en(val) ((rs_cpu_sys_gpio0_debounce_en*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_10                                   (HV_GPIO0_BASE_ADDRESS + 0x100)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_10_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_10

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_10  rs_cpu_sys_gpio0_gpio_trg_mode_10;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_10 {
    unsigned int gpio_trg_mode_10                           :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_10(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_10*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_11                                   (HV_GPIO0_BASE_ADDRESS + 0x104)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_11_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_11

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_11  rs_cpu_sys_gpio0_gpio_trg_mode_11;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_11 {
    unsigned int gpio_trg_mode_11                           :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_11(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_11*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_12                                   (HV_GPIO0_BASE_ADDRESS + 0x108)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_12_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_12

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_12  rs_cpu_sys_gpio0_gpio_trg_mode_12;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_12 {
    unsigned int gpio_trg_mode_12                           :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_12(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_12*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_13                                   (HV_GPIO0_BASE_ADDRESS + 0x10C)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_13_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_13

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_13  rs_cpu_sys_gpio0_gpio_trg_mode_13;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_13 {
    unsigned int gpio_trg_mode_13                           :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_13(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_13*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_14                                   (HV_GPIO0_BASE_ADDRESS + 0x110)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_14_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_14

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_14  rs_cpu_sys_gpio0_gpio_trg_mode_14;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_14 {
    unsigned int gpio_trg_mode_14                           :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_14(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_14*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_15                                   (HV_GPIO0_BASE_ADDRESS + 0x114)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_15_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_15

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_15  rs_cpu_sys_gpio0_gpio_trg_mode_15;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_15 {
    unsigned int gpio_trg_mode_15                           :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_trg_mode_15(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_15*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE2_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x118)

#define CPU_SYS_GPIO0_GPIO_OE2_SET_struct                                rs_cpu_sys_gpio0_gpio_oe2_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe2_set  rs_cpu_sys_gpio0_gpio_oe2_set;
struct _rs_cpu_sys_gpio0_gpio_oe2_set {
    unsigned int gpio2_oe_set                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe2_set(val) ((rs_cpu_sys_gpio0_gpio_oe2_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE3_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x11C)

#define CPU_SYS_GPIO0_GPIO_OE3_SET_struct                                rs_cpu_sys_gpio0_gpio_oe3_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe3_set  rs_cpu_sys_gpio0_gpio_oe3_set;
struct _rs_cpu_sys_gpio0_gpio_oe3_set {
    unsigned int gpio3_oe_set                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe3_set(val) ((rs_cpu_sys_gpio0_gpio_oe3_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT2_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x120)

#define CPU_SYS_GPIO0_GPIO_OUT2_SET_struct                               rs_cpu_sys_gpio0_gpio_out2_set

typedef struct _rs_cpu_sys_gpio0_gpio_out2_set  rs_cpu_sys_gpio0_gpio_out2_set;
struct _rs_cpu_sys_gpio0_gpio_out2_set {
    unsigned int gpio2_out_set                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out2_set(val) ((rs_cpu_sys_gpio0_gpio_out2_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT3_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x124)

#define CPU_SYS_GPIO0_GPIO_OUT3_SET_struct                               rs_cpu_sys_gpio0_gpio_out3_set

typedef struct _rs_cpu_sys_gpio0_gpio_out3_set  rs_cpu_sys_gpio0_gpio_out3_set;
struct _rs_cpu_sys_gpio0_gpio_out3_set {
    unsigned int gpio3_out_set                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out3_set(val) ((rs_cpu_sys_gpio0_gpio_out3_set*)&(val))



#define CPU_SYS_GPIO0_GPIO2_IN                                           (HV_GPIO0_BASE_ADDRESS + 0x128)

#define CPU_SYS_GPIO0_GPIO2_IN_struct                                    rs_cpu_sys_gpio0_gpio2_in

typedef struct _rs_cpu_sys_gpio0_gpio2_in  rs_cpu_sys_gpio0_gpio2_in;
struct _rs_cpu_sys_gpio0_gpio2_in {
    unsigned int gpio2_in                                   :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio2_in(val) ((rs_cpu_sys_gpio0_gpio2_in*)&(val))



#define CPU_SYS_GPIO0_GPIO3_IN                                           (HV_GPIO0_BASE_ADDRESS + 0x12C)

#define CPU_SYS_GPIO0_GPIO3_IN_struct                                    rs_cpu_sys_gpio0_gpio3_in

typedef struct _rs_cpu_sys_gpio0_gpio3_in  rs_cpu_sys_gpio0_gpio3_in;
struct _rs_cpu_sys_gpio0_gpio3_in {
    unsigned int gpio3_in                                   :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio3_in(val) ((rs_cpu_sys_gpio0_gpio3_in*)&(val))



#define CPU_SYS_GPIO0_GPIO2_INT_MASK                                     (HV_GPIO0_BASE_ADDRESS + 0x130)

#define CPU_SYS_GPIO0_GPIO2_INT_MASK_struct                              rs_cpu_sys_gpio0_gpio2_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio2_int_mask  rs_cpu_sys_gpio0_gpio2_int_mask;
struct _rs_cpu_sys_gpio0_gpio2_int_mask {
    unsigned int gpio2_int_mask                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio2_int_mask(val) ((rs_cpu_sys_gpio0_gpio2_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO3_INT_MASK                                     (HV_GPIO0_BASE_ADDRESS + 0x134)

#define CPU_SYS_GPIO0_GPIO3_INT_MASK_struct                              rs_cpu_sys_gpio0_gpio3_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio3_int_mask  rs_cpu_sys_gpio0_gpio3_int_mask;
struct _rs_cpu_sys_gpio0_gpio3_int_mask {
    unsigned int gpio3_int_mask                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio3_int_mask(val) ((rs_cpu_sys_gpio0_gpio3_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO2_INT_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x138)

#define CPU_SYS_GPIO0_GPIO2_INT_CLR_struct                               rs_cpu_sys_gpio0_gpio2_int_clr

typedef struct _rs_cpu_sys_gpio0_gpio2_int_clr  rs_cpu_sys_gpio0_gpio2_int_clr;
struct _rs_cpu_sys_gpio0_gpio2_int_clr {
    unsigned int gpio2_int_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio2_int_clr(val) ((rs_cpu_sys_gpio0_gpio2_int_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO3_INT_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x13C)

#define CPU_SYS_GPIO0_GPIO3_INT_CLR_struct                               rs_cpu_sys_gpio0_gpio3_int_clr

typedef struct _rs_cpu_sys_gpio0_gpio3_int_clr  rs_cpu_sys_gpio0_gpio3_int_clr;
struct _rs_cpu_sys_gpio0_gpio3_int_clr {
    unsigned int gpio3_int_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio3_int_clr(val) ((rs_cpu_sys_gpio0_gpio3_int_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO2_PULSE_DETECT_INT_STATE                       (HV_GPIO0_BASE_ADDRESS + 0x140)

#define CPU_SYS_GPIO0_GPIO2_PULSE_DETECT_INT_STATE_struct                rs_cpu_sys_gpio0_gpio2_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_gpio2_pulse_detect_int_state  rs_cpu_sys_gpio0_gpio2_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_gpio2_pulse_detect_int_state {
    unsigned int gpio2_pulse_detect_int_state               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio2_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_gpio2_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO3_PULSE_DETECT_INT_STATE                       (HV_GPIO0_BASE_ADDRESS + 0x144)

#define CPU_SYS_GPIO0_GPIO3_PULSE_DETECT_INT_STATE_struct                rs_cpu_sys_gpio0_gpio3_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_gpio3_pulse_detect_int_state  rs_cpu_sys_gpio0_gpio3_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_gpio3_pulse_detect_int_state {
    unsigned int gpio3_pulse_detect_int_state               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio3_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_gpio3_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE2_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x14C)

#define CPU_SYS_GPIO0_GPIO_OE2_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe2_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe2_clr  rs_cpu_sys_gpio0_gpio_oe2_clr;
struct _rs_cpu_sys_gpio0_gpio_oe2_clr {
    unsigned int gpio2_oe_clr                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe2_clr(val) ((rs_cpu_sys_gpio0_gpio_oe2_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE3_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x150)

#define CPU_SYS_GPIO0_GPIO_OE3_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe3_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe3_clr  rs_cpu_sys_gpio0_gpio_oe3_clr;
struct _rs_cpu_sys_gpio0_gpio_oe3_clr {
    unsigned int gpio3_oe_clr                               :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_oe3_clr(val) ((rs_cpu_sys_gpio0_gpio_oe3_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT2_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x154)

#define CPU_SYS_GPIO0_GPIO_OUT2_CLR_struct                               rs_cpu_sys_gpio0_gpio_out2_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out2_clr  rs_cpu_sys_gpio0_gpio_out2_clr;
struct _rs_cpu_sys_gpio0_gpio_out2_clr {
    unsigned int gpio2_out_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out2_clr(val) ((rs_cpu_sys_gpio0_gpio_out2_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT3_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x158)

#define CPU_SYS_GPIO0_GPIO_OUT3_CLR_struct                               rs_cpu_sys_gpio0_gpio_out3_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out3_clr  rs_cpu_sys_gpio0_gpio_out3_clr;
struct _rs_cpu_sys_gpio0_gpio_out3_clr {
    unsigned int gpio3_out_clr                              :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio_out3_clr(val) ((rs_cpu_sys_gpio0_gpio_out3_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO2_OUT_STATE                                    (HV_GPIO0_BASE_ADDRESS + 0x160)

#define CPU_SYS_GPIO0_GPIO2_OUT_STATE_struct                             rs_cpu_sys_gpio0_gpio2_out_state

typedef struct _rs_cpu_sys_gpio0_gpio2_out_state  rs_cpu_sys_gpio0_gpio2_out_state;
struct _rs_cpu_sys_gpio0_gpio2_out_state {
    unsigned int gpio2_out_state                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio2_out_state(val) ((rs_cpu_sys_gpio0_gpio2_out_state*)&(val))



#define CPU_SYS_GPIO0_GPIO3_OUT_STATE                                    (HV_GPIO0_BASE_ADDRESS + 0x164)

#define CPU_SYS_GPIO0_GPIO3_OUT_STATE_struct                             rs_cpu_sys_gpio0_gpio3_out_state

typedef struct _rs_cpu_sys_gpio0_gpio3_out_state  rs_cpu_sys_gpio0_gpio3_out_state;
struct _rs_cpu_sys_gpio0_gpio3_out_state {
    unsigned int gpio3_out_state                            :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio3_out_state(val) ((rs_cpu_sys_gpio0_gpio3_out_state*)&(val))



#define CPU_SYS_GPIO0_GPIO2_OE_STATE                                     (HV_GPIO0_BASE_ADDRESS + 0x168)

#define CPU_SYS_GPIO0_GPIO2_OE_STATE_struct                              rs_cpu_sys_gpio0_gpio2_oe_state

typedef struct _rs_cpu_sys_gpio0_gpio2_oe_state  rs_cpu_sys_gpio0_gpio2_oe_state;
struct _rs_cpu_sys_gpio0_gpio2_oe_state {
    unsigned int gpio2_oe_state                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio2_oe_state(val) ((rs_cpu_sys_gpio0_gpio2_oe_state*)&(val))



#define CPU_SYS_GPIO0_GPIO3_OE_STATE                                     (HV_GPIO0_BASE_ADDRESS + 0x16C)

#define CPU_SYS_GPIO0_GPIO3_OE_STATE_struct                              rs_cpu_sys_gpio0_gpio3_oe_state

typedef struct _rs_cpu_sys_gpio0_gpio3_oe_state  rs_cpu_sys_gpio0_gpio3_oe_state;
struct _rs_cpu_sys_gpio0_gpio3_oe_state {
    unsigned int gpio3_oe_state                             :20;
    unsigned int reserved                                   :12;
};
#define cpu_sys_gpio0_gpio3_oe_state(val) ((rs_cpu_sys_gpio0_gpio3_oe_state*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_20                                   (HV_GPIO0_BASE_ADDRESS + 0x200)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_20_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_20

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_20  rs_cpu_sys_gpio0_gpio_trg_mode_20;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_20 {
    unsigned int gpio_trg_mode_20                           : 6;
    unsigned int reserved                                   :26;
};
#define cpu_sys_gpio0_gpio_trg_mode_20(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_20*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_23                                   (HV_GPIO0_BASE_ADDRESS + 0x20C)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_23_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_23

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_23  rs_cpu_sys_gpio0_gpio_trg_mode_23;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_23 {
    unsigned int gpio_trg_mode_23                           : 6;
    unsigned int reserved                                   :26;
};
#define cpu_sys_gpio0_gpio_trg_mode_23(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_23*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE4_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x218)

#define CPU_SYS_GPIO0_GPIO_OE4_SET_struct                                rs_cpu_sys_gpio0_gpio_oe4_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe4_set  rs_cpu_sys_gpio0_gpio_oe4_set;
struct _rs_cpu_sys_gpio0_gpio_oe4_set {
    unsigned int gpio4_oe_set                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe4_set(val) ((rs_cpu_sys_gpio0_gpio_oe4_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE5_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x21C)

#define CPU_SYS_GPIO0_GPIO_OE5_SET_struct                                rs_cpu_sys_gpio0_gpio_oe5_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe5_set  rs_cpu_sys_gpio0_gpio_oe5_set;
struct _rs_cpu_sys_gpio0_gpio_oe5_set {
    unsigned int gpio5_oe_set                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe5_set(val) ((rs_cpu_sys_gpio0_gpio_oe5_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT4_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x220)

#define CPU_SYS_GPIO0_GPIO_OUT4_SET_struct                               rs_cpu_sys_gpio0_gpio_out4_set

typedef struct _rs_cpu_sys_gpio0_gpio_out4_set  rs_cpu_sys_gpio0_gpio_out4_set;
struct _rs_cpu_sys_gpio0_gpio_out4_set {
    unsigned int gpio4_out_set                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out4_set(val) ((rs_cpu_sys_gpio0_gpio_out4_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT5_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x224)

#define CPU_SYS_GPIO0_GPIO_OUT5_SET_struct                               rs_cpu_sys_gpio0_gpio_out5_set

typedef struct _rs_cpu_sys_gpio0_gpio_out5_set  rs_cpu_sys_gpio0_gpio_out5_set;
struct _rs_cpu_sys_gpio0_gpio_out5_set {
    unsigned int gpio5_out_set                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out5_set(val) ((rs_cpu_sys_gpio0_gpio_out5_set*)&(val))



#define CPU_SYS_GPIO0_GPIO4_IN                                           (HV_GPIO0_BASE_ADDRESS + 0x228)

#define CPU_SYS_GPIO0_GPIO4_IN_struct                                    rs_cpu_sys_gpio0_gpio4_in

typedef struct _rs_cpu_sys_gpio0_gpio4_in  rs_cpu_sys_gpio0_gpio4_in;
struct _rs_cpu_sys_gpio0_gpio4_in {
    unsigned int gpio4_in                                   : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio4_in(val) ((rs_cpu_sys_gpio0_gpio4_in*)&(val))



#define CPU_SYS_GPIO0_GPIO5_IN                                           (HV_GPIO0_BASE_ADDRESS + 0x22C)

#define CPU_SYS_GPIO0_GPIO5_IN_struct                                    rs_cpu_sys_gpio0_gpio5_in

typedef struct _rs_cpu_sys_gpio0_gpio5_in  rs_cpu_sys_gpio0_gpio5_in;
struct _rs_cpu_sys_gpio0_gpio5_in {
    unsigned int gpio5_in                                   : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio5_in(val) ((rs_cpu_sys_gpio0_gpio5_in*)&(val))



#define CPU_SYS_GPIO0_GPIO4_INT_MASK                                     (HV_GPIO0_BASE_ADDRESS + 0x230)

#define CPU_SYS_GPIO0_GPIO4_INT_MASK_struct                              rs_cpu_sys_gpio0_gpio4_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio4_int_mask  rs_cpu_sys_gpio0_gpio4_int_mask;
struct _rs_cpu_sys_gpio0_gpio4_int_mask {
    unsigned int gpio4_int_mask                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio4_int_mask(val) ((rs_cpu_sys_gpio0_gpio4_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO5_INT_MASK                                     (HV_GPIO0_BASE_ADDRESS + 0x234)

#define CPU_SYS_GPIO0_GPIO5_INT_MASK_struct                              rs_cpu_sys_gpio0_gpio5_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio5_int_mask  rs_cpu_sys_gpio0_gpio5_int_mask;
struct _rs_cpu_sys_gpio0_gpio5_int_mask {
    unsigned int gpio5_int_mask                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio5_int_mask(val) ((rs_cpu_sys_gpio0_gpio5_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO4_INT_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x238)

#define CPU_SYS_GPIO0_GPIO4_INT_CLR_struct                               rs_cpu_sys_gpio0_gpio4_int_clr

typedef struct _rs_cpu_sys_gpio0_gpio4_int_clr  rs_cpu_sys_gpio0_gpio4_int_clr;
struct _rs_cpu_sys_gpio0_gpio4_int_clr {
    unsigned int gpio4_int_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio4_int_clr(val) ((rs_cpu_sys_gpio0_gpio4_int_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO5_INT_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x23C)

#define CPU_SYS_GPIO0_GPIO5_INT_CLR_struct                               rs_cpu_sys_gpio0_gpio5_int_clr

typedef struct _rs_cpu_sys_gpio0_gpio5_int_clr  rs_cpu_sys_gpio0_gpio5_int_clr;
struct _rs_cpu_sys_gpio0_gpio5_int_clr {
    unsigned int gpio5_int_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio5_int_clr(val) ((rs_cpu_sys_gpio0_gpio5_int_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO4_PULSE_DETECT_INT_STATE                       (HV_GPIO0_BASE_ADDRESS + 0x240)

#define CPU_SYS_GPIO0_GPIO4_PULSE_DETECT_INT_STATE_struct                rs_cpu_sys_gpio0_gpio4_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_gpio4_pulse_detect_int_state  rs_cpu_sys_gpio0_gpio4_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_gpio4_pulse_detect_int_state {
    unsigned int gpio4_pulse_detect_int_state               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio4_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_gpio4_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO5_PULSE_DETECT_INT_STATE                       (HV_GPIO0_BASE_ADDRESS + 0x244)

#define CPU_SYS_GPIO0_GPIO5_PULSE_DETECT_INT_STATE_struct                rs_cpu_sys_gpio0_gpio5_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_gpio5_pulse_detect_int_state  rs_cpu_sys_gpio0_gpio5_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_gpio5_pulse_detect_int_state {
    unsigned int gpio5_pulse_detect_int_state               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio5_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_gpio5_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE4_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x24C)

#define CPU_SYS_GPIO0_GPIO_OE4_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe4_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe4_clr  rs_cpu_sys_gpio0_gpio_oe4_clr;
struct _rs_cpu_sys_gpio0_gpio_oe4_clr {
    unsigned int gpio4_oe_clr                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe4_clr(val) ((rs_cpu_sys_gpio0_gpio_oe4_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE5_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x250)

#define CPU_SYS_GPIO0_GPIO_OE5_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe5_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe5_clr  rs_cpu_sys_gpio0_gpio_oe5_clr;
struct _rs_cpu_sys_gpio0_gpio_oe5_clr {
    unsigned int gpio5_oe_clr                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe5_clr(val) ((rs_cpu_sys_gpio0_gpio_oe5_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT4_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x254)

#define CPU_SYS_GPIO0_GPIO_OUT4_CLR_struct                               rs_cpu_sys_gpio0_gpio_out4_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out4_clr  rs_cpu_sys_gpio0_gpio_out4_clr;
struct _rs_cpu_sys_gpio0_gpio_out4_clr {
    unsigned int gpio4_out_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out4_clr(val) ((rs_cpu_sys_gpio0_gpio_out4_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT5_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x258)

#define CPU_SYS_GPIO0_GPIO_OUT5_CLR_struct                               rs_cpu_sys_gpio0_gpio_out5_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out5_clr  rs_cpu_sys_gpio0_gpio_out5_clr;
struct _rs_cpu_sys_gpio0_gpio_out5_clr {
    unsigned int gpio5_out_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out5_clr(val) ((rs_cpu_sys_gpio0_gpio_out5_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO4_OUT_STATE                                    (HV_GPIO0_BASE_ADDRESS + 0x260)

#define CPU_SYS_GPIO0_GPIO4_OUT_STATE_struct                             rs_cpu_sys_gpio0_gpio4_out_state

typedef struct _rs_cpu_sys_gpio0_gpio4_out_state  rs_cpu_sys_gpio0_gpio4_out_state;
struct _rs_cpu_sys_gpio0_gpio4_out_state {
    unsigned int gpio4_out_state                            : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio4_out_state(val) ((rs_cpu_sys_gpio0_gpio4_out_state*)&(val))



#define CPU_SYS_GPIO0_GPIO5_OUT_STATE                                    (HV_GPIO0_BASE_ADDRESS + 0x264)

#define CPU_SYS_GPIO0_GPIO5_OUT_STATE_struct                             rs_cpu_sys_gpio0_gpio5_out_state

typedef struct _rs_cpu_sys_gpio0_gpio5_out_state  rs_cpu_sys_gpio0_gpio5_out_state;
struct _rs_cpu_sys_gpio0_gpio5_out_state {
    unsigned int gpio5_out_state                            : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio5_out_state(val) ((rs_cpu_sys_gpio0_gpio5_out_state*)&(val))



#define CPU_SYS_GPIO0_GPIO4_OE_STATE                                     (HV_GPIO0_BASE_ADDRESS + 0x268)

#define CPU_SYS_GPIO0_GPIO4_OE_STATE_struct                              rs_cpu_sys_gpio0_gpio4_oe_state

typedef struct _rs_cpu_sys_gpio0_gpio4_oe_state  rs_cpu_sys_gpio0_gpio4_oe_state;
struct _rs_cpu_sys_gpio0_gpio4_oe_state {
    unsigned int gpio4_oe_state                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio4_oe_state(val) ((rs_cpu_sys_gpio0_gpio4_oe_state*)&(val))



#define CPU_SYS_GPIO0_GPIO5_OE_STATE                                     (HV_GPIO0_BASE_ADDRESS + 0x26C)

#define CPU_SYS_GPIO0_GPIO5_OE_STATE_struct                              rs_cpu_sys_gpio0_gpio5_oe_state

typedef struct _rs_cpu_sys_gpio0_gpio5_oe_state  rs_cpu_sys_gpio0_gpio5_oe_state;
struct _rs_cpu_sys_gpio0_gpio5_oe_state {
    unsigned int gpio5_oe_state                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio5_oe_state(val) ((rs_cpu_sys_gpio0_gpio5_oe_state*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_30                                   (HV_GPIO0_BASE_ADDRESS + 0x300)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_30_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_30

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_30  rs_cpu_sys_gpio0_gpio_trg_mode_30;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_30 {
    unsigned int gpio_trg_mode_30                           : 6;
    unsigned int reserved                                   :26;
};
#define cpu_sys_gpio0_gpio_trg_mode_30(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_30*)&(val))



#define CPU_SYS_GPIO0_GPIO_TRG_MODE_33                                   (HV_GPIO0_BASE_ADDRESS + 0x30C)

#define CPU_SYS_GPIO0_GPIO_TRG_MODE_33_struct                            rs_cpu_sys_gpio0_gpio_trg_mode_33

typedef struct _rs_cpu_sys_gpio0_gpio_trg_mode_33  rs_cpu_sys_gpio0_gpio_trg_mode_33;
struct _rs_cpu_sys_gpio0_gpio_trg_mode_33 {
    unsigned int gpio_trg_mode_33                           : 6;
    unsigned int reserved                                   :26;
};
#define cpu_sys_gpio0_gpio_trg_mode_33(val) ((rs_cpu_sys_gpio0_gpio_trg_mode_33*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE6_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x318)

#define CPU_SYS_GPIO0_GPIO_OE6_SET_struct                                rs_cpu_sys_gpio0_gpio_oe6_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe6_set  rs_cpu_sys_gpio0_gpio_oe6_set;
struct _rs_cpu_sys_gpio0_gpio_oe6_set {
    unsigned int gpio6_oe_set                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe6_set(val) ((rs_cpu_sys_gpio0_gpio_oe6_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE7_SET                                       (HV_GPIO0_BASE_ADDRESS + 0x31C)

#define CPU_SYS_GPIO0_GPIO_OE7_SET_struct                                rs_cpu_sys_gpio0_gpio_oe7_set

typedef struct _rs_cpu_sys_gpio0_gpio_oe7_set  rs_cpu_sys_gpio0_gpio_oe7_set;
struct _rs_cpu_sys_gpio0_gpio_oe7_set {
    unsigned int gpio7_oe_set                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe7_set(val) ((rs_cpu_sys_gpio0_gpio_oe7_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT6_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x320)

#define CPU_SYS_GPIO0_GPIO_OUT6_SET_struct                               rs_cpu_sys_gpio0_gpio_out6_set

typedef struct _rs_cpu_sys_gpio0_gpio_out6_set  rs_cpu_sys_gpio0_gpio_out6_set;
struct _rs_cpu_sys_gpio0_gpio_out6_set {
    unsigned int gpio6_out_set                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out6_set(val) ((rs_cpu_sys_gpio0_gpio_out6_set*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT7_SET                                      (HV_GPIO0_BASE_ADDRESS + 0x324)

#define CPU_SYS_GPIO0_GPIO_OUT7_SET_struct                               rs_cpu_sys_gpio0_gpio_out7_set

typedef struct _rs_cpu_sys_gpio0_gpio_out7_set  rs_cpu_sys_gpio0_gpio_out7_set;
struct _rs_cpu_sys_gpio0_gpio_out7_set {
    unsigned int gpio7_out_set                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out7_set(val) ((rs_cpu_sys_gpio0_gpio_out7_set*)&(val))



#define CPU_SYS_GPIO0_GPIO6_IN                                           (HV_GPIO0_BASE_ADDRESS + 0x328)

#define CPU_SYS_GPIO0_GPIO6_IN_struct                                    rs_cpu_sys_gpio0_gpio6_in

typedef struct _rs_cpu_sys_gpio0_gpio6_in  rs_cpu_sys_gpio0_gpio6_in;
struct _rs_cpu_sys_gpio0_gpio6_in {
    unsigned int gpio6_in                                   : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio6_in(val) ((rs_cpu_sys_gpio0_gpio6_in*)&(val))



#define CPU_SYS_GPIO0_GPIO7_IN                                           (HV_GPIO0_BASE_ADDRESS + 0x32C)

#define CPU_SYS_GPIO0_GPIO7_IN_struct                                    rs_cpu_sys_gpio0_gpio7_in

typedef struct _rs_cpu_sys_gpio0_gpio7_in  rs_cpu_sys_gpio0_gpio7_in;
struct _rs_cpu_sys_gpio0_gpio7_in {
    unsigned int gpio7_in                                   : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio7_in(val) ((rs_cpu_sys_gpio0_gpio7_in*)&(val))



#define CPU_SYS_GPIO0_GPIO6_INT_MASK                                     (HV_GPIO0_BASE_ADDRESS + 0x330)

#define CPU_SYS_GPIO0_GPIO6_INT_MASK_struct                              rs_cpu_sys_gpio0_gpio6_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio6_int_mask  rs_cpu_sys_gpio0_gpio6_int_mask;
struct _rs_cpu_sys_gpio0_gpio6_int_mask {
    unsigned int gpio6_int_mask                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio6_int_mask(val) ((rs_cpu_sys_gpio0_gpio6_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO7_INT_MASK                                     (HV_GPIO0_BASE_ADDRESS + 0x334)

#define CPU_SYS_GPIO0_GPIO7_INT_MASK_struct                              rs_cpu_sys_gpio0_gpio7_int_mask

typedef struct _rs_cpu_sys_gpio0_gpio7_int_mask  rs_cpu_sys_gpio0_gpio7_int_mask;
struct _rs_cpu_sys_gpio0_gpio7_int_mask {
    unsigned int gpio7_int_mask                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio7_int_mask(val) ((rs_cpu_sys_gpio0_gpio7_int_mask*)&(val))



#define CPU_SYS_GPIO0_GPIO6_INT_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x338)

#define CPU_SYS_GPIO0_GPIO6_INT_CLR_struct                               rs_cpu_sys_gpio0_gpio6_int_clr

typedef struct _rs_cpu_sys_gpio0_gpio6_int_clr  rs_cpu_sys_gpio0_gpio6_int_clr;
struct _rs_cpu_sys_gpio0_gpio6_int_clr {
    unsigned int gpio6_int_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio6_int_clr(val) ((rs_cpu_sys_gpio0_gpio6_int_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO7_INT_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x33C)

#define CPU_SYS_GPIO0_GPIO7_INT_CLR_struct                               rs_cpu_sys_gpio0_gpio7_int_clr

typedef struct _rs_cpu_sys_gpio0_gpio7_int_clr  rs_cpu_sys_gpio0_gpio7_int_clr;
struct _rs_cpu_sys_gpio0_gpio7_int_clr {
    unsigned int gpio7_int_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio7_int_clr(val) ((rs_cpu_sys_gpio0_gpio7_int_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO6_PULSE_DETECT_INT_STATE                       (HV_GPIO0_BASE_ADDRESS + 0x340)

#define CPU_SYS_GPIO0_GPIO6_PULSE_DETECT_INT_STATE_struct                rs_cpu_sys_gpio0_gpio6_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_gpio6_pulse_detect_int_state  rs_cpu_sys_gpio0_gpio6_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_gpio6_pulse_detect_int_state {
    unsigned int gpio6_pulse_detect_int_state               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio6_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_gpio6_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO7_PULSE_DETECT_INT_STATE                       (HV_GPIO0_BASE_ADDRESS + 0x344)

#define CPU_SYS_GPIO0_GPIO7_PULSE_DETECT_INT_STATE_struct                rs_cpu_sys_gpio0_gpio7_pulse_detect_int_state

typedef struct _rs_cpu_sys_gpio0_gpio7_pulse_detect_int_state  rs_cpu_sys_gpio0_gpio7_pulse_detect_int_state;
struct _rs_cpu_sys_gpio0_gpio7_pulse_detect_int_state {
    unsigned int gpio7_pulse_detect_int_state               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio7_pulse_detect_int_state(val) ((rs_cpu_sys_gpio0_gpio7_pulse_detect_int_state*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE6_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x34C)

#define CPU_SYS_GPIO0_GPIO_OE6_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe6_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe6_clr  rs_cpu_sys_gpio0_gpio_oe6_clr;
struct _rs_cpu_sys_gpio0_gpio_oe6_clr {
    unsigned int gpio6_oe_clr                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe6_clr(val) ((rs_cpu_sys_gpio0_gpio_oe6_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OE7_CLR                                       (HV_GPIO0_BASE_ADDRESS + 0x350)

#define CPU_SYS_GPIO0_GPIO_OE7_CLR_struct                                rs_cpu_sys_gpio0_gpio_oe7_clr

typedef struct _rs_cpu_sys_gpio0_gpio_oe7_clr  rs_cpu_sys_gpio0_gpio_oe7_clr;
struct _rs_cpu_sys_gpio0_gpio_oe7_clr {
    unsigned int gpio7_oe_clr                               : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_oe7_clr(val) ((rs_cpu_sys_gpio0_gpio_oe7_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT6_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x354)

#define CPU_SYS_GPIO0_GPIO_OUT6_CLR_struct                               rs_cpu_sys_gpio0_gpio_out6_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out6_clr  rs_cpu_sys_gpio0_gpio_out6_clr;
struct _rs_cpu_sys_gpio0_gpio_out6_clr {
    unsigned int gpio6_out_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out6_clr(val) ((rs_cpu_sys_gpio0_gpio_out6_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO_OUT7_CLR                                      (HV_GPIO0_BASE_ADDRESS + 0x358)

#define CPU_SYS_GPIO0_GPIO_OUT7_CLR_struct                               rs_cpu_sys_gpio0_gpio_out7_clr

typedef struct _rs_cpu_sys_gpio0_gpio_out7_clr  rs_cpu_sys_gpio0_gpio_out7_clr;
struct _rs_cpu_sys_gpio0_gpio_out7_clr {
    unsigned int gpio7_out_clr                              : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio_out7_clr(val) ((rs_cpu_sys_gpio0_gpio_out7_clr*)&(val))



#define CPU_SYS_GPIO0_GPIO6_OUT_STATE                                    (HV_GPIO0_BASE_ADDRESS + 0x360)

#define CPU_SYS_GPIO0_GPIO6_OUT_STATE_struct                             rs_cpu_sys_gpio0_gpio6_out_state

typedef struct _rs_cpu_sys_gpio0_gpio6_out_state  rs_cpu_sys_gpio0_gpio6_out_state;
struct _rs_cpu_sys_gpio0_gpio6_out_state {
    unsigned int gpio6_out_state                            : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio6_out_state(val) ((rs_cpu_sys_gpio0_gpio6_out_state*)&(val))



#define CPU_SYS_GPIO0_GPIO7_OUT_STATE                                    (HV_GPIO0_BASE_ADDRESS + 0x364)

#define CPU_SYS_GPIO0_GPIO7_OUT_STATE_struct                             rs_cpu_sys_gpio0_gpio7_out_state

typedef struct _rs_cpu_sys_gpio0_gpio7_out_state  rs_cpu_sys_gpio0_gpio7_out_state;
struct _rs_cpu_sys_gpio0_gpio7_out_state {
    unsigned int gpio7_out_state                            : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio7_out_state(val) ((rs_cpu_sys_gpio0_gpio7_out_state*)&(val))



#define CPU_SYS_GPIO0_GPIO6_OE_STATE                                     (HV_GPIO0_BASE_ADDRESS + 0x368)

#define CPU_SYS_GPIO0_GPIO6_OE_STATE_struct                              rs_cpu_sys_gpio0_gpio6_oe_state

typedef struct _rs_cpu_sys_gpio0_gpio6_oe_state  rs_cpu_sys_gpio0_gpio6_oe_state;
struct _rs_cpu_sys_gpio0_gpio6_oe_state {
    unsigned int gpio6_oe_state                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio6_oe_state(val) ((rs_cpu_sys_gpio0_gpio6_oe_state*)&(val))



#define CPU_SYS_GPIO0_GPIO7_OE_STATE                                     (HV_GPIO0_BASE_ADDRESS + 0x36C)

#define CPU_SYS_GPIO0_GPIO7_OE_STATE_struct                              rs_cpu_sys_gpio0_gpio7_oe_state

typedef struct _rs_cpu_sys_gpio0_gpio7_oe_state  rs_cpu_sys_gpio0_gpio7_oe_state;
struct _rs_cpu_sys_gpio0_gpio7_oe_state {
    unsigned int gpio7_oe_state                             : 2;
    unsigned int reserved                                   :30;
};
#define cpu_sys_gpio0_gpio7_oe_state(val) ((rs_cpu_sys_gpio0_gpio7_oe_state*)&(val))



#endif