#ifndef _HV_PAGE_HT7315_KV_DIMMER_CTRL_REG4_H_
#define _HV_PAGE_HT7315_KV_DIMMER_CTRL_REG4_H_

#ifndef HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS
    #define HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS                                         0x11045D00
#endif


#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_10                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x00)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_10_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_10

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_10  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_10;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_10 {
    unsigned int reg_dim_cmd_vaule0_10                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_10(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_10*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_10                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x04)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_10_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_10

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_10  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_10;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_10 {
    unsigned int reg_dim_cmd_vaule1_10                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_10(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_10*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_10                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x08)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_10_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_10

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_10  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_10;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_10 {
    unsigned int reg_dim_cmd_vaule2_10                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_10(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_10*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__10                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x0C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__10_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__10

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__10  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__10;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__10 {
    unsigned int reg_dim_cmd_vaule3_10                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__10(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__10*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_11                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x10)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_11_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_11

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_11  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_11;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_11 {
    unsigned int reg_dim_cmd_vaule0_11                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_11(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_11*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_11                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x14)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_11_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_11

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_11  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_11;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_11 {
    unsigned int reg_dim_cmd_vaule1_11                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_11(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_11*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_11                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x18)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_11_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_11

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_11  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_11;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_11 {
    unsigned int reg_dim_cmd_vaule2_11                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_11(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_11*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__11                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x1C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__11_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__11

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__11  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__11;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__11 {
    unsigned int reg_dim_cmd_vaule3_11                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__11(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__11*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_12                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x20)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_12_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_12

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_12  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_12;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_12 {
    unsigned int reg_dim_cmd_vaule0_12                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_12(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_12*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_12                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x24)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_12_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_12

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_12  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_12;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_12 {
    unsigned int reg_dim_cmd_vaule1_12                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_12(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_12*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_12                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x28)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_12_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_12

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_12  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_12;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_12 {
    unsigned int reg_dim_cmd_vaule2_12                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_12(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_12*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__12                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x2C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__12_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__12

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__12  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__12;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__12 {
    unsigned int reg_dim_cmd_vaule3_12                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__12(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__12*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_13                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x30)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_13_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_13

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_13  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_13;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_13 {
    unsigned int reg_dim_cmd_vaule0_13                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_13(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_13*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_13                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x34)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_13_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_13

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_13  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_13;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_13 {
    unsigned int reg_dim_cmd_vaule1_13                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_13(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_13*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_13                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x38)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_13_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_13

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_13  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_13;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_13 {
    unsigned int reg_dim_cmd_vaule2_13                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_13(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_13*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__13                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x3C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__13_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__13

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__13  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__13;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__13 {
    unsigned int reg_dim_cmd_vaule3_13                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__13(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__13*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_14                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x40)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_14_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_14

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_14  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_14;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_14 {
    unsigned int reg_dim_cmd_vaule0_14                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_14(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_14*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_14                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x44)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_14_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_14

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_14  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_14;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_14 {
    unsigned int reg_dim_cmd_vaule1_14                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_14(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_14*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_14                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x48)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_14_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_14

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_14  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_14;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_14 {
    unsigned int reg_dim_cmd_vaule2_14                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_14(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_14*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__14                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x4C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__14_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__14

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__14  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__14;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__14 {
    unsigned int reg_dim_cmd_vaule3_14                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__14(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__14*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_15                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x50)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_15_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_15

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_15  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_15;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_15 {
    unsigned int reg_dim_cmd_vaule0_15                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_15(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_15*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_15                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x54)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_15_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_15

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_15  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_15;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_15 {
    unsigned int reg_dim_cmd_vaule1_15                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_15(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_15*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_15                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x58)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_15_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_15

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_15  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_15;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_15 {
    unsigned int reg_dim_cmd_vaule2_15                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_15(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_15*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__15                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x5C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__15_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__15

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__15  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__15;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__15 {
    unsigned int reg_dim_cmd_vaule3_15                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__15(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__15*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_16                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x60)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_16_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_16

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_16  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_16;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_16 {
    unsigned int reg_dim_cmd_vaule0_16                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_16(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_16*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_16                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x64)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_16_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_16

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_16  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_16;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_16 {
    unsigned int reg_dim_cmd_vaule1_16                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_16(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_16*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_16                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x68)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_16_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_16

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_16  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_16;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_16 {
    unsigned int reg_dim_cmd_vaule2_16                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_16(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_16*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__16                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x6C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__16_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__16

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__16  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__16;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__16 {
    unsigned int reg_dim_cmd_vaule3_16                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__16(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__16*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_17                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x70)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_17_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_17

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_17  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_17;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_17 {
    unsigned int reg_dim_cmd_vaule0_17                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_17(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_17*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_17                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x74)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_17_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_17

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_17  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_17;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_17 {
    unsigned int reg_dim_cmd_vaule1_17                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_17(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_17*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_17                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x78)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_17_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_17

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_17  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_17;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_17 {
    unsigned int reg_dim_cmd_vaule2_17                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_17(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_17*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__17                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x7C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__17_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__17

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__17  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__17;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__17 {
    unsigned int reg_dim_cmd_vaule3_17                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__17(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__17*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_18                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x80)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_18_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_18

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_18  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_18;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_18 {
    unsigned int reg_dim_cmd_vaule0_18                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_18(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_18*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_18                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x84)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_18_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_18

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_18  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_18;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_18 {
    unsigned int reg_dim_cmd_vaule1_18                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_18(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_18*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_18                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x88)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_18_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_18

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_18  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_18;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_18 {
    unsigned int reg_dim_cmd_vaule2_18                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_18(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_18*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__18                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x8C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__18_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__18

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__18  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__18;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__18 {
    unsigned int reg_dim_cmd_vaule3_18                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__18(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__18*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_19                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x90)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE0_19_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_19

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_19  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_19;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_19 {
    unsigned int reg_dim_cmd_vaule0_19                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_19(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule0_19*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_19                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x94)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE1_19_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_19

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_19  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_19;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_19 {
    unsigned int reg_dim_cmd_vaule1_19                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_19(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule1_19*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_19                     (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x98)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE2_19_struct              rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_19

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_19  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_19;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_19 {
    unsigned int reg_dim_cmd_vaule2_19                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_19(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule2_19*)&(val))



#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__19                    (HV_KV_DIMMER_CTRL_REG4_BASE_ADDRESS + 0x9C)

#define RX_KV_DIMMER_CTRL_REG4_REG_DIM_CMD_VAULE3__19_struct             rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__19

typedef struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__19  rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__19;
struct _rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__19 {
    unsigned int reg_dim_cmd_vaule3_19                      :32;
};
#define rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__19(val) ((rs_rx_kv_dimmer_ctrl_reg4_reg_dim_cmd_vaule3__19*)&(val))



#endif