/*
 * @file hv_cal_Timer.h
 * @brief Header file of hw timer module.
 *
 * @verbatim
 * ==============================================================================
 *                        ##### How to use #####
 * ==============================================================================
 * (+) Use Hv_Cal_Tmr_Init()
 *
 * @endverbatim
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2023-06-12
 */

#ifndef _HV_CAL_TIMER_H
#define _HV_CAL_TIMER_H
#include "Common/hv_comm_DataType.h"

/** @defgroup
 *  cal system timer functions
 *  @{
 */

/*
 The HT7315 supports one timer(Timer0);
 The TMR consists 4-channel timer(0ch-3ch), each timer has 32-bit counter and generate irq;
 The function of this TMR is interval counter. Connect to APB.
 */

/*
Divided 79MHz total bus clock
Frequency_division  Counter_frequency (Hz)  Counter_cycle(ns)
2   39.5M   25.3
4   19.8 M  50.6
8   9.88 M  101.3
16  4.94M   202.5
32  2.47M   405.1
64  1.23M   810.1
128 617.2K  1620.3
256 308.6K  3240.5
*/
typedef enum _TmrDivCcd
{
    TMR_DIV_CCD_2 = 0,
    TMR_DIV_CCD_4,
    TMR_DIV_CCD_8,
    TMR_DIV_CCD_16,
    TMR_DIV_CCD_32,
    TMR_DIV_CCD_64,
    TMR_DIV_CCD_128,
    TMR_DIV_CCD_256,
    TMR_DIV_CCD_MAX
} TmrDivCcd;

typedef enum _TmrcClr
{
    TMRC_CLR_DISABLE = 0,
    TMRC_CLR_ENABLE,
    TMRC_CLR_MAX
} TmrcClr;

typedef enum _TmrcTce
{
    TMRC_TCE_STOP = 0,
    TMRC_TCE_RUN,
    TMRC_TCE_MAX
} TmrcTce;

typedef enum _TmrcCcde
{
    TMRC_CCDE_DIV_DISABLE = 0,
    TMRC_CCDE_DIV_ENABLE,
    TMRC_CCDE_MAX
} TmrcCcde;

typedef enum _TmrcCre
{
    TMRC_CRE_CLR_DISABLE   = 0,
    TMRC_CRE_CLR_ENABLE,
    TMRC_CRE_MAX
} TmrcCre;

typedef enum _TmrIntTiis
{
    TMRINT_TIIS_INT_STAT_NO_MATCH = 0,
    TMRINT_TIIS_INT_STAT_MATCH,
    TMRINT_TIIS_MAX
} TmrIntTiis;

typedef enum _TmrIvlTiie
{
    TMRIVL_TIIE_INT_DISABLE = 0,
    TMRIVL_TIIE_INT_ENABLE,
    TMRIVL_TIIE_MAX
} TmrIvlTiie;

typedef enum _TmrIvlTzce
{
    TMRIVL_TZCE_ZERO_CLR_DISABLE = 0,
    TMRIVL_TZCE_ZERO_CLR_ENABLE,
    TMRIVL_TZCE_MAX
} TmrIvlTzce;

/* TMR register definitions */
#define TMRC_TCE        (1 << 7)
#define TMRC_CCDE       (1 << 6)
#define TMRC_CRE        (1 << 5)
#define TMRINT_TIIS     (1 << 0)
#define TMRIVL_TIIE     (1 << 15)
#define TMRIVL_TZCE     (1 << 0)

#define HW_TMR_HZ       (1000)

typedef enum _TmrChannel
{
    TMR_CH_0 = 0,
    TMR_CH_1,
    TMR_CH_2,
    TMR_CH_3,
    TMR_CH_MAX
} TmrChannel;

typedef VOID (*TMR_CALLBACK)(UINT32 uiArg);

/** TIMER Time base Configuration Structure definition
 */
typedef struct _HwTmrConfig
{
    TmrChannel            enChannel;/*Timer's channel*/
    TmrDivCcd             enDivMode;/*Counter Clock Divided Enable*/
    TmrcTce               enCounterEnable;/*Counter Enable*/
    TmrcCcde              enClockDividedEnable;/*Counter Clock Divided Enable*/
    TmrcClr               enClrEnable;/*Clear to Zero Enable*/
    TmrIntTiis            enIntStatus;/*Timer Interval Interrupt Status*/
    TmrIvlTiie            enIntEnable;/*Timer Interval Interrupt Enale*/
    TmrIvlTzce            enZeroClrEnable;/*Timer Zero Clear Enable*/
    UINT32                uiCompareValue;/*Timer Compare Value*/
    UINT32                uiTimerCounter;/*Timer Counter */
    TMR_CALLBACK          pfTmrCb;/*Timer Callback Handler*/
} HwTmrConfig;

typedef struct _HwTmr
{
    HwTmrConfig    stTmrCfg;/*TMR Base Config*/
    UINT32         uiTmrBaseOffset;/*TMR Base Addr Offset*/
    BOOL           bIntSet;  /*TME irq Set*/
    BOOL           bInISR;   /*TMR In ISR*/
} HwTmr;

/**@brief init tmr parameters
 *  @param params pointer to tmr configure parameters
 *  @return HwTmr structure pointer
 */
HwTmr *Hv_Cal_Tmr_Init(HwTmrConfig *pstTmrCfg);

/** @brief stop timer
 *  @param[in] self HwTmr structure pointer
 */
VOID Hv_Cal_Tmr_Stop(HwTmr *pstTmr);


/**@brief Cleanup tmr parameters
 *  @param self HwTmr structure pointer
 */
VOID Hv_Cal_Tmr_Cleanup(HwTmr *pstTmr);


/**@brief set tmr ms counter register values, use before Hv_Cal_Tmr_Start
 *  @param[in] self HwTmr structure pointer
 *  @param[in] uiMsCounts count ms time
 */
VOID Hv_Cal_Tmr_SetMsCounter(HwTmr *pstTmr, UINT32 uiMsCounts);


/**@brief set system timer ISR handler function
 *  @param irqNum interrupt Number value
 *  @param arg pointer to tmr configure parameters
 *  @return ISR HV_VOS_ISR_RESULT_E result
 */
HV_VOS_ISR_RESULT_E Hv_Cal_Tmr_IrqHandler(UINT32 uiIrqNum, VOID *pArg);

/**@brief set system timer interrupt
 *  @param self HwTmr structure pointer
 */
VOID Hv_Cal_Tmr_SetInterrupt(HwTmr *pstTmr);

/**@brief clean system timer interrupt
 *  @param self HwTmr structure pointer
 */
VOID Hv_Cal_Tmr_ClearInterrupt(HwTmr *pstTmr);

/**@brief start system timer
 *  @param self HwTmr structure pointer
 */
VOID Hv_Cal_Tmr_Start(HwTmr *pstTmr);

/**@brief read system timer counter
 *  @param[in] self HwTmr structure pointer
 *  @param[out] read counter values
 */
UINT32 Hv_Cal_Tmr_ReadCounter(HwTmr *pstTmr);

/** set system timer counter
 *  @param[in] self HwTmr structure pointer
 *  @param[in] count count values
 */
VOID Hv_Cal_Tmr_SetCounter(HwTmr *pstTmr, UINT32 uiCount);

/** @} */
#endif


