#ifndef _HV_PAGE_HT7315_EDP_RX_MAC_WR2_REG_01_H_
#define _HV_PAGE_HT7315_EDP_RX_MAC_WR2_REG_01_H_

#ifndef HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS
    #define HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS                                         0x1104A900
#endif


#define RX_EDP_RX_MAC_WR2_REG_01_00                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x00)

#define RX_EDP_RX_MAC_WR2_REG_01_00_struct                               rs_rx_edp_rx_mac_wr2_reg_01_00

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_00  rs_rx_edp_rx_mac_wr2_reg_01_00;
struct _rs_rx_edp_rx_mac_wr2_reg_01_00 {
    unsigned int reg_01_dprx_sw_dpcd_cr_done                : 5;
    unsigned int reg_01_dprx_sw_dpcd_eq_lock                : 5;
    unsigned int reg_01_dprx_sw_dpcd_symbol_lock            : 5;
    unsigned int reg_01_dprx_sw_dpcd_aln_done               : 2;
    unsigned int reg_01_dprx_sw_dpcd_link_status_updated    : 2;
    unsigned int reg_01_dprx_sw_dpcd_panel_self_test_enable : 2;
    unsigned int reg_01_dprx_sw_dpcd_dsc_enable             : 2;
    unsigned int reserved                                   : 9;
};
#define rx_edp_rx_mac_wr2_reg_01_00(val) ((rs_rx_edp_rx_mac_wr2_reg_01_00*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_04                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x04)

#define RX_EDP_RX_MAC_WR2_REG_01_04_struct                               rs_rx_edp_rx_mac_wr2_reg_01_04

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_04  rs_rx_edp_rx_mac_wr2_reg_01_04;
struct _rs_rx_edp_rx_mac_wr2_reg_01_04 {
    unsigned int reg_01_dprx_sw_dpcd_alternate_scrambler_reset_enable: 2;
    unsigned int reg_01_dprx_sw_dpcd_downspread_msa_timing_par_ignore_en: 2;
    unsigned int reg_01_dprx_sw_dpcd_enhanced_frame_en      : 2;
    unsigned int reg_01_dprx_sw_dpcd_lane0_link_qual_pattern_set: 4;
    unsigned int reg_01_dprx_sw_dpcd_lane0_max_pre_emphasis_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane0_max_swing_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane0_pre_emphasis_set : 3;
    unsigned int reg_01_dprx_sw_dpcd_lane0_voltage_swing_set: 3;
    unsigned int reg_01_dprx_sw_dpcd_lane1_link_qual_pattern_set: 4;
    unsigned int reg_01_dprx_sw_dpcd_lane1_max_pre_emphasis_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane1_max_swing_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane1_pre_emphasis_set : 3;
    unsigned int reserved                                   : 1;
};
#define rx_edp_rx_mac_wr2_reg_01_04(val) ((rs_rx_edp_rx_mac_wr2_reg_01_04*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_08                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x08)

#define RX_EDP_RX_MAC_WR2_REG_01_08_struct                               rs_rx_edp_rx_mac_wr2_reg_01_08

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_08  rs_rx_edp_rx_mac_wr2_reg_01_08;
struct _rs_rx_edp_rx_mac_wr2_reg_01_08 {
    unsigned int reg_01_dprx_sw_dpcd_lane1_voltage_swing_set: 3;
    unsigned int reg_01_dprx_sw_dpcd_lane2_link_qual_pattern_set: 4;
    unsigned int reg_01_dprx_sw_dpcd_lane2_max_pre_emphasis_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane2_max_swing_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane2_pre_emphasis_set : 3;
    unsigned int reg_01_dprx_sw_dpcd_lane2_voltage_swing_set: 3;
    unsigned int reg_01_dprx_sw_dpcd_lane3_link_qual_pattern_set: 4;
    unsigned int reg_01_dprx_sw_dpcd_lane3_max_pre_emphasis_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane3_max_swing_reached: 2;
    unsigned int reg_01_dprx_sw_dpcd_lane3_pre_emphasis_set : 3;
    unsigned int reg_01_dprx_sw_dpcd_lane3_voltage_swing_set: 3;
    unsigned int reserved                                   : 1;
};
#define rx_edp_rx_mac_wr2_reg_01_08(val) ((rs_rx_edp_rx_mac_wr2_reg_01_08*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_0C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x0C)

#define RX_EDP_RX_MAC_WR2_REG_01_0C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_0c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_0c  rs_rx_edp_rx_mac_wr2_reg_01_0c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_0c {
    unsigned int reg_01_dprx_sw_dpcd_lane_count_set         : 6;
    unsigned int reg_01_dprx_sw_dpcd_link_bw_set            : 9;
    unsigned int reg_01_dprx_sw_dpcd_link_rate_set          : 5;
    unsigned int reg_01_dprx_sw_dpcd_mso_number_of_links    : 4;
    unsigned int reg_01_dprx_sw_dpcd_no_aux_transaction_link_training: 2;
    unsigned int reg_01_dprx_sw_dpcd_scrambling_disable     : 2;
    unsigned int reg_01_dprx_sw_dpcd_symbol_error_count_sel : 4;
};
#define rx_edp_rx_mac_wr2_reg_01_0c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_0c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_10                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x10)

#define RX_EDP_RX_MAC_WR2_REG_01_10_struct                               rs_rx_edp_rx_mac_wr2_reg_01_10

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_10  rs_rx_edp_rx_mac_wr2_reg_01_10;
struct _rs_rx_edp_rx_mac_wr2_reg_01_10 {
    unsigned int reg_01_dprx_sw_dpcd_training_aux_rd_interval: 8;
    unsigned int reg_01_dprx_sw_dpcd_training_pattern_select: 5;
    unsigned int reg_01_dprx_sw_dpcd_vsc_sdp_ext_for_color_supported: 2;
    unsigned int reg_01_dprx_sw_dpcd_aux_frame_sync_valid   : 2;
    unsigned int reg_01_dprx_sw_dpcd_cp_irq                 : 2;
    unsigned int reserved                                   :13;
};
#define rx_edp_rx_mac_wr2_reg_01_10(val) ((rs_rx_edp_rx_mac_wr2_reg_01_10*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_14                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x14)

#define RX_EDP_RX_MAC_WR2_REG_01_14_struct                               rs_rx_edp_rx_mac_wr2_reg_01_14

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_14  rs_rx_edp_rx_mac_wr2_reg_01_14;
struct _rs_rx_edp_rx_mac_wr2_reg_01_14 {
    unsigned int reg_01_dprx_sw_dpcd_aux_frame_sync_tx_vbe_master_value:32;
};
#define rx_edp_rx_mac_wr2_reg_01_14(val) ((rs_rx_edp_rx_mac_wr2_reg_01_14*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_18                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x18)

#define RX_EDP_RX_MAC_WR2_REG_01_18_struct                               rs_rx_edp_rx_mac_wr2_reg_01_18

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_18  rs_rx_edp_rx_mac_wr2_reg_01_18;
struct _rs_rx_edp_rx_mac_wr2_reg_01_18 {
    unsigned int reg_01_dprx_sw_dpcd_mccs_irq               : 2;
    unsigned int reg_01_dprx_sw_dpcd_pre_emphasis_lane0     : 3;
    unsigned int reg_01_dprx_sw_dpcd_pre_emphasis_lane1     : 3;
    unsigned int reg_01_dprx_sw_dpcd_pre_emphasis_lane2     : 3;
    unsigned int reg_01_dprx_sw_dpcd_pre_emphasis_lane3     : 3;
    unsigned int reg_01_dprx_sw_dpcd_voltage_swing_lane0    : 3;
    unsigned int reg_01_dprx_sw_dpcd_voltage_swing_lane1    : 3;
    unsigned int reg_01_dprx_sw_dpcd_voltage_swing_lane2    : 3;
    unsigned int reg_01_dprx_sw_dpcd_voltage_swing_lane3    : 3;
    unsigned int reg_01_dprx_sw_dpcd_receive_port_0_status  : 2;
    unsigned int reg_01_dprx_sw_dpcd_receive_port_1_status  : 2;
    unsigned int reserved                                   : 2;
};
#define rx_edp_rx_mac_wr2_reg_01_18(val) ((rs_rx_edp_rx_mac_wr2_reg_01_18*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_1C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x1C)

#define RX_EDP_RX_MAC_WR2_REG_01_1C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_1c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_1c  rs_rx_edp_rx_mac_wr2_reg_01_1c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_1c {
    unsigned int reg_01_dprx_sw_dpcd_symbol_error_count_lane0:17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_1c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_1c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_20                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x20)

#define RX_EDP_RX_MAC_WR2_REG_01_20_struct                               rs_rx_edp_rx_mac_wr2_reg_01_20

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_20  rs_rx_edp_rx_mac_wr2_reg_01_20;
struct _rs_rx_edp_rx_mac_wr2_reg_01_20 {
    unsigned int reg_01_dprx_sw_dpcd_symbol_error_count_lane1:17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_20(val) ((rs_rx_edp_rx_mac_wr2_reg_01_20*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_24                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x24)

#define RX_EDP_RX_MAC_WR2_REG_01_24_struct                               rs_rx_edp_rx_mac_wr2_reg_01_24

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_24  rs_rx_edp_rx_mac_wr2_reg_01_24;
struct _rs_rx_edp_rx_mac_wr2_reg_01_24 {
    unsigned int reg_01_dprx_sw_dpcd_symbol_error_count_lane2:17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_24(val) ((rs_rx_edp_rx_mac_wr2_reg_01_24*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_28                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x28)

#define RX_EDP_RX_MAC_WR2_REG_01_28_struct                               rs_rx_edp_rx_mac_wr2_reg_01_28

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_28  rs_rx_edp_rx_mac_wr2_reg_01_28;
struct _rs_rx_edp_rx_mac_wr2_reg_01_28 {
    unsigned int reg_01_dprx_sw_dpcd_symbol_error_count_lane3:17;
    unsigned int reg_01_dprx_sw_dpcd_tx_remain_ml_psr       : 2;
    unsigned int reserved                                   :13;
};
#define rx_edp_rx_mac_wr2_reg_01_28(val) ((rs_rx_edp_rx_mac_wr2_reg_01_28*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_2C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x2C)

#define RX_EDP_RX_MAC_WR2_REG_01_2C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_2c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_2c  rs_rx_edp_rx_mac_wr2_reg_01_2c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_2c {
    unsigned int reg_01_dprx_sw_dpcd_psr2_link_crc_error    : 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_crc_valid          : 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_first_scan_line_of_the_su: 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_last_scan_line_of_the_su: 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_state              : 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_su_valid           : 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_y_valid            : 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_upate_rfb          : 2;
    unsigned int reg_01_dprx_sw_dpcd_rfb_storage_error      : 2;
    unsigned int reg_01_dprx_sw_dpcd_sink_device_psr_capability_change: 2;
    unsigned int reg_01_dprx_sw_dpcd_sink_device_psr_status : 4;
    unsigned int reg_01_dprx_sw_dpcd_vsc_sdp_uncorrectable_error: 2;
    unsigned int reg_01_dprx_sw_dpcd_enable_psr             : 2;
    unsigned int reg_01_dprx_sw_dpcd_enable_psr2            : 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_crc_verification_in_psr_active: 2;
};
#define rx_edp_rx_mac_wr2_reg_01_2c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_2c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_30                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x30)

#define RX_EDP_RX_MAC_WR2_REG_01_30_struct                               rs_rx_edp_rx_mac_wr2_reg_01_30

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_30  rs_rx_edp_rx_mac_wr2_reg_01_30;
struct _rs_rx_edp_rx_mac_wr2_reg_01_30 {
    unsigned int reg_01_dprx_sw_dpcd_psr_frame_capture_indication: 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_irq_hpd_with_link_crc_errors: 2;
    unsigned int reg_01_dprx_sw_dpcd_psr_su_scan_line_capture_indication: 2;
    unsigned int reg_01_dprx_sw_dpcd_alpm_lock_timeout_error_status: 2;
    unsigned int reg_01_dprx_sw_dpcd_aux_frame_sync_lock_error: 2;
    unsigned int reg_01_dprx_sw_dpcd_test_crc_b_cb_value    :17;
    unsigned int reg_01_dprx_sw_dpcd_test_crc_count         : 5;
};
#define rx_edp_rx_mac_wr2_reg_01_30(val) ((rs_rx_edp_rx_mac_wr2_reg_01_30*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_34                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x34)

#define RX_EDP_RX_MAC_WR2_REG_01_34_struct                               rs_rx_edp_rx_mac_wr2_reg_01_34

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_34  rs_rx_edp_rx_mac_wr2_reg_01_34;
struct _rs_rx_edp_rx_mac_wr2_reg_01_34 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_g_y_value     :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_34(val) ((rs_rx_edp_rx_mac_wr2_reg_01_34*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_38                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x38)

#define RX_EDP_RX_MAC_WR2_REG_01_38_struct                               rs_rx_edp_rx_mac_wr2_reg_01_38

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_38  rs_rx_edp_rx_mac_wr2_reg_01_38;
struct _rs_rx_edp_rx_mac_wr2_reg_01_38 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_r_cr_value    :17;
    unsigned int reg_01_dprx_sw_dpcd_alpm_enable            : 2;
    unsigned int reg_01_dprx_sw_dpcd_alpm_lock_error_irq_hpd_enable: 2;
    unsigned int reg_01_dprx_sw_dpcd_aux_frame_sync_enable  : 2;
    unsigned int reg_01_dprx_sw_dpcd_aux_frame_sync_irq_hpd_enable: 2;
    unsigned int reserved                                   : 7;
};
#define rx_edp_rx_mac_wr2_reg_01_38(val) ((rs_rx_edp_rx_mac_wr2_reg_01_38*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_3C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x3C)

#define RX_EDP_RX_MAC_WR2_REG_01_3C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_3c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_3c  rs_rx_edp_rx_mac_wr2_reg_01_3c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_3c {
    unsigned int reg_01_dprx_sw_dpcd_rx_gtc_freq_lock_done  : 2;
    unsigned int reg_01_dprx_sw_dpcd_rx_gtc_value_phase_skew_en: 2;
    unsigned int reg_01_dprx_sw_dpcd_tx_gtc_cap             : 2;
    unsigned int reg_01_dprx_sw_dpcd_tx_gtc_phase_skew_offset:17;
    unsigned int reserved                                   : 9;
};
#define rx_edp_rx_mac_wr2_reg_01_3c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_3c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_40                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x40)

#define RX_EDP_RX_MAC_WR2_REG_01_40_struct                               rs_rx_edp_rx_mac_wr2_reg_01_40

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_40  rs_rx_edp_rx_mac_wr2_reg_01_40;
struct _rs_rx_edp_rx_mac_wr2_reg_01_40 {
    unsigned int reg_01_dprx_sw_dpcd_tx_gtc_value           :32;
};
#define rx_edp_rx_mac_wr2_reg_01_40(val) ((rs_rx_edp_rx_mac_wr2_reg_01_40*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_44                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x44)

#define RX_EDP_RX_MAC_WR2_REG_01_44_struct                               rs_rx_edp_rx_mac_wr2_reg_01_44

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_44  rs_rx_edp_rx_mac_wr2_reg_01_44;
struct _rs_rx_edp_rx_mac_wr2_reg_01_44 {
    unsigned int reg_01_dprx_sw_dpcd_rx_gtc_value           :32;
};
#define rx_edp_rx_mac_wr2_reg_01_44(val) ((rs_rx_edp_rx_mac_wr2_reg_01_44*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_48                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x48)

#define RX_EDP_RX_MAC_WR2_REG_01_48_struct                               rs_rx_edp_rx_mac_wr2_reg_01_48

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_48  rs_rx_edp_rx_mac_wr2_reg_01_48;
struct _rs_rx_edp_rx_mac_wr2_reg_01_48 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_r_cr_mso_2    :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_48(val) ((rs_rx_edp_rx_mac_wr2_reg_01_48*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_4C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x4C)

#define RX_EDP_RX_MAC_WR2_REG_01_4C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_4c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_4c  rs_rx_edp_rx_mac_wr2_reg_01_4c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_4c {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_g_y_mso_2     :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_4c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_4c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_50                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x50)

#define RX_EDP_RX_MAC_WR2_REG_01_50_struct                               rs_rx_edp_rx_mac_wr2_reg_01_50

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_50  rs_rx_edp_rx_mac_wr2_reg_01_50;
struct _rs_rx_edp_rx_mac_wr2_reg_01_50 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_b_cb_mso_2    :17;
    unsigned int reg_01_dprx_sw_dpcd_test_crc_count_mso_2   : 5;
    unsigned int reserved                                   :10;
};
#define rx_edp_rx_mac_wr2_reg_01_50(val) ((rs_rx_edp_rx_mac_wr2_reg_01_50*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_54                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x54)

#define RX_EDP_RX_MAC_WR2_REG_01_54_struct                               rs_rx_edp_rx_mac_wr2_reg_01_54

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_54  rs_rx_edp_rx_mac_wr2_reg_01_54;
struct _rs_rx_edp_rx_mac_wr2_reg_01_54 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_r_cr_mso_3    :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_54(val) ((rs_rx_edp_rx_mac_wr2_reg_01_54*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_58                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x58)

#define RX_EDP_RX_MAC_WR2_REG_01_58_struct                               rs_rx_edp_rx_mac_wr2_reg_01_58

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_58  rs_rx_edp_rx_mac_wr2_reg_01_58;
struct _rs_rx_edp_rx_mac_wr2_reg_01_58 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_g_y_mso_3     :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_58(val) ((rs_rx_edp_rx_mac_wr2_reg_01_58*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_5C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x5C)

#define RX_EDP_RX_MAC_WR2_REG_01_5C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_5c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_5c  rs_rx_edp_rx_mac_wr2_reg_01_5c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_5c {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_b_cb_mso_3    :17;
    unsigned int reg_01_dprx_sw_dpcd_test_crc_count_mso_3   : 5;
    unsigned int reserved                                   :10;
};
#define rx_edp_rx_mac_wr2_reg_01_5c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_5c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_60                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x60)

#define RX_EDP_RX_MAC_WR2_REG_01_60_struct                               rs_rx_edp_rx_mac_wr2_reg_01_60

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_60  rs_rx_edp_rx_mac_wr2_reg_01_60;
struct _rs_rx_edp_rx_mac_wr2_reg_01_60 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_r_cr_mso_4    :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_60(val) ((rs_rx_edp_rx_mac_wr2_reg_01_60*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_64                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x64)

#define RX_EDP_RX_MAC_WR2_REG_01_64_struct                               rs_rx_edp_rx_mac_wr2_reg_01_64

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_64  rs_rx_edp_rx_mac_wr2_reg_01_64;
struct _rs_rx_edp_rx_mac_wr2_reg_01_64 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_g_y_mso_4     :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_64(val) ((rs_rx_edp_rx_mac_wr2_reg_01_64*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_68                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x68)

#define RX_EDP_RX_MAC_WR2_REG_01_68_struct                               rs_rx_edp_rx_mac_wr2_reg_01_68

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_68  rs_rx_edp_rx_mac_wr2_reg_01_68;
struct _rs_rx_edp_rx_mac_wr2_reg_01_68 {
    unsigned int reg_01_dprx_sw_dpcd_test_crc_b_cb_mso_4    :17;
    unsigned int reg_01_dprx_sw_dpcd_test_crc_count_mso_4   : 5;
    unsigned int reg_01_dprx_sw_dpcd_test_sink_start        : 2;
    unsigned int reg_01_dprx_sw_dpcd_fec_error_count_sel    : 4;
    unsigned int reg_01_dprx_sw_dpcd_fec_lane_select        : 3;
    unsigned int reg_01_dprx_dpcd_sw_msgaux_en              : 1;
};
#define rx_edp_rx_mac_wr2_reg_01_68(val) ((rs_rx_edp_rx_mac_wr2_reg_01_68*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_6C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x6C)

#define RX_EDP_RX_MAC_WR2_REG_01_6C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_6c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_6c  rs_rx_edp_rx_mac_wr2_reg_01_6c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_6c {
    unsigned int reg_01_dprx_sw_dpcd_fec_ready              : 2;
    unsigned int reg_01_dprx_sw_dpcd_mst_en                 : 2;
    unsigned int reg_01_dprx_sw_dpcd_mst_up_req_en          : 2;
    unsigned int reg_01_dprx_sw_dpcd_payload_allocate_start_time_slot: 7;
    unsigned int reg_01_dprx_sw_dpcd_payload_allocate_time_slot_count: 7;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_to_be_allocated: 8;
    unsigned int reg_01_dprx_sw_dpcd_down_rep_msg_rdy       : 2;
    unsigned int reg_01_dprx_sw_dpcd_up_req_msg_rdy         : 2;
};
#define rx_edp_rx_mac_wr2_reg_01_6c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_6c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_70                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x70)

#define RX_EDP_RX_MAC_WR2_REG_01_70_struct                               rs_rx_edp_rx_mac_wr2_reg_01_70

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_70  rs_rx_edp_rx_mac_wr2_reg_01_70;
struct _rs_rx_edp_rx_mac_wr2_reg_01_70 {
    unsigned int reg_01_dprx_sw_dpcd_fec_decode_dis_detected: 2;
    unsigned int reg_01_dprx_sw_dpcd_fec_decode_en_detected : 2;
    unsigned int reg_01_dprx_sw_dpcd_fec_error_count        :16;
    unsigned int reg_01_dprx_sw_dpcd_fec_error_count_valid  : 2;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_act_handled : 2;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_table_updated: 2;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot     : 1;
    unsigned int reserved                                   : 5;
};
#define rx_edp_rx_mac_wr2_reg_01_70(val) ((rs_rx_edp_rx_mac_wr2_reg_01_70*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_74                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x74)

#define RX_EDP_RX_MAC_WR2_REG_01_74_struct                               rs_rx_edp_rx_mac_wr2_reg_01_74

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_74  rs_rx_edp_rx_mac_wr2_reg_01_74;
struct _rs_rx_edp_rx_mac_wr2_reg_01_74 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_1   : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_2   : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_3   : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_4   : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_74(val) ((rs_rx_edp_rx_mac_wr2_reg_01_74*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_78                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x78)

#define RX_EDP_RX_MAC_WR2_REG_01_78_struct                               rs_rx_edp_rx_mac_wr2_reg_01_78

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_78  rs_rx_edp_rx_mac_wr2_reg_01_78;
struct _rs_rx_edp_rx_mac_wr2_reg_01_78 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_5   : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_6   : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_7   : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_8   : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_78(val) ((rs_rx_edp_rx_mac_wr2_reg_01_78*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_7C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x7C)

#define RX_EDP_RX_MAC_WR2_REG_01_7C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_7c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_7c  rs_rx_edp_rx_mac_wr2_reg_01_7c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_7c {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_9   : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_10  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_11  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_12  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_7c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_7c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_80                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x80)

#define RX_EDP_RX_MAC_WR2_REG_01_80_struct                               rs_rx_edp_rx_mac_wr2_reg_01_80

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_80  rs_rx_edp_rx_mac_wr2_reg_01_80;
struct _rs_rx_edp_rx_mac_wr2_reg_01_80 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_13  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_14  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_15  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_16  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_80(val) ((rs_rx_edp_rx_mac_wr2_reg_01_80*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_84                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x84)

#define RX_EDP_RX_MAC_WR2_REG_01_84_struct                               rs_rx_edp_rx_mac_wr2_reg_01_84

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_84  rs_rx_edp_rx_mac_wr2_reg_01_84;
struct _rs_rx_edp_rx_mac_wr2_reg_01_84 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_17  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_18  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_19  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_20  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_84(val) ((rs_rx_edp_rx_mac_wr2_reg_01_84*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_88                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x88)

#define RX_EDP_RX_MAC_WR2_REG_01_88_struct                               rs_rx_edp_rx_mac_wr2_reg_01_88

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_88  rs_rx_edp_rx_mac_wr2_reg_01_88;
struct _rs_rx_edp_rx_mac_wr2_reg_01_88 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_21  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_22  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_23  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_24  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_88(val) ((rs_rx_edp_rx_mac_wr2_reg_01_88*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_8C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x8C)

#define RX_EDP_RX_MAC_WR2_REG_01_8C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_8c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_8c  rs_rx_edp_rx_mac_wr2_reg_01_8c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_8c {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_25  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_26  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_27  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_28  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_8c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_8c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_90                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x90)

#define RX_EDP_RX_MAC_WR2_REG_01_90_struct                               rs_rx_edp_rx_mac_wr2_reg_01_90

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_90  rs_rx_edp_rx_mac_wr2_reg_01_90;
struct _rs_rx_edp_rx_mac_wr2_reg_01_90 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_29  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_30  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_31  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_32  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_90(val) ((rs_rx_edp_rx_mac_wr2_reg_01_90*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_94                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x94)

#define RX_EDP_RX_MAC_WR2_REG_01_94_struct                               rs_rx_edp_rx_mac_wr2_reg_01_94

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_94  rs_rx_edp_rx_mac_wr2_reg_01_94;
struct _rs_rx_edp_rx_mac_wr2_reg_01_94 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_33  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_34  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_35  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_36  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_94(val) ((rs_rx_edp_rx_mac_wr2_reg_01_94*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_98                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x98)

#define RX_EDP_RX_MAC_WR2_REG_01_98_struct                               rs_rx_edp_rx_mac_wr2_reg_01_98

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_98  rs_rx_edp_rx_mac_wr2_reg_01_98;
struct _rs_rx_edp_rx_mac_wr2_reg_01_98 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_37  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_38  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_39  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_40  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_98(val) ((rs_rx_edp_rx_mac_wr2_reg_01_98*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_9C                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0x9C)

#define RX_EDP_RX_MAC_WR2_REG_01_9C_struct                               rs_rx_edp_rx_mac_wr2_reg_01_9c

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_9c  rs_rx_edp_rx_mac_wr2_reg_01_9c;
struct _rs_rx_edp_rx_mac_wr2_reg_01_9c {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_41  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_42  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_43  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_44  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_9c(val) ((rs_rx_edp_rx_mac_wr2_reg_01_9c*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_A0                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xA0)

#define RX_EDP_RX_MAC_WR2_REG_01_A0_struct                               rs_rx_edp_rx_mac_wr2_reg_01_a0

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_a0  rs_rx_edp_rx_mac_wr2_reg_01_a0;
struct _rs_rx_edp_rx_mac_wr2_reg_01_a0 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_45  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_46  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_47  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_48  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_a0(val) ((rs_rx_edp_rx_mac_wr2_reg_01_a0*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_A4                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xA4)

#define RX_EDP_RX_MAC_WR2_REG_01_A4_struct                               rs_rx_edp_rx_mac_wr2_reg_01_a4

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_a4  rs_rx_edp_rx_mac_wr2_reg_01_a4;
struct _rs_rx_edp_rx_mac_wr2_reg_01_a4 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_49  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_50  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_51  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_52  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_a4(val) ((rs_rx_edp_rx_mac_wr2_reg_01_a4*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_A8                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xA8)

#define RX_EDP_RX_MAC_WR2_REG_01_A8_struct                               rs_rx_edp_rx_mac_wr2_reg_01_a8

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_a8  rs_rx_edp_rx_mac_wr2_reg_01_a8;
struct _rs_rx_edp_rx_mac_wr2_reg_01_a8 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_53  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_54  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_55  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_56  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_a8(val) ((rs_rx_edp_rx_mac_wr2_reg_01_a8*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_AC                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xAC)

#define RX_EDP_RX_MAC_WR2_REG_01_AC_struct                               rs_rx_edp_rx_mac_wr2_reg_01_ac

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_ac  rs_rx_edp_rx_mac_wr2_reg_01_ac;
struct _rs_rx_edp_rx_mac_wr2_reg_01_ac {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_57  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_58  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_59  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_60  : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_ac(val) ((rs_rx_edp_rx_mac_wr2_reg_01_ac*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_B0                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xB0)

#define RX_EDP_RX_MAC_WR2_REG_01_B0_struct                               rs_rx_edp_rx_mac_wr2_reg_01_b0

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_b0  rs_rx_edp_rx_mac_wr2_reg_01_b0;
struct _rs_rx_edp_rx_mac_wr2_reg_01_b0 {
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_61  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_62  : 8;
    unsigned int reg_01_dprx_sw_dpcd_vc_payload_id_slot_63  : 8;
    unsigned int reserved                                   : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_b0(val) ((rs_rx_edp_rx_mac_wr2_reg_01_b0*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_B4                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xB4)

#define RX_EDP_RX_MAC_WR2_REG_01_B4_struct                               rs_rx_edp_rx_mac_wr2_reg_01_b4

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_b4  rs_rx_edp_rx_mac_wr2_reg_01_b4;
struct _rs_rx_edp_rx_mac_wr2_reg_01_b4 {
    unsigned int reg_01_dprx_sw_dpcd_dsc_chunk_length_error : 2;
    unsigned int reg_01_dprx_sw_dpcd_dsc_error_status       : 2;
    unsigned int reg_01_dprx_sw_dpcd_dsc_crc_0_value        :17;
    unsigned int reserved                                   :11;
};
#define rx_edp_rx_mac_wr2_reg_01_b4(val) ((rs_rx_edp_rx_mac_wr2_reg_01_b4*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_B8                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xB8)

#define RX_EDP_RX_MAC_WR2_REG_01_B8_struct                               rs_rx_edp_rx_mac_wr2_reg_01_b8

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_b8  rs_rx_edp_rx_mac_wr2_reg_01_b8;
struct _rs_rx_edp_rx_mac_wr2_reg_01_b8 {
    unsigned int reg_01_dprx_sw_dpcd_dsc_crc_1_value        :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_b8(val) ((rs_rx_edp_rx_mac_wr2_reg_01_b8*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_BC                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xBC)

#define RX_EDP_RX_MAC_WR2_REG_01_BC_struct                               rs_rx_edp_rx_mac_wr2_reg_01_bc

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_bc  rs_rx_edp_rx_mac_wr2_reg_01_bc;
struct _rs_rx_edp_rx_mac_wr2_reg_01_bc {
    unsigned int reg_01_dprx_sw_dpcd_dsc_crc_2_value        :17;
    unsigned int reserved                                   :15;
};
#define rx_edp_rx_mac_wr2_reg_01_bc(val) ((rs_rx_edp_rx_mac_wr2_reg_01_bc*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_D8                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xD8)

#define RX_EDP_RX_MAC_WR2_REG_01_D8_struct                               rs_rx_edp_rx_mac_wr2_reg_01_d8

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_d8  rs_rx_edp_rx_mac_wr2_reg_01_d8;
struct _rs_rx_edp_rx_mac_wr2_reg_01_d8 {
    unsigned int reg_01_dprx_symbol_lock_pos_sw             :32;
};
#define rx_edp_rx_mac_wr2_reg_01_d8(val) ((rs_rx_edp_rx_mac_wr2_reg_01_d8*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_DC                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xDC)

#define RX_EDP_RX_MAC_WR2_REG_01_DC_struct                               rs_rx_edp_rx_mac_wr2_reg_01_dc

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_dc  rs_rx_edp_rx_mac_wr2_reg_01_dc;
struct _rs_rx_edp_rx_mac_wr2_reg_01_dc {
    unsigned int reg_01_dprx_bw_set_0                       : 8;
    unsigned int reg_01_dprx_bw_set_1                       : 8;
    unsigned int reg_01_dprx_bw_set_2                       : 8;
    unsigned int reg_01_dprx_bw_set_3                       : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_dc(val) ((rs_rx_edp_rx_mac_wr2_reg_01_dc*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_E0                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xE0)

#define RX_EDP_RX_MAC_WR2_REG_01_E0_struct                               rs_rx_edp_rx_mac_wr2_reg_01_e0

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_e0  rs_rx_edp_rx_mac_wr2_reg_01_e0;
struct _rs_rx_edp_rx_mac_wr2_reg_01_e0 {
    unsigned int reg_01_dprx_aux_addr_irq0_l                :12;
    unsigned int reg_01_dprx_aux_addr_irq0_h                :12;
    unsigned int reg_01_dprx_aux_wr_irq0                    : 2;
    unsigned int reg_01_dprx_aux_rd_irq0                    : 2;
    unsigned int reg_01_dprx_mac_clkdet_en                  : 4;
};
#define rx_edp_rx_mac_wr2_reg_01_e0(val) ((rs_rx_edp_rx_mac_wr2_reg_01_e0*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_E4                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xE4)

#define RX_EDP_RX_MAC_WR2_REG_01_E4_struct                               rs_rx_edp_rx_mac_wr2_reg_01_e4

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_e4  rs_rx_edp_rx_mac_wr2_reg_01_e4;
struct _rs_rx_edp_rx_mac_wr2_reg_01_e4 {
    unsigned int reg_01_dprx_aux_addr_irq1_l                :12;
    unsigned int reg_01_dprx_aux_addr_irq1_h                :12;
    unsigned int reg_01_dprx_aux_wr_irq1                    : 2;
    unsigned int reg_01_dprx_aux_rd_irq1                    : 2;
    unsigned int reg_01_dprx_mac_clkdet_lane_sel            : 4;
};
#define rx_edp_rx_mac_wr2_reg_01_e4(val) ((rs_rx_edp_rx_mac_wr2_reg_01_e4*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_E8                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xE8)

#define RX_EDP_RX_MAC_WR2_REG_01_E8_struct                               rs_rx_edp_rx_mac_wr2_reg_01_e8

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_e8  rs_rx_edp_rx_mac_wr2_reg_01_e8;
struct _rs_rx_edp_rx_mac_wr2_reg_01_e8 {
    unsigned int reg_01_dprx_aux_addr_irq2_l                :12;
    unsigned int reg_01_dprx_aux_addr_irq2_h                :12;
    unsigned int reg_01_dprx_aux_wr_irq2                    : 2;
    unsigned int reg_01_dprx_aux_rd_irq2                    : 2;
    unsigned int reg_01_dprx_mac_clkdet_abn_mode            : 4;
};
#define rx_edp_rx_mac_wr2_reg_01_e8(val) ((rs_rx_edp_rx_mac_wr2_reg_01_e8*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_EC                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xEC)

#define RX_EDP_RX_MAC_WR2_REG_01_EC_struct                               rs_rx_edp_rx_mac_wr2_reg_01_ec

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_ec  rs_rx_edp_rx_mac_wr2_reg_01_ec;
struct _rs_rx_edp_rx_mac_wr2_reg_01_ec {
    unsigned int reg_01_dprx_aux_addr_irq3_l                :12;
    unsigned int reg_01_dprx_aux_addr_irq3_h                :12;
    unsigned int reg_01_dprx_aux_wr_irq3                    : 2;
    unsigned int reg_01_dprx_aux_rd_irq3                    : 2;
    unsigned int reserved                                   : 4;
};
#define rx_edp_rx_mac_wr2_reg_01_ec(val) ((rs_rx_edp_rx_mac_wr2_reg_01_ec*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_F0                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xF0)

#define RX_EDP_RX_MAC_WR2_REG_01_F0_struct                               rs_rx_edp_rx_mac_wr2_reg_01_f0

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_f0  rs_rx_edp_rx_mac_wr2_reg_01_f0;
struct _rs_rx_edp_rx_mac_wr2_reg_01_f0 {
    unsigned int regr_01_dprx_aux_op_irq_st                 : 8;
    unsigned int reg_01_dprx_mac_clkdet_window_size         :16;
    unsigned int reg_01_dprx_mac_clkdet_stable_th           : 8;
};
#define rx_edp_rx_mac_wr2_reg_01_f0(val) ((rs_rx_edp_rx_mac_wr2_reg_01_f0*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_F4                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xF4)

#define RX_EDP_RX_MAC_WR2_REG_01_F4_struct                               rs_rx_edp_rx_mac_wr2_reg_01_f4

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_f4  rs_rx_edp_rx_mac_wr2_reg_01_f4;
struct _rs_rx_edp_rx_mac_wr2_reg_01_f4 {
    unsigned int reg_01_dprx_mac_clkdet_low_th              :16;
    unsigned int reg_01_dprx_mac_clkdet_high_th             :16;
};
#define rx_edp_rx_mac_wr2_reg_01_f4(val) ((rs_rx_edp_rx_mac_wr2_reg_01_f4*)&(val))



#define RX_EDP_RX_MAC_WR2_REG_01_F8                                      (HV_EDP_RX_MAC_WR2_REG_01_BASE_ADDRESS + 0xF8)

#define RX_EDP_RX_MAC_WR2_REG_01_F8_struct                               rs_rx_edp_rx_mac_wr2_reg_01_f8

typedef struct _rs_rx_edp_rx_mac_wr2_reg_01_f8  rs_rx_edp_rx_mac_wr2_reg_01_f8;
struct _rs_rx_edp_rx_mac_wr2_reg_01_f8 {
    unsigned int reg_01_force_training_fail                 : 2;
    unsigned int reg_01_lane0_voltage_swing_expected        : 2;
    unsigned int reg_01_lane1_voltage_swing_expected        : 2;
    unsigned int reg_01_lane2_voltage_swing_expected        : 2;
    unsigned int reg_01_lane3_voltage_swing_expected        : 2;
    unsigned int reg_01_lane0_pre_emphasis_expected         : 2;
    unsigned int reg_01_lane1_pre_emphasis_expected         : 2;
    unsigned int reg_01_lane2_pre_emphasis_expected         : 2;
    unsigned int reg_01_lane3_pre_emphasis_expected         : 2;
    unsigned int reserved                                   :14;
};
#define rx_edp_rx_mac_wr2_reg_01_f8(val) ((rs_rx_edp_rx_mac_wr2_reg_01_f8*)&(val))



#endif