#ifndef _HV_PAGE_HT7315_HDMI21_RX_CEC_00_H_
#define _HV_PAGE_HT7315_HDMI21_RX_CEC_00_H_

#ifndef HV_HDMI21_RX_CEC_00_BASE_ADDRESS
    #define HV_HDMI21_RX_CEC_00_BASE_ADDRESS                                         0x11008500
#endif


#define STANDBY_HDMI21_RX_CEC_00_00                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x00)

#define STANDBY_HDMI21_RX_CEC_00_00_struct                               rs_standby_hdmi21_rx_cec_00_00

typedef struct _rs_standby_hdmi21_rx_cec_00_00  rs_standby_hdmi21_rx_cec_00_00;
struct _rs_standby_hdmi21_rx_cec_00_00 {
    unsigned int reg_00_HPD                                 : 1;
    unsigned int reserved                                   :31;
};
#define standby_hdmi21_rx_cec_00_00(val) ((rs_standby_hdmi21_rx_cec_00_00*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_08                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x08)

#define STANDBY_HDMI21_RX_CEC_00_08_struct                               rs_standby_hdmi21_rx_cec_00_08

typedef struct _rs_standby_hdmi21_rx_cec_00_08  rs_standby_hdmi21_rx_cec_00_08;
struct _rs_standby_hdmi21_rx_cec_00_08 {
    unsigned int reg_00_HDMIRX_REVISION_ID                  :32;
};
#define standby_hdmi21_rx_cec_00_08(val) ((rs_standby_hdmi21_rx_cec_00_08*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_10                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x10)

#define STANDBY_HDMI21_RX_CEC_00_10_struct                               rs_standby_hdmi21_rx_cec_00_10

typedef struct _rs_standby_hdmi21_rx_cec_00_10  rs_standby_hdmi21_rx_cec_00_10;
struct _rs_standby_hdmi21_rx_cec_00_10 {
    unsigned int reg_00_SEND                                : 1;
    unsigned int reg_00_FRAME_TYP                           : 2;
    unsigned int reg_00_BC_NACK                             : 1;
    unsigned int reg_00_STANDBY                             : 1;
    unsigned int reserved                                   :27;
};
#define standby_hdmi21_rx_cec_00_10(val) ((rs_standby_hdmi21_rx_cec_00_10*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_14                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x14)

#define STANDBY_HDMI21_RX_CEC_00_14_struct                               rs_standby_hdmi21_rx_cec_00_14

typedef struct _rs_standby_hdmi21_rx_cec_00_14  rs_standby_hdmi21_rx_cec_00_14;
struct _rs_standby_hdmi21_rx_cec_00_14 {
    unsigned int reg_00_DONE_mask                           : 1;
    unsigned int reg_00_EOM_mask                            : 1;
    unsigned int reg_00_NACK_mask                           : 1;
    unsigned int reg_00_ARB_LOST_mask                       : 1;
    unsigned int reg_00_ERROR_INITIATOR_mask                : 1;
    unsigned int reg_00_ERROR_FLOW_mask                     : 1;
    unsigned int reg_00_WAKEUP_mask                         : 1;
    unsigned int reserved                                   :25;
};
#define standby_hdmi21_rx_cec_00_14(val) ((rs_standby_hdmi21_rx_cec_00_14*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_18                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x18)

#define STANDBY_HDMI21_RX_CEC_00_18_struct                               rs_standby_hdmi21_rx_cec_00_18

typedef struct _rs_standby_hdmi21_rx_cec_00_18  rs_standby_hdmi21_rx_cec_00_18;
struct _rs_standby_hdmi21_rx_cec_00_18 {
    unsigned int reg_00_CEC_ADDR_L                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_18(val) ((rs_standby_hdmi21_rx_cec_00_18*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_1C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x1C)

#define STANDBY_HDMI21_RX_CEC_00_1C_struct                               rs_standby_hdmi21_rx_cec_00_1c

typedef struct _rs_standby_hdmi21_rx_cec_00_1c  rs_standby_hdmi21_rx_cec_00_1c;
struct _rs_standby_hdmi21_rx_cec_00_1c {
    unsigned int reg_00_CEC_ADDR_H                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_1c(val) ((rs_standby_hdmi21_rx_cec_00_1c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_20                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x20)

#define STANDBY_HDMI21_RX_CEC_00_20_struct                               rs_standby_hdmi21_rx_cec_00_20

typedef struct _rs_standby_hdmi21_rx_cec_00_20  rs_standby_hdmi21_rx_cec_00_20;
struct _rs_standby_hdmi21_rx_cec_00_20 {
    unsigned int reg_00_CEC_TX_CNT                          : 5;
    unsigned int reserved                                   :27;
};
#define standby_hdmi21_rx_cec_00_20(val) ((rs_standby_hdmi21_rx_cec_00_20*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_24                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x24)

#define STANDBY_HDMI21_RX_CEC_00_24_struct                               rs_standby_hdmi21_rx_cec_00_24

typedef struct _rs_standby_hdmi21_rx_cec_00_24  rs_standby_hdmi21_rx_cec_00_24;
struct _rs_standby_hdmi21_rx_cec_00_24 {
    unsigned int regr_00_CEC_RX_CNT                         : 5;
    unsigned int regr_00_wtx_state                          : 3;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_24(val) ((rs_standby_hdmi21_rx_cec_00_24*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_28                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x28)

#define STANDBY_HDMI21_RX_CEC_00_28_struct                               rs_standby_hdmi21_rx_cec_00_28

typedef struct _rs_standby_hdmi21_rx_cec_00_28  rs_standby_hdmi21_rx_cec_00_28;
struct _rs_standby_hdmi21_rx_cec_00_28 {
    unsigned int reg_00_DATABYTE0                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_28(val) ((rs_standby_hdmi21_rx_cec_00_28*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_2C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x2C)

#define STANDBY_HDMI21_RX_CEC_00_2C_struct                               rs_standby_hdmi21_rx_cec_00_2c

typedef struct _rs_standby_hdmi21_rx_cec_00_2c  rs_standby_hdmi21_rx_cec_00_2c;
struct _rs_standby_hdmi21_rx_cec_00_2c {
    unsigned int reg_00_DATABYTE1                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_2c(val) ((rs_standby_hdmi21_rx_cec_00_2c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_30                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x30)

#define STANDBY_HDMI21_RX_CEC_00_30_struct                               rs_standby_hdmi21_rx_cec_00_30

typedef struct _rs_standby_hdmi21_rx_cec_00_30  rs_standby_hdmi21_rx_cec_00_30;
struct _rs_standby_hdmi21_rx_cec_00_30 {
    unsigned int reg_00_DATABYTE2                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_30(val) ((rs_standby_hdmi21_rx_cec_00_30*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_34                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x34)

#define STANDBY_HDMI21_RX_CEC_00_34_struct                               rs_standby_hdmi21_rx_cec_00_34

typedef struct _rs_standby_hdmi21_rx_cec_00_34  rs_standby_hdmi21_rx_cec_00_34;
struct _rs_standby_hdmi21_rx_cec_00_34 {
    unsigned int reg_00_DATABYTE3                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_34(val) ((rs_standby_hdmi21_rx_cec_00_34*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_38                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x38)

#define STANDBY_HDMI21_RX_CEC_00_38_struct                               rs_standby_hdmi21_rx_cec_00_38

typedef struct _rs_standby_hdmi21_rx_cec_00_38  rs_standby_hdmi21_rx_cec_00_38;
struct _rs_standby_hdmi21_rx_cec_00_38 {
    unsigned int reg_00_DATABYTE4                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_38(val) ((rs_standby_hdmi21_rx_cec_00_38*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_3C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x3C)

#define STANDBY_HDMI21_RX_CEC_00_3C_struct                               rs_standby_hdmi21_rx_cec_00_3c

typedef struct _rs_standby_hdmi21_rx_cec_00_3c  rs_standby_hdmi21_rx_cec_00_3c;
struct _rs_standby_hdmi21_rx_cec_00_3c {
    unsigned int reg_00_DATABYTE5                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_3c(val) ((rs_standby_hdmi21_rx_cec_00_3c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_40                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x40)

#define STANDBY_HDMI21_RX_CEC_00_40_struct                               rs_standby_hdmi21_rx_cec_00_40

typedef struct _rs_standby_hdmi21_rx_cec_00_40  rs_standby_hdmi21_rx_cec_00_40;
struct _rs_standby_hdmi21_rx_cec_00_40 {
    unsigned int reg_00_DATABYTE6                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_40(val) ((rs_standby_hdmi21_rx_cec_00_40*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_44                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x44)

#define STANDBY_HDMI21_RX_CEC_00_44_struct                               rs_standby_hdmi21_rx_cec_00_44

typedef struct _rs_standby_hdmi21_rx_cec_00_44  rs_standby_hdmi21_rx_cec_00_44;
struct _rs_standby_hdmi21_rx_cec_00_44 {
    unsigned int reg_00_DATABYTE7                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_44(val) ((rs_standby_hdmi21_rx_cec_00_44*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_48                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x48)

#define STANDBY_HDMI21_RX_CEC_00_48_struct                               rs_standby_hdmi21_rx_cec_00_48

typedef struct _rs_standby_hdmi21_rx_cec_00_48  rs_standby_hdmi21_rx_cec_00_48;
struct _rs_standby_hdmi21_rx_cec_00_48 {
    unsigned int reg_00_DATABYTE8                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_48(val) ((rs_standby_hdmi21_rx_cec_00_48*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_4C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x4C)

#define STANDBY_HDMI21_RX_CEC_00_4C_struct                               rs_standby_hdmi21_rx_cec_00_4c

typedef struct _rs_standby_hdmi21_rx_cec_00_4c  rs_standby_hdmi21_rx_cec_00_4c;
struct _rs_standby_hdmi21_rx_cec_00_4c {
    unsigned int reg_00_DATABYTE9                           : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_4c(val) ((rs_standby_hdmi21_rx_cec_00_4c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_50                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x50)

#define STANDBY_HDMI21_RX_CEC_00_50_struct                               rs_standby_hdmi21_rx_cec_00_50

typedef struct _rs_standby_hdmi21_rx_cec_00_50  rs_standby_hdmi21_rx_cec_00_50;
struct _rs_standby_hdmi21_rx_cec_00_50 {
    unsigned int reg_00_DATABYTE10                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_50(val) ((rs_standby_hdmi21_rx_cec_00_50*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_54                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x54)

#define STANDBY_HDMI21_RX_CEC_00_54_struct                               rs_standby_hdmi21_rx_cec_00_54

typedef struct _rs_standby_hdmi21_rx_cec_00_54  rs_standby_hdmi21_rx_cec_00_54;
struct _rs_standby_hdmi21_rx_cec_00_54 {
    unsigned int reg_00_DATABYTE11                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_54(val) ((rs_standby_hdmi21_rx_cec_00_54*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_58                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x58)

#define STANDBY_HDMI21_RX_CEC_00_58_struct                               rs_standby_hdmi21_rx_cec_00_58

typedef struct _rs_standby_hdmi21_rx_cec_00_58  rs_standby_hdmi21_rx_cec_00_58;
struct _rs_standby_hdmi21_rx_cec_00_58 {
    unsigned int reg_00_DATABYTE12                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_58(val) ((rs_standby_hdmi21_rx_cec_00_58*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_5C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x5C)

#define STANDBY_HDMI21_RX_CEC_00_5C_struct                               rs_standby_hdmi21_rx_cec_00_5c

typedef struct _rs_standby_hdmi21_rx_cec_00_5c  rs_standby_hdmi21_rx_cec_00_5c;
struct _rs_standby_hdmi21_rx_cec_00_5c {
    unsigned int reg_00_DATABYTE13                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_5c(val) ((rs_standby_hdmi21_rx_cec_00_5c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_60                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x60)

#define STANDBY_HDMI21_RX_CEC_00_60_struct                               rs_standby_hdmi21_rx_cec_00_60

typedef struct _rs_standby_hdmi21_rx_cec_00_60  rs_standby_hdmi21_rx_cec_00_60;
struct _rs_standby_hdmi21_rx_cec_00_60 {
    unsigned int reg_00_DATABYTE14                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_60(val) ((rs_standby_hdmi21_rx_cec_00_60*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_64                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x64)

#define STANDBY_HDMI21_RX_CEC_00_64_struct                               rs_standby_hdmi21_rx_cec_00_64

typedef struct _rs_standby_hdmi21_rx_cec_00_64  rs_standby_hdmi21_rx_cec_00_64;
struct _rs_standby_hdmi21_rx_cec_00_64 {
    unsigned int reg_00_DATABYTE15                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_64(val) ((rs_standby_hdmi21_rx_cec_00_64*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_68                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x68)

#define STANDBY_HDMI21_RX_CEC_00_68_struct                               rs_standby_hdmi21_rx_cec_00_68

typedef struct _rs_standby_hdmi21_rx_cec_00_68  rs_standby_hdmi21_rx_cec_00_68;
struct _rs_standby_hdmi21_rx_cec_00_68 {
    unsigned int regr_00_DATABYTE0                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_68(val) ((rs_standby_hdmi21_rx_cec_00_68*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_6C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x6C)

#define STANDBY_HDMI21_RX_CEC_00_6C_struct                               rs_standby_hdmi21_rx_cec_00_6c

typedef struct _rs_standby_hdmi21_rx_cec_00_6c  rs_standby_hdmi21_rx_cec_00_6c;
struct _rs_standby_hdmi21_rx_cec_00_6c {
    unsigned int regr_00_DATABYTE1                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_6c(val) ((rs_standby_hdmi21_rx_cec_00_6c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_70                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x70)

#define STANDBY_HDMI21_RX_CEC_00_70_struct                               rs_standby_hdmi21_rx_cec_00_70

typedef struct _rs_standby_hdmi21_rx_cec_00_70  rs_standby_hdmi21_rx_cec_00_70;
struct _rs_standby_hdmi21_rx_cec_00_70 {
    unsigned int regr_00_DATABYTE2                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_70(val) ((rs_standby_hdmi21_rx_cec_00_70*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_74                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x74)

#define STANDBY_HDMI21_RX_CEC_00_74_struct                               rs_standby_hdmi21_rx_cec_00_74

typedef struct _rs_standby_hdmi21_rx_cec_00_74  rs_standby_hdmi21_rx_cec_00_74;
struct _rs_standby_hdmi21_rx_cec_00_74 {
    unsigned int regr_00_DATABYTE3                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_74(val) ((rs_standby_hdmi21_rx_cec_00_74*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_78                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x78)

#define STANDBY_HDMI21_RX_CEC_00_78_struct                               rs_standby_hdmi21_rx_cec_00_78

typedef struct _rs_standby_hdmi21_rx_cec_00_78  rs_standby_hdmi21_rx_cec_00_78;
struct _rs_standby_hdmi21_rx_cec_00_78 {
    unsigned int regr_00_DATABYTE4                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_78(val) ((rs_standby_hdmi21_rx_cec_00_78*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_7C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x7C)

#define STANDBY_HDMI21_RX_CEC_00_7C_struct                               rs_standby_hdmi21_rx_cec_00_7c

typedef struct _rs_standby_hdmi21_rx_cec_00_7c  rs_standby_hdmi21_rx_cec_00_7c;
struct _rs_standby_hdmi21_rx_cec_00_7c {
    unsigned int regr_00_DATABYTE5                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_7c(val) ((rs_standby_hdmi21_rx_cec_00_7c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_80                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x80)

#define STANDBY_HDMI21_RX_CEC_00_80_struct                               rs_standby_hdmi21_rx_cec_00_80

typedef struct _rs_standby_hdmi21_rx_cec_00_80  rs_standby_hdmi21_rx_cec_00_80;
struct _rs_standby_hdmi21_rx_cec_00_80 {
    unsigned int regr_00_DATABYTE6                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_80(val) ((rs_standby_hdmi21_rx_cec_00_80*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_84                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x84)

#define STANDBY_HDMI21_RX_CEC_00_84_struct                               rs_standby_hdmi21_rx_cec_00_84

typedef struct _rs_standby_hdmi21_rx_cec_00_84  rs_standby_hdmi21_rx_cec_00_84;
struct _rs_standby_hdmi21_rx_cec_00_84 {
    unsigned int regr_00_DATABYTE7                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_84(val) ((rs_standby_hdmi21_rx_cec_00_84*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_88                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x88)

#define STANDBY_HDMI21_RX_CEC_00_88_struct                               rs_standby_hdmi21_rx_cec_00_88

typedef struct _rs_standby_hdmi21_rx_cec_00_88  rs_standby_hdmi21_rx_cec_00_88;
struct _rs_standby_hdmi21_rx_cec_00_88 {
    unsigned int regr_00_DATABYTE8                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_88(val) ((rs_standby_hdmi21_rx_cec_00_88*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_8C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x8C)

#define STANDBY_HDMI21_RX_CEC_00_8C_struct                               rs_standby_hdmi21_rx_cec_00_8c

typedef struct _rs_standby_hdmi21_rx_cec_00_8c  rs_standby_hdmi21_rx_cec_00_8c;
struct _rs_standby_hdmi21_rx_cec_00_8c {
    unsigned int regr_00_DATABYTE9                          : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_8c(val) ((rs_standby_hdmi21_rx_cec_00_8c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_90                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x90)

#define STANDBY_HDMI21_RX_CEC_00_90_struct                               rs_standby_hdmi21_rx_cec_00_90

typedef struct _rs_standby_hdmi21_rx_cec_00_90  rs_standby_hdmi21_rx_cec_00_90;
struct _rs_standby_hdmi21_rx_cec_00_90 {
    unsigned int regr_00_DATABYTE10                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_90(val) ((rs_standby_hdmi21_rx_cec_00_90*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_94                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x94)

#define STANDBY_HDMI21_RX_CEC_00_94_struct                               rs_standby_hdmi21_rx_cec_00_94

typedef struct _rs_standby_hdmi21_rx_cec_00_94  rs_standby_hdmi21_rx_cec_00_94;
struct _rs_standby_hdmi21_rx_cec_00_94 {
    unsigned int regr_00_DATABYTE11                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_94(val) ((rs_standby_hdmi21_rx_cec_00_94*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_98                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x98)

#define STANDBY_HDMI21_RX_CEC_00_98_struct                               rs_standby_hdmi21_rx_cec_00_98

typedef struct _rs_standby_hdmi21_rx_cec_00_98  rs_standby_hdmi21_rx_cec_00_98;
struct _rs_standby_hdmi21_rx_cec_00_98 {
    unsigned int regr_00_DATABYTE12                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_98(val) ((rs_standby_hdmi21_rx_cec_00_98*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_9C                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0x9C)

#define STANDBY_HDMI21_RX_CEC_00_9C_struct                               rs_standby_hdmi21_rx_cec_00_9c

typedef struct _rs_standby_hdmi21_rx_cec_00_9c  rs_standby_hdmi21_rx_cec_00_9c;
struct _rs_standby_hdmi21_rx_cec_00_9c {
    unsigned int regr_00_DATABYTE13                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_9c(val) ((rs_standby_hdmi21_rx_cec_00_9c*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_A0                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0xA0)

#define STANDBY_HDMI21_RX_CEC_00_A0_struct                               rs_standby_hdmi21_rx_cec_00_a0

typedef struct _rs_standby_hdmi21_rx_cec_00_a0  rs_standby_hdmi21_rx_cec_00_a0;
struct _rs_standby_hdmi21_rx_cec_00_a0 {
    unsigned int regr_00_DATABYTE14                         : 8;
    unsigned int reserved                                   :24;
};
#define standby_hdmi21_rx_cec_00_a0(val) ((rs_standby_hdmi21_rx_cec_00_a0*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_A4                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0xA4)

#define STANDBY_HDMI21_RX_CEC_00_A4_struct                               rs_standby_hdmi21_rx_cec_00_a4

typedef struct _rs_standby_hdmi21_rx_cec_00_a4  rs_standby_hdmi21_rx_cec_00_a4;
struct _rs_standby_hdmi21_rx_cec_00_a4 {
    unsigned int regr_00_DATABYTE15                         : 8;
    unsigned int regr_00_wake_ctrl_status                   : 8;
    unsigned int reserved                                   :16;
};
#define standby_hdmi21_rx_cec_00_a4(val) ((rs_standby_hdmi21_rx_cec_00_a4*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_A8                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0xA8)

#define STANDBY_HDMI21_RX_CEC_00_A8_struct                               rs_standby_hdmi21_rx_cec_00_a8

typedef struct _rs_standby_hdmi21_rx_cec_00_a8  rs_standby_hdmi21_rx_cec_00_a8;
struct _rs_standby_hdmi21_rx_cec_00_a8 {
    unsigned int reg_00_LOCKED_BUFFER                       : 1;
    unsigned int reserved                                   :31;
};
#define standby_hdmi21_rx_cec_00_a8(val) ((rs_standby_hdmi21_rx_cec_00_a8*)&(val))



#define STANDBY_HDMI21_RX_CEC_00_AC                                      (HV_HDMI21_RX_CEC_00_BASE_ADDRESS + 0xAC)

#define STANDBY_HDMI21_RX_CEC_00_AC_struct                               rs_standby_hdmi21_rx_cec_00_ac

typedef struct _rs_standby_hdmi21_rx_cec_00_ac  rs_standby_hdmi21_rx_cec_00_ac;
struct _rs_standby_hdmi21_rx_cec_00_ac {
    unsigned int reg_00_OPCODE0X04EN                        : 1;
    unsigned int reg_00_OPCODE0X0DEN                        : 1;
    unsigned int reg_00_OPCODE0X41EN                        : 1;
    unsigned int reg_00_OPCODE0X42EN                        : 1;
    unsigned int reg_00_OPCODE0X44EN                        : 1;
    unsigned int reg_00_OPCODE0X70EN                        : 1;
    unsigned int reg_00_OPCODE0X82EN                        : 1;
    unsigned int reg_00_OPCODE0X86EN                        : 1;
    unsigned int reg_00_hd_rcv_clr                          : 1;
    unsigned int reg_00_hd_locked_clr                       : 1;
    unsigned int reserved                                   :22;
};
#define standby_hdmi21_rx_cec_00_ac(val) ((rs_standby_hdmi21_rx_cec_00_ac*)&(val))



#endif