#ifndef _HV_PAGE_HT7315_HDMI_RX_HDCP2X_00_01_H_
#define _HV_PAGE_HT7315_HDMI_RX_HDCP2X_00_01_H_

#ifndef HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS
    #define HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS                                         0x1104E700
#endif


#define RX_HDMI_RX_HDCP2X_00_01_00                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x00)

#define RX_HDMI_RX_HDCP2X_00_01_00_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_00

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_00  rs_rx_hdmi_rx_hdcp2x_00_01_00;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_00 {
    unsigned int reg_01_hdmirx_hdcp2x_message0              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message1              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message2              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message3              : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_00(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_00*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_04                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x04)

#define RX_HDMI_RX_HDCP2X_00_01_04_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_04

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_04  rs_rx_hdmi_rx_hdcp2x_00_01_04;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_04 {
    unsigned int reg_01_hdmirx_hdcp2x_message4              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message5              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message6              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message7              : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_04(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_04*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_08                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x08)

#define RX_HDMI_RX_HDCP2X_00_01_08_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_08

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_08  rs_rx_hdmi_rx_hdcp2x_00_01_08;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_08 {
    unsigned int reg_01_hdmirx_hdcp2x_message8              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message9              : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message10             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message11             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_08(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_08*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_0C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x0C)

#define RX_HDMI_RX_HDCP2X_00_01_0C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_0c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_0c  rs_rx_hdmi_rx_hdcp2x_00_01_0c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_0c {
    unsigned int reg_01_hdmirx_hdcp2x_message12             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message13             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message14             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message15             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_0c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_0c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_10                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x10)

#define RX_HDMI_RX_HDCP2X_00_01_10_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_10

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_10  rs_rx_hdmi_rx_hdcp2x_00_01_10;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_10 {
    unsigned int reg_01_hdmirx_hdcp2x_message16             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message17             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message18             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message19             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_10(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_10*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_14                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x14)

#define RX_HDMI_RX_HDCP2X_00_01_14_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_14

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_14  rs_rx_hdmi_rx_hdcp2x_00_01_14;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_14 {
    unsigned int reg_01_hdmirx_hdcp2x_message20             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message21             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message22             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message23             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_14(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_14*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_18                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x18)

#define RX_HDMI_RX_HDCP2X_00_01_18_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_18

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_18  rs_rx_hdmi_rx_hdcp2x_00_01_18;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_18 {
    unsigned int reg_01_hdmirx_hdcp2x_message24             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message25             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message26             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message27             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_18(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_18*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_1C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x1C)

#define RX_HDMI_RX_HDCP2X_00_01_1C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_1c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_1c  rs_rx_hdmi_rx_hdcp2x_00_01_1c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_1c {
    unsigned int reg_01_hdmirx_hdcp2x_message28             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message29             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message30             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message31             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_1c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_1c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_20                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x20)

#define RX_HDMI_RX_HDCP2X_00_01_20_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_20

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_20  rs_rx_hdmi_rx_hdcp2x_00_01_20;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_20 {
    unsigned int reg_01_hdmirx_hdcp2x_message32             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message33             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message34             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message35             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_20(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_20*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_24                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x24)

#define RX_HDMI_RX_HDCP2X_00_01_24_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_24

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_24  rs_rx_hdmi_rx_hdcp2x_00_01_24;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_24 {
    unsigned int reg_01_hdmirx_hdcp2x_message36             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message37             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message38             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message39             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_24(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_24*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_28                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x28)

#define RX_HDMI_RX_HDCP2X_00_01_28_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_28

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_28  rs_rx_hdmi_rx_hdcp2x_00_01_28;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_28 {
    unsigned int reg_01_hdmirx_hdcp2x_message40             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message41             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message42             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message43             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_28(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_28*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_2C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x2C)

#define RX_HDMI_RX_HDCP2X_00_01_2C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_2c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_2c  rs_rx_hdmi_rx_hdcp2x_00_01_2c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_2c {
    unsigned int reg_01_hdmirx_hdcp2x_message44             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message45             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message46             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message47             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_2c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_2c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_30                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x30)

#define RX_HDMI_RX_HDCP2X_00_01_30_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_30

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_30  rs_rx_hdmi_rx_hdcp2x_00_01_30;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_30 {
    unsigned int reg_01_hdmirx_hdcp2x_message48             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message49             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message50             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message51             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_30(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_30*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_34                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x34)

#define RX_HDMI_RX_HDCP2X_00_01_34_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_34

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_34  rs_rx_hdmi_rx_hdcp2x_00_01_34;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_34 {
    unsigned int reg_01_hdmirx_hdcp2x_message52             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message53             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message54             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message55             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_34(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_34*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_38                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x38)

#define RX_HDMI_RX_HDCP2X_00_01_38_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_38

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_38  rs_rx_hdmi_rx_hdcp2x_00_01_38;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_38 {
    unsigned int reg_01_hdmirx_hdcp2x_message56             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message57             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message58             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message59             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_38(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_38*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_3C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x3C)

#define RX_HDMI_RX_HDCP2X_00_01_3C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_3c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_3c  rs_rx_hdmi_rx_hdcp2x_00_01_3c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_3c {
    unsigned int reg_01_hdmirx_hdcp2x_message60             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message61             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message62             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message63             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_3c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_3c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_40                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x40)

#define RX_HDMI_RX_HDCP2X_00_01_40_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_40

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_40  rs_rx_hdmi_rx_hdcp2x_00_01_40;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_40 {
    unsigned int reg_01_hdmirx_hdcp2x_message64             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message65             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message66             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message67             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_40(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_40*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_44                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x44)

#define RX_HDMI_RX_HDCP2X_00_01_44_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_44

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_44  rs_rx_hdmi_rx_hdcp2x_00_01_44;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_44 {
    unsigned int reg_01_hdmirx_hdcp2x_message68             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message69             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message70             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message71             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_44(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_44*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_48                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x48)

#define RX_HDMI_RX_HDCP2X_00_01_48_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_48

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_48  rs_rx_hdmi_rx_hdcp2x_00_01_48;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_48 {
    unsigned int reg_01_hdmirx_hdcp2x_message72             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message73             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message74             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message75             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_48(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_48*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_4C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x4C)

#define RX_HDMI_RX_HDCP2X_00_01_4C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_4c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_4c  rs_rx_hdmi_rx_hdcp2x_00_01_4c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_4c {
    unsigned int reg_01_hdmirx_hdcp2x_message76             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message77             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message78             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message79             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_4c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_4c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_50                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x50)

#define RX_HDMI_RX_HDCP2X_00_01_50_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_50

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_50  rs_rx_hdmi_rx_hdcp2x_00_01_50;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_50 {
    unsigned int reg_01_hdmirx_hdcp2x_message80             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message81             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message82             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message83             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_50(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_50*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_54                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x54)

#define RX_HDMI_RX_HDCP2X_00_01_54_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_54

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_54  rs_rx_hdmi_rx_hdcp2x_00_01_54;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_54 {
    unsigned int reg_01_hdmirx_hdcp2x_message84             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message85             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message86             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message87             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_54(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_54*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_58                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x58)

#define RX_HDMI_RX_HDCP2X_00_01_58_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_58

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_58  rs_rx_hdmi_rx_hdcp2x_00_01_58;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_58 {
    unsigned int reg_01_hdmirx_hdcp2x_message88             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message89             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message90             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message91             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_58(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_58*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_5C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x5C)

#define RX_HDMI_RX_HDCP2X_00_01_5C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_5c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_5c  rs_rx_hdmi_rx_hdcp2x_00_01_5c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_5c {
    unsigned int reg_01_hdmirx_hdcp2x_message92             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message93             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message94             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message95             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_5c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_5c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_60                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x60)

#define RX_HDMI_RX_HDCP2X_00_01_60_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_60

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_60  rs_rx_hdmi_rx_hdcp2x_00_01_60;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_60 {
    unsigned int reg_01_hdmirx_hdcp2x_message96             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message97             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message98             : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message99             : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_60(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_60*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_64                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x64)

#define RX_HDMI_RX_HDCP2X_00_01_64_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_64

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_64  rs_rx_hdmi_rx_hdcp2x_00_01_64;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_64 {
    unsigned int reg_01_hdmirx_hdcp2x_message100            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message101            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message102            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message103            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_64(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_64*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_68                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x68)

#define RX_HDMI_RX_HDCP2X_00_01_68_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_68

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_68  rs_rx_hdmi_rx_hdcp2x_00_01_68;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_68 {
    unsigned int reg_01_hdmirx_hdcp2x_message104            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message105            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message106            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message107            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_68(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_68*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_6C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x6C)

#define RX_HDMI_RX_HDCP2X_00_01_6C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_6c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_6c  rs_rx_hdmi_rx_hdcp2x_00_01_6c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_6c {
    unsigned int reg_01_hdmirx_hdcp2x_message108            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message109            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message110            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message111            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_6c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_6c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_70                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x70)

#define RX_HDMI_RX_HDCP2X_00_01_70_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_70

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_70  rs_rx_hdmi_rx_hdcp2x_00_01_70;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_70 {
    unsigned int reg_01_hdmirx_hdcp2x_message112            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message113            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message114            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message115            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_70(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_70*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_74                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x74)

#define RX_HDMI_RX_HDCP2X_00_01_74_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_74

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_74  rs_rx_hdmi_rx_hdcp2x_00_01_74;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_74 {
    unsigned int reg_01_hdmirx_hdcp2x_message116            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message117            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message118            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message119            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_74(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_74*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_78                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x78)

#define RX_HDMI_RX_HDCP2X_00_01_78_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_78

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_78  rs_rx_hdmi_rx_hdcp2x_00_01_78;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_78 {
    unsigned int reg_01_hdmirx_hdcp2x_message120            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message121            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message122            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message123            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_78(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_78*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_7C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x7C)

#define RX_HDMI_RX_HDCP2X_00_01_7C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_7c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_7c  rs_rx_hdmi_rx_hdcp2x_00_01_7c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_7c {
    unsigned int reg_01_hdmirx_hdcp2x_message124            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message125            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message126            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message127            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_7c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_7c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_80                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x80)

#define RX_HDMI_RX_HDCP2X_00_01_80_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_80

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_80  rs_rx_hdmi_rx_hdcp2x_00_01_80;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_80 {
    unsigned int reg_01_hdmirx_hdcp2x_message128            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message129            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message130            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message131            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_80(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_80*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_84                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x84)

#define RX_HDMI_RX_HDCP2X_00_01_84_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_84

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_84  rs_rx_hdmi_rx_hdcp2x_00_01_84;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_84 {
    unsigned int reg_01_hdmirx_hdcp2x_message132            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message133            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message134            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message135            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_84(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_84*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_88                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x88)

#define RX_HDMI_RX_HDCP2X_00_01_88_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_88

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_88  rs_rx_hdmi_rx_hdcp2x_00_01_88;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_88 {
    unsigned int reg_01_hdmirx_hdcp2x_message136            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message137            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message138            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message139            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_88(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_88*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_8C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x8C)

#define RX_HDMI_RX_HDCP2X_00_01_8C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_8c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_8c  rs_rx_hdmi_rx_hdcp2x_00_01_8c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_8c {
    unsigned int reg_01_hdmirx_hdcp2x_message140            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message141            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message142            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message143            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_8c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_8c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_90                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x90)

#define RX_HDMI_RX_HDCP2X_00_01_90_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_90

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_90  rs_rx_hdmi_rx_hdcp2x_00_01_90;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_90 {
    unsigned int reg_01_hdmirx_hdcp2x_message144            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message145            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message146            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message147            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_90(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_90*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_94                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x94)

#define RX_HDMI_RX_HDCP2X_00_01_94_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_94

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_94  rs_rx_hdmi_rx_hdcp2x_00_01_94;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_94 {
    unsigned int reg_01_hdmirx_hdcp2x_message148            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message149            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message150            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message151            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_94(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_94*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_98                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x98)

#define RX_HDMI_RX_HDCP2X_00_01_98_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_98

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_98  rs_rx_hdmi_rx_hdcp2x_00_01_98;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_98 {
    unsigned int reg_01_hdmirx_hdcp2x_message152            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message153            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message154            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message155            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_98(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_98*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_9C                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0x9C)

#define RX_HDMI_RX_HDCP2X_00_01_9C_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_9c

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_9c  rs_rx_hdmi_rx_hdcp2x_00_01_9c;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_9c {
    unsigned int reg_01_hdmirx_hdcp2x_message156            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message157            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message158            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message159            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_9c(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_9c*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_A0                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xA0)

#define RX_HDMI_RX_HDCP2X_00_01_A0_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_a0

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_a0  rs_rx_hdmi_rx_hdcp2x_00_01_a0;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_a0 {
    unsigned int reg_01_hdmirx_hdcp2x_message160            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message161            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message162            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message163            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_a0(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_a0*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_A4                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xA4)

#define RX_HDMI_RX_HDCP2X_00_01_A4_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_a4

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_a4  rs_rx_hdmi_rx_hdcp2x_00_01_a4;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_a4 {
    unsigned int reg_01_hdmirx_hdcp2x_message164            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message165            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message166            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message167            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_a4(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_a4*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_A8                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xA8)

#define RX_HDMI_RX_HDCP2X_00_01_A8_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_a8

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_a8  rs_rx_hdmi_rx_hdcp2x_00_01_a8;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_a8 {
    unsigned int reg_01_hdmirx_hdcp2x_message168            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message169            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message170            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message171            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_a8(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_a8*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_AC                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xAC)

#define RX_HDMI_RX_HDCP2X_00_01_AC_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_ac

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_ac  rs_rx_hdmi_rx_hdcp2x_00_01_ac;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_ac {
    unsigned int reg_01_hdmirx_hdcp2x_message172            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message173            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message174            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message175            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_ac(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_ac*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_B0                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xB0)

#define RX_HDMI_RX_HDCP2X_00_01_B0_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_b0

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_b0  rs_rx_hdmi_rx_hdcp2x_00_01_b0;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_b0 {
    unsigned int reg_01_hdmirx_hdcp2x_message176            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message177            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message178            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message179            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_b0(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_b0*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_B4                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xB4)

#define RX_HDMI_RX_HDCP2X_00_01_B4_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_b4

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_b4  rs_rx_hdmi_rx_hdcp2x_00_01_b4;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_b4 {
    unsigned int reg_01_hdmirx_hdcp2x_message180            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message181            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message182            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message183            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_b4(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_b4*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_B8                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xB8)

#define RX_HDMI_RX_HDCP2X_00_01_B8_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_b8

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_b8  rs_rx_hdmi_rx_hdcp2x_00_01_b8;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_b8 {
    unsigned int reg_01_hdmirx_hdcp2x_message184            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message185            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message186            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message187            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_b8(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_b8*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_BC                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xBC)

#define RX_HDMI_RX_HDCP2X_00_01_BC_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_bc

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_bc  rs_rx_hdmi_rx_hdcp2x_00_01_bc;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_bc {
    unsigned int reg_01_hdmirx_hdcp2x_message188            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message189            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message190            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message191            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_bc(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_bc*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_C0                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xC0)

#define RX_HDMI_RX_HDCP2X_00_01_C0_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_c0

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_c0  rs_rx_hdmi_rx_hdcp2x_00_01_c0;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_c0 {
    unsigned int reg_01_hdmirx_hdcp2x_message192            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message193            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message194            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message195            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_c0(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_c0*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_C4                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xC4)

#define RX_HDMI_RX_HDCP2X_00_01_C4_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_c4

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_c4  rs_rx_hdmi_rx_hdcp2x_00_01_c4;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_c4 {
    unsigned int reg_01_hdmirx_hdcp2x_message196            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message197            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message198            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message199            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_c4(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_c4*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_C8                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xC8)

#define RX_HDMI_RX_HDCP2X_00_01_C8_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_c8

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_c8  rs_rx_hdmi_rx_hdcp2x_00_01_c8;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_c8 {
    unsigned int reg_01_hdmirx_hdcp2x_message200            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message201            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message202            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message203            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_c8(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_c8*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_CC                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xCC)

#define RX_HDMI_RX_HDCP2X_00_01_CC_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_cc

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_cc  rs_rx_hdmi_rx_hdcp2x_00_01_cc;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_cc {
    unsigned int reg_01_hdmirx_hdcp2x_message204            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message205            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message206            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message207            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_cc(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_cc*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_D0                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xD0)

#define RX_HDMI_RX_HDCP2X_00_01_D0_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_d0

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_d0  rs_rx_hdmi_rx_hdcp2x_00_01_d0;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_d0 {
    unsigned int reg_01_hdmirx_hdcp2x_message208            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message209            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message210            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message211            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_d0(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_d0*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_D4                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xD4)

#define RX_HDMI_RX_HDCP2X_00_01_D4_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_d4

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_d4  rs_rx_hdmi_rx_hdcp2x_00_01_d4;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_d4 {
    unsigned int reg_01_hdmirx_hdcp2x_message212            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message213            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message214            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message215            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_d4(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_d4*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_D8                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xD8)

#define RX_HDMI_RX_HDCP2X_00_01_D8_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_d8

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_d8  rs_rx_hdmi_rx_hdcp2x_00_01_d8;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_d8 {
    unsigned int reg_01_hdmirx_hdcp2x_message216            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message217            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message218            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message219            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_d8(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_d8*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_DC                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xDC)

#define RX_HDMI_RX_HDCP2X_00_01_DC_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_dc

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_dc  rs_rx_hdmi_rx_hdcp2x_00_01_dc;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_dc {
    unsigned int reg_01_hdmirx_hdcp2x_message220            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message221            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message222            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message223            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_dc(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_dc*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_E0                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xE0)

#define RX_HDMI_RX_HDCP2X_00_01_E0_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_e0

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_e0  rs_rx_hdmi_rx_hdcp2x_00_01_e0;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_e0 {
    unsigned int reg_01_hdmirx_hdcp2x_message224            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message225            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message226            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message227            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_e0(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_e0*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_E4                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xE4)

#define RX_HDMI_RX_HDCP2X_00_01_E4_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_e4

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_e4  rs_rx_hdmi_rx_hdcp2x_00_01_e4;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_e4 {
    unsigned int reg_01_hdmirx_hdcp2x_message228            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message229            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message230            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message231            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_e4(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_e4*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_E8                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xE8)

#define RX_HDMI_RX_HDCP2X_00_01_E8_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_e8

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_e8  rs_rx_hdmi_rx_hdcp2x_00_01_e8;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_e8 {
    unsigned int reg_01_hdmirx_hdcp2x_message232            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message233            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message234            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message235            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_e8(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_e8*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_EC                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xEC)

#define RX_HDMI_RX_HDCP2X_00_01_EC_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_ec

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_ec  rs_rx_hdmi_rx_hdcp2x_00_01_ec;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_ec {
    unsigned int reg_01_hdmirx_hdcp2x_message236            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message237            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message238            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message239            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_ec(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_ec*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_F0                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xF0)

#define RX_HDMI_RX_HDCP2X_00_01_F0_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_f0

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_f0  rs_rx_hdmi_rx_hdcp2x_00_01_f0;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_f0 {
    unsigned int reg_01_hdmirx_hdcp2x_message240            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message241            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message242            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message243            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_f0(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_f0*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_F4                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xF4)

#define RX_HDMI_RX_HDCP2X_00_01_F4_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_f4

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_f4  rs_rx_hdmi_rx_hdcp2x_00_01_f4;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_f4 {
    unsigned int reg_01_hdmirx_hdcp2x_message244            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message245            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message246            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message247            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_f4(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_f4*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_F8                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xF8)

#define RX_HDMI_RX_HDCP2X_00_01_F8_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_f8

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_f8  rs_rx_hdmi_rx_hdcp2x_00_01_f8;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_f8 {
    unsigned int reg_01_hdmirx_hdcp2x_message248            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message249            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message250            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message251            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_f8(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_f8*)&(val))



#define RX_HDMI_RX_HDCP2X_00_01_FC                                       (HV_HDMI_RX_HDCP2X_00_01_BASE_ADDRESS + 0xFC)

#define RX_HDMI_RX_HDCP2X_00_01_FC_struct                                rs_rx_hdmi_rx_hdcp2x_00_01_fc

typedef struct _rs_rx_hdmi_rx_hdcp2x_00_01_fc  rs_rx_hdmi_rx_hdcp2x_00_01_fc;
struct _rs_rx_hdmi_rx_hdcp2x_00_01_fc {
    unsigned int reg_01_hdmirx_hdcp2x_message252            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message253            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message254            : 8;
    unsigned int reg_01_hdmirx_hdcp2x_message255            : 8;
};
#define rx_hdmi_rx_hdcp2x_00_01_fc(val) ((rs_rx_hdmi_rx_hdcp2x_00_01_fc*)&(val))



#endif