#ifndef _HV_PAGE_HT7315_HDMI21_RX21_PRE_PROC_REG_01_H_
#define _HV_PAGE_HT7315_HDMI21_RX21_PRE_PROC_REG_01_H_

#ifndef HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS
    #define HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS                                         0x1104E300
#endif


#define RX_HDMI21_RX21_PRE_PROC_REG_01_00                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_00_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_00

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_00  rs_rx_hdmi21_rx21_pre_proc_reg_01_00;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_00 {
    unsigned int reg_01_hd21rx_lane_symbol_match_option     : 2;
    unsigned int reg_01_hd21rx_decode_16b18b_init_par       : 5;
    unsigned int reg_01_hd21rx_decode_err_clren             : 1;
    unsigned int reg_01_hd21rx_decode_k_option              : 8;
    unsigned int reg_01_hd21rx_descramble_bypass            : 1;
    unsigned int reg_01_hd21rx_deskew_th                    : 5;
    unsigned int reserved                                   :10;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_00(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_00*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_04                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_04_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_04

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_04  rs_rx_hdmi21_rx21_pre_proc_reg_01_04;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_04 {
    unsigned int reg_01_hd21rx_decode_err_window            :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_04(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_04*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_08                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_08_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_08

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_08  rs_rx_hdmi21_rx21_pre_proc_reg_01_08;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_08 {
    unsigned int reg_01_hd21rx_code_err_thresh              :16;
    unsigned int reg_01_hd21rx_disp_err_thresh              :16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_08(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_08*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_0C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x0C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_0C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_0c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_0c  rs_rx_hdmi21_rx21_pre_proc_reg_01_0c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_0c {
    unsigned int reg_01_hd21rx_deskew_sw_value0             : 5;
    unsigned int reg_01_hd21rx_deskew_sw_value1             : 5;
    unsigned int reg_01_hd21rx_deskew_sw_value2             : 5;
    unsigned int reg_01_hd21rx_deskew_sw_value3             : 5;
    unsigned int reg_01_hd21rx_deskew_sw_en                 : 1;
    unsigned int reg_01_hd21rx_deskew_en                    : 1;
    unsigned int regr_01_hd21rx_deskew_lock                 : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_hd21rx_lanedata_swap_sel            : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_0c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_0c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_10                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x10)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_10_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_10

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_10  rs_rx_hdmi21_rx21_pre_proc_reg_01_10;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_10 {
    unsigned int reg_01_hd21rx_ltp_req_set_ctrl             : 3;
    unsigned int reg_01_hd21rx_ltp_req_sw_rxset             : 1;
    unsigned int reg_01_hd21rx_flt_step_timer_en            : 1;
    unsigned int reg_01_hd21rx_ltp_train_en                 : 1;
    unsigned int reg_01_hd21rx_ltp_train_bypass             : 1;
    unsigned int reg_01_hd21rx_ltp5678_chk_sel              : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_hd21rx_ln0_ltp_req_sw_value         : 4;
    unsigned int reg_01_hd21rx_ln1_ltp_req_sw_value         : 4;
    unsigned int reg_01_hd21rx_ln2_ltp_req_sw_value         : 4;
    unsigned int reg_01_hd21rx_ln3_ltp_req_sw_value         : 4;
    unsigned int reg_01_hd21rx_ltp_chk_st_sel               : 1;
    unsigned int reg_01_hd21rx_ltp_chk_win_sel              : 1;
    unsigned int reg_01_hd21rx_ltpe_chk_en                  : 1;
    unsigned int reg_01_hd21rx_ltpe_chk_set_sel             : 1;
    unsigned int reg_01_hd21rx_lt_auto_eq_st_en             : 1;
    unsigned int reserved_1                                 : 2;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_10(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_10*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_14                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x14)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_14_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_14

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_14  rs_rx_hdmi21_rx21_pre_proc_reg_01_14;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_14 {
    unsigned int reg_01_hd21rx_ln0_ltp_req_group            :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_14(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_14*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_18                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_18_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_18

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_18  rs_rx_hdmi21_rx21_pre_proc_reg_01_18;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_18 {
    unsigned int reg_01_hd21rx_ln1_ltp_req_group            :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_18(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_18*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_1C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_1C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_1c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_1c  rs_rx_hdmi21_rx21_pre_proc_reg_01_1c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_1c {
    unsigned int reg_01_hd21rx_ln2_ltp_req_group            :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_1c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_1c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_20                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x20)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_20_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_20

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_20  rs_rx_hdmi21_rx21_pre_proc_reg_01_20;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_20 {
    unsigned int reg_01_hd21rx_ln3_ltp_req_group            :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_20(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_20*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_24                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x24)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_24_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_24

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_24  rs_rx_hdmi21_rx21_pre_proc_reg_01_24;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_24 {
    unsigned int reg_01_hd21rx_flt_step_timer_th            :24;
    unsigned int reg_01_hd21rx_ffe_max                      : 4;
    unsigned int reg_01_eq_permit_sw_en                     : 1;
    unsigned int reg_01_eq_permit_sw                        : 1;
    unsigned int reg_01_eq_permit_hw_ln_sel                 : 2;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_24(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_24*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_28                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x28)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_28_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_28

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_28  rs_rx_hdmi21_rx21_pre_proc_reg_01_28;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_28 {
    unsigned int reg_01_hd21rx_ltp1_timer_th                :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_28(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_28*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_2C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x2C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_2C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_2c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_2c  rs_rx_hdmi21_rx21_pre_proc_reg_01_2c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_2c {
    unsigned int reg_01_hd21rx_ltp1_met_th                  :24;
    unsigned int reg_01_hd21rx_ltp1_chk_en                  : 1;
    unsigned int reserved                                   : 7;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_2c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_2c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_30                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x30)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_30_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_30

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_30  rs_rx_hdmi21_rx21_pre_proc_reg_01_30;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_30 {
    unsigned int reg_01_hd21rx_ltp2_timer_th                :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_30(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_30*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_34                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_34_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_34

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_34  rs_rx_hdmi21_rx21_pre_proc_reg_01_34;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_34 {
    unsigned int reg_01_hd21rx_ltp2_met_th                  :24;
    unsigned int reg_01_hd21rx_ltp2_chk_en                  : 1;
    unsigned int reserved                                   : 7;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_34(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_34*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_38                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_38_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_38

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_38  rs_rx_hdmi21_rx21_pre_proc_reg_01_38;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_38 {
    unsigned int reg_01_hd21rx_ltp3_timer_th                :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_38(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_38*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_3C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_3C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_3c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_3c  rs_rx_hdmi21_rx21_pre_proc_reg_01_3c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_3c {
    unsigned int reg_01_hd21rx_ltp3_met_th                  :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_3c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_3c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_40                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x40)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_40_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_40

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_40  rs_rx_hdmi21_rx21_pre_proc_reg_01_40;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_40 {
    unsigned int reg_01_hd21rx_ltp4_timer_th                :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_40(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_40*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_44                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x44)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_44_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_44

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_44  rs_rx_hdmi21_rx21_pre_proc_reg_01_44;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_44 {
    unsigned int reg_01_hd21rx_ltp4_met_th                  :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_44(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_44*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_48                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x48)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_48_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_48

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_48  rs_rx_hdmi21_rx21_pre_proc_reg_01_48;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_48 {
    unsigned int reg_01_hd21rx_ltp5678_timer_th             :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_48(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_48*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_4C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x4C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_4C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_4c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_4c  rs_rx_hdmi21_rx21_pre_proc_reg_01_4c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_4c {
    unsigned int reg_01_hd21rx_ltp5678_met_th               :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_4c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_4c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_50                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x50)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_50_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_50

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_50  rs_rx_hdmi21_rx21_pre_proc_reg_01_50;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_50 {
    unsigned int reg_01_hd21rx_auto_eq_timer_oscclk_x256_th :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_50(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_50*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_54                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x54)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_54_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_54

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_54  rs_rx_hdmi21_rx21_pre_proc_reg_01_54;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_54 {
    unsigned int reg_01_hd21rx_buf_pipe0_clr                : 1;
    unsigned int reg_01_hd21rx_rs_enable                    : 1;
    unsigned int reg_01_hd21rx_rs_start_ctl_sel             : 2;
    unsigned int reg_01_hd21rx_superblk_on_thro             : 4;
    unsigned int reg_01_hd21rx_rs_done_thro                 :10;
    unsigned int reserved                                   :14;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_54(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_54*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_58                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x58)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_58_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_58

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_58  rs_rx_hdmi21_rx21_pre_proc_reg_01_58;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_58 {
    unsigned int reg_01_hd21rx_phy_rstn_en                  : 4;
    unsigned int reg_01_hd21rx_phy_rst_ltp3_en              : 1;
    unsigned int reg_01_hd21rx_phy_rst_ltp4_en              : 1;
    unsigned int reg_01_hd21rx_phy_rst_ltp5678_en           : 1;
    unsigned int reg_01_hd21rx_ltp4_ln_clk_stbl_chk_en      : 1;
    unsigned int reg_01_hd21rx_ltp4_phy_cr_chk_en           : 1;
    unsigned int regr_01_phy_rstn                           : 4;
    unsigned int reg_01_hd21rx_phy_rst_bef_threshold        :19;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_58(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_58*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_5C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x5C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_5C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_5c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_5c  rs_rx_hdmi21_rx21_pre_proc_reg_01_5c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_5c {
    unsigned int reg_01_hd21rx_phy_rst_wait_th              :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_5c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_5c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_60                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x60)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_60_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_60

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_60  rs_rx_hdmi21_rx21_pre_proc_reg_01_60;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_60 {
    unsigned int reg_01_hd21rx_phy_rst_length               :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_60(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_60*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_64                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x64)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_64_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_64

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_64  rs_rx_hdmi21_rx21_pre_proc_reg_01_64;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_64 {
    unsigned int regr_01_hd21rx_symbol_lock                 : 4;
    unsigned int regr_01_hd21rx_symnol_sel_result_0         : 5;
    unsigned int regr_01_hd21rx_symnol_sel_result_1         : 5;
    unsigned int regr_01_hd21rx_symnol_sel_result_2         : 5;
    unsigned int regr_01_hd21rx_symnol_sel_result_3         : 5;
    unsigned int regr_01_hd21rx_lane_afifo_full             : 4;
    unsigned int regr_01_hd21rx_lane_afifo_empty            : 4;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_64(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_64*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_68                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x68)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_68_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_68

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_68  rs_rx_hdmi21_rx21_pre_proc_reg_01_68;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_68 {
    unsigned int regr_01_hd21rx_decode_code_err_cnt_0       :16;
    unsigned int regr_01_hd21rx_decode_code_err_cnt_1       :16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_68(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_68*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_6C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x6C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_6C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_6c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_6c  rs_rx_hdmi21_rx21_pre_proc_reg_01_6c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_6c {
    unsigned int regr_01_hd21rx_decode_code_err_cnt_2       :16;
    unsigned int regr_01_hd21rx_decode_code_err_cnt_3       :16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_6c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_6c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_70                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x70)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_70_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_70

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_70  rs_rx_hdmi21_rx21_pre_proc_reg_01_70;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_70 {
    unsigned int regr_01_hd21rx_decode_disp_err_cnt_0       :16;
    unsigned int regr_01_hd21rx_decode_disp_err_cnt_1       :16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_70(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_70*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_74                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x74)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_74_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_74

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_74  rs_rx_hdmi21_rx21_pre_proc_reg_01_74;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_74 {
    unsigned int regr_01_hd21rx_decode_disp_err_cnt_2       :16;
    unsigned int regr_01_hd21rx_decode_disp_err_cnt_3       :16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_74(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_74*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_78                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x78)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_78_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_78

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_78  rs_rx_hdmi21_rx21_pre_proc_reg_01_78;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_78 {
    unsigned int regr_01_hd21rx_deskew_value0               : 5;
    unsigned int regr_01_hd21rx_deskew_value1               : 5;
    unsigned int regr_01_hd21rx_deskew_value2               : 5;
    unsigned int regr_01_hd21rx_deskew_value3               : 5;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_78(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_78*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_7C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x7C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_7C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_7c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_7c  rs_rx_hdmi21_rx21_pre_proc_reg_01_7c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_7c {
    unsigned int regr_01_hd21rx_reed_solo_corcunt           :15;
    unsigned int regr_01_hd21rx_rs_err_corrt                :16;
    unsigned int regr_01_hd21rx_rs_fail                     : 1;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_7c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_7c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_80                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x80)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_80_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_80

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_80  rs_rx_hdmi21_rx21_pre_proc_reg_01_80;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_80 {
    unsigned int regr_01_hd21rx_rs_buf_space00              : 8;
    unsigned int regr_01_hd21rx_rs_buf_space01              : 8;
    unsigned int regr_01_tmdsrx_auto_eq_debug_phy_init_cnt  : 8;
    unsigned int regr_01_tmdsrx_auto_eq_debug_eq_permit_cnt : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_80(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_80*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_84                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x84)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_84_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_84

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_84  rs_rx_hdmi21_rx21_pre_proc_reg_01_84;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_84 {
    unsigned int regr_01_hd21rx_rs_cnt0                     :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_84(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_84*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_88                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x88)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_88_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_88

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_88  rs_rx_hdmi21_rx21_pre_proc_reg_01_88;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_88 {
    unsigned int regr_01_hd21rx_rs_cnt1                     :32;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_88(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_88*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_8C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x8C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_8C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_8c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_8c  rs_rx_hdmi21_rx21_pre_proc_reg_01_8c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_8c {
    unsigned int regr_01_hd21rx_ltp1_met_cnt_ln0            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_8c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_8c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_90                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x90)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_90_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_90

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_90  rs_rx_hdmi21_rx21_pre_proc_reg_01_90;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_90 {
    unsigned int regr_01_hd21rx_ltp2_met_cnt_ln0            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_90(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_90*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_94                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x94)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_94_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_94

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_94  rs_rx_hdmi21_rx21_pre_proc_reg_01_94;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_94 {
    unsigned int regr_01_hd21rx_ltp3_met_cnt_ln0            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_94(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_94*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_98                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x98)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_98_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_98

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_98  rs_rx_hdmi21_rx21_pre_proc_reg_01_98;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_98 {
    unsigned int regr_01_hd21rx_ltp4_met_cnt_ln0            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_98(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_98*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_9C                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0x9C)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_9C_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_9c

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_9c  rs_rx_hdmi21_rx21_pre_proc_reg_01_9c;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_9c {
    unsigned int regr_01_hd21rx_ltp5678_met_cnt_ln0         :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_9c(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_9c*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_A0                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xA0)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_A0_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_a0

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_a0  rs_rx_hdmi21_rx21_pre_proc_reg_01_a0;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_a0 {
    unsigned int regr_01_hd21rx_ltp1_met_cnt_ln1            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_a0(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_a0*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_A4                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xA4)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_A4_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_a4

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_a4  rs_rx_hdmi21_rx21_pre_proc_reg_01_a4;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_a4 {
    unsigned int regr_01_hd21rx_ltp2_met_cnt_ln1            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_a4(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_a4*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_A8                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xA8)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_A8_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_a8

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_a8  rs_rx_hdmi21_rx21_pre_proc_reg_01_a8;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_a8 {
    unsigned int regr_01_hd21rx_ltp3_met_cnt_ln1            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_a8(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_a8*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_AC                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xAC)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_AC_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_ac

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_ac  rs_rx_hdmi21_rx21_pre_proc_reg_01_ac;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_ac {
    unsigned int regr_01_hd21rx_ltp4_met_cnt_ln1            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_ac(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_ac*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_B0                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xB0)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_B0_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_b0

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_b0  rs_rx_hdmi21_rx21_pre_proc_reg_01_b0;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_b0 {
    unsigned int regr_01_hd21rx_ltp5678_met_cnt_ln1         :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_b0(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_b0*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_B4                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xB4)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_B4_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_b4

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_b4  rs_rx_hdmi21_rx21_pre_proc_reg_01_b4;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_b4 {
    unsigned int regr_01_hd21rx_ltp1_met_cnt_ln2            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_b4(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_b4*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_B8                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xB8)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_B8_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_b8

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_b8  rs_rx_hdmi21_rx21_pre_proc_reg_01_b8;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_b8 {
    unsigned int regr_01_hd21rx_ltp2_met_cnt_ln2            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_b8(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_b8*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_BC                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xBC)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_BC_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_bc

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_bc  rs_rx_hdmi21_rx21_pre_proc_reg_01_bc;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_bc {
    unsigned int regr_01_hd21rx_ltp3_met_cnt_ln2            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_bc(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_bc*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_C0                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xC0)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_C0_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_c0

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_c0  rs_rx_hdmi21_rx21_pre_proc_reg_01_c0;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_c0 {
    unsigned int regr_01_hd21rx_ltp4_met_cnt_ln2            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_c0(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_c0*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_C4                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xC4)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_C4_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_c4

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_c4  rs_rx_hdmi21_rx21_pre_proc_reg_01_c4;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_c4 {
    unsigned int regr_01_hd21rx_ltp5678_met_cnt_ln2         :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_c4(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_c4*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_C8                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xC8)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_C8_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_c8

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_c8  rs_rx_hdmi21_rx21_pre_proc_reg_01_c8;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_c8 {
    unsigned int regr_01_hd21rx_ltp1_met_cnt_ln3            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_c8(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_c8*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_CC                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xCC)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_CC_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_cc

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_cc  rs_rx_hdmi21_rx21_pre_proc_reg_01_cc;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_cc {
    unsigned int regr_01_hd21rx_ltp2_met_cnt_ln3            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_cc(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_cc*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_D0                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xD0)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_D0_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_d0

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_d0  rs_rx_hdmi21_rx21_pre_proc_reg_01_d0;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_d0 {
    unsigned int regr_01_hd21rx_ltp3_met_cnt_ln3            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_d0(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_d0*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_D4                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xD4)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_D4_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_d4

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_d4  rs_rx_hdmi21_rx21_pre_proc_reg_01_d4;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_d4 {
    unsigned int regr_01_hd21rx_ltp4_met_cnt_ln3            :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_d4(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_d4*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_D8                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xD8)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_D8_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_d8

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_d8  rs_rx_hdmi21_rx21_pre_proc_reg_01_d8;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_d8 {
    unsigned int regr_01_hd21rx_ltp5678_met_cnt_ln3         :24;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_d8(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_d8*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_DC                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xDC)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_DC_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_dc

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_dc  rs_rx_hdmi21_rx21_pre_proc_reg_01_dc;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_dc {
    unsigned int regr_01_hd21rx_ln0_ltp_req                 : 4;
    unsigned int regr_01_hd21rx_ln1_ltp_req                 : 4;
    unsigned int regr_01_hd21rx_ln2_ltp_req                 : 4;
    unsigned int regr_01_hd21rx_ln3_ltp_req                 : 4;
    unsigned int regr_01_hd21rx_ltp_st_cs                   : 8;
    unsigned int regr_01_hd21rx_ltp_training_done           : 1;
    unsigned int regr_01_hd21rx_fst_blk_cnt_eq_510_en       : 1;
    unsigned int regr_01_hd21rx_rs_superblk_on              : 1;
    unsigned int regr_01_hd21rx_tri_byt_typ_state           : 2;
    unsigned int regr_01_hd21rx_frl_upkt_rnxt_state         : 2;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_dc(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_dc*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_E0                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xE0)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_E0_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_e0

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_e0  rs_rx_hdmi21_rx21_pre_proc_reg_01_e0;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_e0 {
    unsigned int regr_01_hd21rx_ln0_ltpe_cnt                : 4;
    unsigned int regr_01_hd21rx_ln1_ltpe_cnt                : 4;
    unsigned int regr_01_hd21rx_ln2_ltpe_cnt                : 4;
    unsigned int regr_01_hd21rx_ln3_ltpe_cnt                : 4;
    unsigned int regr_01_hd21rx_frl_ln_lock_st              :12;
    unsigned int regr_01_hd21rx_frl_lnlocked                : 4;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_e0(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_e0*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_E4                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xE4)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_E4_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_e4

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_e4  rs_rx_hdmi21_rx21_pre_proc_reg_01_e4;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_e4 {
    unsigned int reg_01_hd21rx_auto_eq_permit_enable        : 1;
    unsigned int reg_01_hd21rx_code_err_auto_phy_init_en    : 1;
    unsigned int reg_01_hd21rx_clk_not_good_auto_phy_init_en: 1;
    unsigned int reg_01_hd21rx_phy_config_bypass            : 1;
    unsigned int reg_01_hd21rx_phy_init_bypass              : 1;
    unsigned int reg_01_hd21rx_check_crdone0_bypass         : 1;
    unsigned int reg_01_hd21rx_check_ckgood0_bypass         : 1;
    unsigned int reg_01_hd21rx_check_aln0_bypass            : 1;
    unsigned int reg_01_hd21rx_check_crdone1_bypass         : 1;
    unsigned int reg_01_hd21rx_check_ckgood1_bypass         : 1;
    unsigned int reg_01_hd21rx_check_aln1_bypass            : 1;
    unsigned int reg_01_hd21rx_check_deskew_bypass          : 1;
    unsigned int reg_01_hd21rx_check_eqdone_bypass          : 1;
    unsigned int reg_01_hd21rx_dfe_permit_bypass            : 1;
    unsigned int reg_01_hd21rx_eq_permit_bypass             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_hd21rx_phy_config_sw_trig           : 1;
    unsigned int reg_01_hd21rx_eq_permit_sw_trig            : 1;
    unsigned int reserved_1                                 : 1;
    unsigned int reg_01_hd21rx_link_training_mode           : 1;
    unsigned int reserved_2                                 : 4;
    unsigned int reg_01_hd21rx_cycle_oscclk_phy_init        : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_e4(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_e4*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_E8                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xE8)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_E8_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_e8

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_e8  rs_rx_hdmi21_rx21_pre_proc_reg_01_e8;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_e8 {
    unsigned int reg_01_hd21rx_cycle_oscclk_eq_permit       : 8;
    unsigned int reg_01_hd21rx_cycle_oscclk_dfe_permit      : 8;
    unsigned int reg_01_hd21rx_cycle_oscclk_x64_crdone_timeout:16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_e8(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_e8*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_EC                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xEC)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_EC_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_ec

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_ec  rs_rx_hdmi21_rx21_pre_proc_reg_01_ec;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_ec {
    unsigned int reg_01_hd21rx_cycle_oscclk_x64_ckgood_timeout:16;
    unsigned int reg_01_hd21rx_cycle_oscclk_x64_aln_timeout :16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_ec(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_ec*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_F0                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xF0)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_F0_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_f0

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_f0  rs_rx_hdmi21_rx21_pre_proc_reg_01_f0;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_f0 {
    unsigned int reg_01_hd21rx_cycle_oscclk_x64_deskew_timeout:16;
    unsigned int reg_01_hd21rx_cycle_oscclk_x64_eqdone_timeout:16;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_f0(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_f0*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_F4                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xF4)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_F4_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_f4

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_f4  rs_rx_hdmi21_rx21_pre_proc_reg_01_f4;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_f4 {
    unsigned int reg_01_hd21rx_cycle_oscclk_x64_check_clk_time:16;
    unsigned int reg_01_hd21rx_bf_phy_init_eq_pertmit1_cnt  : 8;
    unsigned int reg_01_hd21rx_auto_eq0_loop_cnt_th         : 8;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_f4(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_f4*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_F8                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xF8)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_F8_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_f8

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_f8  rs_rx_hdmi21_rx21_pre_proc_reg_01_f8;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_f8 {
    unsigned int reg_01_hd21rx_cycle_oscclk_x64_autoeq_err_det:20;
    unsigned int reg_01_hd21rx_auto_eq1_loop_cnt_th         :12;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_f8(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_f8*)&(val))



#define RX_HDMI21_RX21_PRE_PROC_REG_01_FC                                (HV_HDMI21_RX21_PRE_PROC_REG_01_BASE_ADDRESS + 0xFC)

#define RX_HDMI21_RX21_PRE_PROC_REG_01_FC_struct                         rs_rx_hdmi21_rx21_pre_proc_reg_01_fc

typedef struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_fc  rs_rx_hdmi21_rx21_pre_proc_reg_01_fc;
struct _rs_rx_hdmi21_rx21_pre_proc_reg_01_fc {
    unsigned int reg_01_hd21rx_eq_permit_err_th             :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_hd21rx_phy_init_err_th              :15;
    unsigned int reg_01_hd21rx_auto_eq_debug_clr            : 1;
};
#define rx_hdmi21_rx21_pre_proc_reg_01_fc(val) ((rs_rx_hdmi21_rx21_pre_proc_reg_01_fc*)&(val))



#endif