/**
 * @file hv_pm51_app_PM.c
 * @brief 
 * @details 
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20230301
 * @copyright Copyright(c),2023-3, Hiview Software. All rights reserved.
 * @par History: 
 * <table>
 * <tr><th>author                     <th>date           <th>description
 * <tr><td>HiView SoC Software Team   <td>20230301       <td>Create and first Version.
 * </table>
**/

#include <reg51.h>
#include "HS_PAGE_HT7315_8051_reg.h"
#include "hv_pm51_Setting.h"
#include "hv_pm51_driver_UART.h"
#include "hv_pm51_driver_Reg.h"
#include "hv_pm51_driver_ADC.h"
#include "hv_pm51_driver_I2C.h"
#include "hv_pm51_driver_Timer.h"
#include "hv_pm51_driver_GPIO.h"
#include "hv_pm51_app_Mailbox.h"
#include "hv_pm51_app_Sys.h"
#include "hv_pm51_app_PM.h"
#include "Keyboard.h"
#include "KeyboardConfig.h"
#include "BoardConfig.h"

#define MIPS_BOOT_ADDR      0xBFC09
#define MIPS_BOOT_ADDR_2ND  0xBFC18
#define CUR_STATUS_E2P_ADDR 0x000C

/* User Config Data */
UCHAR8 ucPmuFlag;
UCHAR8 ucPmLedMode;
UCHAR8 ucDbBuffer;

xUCHAR8 ucACBootFlag = HV_FALSE;
xUCHAR8 ucFactoyMode = HV_MODE_OFF;
UCHAR8 ucPowerState = POWER_STATE_POWER_ON;

extern volatile IntFlags g_unIntFlag;
#if (PM51_CONFIG_POWER_KEY_MODE & POWER_KEY_MODE_MULTI)
extern xdata BOOL g_bPowerKeyHold;
#endif

static void PM_DpmsDisable(void)
{
    /* wake up disable except adc */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR,
                      HS_Standby__standby_mcu_reg__reg_wake_int_en_BITSTART,
                      HS_Standby__standby_mcu_reg__reg_wake_int_en_BITEND, 0x0);
#if ADC_KEY_ENABLE
#if ADC0_KEY_ENABLE
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR, 20, 20, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR, 4, 4, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR, 20, 20, 0x1);
#endif

#if ADC1_KEY_ENABLE
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR, 21, 21, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR, 5, 5, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR, 21, 21, 0x1);
#endif
#endif

#if HV_BOARD_CONFIG_HDMI_HPD_5V
    /* HDMI HPD GPIO OE Setting */
    /* set HDMI0 OE = 1 */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_oe_ADDR, 14, 14, 0x1);
    /* set HDMI1 OE = 1 */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_oe_ADDR, 15, 15, 0x1);

    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_edid_ADDR, 
                          HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_edid_BITSTART, 
                          HS_Standby__hdmi21_rx_eddc_00__reg_00_slv_en_edid_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_edid_ADDR, 
                          HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_edid_BITSTART, 
                          HS_Standby__hdmi21_rx_eddc_01__reg_01_slv_en_edid_BITEND, 0x0);
#endif

#if DPMS_DP0_GPIO_ENABLE
#if (HV_CONFIG_ON == HV_PROJECT_CONFIG_DP_NOSTAND_CABLE_ENABLE)
    Hv_PM51_Gpio_EnableInt(DPMS_DP0_GPIO, GPIO_INTR_EDGE_P);
    Hv_PM51_Gpio_EnableInt(DPMS_DP0_GPIO, GPIO_INTR_EDGE_N);
#else
    Hv_PM51_Gpio_DisableInt(DPMS_DP0_GPIO);
#endif
#endif

#if DPMS_DP1_GPIO_ENABLE
#if (HV_CONFIG_ON == HV_PROJECT_CONFIG_DP_NOSTAND_CABLE_ENABLE)
    Hv_PM51_Gpio_EnableInt(DPMS_DP1_GPIO, GPIO_INTR_EDGE_P);
    Hv_PM51_Gpio_EnableInt(DPMS_DP1_GPIO, GPIO_INTR_EDGE_N);
#else
    Hv_PM51_Gpio_DisableInt(DPMS_DP1_GPIO);
#endif
#endif
#if DPMS_TYPEC0_ENABLE
    Hv_PM51_Timer_Clear(INNERTIMER1);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCF_IRQ_mask_for_connection_detection_FSM_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C03_RXFSM_SOP_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C07_RSTFSM_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_power_role_state_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITEND, 0x2);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_try_src_support_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_ra_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITEND, 0x33);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_rd_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITEND, 0x7F);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITEND, 0xA);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_delay_cnt_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITEND, 0x493E0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITEND, 0x41);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_drp_toggle_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_drp_toggle_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_drp_toggle_BITEND, 0x1);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__00_rstn_ccdet_ADDR,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITSTART,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__00_rstn_ccdet_ADDR,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITSTART,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITEND, 0x1);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITEND, 0x4);
#endif
    return;
}

void Hv_PM51_PM_PowerOffMainDomain(void)
{
    xULONG32 ulRData32;
    
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_apb_clk_sel_ADDR); /*  APB CLK sel reg_apb_clk_sel */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_apb_clk_sel_ADDR, ulRData32 | BIT_4);
    Hv_PM51_Sys_DelayMs(1);
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR); /*  Standby reset reg_stb_sw_rst_n */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR, ulRData32 & ~(BIT_0));
    Hv_PM51_Sys_DelayMs(1);
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR); /*  Iso reg_stby_iso */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR, ulRData32 | BIT_1);
    Hv_PM51_Sys_DelayMs(1);
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_power_on_ADDR); /* Main Domain POWER OFF reg_power_on */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_power_on_ADDR, ulRData32 & ~(BIT_2));
    Hv_PM51_Sys_DelayMs(1);
}

#if (HV_PROJECT_CONFIG_ESEGMENT_PM51 == HV_CONFIG_ON)
void Hv_PM51_Sys_HdmiEdidSegmentInit(void)
{
    /* HDMI0 */
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_edid_segment_update_ADDR,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_edid_segment_update_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_edid_segment_update_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_ADDR,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_ADDR,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_edid_segment_update_BITEND, 0x0);

    /* HDMI1 */
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_edid_segment_update_ADDR,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_edid_segment_update_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_edid_segment_update_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_ADDR,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_ADDR,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_edid_segment_update_BITEND, 0x0);
}
#endif

void Hv_PM51_PM_DpmsEnable(void)
{
    xULONG32 ulEdge = 0;
    xULONG32 ulWakeEn = 0;

#if DPMS_DP0_CABLE_ENABLE
    ulEdge |= (1 << WAKEUP_DP_CABLE_0);
#if CABLE_WAKEUP_DOUBLE
    ulEdge |= (1 << (16 + WAKEUP_DP_CABLE_0));
#endif
    ulWakeEn |= (1 << WAKEUP_DP_CABLE_0);
#endif

#if DPMS_DP1_CABLE_ENABLE
    ulEdge |= (1 << WAKEUP_DP_CABLE_1);
#if CABLE_WAKEUP_DOUBLE
    ulEdge |= (1 << (16 + WAKEUP_DP_CABLE_1));
#endif
    ulWakeEn |= (1 << WAKEUP_DP_CABLE_1);
#endif

#if DPMS_DP0_AUX_ENABLE
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_dprx0_aux_sw_sel_ADDR,
                      HS_Standby__standby_peri_reg__reg_dprx0_aux_sw_sel_BITSTART,
                      HS_Standby__standby_peri_reg__reg_dprx0_aux_sw_sel_BITEND, 0x2);  /* reg_dprx_aux_sw_sel */
    ulEdge |= (1 << WAKEUP_AUX_0);
    ulWakeEn |= (1 << WAKEUP_AUX_0);
#endif

#if DPMS_DP1_AUX_ENABLE
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_dprx1_aux_sw_sel_ADDR,
                      HS_Standby__standby_peri_reg__reg_dprx1_aux_sw_sel_BITSTART,
                      HS_Standby__standby_peri_reg__reg_dprx1_aux_sw_sel_BITEND, 0x2);  /* reg_dprx_aux_sw_sel */
    ulEdge |= (1 << WAKEUP_AUX_1);
    ulWakeEn |= (1 << WAKEUP_AUX_1);
#endif

#if DPMS_HDMI0_CABLE_ENABLE
    ulEdge |= (1 << WAKEUP_HDMI_CABLE_0);
#if CABLE_WAKEUP_DOUBLE
    ulEdge |= (1 << (16 + WAKEUP_HDMI_CABLE_0));
#endif
    ulWakeEn |= (1 << WAKEUP_HDMI_CABLE_0);
#endif

#if DPMS_HDMI1_CABLE_ENABLE
    ulEdge |= (1 << WAKEUP_HDMI_CABLE_1);
#if CABLE_WAKEUP_DOUBLE
    ulEdge |= (1 << (16 + WAKEUP_HDMI_CABLE_1));
#endif
    ulWakeEn |= (1 << WAKEUP_HDMI_CABLE_1);
#endif

#if DPMS_HDMI0_CEC_ENABLE
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_io_ctrl_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_io_ctrl_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi_rx0_cec_io_ctrl_BITEND, 0x19);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_rcv_clr_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_00__reg_00_hd_locked_clr_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_ADDR,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_ADDR,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_clr_cec_wakeupctrl_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_wakeupctrl_ADDR,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_wakeupctrl_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_00__reg_00_int_en_cec_wakeupctrl_BITEND, 0x1);
    ulEdge |= (1 << WAKEUP_HDMI_CEC_0);
    ulWakeEn |= (1 << WAKEUP_HDMI_CEC_0);
#endif

#if DPMS_HDMI1_CEC_ENABLE
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_io_ctrl_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_io_ctrl_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_hdmi_rx1_cec_io_ctrl_BITEND, 0x19);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_rcv_clr_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_ADDR,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_BITSTART,
                      HS_Standby__HDMI21_RX_CEC_01__reg_01_hd_locked_clr_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_ADDR,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_ADDR,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_clr_cec_wakeupctrl_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_wakeupctrl_ADDR,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_wakeupctrl_BITSTART,
                      HS_Standby__hdmi21_rx_eddc_01__reg_01_int_en_cec_wakeupctrl_BITEND, 0x1);
    ulEdge |= (1 << WAKEUP_HDMI_CEC_1);
    ulWakeEn |= (1 << WAKEUP_HDMI_CEC_1);
#endif

#if DPMS_HDMI0_TMDS_ENABLE
    ulEdge |= (1 << WAKEUP_RX_PHY_2);
    ulWakeEn |= (1 << WAKEUP_RX_PHY_2);
#endif

#if DPMS_HDMI1_TMDS_ENABLE
    ulEdge |= (1 << WAKEUP_RX_PHY_3);
    ulWakeEn |= (1 << WAKEUP_RX_PHY_3);
#endif

#if DPMS_TYPEC0_ENABLE
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCF_IRQ_mask_for_connection_detection_FSM_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C03_RXFSM_SOP_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C07_RSTFSM_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_BITEND, 0x0);
#if DPMS_TYPEC_USE_DRP
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_power_role_state_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITEND, 0x2);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_try_src_support_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_ra_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITEND, 0x33);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_rd_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITEND, 0x7F);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITEND, 0xA);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_delay_cnt_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITEND, 0x493E0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITEND, 0x41);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_drp_toggle_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_drp_toggle_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_drp_toggle_BITEND, 0x1);
#else
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_power_role_state_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_power_role_state_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_try_src_support_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_try_src_support_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_ra_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_ra_threshold_BITEND, 0x33);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_rd_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_rd_threshold_BITEND, 0xA6);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_sink_con_threshold_BITEND, 0xA);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_delay_cnt_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_delay_cnt_BITEND, 0x493E0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DA6_Plug_Flip_detection_configuration_BITEND, 0x41);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cmd_direct_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cmd_direct_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cmd_direct_BITEND, 0x6);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_ADDR,
                      HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_BITSTART,
                      HS_Standby__usb_typec_top_00__reg_00_cmd_direct_en_BITEND, 0x2);
#endif
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__00_rstn_ccdet_ADDR,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITSTART,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__00_rstn_ccdet_ADDR,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITSTART,
                      HS_Standby__usb_typec_top_00__00_rstn_ccdet_BITEND, 0x1);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_BITEND, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCE_IRQ_mask_for_CC_Voltage_detection_BITEND, 0x4);

    ulEdge |= (1 << WAKEUP_TYPE_C_0);
    ulWakeEn |= (1 << WAKEUP_TYPE_C_0);
#endif

#if DPMS_TYPEC1_ENABLE
    ulEdge |= (1 << WAKEUP_TYPE_C_1);
    ulWakeEn |= (1 << WAKEUP_TYPE_C_1);
#endif
    ulEdge |= Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR);
    ulWakeEn |= Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR) >> 16;
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_wake_int_edge_p_ADDR, ulEdge);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_wake_int_en_ADDR,
                    HS_Standby__standby_mcu_reg__reg_wake_int_en_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_wake_int_en_BITEND,
                    ulWakeEn);

#if DPMS_DP0_GPIO_ENABLE
#if (HV_CONFIG_ON == HV_PROJECT_CONFIG_DP_NOSTAND_CABLE_ENABLE)
    Hv_PM51_Gpio_DisableInt(DPMS_DP0_GPIO);
    Hv_PM51_Gpio_EnableInt(DPMS_DP0_GPIO, GPIO_INTR_EDGE_P);
#else
    Hv_PM51_Gpio_EnableInt(DPMS_DP0_GPIO, GPIO_INTR_EDGE_P);
#endif
#endif

#if DPMS_DP1_GPIO_ENABLE
#if (HV_CONFIG_ON == HV_PROJECT_CONFIG_DP_NOSTAND_CABLE_ENABLE)
    Hv_PM51_Gpio_DisableInt(DPMS_DP1_GPIO);
    Hv_PM51_Gpio_EnableInt(DPMS_DP1_GPIO, GPIO_INTR_EDGE_P);
#else
    Hv_PM51_Gpio_EnableInt(DPMS_DP1_GPIO, GPIO_INTR_EDGE_P);
#endif
#endif

#if DPMS_TYPEC0_ENABLE
    Hv_PM51_Timer_Set(INNERTIMER1, 0xFFFF);
#endif
    return;
}

void Hv_PM51_PM_SetHpdLow(void)
{
#if (HV_BOARD_CONFIG_DISPLAYPORT_0 == PORT_VALID)
#if (HV_BOARD_CONFIG_DP0_TYPE == DP_PORT_NORM)
#ifdef HV_BOARD_CONFIG_DP0_HPD_GPIO
    /* Set DP0 Hot Plug LOW */
    Hv_PM51_Gpio_SetIODirection(HV_BOARD_CONFIG_DP0_HPD_GPIO, GPIO_OUTPUT);
    Hv_PM51_Gpio_SetOutputLevel(HV_BOARD_CONFIG_DP0_HPD_GPIO, GPIO_LEVEL_LOW);
#endif
#endif
#endif

#if (HV_BOARD_CONFIG_DISPLAYPORT_1 == PORT_VALID)
#if (HV_BOARD_CONFIG_DP1_TYPE == DP_PORT_NORM)
    /* Set DP1 Hot Plug LOW */
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_ADDR,
                  HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_BITSTART,
                  HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_oe_ADDR, 12, 12, 0x1);

    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_o_ADDR, 4, 4, 0x0);

    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_ADDR,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_BITSTART,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_ADDR,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_BITSTART,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_BITEND, 0x29);
#endif
#endif

    return;
}

void Hv_PM51_PM_EnterStandBy(void)
{
    xULONG32 ulRData32;
    xULONG32 ulWakeIntStat;
    xULONG32 ulWakeIntClr;

    Hv_PM51_Sys_SetMipsBootState(HV_FALSE);
    Hv_PM51_Sys_ResetMipsBootRetry();
    Hv_PM51_Sys_SetMipsBootTimerState(HV_FALSE);

    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_o_ADDR, 0, 0, 0x0);

#if (HV_BOARD_CONFIG_DISPLAYPORT_0 == PORT_VALID)
#if (HV_BOARD_CONFIG_DP0_TYPE == DP_PORT_NORM)
#ifdef HV_BOARD_CONFIG_DP0_HPD_GPIO
    if((Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_dp0_cable_ADDR) & 0x1) == 0x0)
    {
        /* Set DP0 Hot Plug High */
        Hv_PM51_Gpio_SetIODirection(HV_BOARD_CONFIG_DP0_HPD_GPIO, GPIO_OUTPUT);
        Hv_PM51_Gpio_SetOutputLevel(HV_BOARD_CONFIG_DP0_HPD_GPIO, GPIO_LEVEL_HIGH);
    }
    else
    {
        Hv_PM51_Gpio_SetIODirection(HV_BOARD_CONFIG_DP0_HPD_GPIO, GPIO_OUTPUT);
        Hv_PM51_Gpio_SetOutputLevel(HV_BOARD_CONFIG_DP0_HPD_GPIO, GPIO_LEVEL_LOW);
    }
#endif
#endif
#endif

#if (HV_BOARD_CONFIG_DISPLAYPORT_1 == PORT_VALID)
#if (HV_BOARD_CONFIG_DP1_TYPE == DP_PORT_NORM)
    /* Set DP1 Hot Plug High */
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_ADDR,
                  HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_BITSTART,
                  HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i4_use_sel_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_ADDR,
                      HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_BITSTART,
                      HS_Standby__SH08_TOP_STBY__reg_stby_gpio_i_in_sel_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_oe_ADDR, 12, 12, 0x1);

    if((Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_dp1_cable_ADDR) & 0x2) == 0x0)
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_o_ADDR, 4, 4, 0x1);
    }
    else
    {
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_gpio_o_ADDR, 4, 4, 0x0);
    }

    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_ADDR,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_BITSTART,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_func_sel_BITEND, 0x1);
    Hv_PM51_Reg_WriteMask(HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_ADDR,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_BITSTART,
                  HS_Standby__SH08_TOP_STBY__reg_dp_rx1_hpd_io_ctrl_BITEND, 0x29);
#endif
#endif

    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_apb_clk_sel_ADDR); /*  APB CLK sel reg_apb_clk_sel */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_apb_clk_sel_ADDR, ulRData32 | BIT_4);
    Hv_PM51_Sys_DelayMs(1);
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR); /*  Standby reset reg_stb_sw_rst_n */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR, ulRData32 & ~(BIT_0));
    Hv_PM51_Sys_DelayMs(1);
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR); /*  Iso reg_stby_iso */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR, ulRData32 | BIT_1);
    Hv_PM51_Sys_DelayMs(1);
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_power_on_ADDR); /* Main Domain POWER OFF reg_power_on */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_power_on_ADDR, ulRData32 & ~(BIT_2));
    Hv_PM51_Sys_DelayMs(1);

    /* clear wake int status first */
    ulWakeIntStat = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__regr_wake_int_stat_ADDR) & 0xFFFF;
    ulWakeIntClr = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_wake_int_clr_ADDR);
    ulWakeIntStat |= ulWakeIntClr;
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_wake_int_clr_ADDR, ulWakeIntStat);

#if PM51_CONFIG_FAKE_DC
    if (ucPowerState == POWER_STATE_OFF)
    {
        PM51_Key_SetLed(E_KEY_LED_OFF);
        Hv_PM51_Sys_SetStandby2DCTimerState(HV_FALSE);
        PM_DpmsDisable();

        /* Simulate Typec Unplug*/
        /* Clear sw_ctrl_rd_en & sw_ctrl_rp_en in TypeC_GenericInitPort*/
        Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rd_en_ADDR,
                    HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rd_en_BITSTART,
                    HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rd_en_BITEND, 0x1);
        Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rp_en_ADDR,
                    HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rp_en_BITSTART,
                    HS_Standby__usb_typec_top_00__reg_00_sw_ctrl_rp_en_BITEND, 0x1);
        Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_ADDR,
                    HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITSTART,
                    HS_Standby__usb_typec_top_00__reg_00_cc1_rd_en_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_ADDR,
                    HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITSTART,
                    HS_Standby__usb_typec_top_00__reg_00_cc2_rd_en_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_ADDR,
                    HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITSTART,
                    HS_Standby__usb_typec_top_00__reg_00_cc1_rp_en_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_ADDR,
                    HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITSTART,
                    HS_Standby__usb_typec_top_00__reg_00_cc2_rp_en_BITEND, 0x0);

        /* Set HDPMI Hot Plug Low */
        Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_ADDR,
                    HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_BITSTART,
                    HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_ADDR,
                    HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_BITSTART,
                    HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_BITEND, 0x0);
        Hv_PM51_Gpio_SetIODirection(GPIO6, GPIO_OUTPUT);
        Hv_PM51_Gpio_SetIODirection(GPIO7, GPIO_OUTPUT);
        Hv_PM51_Gpio_SetOutputLevel(GPIO6, GPIO_LEVEL_LOW);
        Hv_PM51_Gpio_SetOutputLevel(GPIO7, GPIO_LEVEL_LOW);

        /* short det setting */
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_rx_standby_0p9_ADDR,
                    HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITSTART,
                    HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITEND, 0xC);/* reg_rx_standby_0p9 */

        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_ADDR,
                    HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_BITSTART,
                    HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_BITEND, 0xF);/* reg_rx_ckdet_en_0p9 */
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_BITEND, 0x0);/* reg_rxphy_short_det_enb */

        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_BITEND, 0x10E);  /* 0x10E For another para*/ /* 0x20F58 For another para*/ /* 0x3B538 For another para*/
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_BITEND, 0x1);  /* 0x41EB0 For another para*/ /* 0x20F58 For another para*/ /* 0x6978 For another para*/
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_BITEND, 0x10E);   /* 0x10E For another para*/ /* 0x20F58 For another para*/ /* 0x3B538 For another para*/
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_BITEND, 0x1);   /* 0x41EB0 For another para*/ /* 0x20F58 For another para*/ /* 0x6978 For another para*/

        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITEND, 0xC);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITEND, 0x0);
    }
    else
#endif
    {
        Hv_PM51_PM_DpmsEnable();

        /* short det setting */
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_rx_standby_0p9_ADDR,
                    HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITSTART,
                    HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITEND, 0xC);/* reg_rx_standby_0p9 */

        Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_ADDR,
                    HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_BITSTART,
                    HS_Standby__standby_peri_reg__reg_rx_ckdet_en_0p9_BITEND, 0xF);/* reg_rx_ckdet_en_0p9 */
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_enb_BITEND, 0x0);/* reg_rxphy_short_det_enb */

        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_l_num_BITEND, 0x10E);  /* 0x10E For another para*/ /* 0x20F58 For another para*/ /* 0x3B538 For another para*/
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy2_short_det_pwm_h_num_BITEND, 0x41EB0);  /* 0x41EB0 For another para*/ /* 0x20F58 For another para*/ /* 0x6978 For another para*/
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_l_num_BITEND, 0x10E);   /* 0x10E For another para*/ /* 0x20F58 For another para*/ /* 0x3B538 For another para*/
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy3_short_det_pwm_h_num_BITEND, 0x41EB0);   /* 0x41EB0 For another para*/ /* 0x20F58 For another para*/ /* 0x6978 For another para*/

        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITEND, 0x0);
        Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_ADDR,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITSTART,
                    HS_Standby__standby_mcu_reg__reg_rxphy_short_det_pwm_update_en_BITEND, 0xC);

        /* Set HDPMI Hot Plug High */
        Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_ADDR,
                    HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_BITSTART,
                    HS_Standby__HDMI21_RX_CEC_00__reg_00_HPD_BITEND, 0x1);
        Hv_PM51_Reg_WriteMask(HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_ADDR,
                    HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_BITSTART,
                    HS_Standby__HDMI21_RX_CEC_01__reg_01_HPD_BITEND, 0x1);
        #if HV_BOARD_CONFIG_HDMI_HPD_5V
        /* HDMI HPD GPIO OE Setting */
        Hv_PM51_Gpio_SetIODirection(GPIO6, GPIO_INPUT);
        Hv_PM51_Gpio_SetIODirection(GPIO7, GPIO_INPUT);
        #endif
    }

#if (HV_PROJECT_CONFIG_ESEGMENT_PM51 == HV_CONFIG_ON)
    Hv_PM51_Sys_HdmiEdidSegmentInit();
#endif

#if PM51_DEBUG_DUMMY_REGS
    Hv_PM51_Reg_WriteByte(PM51_DEBUG_PM_STATUS_ADDR, PM51_DEBUG_PM_STATUS_STANDBY);
    Hv_PM51_Reg_WriteByte(PM51_DEBUG_RISC_BOOT_STATUS_ADDR, PM51_DEBUG_RISC_BOOT_STATUS_NOT_BOOT);
    Hv_PM51_Reg_WriteByte(PM51_DEBUG_WAKEUP_REASON_ADDR, 0);
#endif

    return;
}

void Hv_PM51_PM_EnterPowerOff(void)
{
    xULONG32 ulRData32;

    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_apb_clk_sel_ADDR); /*  APB CLK sel reg_apb_clk_sel */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_apb_clk_sel_ADDR, ulRData32 | BIT_4);
    
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR); /*  Standby reset reg_stb_sw_rst_n */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR, ulRData32 & ~(BIT_0));
    
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR); /* Enable Iso reg_stby_iso */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR, ulRData32 | BIT_1);
    
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_power_on_ADDR); /* POWER OFF reg_power_on */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_power_on_ADDR, ulRData32 & ~(BIT_2));
    
    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__AON_REG__reg_pmu_mcu_off_req_ADDR);/*  OFF mode request reg_pmu_mcu_off_req */
    ulRData32 = ulRData32 | BIT_16;
    Hv_PM51_Reg_Write(HS_Standby__AON_REG__reg_pmu_mcu_off_req_ADDR, ulRData32);

    Hv_PM51_PM_SetHpdLow();
}

/*  Boot MIPS */
void Hv_PM51_PM_BootUpSequense(UCHAR8 ucType, UCHAR8 ucVal)
{
    xULONG32 ulRData32;
    xdata Msg stMsg;

    Hv_PM51_Uart_Print("PM51 BootUp MIPS Sequense...\r\n");
    ulRData32 = Hv_PM51_Reg_ReadMask(HS_Standby__standby_mcu_reg__regr_power_on_ADDR,
                           HS_Standby__standby_mcu_reg__regr_power_on_BITSTART,
                           HS_Standby__standby_mcu_reg__regr_power_on_BITEND);

    if(ulRData32 == 1)
    {
       return;
    }

    Hv_PM51_Sys_SetKeyState(HV_FALSE);
    Hv_PM51_Sys_SetStandby2DCTimerState(HV_FALSE);

#if DPMS_TYPEC0_ENABLE
    Hv_PM51_Timer_Clear(INNERTIMER1);
#endif

    /* handover spi to mips */
    ulRData32 = Hv_PM51_Reg_Read(0x11008400);  /* spi_func_sel */
    ulRData32 = ulRData32 & ~(BIT_16)
                      & ~(BIT_17)
                      & ~(BIT_18)
                      & ~(BIT_19)
                      & ~(BIT_20)
                      & ~(BIT_21);
    Hv_PM51_Reg_Write(0x11008400, ulRData32);

    PM_DpmsDisable();

    ulRData32 = Hv_PM51_Reg_Read(HS_Standby__standby_mcu_reg__reg_power_on_ADDR);
    ulRData32 = ulRData32 | (BIT_2);  /* power_on = 1 */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_power_on_ADDR, ulRData32);
    /* wait for DCDC work */
    Hv_PM51_Sys_DelayMs(5);
    ulRData32 = ulRData32 & ~(BIT_1);  /* stby_iso = 0 */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stby_iso_ADDR, ulRData32);
    Hv_PM51_Sys_DelayMs(1);
    ulRData32 = ulRData32 | (BIT_0);  /* stb_sw_rst release */
    Hv_PM51_Reg_Write(HS_Standby__standby_mcu_reg__reg_stb_sw_rst_n_ADDR, ulRData32);

    /* clk setting for typec */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_typec0_clk_en_ADDR,
                        HS_Standby__standby_mcu_reg__reg_typec0_clk_en_BITSTART,
                        HS_Standby__standby_mcu_reg__reg_typec0_clk_en_BITEND, 0x1);  /* reg_typec0_clk_en */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_typec1_clk_en_ADDR,
                        HS_Standby__standby_mcu_reg__reg_typec1_clk_en_BITSTART,
                        HS_Standby__standby_mcu_reg__reg_typec1_clk_en_BITEND, 0x1);  /* reg_typec1_clk_en */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_typec0_pclk_en_ADDR,
                        HS_Standby__standby_mcu_reg__reg_typec0_pclk_en_BITSTART,
                        HS_Standby__standby_mcu_reg__reg_typec0_pclk_en_BITEND, 0x1);  /* reg_typec0_pclk_en */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_mcu_reg__reg_typec1_pclk_en_ADDR,
                        HS_Standby__standby_mcu_reg__reg_typec1_pclk_en_BITSTART,
                        HS_Standby__standby_mcu_reg__reg_typec1_pclk_en_BITEND, 0x1);  /* reg_typec1_pclk_en */
    /* disable typec0 interrupt */
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2D81_PD_RX_IRQ_Mask_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2D83_PD_RX_FSM_SOP_IRQ_Mask_BITEND, 0x0); 
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_ADDR,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCD_IRQ_mask_for_VBUS_or_VCONN_Power_detection_BITSTART,
                      HS_Standby__usb_typec_1_00__REG_00_RW_2DCF_IRQ_mask_for_connection_detection_FSM_BITEND, 0x0);
    /* clear typec0 interrupt flag */
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C01_RX_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C03_RXFSM_SOP_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C04_RXFSM_SOPP_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C07_RSTFSM_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C08_PE_TIMER_IRQFLAG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0B_Reserved_for_PE_TIMER_IRQFLAG_BITEND, 0x0);
    Hv_PM51_Reg_WriteMask(HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_ADDR,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0C_PD_TOP_IRQFALG_BITSTART,
                      HS_Standby__usb_typec_0_00__REG_00_RO_2C0F_IRQ_MISC_BITEND, 0x0);
    /* set reg_rx_standby_0p9 = 0 */
    Hv_PM51_Reg_WriteMask(HS_Standby__standby_peri_reg__reg_rx_standby_0p9_ADDR,
                      HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITSTART,
                      HS_Standby__standby_peri_reg__reg_rx_standby_0p9_BITEND, 0x0);

#if SILLICON_CLK_OSC
    /* clk sel setting for OSC 27MHz */
    Hv_PM51_Reg_WriteMask(0x1101100c, 3, 3, 0x1);    /* reg_axi_clk_sel */
    Hv_PM51_Reg_WriteMask(0x1101100c, 4, 4, 0x1);    /* reg_cpu_clk_sel */
    Hv_PM51_Reg_WriteMask(0x1101100c, 5, 6, 0x1);    /* reg_cpu_src_sel */
    Hv_PM51_Reg_WriteMask(0x1101100c, 0, 0, 0x1);    /* reg_apb_clk_sel */
#else
    /* syspll setting */ /* CPU_AXI:621Mhz 497.8MHz APB:191.077MHz */
    Hv_PM51_Reg_WriteMask(0x1101102C, 25, 30, 0x1);  /* reg_syspll_prediv */
    Hv_PM51_Reg_WriteMask(0x11011030, 0, 9, 0x5c);   /* reg_syspll_fbdiv_int */
    Hv_PM51_Reg_WriteMask(0x11011030, 16, 31, 0x0);  /* reg_syspll_fbdiv_frac */
    Hv_PM51_Reg_WriteMask(0x11011034, 0, 9, 0xd);    /* reg_syspll_postdiv0 */
    Hv_PM51_Reg_WriteMask(0x11011034, 10, 19, 0x5);  /* reg_syspll_postdiv1 */
    Hv_PM51_Reg_WriteMask(0x11011034, 20, 29, 0x4);  /* reg_syspll_postdiv2 */
    Hv_PM51_Reg_WriteMask(0x11011038, 0, 0, 0x0);    /* reg_syspll_postdiv0_div2 */
    Hv_PM51_Reg_WriteMask(0x11011038, 1, 6, 0x1);    /* reg_syspll_postdiv0_0 */
    Hv_PM51_Reg_WriteMask(0x11011038, 7, 12, 0x1);   /* reg_syspll_postdiv0_1 */

    /* clk sel setting for pll */
    Hv_PM51_Reg_WriteMask(0x1101100c, 3, 3, 0x0);    /* reg_axi_clk_sel */
    Hv_PM51_Reg_WriteMask(0x1101100c, 4, 4, 0x0);    /* reg_cpu_clk_sel */
    Hv_PM51_Reg_WriteMask(0x1101100c, 5, 6, 0x0);    /* reg_cpu_src_sel */
    Hv_PM51_Reg_WriteMask(0x1101100c, 0, 0, 0x0);    /* reg_apb_clk_sel */
#endif
    /* clk en */
    Hv_PM51_Reg_WriteMask(0x11011000, 1, 1, 0x1);    /* reg_src_clk_en */
    Hv_PM51_Reg_WriteMask(0x11011000, 5, 5, 0x1);    /* reg_blk2_arb_aclk_en */
    Hv_PM51_Reg_WriteMask(0x11011000, 7, 7, 0x1);    /* reg_blk2_osc_clk_en */
    Hv_PM51_Reg_WriteMask(0x11011000, 8, 8, 0x1);    /* reg_blk2_sh1_aclk_en */
    /* rstn */
    Hv_PM51_Reg_WriteMask(0x11011004, 2, 2, 0x1);    /* reg_cpu_rst_n */
    Hv_PM51_Reg_WriteMask(0x11011004, 3, 3, 0x1);    /* reg_axi_rst_n */
    Hv_PM51_Reg_WriteMask(0x11011004, 15, 15, 0x1);  /* reg_sh5_axi_rst_n */
    Hv_PM51_Reg_WriteMask(0x11011004, 16, 16, 0x1);  /* reg_sw_rst_n */
    Hv_PM51_Reg_WriteMask(0x11011004, 18, 18, 0x1);  /* reg_syspll_rst_n */
    Hv_PM51_Reg_WriteMask(0x11011004, 20, 20, 0x1);  /* reg_sh1_axi_rst_n */
    Hv_PM51_Reg_WriteMask(0x11011004, 24, 24, 0x1);  /* reg_sh6_sscg_rst_n */

    /* mailbox wakeup reason to MIPS */
    stMsg.stMsgHeader.u8MsgType = E_MAILBOX_CMD_PM_TO_RISC_WAKEUP;
    stMsg.stMsgHeader.pu8MsgLen[0] = 2;
    stMsg.u8Val[0] = ucType; /* wakeup reason */
    stMsg.u8Val[1] = 0;
    stMsg.u8Val[2] = 0;
    stMsg.u8Val[3] = 0;
    stMsg.u8Val[4] = ucVal;  /* key val, IR val or channel index, ect */
    stMsg.u8Val[5] = 0;
    stMsg.u8Val[6] = 0;
    stMsg.u8Val[7] = 0;
    Hv_PM51_Reg_WriteArray(HS_Standby__standby_mcu_reg__reg_stby_reg1_ADDR, *(ULONG32 *)&stMsg.u8Val[0]);
    Hv_PM51_Reg_WriteArray(HS_Standby__standby_mcu_reg__reg_stby_reg2_ADDR, *(ULONG32 *)&stMsg.u8Val[4]);
    Hv_PM51_Reg_WriteArray(HS_Standby__standby_mcu_reg__reg_stby_reg3_ADDR, *(ULONG32 *)&stMsg.u8Val[8]);
    Hv_PM51_Reg_WriteArray(HS_Standby__standby_mcu_reg__reg_stby_reg0_ADDR, *(ULONG32 *)&stMsg);

#if BOOTUP_MIPS_ENABLE    
    if(ucDbBuffer == 0xaa)
    {
        Hv_PM51_Reg_WriteMask(0x11011110, 12, 31, MIPS_BOOT_ADDR_2ND);   /* mips0_ExceptionBase 1 */
    }
    else
    {
        Hv_PM51_Reg_WriteMask(0x11011110, 12, 31, MIPS_BOOT_ADDR);   /* mips0_ExceptionBase 0 */
    }
    Hv_PM51_Sys_DelayMs(10);
    Hv_PM51_Reg_WriteMask(0x11011114, 4, 4, 0);           /* mips0_reg_rstn */
    Hv_PM51_Reg_WriteMask(0x11011114, 4, 4, 1);
    
    Hv_PM51_Uart_Print("PM51 BootUp MIPS Sequense done!\r\n");
#else
    Hv_PM51_Uart_Print("PM51 Does Not Support Booting MIPS!\r\n");
#endif
    if (ucType)
    {
        ucACBootFlag = 0xaa;
    }
#if BOOTUP_MIPS_RETRY
    Hv_PM51_Sys_SetMipsBootTimerState(HV_TRUE);
    Hv_PM51_Timer_Set(EXTIMER1, MIPS_BOOT_TIMEOUT);  
#endif

#if PM51_DEBUG_DUMMY_REGS
    Hv_PM51_Reg_WriteByte(PM51_DEBUG_PM_STATUS_ADDR, PM51_DEBUG_PM_STATUS_NORMAL);
    Hv_PM51_Reg_WriteByte(PM51_DEBUG_WAKEUP_REASON_ADDR, (ucType+1));
#endif
}

void Hv_PM51_PM_EnterIdle(void)
{
#if (PM51_CONFIG_POWER_KEY_MODE & POWER_KEY_MODE_MULTI)
    if(g_bPowerKeyHold)
    {
        xULONG32 ulRData32 = 0;

        ulRData32 = Hv_PM51_Reg_ReadMask(HS_Standby__AON_REG__regr_pwr_key_di_ADDR, 
                                   HS_Standby__AON_REG__regr_pwr_key_di_BITSTART, 
                                   HS_Standby__AON_REG__regr_pwr_key_di_BITEND);

        if(ulRData32)
        {
            xdata Msg stMsg;
            stMsg.u8Val[0] = E_POWER_KEY_VAL_0;
            stMsg.stMsgHeader.u8MsgType = E_MAILBOX_CMD_PM_TO_RISC_KEY_UPSPRING;
            stMsg.stMsgHeader.pu8MsgLen[0] = 1;
            Hv_PM51_Mailbox_Send(&stMsg);
            g_bPowerKeyHold = HV_FALSE;
        }
        else
        {
            return;
        }
    }
#endif
    if((g_unIntFlag.All == 0) && (Hv_PM51_Mailbox_MsgPoolIsEmpty()))
    {
        //Hv_PM51_Uart_Print("PM51 Go Idle!\r\n");
        /* PCON.7 SMOD Double baud rate bit. For use, see the Serial Interface section below. */
        /* PCON.6 Not implemented. Returns zero when read. */
        /* PCON.5 Not implemented. Returns zero when read. */
        /* PCON.4 Not implemented. Returns zero when read. */
        /* PCON.3 GF1 General purpose flag bit. */
        /* PCON.2 GF0 General purpose flag bit. */
        /* PCON.1 PD Power-Down bit. If 1, Power-Down mode is entered. NO USE */
        /* PCON.0 IDL Idle bit. If 1, Idle mode is entered. */
        PCON |=  BIT_0;
    }
}

void Hv_PM51_PM_PowerOnReadE2P(void)
{

    xUCHAR8 ucCurStatus;
    ucCurStatus = Hv_PM51_I2C_E2PReadByte(I2C_EEPROM_DEFAULT_ID, CUR_STATUS_E2P_ADDR, 0);

    if((ucCurStatus == POWER_STATE_OFF) && ucACBootFlag)
    {
        ucPowerState = POWER_STATE_OFF;
#if PM51_CONFIG_FAKE_DC
        Hv_PM51_PM_EnterStandBy();
        Hv_PM51_PM_SetHpdLow();
#else
        Hv_PM51_PM_EnterPowerOff();
#endif
    }
    else
    {
        if(ucACBootFlag){
            Hv_PM51_Reg_WriteMask(HS_Standby__AON_REG__reg_first_start_flag_ADDR,
                              HS_Standby__AON_REG__reg_first_start_flag_BITSTART,
                              HS_Standby__AON_REG__reg_first_start_flag_BITEND, 0);
        }
    }
}

void Hv_PM51_PM_PowerOnCheckPmu(void)
{
    xULONG32 ulRData32;
    ulRData32 = Hv_PM51_Reg_ReadMask(HS_Standby__AON_REG__reg_first_start_flag_ADDR,
                               HS_Standby__AON_REG__reg_first_start_flag_BITSTART,
                               HS_Standby__AON_REG__reg_first_start_flag_BITEND);


    if(ulRData32 == 1)
    {
        ucACBootFlag = HV_TRUE;
    }
    else
    {
        ucACBootFlag = HV_FALSE;
    }

#if (HV_BOARD_CONFIG_DATABASE_STORAGE_TYPE == STORAGE_EEPROM)
    /* I2C Init */
    Hv_PM51_I2C_Init();
    Hv_PM51_PM_PowerOnReadE2P();
#endif
}

