/**
 * @file  hv_drv_TypecHardware.h
 * @brief   UPD Hardware Abstraction layer file
 *          This header file contains the functions for UPD350 hardware interface access
 *          for GPIO, Register access, PIO override
 * @details This file provides the following functions: \n
 *          (1) \n
 *          (2) \n
 *          (3) \n
 *
 * 
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-25
 * @copyright Copyright(c),2022-8, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date         <th>Change Description
 * <tr><td>Hiview SoC Software Team       <td>2022-08-25   <td>init
 * </table>
*/

#ifndef _HV_DRV_TYPECHARDWARE_H_
#define _HV_DRV_TYPECHARDWARE_H_

#define UPD_PORT0_BASE_ADDR                           0xB100A000
#define UPD_PORT1_BASE_ADDR                           0xB100A900

#define UPD_CC_DRP_DELAY_CNT                          0x0224

#define UPD_CC_RP_EN_DRP_ROLE                         0x0254
#define UPD_CC_PREN_DRP_NOREALCHIP                    BIT(0)
#define UPD_CC_PREN_DRP_REALCHIP                      BIT(1)

#define UPD_REG_CC_CHIP_CONFIG                        0x0204
#define UPD_CC0_DET_2BIT_EN                           BIT(6)
#define UPD_CC1_DET_2BIT_EN                           BIT(7)

#define UPD_REG_CC_SW_CONFIG                          0x0205
#define UPD_SW_CTRL_RD_EN                             BIT(0)
#define UPD_SW_CTRL_RP_EN                             BIT(1)

#define UPD_REG_TYPEC_VBUS_VALUE                      0x0228
#define UPD_TYPEC_VBUS_VALUE_MASK                     0xFF

#define UPD_REG_TYPEC_VBUS_SEL                        0x0229
#define UPD_TYPEC_VBUS_SEL_MASK                       BIT(0)

#define UPD_REG_TYPEC_TRIM_INITIAL                    0x0191

//pd base setting
#define UPD_REG_RW_MODULE_CLOCK                       0x0101
#define UPD_REG_RW_FSM_CLK                            0x01A0
#define UPD_REG_RW_IDLE_COUNTER_LEN                   0x010D

#define UPD_REG_RW_TYPEC_RST                          0x0200
#define UPD_REG_RW_CLK_FREQ                           0x0230

#define UPD_REG_RW_BIST_PATT_CTRL                     0x0112
#define UPD_BIST_PATT_CTRL_MASK                       BIT(7)

//vbus and vconn pwr detection config
#define UPD_REG_RW_VBUS_VCONN_CONFIG                  0x01A1
#define UPD_REG_RW_VBUS_VCONN_IRQ_EDGE                0x01A2
#define UPD_REG_RW_PLUG_FLIP_DET_CONFIG               0x01A6
#define UPD_CC_RP_EN_MASK                             BIT(0)
#define UPD_CC_SEL_PLUG_MASK                          BIT(1)
#define UPD_PLUG_APP_MODE_MASK                        BIT(2)

//tx bit rate
#define UPD_REG_RW_TX_MSG_BITRATE                     0x0115
#define UPD_REG_RW_CONFIG_LOW                         0x0208
#define UPD_REG_RW_CONFIG_HIGH                        0x0209
//PWR
#define UPD_REG_RW_VBUS_ON_TH                         0x0210
#define UPD_REG_RW_VBUS_OFF_TH                        0x0211
#define UPD_REG_RW_VCONN_ON_TH                        0x0214
#define UPD_REG_RW_VCONN_OFF_TH                       0x0215
#define UPD_REG_RW_VSINK_DISCONNECT_TH                0x0218
#define UPD_REG_RW_VSINK_DISCONNECT_PD_TH             0x0219
#define UPD_REG_RW_VSAFE0V_TH                         0x021A
#define UPD_REG_RW_VVCONN_DISCONNECT_TH               0x021B
#define UPD_REG_RW_VVCONN_DISCHARGE_TH                0x021C
#define UPD_REG_RW_VRD_USB_TH                         0x021D
//TIMER
#define UPD_REG_RW_TERROR_RECOVERY                    0x0231
#define UPD_REG_RW_TCCDEBOUNCE                        0x0232
#define UPD_REG_RW_TPDDEBOUNCE                        0x0233
#define UPD_REG_RW_TTRYCCDEBOUNCE                     0x0234
#define UPD_REG_RW_TDRP                               0x0235
#define UPD_REG_RW_DCSRC_DRP                          0x0236
#define UPD_REG_RW_TDRP_TRY                           0x0237
#define UPD_REG_RW_TDRP_TRYWAIT                       0x0238            //2 bytes
#define UPD_REG_RW_TTRY_TIMEOUT                       0x023A            //2 bytes
//DRP
#define UPD_REG_RW_DRP_CONFIG                         0x0240
//RX and TX message control
#define UPD_REG_RW_RX_TX_MAC_CTL                      0x013C
#define UPD_REG_RW_RX_SOP_TYPE_SET                    0x0102
#define UPD_REG_RO_RX_MSG_DATA_BASE                   0x0700
#define UPD_REG_RO_RX_SOP_TYPE                        0x003F
#define UPD_REG_RO_RX_CRC                             0x0041
#define UPD_REG_RW_TX_MSG_CONTROL                     0x0112
#define UPD_REG_RW_TX_MSG_CONTROL1                    0x0113
#define UPD_REG_RW_TX_SOP_TYPE_SET                    0x0107
#define UPD_REG_RW_TX_RETRY_COUNTER                   0x013D
#define UPD_REG_RW_TX_MSG_DATA_BASE                   0x0500
#define UPD_REG_RW_TX_CRC                             0x0116
#define UPD_REG_RW_TX_MSG_BUFFER_CTRL                 0x0114
//msg id reset
#define UPD_REG_RW_MSGID_RST_SOP                      0x013E
//hard reset
#define UPD_REG_RW_MCU_FINISH_HARD_RST_SET            0x013F
//CC SET
#define UPD_REG_RW_CC_CHG_CNT                         0x01B0            //cc votage det filter
#define UPD_REG_RW_CC_CHG_THD                         0x01B1
#define UPD_REG_RW_CC_ADC_IN_DB                       0x0223
#define UPD_REG_RW_CC_RPRD_SET                        0x0204

#define UPD_REG_RW_CC_RA_THRD                         0x0220
#define UPD_REG_RW_CC_RD_THRD                         0x0221
#define UPD_REG_RW_SINK_CON_TH                        0x0222
#define UPD_REG_RW_CC1_ADC_IN                         0x0248
#define UPD_REG_RW_CC2_ADC_IN                         0x024A
//FSM STATE INIT
#define UPD_REG_RW_FSM_CMD_DIRECT                     0x023C

//interrupt - FLAG
#define UPD_REG_RO_RX_IRQFLAG                         0x0001
#define UPD_REG_RO_TX_IRQFLAG                         0x0002
#define UPD_REG_RO_PWR_DET_IRQFLAG_ALIGN              0x000C
#define UPD_REG_RO_PWR_DET_IRQFLAG                    0x000D
#define UPD_REG_RO_CCVOL_DET_IRQFLAG                  0x000E
#define UPD_REG_RO_TXFSM_SOP_IRQFLAG                  0x0005            //bit2 tx fail, bit4 tx done
#define UPD_REG_RO_TXFSM_SOP_P_IRQFLAG                0x0006            //bit2 tx fail, bit4 tx done
#define UPD_REG_RO_MISC_IRQFLAG                       0x000F            //bit1 for DRP done

//interrupt - Mask
#define UPD_REG_RW_RX_IRQMASK                         0x0181
#define UPD_REG_RW_TX_IRQMASK                         0x0182
#define UPD_TX_GCRC_FOR_RXMSG_MSKBIT                  BIT(1)
#define UPD_REG_RW_PWR_DET_IRQMASK                    0x01CD
#define UPD_REG_RW_CCVOL_DET_IRQMASK                  0x01CE
#define UPD_REG_RW_TXFSM_SOP_IRQMASK                  0x0185
#define UPD_REG_RW_TXFSM_SOP_P_IRQMASK                0x0186
#define UPD_REG_RW_MISC_IRQMASK                       0x01CF

//UPD EXTERNAL CTRL, VBUS, DISCHA
#define UPD_REG_RW_EXTEN_CTRL0                        0x0250
#define UPD_REG_RW_EXTEN_CTRL1                        0x0251

#define UPD_REG_RW_CC_VCONN_SEL                     0x0204
#define UPD_VCONN_CC1_SEL                           BIT(4)
#define UPD_VCONN_CC2_SEL                           BIT(5)

//FSM state
#define UPD_REG_RO_FSM_STATE                        0x024C
#define UPD_FSM_STATE_MASK                          0x1F            //bit0-bit4
#define UPD_FSM_STATE_ATTACHED_SNK                  4
#define UPD_FSM_STATE_ATTACHED_SRC                  8

//sleep mode 
#define UPD_REG_PHY_SLEEP_MODE                      0x0410

//base setting
#define UPD_CONFIG_LOW_PWRROLE_MASK                  (BIT(0)|BIT(1))
#define UPD_CONFIG_LOW_PWRROLE_SOURCE                0
#define UPD_CONFIG_LOW_PWRROLE_SINK                  1
#define UPD_CONFIG_LOW_PWRROLE_DRP                   2
#define UPD_CONFIG_LOW_PWRROLE_POS                   0
#define UPD_CONFIG_LOW_DRP_PREFERENCE                BIT(2)            //0: source, 1: sink
#define UPD_CONFIG_LOW_SELF_POWERED                  BIT(3)
#define UPD_CONFIG_LOW_ACCSRY_SUPPORT                BIT(4)
#define UPD_CONFIG_LOW_DEBUG_ACCSRY_SUPPORT          BIT(5)
#define UPD_CONFIG_LOW_VCONN_ACCSRY_SUPPORT          BIT(6)
#define UPD_CONFIG_HIGH_PD_SUPPORT                   BIT(0)
#define UPD_CONFIG_HIGH_TRY_SRC_SUPPORT              BIT(1)
#define UPD_CONFIG_HIGH_TRY_SINK_SUPPORT             BIT(2)
#define UPD_CONFIG_HIGH_VBUS_OPERATE_MODE            BIT(3)            //0: <=5V, 1: >5V
//RSTN
#define UPD_TYPEC_PD_RST_RSTN_PERI                   BIT(0)
#define UPD_TYPEC_PD_RST_RSTN_CCDET                  BIT(1)
#define UPD_TYPEC_PD_RST_RSTN_USBPD                  BIT(2)
//DRP
#define UPD_DRP_CONFIG_PR_SWAP_INFLOW               BIT(2)
#define UPD_DRP_CONFIG_PR_SWAP_RDY                  BIT(3)
#define UPD_DRP_CONFIG_PR_SWAP_ACCEPT               BIT(4)
#define UPD_DRP_CONFIG_TOGGLE_EN                    BIT(5)

//CC RP RD
#define UPD_CC_RPRD_SET_MASK                        (BIT(0) | BIT(1) | BIT(2)| BIT(3))
#define UPD_CC_RPRD_RDEN_CC1                        BIT(0)
#define UPD_CC_RPRD_RDEN_CC2                        BIT(1)
#define UPD_CC_RPRD_RPEN_CC1                        BIT(2)
#define UPD_CC_RPRD_RPEN_CC2                        BIT(3)

//FSM STATE INIT
#define UPD_FSM_CMD_DIRECT_MASK                      0x1F            //[4:0]
#define UPD_FSM_CMD_DIRECT_POS                       0
#define UPD_FSM_CMD_DIRECT_EN                        BIT(6)            //BIT5 force to enter one state all the time, no use

//RX TX CHEN
#define UPD_RXTX_CTL_RX_CHEN                        BIT(0)
#define UPD_RXTX_CTL_TX_CHEN                        BIT(1)
//RX TX SOP
#define UPD_RX_SOP_TYPE_MASK                        0x3F
#define UPD_RX_SOP_TYPE_SOP                         BIT(0)
#define UPD_RX_SOP_TYPE_SOP_P                       BIT(1)
#define UPD_RX_SOP_TYPE_SOP_PP                      BIT(2)
#define UPD_RX_SOP_TYPE_SOP_P_D                     BIT(3)
#define UPD_RX_SOP_TYPE_SOP_PP_D                    BIT(4)
#define UPD_RX_SOP_TYPE_MYPAT                       BIT(5)
#define UPD_TX_SOP_TYPE_MASK                        0x3F
#define UPD_TX_SOP_TYPE_SOP                         BIT(0)
#define UPD_TX_SOP_TYPE_SOP_P                       BIT(1)
#define UPD_TX_SOP_TYPE_SOP_PP                      BIT(2)
#define UPD_TX_SOP_TYPE_SOP_P_D                     BIT(3)
#define UPD_TX_SOP_TYPE_SOP_PP_D                    BIT(4)
#define UPD_TX_SOP_TYPE_MYPAT                       BIT(5)
#define UPD_TX_SOP_TYPE_FIXED_EN                    BIT(6)
//TX retry counter set
#define UPD_TX_RETRY_COUNTER_MASK                   0xF0
#define UPD_TX_RETRY_COUNTER_POS                    4
//TX hard reset and cable reset set
#define UPD_TX_CONTROL1_CABLE_HARD_RST                BIT(1)        //set: cable reset, clear: hard reset
#define UPD_TX_CONTROL1_CABLE_HARD_RST_REQ            BIT(0)        //default rising edge active
#define UPD_MCU_FINISH_HARD_RST_SET                   BIT(0)        //set after mcu finish hard reset
//msg id reset
#define UPD_MSGID_RST_SOP_CTRL                      BIT(0)
#define UPD_MSGID_RST_SOP_SEL                       BIT(1)
#define UPD_MSGID_RST_SOPP_CTRL                     BIT(2)
#define UPD_MSGID_RST_SOPP_SEL                      BIT(3)

//interrupt - Mask BIT
#define UPD_RX_MSG_RECEIVE_MASKBIT                  BIT(0)
#define UPD_RX_HARD_RST_MASKBIT                     BIT(1)
#define UPD_RX_CABLE_RST_MASKBIT                    BIT(2)
#define UPD_RX_CHANNEL_BUSY_MASKBIT                 BIT(3)
#define UPD_RX_GOODCRC_RECEIVE_MASKBIT              BIT(4)
#define UPD_TX_MSG_SEND_MASKBIT                     BIT(0)        //TO CONFIRM, no use now
#define UPD_CCVOL_DET_CC0_CHG_MASKBIT               BIT(0)        //for attach and detach
#define UPD_CCVOL_DET_CC1_CHG_MASKBIT               BIT(1)        //for attach and detach
#define UPD_CCVOL_DET_CC_CHG_MASK                  (BIT(0) | BIT(1))
#define UPD_CCVOL_DET_CC_CHG_POS                    0
#define UPD_TXFSM_PHY_SEND_MSG_MASKBIT              BIT(0)
#define UPD_TXFSM_NOGCRC_TIME_OUT_MASKBIT           BIT(1)
#define UPD_TXFSM_TX_FAIL_MASKBIT                   BIT(2)
#define UPD_TXFSM_FSM_STAT_CHG_MASKBIT              BIT(3)
#define UPD_TXFSM_TX_DONE_MASKBIT                   BIT(4)
#define UPD_PWR_DET_CC_ADCIN_CHG_MASK               (BIT(5) | BIT(6))
#define UPD_PWR_DET_CC_ADCIN_CHG_POS                5
#define UPD_PWR_DET_CC1_ADCIN_CHG_MASKBIT           BIT(5)
#define UPD_PWR_DET_CC2_ADCIN_CHG_MASKBIT           BIT(6)
#define UPD_PWR_DET_CC_VCONN_ON_OFF_MASK            (BIT(2) | BIT(3))
#define UPD_PWR_DET_CC_VCONN_ON_MASKBIT             BIT(2)
#define UPD_PWR_DET_CC_VCONN_OFF_MASKBIT            BIT(3)
#define UPD_MISC_DRP_DONE_MASKBIT                   BIT(1)

//UPD EXTERNAL     - BIT CTRL
#define UPD_EXTEN_CTRL0_RP_DIS                      BIT(0)                //set 1 use default, set 0 use seta and setb to config
#define UPD_EXTEN_CTRL0_RES_SET_MASK                (BIT(1)|BIT(2))
#define UPD_EXTEN_CTRL0_RES_SETA                    BIT(1)
#define UPD_EXTEN_CTRL0_RES_SETB                    BIT(2)
#define UPD_EXTEN_CTRL0_RES_SET_POS                 1
#define UPD_EXTEN_CTRL0_AUX_PN_SET                  BIT(3)
#define UPD_EXTEN_CTRL0_CC1_RD_EN                   BIT(4)    //no use now
#define UPD_EXTEN_CTRL0_CC2_RD_EN                   BIT(5)  //no use now
#define UPD_EXTEN_CTRL0_CC1_VON_SW                  BIT(6)    //no use now
#define UPD_EXTEN_CTRL0_CC2_VON_SW                  BIT(7)    //no use now
//ctrl1
#define UPD_EXTEN_CTRL1_DISCHA                      BIT(0)
#define UPD_EXTEN_CTRL1_VBUS_PMU_EN                 BIT(1)
/*power role sel for rp/rd det in design*/
#define UPD_EXTEN_CTRL1_PWR_ROLE_SEL                BIT(2)

// *****************************************************************************
// *****************************************************************************
// Section: Constants
// *****************************************************************************
// *****************************************************************************
/* Defines used for 'u8IntrType' */
#define UPD_GPIO_CLEAR_INTR            0
/* use UPD_CFG_PIO_RISING_ALERT, UPD_CFG_PIO_FALLING_ALERT defines for rising & falling pio intr*/

/* UPD SPI Opcodes definition */

/*****************************************************************************************************/
/* UPD Address Base*/
#define UPD_SYSTEM_CSR_BASE_ADDR                    0x0000
#define UPD_HPD_BASE_ADDR                           0x0C00 
#define UPD_CLK_PWR_MGMT_CSR_BASE_ADDR              0x1000
/**************************************************************************************************/

/* System Control and Status Register */
#define UPD_VID                      (UPD_SYSTEM_CSR_BASE_ADDR + 0x04)
#define UPD_SPI_TEST                 (UPD_SYSTEM_CSR_BASE_ADDR + 0x0E)
#define UPD_HW_CTL                   (UPD_SYSTEM_CSR_BASE_ADDR + 0x18)
#define UPD_PIO_STS                  (UPD_SYSTEM_CSR_BASE_ADDR + 0x20)
#define UPD_PIO_STS_LOW              (UPD_SYSTEM_CSR_BASE_ADDR + 0x20)
#define UPD_PIO_STS_HIGH             (UPD_SYSTEM_CSR_BASE_ADDR + 0x21)
#define UPD_PIO_INT_STS              (UPD_SYSTEM_CSR_BASE_ADDR + 0x22)
#define UPD_PIO_INT_EN               (UPD_SYSTEM_CSR_BASE_ADDR + 0x24)

/* Configure PIOx Registers*/
#define UPD_CFG_PIO_BASE            (UPD_SYSTEM_CSR_BASE_ADDR + 0x30)                                                  
#define UPD_CFG_PIO0                (UPD_SYSTEM_CSR_BASE_ADDR + 0x30)
#define UPD_CFG_PIO1                (UPD_SYSTEM_CSR_BASE_ADDR + 0x31)
#define UPD_CFG_PIO2                (UPD_SYSTEM_CSR_BASE_ADDR + 0x32)
#define UPD_CFG_PIO3                (UPD_SYSTEM_CSR_BASE_ADDR + 0x33)
#define UPD_CFG_PIO4                (UPD_SYSTEM_CSR_BASE_ADDR + 0x34)
#define UPD_CFG_PIO5                (UPD_SYSTEM_CSR_BASE_ADDR + 0x35)
#define UPD_CFG_PIO6                (UPD_SYSTEM_CSR_BASE_ADDR + 0x36)
#define UPD_CFG_PIO7                (UPD_SYSTEM_CSR_BASE_ADDR + 0x37)
#define UPD_CFG_PIO8                (UPD_SYSTEM_CSR_BASE_ADDR + 0x38)
#define UPD_CFG_PIO9                (UPD_SYSTEM_CSR_BASE_ADDR + 0x39)
#define UPD_CFG_PIO10               (UPD_SYSTEM_CSR_BASE_ADDR + 0x3A)
#define UPD_CFG_PIO11               (UPD_SYSTEM_CSR_BASE_ADDR + 0x3B)
#define UPD_CFG_PIO12               (UPD_SYSTEM_CSR_BASE_ADDR + 0x3C)
#define UPD_CFG_PIO13               (UPD_SYSTEM_CSR_BASE_ADDR + 0x3D)
#define UPD_CFG_PIO14               (UPD_SYSTEM_CSR_BASE_ADDR + 0x3E)
#define UPD_CFG_PIO15               (UPD_SYSTEM_CSR_BASE_ADDR + 0x3F)

#define UPD_CFG_PIO_REGADDR(PIONum) (UPD_CFG_PIO_BASE + PIONum)

/* PIO override register*/
#define UPD_PIO_MON_VAL               (UPD_SYSTEM_CSR_BASE_ADDR + 0x54)
#define UPD_PIO_OVR_EN                (UPD_SYSTEM_CSR_BASE_ADDR + 0x55)
#define UPD_PIO_OVR_STS               (UPD_SYSTEM_CSR_BASE_ADDR + 0x56)
#define UPD_PIO_OVR_INT_STS           (UPD_SYSTEM_CSR_BASE_ADDR + 0x57)
#define UPD_PIO_OVR_INT_EN            (UPD_SYSTEM_CSR_BASE_ADDR + 0x58)
                                                                                                
#define UPD_CFG_PIO_OUT_LOW           (UPD_SYSTEM_CSR_BASE_ADDR + 0x59)
#define UPD_CFG_PIO_OUT_HIGH          (UPD_SYSTEM_CSR_BASE_ADDR + 0x5A)
#define UPD_CFG_PIO_OUT_UPD_LOW       (UPD_SYSTEM_CSR_BASE_ADDR + 0x5B)
#define UPD_CFG_PIO_OUT_UPD_HIGH      (UPD_SYSTEM_CSR_BASE_ADDR + 0x5C)
#define UPD_FRS_PIO_OVR_EN_MSK        (UPD_SYSTEM_CSR_BASE_ADDR + 0x5D)
                                                  
#define UPD_PIO_OVR_OUT               (UPD_SYSTEM_CSR_BASE_ADDR + 0x68)
#define UPD_PIO_OVR_DIR               (UPD_SYSTEM_CSR_BASE_ADDR + 0x6A)
                                                  
#define UPD_PIO_DEBOUNCE_10MS_COUNT (UPD_SYSTEM_CSR_BASE_ADDR + 0x6C)
#define UPD_PIO_DEBOUNCE_1MS_COUNT  (UPD_SYSTEM_CSR_BASE_ADDR + 0x6D)
#define UPD_PIO_DEBOUNCE_1US_COUNT  (UPD_SYSTEM_CSR_BASE_ADDR + 0x6E)
#define UPD_PIO_DEBOUNCE_EN         (UPD_SYSTEM_CSR_BASE_ADDR + 0x70)                                                  
                                                  
                                                                                           
#define UPD_TRIM_ZTC                (UPD_SYSTEM_CSR_BASE_ADDR + 0x98)
#define UPD_TRIM_ZTC_BYTE_3         (UPD_TRIM_ZTC + 0x02)
                                                  
#define UPD_PIO_OVR0_SRC_SEL        (UPD_SYSTEM_CSR_BASE_ADDR + 0xC0)                            
#define UPD_PIO_OVR1_SRC_SEL        (UPD_SYSTEM_CSR_BASE_ADDR + 0xC1)
#define UPD_PIO_OVR2_SRC_SEL        (UPD_SYSTEM_CSR_BASE_ADDR + 0xC2)                                                      
#define UPD_PIO_OVR3_SRC_SEL        (UPD_SYSTEM_CSR_BASE_ADDR + 0xC3)                                                      
#define UPD_PIO_OVR4_SRC_SEL        (UPD_SYSTEM_CSR_BASE_ADDR + 0xC4)                                                      
#define UPD_PIO_OVR5_SRC_SEL        (UPD_SYSTEM_CSR_BASE_ADDR + 0xC5)                                                      
                                                  
#define UPD_PIO_OVR0_OUT_EN            (UPD_SYSTEM_CSR_BASE_ADDR + 0xD0)                                
#define UPD_PIO_OVR1_OUT_EN            (UPD_SYSTEM_CSR_BASE_ADDR + 0xD2)
#define UPD_PIO_OVR2_OUT_EN            (UPD_SYSTEM_CSR_BASE_ADDR + 0xD4)                                                      
#define UPD_PIO_OVR3_OUT_EN            (UPD_SYSTEM_CSR_BASE_ADDR + 0xD6)                                                      
#define UPD_PIO_OVR4_OUT_EN            (UPD_SYSTEM_CSR_BASE_ADDR + 0xD8)                                                      
#define UPD_PIO_OVR5_OUT_EN            (UPD_SYSTEM_CSR_BASE_ADDR + 0xDA)        
           
#define UPD_HPD_CTL                 (UPD_HPD_BASE_ADDR + 0x00)
#define UPD_HPD_INT_STS             (UPD_HPD_BASE_ADDR + 0x01)
#define UPD_HPD_INT_EN              (UPD_HPD_BASE_ADDR + 0x02)
#define UPD_HPD_QUEUE               (UPD_HPD_BASE_ADDR + 0x03)
#define UPD_IRQ_HPD_MIN_TIME        (UPD_HPD_BASE_ADDR + 0x04)
#define UPD_IRQ_HPD_MAX_TIME        (UPD_HPD_BASE_ADDR + 0x05)
#define UPD_HPD_HIGH_DET_TIME       (UPD_HPD_BASE_ADDR + 0x06)
#define UPD_HPD_LOW_DET_TIME        (UPD_HPD_BASE_ADDR + 0x08)
/**************************************************************************************************/

/* Defines for PIO Overridex Source Select Register (PIO_OVRx_SRC_SEL)*/
/* defines for Override Select[4:0]*/
#define UPD_PIO_OVR_SRC_SEL_VBUS_THR                0x11
#define UPD_PIO_OVR_SRC_SEL_VBUS_THR_AND_FRS_DET    0x12 
#define UPD_PIO_OVR_SRC_SEL_FRS_SIG_DETECTED        0x13 
/* define for VBUS Threshold Select [7:5] field*/                                              
#define UPD_PIO_OVR_VBUS_THR_SEL_POS                5

#define UPD_PIO_OVR_VSAFE0V_THR_MATCH          (0 << UPD_PIO_OVR_VBUS_THR_SEL_POS)
#define UPD_PIO_OVR_VBUS0_THR_MATCH            (1 << UPD_PIO_OVR_VBUS_THR_SEL_POS)
#define UPD_PIO_OVR_VBUS1_THR_MATCH            (2 << UPD_PIO_OVR_VBUS_THR_SEL_POS)    
#define UPD_PIO_OVR_VBUS2_THR_MATCH            (3 << UPD_PIO_OVR_VBUS_THR_SEL_POS)                                                      
#define UPD_PIO_OVR_VBUS3_THR_MATCH            (4 << UPD_PIO_OVR_VBUS_THR_SEL_POS)                                                      
#define UPD_PIO_OVR_VBUS4_THR_MATCH            (5 << UPD_PIO_OVR_VBUS_THR_SEL_POS)
                                                  
/* Override Selection bit define*/
#define UPD_PIO_OVR_0                        BIT(0)                                          
#define UPD_PIO_OVR_1                        BIT(1)
#define UPD_PIO_OVR_2                        BIT(2)    
#define UPD_PIO_OVR_3                        BIT(3)    
#define UPD_PIO_OVR_4                        BIT(4)
#define UPD_PIO_OVR_5                        BIT(5)        
                                                  
#define UPD_MCU_ACTIVE                      0
#define UPD_MCU_IDLE                        1 
                                                  
#define UPD_PIO_DEBOUNCE_FIELD_WIDTH        2

/*Debounce Enable type*/
#define UPD_PIO_DEBOUNCE_DISABLE            0                                                  
#define UPD_PIO_DEBOUNCE_CNT_TYP_1_US       1
#define UPD_PIO_DEBOUNCE_CNT_TYP_1_MS       2
#define UPD_PIO_DEBOUNCE_CNT_TYP_10_MS      3
#define UPD_PIO_DEBOUNCE_DISABLE_MASK       3                                                  
/*****************************************************************************************************/

/* Mask Macros of System Control and Status Register */

/* TRIM_ZTC */
#define UPD_PM_V2I_ENABLE                BIT(0)

/* TYPEC_HW_CTL Register Bits */
#define UPD_SRESET                        BIT(0)
#define UPD_DEV_READY                     BIT(2)
#define UPD_HW_CTL_REG_DEV_RDY_MSK        BIT(2)

/*****************************************************************************************************/

/* Clock and Power Management control and status register */ 
#define UPD_CLK_CTL                     (UPD_CLK_PWR_MGMT_CSR_BASE_ADDR + 0x00)
#define UPD_CC_SAMP_CLK                 (UPD_CLK_PWR_MGMT_CSR_BASE_ADDR + 0x06)
#define UPD_VBUS_SAMP_CLK               (UPD_CLK_PWR_MGMT_CSR_BASE_ADDR + 0x07)
#define UPD_CLK_GATE                    (UPD_CLK_PWR_MGMT_CSR_BASE_ADDR + 0x08)
#define UPD_CLK_GATE_LOW                (UPD_CLK_PWR_MGMT_CSR_BASE_ADDR + 0x08)
#define UPD_CLK_GATE_HIGH               (UPD_CLK_PWR_MGMT_CSR_BASE_ADDR + 0x09)

/*Defines for UPD_CC_SAMP_CLK register*/
#define UPD_CC_CLK_20_KHZ               0
#define UPD_CC_CLK_48_KHZ               BIT(3)

#define UPD_CC_SAMP_GEN_10_KS           0
#define UPD_CC_SAMP_GEN_50_KS           BIT(0)
#define UPD_CC_SAMP_GEN_100_KS          BIT(1)
#define UPD_CC_SAMP_GEN_200_KS          (BIT(0) | BIT(1))
#define UPD_CC_SAMP_GEN_250_KS          BIT(2)
#define UPD_CC_SAMP_GEN_300_KS          (BIT(0) | BIT(2))
#define UPD_CC_SAMP_GEN_375_KS          (BIT(1) | BIT(2))
#define UPD_CC_SAMP_GEN_500_KS          (BIT(0) | BIT(1) | BIT(2))

/*Defines for UPD_VBUS_SAMP_CLK register*/
#define UPD_VBUS_CLK_20_KHZ             0
#define UPD_VBUS_CLK_48_KHZ             BIT(3)

#define UPD_VBUS_SAMP_GEN_10_KS         0
#define UPD_VBUS_SAMP_GEN_50_KS         BIT(0)
#define UPD_VBUS_SAMP_GEN_100_KS        BIT(1)
#define UPD_VBUS_SAMP_GEN_200_KS        (BIT(0) | BIT(1))
#define UPD_VBUS_SAMP_GEN_250_KS        BIT(2)
#define UPD_VBUS_SAMP_GEN_300_KS        (BIT(0) | BIT(2))
#define UPD_VBUS_SAMP_GEN_375_KS        (BIT(1) | BIT(2))
#define UPD_VBUS_SAMP_GEN_500_KS        (BIT(0) | BIT(1) | BIT(2))
             
/*Defines for UPD_CLK_GATE_LOW register*/
#define UPD_GPT_CLK_GATE_EN             BIT(0)
#define UPD_PWR_SW_CLK_GATE_EN          BIT(1)
#define UPD_I2C_CLK_GATE_EN             BIT(2)
#define UPD_SPI_CLK_GATE_EN             BIT(3)
#define UPD_OTP_CTRL_CLK_GATE_EN        BIT(4)
#define UPD_ANA_TEST_GATE_EN            BIT(5)
#define UPD_PPC_CLK_GATE_EN             BIT(6)
#define UPD_PIO_CLK_GATE_EN             BIT(7)

/*Defines for UPD_CLK_GATE_HIGH register*/
#define UPD_OCS_CLK_GATE_EN             BIT(0)
#define UPD_PD_MAC_CLK_GATE_EN          BIT(1)
#define UPD_WDT_CLK_GATE_EN             BIT(2)
#define UPD_HPD_CLK_GATE_EN             BIT(3)
#define UPD_CABLE_PLUG_CLK_GATE_EN      BIT(4)

/*Vendor ID & Product ID information*/
#define UPD_VID_LSB                     0x24
#define UPD_VID_MSB                     0x04  
                                                  
#define UPD_PID_LSB                     0x50   
#define UPD_PID_MSB                     0x03
                                                  
#define UPD_SPI_TEST_VAL                0x02   
                                                  
/*****************************************************************************************************/

/* UPD idle state*/
#define UPD_STATE_ACTIVE                    0x01
#define UPD_STATE_IDLE                      0x02
#define UPD_STATE_STARTED_IDLE_TIMER        0x03
                                                  
#define UPD_48MHZ_OSC_ENABLE    BIT(1)
#define UPD_RING_OSC_ENABLE     BIT(2)
#define UPD_SYS_CLK_ENABLE      BIT(6)

/*Status of ports whether disabled or enabled*/
#define UPD_PORT_DISABLED        0x00
#define UPD_PORT_ENABLED         0x01

/* Default UPD VBUS Threshold value */
#define UPD_VBUS_THRS_DEFAULT    222 

/*Defines used in UPD_InitHPD() API*/
#define HPD_IRQ_MIN_TIME_350US           5
#define HPD_IRQ_MIN_TIME_2_1MS           40
#define UPD_HPD_HIGH_DET_TIME_100_1MS    2000
#define UPD_HPD_LOW_DET_TIME_2_1MS       40

#define UPD_IRQ_HPD_EN                   BIT(0)
#define UPD_HPD_LOW_EN                   BIT(1)
#define UPD_HPD_HIGH_EN                  BIT(2)
#define UPD_QUEUE_NOT_EMPTY_EN           BIT(3)

#define UPD_CFG_PIO_ENABLE               BIT(0)
#define UPD_CFG_PIO_RISING_EDGE          BIT(4)

#define UPD_HPD_ENABLE                   BIT(0)
#define UPD_HPD_CFG                      BIT(1)

/*Defines for gu16HPDStsISR variable*/
#define UPD_HPD_INTERRUPT_OCCURRED       BIT(8)

#define UPD_HPD_EVENT_MASK               (BIT(1)|BIT(0))
#define UPD_HPD_EVENT_SIZE               2
#define UPD_HPD_WRITE_CLR                0x55
#define UPD_HPD_QUEUE_SIZE               4

typedef enum
{
    eUPDPIO_FAULT_IN = 0,
    eUPDPIO_EN_FRS
} eUPD_INPUT_PIO;

// *****************************************************************************
// *****************************************************************************
// Section: Interface Routines
// *****************************************************************************
// *****************************************************************************
/****************************************************************************************************
    Function:
        void Hv_Typec_RegWriteByte (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 u8WriteData)

    Summary:
        Wrapper to do BYTE write to UPD register
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to write a BYTE to any given UPD register address
        
    Precondition:
        None.

    Parameters:
        u8PortNum        - Corresponding port number
        u16RegOffset    - UPD Register Address where given data to be written
        u8WriteData        - Byte data to be written to the location

    Return:
        None.

    Remarks:
        None.
 **************************************************************************************************/
void Hv_Typec_RegWriteByte (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 u8WriteData);

/*****************************************************************************************************
    Function:
        void Hv_Typec_RegWriteWord (UINT8 u8PortNum, UINT16 u16RegOffset, UINT32 u16WriteData)

    Summary:
        Wrapper to do WORD write to UPD register
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to write a WORD to any given UPD register address
        
    Precondition:
        None.

    Parameters:
        u8PortNum        -  Corresponding port number
        u16RegOffset    -  UPD Register Address where given data to be written
        u16WriteData    -  16-bit WORD data to be written to the location

    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void Hv_Typec_RegWriteWord (UINT8 u8PortNum, UINT16 u16RegOffset, UINT32 u16WriteData);

/*****************************************************************************************************
    Function:
        UINT8 Hv_Typec_RegReadByte (UINT8 u8PortNum, UINT16 u16RegOffset)

    Summary:
        Wrapper to read a BYTE from a UPD register.
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to read a BYTE from any given UPD register address. 
        It returns the read value.
        
    Precondition:
        None.

    Parameters:
        u8PortNum        -  Corresponding port number
        u16RegOffset    -  UPD Register Address from where data to be read

    Return:
        UINT8             - Read data is written.

    Remarks:
        None.
**************************************************************************************************/
UINT8 Hv_Typec_RegReadByte (UINT8 u8PortNum, UINT16 u16RegOffset);

/*****************************************************************************************************
    Function:
        UINT16 Hv_Typec_RegReadWord (UINT8 u8PortNum, UINT16 u16RegOffset)

    Summary:
        Wrapper to read a WORD from a UPD register through SPI
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to read a WORD from any given UPD register address. 
        It returns the read value.
        
    Precondition:
        None.

    Parameters:
        u8PortNum        -  Corresponding port number
        u16RegOffset    -  UPD Register Address from where data to be read

    Return:
        UINT16             - Read data is written.

    Remarks:
        None.
**************************************************************************************************/
UINT16 Hv_Typec_RegReadWord (UINT8 u8PortNum, UINT16 u16RegOffset);

/*****************************************************************************************************
    Function:
        void Hv_Typec_RegisterWrite (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8WriteData, UINT8 u8WriteDataLen)

    Summary:
        To write a buffer to a UPD register address
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to write a buffer to UPD Register Address.
        
    Precondition:
        None.

    Parameters:
        u8PortNum        - Corresponding port number
        u16RegOffset    - UPD Register Address where data buffer to be written
        pu8WriteData    - Pointer to buffer to be written
        u8WriteDataLen    - size of buffer to be written

    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void Hv_Typec_RegisterWrite (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8WriteData, UINT8 u8WriteDataLen);

/*****************************************************************************************************
    Function:
        void Hv_Typec_RegisterRead (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8ReadData, UINT16 u8Readlen)

    Summary:
        To read a buffer from a UPD register address
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to read buffer of passed data size from UPD Register Address.
        
    Precondition:
        None.

    Parameters:
        u8PortNum        -  Corresponding port number
        u16RegOffset    -  UPD Register Address from where buffer to be read
        *pu8ReadData    -  Pointer to data buffer where read data is to be updated
        u8Readlen       -  size of data to read from the register

    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void Hv_Typec_RegisterRead (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8ReadData, UINT8 u8Readlen);

/*****************************************************************************************************
    Function:
        void Hv_Typec_RegByteSetBit (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 u8BitMsk);

    Summary:
        To SET a bit in a Byte accessed UPD Register.
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to SET a specified bit in a UPD Register through Byte access.
        
    Precondition:
        It is confined to byte access of the UPD Register.

    Parameters:
        u8PortNum        -  Corresponding port number
        u16RegOffset    -  UPD Register Address
        u8BitMsk        -  Mask for the bit to be SET

    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void Hv_Typec_RegByteSetBit (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 u8BitMsk);

/*****************************************************************************************************
    Function:
        void Hv_Typec_RegByteClearBit (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 u8BitMsk)

    Summary:
        To CLEAR a bit in a Byte accessed UPD Register.
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to CLEAR a specified bit in a UPD Register through Byte access.
        
    Precondition:
        It is confined to byte access of the UPD Register.

    Parameters:
        u8PortNum        -  Corresponding port number
        u16RegOffset    -  UPD Register Address
        u8BitMsk        -  Mask for the bit to be CLEARed

    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void Hv_Typec_RegByteClearBit (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 u8BitMsk);

/*****************************************************************************************************
    Function:
        void Hv_Typec_RegisterWriteISR (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8WriteData, UINT8 u8WriteDataLen);

    Summary:
        To write a buffer in ISR context to a UPD register address.
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is used in ISR to write a buffer to UPD Register Address without enabling or 
        disabling the interrupts.
        
    Precondition:
        It should be used only in ISR.

    Parameters:
        u8PortNum        - Corresponding port number
        u16RegOffset    - UPD Register Address where data buffer to be written
        pu8WriteData    - Pointer to buffer to be written
        u8WriteDataLen  - size of buffer to be written

    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void Hv_Typec_RegisterWriteISR (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8WriteData, UINT8 u8WriteDataLen);

/*****************************************************************************************************
    Function:
        void Hv_Typec_RegisterReadISR (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8ReadData, UINT8 u8Readlen)

    Summary:
        To read a buffer in ISR context from a UPD register address.
    
    Devices Supported:
        HiView Typec Controller

    Description:
        This API is used in ISR to read a buffer from UPD register address without enabling or 
        disabling the interrupts.
        
    Precondition:
        It should be used only in ISR.

    Parameters:
        u8PortNum        -  Corresponding port number
        u16RegOffset    -  UPD Register Address from where buffer to be read
        *pu8ReadData    -  Pointer to data buffer where read data is to be updated
        u8Readlen       -  size of data to read from the register

    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void Hv_Typec_RegisterReadISR (UINT8 u8PortNum, UINT16 u16RegOffset, UINT8 *pu8ReadData, UINT8 u8Readlen);

/**************************************************************************************************
    Function:
        void UPD_SetIdleCB (UINT8 u8PortNum, UINT8 u8DummyVariable)

    Summary:
        This API is given as the timer call back API when starting the Idle Timer 

    Devices Supported:
        HiView Typec Controller

    Description:
        This API is given as the timer call back API when starting the Idle Timer
        started to indicate the UPD350s Idle state. 

    Conditions:
        confined to INCLUDE_POWER_MANAGEMENT_CTRL define.

    Input:
        u8PortNum - Port number of the device.
                    Value passed will be less than CONFIG_PD_PORT_COUNT.
                    
        u8DummyVariable - Dummy state variable
        
    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void UPD_SetIdleCB (UINT8 u8PortNum, UINT8 u8DummyVariable);

/**************************************************************************************************
    Function:
        void PD_StartIdleTimer (UINT8 u8PortNum)

    Summary:
        This API starts the port Idle timer 

    Devices Supported:
        HiView Typec Controller

    Description:
        This API starts the  port Idle timer with the value specified in
        UPD_IDLE_TIMEOUT_MS

    Conditions:
        confined to INCLUDE_POWER_MANAGEMENT_CTRL define.

    Input:
        u8PortNum - Port number of the device.
                    Value passed will be less than CONFIG_PD_PORT_COUNT.
        
    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void PD_StartIdleTimer (UINT8 u8PortNum);

/**************************************************************************************************
    Function:
        UINT8 UPD_ReturnUPDsActiveSts ()

    Summary:
        This API is to check the active or idle status of UPD350s 

    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to check the Active or Idle status of UPD350s
    Conditions:
        confined to INCLUDE_POWER_MANAGEMENT_CTRL define.

    Input:
        None
        
    Return:
        None.

    Remarks:
        HV_TRUE - UPD350s are in Active State
        HV_FALSE - All the UPD350s are in Idle State
**************************************************************************************************/
UINT8 UPD_ReturnUPDsActiveSts ();

/**************************************************************************************************
    Function:
        UPD_PwrManagementCtrl (UINT8 u8PortNum)

    Summary:
        This API is to initiate the Power Management control.

    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to initiate the Power Management control and indicate the
        Application layer to put MCU in Idle state.

    Conditions:
        confined to INCLUDE_POWER_MANAGEMENT_CTRL define.

    Input:
        u8PortNum - Port number of the device.
                    Value passed will be less than CONFIG_PD_PORT_COUNT.
        
    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void UPD_PwrManagementCtrl (UINT8 u8PortNum);

/**************************************************************************************************
    Function:
        UPD_InitPwrManagement (UINT8 u8PortNum)

    Summary:
        This API is to initialize the Power Management control.

    Devices Supported:
        HiView Typec Controller

    Description:
        This API is to initialize the Power Management control variables and starts
        the Idle timer during initialization.

    Conditions:
        confined to INCLUDE_POWER_MANAGEMENT_CTRL define.

    Input:
        u8PortNum - Port number of the device.
                    Value passed will be less than CONFIG_PD_PORT_COUNT.
        
    Return:
        None.

    Remarks:
        None.
**************************************************************************************************/
void UPD_InitPwrManagement (UINT8 u8PortNum);

#endif /*_UPD_HW_H_*/

