#ifndef _HV_PAGE_HT7315_SH12_TOP_00_H_
#define _HV_PAGE_HT7315_SH12_TOP_00_H_

#ifndef HV_SH12_TOP_00_BASE_ADDRESS
    #define HV_SH12_TOP_00_BASE_ADDRESS                                         0x11044200
#endif


#define RX_SH12_TOP_00_00                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x00)

#define RX_SH12_TOP_00_00_struct                                         rs_rx_sh12_top_00_00

typedef struct _rs_rx_sh12_top_00_00  rs_rx_sh12_top_00_00;
struct _rs_rx_sh12_top_00_00 {
    unsigned int reg_00_mute_htotal                         :15;
    unsigned int reg_00_mute_vtotal                         :15;
    unsigned int reg_00_sh12_clk_en                         : 1;
    unsigned int reserved                                   : 1;
};
#define rx_sh12_top_00_00(val) ((rs_rx_sh12_top_00_00*)&(val))



#define RX_SH12_TOP_00_04                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x04)

#define RX_SH12_TOP_00_04_struct                                         rs_rx_sh12_top_00_04

typedef struct _rs_rx_sh12_top_00_04  rs_rx_sh12_top_00_04;
struct _rs_rx_sh12_top_00_04 {
    unsigned int reg_00_mute_hs_bporch                      : 8;
    unsigned int reg_00_mute_hact                           :14;
    unsigned int reserved                                   :10;
};
#define rx_sh12_top_00_04(val) ((rs_rx_sh12_top_00_04*)&(val))



#define RX_SH12_TOP_00_08                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x08)

#define RX_SH12_TOP_00_08_struct                                         rs_rx_sh12_top_00_08

typedef struct _rs_rx_sh12_top_00_08  rs_rx_sh12_top_00_08;
struct _rs_rx_sh12_top_00_08 {
    unsigned int reg_00_mute_vact                           :14;
    unsigned int reg_00_mute_vs_bporch                      : 8;
    unsigned int reg_00_mute_hs_width                       : 4;
    unsigned int reg_00_mute_vs_width                       : 4;
    unsigned int reserved                                   : 2;
};
#define rx_sh12_top_00_08(val) ((rs_rx_sh12_top_00_08*)&(val))



#define RX_SH12_TOP_00_0C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x0C)

#define RX_SH12_TOP_00_0C_struct                                         rs_rx_sh12_top_00_0c

typedef struct _rs_rx_sh12_top_00_0c  rs_rx_sh12_top_00_0c;
struct _rs_rx_sh12_top_00_0c {
    unsigned int reg_00_mute_hact_min                       :14;
    unsigned int reg_00_mute_hact_max                       :14;
    unsigned int reserved                                   : 4;
};
#define rx_sh12_top_00_0c(val) ((rs_rx_sh12_top_00_0c*)&(val))



#define RX_SH12_TOP_00_10                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x10)

#define RX_SH12_TOP_00_10_struct                                         rs_rx_sh12_top_00_10

typedef struct _rs_rx_sh12_top_00_10  rs_rx_sh12_top_00_10;
struct _rs_rx_sh12_top_00_10 {
    unsigned int reg_00_mute_vact_min                       :14;
    unsigned int reg_00_mute_vact_max                       :14;
    unsigned int reserved                                   : 4;
};
#define rx_sh12_top_00_10(val) ((rs_rx_sh12_top_00_10*)&(val))



#define RX_SH12_TOP_00_14                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x14)

#define RX_SH12_TOP_00_14_struct                                         rs_rx_sh12_top_00_14

typedef struct _rs_rx_sh12_top_00_14  rs_rx_sh12_top_00_14;
struct _rs_rx_sh12_top_00_14 {
    unsigned int reg_00_mute_vblank_max                     : 8;
    unsigned int reg_00_mute_frm_trig_pos                   :18;
    unsigned int reg_00_mute_freerun_keep_time              : 6;
};
#define rx_sh12_top_00_14(val) ((rs_rx_sh12_top_00_14*)&(val))



#define RX_SH12_TOP_00_18                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x18)

#define RX_SH12_TOP_00_18_struct                                         rs_rx_sh12_top_00_18

typedef struct _rs_rx_sh12_top_00_18  rs_rx_sh12_top_00_18;
struct _rs_rx_sh12_top_00_18 {
    unsigned int reg_00_mute_force_stable                   : 1;
    unsigned int reg_00_mute_rx_lockn_det_enable            : 1;
    unsigned int reg_00_mute_rx_de_det_enable               : 1;
    unsigned int reg_00_mute_hs_pos                         :10;
    unsigned int reg_00_mute_vs_pos                         :10;
    unsigned int reg_00_mute_dummy_de_enable                : 1;
    unsigned int reg_00_mute_dummy_de_num                   : 8;
};
#define rx_sh12_top_00_18(val) ((rs_rx_sh12_top_00_18*)&(val))



#define RX_SH12_TOP_00_1C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x1C)

#define RX_SH12_TOP_00_1C_struct                                         rs_rx_sh12_top_00_1c

typedef struct _rs_rx_sh12_top_00_1c  rs_rx_sh12_top_00_1c;
struct _rs_rx_sh12_top_00_1c {
    unsigned int reg_00_mute_det_enable                     : 1;
    unsigned int reg_00_mute_hmin_det_enable                : 1;
    unsigned int reg_00_mute_hmax_det_enable                : 1;
    unsigned int reg_00_mute_vmin_det_enable                : 1;
    unsigned int reg_00_mute_vmax_det_enable                : 1;
    unsigned int reg_00_mute_httl_max_det_enable            : 1;
    unsigned int reg_00_mute_vblk_max_det_enable            : 1;
    unsigned int reg_00_mute_force_freerun                  : 1;
    unsigned int reg_00_mute_state_mode                     : 1;
    unsigned int reg_00_mute_de_ln2_dly                     : 2;
    unsigned int reg_00_mute_norm_post_delay                : 6;
    unsigned int reg_00_mute_freerun2norm_threshold         : 4;
    unsigned int reg_00_mute_clk_det_enable                 : 1;
    unsigned int reg_00_mute_lr_slf_gen                     : 1;
    unsigned int reg_00_mute_test_en                        : 1;
    unsigned int reg_00_mute_lr_slf_gen_mode                : 1;
    unsigned int reg_00_mute_mute_oe_mode                   : 1;
    unsigned int reg_00_inclk_locked_th                     : 5;
    unsigned int reg_00_sh12_prog_src_stable_en             : 1;
};
#define rx_sh12_top_00_1c(val) ((rs_rx_sh12_top_00_1c*)&(val))



#define RX_SH12_TOP_00_20                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x20)

#define RX_SH12_TOP_00_20_struct                                         rs_rx_sh12_top_00_20

typedef struct _rs_rx_sh12_top_00_20  rs_rx_sh12_top_00_20;
struct _rs_rx_sh12_top_00_20 {
    unsigned int reg_00_inclk_freq_low_th                   :12;
    unsigned int reg_00_inclk_freq_high_th                  :12;
    unsigned int reg_00_aging_ctrl_sel                      : 1;
    unsigned int reg_00_aging_ctrl_freerun_en               : 1;
    unsigned int reserved                                   : 3;
    unsigned int reg_00_inclk_unlocked_th                   : 3;
};
#define rx_sh12_top_00_20(val) ((rs_rx_sh12_top_00_20*)&(val))



#define RX_SH12_TOP_00_24                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x24)

#define RX_SH12_TOP_00_24_struct                                         rs_rx_sh12_top_00_24

typedef struct _rs_rx_sh12_top_00_24  rs_rx_sh12_top_00_24;
struct _rs_rx_sh12_top_00_24 {
    unsigned int reg_00_mute_htotal_max                     :15;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_rxclk_stable_sel                    : 1;
    unsigned int reg_00_inclk_no_ck_option                  : 8;
    unsigned int reg_00_mute_norm2freerun_threshold         : 4;
    unsigned int reg_00_mute_bypass_state_for_clkabn        : 1;
    unsigned int reg_00_mute_state_w4_enable                : 1;
    unsigned int reg_00_freerun_int_sel                     : 1;
};
#define rx_sh12_top_00_24(val) ((rs_rx_sh12_top_00_24*)&(val))



#define RX_SH12_TOP_00_28                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x28)

#define RX_SH12_TOP_00_28_struct                                         rs_rx_sh12_top_00_28

typedef struct _rs_rx_sh12_top_00_28  rs_rx_sh12_top_00_28;
struct _rs_rx_sh12_top_00_28 {
    unsigned int reg_00_mute_antiglitch_th                  : 6;
    unsigned int reg_00_mute_vttl_min_det_enable            : 1;
    unsigned int reg_00_mute_port_num_sel                   : 1;
    unsigned int reg_00_mute_de_normal_option               : 4;
    unsigned int reg_00_mute_no_de_det_enable               : 1;
    unsigned int reg_00_mute_vs_freq_det_enable             : 1;
    unsigned int reg_00_mute_datapath_sel                   : 2;
    unsigned int reg_00_mute_norm_hs_fix_backporch          : 1;
    unsigned int reg_00_mute_norm_vs_fix_backporch          : 1;
    unsigned int reg_00_freerun_v_segment_cycle             :14;
};
#define rx_sh12_top_00_28(val) ((rs_rx_sh12_top_00_28*)&(val))



#define RX_SH12_TOP_00_2C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x2C)

#define RX_SH12_TOP_00_2C_struct                                         rs_rx_sh12_top_00_2c

typedef struct _rs_rx_sh12_top_00_2c  rs_rx_sh12_top_00_2c;
struct _rs_rx_sh12_top_00_2c {
    unsigned int reg_00_mute_norm_delay                     :13;
    unsigned int reg_00_mute_data_compensation              : 3;
    unsigned int reg_00_mute_hact_out                       :14;
    unsigned int reg_00_mute_sram_addr_sel                  : 2;
};
#define rx_sh12_top_00_2c(val) ((rs_rx_sh12_top_00_2c*)&(val))



#define RX_SH12_TOP_00_30                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x30)

#define RX_SH12_TOP_00_30_struct                                         rs_rx_sh12_top_00_30

typedef struct _rs_rx_sh12_top_00_30  rs_rx_sh12_top_00_30;
struct _rs_rx_sh12_top_00_30 {
    unsigned int reg_00_mute_comp_w2_en                     : 1;
    unsigned int reg_00_mute_htotal_out_mode                : 1;
    unsigned int reg_00_vs_measure_en                       : 1;
    unsigned int reg_00_vs_measure_sel                      : 3;
    unsigned int reg_00_mute_norm_clr_delay                 :12;
    unsigned int reg_00_mute_type_fsm_en                    :14;
};
#define rx_sh12_top_00_30(val) ((rs_rx_sh12_top_00_30*)&(val))



#define RX_SH12_TOP_00_34                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x34)

#define RX_SH12_TOP_00_34_struct                                         rs_rx_sh12_top_00_34

typedef struct _rs_rx_sh12_top_00_34  rs_rx_sh12_top_00_34;
struct _rs_rx_sh12_top_00_34 {
    unsigned int reg_00_sh12_spare                          :32;
};
#define rx_sh12_top_00_34(val) ((rs_rx_sh12_top_00_34*)&(val))



#define RX_SH12_TOP_00_38                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x38)

#define RX_SH12_TOP_00_38_struct                                         rs_rx_sh12_top_00_38

typedef struct _rs_rx_sh12_top_00_38  rs_rx_sh12_top_00_38;
struct _rs_rx_sh12_top_00_38 {
    unsigned int reg_00_freerun_v_segment_blank             :22;
    unsigned int reg_00_freerun_v_segment_enable            : 1;
    unsigned int reg_00_mute_norm_htotal_out_sel            : 2;
    unsigned int reg_00_mute_port_sel                       : 3;
    unsigned int reg_00_mute_deproc_option                  : 3;
    unsigned int reg_00_mute_bypass_wait1_permit            : 1;
};
#define rx_sh12_top_00_38(val) ((rs_rx_sh12_top_00_38*)&(val))



#define RX_SH12_TOP_00_3C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x3C)

#define RX_SH12_TOP_00_3C_struct                                         rs_rx_sh12_top_00_3c

typedef struct _rs_rx_sh12_top_00_3c  rs_rx_sh12_top_00_3c;
struct _rs_rx_sh12_top_00_3c {
    unsigned int reg_00_sh12_rx_crc_en                      : 1;
    unsigned int reg_00_sh12_rx_crc_mode                    : 6;
    unsigned int reg_00_sh12_mute_int                       : 1;
    unsigned int reg_00_sh12_rx_crc_fnum                    : 8;
    unsigned int reg_00_sh12_rx_crc_lnum                    : 8;
    unsigned int reg_00_sh12_mute_dbg_sel                   : 4;
    unsigned int reserved                                   : 4;
};
#define rx_sh12_top_00_3c(val) ((rs_rx_sh12_top_00_3c*)&(val))



#define RX_SH12_TOP_00_40                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x40)

#define RX_SH12_TOP_00_40_struct                                         rs_rx_sh12_top_00_40

typedef struct _rs_rx_sh12_top_00_40  rs_rx_sh12_top_00_40;
struct _rs_rx_sh12_top_00_40 {
    unsigned int reg_00_mute_no_de_th                       :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_40(val) ((rs_rx_sh12_top_00_40*)&(val))



#define RX_SH12_TOP_00_44                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x44)

#define RX_SH12_TOP_00_44_struct                                         rs_rx_sh12_top_00_44

typedef struct _rs_rx_sh12_top_00_44  rs_rx_sh12_top_00_44;
struct _rs_rx_sh12_top_00_44 {
    unsigned int reg_00_multichip_lockn_sel                 : 2;
    unsigned int reg_00_multichip_freenrun_sel              : 2;
    unsigned int reg_00_multichip_mute_action_sel           : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_00_multichip_freenrun_o_sel            : 1;
    unsigned int reg_00_mute_multichip_slave_on             : 1;
    unsigned int reg_00_mute_multichip_delay                : 4;
    unsigned int reserved_1                                 : 3;
    unsigned int reg_00_mute_multichip_data_compensation    : 1;
    unsigned int reg_00_mute_vs_freq_sw_en                  : 1;
    unsigned int reg_00_mute_vs_freq_sw_set                 : 1;
    unsigned int reg_00_mute_vact_out                       :14;
};
#define rx_sh12_top_00_44(val) ((rs_rx_sh12_top_00_44*)&(val))



#define RX_SH12_TOP_00_48                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x48)

#define RX_SH12_TOP_00_48_struct                                         rs_rx_sh12_top_00_48

typedef struct _rs_rx_sh12_top_00_48  rs_rx_sh12_top_00_48;
struct _rs_rx_sh12_top_00_48 {
    unsigned int reg_00_mute_vs_freq_low_th                 :24;
    unsigned int reg_00_mute_vs_freq_low_time               : 4;
    unsigned int reg_00_mute_vs_freq_high_time              : 4;
};
#define rx_sh12_top_00_48(val) ((rs_rx_sh12_top_00_48*)&(val))



#define RX_SH12_TOP_00_4C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x4C)

#define RX_SH12_TOP_00_4C_struct                                         rs_rx_sh12_top_00_4c

typedef struct _rs_rx_sh12_top_00_4c  rs_rx_sh12_top_00_4c;
struct _rs_rx_sh12_top_00_4c {
    unsigned int reg_00_mute_vs_freq_high_th                :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_4c(val) ((rs_rx_sh12_top_00_4c*)&(val))



#define RX_SH12_TOP_00_50                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x50)

#define RX_SH12_TOP_00_50_struct                                         rs_rx_sh12_top_00_50

typedef struct _rs_rx_sh12_top_00_50  rs_rx_sh12_top_00_50;
struct _rs_rx_sh12_top_00_50 {
    unsigned int reg_00_mute_vs_freq_diff_th                :24;
    unsigned int reg_00_mute_vs_freq_diff_time              : 4;
    unsigned int reg_00_mute_vs_freq_func_en                : 4;
};
#define rx_sh12_top_00_50(val) ((rs_rx_sh12_top_00_50*)&(val))



#define RX_SH12_TOP_00_54                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x54)

#define RX_SH12_TOP_00_54_struct                                         rs_rx_sh12_top_00_54

typedef struct _rs_rx_sh12_top_00_54  rs_rx_sh12_top_00_54;
struct _rs_rx_sh12_top_00_54 {
    unsigned int reg_00_mute_vs_freq_diff_th1               :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_54(val) ((rs_rx_sh12_top_00_54*)&(val))



#define RX_SH12_TOP_00_58                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x58)

#define RX_SH12_TOP_00_58_struct                                         rs_rx_sh12_top_00_58

typedef struct _rs_rx_sh12_top_00_58  rs_rx_sh12_top_00_58;
struct _rs_rx_sh12_top_00_58 {
    unsigned int reg_00_mute_abh_min_int_cnt_th             : 8;
    unsigned int reg_00_mute_abh_max_int_cnt_th             : 8;
    unsigned int reg_00_mute_htotal_max_step                :10;
    unsigned int reg_00_mute_clk_src_freerun_mode           : 1;
    unsigned int reg_00_random_tgen_en                      : 1;
    unsigned int reg_00_mute_httl_min_comp_en               : 1;
    unsigned int reg_00_mute_httl_max_comp_en               : 1;
    unsigned int reserved                                   : 2;
};
#define rx_sh12_top_00_58(val) ((rs_rx_sh12_top_00_58*)&(val))



#define RX_SH12_TOP_00_5C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x5C)

#define RX_SH12_TOP_00_5C_struct                                         rs_rx_sh12_top_00_5c

typedef struct _rs_rx_sh12_top_00_5c  rs_rx_sh12_top_00_5c;
struct _rs_rx_sh12_top_00_5c {
    unsigned int reg_00_mute_htotal_min                     :15;
    unsigned int reg_00_mute_vblank_min                     :15;
    unsigned int reg_00_mute_httl_min_det_enable            : 1;
    unsigned int reg_00_mute_vblk_min_det_enable            : 1;
};
#define rx_sh12_top_00_5c(val) ((rs_rx_sh12_top_00_5c*)&(val))



#define RX_SH12_TOP_00_60                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x60)

#define RX_SH12_TOP_00_60_struct                                         rs_rx_sh12_top_00_60

typedef struct _rs_rx_sh12_top_00_60  rs_rx_sh12_top_00_60;
struct _rs_rx_sh12_top_00_60 {
    unsigned int reg_00_rx_bw_meter_act_en                  : 1;
    unsigned int reg_00_rx_bw_meter_th                      :16;
    unsigned int reg_00_freerun_v_segment_cycle_1st         :14;
    unsigned int reserved                                   : 1;
};
#define rx_sh12_top_00_60(val) ((rs_rx_sh12_top_00_60*)&(val))



#define RX_SH12_TOP_00_64                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x64)

#define RX_SH12_TOP_00_64_struct                                         rs_rx_sh12_top_00_64

typedef struct _rs_rx_sh12_top_00_64  rs_rx_sh12_top_00_64;
struct _rs_rx_sh12_top_00_64 {
    unsigned int reg_00_frame_rate_level_1_threshold        :24;
    unsigned int reg_00_rx_bw_meter_delta                   : 4;
    unsigned int reg_00_mute_db_en                          : 1;
    unsigned int reg_00_mute_db_seamless_en                 : 1;
    unsigned int reg_00_seamless_apply_in                   : 1;
    unsigned int reserved                                   : 1;
};
#define rx_sh12_top_00_64(val) ((rs_rx_sh12_top_00_64*)&(val))



#define RX_SH12_TOP_00_68                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x68)

#define RX_SH12_TOP_00_68_struct                                         rs_rx_sh12_top_00_68

typedef struct _rs_rx_sh12_top_00_68  rs_rx_sh12_top_00_68;
struct _rs_rx_sh12_top_00_68 {
    unsigned int reg_00_frame_rate_level_1_tolerance        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_68(val) ((rs_rx_sh12_top_00_68*)&(val))



#define RX_SH12_TOP_00_6C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x6C)

#define RX_SH12_TOP_00_6C_struct                                         rs_rx_sh12_top_00_6c

typedef struct _rs_rx_sh12_top_00_6c  rs_rx_sh12_top_00_6c;
struct _rs_rx_sh12_top_00_6c {
    unsigned int reg_00_frame_rate_level_2_threshold        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_6c(val) ((rs_rx_sh12_top_00_6c*)&(val))



#define RX_SH12_TOP_00_70                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x70)

#define RX_SH12_TOP_00_70_struct                                         rs_rx_sh12_top_00_70

typedef struct _rs_rx_sh12_top_00_70  rs_rx_sh12_top_00_70;
struct _rs_rx_sh12_top_00_70 {
    unsigned int reg_00_frame_rate_level_2_tolerance        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_70(val) ((rs_rx_sh12_top_00_70*)&(val))



#define RX_SH12_TOP_00_74                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x74)

#define RX_SH12_TOP_00_74_struct                                         rs_rx_sh12_top_00_74

typedef struct _rs_rx_sh12_top_00_74  rs_rx_sh12_top_00_74;
struct _rs_rx_sh12_top_00_74 {
    unsigned int reg_00_frame_rate_level_3_threshold        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_74(val) ((rs_rx_sh12_top_00_74*)&(val))



#define RX_SH12_TOP_00_78                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x78)

#define RX_SH12_TOP_00_78_struct                                         rs_rx_sh12_top_00_78

typedef struct _rs_rx_sh12_top_00_78  rs_rx_sh12_top_00_78;
struct _rs_rx_sh12_top_00_78 {
    unsigned int reg_00_frame_rate_level_3_tolerance        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_78(val) ((rs_rx_sh12_top_00_78*)&(val))



#define RX_SH12_TOP_00_7C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x7C)

#define RX_SH12_TOP_00_7C_struct                                         rs_rx_sh12_top_00_7c

typedef struct _rs_rx_sh12_top_00_7c  rs_rx_sh12_top_00_7c;
struct _rs_rx_sh12_top_00_7c {
    unsigned int reg_00_frame_rate_level_4_threshold        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_7c(val) ((rs_rx_sh12_top_00_7c*)&(val))



#define RX_SH12_TOP_00_80                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x80)

#define RX_SH12_TOP_00_80_struct                                         rs_rx_sh12_top_00_80

typedef struct _rs_rx_sh12_top_00_80  rs_rx_sh12_top_00_80;
struct _rs_rx_sh12_top_00_80 {
    unsigned int reg_00_frame_rate_level_4_tolerance        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_80(val) ((rs_rx_sh12_top_00_80*)&(val))



#define RX_SH12_TOP_00_84                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x84)

#define RX_SH12_TOP_00_84_struct                                         rs_rx_sh12_top_00_84

typedef struct _rs_rx_sh12_top_00_84  rs_rx_sh12_top_00_84;
struct _rs_rx_sh12_top_00_84 {
    unsigned int reg_00_frame_rate_level_5_threshold        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_84(val) ((rs_rx_sh12_top_00_84*)&(val))



#define RX_SH12_TOP_00_88                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x88)

#define RX_SH12_TOP_00_88_struct                                         rs_rx_sh12_top_00_88

typedef struct _rs_rx_sh12_top_00_88  rs_rx_sh12_top_00_88;
struct _rs_rx_sh12_top_00_88 {
    unsigned int reg_00_frame_rate_level_5_tolerance        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_88(val) ((rs_rx_sh12_top_00_88*)&(val))



#define RX_SH12_TOP_00_8C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x8C)

#define RX_SH12_TOP_00_8C_struct                                         rs_rx_sh12_top_00_8c

typedef struct _rs_rx_sh12_top_00_8c  rs_rx_sh12_top_00_8c;
struct _rs_rx_sh12_top_00_8c {
    unsigned int reg_00_frame_rate_level_6_threshold        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_8c(val) ((rs_rx_sh12_top_00_8c*)&(val))



#define RX_SH12_TOP_00_90                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x90)

#define RX_SH12_TOP_00_90_struct                                         rs_rx_sh12_top_00_90

typedef struct _rs_rx_sh12_top_00_90  rs_rx_sh12_top_00_90;
struct _rs_rx_sh12_top_00_90 {
    unsigned int reg_00_frame_rate_level_6_tolerance        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_90(val) ((rs_rx_sh12_top_00_90*)&(val))



#define RX_SH12_TOP_00_94                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x94)

#define RX_SH12_TOP_00_94_struct                                         rs_rx_sh12_top_00_94

typedef struct _rs_rx_sh12_top_00_94  rs_rx_sh12_top_00_94;
struct _rs_rx_sh12_top_00_94 {
    unsigned int reg_00_frame_rate_level_7_threshold        :24;
    unsigned int reserved                                   : 8;
};
#define rx_sh12_top_00_94(val) ((rs_rx_sh12_top_00_94*)&(val))



#define RX_SH12_TOP_00_98                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x98)

#define RX_SH12_TOP_00_98_struct                                         rs_rx_sh12_top_00_98

typedef struct _rs_rx_sh12_top_00_98  rs_rx_sh12_top_00_98;
struct _rs_rx_sh12_top_00_98 {
    unsigned int reg_00_frame_rate_level_7_tolerance        :24;
    unsigned int reg_00_frame_rate_level_stable_filter      : 3;
    unsigned int reserved                                   : 5;
};
#define rx_sh12_top_00_98(val) ((rs_rx_sh12_top_00_98*)&(val))



#define RX_SH12_TOP_00_9C                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0x9C)

#define RX_SH12_TOP_00_9C_struct                                         rs_rx_sh12_top_00_9c

typedef struct _rs_rx_sh12_top_00_9c  rs_rx_sh12_top_00_9c;
struct _rs_rx_sh12_top_00_9c {
    unsigned int reg_00_sh12_rx_crc_value0                  :32;
};
#define rx_sh12_top_00_9c(val) ((rs_rx_sh12_top_00_9c*)&(val))



#define RX_SH12_TOP_00_A0                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xA0)

#define RX_SH12_TOP_00_A0_struct                                         rs_rx_sh12_top_00_a0

typedef struct _rs_rx_sh12_top_00_a0  rs_rx_sh12_top_00_a0;
struct _rs_rx_sh12_top_00_a0 {
    unsigned int reg_00_sh12_rx_crc_value1                  :32;
};
#define rx_sh12_top_00_a0(val) ((rs_rx_sh12_top_00_a0*)&(val))



#define RX_SH12_TOP_00_A4                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xA4)

#define RX_SH12_TOP_00_A4_struct                                         rs_rx_sh12_top_00_a4

typedef struct _rs_rx_sh12_top_00_a4  rs_rx_sh12_top_00_a4;
struct _rs_rx_sh12_top_00_a4 {
    unsigned int reg_00_sh12_rx_crc_value2                  :32;
};
#define rx_sh12_top_00_a4(val) ((rs_rx_sh12_top_00_a4*)&(val))



#define RX_SH12_TOP_00_A8                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xA8)

#define RX_SH12_TOP_00_A8_struct                                         rs_rx_sh12_top_00_a8

typedef struct _rs_rx_sh12_top_00_a8  rs_rx_sh12_top_00_a8;
struct _rs_rx_sh12_top_00_a8 {
    unsigned int reg_00_sh12_rx_crc_value3                  :32;
};
#define rx_sh12_top_00_a8(val) ((rs_rx_sh12_top_00_a8*)&(val))



#define RX_SH12_TOP_00_AC                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xAC)

#define RX_SH12_TOP_00_AC_struct                                         rs_rx_sh12_top_00_ac

typedef struct _rs_rx_sh12_top_00_ac  rs_rx_sh12_top_00_ac;
struct _rs_rx_sh12_top_00_ac {
    unsigned int reg_00_sh12_mute_crc_value0                :32;
};
#define rx_sh12_top_00_ac(val) ((rs_rx_sh12_top_00_ac*)&(val))



#define RX_SH12_TOP_00_B0                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xB0)

#define RX_SH12_TOP_00_B0_struct                                         rs_rx_sh12_top_00_b0

typedef struct _rs_rx_sh12_top_00_b0  rs_rx_sh12_top_00_b0;
struct _rs_rx_sh12_top_00_b0 {
    unsigned int reg_00_sh12_mute_crc_value1                :32;
};
#define rx_sh12_top_00_b0(val) ((rs_rx_sh12_top_00_b0*)&(val))



#define RX_SH12_TOP_00_B4                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xB4)

#define RX_SH12_TOP_00_B4_struct                                         rs_rx_sh12_top_00_b4

typedef struct _rs_rx_sh12_top_00_b4  rs_rx_sh12_top_00_b4;
struct _rs_rx_sh12_top_00_b4 {
    unsigned int reg_00_sh12_mute_crc_value2                :32;
};
#define rx_sh12_top_00_b4(val) ((rs_rx_sh12_top_00_b4*)&(val))



#define RX_SH12_TOP_00_B8                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xB8)

#define RX_SH12_TOP_00_B8_struct                                         rs_rx_sh12_top_00_b8

typedef struct _rs_rx_sh12_top_00_b8  rs_rx_sh12_top_00_b8;
struct _rs_rx_sh12_top_00_b8 {
    unsigned int reg_00_sh12_mute_crc_value3                :32;
};
#define rx_sh12_top_00_b8(val) ((rs_rx_sh12_top_00_b8*)&(val))



#define RX_SH12_TOP_00_BC                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xBC)

#define RX_SH12_TOP_00_BC_struct                                         rs_rx_sh12_top_00_bc

typedef struct _rs_rx_sh12_top_00_bc  rs_rx_sh12_top_00_bc;
struct _rs_rx_sh12_top_00_bc {
    unsigned int regr_00_frame_rate_out_current             :24;
    unsigned int regr_00_frame_rate_level                   : 3;
    unsigned int regr_00_rx_inclk_status                    : 3;
    unsigned int regr_00_rx_clk_stable                      : 1;
    unsigned int reserved                                   : 1;
};
#define rx_sh12_top_00_bc(val) ((rs_rx_sh12_top_00_bc*)&(val))



#define RX_SH12_TOP_00_C0                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xC0)

#define RX_SH12_TOP_00_C0_struct                                         rs_rx_sh12_top_00_c0

typedef struct _rs_rx_sh12_top_00_c0  rs_rx_sh12_top_00_c0;
struct _rs_rx_sh12_top_00_c0 {
    unsigned int regr_00_sh12_rx_crc_data0                  :32;
};
#define rx_sh12_top_00_c0(val) ((rs_rx_sh12_top_00_c0*)&(val))



#define RX_SH12_TOP_00_C4                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xC4)

#define RX_SH12_TOP_00_C4_struct                                         rs_rx_sh12_top_00_c4

typedef struct _rs_rx_sh12_top_00_c4  rs_rx_sh12_top_00_c4;
struct _rs_rx_sh12_top_00_c4 {
    unsigned int regr_00_sh12_rx_crc_data1                  :32;
};
#define rx_sh12_top_00_c4(val) ((rs_rx_sh12_top_00_c4*)&(val))



#define RX_SH12_TOP_00_C8                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xC8)

#define RX_SH12_TOP_00_C8_struct                                         rs_rx_sh12_top_00_c8

typedef struct _rs_rx_sh12_top_00_c8  rs_rx_sh12_top_00_c8;
struct _rs_rx_sh12_top_00_c8 {
    unsigned int regr_00_sh12_rx_crc_data2                  :32;
};
#define rx_sh12_top_00_c8(val) ((rs_rx_sh12_top_00_c8*)&(val))



#define RX_SH12_TOP_00_CC                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xCC)

#define RX_SH12_TOP_00_CC_struct                                         rs_rx_sh12_top_00_cc

typedef struct _rs_rx_sh12_top_00_cc  rs_rx_sh12_top_00_cc;
struct _rs_rx_sh12_top_00_cc {
    unsigned int regr_00_sh12_rx_crc_data3                  :32;
};
#define rx_sh12_top_00_cc(val) ((rs_rx_sh12_top_00_cc*)&(val))



#define RX_SH12_TOP_00_D0                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xD0)

#define RX_SH12_TOP_00_D0_struct                                         rs_rx_sh12_top_00_d0

typedef struct _rs_rx_sh12_top_00_d0  rs_rx_sh12_top_00_d0;
struct _rs_rx_sh12_top_00_d0 {
    unsigned int regr_00_sh12_mute_crc_data0                :32;
};
#define rx_sh12_top_00_d0(val) ((rs_rx_sh12_top_00_d0*)&(val))



#define RX_SH12_TOP_00_D4                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xD4)

#define RX_SH12_TOP_00_D4_struct                                         rs_rx_sh12_top_00_d4

typedef struct _rs_rx_sh12_top_00_d4  rs_rx_sh12_top_00_d4;
struct _rs_rx_sh12_top_00_d4 {
    unsigned int regr_00_sh12_mute_crc_data1                :32;
};
#define rx_sh12_top_00_d4(val) ((rs_rx_sh12_top_00_d4*)&(val))



#define RX_SH12_TOP_00_D8                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xD8)

#define RX_SH12_TOP_00_D8_struct                                         rs_rx_sh12_top_00_d8

typedef struct _rs_rx_sh12_top_00_d8  rs_rx_sh12_top_00_d8;
struct _rs_rx_sh12_top_00_d8 {
    unsigned int regr_00_sh12_mute_crc_data2                :32;
};
#define rx_sh12_top_00_d8(val) ((rs_rx_sh12_top_00_d8*)&(val))



#define RX_SH12_TOP_00_DC                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xDC)

#define RX_SH12_TOP_00_DC_struct                                         rs_rx_sh12_top_00_dc

typedef struct _rs_rx_sh12_top_00_dc  rs_rx_sh12_top_00_dc;
struct _rs_rx_sh12_top_00_dc {
    unsigned int regr_00_sh12_mute_crc_data3                :32;
};
#define rx_sh12_top_00_dc(val) ((rs_rx_sh12_top_00_dc*)&(val))



#define RX_SH12_TOP_00_E0                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xE0)

#define RX_SH12_TOP_00_E0_struct                                         rs_rx_sh12_top_00_e0

typedef struct _rs_rx_sh12_top_00_e0  rs_rx_sh12_top_00_e0;
struct _rs_rx_sh12_top_00_e0 {
    unsigned int regr_00_mute_vs_pre_period                 :24;
    unsigned int regr_00_mute_ip_freerun_en_pre             : 1;
    unsigned int regr_00_mute_ip_mute_comp_en_pre           : 1;
    unsigned int regr_00_mute_ip_mute_comp_en               : 1;
    unsigned int regr_00_mute_ip_mute_oe_en                 : 1;
    unsigned int regr_00_mute_freerun_in_to_slave           : 1;
    unsigned int regr_00_mute_sync_lockn_to_master          : 1;
    unsigned int reserved                                   : 2;
};
#define rx_sh12_top_00_e0(val) ((rs_rx_sh12_top_00_e0*)&(val))



#define RX_SH12_TOP_00_E4                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xE4)

#define RX_SH12_TOP_00_E4_struct                                         rs_rx_sh12_top_00_e4

typedef struct _rs_rx_sh12_top_00_e4  rs_rx_sh12_top_00_e4;
struct _rs_rx_sh12_top_00_e4 {
    unsigned int regr_00_mute_vtotal                        :16;
    unsigned int regr_00_rx_bw_meter_det                    :16;
};
#define rx_sh12_top_00_e4(val) ((rs_rx_sh12_top_00_e4*)&(val))



#define RX_SH12_TOP_00_E8                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xE8)

#define RX_SH12_TOP_00_E8_struct                                         rs_rx_sh12_top_00_e8

typedef struct _rs_rx_sh12_top_00_e8  rs_rx_sh12_top_00_e8;
struct _rs_rx_sh12_top_00_e8 {
    unsigned int regr_00_mute_hact                          :14;
    unsigned int reserved                                   : 2;
    unsigned int regr_00_mute_vact                          :15;
    unsigned int reserved_1                                 : 1;
};
#define rx_sh12_top_00_e8(val) ((rs_rx_sh12_top_00_e8*)&(val))



#define RX_SH12_TOP_00_EC                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xEC)

#define RX_SH12_TOP_00_EC_struct                                         rs_rx_sh12_top_00_ec

typedef struct _rs_rx_sh12_top_00_ec  rs_rx_sh12_top_00_ec;
struct _rs_rx_sh12_top_00_ec {
    unsigned int regr_00_mute_vs_period                     :24;
    unsigned int regr_00_sh12_rx_crc_done                   : 1;
    unsigned int regr_00_sh12_rx_crc_fail                   : 1;
    unsigned int regr_00_sh12_mute_crc_done                 : 1;
    unsigned int regr_00_sh12_mute_crc_fail                 : 1;
    unsigned int reserved                                   : 4;
};
#define rx_sh12_top_00_ec(val) ((rs_rx_sh12_top_00_ec*)&(val))



#define RX_SH12_TOP_00_F0                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xF0)

#define RX_SH12_TOP_00_F0_struct                                         rs_rx_sh12_top_00_f0

typedef struct _rs_rx_sh12_top_00_f0  rs_rx_sh12_top_00_f0;
struct _rs_rx_sh12_top_00_f0 {
    unsigned int regr_00_mute_rx_htotal                     :15;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_mute_htotal                        :15;
    unsigned int reserved_1                                 : 1;
};
#define rx_sh12_top_00_f0(val) ((rs_rx_sh12_top_00_f0*)&(val))



#define RX_SH12_TOP_00_F4                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xF4)

#define RX_SH12_TOP_00_F4_struct                                         rs_rx_sh12_top_00_f4

typedef struct _rs_rx_sh12_top_00_f4  rs_rx_sh12_top_00_f4;
struct _rs_rx_sh12_top_00_f4 {
    unsigned int regr_00_mute_state                         :10;
    unsigned int regr_00_mute_src_stable                    : 1;
    unsigned int reserved                                   : 7;
    unsigned int regr_00_mute_result                        :14;
};
#define rx_sh12_top_00_f4(val) ((rs_rx_sh12_top_00_f4*)&(val))



#define RX_SH12_TOP_00_F8                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xF8)

#define RX_SH12_TOP_00_F8_struct                                         rs_rx_sh12_top_00_f8

typedef struct _rs_rx_sh12_top_00_f8  rs_rx_sh12_top_00_f8;
struct _rs_rx_sh12_top_00_f8 {
    unsigned int regr_00_bus_eni_freerun                    : 1;
    unsigned int regr_00_aging_slave_en                     : 1;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_mute_sram_waddr                    :12;
    unsigned int regr_00_mute_sram_raddr                    :12;
    unsigned int reserved_1                                 : 5;
};
#define rx_sh12_top_00_f8(val) ((rs_rx_sh12_top_00_f8*)&(val))



#define RX_SH12_TOP_00_FC                                                (HV_SH12_TOP_00_BASE_ADDRESS + 0xFC)

#define RX_SH12_TOP_00_FC_struct                                         rs_rx_sh12_top_00_fc

typedef struct _rs_rx_sh12_top_00_fc  rs_rx_sh12_top_00_fc;
struct _rs_rx_sh12_top_00_fc {
    unsigned int regr_00_mute_clk_abn                       : 1;
    unsigned int regr_00_mute_hde_min_abn                   : 1;
    unsigned int regr_00_mute_hde_max_abn                   : 1;
    unsigned int regr_00_mute_htotal_max_abn                : 1;
    unsigned int regr_00_mute_vde_min_abn                   : 1;
    unsigned int regr_00_mute_vde_max_abn                   : 1;
    unsigned int regr_00_mute_vblk_max_abn                  : 1;
    unsigned int regr_00_mute_no_de                         : 1;
    unsigned int regr_00_mute_en                            : 1;
    unsigned int regr_00_mute_vx1_lock_abn                  : 1;
    unsigned int regr_00_mute_vx1_de_abn                    : 1;
    unsigned int regr_00_mute_vs_freq_is_low                : 1;
    unsigned int regr_00_mute_vs_freq_is_high               : 1;
    unsigned int regr_00_mute_vttl_min_abn                  : 1;
    unsigned int regr_00_mute_vs_freq_diff_high             : 1;
    unsigned int regr_00_mute_vs_freq_diff_long             : 1;
    unsigned int regr_00_mute_htotal_min_abn                : 1;
    unsigned int regr_00_mute_vblk_min_abn                  : 1;
    unsigned int regr_00_dummy_0                            :14;
};
#define rx_sh12_top_00_fc(val) ((rs_rx_sh12_top_00_fc*)&(val))



#endif