#ifndef _HV_PAGE_HT7315_HDMI21_RX_PKDEC_00_H_
#define _HV_PAGE_HT7315_HDMI21_RX_PKDEC_00_H_

#ifndef HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS
    #define HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS                                         0x1104D100
#endif


#define RX_HDMI21_RX_PKDEC_00_00                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX_PKDEC_00_00_struct                                  rs_rx_hdmi21_rx_pkdec_00_00

typedef struct _rs_rx_hdmi21_rx_pkdec_00_00  rs_rx_hdmi21_rx_pkdec_00_00;
struct _rs_rx_hdmi21_rx_pkdec_00_00 {
    unsigned int reserved                                   : 8;
    unsigned int regr_00_drm_ph1                            : 8;
    unsigned int regr_00_drm_ph2                            : 8;
    unsigned int reserved_1                                 : 8;
};
#define rx_hdmi21_rx_pkdec_00_00(val) ((rs_rx_hdmi21_rx_pkdec_00_00*)&(val))



#define RX_HDMI21_RX_PKDEC_00_04                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX_PKDEC_00_04_struct                                  rs_rx_hdmi21_rx_pkdec_00_04

typedef struct _rs_rx_hdmi21_rx_pkdec_00_04  rs_rx_hdmi21_rx_pkdec_00_04;
struct _rs_rx_hdmi21_rx_pkdec_00_04 {
    unsigned int regr_00_drm_payload0                       : 8;
    unsigned int regr_00_drm_payload1                       : 8;
    unsigned int regr_00_drm_payload2                       : 8;
    unsigned int regr_00_drm_payload3                       : 8;
};
#define rx_hdmi21_rx_pkdec_00_04(val) ((rs_rx_hdmi21_rx_pkdec_00_04*)&(val))



#define RX_HDMI21_RX_PKDEC_00_08                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX_PKDEC_00_08_struct                                  rs_rx_hdmi21_rx_pkdec_00_08

typedef struct _rs_rx_hdmi21_rx_pkdec_00_08  rs_rx_hdmi21_rx_pkdec_00_08;
struct _rs_rx_hdmi21_rx_pkdec_00_08 {
    unsigned int regr_00_drm_payload4                       : 8;
    unsigned int regr_00_drm_payload5                       : 8;
    unsigned int regr_00_drm_payload6                       : 8;
    unsigned int regr_00_drm_payload7                       : 8;
};
#define rx_hdmi21_rx_pkdec_00_08(val) ((rs_rx_hdmi21_rx_pkdec_00_08*)&(val))



#define RX_HDMI21_RX_PKDEC_00_0C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x0C)

#define RX_HDMI21_RX_PKDEC_00_0C_struct                                  rs_rx_hdmi21_rx_pkdec_00_0c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_0c  rs_rx_hdmi21_rx_pkdec_00_0c;
struct _rs_rx_hdmi21_rx_pkdec_00_0c {
    unsigned int regr_00_drm_payload8                       : 8;
    unsigned int regr_00_drm_payload9                       : 8;
    unsigned int regr_00_drm_payload10                      : 8;
    unsigned int regr_00_drm_payload11                      : 8;
};
#define rx_hdmi21_rx_pkdec_00_0c(val) ((rs_rx_hdmi21_rx_pkdec_00_0c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_10                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x10)

#define RX_HDMI21_RX_PKDEC_00_10_struct                                  rs_rx_hdmi21_rx_pkdec_00_10

typedef struct _rs_rx_hdmi21_rx_pkdec_00_10  rs_rx_hdmi21_rx_pkdec_00_10;
struct _rs_rx_hdmi21_rx_pkdec_00_10 {
    unsigned int regr_00_drm_payload12                      : 8;
    unsigned int regr_00_drm_payload13                      : 8;
    unsigned int regr_00_drm_payload14                      : 8;
    unsigned int regr_00_drm_payload15                      : 8;
};
#define rx_hdmi21_rx_pkdec_00_10(val) ((rs_rx_hdmi21_rx_pkdec_00_10*)&(val))



#define RX_HDMI21_RX_PKDEC_00_14                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x14)

#define RX_HDMI21_RX_PKDEC_00_14_struct                                  rs_rx_hdmi21_rx_pkdec_00_14

typedef struct _rs_rx_hdmi21_rx_pkdec_00_14  rs_rx_hdmi21_rx_pkdec_00_14;
struct _rs_rx_hdmi21_rx_pkdec_00_14 {
    unsigned int regr_00_drm_payload16                      : 8;
    unsigned int regr_00_drm_payload17                      : 8;
    unsigned int regr_00_drm_payload18                      : 8;
    unsigned int regr_00_drm_payload19                      : 8;
};
#define rx_hdmi21_rx_pkdec_00_14(val) ((rs_rx_hdmi21_rx_pkdec_00_14*)&(val))



#define RX_HDMI21_RX_PKDEC_00_18                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX_PKDEC_00_18_struct                                  rs_rx_hdmi21_rx_pkdec_00_18

typedef struct _rs_rx_hdmi21_rx_pkdec_00_18  rs_rx_hdmi21_rx_pkdec_00_18;
struct _rs_rx_hdmi21_rx_pkdec_00_18 {
    unsigned int regr_00_drm_payload20                      : 8;
    unsigned int regr_00_drm_payload21                      : 8;
    unsigned int regr_00_drm_payload22                      : 8;
    unsigned int regr_00_drm_payload23                      : 8;
};
#define rx_hdmi21_rx_pkdec_00_18(val) ((rs_rx_hdmi21_rx_pkdec_00_18*)&(val))



#define RX_HDMI21_RX_PKDEC_00_1C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX_PKDEC_00_1C_struct                                  rs_rx_hdmi21_rx_pkdec_00_1c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_1c  rs_rx_hdmi21_rx_pkdec_00_1c;
struct _rs_rx_hdmi21_rx_pkdec_00_1c {
    unsigned int regr_00_drm_payload24                      : 8;
    unsigned int regr_00_drm_payload25                      : 8;
    unsigned int regr_00_drm_payload26                      : 8;
    unsigned int regr_00_drm_payload27                      : 8;
};
#define rx_hdmi21_rx_pkdec_00_1c(val) ((rs_rx_hdmi21_rx_pkdec_00_1c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_24                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x24)

#define RX_HDMI21_RX_PKDEC_00_24_struct                                  rs_rx_hdmi21_rx_pkdec_00_24

typedef struct _rs_rx_hdmi21_rx_pkdec_00_24  rs_rx_hdmi21_rx_pkdec_00_24;
struct _rs_rx_hdmi21_rx_pkdec_00_24 {
    unsigned int regr_00_AUDS_MAS_SAMPLE_PRESENT            : 4;
    unsigned int regr_00_AUDS_MAS_SAMPLE_FLAT               : 4;
    unsigned int regr_00_CTSN_CNT_STS                       : 1;
    unsigned int reserved                                   : 7;
    unsigned int regr_00_OBA_OBM_SAMPLES_PRESENT            : 4;
    unsigned int regr_00_OBA_OBM_SAMPLES_INVALID            : 4;
    unsigned int reserved_1                                 : 8;
};
#define rx_hdmi21_rx_pkdec_00_24(val) ((rs_rx_hdmi21_rx_pkdec_00_24*)&(val))



#define RX_HDMI21_RX_PKDEC_00_34                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX_PKDEC_00_34_struct                                  rs_rx_hdmi21_rx_pkdec_00_34

typedef struct _rs_rx_hdmi21_rx_pkdec_00_34  rs_rx_hdmi21_rx_pkdec_00_34;
struct _rs_rx_hdmi21_rx_pkdec_00_34 {
    unsigned int reserved                                   : 4;
    unsigned int reg_00_PD_FIFO_WE                          : 1;
    unsigned int reg_00_PD_FIFO_CLR                         : 1;
    unsigned int reg_00_PD_FIFO_SKIP                        : 1;
    unsigned int reg_00_hd_vsi_mux                          : 1;
    unsigned int reg_00_PD_FIFO_FILL_INFO_CLR               : 1;
    unsigned int reg_00_pkt_clr                             : 1;
    unsigned int reserved_1                                 : 2;
    unsigned int reg_00_GCP_AVMUTE_ALLSPS                   : 1;
    unsigned int reg_00_GCPFORCE_SETAVMUTE                  : 1;
    unsigned int reg_00_GCPFORCE_CLRAVMUTE                  : 1;
    unsigned int reg_00_GCP_GLOBAVMUTE                      : 1;
    unsigned int reg_00_PFIFO_STORE_ACR                     : 1;
    unsigned int reg_00_PFIFO_STORE_GCP                     : 1;
    unsigned int reg_00_PFIFO_STORE_ACP                     : 1;
    unsigned int reg_00_PFIFO_STORE_ISRC1                   : 1;
    unsigned int reg_00_PFIFO_STORE_ISRC2                   : 1;
    unsigned int reg_00_PFIFO_STORE_GMTP                    : 1;
    unsigned int reg_00_PFIFO_STORE_VS_IF                   : 1;
    unsigned int reg_00_PFIFO_STORE_AVI_IF                  : 1;
    unsigned int reg_00_PFIFO_STORE_SPD_IF                  : 1;
    unsigned int reg_00_PFIFO_STORE_AUD_IF                  : 1;
    unsigned int reg_00_PFIFO_STORE_MPEGS_IF                : 1;
    unsigned int reg_00_PFIFO_STORE_NTSCVBI_IF              : 1;
    unsigned int reg_00_PFIFO_STORE_AMP                     : 1;
    unsigned int reg_00_PFIFO_STORE_DRM_IF                  : 1;
    unsigned int reg_00_PFIFO_STORE_EMP                     : 1;
    unsigned int reg_00_PFIFO_STORE_FILTER_EN               : 1;
};
#define rx_hdmi21_rx_pkdec_00_34(val) ((rs_rx_hdmi21_rx_pkdec_00_34*)&(val))



#define RX_HDMI21_RX_PKDEC_00_38                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX_PKDEC_00_38_struct                                  rs_rx_hdmi21_rx_pkdec_00_38

typedef struct _rs_rx_hdmi21_rx_pkdec_00_38  rs_rx_hdmi21_rx_pkdec_00_38;
struct _rs_rx_hdmi21_rx_pkdec_00_38 {
    unsigned int reg_00_PD_FIFO_TH_MIN                      :10;
    unsigned int reg_00_PD_FIFO_TH_MAX                      :10;
    unsigned int reg_00_PD_FIFO_TH_START                    :10;
    unsigned int reserved                                   : 2;
};
#define rx_hdmi21_rx_pkdec_00_38(val) ((rs_rx_hdmi21_rx_pkdec_00_38*)&(val))



#define RX_HDMI21_RX_PKDEC_00_3C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX_PKDEC_00_3C_struct                                  rs_rx_hdmi21_rx_pkdec_00_3c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_3c  rs_rx_hdmi21_rx_pkdec_00_3c;
struct _rs_rx_hdmi21_rx_pkdec_00_3c {
    unsigned int regr_00_PD_FIFO_FILL_MIN                   :16;
    unsigned int regr_00_PD_FIFO_FILL_MAX                   :16;
};
#define rx_hdmi21_rx_pkdec_00_3c(val) ((rs_rx_hdmi21_rx_pkdec_00_3c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_40                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x40)

#define RX_HDMI21_RX_PKDEC_00_40_struct                                  rs_rx_hdmi21_rx_pkdec_00_40

typedef struct _rs_rx_hdmi21_rx_pkdec_00_40  rs_rx_hdmi21_rx_pkdec_00_40;
struct _rs_rx_hdmi21_rx_pkdec_00_40 {
    unsigned int regr_00_PD_FIFO_DATA                       :32;
};
#define rx_hdmi21_rx_pkdec_00_40(val) ((rs_rx_hdmi21_rx_pkdec_00_40*)&(val))



#define RX_HDMI21_RX_PKDEC_00_44                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x44)

#define RX_HDMI21_RX_PKDEC_00_44_struct                                  rs_rx_hdmi21_rx_pkdec_00_44

typedef struct _rs_rx_hdmi21_rx_pkdec_00_44  rs_rx_hdmi21_rx_pkdec_00_44;
struct _rs_rx_hdmi21_rx_pkdec_00_44 {
    unsigned int reg_00_AUDIODET_THRESHOLD                  : 5;
    unsigned int reg_00_PFIFO_STORE_USR                     : 1;
    unsigned int reg_00_PFIFO_USR_PH                        : 8;
    unsigned int reserved                                   :18;
};
#define rx_hdmi21_rx_pkdec_00_44(val) ((rs_rx_hdmi21_rx_pkdec_00_44*)&(val))



#define RX_HDMI21_RX_PKDEC_00_50                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x50)

#define RX_HDMI21_RX_PKDEC_00_50_struct                                  rs_rx_hdmi21_rx_pkdec_00_50

typedef struct _rs_rx_hdmi21_rx_pkdec_00_50  rs_rx_hdmi21_rx_pkdec_00_50;
struct _rs_rx_hdmi21_rx_pkdec_00_50 {
    unsigned int regr_00_PD_FIFO_FILL_STATE                 :16;
    unsigned int reserved                                   :16;
};
#define rx_hdmi21_rx_pkdec_00_50(val) ((rs_rx_hdmi21_rx_pkdec_00_50*)&(val))



#define RX_HDMI21_RX_PKDEC_00_54                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x54)

#define RX_HDMI21_RX_PKDEC_00_54_struct                                  rs_rx_hdmi21_rx_pkdec_00_54

typedef struct _rs_rx_hdmi21_rx_pkdec_00_54  rs_rx_hdmi21_rx_pkdec_00_54;
struct _rs_rx_hdmi21_rx_pkdec_00_54 {
    unsigned int reg_00_CTS_N_MEAS_MODE                     : 2;
    unsigned int reg_00_DELTACTS_IRQTRIG                    : 3;
    unsigned int reserved                                   :27;
};
#define rx_hdmi21_rx_pkdec_00_54(val) ((rs_rx_hdmi21_rx_pkdec_00_54*)&(val))



#define RX_HDMI21_RX_PKDEC_00_58                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x58)

#define RX_HDMI21_RX_PKDEC_00_58_struct                                  rs_rx_hdmi21_rx_pkdec_00_58

typedef struct _rs_rx_hdmi21_rx_pkdec_00_58  rs_rx_hdmi21_rx_pkdec_00_58;
struct _rs_rx_hdmi21_rx_pkdec_00_58 {
    unsigned int regr_00_CTS_N_MAX                          :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_pkdec_00_58(val) ((rs_rx_hdmi21_rx_pkdec_00_58*)&(val))



#define RX_HDMI21_RX_PKDEC_00_5C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x5C)

#define RX_HDMI21_RX_PKDEC_00_5C_struct                                  rs_rx_hdmi21_rx_pkdec_00_5c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_5c  rs_rx_hdmi21_rx_pkdec_00_5c;
struct _rs_rx_hdmi21_rx_pkdec_00_5c {
    unsigned int regr_00_CTS_N_MIN                          :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_pkdec_00_5c(val) ((rs_rx_hdmi21_rx_pkdec_00_5c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_64                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x64)

#define RX_HDMI21_RX_PKDEC_00_64_struct                                  rs_rx_hdmi21_rx_pkdec_00_64

typedef struct _rs_rx_hdmi21_rx_pkdec_00_64  rs_rx_hdmi21_rx_pkdec_00_64;
struct _rs_rx_hdmi21_rx_pkdec_00_64 {
    unsigned int reserved                                   : 8;
    unsigned int reg_00_pram_dat_read_strobe                : 1;
    unsigned int reserved_1                                 :23;
};
#define rx_hdmi21_rx_pkdec_00_64(val) ((rs_rx_hdmi21_rx_pkdec_00_64*)&(val))



#define RX_HDMI21_RX_PKDEC_00_68                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x68)

#define RX_HDMI21_RX_PKDEC_00_68_struct                                  rs_rx_hdmi21_rx_pkdec_00_68

typedef struct _rs_rx_hdmi21_rx_pkdec_00_68  rs_rx_hdmi21_rx_pkdec_00_68;
struct _rs_rx_hdmi21_rx_pkdec_00_68 {
    unsigned int regr_00_PD_FIFO_TH_MIN_PASS                : 1;
    unsigned int regr_00_PD_FIFO_TH_MAX_PASS                : 1;
    unsigned int regr_00_PD_FIFO_TH_START_PASS              : 1;
    unsigned int regr_00_PD_FIFO_UNDERFL                    : 1;
    unsigned int regr_00_PD_FIFO_OVERFL                     : 1;
    unsigned int reserved                                   : 3;
    unsigned int regr_00_PD_FIFO_NEW_ENTRY                  : 1;
    unsigned int reserved_1                                 : 2;
    unsigned int regr_00_AUDS_LAYOUT                        : 1;
    unsigned int regr_00_OBA_LAYOUT                         : 1;
    unsigned int regr_00_NTSCVBI_RCV                        : 1;
    unsigned int regr_00_AMP_RCV                            : 1;
    unsigned int regr_00_VSI_RCV                            : 1;
    unsigned int regr_00_GCP_RCV                            : 1;
    unsigned int regr_00_ACR_RCV                            : 1;
    unsigned int regr_00_AVI_RCV                            : 1;
    unsigned int regr_00_AIF_RCV                            : 1;
    unsigned int regr_00_GMD_RCV                            : 1;
    unsigned int regr_00_GCP_AV_MUTE_CHG                    : 1;
    unsigned int regr_00_ACR_CTS_CHG                        : 1;
    unsigned int regr_00_ACR_N_CHG                          : 1;
    unsigned int regr_00_AVI_CKS_CHG                        : 1;
    unsigned int regr_00_AIF_CKS_CHG                        : 1;
    unsigned int regr_00_GMD_CKS_CHG                        : 1;
    unsigned int regr_00_VSI_CKS_CHG                        : 1;
    unsigned int reserved_2                                 : 1;
    unsigned int regr_00_NTSCVBI_CKS_CHG                    : 1;
    unsigned int regr_00_DRM_RCV                            : 1;
    unsigned int regr_00_DRM_CKS_CHG                        : 1;
};
#define rx_hdmi21_rx_pkdec_00_68(val) ((rs_rx_hdmi21_rx_pkdec_00_68*)&(val))



#define RX_HDMI21_RX_PKDEC_00_6C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x6C)

#define RX_HDMI21_RX_PKDEC_00_6C_struct                                  rs_rx_hdmi21_rx_pkdec_00_6c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_6c  rs_rx_hdmi21_rx_pkdec_00_6c;
struct _rs_rx_hdmi21_rx_pkdec_00_6c {
    unsigned int regr_00_AUDS_RCV                           : 1;
    unsigned int regr_00_OBA_RCV                            : 1;
    unsigned int regr_00_DST_RCV                            : 1;
    unsigned int regr_00_HBR_RCV                            : 1;
    unsigned int regr_00_OBM_RCV                            : 1;
    unsigned int regr_00_MAS_RCV                            : 1;
    unsigned int reserved                                   :26;
};
#define rx_hdmi21_rx_pkdec_00_6c(val) ((rs_rx_hdmi21_rx_pkdec_00_6c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_70                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x70)

#define RX_HDMI21_RX_PKDEC_00_70_struct                                  rs_rx_hdmi21_rx_pkdec_00_70

typedef struct _rs_rx_hdmi21_rx_pkdec_00_70  rs_rx_hdmi21_rx_pkdec_00_70;
struct _rs_rx_hdmi21_rx_pkdec_00_70 {
    unsigned int regr_00_VSI_VSPAYLOAD_0                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_1                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_2                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_3                    : 8;
};
#define rx_hdmi21_rx_pkdec_00_70(val) ((rs_rx_hdmi21_rx_pkdec_00_70*)&(val))



#define RX_HDMI21_RX_PKDEC_00_74                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x74)

#define RX_HDMI21_RX_PKDEC_00_74_struct                                  rs_rx_hdmi21_rx_pkdec_00_74

typedef struct _rs_rx_hdmi21_rx_pkdec_00_74  rs_rx_hdmi21_rx_pkdec_00_74;
struct _rs_rx_hdmi21_rx_pkdec_00_74 {
    unsigned int regr_00_VSI_VSPAYLOAD_4                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_5                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_6                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_7                    : 8;
};
#define rx_hdmi21_rx_pkdec_00_74(val) ((rs_rx_hdmi21_rx_pkdec_00_74*)&(val))



#define RX_HDMI21_RX_PKDEC_00_78                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x78)

#define RX_HDMI21_RX_PKDEC_00_78_struct                                  rs_rx_hdmi21_rx_pkdec_00_78

typedef struct _rs_rx_hdmi21_rx_pkdec_00_78  rs_rx_hdmi21_rx_pkdec_00_78;
struct _rs_rx_hdmi21_rx_pkdec_00_78 {
    unsigned int regr_00_VSI_VSPAYLOAD_8                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_9                    : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_10                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_11                   : 8;
};
#define rx_hdmi21_rx_pkdec_00_78(val) ((rs_rx_hdmi21_rx_pkdec_00_78*)&(val))



#define RX_HDMI21_RX_PKDEC_00_7C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x7C)

#define RX_HDMI21_RX_PKDEC_00_7C_struct                                  rs_rx_hdmi21_rx_pkdec_00_7c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_7c  rs_rx_hdmi21_rx_pkdec_00_7c;
struct _rs_rx_hdmi21_rx_pkdec_00_7c {
    unsigned int regr_00_VSI_VSPAYLOAD_12                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_13                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_14                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_15                   : 8;
};
#define rx_hdmi21_rx_pkdec_00_7c(val) ((rs_rx_hdmi21_rx_pkdec_00_7c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_80                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x80)

#define RX_HDMI21_RX_PKDEC_00_80_struct                                  rs_rx_hdmi21_rx_pkdec_00_80

typedef struct _rs_rx_hdmi21_rx_pkdec_00_80  rs_rx_hdmi21_rx_pkdec_00_80;
struct _rs_rx_hdmi21_rx_pkdec_00_80 {
    unsigned int regr_00_VSI_VSPAYLOAD_16                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_17                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_18                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_19                   : 8;
};
#define rx_hdmi21_rx_pkdec_00_80(val) ((rs_rx_hdmi21_rx_pkdec_00_80*)&(val))



#define RX_HDMI21_RX_PKDEC_00_84                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x84)

#define RX_HDMI21_RX_PKDEC_00_84_struct                                  rs_rx_hdmi21_rx_pkdec_00_84

typedef struct _rs_rx_hdmi21_rx_pkdec_00_84  rs_rx_hdmi21_rx_pkdec_00_84;
struct _rs_rx_hdmi21_rx_pkdec_00_84 {
    unsigned int regr_00_VSI_VSPAYLOAD_20                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_21                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_22                   : 8;
    unsigned int regr_00_VSI_VSPAYLOAD_23                   : 8;
};
#define rx_hdmi21_rx_pkdec_00_84(val) ((rs_rx_hdmi21_rx_pkdec_00_84*)&(val))



#define RX_HDMI21_RX_PKDEC_00_8C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x8C)

#define RX_HDMI21_RX_PKDEC_00_8C_struct                                  rs_rx_hdmi21_rx_pkdec_00_8c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_8c  rs_rx_hdmi21_rx_pkdec_00_8c;
struct _rs_rx_hdmi21_rx_pkdec_00_8c {
    unsigned int regr_00_PKTDEC_CLRAVMUTE                   : 1;
    unsigned int regr_00_PKTDEC_SETAVMUTE                   : 1;
    unsigned int reserved                                   : 2;
    unsigned int regr_00_PKTDEC_GCP_CD                      : 4;
    unsigned int regr_00_PKTDEC_GCP_PP                      : 4;
    unsigned int regr_00_PKTDEC_DEFAULT_PHASE               : 1;
    unsigned int reserved_1                                 :19;
};
#define rx_hdmi21_rx_pkdec_00_8c(val) ((rs_rx_hdmi21_rx_pkdec_00_8c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_90                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x90)

#define RX_HDMI21_RX_PKDEC_00_90_struct                                  rs_rx_hdmi21_rx_pkdec_00_90

typedef struct _rs_rx_hdmi21_rx_pkdec_00_90  rs_rx_hdmi21_rx_pkdec_00_90;
struct _rs_rx_hdmi21_rx_pkdec_00_90 {
    unsigned int regr_00_CTS_DECODED                        :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_pkdec_00_90(val) ((rs_rx_hdmi21_rx_pkdec_00_90*)&(val))



#define RX_HDMI21_RX_PKDEC_00_94                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x94)

#define RX_HDMI21_RX_PKDEC_00_94_struct                                  rs_rx_hdmi21_rx_pkdec_00_94

typedef struct _rs_rx_hdmi21_rx_pkdec_00_94  rs_rx_hdmi21_rx_pkdec_00_94;
struct _rs_rx_hdmi21_rx_pkdec_00_94 {
    unsigned int regr_00_N_DECODED                          :20;
    unsigned int reserved                                   : 8;
    unsigned int regr_00_AVI_ACE                            : 4;
};
#define rx_hdmi21_rx_pkdec_00_94(val) ((rs_rx_hdmi21_rx_pkdec_00_94*)&(val))



#define RX_HDMI21_RX_PKDEC_00_98                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x98)

#define RX_HDMI21_RX_PKDEC_00_98_struct                                  rs_rx_hdmi21_rx_pkdec_00_98

typedef struct _rs_rx_hdmi21_rx_pkdec_00_98  rs_rx_hdmi21_rx_pkdec_00_98;
struct _rs_rx_hdmi21_rx_pkdec_00_98 {
    unsigned int regr_00_AVI_VERSION                        : 8;
    unsigned int regr_00_AVI_LENGTH                         : 5;
    unsigned int reserved                                   : 3;
    unsigned int regr_00_AVI_CHECKSUM                       : 8;
    unsigned int regr_00_PIX_REP_FACTOR                     : 4;
    unsigned int regr_00_CONTENT_TYPE                       : 2;
    unsigned int regr_00_QUANT_RANGE                        : 2;
};
#define rx_hdmi21_rx_pkdec_00_98(val) ((rs_rx_hdmi21_rx_pkdec_00_98*)&(val))



#define RX_HDMI21_RX_PKDEC_00_9C                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0x9C)

#define RX_HDMI21_RX_PKDEC_00_9C_struct                                  rs_rx_hdmi21_rx_pkdec_00_9c

typedef struct _rs_rx_hdmi21_rx_pkdec_00_9c  rs_rx_hdmi21_rx_pkdec_00_9c;
struct _rs_rx_hdmi21_rx_pkdec_00_9c {
    unsigned int regr_00_SCAN_INFO                          : 2;
    unsigned int regr_00_BAR_INFO_VALID                     : 2;
    unsigned int regr_00_ACT_INFO_PRESENT                   : 1;
    unsigned int regr_00_VIDEO_FORMAT                       : 2;
    unsigned int regr_00_VIDEO_FORMAT_Y2                    : 1;
    unsigned int regr_00_ACT_ASPECT_RAT                     : 4;
    unsigned int regr_00_PIC_ASPECT_RAT                     : 2;
    unsigned int regr_00_COLORIMETRY                        : 2;
    unsigned int regr_00_NON_UNIF_SCALE                     : 2;
    unsigned int regr_00_RGB_QUANT_RANGE                    : 2;
    unsigned int regr_00_EXT_COLORIMETRY                    : 3;
    unsigned int regr_00_IT_CONTENT                         : 1;
    unsigned int regr_00_VID_IDENT_CODE                     : 7;
    unsigned int regr_00_VID_IDENT_CODE_VIC7                : 1;
};
#define rx_hdmi21_rx_pkdec_00_9c(val) ((rs_rx_hdmi21_rx_pkdec_00_9c*)&(val))



#define RX_HDMI21_RX_PKDEC_00_A0                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xA0)

#define RX_HDMI21_RX_PKDEC_00_A0_struct                                  rs_rx_hdmi21_rx_pkdec_00_a0

typedef struct _rs_rx_hdmi21_rx_pkdec_00_a0  rs_rx_hdmi21_rx_pkdec_00_a0;
struct _rs_rx_hdmi21_rx_pkdec_00_a0 {
    unsigned int regr_00_LIN_END_TOP_BAR                    :16;
    unsigned int regr_00_LIN_ST_BOT_BAR                     :16;
};
#define rx_hdmi21_rx_pkdec_00_a0(val) ((rs_rx_hdmi21_rx_pkdec_00_a0*)&(val))



#define RX_HDMI21_RX_PKDEC_00_A4                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xA4)

#define RX_HDMI21_RX_PKDEC_00_A4_struct                                  rs_rx_hdmi21_rx_pkdec_00_a4

typedef struct _rs_rx_hdmi21_rx_pkdec_00_a4  rs_rx_hdmi21_rx_pkdec_00_a4;
struct _rs_rx_hdmi21_rx_pkdec_00_a4 {
    unsigned int regr_00_PIX_END_LEF_BAR                    :16;
    unsigned int regr_00_PIX_ST_RIG_BAR                     :16;
};
#define rx_hdmi21_rx_pkdec_00_a4(val) ((rs_rx_hdmi21_rx_pkdec_00_a4*)&(val))



#define RX_HDMI21_RX_PKDEC_00_A8                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xA8)

#define RX_HDMI21_RX_PKDEC_00_A8_struct                                  rs_rx_hdmi21_rx_pkdec_00_a8

typedef struct _rs_rx_hdmi21_rx_pkdec_00_a8  rs_rx_hdmi21_rx_pkdec_00_a8;
struct _rs_rx_hdmi21_rx_pkdec_00_a8 {
    unsigned int regr_00_AIF_VERSION                        : 8;
    unsigned int regr_00_AIF_LENGTH                         : 5;
    unsigned int regr_00_AIF_CHECK_SUM                      : 8;
    unsigned int regr_00_CHANNEL_COUNT                      : 3;
    unsigned int regr_00_CODING_TYPE                        : 4;
    unsigned int regr_00_SAMPLE_SIZE                        : 2;
    unsigned int reserved                                   : 2;
};
#define rx_hdmi21_rx_pkdec_00_a8(val) ((rs_rx_hdmi21_rx_pkdec_00_a8*)&(val))



#define RX_HDMI21_RX_PKDEC_00_AC                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xAC)

#define RX_HDMI21_RX_PKDEC_00_AC_struct                                  rs_rx_hdmi21_rx_pkdec_00_ac

typedef struct _rs_rx_hdmi21_rx_pkdec_00_ac  rs_rx_hdmi21_rx_pkdec_00_ac;
struct _rs_rx_hdmi21_rx_pkdec_00_ac {
    unsigned int regr_00_SAMPLE_FREQ                        : 3;
    unsigned int regr_00_AIF_DATA_BYTE_3                    : 8;
    unsigned int regr_00_CH_SPEAK_ALLOC                     : 8;
    unsigned int regr_00_LEVEL_SHIFT_VAL                    : 4;
    unsigned int regr_00_DWNMIX_INHIBIT                     : 1;
    unsigned int regr_00_LFE_PLAYBACK_LEVEL                 : 2;
    unsigned int regr_00_GMD_AFF_GAMUT_SEQ                  : 4;
    unsigned int reserved                                   : 2;
};
#define rx_hdmi21_rx_pkdec_00_ac(val) ((rs_rx_hdmi21_rx_pkdec_00_ac*)&(val))



#define RX_HDMI21_RX_PKDEC_00_B0                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xB0)

#define RX_HDMI21_RX_PKDEC_00_B0_struct                                  rs_rx_hdmi21_rx_pkdec_00_b0

typedef struct _rs_rx_hdmi21_rx_pkdec_00_b0  rs_rx_hdmi21_rx_pkdec_00_b0;
struct _rs_rx_hdmi21_rx_pkdec_00_b0 {
    unsigned int regr_00_GMD_GBD_PROFILE                    : 3;
    unsigned int regr_00_GMD_NEXT_FILED                     : 1;
    unsigned int regr_00_GMD_CUR_GM_SEQ_NUM                 : 4;
    unsigned int regr_00_GMD_PACKET_SEQ                     : 2;
    unsigned int regr_00_GMD_NO_CMT_GBD                     : 1;
    unsigned int regr_00_GMD_GBD_LENGTH                     :16;
    unsigned int regr_00_vsi_LENGTH                         : 5;
};
#define rx_hdmi21_rx_pkdec_00_b0(val) ((rs_rx_hdmi21_rx_pkdec_00_b0*)&(val))



#define RX_HDMI21_RX_PKDEC_00_B4                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xB4)

#define RX_HDMI21_RX_PKDEC_00_B4_struct                                  rs_rx_hdmi21_rx_pkdec_00_b4

typedef struct _rs_rx_hdmi21_rx_pkdec_00_b4  rs_rx_hdmi21_rx_pkdec_00_b4;
struct _rs_rx_hdmi21_rx_pkdec_00_b4 {
    unsigned int regr_00_GMD_CHECKSUM                       : 8;
    unsigned int regr_00_IEEE_REG_ID                        :24;
};
#define rx_hdmi21_rx_pkdec_00_b4(val) ((rs_rx_hdmi21_rx_pkdec_00_b4*)&(val))



#define RX_HDMI21_RX_PKDEC_00_B8                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xB8)

#define RX_HDMI21_RX_PKDEC_00_B8_struct                                  rs_rx_hdmi21_rx_pkdec_00_b8

typedef struct _rs_rx_hdmi21_rx_pkdec_00_b8  rs_rx_hdmi21_rx_pkdec_00_b8;
struct _rs_rx_hdmi21_rx_pkdec_00_b8 {
    unsigned int regr_00_share_HEADER_BYTE0                 : 8;
    unsigned int regr_00_share_HEADER_BYTE1                 : 8;
    unsigned int reserved                                   :16;
};
#define rx_hdmi21_rx_pkdec_00_b8(val) ((rs_rx_hdmi21_rx_pkdec_00_b8*)&(val))



#define RX_HDMI21_RX_PKDEC_00_BC                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xBC)

#define RX_HDMI21_RX_PKDEC_00_BC_struct                                  rs_rx_hdmi21_rx_pkdec_00_bc

typedef struct _rs_rx_hdmi21_rx_pkdec_00_bc  rs_rx_hdmi21_rx_pkdec_00_bc;
struct _rs_rx_hdmi21_rx_pkdec_00_bc {
    unsigned int regr_00_share_PACKET_BYTE0                 : 8;
    unsigned int regr_00_share_PACKET_BYTE1                 : 8;
    unsigned int regr_00_share_PACKET_BYTE2                 : 8;
    unsigned int regr_00_share_PACKET_BYTE3                 : 8;
};
#define rx_hdmi21_rx_pkdec_00_bc(val) ((rs_rx_hdmi21_rx_pkdec_00_bc*)&(val))



#define RX_HDMI21_RX_PKDEC_00_C0                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xC0)

#define RX_HDMI21_RX_PKDEC_00_C0_struct                                  rs_rx_hdmi21_rx_pkdec_00_c0

typedef struct _rs_rx_hdmi21_rx_pkdec_00_c0  rs_rx_hdmi21_rx_pkdec_00_c0;
struct _rs_rx_hdmi21_rx_pkdec_00_c0 {
    unsigned int regr_00_share_PACKET_BYTE4                 : 8;
    unsigned int regr_00_share_PACKET_BYTE5                 : 8;
    unsigned int regr_00_share_PACKET_BYTE6                 : 8;
    unsigned int regr_00_share_PACKET_BYTE7                 : 8;
};
#define rx_hdmi21_rx_pkdec_00_c0(val) ((rs_rx_hdmi21_rx_pkdec_00_c0*)&(val))



#define RX_HDMI21_RX_PKDEC_00_C4                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xC4)

#define RX_HDMI21_RX_PKDEC_00_C4_struct                                  rs_rx_hdmi21_rx_pkdec_00_c4

typedef struct _rs_rx_hdmi21_rx_pkdec_00_c4  rs_rx_hdmi21_rx_pkdec_00_c4;
struct _rs_rx_hdmi21_rx_pkdec_00_c4 {
    unsigned int regr_00_share_PACKET_BYTE8                 : 8;
    unsigned int regr_00_share_PACKET_BYTE9                 : 8;
    unsigned int regr_00_share_PACKET_BYTE10                : 8;
    unsigned int regr_00_share_PACKET_BYTE11                : 8;
};
#define rx_hdmi21_rx_pkdec_00_c4(val) ((rs_rx_hdmi21_rx_pkdec_00_c4*)&(val))



#define RX_HDMI21_RX_PKDEC_00_C8                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xC8)

#define RX_HDMI21_RX_PKDEC_00_C8_struct                                  rs_rx_hdmi21_rx_pkdec_00_c8

typedef struct _rs_rx_hdmi21_rx_pkdec_00_c8  rs_rx_hdmi21_rx_pkdec_00_c8;
struct _rs_rx_hdmi21_rx_pkdec_00_c8 {
    unsigned int regr_00_share_PACKET_BYTE12                : 8;
    unsigned int regr_00_share_PACKET_BYTE13                : 8;
    unsigned int regr_00_share_PACKET_BYTE14                : 8;
    unsigned int regr_00_share_PACKET_BYTE15                : 8;
};
#define rx_hdmi21_rx_pkdec_00_c8(val) ((rs_rx_hdmi21_rx_pkdec_00_c8*)&(val))



#define RX_HDMI21_RX_PKDEC_00_CC                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xCC)

#define RX_HDMI21_RX_PKDEC_00_CC_struct                                  rs_rx_hdmi21_rx_pkdec_00_cc

typedef struct _rs_rx_hdmi21_rx_pkdec_00_cc  rs_rx_hdmi21_rx_pkdec_00_cc;
struct _rs_rx_hdmi21_rx_pkdec_00_cc {
    unsigned int regr_00_share_PACKET_BYTE16                : 8;
    unsigned int regr_00_share_PACKET_BYTE17                : 8;
    unsigned int regr_00_share_PACKET_BYTE18                : 8;
    unsigned int regr_00_share_PACKET_BYTE19                : 8;
};
#define rx_hdmi21_rx_pkdec_00_cc(val) ((rs_rx_hdmi21_rx_pkdec_00_cc*)&(val))



#define RX_HDMI21_RX_PKDEC_00_D0                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xD0)

#define RX_HDMI21_RX_PKDEC_00_D0_struct                                  rs_rx_hdmi21_rx_pkdec_00_d0

typedef struct _rs_rx_hdmi21_rx_pkdec_00_d0  rs_rx_hdmi21_rx_pkdec_00_d0;
struct _rs_rx_hdmi21_rx_pkdec_00_d0 {
    unsigned int regr_00_share_PACKET_BYTE20                : 8;
    unsigned int regr_00_share_PACKET_BYTE21                : 8;
    unsigned int regr_00_share_PACKET_BYTE22                : 8;
    unsigned int regr_00_share_PACKET_BYTE23                : 8;
};
#define rx_hdmi21_rx_pkdec_00_d0(val) ((rs_rx_hdmi21_rx_pkdec_00_d0*)&(val))



#define RX_HDMI21_RX_PKDEC_00_D4                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xD4)

#define RX_HDMI21_RX_PKDEC_00_D4_struct                                  rs_rx_hdmi21_rx_pkdec_00_d4

typedef struct _rs_rx_hdmi21_rx_pkdec_00_d4  rs_rx_hdmi21_rx_pkdec_00_d4;
struct _rs_rx_hdmi21_rx_pkdec_00_d4 {
    unsigned int regr_00_share_PACKET_BYTE24                : 8;
    unsigned int regr_00_share_PACKET_BYTE25                : 8;
    unsigned int regr_00_share_PACKET_BYTE26                : 8;
    unsigned int regr_00_share_PACKET_BYTE27                : 8;
};
#define rx_hdmi21_rx_pkdec_00_d4(val) ((rs_rx_hdmi21_rx_pkdec_00_d4*)&(val))



#define RX_HDMI21_RX_PKDEC_00_D8                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xD8)

#define RX_HDMI21_RX_PKDEC_00_D8_struct                                  rs_rx_hdmi21_rx_pkdec_00_d8

typedef struct _rs_rx_hdmi21_rx_pkdec_00_d8  rs_rx_hdmi21_rx_pkdec_00_d8;
struct _rs_rx_hdmi21_rx_pkdec_00_d8 {
    unsigned int regr_00_share1_HEADER_BYTE0                : 8;
    unsigned int regr_00_share1_HEADER_BYTE1                : 8;
    unsigned int reserved                                   :16;
};
#define rx_hdmi21_rx_pkdec_00_d8(val) ((rs_rx_hdmi21_rx_pkdec_00_d8*)&(val))



#define RX_HDMI21_RX_PKDEC_00_DC                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xDC)

#define RX_HDMI21_RX_PKDEC_00_DC_struct                                  rs_rx_hdmi21_rx_pkdec_00_dc

typedef struct _rs_rx_hdmi21_rx_pkdec_00_dc  rs_rx_hdmi21_rx_pkdec_00_dc;
struct _rs_rx_hdmi21_rx_pkdec_00_dc {
    unsigned int regr_00_share1_PACKET_BYTE0                : 8;
    unsigned int regr_00_share1_PACKET_BYTE1                : 8;
    unsigned int regr_00_share1_PACKET_BYTE2                : 8;
    unsigned int regr_00_share1_PACKET_BYTE3                : 8;
};
#define rx_hdmi21_rx_pkdec_00_dc(val) ((rs_rx_hdmi21_rx_pkdec_00_dc*)&(val))



#define RX_HDMI21_RX_PKDEC_00_E0                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xE0)

#define RX_HDMI21_RX_PKDEC_00_E0_struct                                  rs_rx_hdmi21_rx_pkdec_00_e0

typedef struct _rs_rx_hdmi21_rx_pkdec_00_e0  rs_rx_hdmi21_rx_pkdec_00_e0;
struct _rs_rx_hdmi21_rx_pkdec_00_e0 {
    unsigned int regr_00_share1_PACKET_BYTE4                : 8;
    unsigned int regr_00_share1_PACKET_BYTE5                : 8;
    unsigned int regr_00_share1_PACKET_BYTE6                : 8;
    unsigned int regr_00_share1_PACKET_BYTE7                : 8;
};
#define rx_hdmi21_rx_pkdec_00_e0(val) ((rs_rx_hdmi21_rx_pkdec_00_e0*)&(val))



#define RX_HDMI21_RX_PKDEC_00_E4                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xE4)

#define RX_HDMI21_RX_PKDEC_00_E4_struct                                  rs_rx_hdmi21_rx_pkdec_00_e4

typedef struct _rs_rx_hdmi21_rx_pkdec_00_e4  rs_rx_hdmi21_rx_pkdec_00_e4;
struct _rs_rx_hdmi21_rx_pkdec_00_e4 {
    unsigned int regr_00_share1_PACKET_BYTE8                : 8;
    unsigned int regr_00_share1_PACKET_BYTE9                : 8;
    unsigned int regr_00_share1_PACKET_BYTE10               : 8;
    unsigned int regr_00_share1_PACKET_BYTE11               : 8;
};
#define rx_hdmi21_rx_pkdec_00_e4(val) ((rs_rx_hdmi21_rx_pkdec_00_e4*)&(val))



#define RX_HDMI21_RX_PKDEC_00_E8                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xE8)

#define RX_HDMI21_RX_PKDEC_00_E8_struct                                  rs_rx_hdmi21_rx_pkdec_00_e8

typedef struct _rs_rx_hdmi21_rx_pkdec_00_e8  rs_rx_hdmi21_rx_pkdec_00_e8;
struct _rs_rx_hdmi21_rx_pkdec_00_e8 {
    unsigned int regr_00_share1_PACKET_BYTE12               : 8;
    unsigned int regr_00_share1_PACKET_BYTE13               : 8;
    unsigned int regr_00_share1_PACKET_BYTE14               : 8;
    unsigned int regr_00_share1_PACKET_BYTE15               : 8;
};
#define rx_hdmi21_rx_pkdec_00_e8(val) ((rs_rx_hdmi21_rx_pkdec_00_e8*)&(val))



#define RX_HDMI21_RX_PKDEC_00_EC                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xEC)

#define RX_HDMI21_RX_PKDEC_00_EC_struct                                  rs_rx_hdmi21_rx_pkdec_00_ec

typedef struct _rs_rx_hdmi21_rx_pkdec_00_ec  rs_rx_hdmi21_rx_pkdec_00_ec;
struct _rs_rx_hdmi21_rx_pkdec_00_ec {
    unsigned int regr_00_share1_PACKET_BYTE16               : 8;
    unsigned int regr_00_share1_PACKET_BYTE17               : 8;
    unsigned int regr_00_share1_PACKET_BYTE18               : 8;
    unsigned int regr_00_share1_PACKET_BYTE19               : 8;
};
#define rx_hdmi21_rx_pkdec_00_ec(val) ((rs_rx_hdmi21_rx_pkdec_00_ec*)&(val))



#define RX_HDMI21_RX_PKDEC_00_F0                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xF0)

#define RX_HDMI21_RX_PKDEC_00_F0_struct                                  rs_rx_hdmi21_rx_pkdec_00_f0

typedef struct _rs_rx_hdmi21_rx_pkdec_00_f0  rs_rx_hdmi21_rx_pkdec_00_f0;
struct _rs_rx_hdmi21_rx_pkdec_00_f0 {
    unsigned int regr_00_share1_PACKET_BYTE20               : 8;
    unsigned int regr_00_share1_PACKET_BYTE21               : 8;
    unsigned int regr_00_share1_PACKET_BYTE22               : 8;
    unsigned int regr_00_share1_PACKET_BYTE23               : 8;
};
#define rx_hdmi21_rx_pkdec_00_f0(val) ((rs_rx_hdmi21_rx_pkdec_00_f0*)&(val))



#define RX_HDMI21_RX_PKDEC_00_F4                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xF4)

#define RX_HDMI21_RX_PKDEC_00_F4_struct                                  rs_rx_hdmi21_rx_pkdec_00_f4

typedef struct _rs_rx_hdmi21_rx_pkdec_00_f4  rs_rx_hdmi21_rx_pkdec_00_f4;
struct _rs_rx_hdmi21_rx_pkdec_00_f4 {
    unsigned int regr_00_share1_PACKET_BYTE24               : 8;
    unsigned int regr_00_share1_PACKET_BYTE25               : 8;
    unsigned int regr_00_share1_PACKET_BYTE26               : 8;
    unsigned int regr_00_share1_PACKET_BYTE27               : 8;
};
#define rx_hdmi21_rx_pkdec_00_f4(val) ((rs_rx_hdmi21_rx_pkdec_00_f4*)&(val))



#define RX_HDMI21_RX_PKDEC_00_F8                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xF8)

#define RX_HDMI21_RX_PKDEC_00_F8_struct                                  rs_rx_hdmi21_rx_pkdec_00_f8

typedef struct _rs_rx_hdmi21_rx_pkdec_00_f8  rs_rx_hdmi21_rx_pkdec_00_f8;
struct _rs_rx_hdmi21_rx_pkdec_00_f8 {
    unsigned int reg_00_pkty0_switch                        : 8;
    unsigned int reserved                                   :24;
};
#define rx_hdmi21_rx_pkdec_00_f8(val) ((rs_rx_hdmi21_rx_pkdec_00_f8*)&(val))



#define RX_HDMI21_RX_PKDEC_00_FC                                         (HV_HDMI21_RX_PKDEC_00_BASE_ADDRESS + 0xFC)

#define RX_HDMI21_RX_PKDEC_00_FC_struct                                  rs_rx_hdmi21_rx_pkdec_00_fc

typedef struct _rs_rx_hdmi21_rx_pkdec_00_fc  rs_rx_hdmi21_rx_pkdec_00_fc;
struct _rs_rx_hdmi21_rx_pkdec_00_fc {
    unsigned int reg_00_pkty1_switch                        : 8;
    unsigned int reserved                                   :24;
};
#define rx_hdmi21_rx_pkdec_00_fc(val) ((rs_rx_hdmi21_rx_pkdec_00_fc*)&(val))



#endif