#ifndef _HV_PAGE_HT7315_DPU_RVDM_00_H_
#define _HV_PAGE_HT7315_DPU_RVDM_00_H_

#ifndef HV_DPU_RVDM_00_BASE_ADDRESS
    #define HV_DPU_RVDM_00_BASE_ADDRESS                                         0x11024300
#endif


#define DISP_TOP_DPU_RVDM_00_00                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_RVDM_00_00_struct                                   rs_disp_top_dpu_rvdm_00_00

typedef struct _rs_disp_top_dpu_rvdm_00_00  rs_disp_top_dpu_rvdm_00_00;
struct _rs_disp_top_dpu_rvdm_00_00 {
    unsigned int reg_00_dm_rd_buf_size                      :10;
    unsigned int reserved                                   :22;
};
#define disp_top_dpu_rvdm_00_00(val) ((rs_disp_top_dpu_rvdm_00_00*)&(val))



#define DISP_TOP_DPU_RVDM_00_04                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_RVDM_00_04_struct                                   rs_disp_top_dpu_rvdm_00_04

typedef struct _rs_disp_top_dpu_rvdm_00_04  rs_disp_top_dpu_rvdm_00_04;
struct _rs_disp_top_dpu_rvdm_00_04 {
    unsigned int reg_00_dm_rd_4k_bound_en                   : 1;
    unsigned int reg_00_dm_rd_access_mode                   : 1;
    unsigned int reg_00_dm_rd_burst_len                     : 8;
    unsigned int reg_00_dm_rd_burst_rmd                     : 8;
    unsigned int reg_00_dm_rd_col_step_dir                  : 1;
    unsigned int reg_00_dm_rd_db_en                         : 1;
    unsigned int reg_00_dm_rd_enable                        : 1;
    unsigned int reg_00_dm_rd_head_prefetch_num             : 2;
    unsigned int reg_00_dm_rd_line_step_dir                 : 1;
    unsigned int reg_00_dm_rd_outstanding                   : 4;
    unsigned int reg_00_dm_rd_ovflow_clr                    : 1;
    unsigned int reg_00_dm_rd_udflow_clr                    : 1;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_rvdm_00_04(val) ((rs_disp_top_dpu_rvdm_00_04*)&(val))



#define DISP_TOP_DPU_RVDM_00_08                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_RVDM_00_08_struct                                   rs_disp_top_dpu_rvdm_00_08

typedef struct _rs_disp_top_dpu_rvdm_00_08  rs_disp_top_dpu_rvdm_00_08;
struct _rs_disp_top_dpu_rvdm_00_08 {
    unsigned int reg_00_dm_rd_burst_num                     :32;
};
#define disp_top_dpu_rvdm_00_08(val) ((rs_disp_top_dpu_rvdm_00_08*)&(val))



#define DISP_TOP_DPU_RVDM_00_0C                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_RVDM_00_0C_struct                                   rs_disp_top_dpu_rvdm_00_0c

typedef struct _rs_disp_top_dpu_rvdm_00_0c  rs_disp_top_dpu_rvdm_00_0c;
struct _rs_disp_top_dpu_rvdm_00_0c {
    unsigned int reg_00_dm_rd_col_step                      :32;
};
#define disp_top_dpu_rvdm_00_0c(val) ((rs_disp_top_dpu_rvdm_00_0c*)&(val))



#define DISP_TOP_DPU_RVDM_00_10                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_RVDM_00_10_struct                                   rs_disp_top_dpu_rvdm_00_10

typedef struct _rs_disp_top_dpu_rvdm_00_10  rs_disp_top_dpu_rvdm_00_10;
struct _rs_disp_top_dpu_rvdm_00_10 {
    unsigned int reg_00_dm_rd_line_step                     :32;
};
#define disp_top_dpu_rvdm_00_10(val) ((rs_disp_top_dpu_rvdm_00_10*)&(val))



#define DISP_TOP_DPU_RVDM_00_14                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_RVDM_00_14_struct                                   rs_disp_top_dpu_rvdm_00_14

typedef struct _rs_disp_top_dpu_rvdm_00_14  rs_disp_top_dpu_rvdm_00_14;
struct _rs_disp_top_dpu_rvdm_00_14 {
    unsigned int reg_00_dm_rd_start_adr                     :32;
};
#define disp_top_dpu_rvdm_00_14(val) ((rs_disp_top_dpu_rvdm_00_14*)&(val))



#define DISP_TOP_DPU_RVDM_00_18                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x18)

#define DISP_TOP_DPU_RVDM_00_18_struct                                   rs_disp_top_dpu_rvdm_00_18

typedef struct _rs_disp_top_dpu_rvdm_00_18  rs_disp_top_dpu_rvdm_00_18;
struct _rs_disp_top_dpu_rvdm_00_18 {
    unsigned int reg_00_dm_rd_col_dat_num                   :16;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_rvdm_00_18(val) ((rs_disp_top_dpu_rvdm_00_18*)&(val))



#define DISP_TOP_DPU_RVDM_00_1C                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x1C)

#define DISP_TOP_DPU_RVDM_00_1C_struct                                   rs_disp_top_dpu_rvdm_00_1c

typedef struct _rs_disp_top_dpu_rvdm_00_1c  rs_disp_top_dpu_rvdm_00_1c;
struct _rs_disp_top_dpu_rvdm_00_1c {
    unsigned int reg_00_dm_rd_rdata_index                   :32;
};
#define disp_top_dpu_rvdm_00_1c(val) ((rs_disp_top_dpu_rvdm_00_1c*)&(val))



#define DISP_TOP_DPU_RVDM_00_20                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x20)

#define DISP_TOP_DPU_RVDM_00_20_struct                                   rs_disp_top_dpu_rvdm_00_20

typedef struct _rs_disp_top_dpu_rvdm_00_20  rs_disp_top_dpu_rvdm_00_20;
struct _rs_disp_top_dpu_rvdm_00_20 {
    unsigned int reg_00_dm_rd_total_col_num                 :16;
    unsigned int reg_00_dm_rd_total_line_num                :16;
};
#define disp_top_dpu_rvdm_00_20(val) ((rs_disp_top_dpu_rvdm_00_20*)&(val))



#define DISP_TOP_DPU_RVDM_00_24                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x24)

#define DISP_TOP_DPU_RVDM_00_24_struct                                   rs_disp_top_dpu_rvdm_00_24

typedef struct _rs_disp_top_dpu_rvdm_00_24  rs_disp_top_dpu_rvdm_00_24;
struct _rs_disp_top_dpu_rvdm_00_24 {
    unsigned int reg_00_dm_start_adr0                       :32;
};
#define disp_top_dpu_rvdm_00_24(val) ((rs_disp_top_dpu_rvdm_00_24*)&(val))



#define DISP_TOP_DPU_RVDM_00_28                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x28)

#define DISP_TOP_DPU_RVDM_00_28_struct                                   rs_disp_top_dpu_rvdm_00_28

typedef struct _rs_disp_top_dpu_rvdm_00_28  rs_disp_top_dpu_rvdm_00_28;
struct _rs_disp_top_dpu_rvdm_00_28 {
    unsigned int reg_00_dm_start_adr1                       :32;
};
#define disp_top_dpu_rvdm_00_28(val) ((rs_disp_top_dpu_rvdm_00_28*)&(val))



#define DISP_TOP_DPU_RVDM_00_2C                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x2C)

#define DISP_TOP_DPU_RVDM_00_2C_struct                                   rs_disp_top_dpu_rvdm_00_2c

typedef struct _rs_disp_top_dpu_rvdm_00_2c  rs_disp_top_dpu_rvdm_00_2c;
struct _rs_disp_top_dpu_rvdm_00_2c {
    unsigned int reg_00_dm_start_adr2                       :32;
};
#define disp_top_dpu_rvdm_00_2c(val) ((rs_disp_top_dpu_rvdm_00_2c*)&(val))



#define DISP_TOP_DPU_RVDM_00_30                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x30)

#define DISP_TOP_DPU_RVDM_00_30_struct                                   rs_disp_top_dpu_rvdm_00_30

typedef struct _rs_disp_top_dpu_rvdm_00_30  rs_disp_top_dpu_rvdm_00_30;
struct _rs_disp_top_dpu_rvdm_00_30 {
    unsigned int reg_00_dm_start_adr3                       :32;
};
#define disp_top_dpu_rvdm_00_30(val) ((rs_disp_top_dpu_rvdm_00_30*)&(val))



#define DISP_TOP_DPU_RVDM_00_34                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x34)

#define DISP_TOP_DPU_RVDM_00_34_struct                                   rs_disp_top_dpu_rvdm_00_34

typedef struct _rs_disp_top_dpu_rvdm_00_34  rs_disp_top_dpu_rvdm_00_34;
struct _rs_disp_top_dpu_rvdm_00_34 {
    unsigned int reg_00_dm_start_adr4                       :32;
};
#define disp_top_dpu_rvdm_00_34(val) ((rs_disp_top_dpu_rvdm_00_34*)&(val))



#define DISP_TOP_DPU_RVDM_00_38                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x38)

#define DISP_TOP_DPU_RVDM_00_38_struct                                   rs_disp_top_dpu_rvdm_00_38

typedef struct _rs_disp_top_dpu_rvdm_00_38  rs_disp_top_dpu_rvdm_00_38;
struct _rs_disp_top_dpu_rvdm_00_38 {
    unsigned int reg_00_dm_start_adr5                       :32;
};
#define disp_top_dpu_rvdm_00_38(val) ((rs_disp_top_dpu_rvdm_00_38*)&(val))



#define DISP_TOP_DPU_RVDM_00_3C                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x3C)

#define DISP_TOP_DPU_RVDM_00_3C_struct                                   rs_disp_top_dpu_rvdm_00_3c

typedef struct _rs_disp_top_dpu_rvdm_00_3c  rs_disp_top_dpu_rvdm_00_3c;
struct _rs_disp_top_dpu_rvdm_00_3c {
    unsigned int reg_00_dm_start_adr6                       :32;
};
#define disp_top_dpu_rvdm_00_3c(val) ((rs_disp_top_dpu_rvdm_00_3c*)&(val))



#define DISP_TOP_DPU_RVDM_00_40                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x40)

#define DISP_TOP_DPU_RVDM_00_40_struct                                   rs_disp_top_dpu_rvdm_00_40

typedef struct _rs_disp_top_dpu_rvdm_00_40  rs_disp_top_dpu_rvdm_00_40;
struct _rs_disp_top_dpu_rvdm_00_40 {
    unsigned int reg_00_dm_start_adr7                       :32;
};
#define disp_top_dpu_rvdm_00_40(val) ((rs_disp_top_dpu_rvdm_00_40*)&(val))



#define DISP_TOP_DPU_RVDM_00_44                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x44)

#define DISP_TOP_DPU_RVDM_00_44_struct                                   rs_disp_top_dpu_rvdm_00_44

typedef struct _rs_disp_top_dpu_rvdm_00_44  rs_disp_top_dpu_rvdm_00_44;
struct _rs_disp_top_dpu_rvdm_00_44 {
    unsigned int reg_00_dm_start_addr_sw_enable             : 1;
    unsigned int reserved                                   :31;
};
#define disp_top_dpu_rvdm_00_44(val) ((rs_disp_top_dpu_rvdm_00_44*)&(val))



#define DISP_TOP_DPU_RVDM_00_48                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x48)

#define DISP_TOP_DPU_RVDM_00_48_struct                                   rs_disp_top_dpu_rvdm_00_48

typedef struct _rs_disp_top_dpu_rvdm_00_48  rs_disp_top_dpu_rvdm_00_48;
struct _rs_disp_top_dpu_rvdm_00_48 {
    unsigned int reg_00_dm_sw_start_adr                     :32;
};
#define disp_top_dpu_rvdm_00_48(val) ((rs_disp_top_dpu_rvdm_00_48*)&(val))



#define DISP_TOP_DPU_RVDM_00_4C                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x4C)

#define DISP_TOP_DPU_RVDM_00_4C_struct                                   rs_disp_top_dpu_rvdm_00_4c

typedef struct _rs_disp_top_dpu_rvdm_00_4c  rs_disp_top_dpu_rvdm_00_4c;
struct _rs_disp_top_dpu_rvdm_00_4c {
    unsigned int reg_00_en                                  : 1;
    unsigned int reg_00_en_no_latch                         : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_rvdm_00_4c(val) ((rs_disp_top_dpu_rvdm_00_4c*)&(val))



#define DISP_TOP_DPU_RVDM_00_50                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x50)

#define DISP_TOP_DPU_RVDM_00_50_struct                                   rs_disp_top_dpu_rvdm_00_50

typedef struct _rs_disp_top_dpu_rvdm_00_50  rs_disp_top_dpu_rvdm_00_50;
struct _rs_disp_top_dpu_rvdm_00_50 {
    unsigned int mem_reg_00                                 : 8;
    unsigned int reg_00_mem_ema                             :16;
    unsigned int reserved                                   : 8;
};
#define disp_top_dpu_rvdm_00_50(val) ((rs_disp_top_dpu_rvdm_00_50*)&(val))



#define DISP_TOP_DPU_RVDM_00_80                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x80)

#define DISP_TOP_DPU_RVDM_00_80_struct                                   rs_disp_top_dpu_rvdm_00_80

typedef struct _rs_disp_top_dpu_rvdm_00_80  rs_disp_top_dpu_rvdm_00_80;
struct _rs_disp_top_dpu_rvdm_00_80 {
    unsigned int reg_00_pq_dynamic_crc_enable               : 1;
    unsigned int reserved                                   :31;
};
#define disp_top_dpu_rvdm_00_80(val) ((rs_disp_top_dpu_rvdm_00_80*)&(val))



#define DISP_TOP_DPU_RVDM_00_84                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x84)

#define DISP_TOP_DPU_RVDM_00_84_struct                                   rs_disp_top_dpu_rvdm_00_84

typedef struct _rs_disp_top_dpu_rvdm_00_84  rs_disp_top_dpu_rvdm_00_84;
struct _rs_disp_top_dpu_rvdm_00_84 {
    unsigned int regr_00_dynamic_crc_out0                   :32;
};
#define disp_top_dpu_rvdm_00_84(val) ((rs_disp_top_dpu_rvdm_00_84*)&(val))



#define DISP_TOP_DPU_RVDM_00_88                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x88)

#define DISP_TOP_DPU_RVDM_00_88_struct                                   rs_disp_top_dpu_rvdm_00_88

typedef struct _rs_disp_top_dpu_rvdm_00_88  rs_disp_top_dpu_rvdm_00_88;
struct _rs_disp_top_dpu_rvdm_00_88 {
    unsigned int regr_00_dynamic_crc_out1                   :32;
};
#define disp_top_dpu_rvdm_00_88(val) ((rs_disp_top_dpu_rvdm_00_88*)&(val))



#define DISP_TOP_DPU_RVDM_00_8C                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0x8C)

#define DISP_TOP_DPU_RVDM_00_8C_struct                                   rs_disp_top_dpu_rvdm_00_8c

typedef struct _rs_disp_top_dpu_rvdm_00_8c  rs_disp_top_dpu_rvdm_00_8c;
struct _rs_disp_top_dpu_rvdm_00_8c {
    unsigned int regr_00_pq_dynamic_crc_fail                : 1;
    unsigned int reserved                                   :31;
};
#define disp_top_dpu_rvdm_00_8c(val) ((rs_disp_top_dpu_rvdm_00_8c*)&(val))



#define DISP_TOP_DPU_RVDM_00_DC                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xDC)

#define DISP_TOP_DPU_RVDM_00_DC_struct                                   rs_disp_top_dpu_rvdm_00_dc

typedef struct _rs_disp_top_dpu_rvdm_00_dc  rs_disp_top_dpu_rvdm_00_dc;
struct _rs_disp_top_dpu_rvdm_00_dc {
    unsigned int reg_00_mem_ro                              : 4;
    unsigned int reserved                                   :28;
};
#define disp_top_dpu_rvdm_00_dc(val) ((rs_disp_top_dpu_rvdm_00_dc*)&(val))



#define DISP_TOP_DPU_RVDM_00_E0                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xE0)

#define DISP_TOP_DPU_RVDM_00_E0_struct                                   rs_disp_top_dpu_rvdm_00_e0

typedef struct _rs_disp_top_dpu_rvdm_00_e0  rs_disp_top_dpu_rvdm_00_e0;
struct _rs_disp_top_dpu_rvdm_00_e0 {
    unsigned int regr_00_dm_rd_buf_space                    :10;
    unsigned int reserved                                   :22;
};
#define disp_top_dpu_rvdm_00_e0(val) ((rs_disp_top_dpu_rvdm_00_e0*)&(val))



#define DISP_TOP_DPU_RVDM_00_E4                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xE4)

#define DISP_TOP_DPU_RVDM_00_E4_struct                                   rs_disp_top_dpu_rvdm_00_e4

typedef struct _rs_disp_top_dpu_rvdm_00_e4  rs_disp_top_dpu_rvdm_00_e4;
struct _rs_disp_top_dpu_rvdm_00_e4 {
    unsigned int regr_00_dm_rd_afifo_ovflow                 : 1;
    unsigned int regr_00_dm_rd_afifo_udflow                 : 1;
    unsigned int regr_00_dm_rd_block_num                    :16;
    unsigned int regr_00_dm_rd_buf_ovflow                   : 1;
    unsigned int regr_00_dm_rd_buf_udflow                   : 1;
    unsigned int regr_00_dm_rd_bus_idle                     : 1;
    unsigned int regr_00_dm_rd_cmd_sent                     : 4;
    unsigned int reserved                                   : 7;
};
#define disp_top_dpu_rvdm_00_e4(val) ((rs_disp_top_dpu_rvdm_00_e4*)&(val))



#define DISP_TOP_DPU_RVDM_00_E8                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xE8)

#define DISP_TOP_DPU_RVDM_00_E8_struct                                   rs_disp_top_dpu_rvdm_00_e8

typedef struct _rs_disp_top_dpu_rvdm_00_e8  rs_disp_top_dpu_rvdm_00_e8;
struct _rs_disp_top_dpu_rvdm_00_e8 {
    unsigned int regr_00_dm_rd_cnt                          :32;
};
#define disp_top_dpu_rvdm_00_e8(val) ((rs_disp_top_dpu_rvdm_00_e8*)&(val))



#define DISP_TOP_DPU_RVDM_00_EC                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xEC)

#define DISP_TOP_DPU_RVDM_00_EC_struct                                   rs_disp_top_dpu_rvdm_00_ec

typedef struct _rs_disp_top_dpu_rvdm_00_ec  rs_disp_top_dpu_rvdm_00_ec;
struct _rs_disp_top_dpu_rvdm_00_ec {
    unsigned int regr_00_dm_rd_dat_wait                     :12;
    unsigned int regr_00_dm_rd_line_num                     :16;
    unsigned int regr_00_dm_rd_st                           : 4;
};
#define disp_top_dpu_rvdm_00_ec(val) ((rs_disp_top_dpu_rvdm_00_ec*)&(val))



#define DISP_TOP_DPU_RVDM_00_F0                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xF0)

#define DISP_TOP_DPU_RVDM_00_F0_struct                                   rs_disp_top_dpu_rvdm_00_f0

typedef struct _rs_disp_top_dpu_rvdm_00_f0  rs_disp_top_dpu_rvdm_00_f0;
struct _rs_disp_top_dpu_rvdm_00_f0 {
    unsigned int regr_00_dm_rd_rdata_0                      :32;
};
#define disp_top_dpu_rvdm_00_f0(val) ((rs_disp_top_dpu_rvdm_00_f0*)&(val))



#define DISP_TOP_DPU_RVDM_00_F4                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xF4)

#define DISP_TOP_DPU_RVDM_00_F4_struct                                   rs_disp_top_dpu_rvdm_00_f4

typedef struct _rs_disp_top_dpu_rvdm_00_f4  rs_disp_top_dpu_rvdm_00_f4;
struct _rs_disp_top_dpu_rvdm_00_f4 {
    unsigned int regr_00_dm_rd_rdata_1                      :32;
};
#define disp_top_dpu_rvdm_00_f4(val) ((rs_disp_top_dpu_rvdm_00_f4*)&(val))



#define DISP_TOP_DPU_RVDM_00_F8                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xF8)

#define DISP_TOP_DPU_RVDM_00_F8_struct                                   rs_disp_top_dpu_rvdm_00_f8

typedef struct _rs_disp_top_dpu_rvdm_00_f8  rs_disp_top_dpu_rvdm_00_f8;
struct _rs_disp_top_dpu_rvdm_00_f8 {
    unsigned int regr_00_dm_rd_rdata_2                      :32;
};
#define disp_top_dpu_rvdm_00_f8(val) ((rs_disp_top_dpu_rvdm_00_f8*)&(val))



#define DISP_TOP_DPU_RVDM_00_FC                                          (HV_DPU_RVDM_00_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_RVDM_00_FC_struct                                   rs_disp_top_dpu_rvdm_00_fc

typedef struct _rs_disp_top_dpu_rvdm_00_fc  rs_disp_top_dpu_rvdm_00_fc;
struct _rs_disp_top_dpu_rvdm_00_fc {
    unsigned int regr_00_dm_rd_rdata_3                      :32;
};
#define disp_top_dpu_rvdm_00_fc(val) ((rs_disp_top_dpu_rvdm_00_fc*)&(val))



#endif