/**
 * @file hv_cal_mprt.c
 * @brief MPRT spi CAL module driver
 * @details This module provide interfaces for DRV level.
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 20230203
 * @copyright Copyright(c),2023-2, Hiview Software. All rights reserved.
 * @par History:
 * <table>
 * <tr><th>Author                         <th>Date             <th>Details
 * <tr><td>HiView SoC Software Team   <td>20230203       <td>Create and first Version.
 * </table>
 **/

#include "hv_cal_mprt.h"
#include "hv_vos_Comm.h"
#include "HV_REGS_HT7315.h"
#include "hv_comm_Log.h"


VOID Hv_Cal_MPRT_Init(VOID)
{
    HV_LOG_DEBUG(VIDEO, "Hv_Cal_MPRT_Init");
#if (HV_PROJECT_CONFIG_FULL_LOCALDIMMING == HV_CONFIG_OFF)
    /*PWM 41K*/
    // HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio11_func_sel, 5);
    // HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_1C, reg_gpio11_io_ctrl, 41);
    /*输出 低频mprt*/
    // HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio12_func_sel, 5);
    // HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_1C, reg_gpio12_io_ctrl, 41);
    /*背光总控开关*/
    // HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio13_func_sel, 6);
    // HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_1C, reg_gpio13_io_ctrl, 41);
#endif
    HV_W32_FIELD(TX_PIF_TX_TOP_PIF_TX_CLKGEN0, reg_pif_ptg_clk_en, 1);

    HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode2, 2);
    //HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode3, 2);
    return;
}

VOID Hv_Cal_MPRT_PwmEnable(UCHAR8 ucPort, BOOL bEn)
{
    /*设置o_vsync的脉冲宽度*/
    HV_W32_FIELD(TX_HSTX_TOP_1C, reg_mprt_pwm_broaden, 0xffff);

    switch (ucPort)
    {
        case 0:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable0, bEn);
            break;
        }
        case 1:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable1, bEn);
            break;
        }
        case 2:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable2, bEn);
            break;
        }
        case 3:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable3, bEn);
            break;
        }
        case 4:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable4, bEn);
            break;
        }
        case 5:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable5, bEn);
            break;
        }
        case 6:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable6, bEn);
            break;
        }
        case 7:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable7, bEn);
            break;
        }
        default:
        {
            HV_W32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable0, bEn);
            break;
        }
    }
    return;
}

BOOL Hv_Cal_MPRT_GetPwmEnable(UCHAR8 ucPort)
{
    BOOL bEn = 0;
    HV_R32_DECL_VAR();
    switch (ucPort)
    {
        case 0:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable0);
            break;
        }
        case 1:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable1);
            break;
        }
        case 2:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable2);
            break;
        }
        case 3:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable3);
            break;
        }
        case 4:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable4);
            break;
        }
        case 5:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable5);
            break;
        }
        case 6:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable6);
            break;
        }
        case 7:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable7);
            break;
        }
        default:
        {
            bEn = HV_R32_FIELD(TX_HSTX_TOP_48, reg_mprt_pwm_enable0);
            break;
        }
    }
    return bEn;
}

VOID Hv_Cal_MPRT_PwmSetMode(USHORT16 usPwmPort, USHORT16 usMode)
{
    switch (usPwmPort)
    {
        case 0:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode0, usMode);
            break;
        case 1:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode1, usMode);
            break;
        case 2:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode2, usMode);
            break;
        case 3:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode3, usMode);
            break;
        case 4:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode4, usMode);
            break;
        case 5:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode5, usMode);
            break;
        case 6:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode6, usMode);
            break;
        case 7:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode7, usMode);
            break;
        default:
            HV_W32_FIELD(TX_HSTX_TOP_20, reg_mprt_pwm_mode0, usMode);
    }
    return;
}

VOID Hv_Cal_MPRT_PwmSetStart(USHORT16 usPwmPort, USHORT16 usStart)
{
    switch (usPwmPort)
    {
        case 0:
            HV_W32_FIELD(TX_HSTX_TOP_24, reg_mprt_pwm_sta0, usStart);
            break;
        case 1:
            HV_W32_FIELD(TX_HSTX_TOP_24, reg_mprt_pwm_sta1, usStart);
            break;
        case 2:
            HV_W32_FIELD(TX_HSTX_TOP_28, reg_mprt_pwm_sta2, usStart);
            break;
        case 3:
            HV_W32_FIELD(TX_HSTX_TOP_28, reg_mprt_pwm_sta3, usStart);
            break;
        case 4:
            HV_W32_FIELD(TX_HSTX_TOP_2C, reg_mprt_pwm_sta4, usStart);
            break;
        case 5:
            HV_W32_FIELD(TX_HSTX_TOP_2C, reg_mprt_pwm_sta5, usStart);
            break;
        case 6:
            HV_W32_FIELD(TX_HSTX_TOP_30, reg_mprt_pwm_sta6, usStart);
            break;
        case 7:
            HV_W32_FIELD(TX_HSTX_TOP_30, reg_mprt_pwm_sta7, usStart);
            break;
        default:
            HV_W32_FIELD(TX_HSTX_TOP_24, reg_mprt_pwm_sta0, usStart);
    }
    return;
}

VOID Hv_Cal_MPRT_PwmSetValue(USHORT16 usPwmPort, USHORT16 usVale)
{
    switch (usPwmPort)
    {
        case 0:
            HV_W32_FIELD(TX_HSTX_TOP_34, reg_mprt_pwm_val0, usVale);
            break;
        case 1:
            HV_W32_FIELD(TX_HSTX_TOP_34, reg_mprt_pwm_val1, usVale);
            break;
        case 2:
            HV_W32_FIELD(TX_HSTX_TOP_38, reg_mprt_pwm_val2, usVale);
            break;
        case 3:
            HV_W32_FIELD(TX_HSTX_TOP_38, reg_mprt_pwm_val3, usVale);
            break;
        case 4:
            HV_W32_FIELD(TX_HSTX_TOP_3C, reg_mprt_pwm_val4, usVale);
            break;
        case 5:
            HV_W32_FIELD(TX_HSTX_TOP_3C, reg_mprt_pwm_val5, usVale);
            break;
        case 6:
            HV_W32_FIELD(TX_HSTX_TOP_40, reg_mprt_pwm_val6, usVale);
            break;
        case 7:
            HV_W32_FIELD(TX_HSTX_TOP_40, reg_mprt_pwm_val7, usVale);
            break;
        default:
            HV_W32_FIELD(TX_HSTX_TOP_34, reg_mprt_pwm_val0, usVale);
    }
    return;
}

VOID Hv_Cal_MPRT_PwmSetMult(USHORT16 usPwmPort, USHORT16 usMult)
{
    switch (usPwmPort)
    {
        case 0:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult0, usMult);
            break;
        case 1:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult1, usMult);
            break;
        case 2:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult2, usMult);
            break;
        case 3:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult3, usMult);
            break;
        case 4:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult4, usMult);
            break;
        case 5:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult5, usMult);
            break;
        case 6:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult6, usMult);
            break;
        case 7:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult7, usMult);
            break;
        default:
            HV_W32_FIELD(TX_HSTX_TOP_44, reg_mprt_pwm_mult0, usMult);
    }
    return;
}

VOID Hv_Cal_MPRT_PwmSetPol(USHORT16 usPwmPort, UCHAR8 ucPol)
{
    UCHAR8 ucReadPol = 0;
    HV_R32_DECL_VAR();
    ucReadPol = (UCHAR8) HV_R32_FIELD(TX_HSTX_TOP_18, reg_pwm_pol);
    ucReadPol = ucReadPol | (ucPol << usPwmPort);
    HV_W32_FIELD(TX_HSTX_TOP_18, reg_pwm_pol, ucReadPol);
    return;
}

VOID Hv_Cal_MPRT_PwmSetMux(USHORT16 usPwmPort, UCHAR8 ucMux)
{
    switch (usPwmPort)
    {
        case 0:
            HV_W32_FIELD(TX_HSTX_TOP_4C, reg_mprt_pwm_mux0, ucMux);
            break;
        case 1:
            HV_W32_FIELD(TX_HSTX_TOP_4C, reg_mprt_pwm_mux1, ucMux);
            break;
        case 2:
            HV_W32_FIELD(TX_HSTX_TOP_4C, reg_mprt_pwm_mux2, ucMux);
            break;
        case 3:
            HV_W32_FIELD(TX_HSTX_TOP_4C, reg_mprt_pwm_mux3, ucMux);
            break;
        case 4:
            HV_W32_FIELD(TX_HSTX_TOP_50, reg_mprt_pwm_mux4, ucMux);
            break;
        case 5:
            HV_W32_FIELD(TX_HSTX_TOP_50, reg_mprt_pwm_mux5, ucMux);
            break;
        case 6:
            HV_W32_FIELD(TX_HSTX_TOP_50, reg_mprt_pwm_mux6, ucMux);
            break;
        case 7:
            HV_W32_FIELD(TX_HSTX_TOP_50, reg_mprt_pwm_mux7, ucMux);
            break;
        default:
            HV_W32_FIELD(TX_HSTX_TOP_4C, reg_mprt_pwm_mux0, ucMux);
    }
    return;
}

VOID Hv_Cal_MPRT_SetMprtSource(UCHAR8 ucSource)
{
    HV_W32_FIELD(TX_HSTX_TOP_00, reg_hstx_dbg_sel, ucSource);
    return;
}

VOID Hv_Cal_MPRT_SetMprtVsClear(UCHAR8 ucPort)
{
    HV_W32_FIELD(TX_HSTX_TOP_04, reg_mprt_pwm_vs_clr, ucPort);
    return;
}

VOID Hv_Cal_MPRT_SetMprtStaVrrEn(UCHAR8 ucPort)
{
    HV_W32_FIELD(TX_HSTX_TOP_04, reg_mprt_pwm_sta_vrr, ucPort);
    return;
}

VOID Hv_Cal_MPRT_SetLdcVsync(UCHAR8 ucPort)
{
    HV_W32_FIELD(TX_HSTX_TOP_04, reg_mprt_pwm_edge_mux, 1 << ucPort);
    Hv_Cal_MPRT_PwmSetMode(ucPort, 4);
    Hv_Cal_MPRT_PwmEnable(ucPort, 1);
}

#if 0
VOID Hv_Cal_MPRT_SPI_CleanMprtVsInt(VOID)
{
    HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_28, reg_ldg_int_clr, 0x4);
    HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_28, reg_ldg_int_clr, 0);
    return;
}

VOID Hv_Cal_MPRT_SPI_SetMprtVsIntMode(UINT32 uiIntMode)
{
    HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_28, reg_ldg_int_mode, uiIntMode);
    return;
}

VOID Hv_Cal_MPRT_SPI_EnableMprtVsInt(BOOL bEn)
{
    HV_W32_FIELD(DISP_TOP_DPU_LDG_DPC_28, reg_ldg_int_en, bEn << 2);
    return;
}

VOID Hv_Cal_MPRT_PwmSetPtgSel()
{
    /* PTG_POL for MPRT_PWM_VSYNC */
    HV_W32_FIELD(TX_PIF_TX_TOP_PTG_POL_SEL_0, reg_ptg_pol5_sel, 5);
    /* PTG_POL for MPRT_PWM_HSYNC */
    HV_W32_FIELD(TX_PIF_TX_TOP_PTG_POL_SEL_1, reg_ptg_pol6_sel, 6);
    return;
}

VOID Hv_Cal_MPRT_FrameRateDectIntInit()
{
    /*防止一直报中断，需要调节一个rate_diff值*/
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_34, reg_frame_rate_diff, 11);
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_38, reg_frame_rate_greater, 1);
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_38, reg_frame_rate_less, 1);

    HV_W32_FIELD(TX_FRAME_RATE_DET_1_20, reg_int_level_p, 1);
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_08, reg_frame_rate_det_en, 1);
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_20, reg_int_clr, 1);
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_20, reg_int_clr, 0);

    return;
}

VOID Hv_Cal_MPRT_ClearFrameRateDectInt()
{
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_20, reg_int_clr, 1);
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_20, reg_int_clr, 0);
    return;
}

VOID Hv_Cal_MPRT_FrameRateDectIntEn(BOOL bEn)
{
    HV_W32_FIELD(TX_FRAME_RATE_DET_1_20, reg_int_en, bEn);
    return;
}

USHORT16 Hv_Cal_MPRT_GetRXVToal()
{
    HV_R32_DECL_VAR();
    return (USHORT16) HV_R32_FIELD(DISP_TOP_DTC_TOP_D4, regr_tx_vtotal);
}

USHORT16 Hv_Cal_MPRT_GetMprtPwmVal(USHORT16 usPwmPort)
{
    USHORT16 usVal;
    HV_R32_DECL_VAR();
    switch (usPwmPort)
    {
        case 0:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_34, reg_mprt_pwm_val0);
            break;
        case 1:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_34, reg_mprt_pwm_val1);
            break;
        case 2:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_38, reg_mprt_pwm_val2);
            break;
        case 3:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_38, reg_mprt_pwm_val3);
            break;
        case 4:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_3C, reg_mprt_pwm_val4);
            break;
        case 5:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_3C, reg_mprt_pwm_val5);
            break;
        case 6:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_40, reg_mprt_pwm_val6);
            break;
        case 7:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_40, reg_mprt_pwm_val7);
            break;
        default:
            usVal = (USHORT16) HV_R32_FIELD(TX_HSTX_TOP_34, reg_mprt_pwm_val0);
    }
    return usVal;
}

VOID Hv_Cal_MPRT_SetPTGReg()
{
    HV_W32_FIELD(TX_KTX_PTG_00_00, reg_00_ktx_ptg0_base0_frm_timer, 100);
    HV_W32_FIELD(TX_KTX_PTG_00_04, reg_00_ktx_ptg0_base0_frm_patt, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_08, reg_00_ktx_ptg0_base0_frm_cnt_enable, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_08, reg_00_ktx_ptg0_base0_frm_patt_type, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_08, reg_00_ktx_ptg0_base0_lc_flag_en, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_08, reg_00_ktx_ptg0_base1_frm_cnt_enable, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_08, reg_00_ktx_ptg0_base1_frm_patt_type, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_08, reg_00_ktx_ptg0_base1_lc_flag_en, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_0C, reg_00_ktx_ptg0_base1_frm_timer, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_0C, reg_00_ktx_ptg0_base1_frm_limited_width, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_10, reg_00_ktx_ptg0_base1_frm_patt, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_14, reg_00_ktx_ptg0_u0_1st_start_line_l, 2);
    HV_W32_FIELD(TX_KTX_PTG_00_14, reg_00_ktx_ptg0_u0_1st_end_line_l, 5);
    HV_W32_FIELD(TX_KTX_PTG_00_14, reg_00_ktx_ptg0_u0_1st_patt_type, 3);
    HV_W32_FIELD(TX_KTX_PTG_00_18, reg_00_ktx_ptg0_u0_1st_h_rp, 363);
    HV_W32_FIELD(TX_KTX_PTG_00_20, reg_00_ktx_ptg0_u0_1st_rp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_20, reg_00_ktx_ptg0_u0_1st_fp_patt_l, 8);
    HV_W32_FIELD(TX_KTX_PTG_00_24, reg_00_ktx_ptg0_u1_1st_start_line_l, 5);
    HV_W32_FIELD(TX_KTX_PTG_00_24, reg_00_ktx_ptg0_u1_1st_end_line_l, 2180);
    HV_W32_FIELD(TX_KTX_PTG_00_28, reg_00_ktx_ptg0_u1_1st_h_fp, 857);
    HV_W32_FIELD(TX_KTX_PTG_00_30, reg_00_ktx_ptg0_u1_1st_rp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_30, reg_00_ktx_ptg0_u1_1st_fp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_38, reg_00_ktx_ptg0_u2_unit_mode, 15);
    HV_W32_FIELD(TX_KTX_PTG_00_3C, reg_00_ktx_ptg0_u2_frm_sel, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_44, reg_00_ktx_ptg0_u3_1st_start_line_l, 2181);
    HV_W32_FIELD(TX_KTX_PTG_00_44, reg_00_ktx_ptg0_u3_1st_end_line_l, 2181);
    HV_W32_FIELD(TX_KTX_PTG_00_48, reg_00_ktx_ptg0_u3_1st_h_fp, 200);
    HV_W32_FIELD(TX_KTX_PTG_00_4C, reg_00_ktx_ptg0_u3_frm_sel, 2);
    HV_W32_FIELD(TX_KTX_PTG_00_50, reg_00_ktx_ptg0_u3_1st_rp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_50, reg_00_ktx_ptg0_u3_1st_fp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_58, reg_00_ktx_ptg0_u4_unit_mode, 15);
    HV_W32_FIELD(TX_KTX_PTG_00_58, reg_00_ktx_ptg0_u4_1st_h_fp, 1936);
    HV_W32_FIELD(TX_KTX_PTG_00_5C, reg_00_ktx_ptg0_u4_frm_sel, 2);
    HV_W32_FIELD(TX_KTX_PTG_00_60, reg_00_ktx_ptg0_u4_1st_rp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_60, reg_00_ktx_ptg0_u4_1st_fp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_64, reg_00_ktx_ptg0_u5_1st_start_line_l, 10);
    HV_W32_FIELD(TX_KTX_PTG_00_64, reg_00_ktx_ptg0_u5_1st_end_line_l, 16);
    HV_W32_FIELD(TX_KTX_PTG_00_64, reg_00_ktx_ptg0_u5_1st_patt_type, 6);
    HV_W32_FIELD(TX_KTX_PTG_00_68, reg_00_ktx_ptg0_u5_1st_h_rp, 140);
    HV_W32_FIELD(TX_KTX_PTG_00_68, reg_00_ktx_ptg0_u5_1st_h_fp, 520);
    HV_W32_FIELD(TX_KTX_PTG_00_70, reg_00_ktx_ptg0_u5_1st_rp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_70, reg_00_ktx_ptg0_u5_1st_fp_patt_l, 64);
    HV_W32_FIELD(TX_KTX_PTG_00_74, reg_00_ktx_ptg0_u6_1st_end_line_l, 8191);
    HV_W32_FIELD(TX_KTX_PTG_00_78, reg_00_ktx_ptg0_u6_1st_h_rp, 140);
    HV_W32_FIELD(TX_KTX_PTG_00_78, reg_00_ktx_ptg0_u6_1st_h_fp, 520);
    HV_W32_FIELD(TX_KTX_PTG_00_80, reg_00_ktx_ptg0_u6_1st_rp_patt_l, 1);
    HV_W32_FIELD(TX_KTX_PTG_00_80, reg_00_ktx_ptg0_u6_1st_fp_patt_l, 1);
    return;
}


// TODO: 根据实际使用的pin脚设置pin share
VOID Hv_Cal_MPRT_SetMprtPinShare()
{
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio10_func_sel, 5);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio11_func_sel, 5);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio12_func_sel, 5);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio13_func_sel, 6);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio14_func_sel, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio15_func_sel, 6);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio16_func_sel, 7);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio17_func_sel, 7);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_0, reg_gpio18_func_sel, 5);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_10, reg_gpio13_ptg_sel, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_10, reg_gpio14_ptg_sel, 2);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_10, reg_gpio15_ptg_sel, 3);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_14, reg_gpio16_ptg_sel, 4);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_14, reg_gpio17_ptg_sel, 5);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_14, reg_gpio18_ptg_sel, 8);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_1C, reg_gpio10_io_ctrl, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_1C, reg_gpio11_io_ctrl, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_1C, reg_gpio12_io_ctrl, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_1C, reg_gpio13_io_ctrl, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_20, reg_gpio14_io_ctrl, 7);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_20, reg_gpio15_io_ctrl, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_20, reg_gpio16_io_ctrl, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_20, reg_gpio17_io_ctrl, 1);
    HV_W32_FIELD(SYS_SH08_TOP_TX_CTRL_24, reg_gpio18_io_ctrl, 11);

    return;
}
#endif
