#ifndef _HV_PAGE_HT7315_HDMI21_RX_POST_0_PROC_00_H_
#define _HV_PAGE_HT7315_HDMI21_RX_POST_0_PROC_00_H_

#ifndef HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS
    #define HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS                                         0x1104D400
#endif


#define RX_HDMI21_RX_POST_0_PROC_00_00                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX_POST_0_PROC_00_00_struct                            rs_rx_hdmi21_rx_post_0_proc_00_00

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_00  rs_rx_hdmi21_rx_post_0_proc_00_00;
struct _rs_rx_hdmi21_rx_post_0_proc_00_00 {
    unsigned int reg_00_ctrl_preamble_th                    : 3;
    unsigned int reg_00_remove_lgb                          : 1;
    unsigned int reg_00_remove_tgb                          : 1;
    unsigned int reg_00_poladi_vsync_cnt_clear              : 1;
    unsigned int reg_00_poladj_vsync_cnt_thr                : 8;
    unsigned int reg_00_poladj_vs_pol_adj_mode              : 2;
    unsigned int reg_00_poladj_hs_pol_adj_mode              : 2;
    unsigned int reg_00_tmds_vs_pol_inv                     : 1;
    unsigned int reg_00_tmds_hs_pol_inv                     : 1;
    unsigned int reg_00_hdcp_bypass                         : 1;
    unsigned int reg_00_dvi_mode_sel                        : 1;
    unsigned int reg_00_dvi_mode_set                        : 1;
    unsigned int reg_00_mr_detect_value_clr                 : 1;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_post_0_proc_00_00(val) ((rs_rx_hdmi21_rx_post_0_proc_00_00*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_04                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX_POST_0_PROC_00_04_struct                            rs_rx_hdmi21_rx_post_0_proc_00_04

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_04  rs_rx_hdmi21_rx_post_0_proc_00_04;
struct _rs_rx_hdmi21_rx_post_0_proc_00_04 {
    unsigned int reg_00_pkt_dec_error_correct               : 1;
    unsigned int reg_00_pkt_dec_corrected_error_discard     : 1;
    unsigned int reg_00_pkt_dec_uncorrected_error_discard   : 1;
    unsigned int reg_00_pkt_dec_error_cnt_clr               : 1;
    unsigned int reg_00_audio_pkt_error_codeins_en          : 1;
    unsigned int reg_00_audio_pkt_error_ins_code            : 8;
    unsigned int reg_00_pkt_checksum_err_filter             : 1;
    unsigned int reg_00_pkt_err_filter                      : 1;
    unsigned int reg_00_pkt_acrp_err_filter                 : 1;
    unsigned int reg_00_pkt_gcp_err_filter                  : 1;
    unsigned int reg_00_pkt_vsi_err_filter                  : 1;
    unsigned int reg_00_pkt_avi_err_filter                  : 1;
    unsigned int reg_00_pkt_aif_err_filter                  : 1;
    unsigned int reg_00_pkt_gmd_err_filter                  : 1;
    unsigned int reg_00_pkt_isrc_err_filter                 : 1;
    unsigned int reg_00_pkt_ntscvbi_err_filter              : 1;
    unsigned int reg_00_pkt_drm_err_filter                  : 1;
    unsigned int reg_00_pkt_amp_err_filter                  : 1;
    unsigned int reg_00_pkt_emp_err_filter                  : 1;
    unsigned int reg_00_pkt_spd_err_filter                  : 1;
    unsigned int reg_00_pkt_mpeg_err_filter                 : 1;
    unsigned int reserved                                   : 4;
};
#define rx_hdmi21_rx_post_0_proc_00_04(val) ((rs_rx_hdmi21_rx_post_0_proc_00_04*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_08                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX_POST_0_PROC_00_08_struct                            rs_rx_hdmi21_rx_post_0_proc_00_08

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_08  rs_rx_hdmi21_rx_post_0_proc_00_08;
struct _rs_rx_hdmi21_rx_post_0_proc_00_08 {
    unsigned int reg_00_audio_pao_rate                      : 2;
    unsigned int reg_00_audio_pao_disable                   : 1;
    unsigned int reg_00_audio_afif_init                     : 1;
    unsigned int reg_00_audio_afif_th_start                 : 9;
    unsigned int reg_00_audio_afif_th_min                   : 9;
    unsigned int reg_00_audio_afif_th_max                   : 9;
    unsigned int reg_00_audio_pao_mute_en                   : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_08(val) ((rs_rx_hdmi21_rx_post_0_proc_00_08*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_0C                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x0C)

#define RX_HDMI21_RX_POST_0_PROC_00_0C_struct                            rs_rx_hdmi21_rx_post_0_proc_00_0c

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_0c  rs_rx_hdmi21_rx_post_0_proc_00_0c;
struct _rs_rx_hdmi21_rx_post_0_proc_00_0c {
    unsigned int reg_00_audio_afif_subpacket_desel          : 4;
    unsigned int reg_00_audio_afif_subpackets               : 1;
    unsigned int reg_00_audio_layout_ctrl                   : 2;
    unsigned int reg_00_audio_mute_mode                     : 2;
    unsigned int reg_00_audio_mute_sel                      : 2;
    unsigned int reg_00_audio_mute_speed                    : 7;
    unsigned int reg_00_audio_auto_aclk_mute                : 2;
    unsigned int reg_00_audio_auto_spflat_mute              : 4;
    unsigned int reg_00_audio_ch_map                        : 8;
};
#define rx_hdmi21_rx_post_0_proc_00_0c(val) ((rs_rx_hdmi21_rx_post_0_proc_00_0c*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_10                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x10)

#define RX_HDMI21_RX_POST_0_PROC_00_10_struct                            rs_rx_hdmi21_rx_post_0_proc_00_10

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_10  rs_rx_hdmi21_rx_post_0_proc_00_10;
struct _rs_rx_hdmi21_rx_post_0_proc_00_10 {
    unsigned int reg_00_audio_ch_map_manual                 : 1;
    unsigned int reg_00_audio_ws_disable                    : 1;
    unsigned int reg_00_audio_i2s_lpcm_bpcuv                : 1;
    unsigned int reg_00_audio_spdif_disable                 : 4;
    unsigned int reg_00_audio_i2s_disable                   : 4;
    unsigned int reg_00_audio_i2s_32_16                     : 1;
    unsigned int reg_00_audio_sck_disable                   : 1;
    unsigned int reg_00_audio_apply_int_mute                : 1;
    unsigned int reg_00_audio_aport_shdw_ctrl               : 2;
    unsigned int reg_00_audio_fmt_sel                       : 1;
    unsigned int reg_00_audio_fmt                           : 3;
    unsigned int reg_00_audio_itesttone_en                  : 1;
    unsigned int reg_00_audio_hbr_mode                      : 1;
    unsigned int reg_00_audio_pll_lock_filter_byp           : 1;
    unsigned int reg_00_audio_pll_lock_toggle_div           : 4;
    unsigned int reg_00_audio_afifo_clear_fill              : 1;
    unsigned int reg_00_audio_avmute_en                     : 1;
    unsigned int reg_00_audio_fc_lfe_exchg                  : 1;
    unsigned int reg_00_audio_pll_cts_n_ref                 : 1;
    unsigned int reg_00_audio_mute_out_en                   : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_10(val) ((rs_rx_hdmi21_rx_post_0_proc_00_10*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_14                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x14)

#define RX_HDMI21_RX_POST_0_PROC_00_14_struct                            rs_rx_hdmi21_rx_post_0_proc_00_14

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_14  rs_rx_hdmi21_rx_post_0_proc_00_14;
struct _rs_rx_hdmi21_rx_post_0_proc_00_14 {
    unsigned int reg_00_audio_pll_cts_manual                :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_post_0_proc_00_14(val) ((rs_rx_hdmi21_rx_post_0_proc_00_14*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_18                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX_POST_0_PROC_00_18_struct                            rs_rx_hdmi21_rx_post_0_proc_00_18

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_18  rs_rx_hdmi21_rx_post_0_proc_00_18;
struct _rs_rx_hdmi21_rx_post_0_proc_00_18 {
    unsigned int reg_00_audio_pll_n_manual                  :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_post_0_proc_00_18(val) ((rs_rx_hdmi21_rx_post_0_proc_00_18*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_1C                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX_POST_0_PROC_00_1C_struct                            rs_rx_hdmi21_rx_post_0_proc_00_1c

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_1c  rs_rx_hdmi21_rx_post_0_proc_00_1c;
struct _rs_rx_hdmi21_rx_post_0_proc_00_1c {
    unsigned int reg_00_hd21rx_vid_colordepth               : 4;
    unsigned int reg_00_hd21rx_gcp_zero_vid_fields          : 4;
    unsigned int reg_00_hd21rx_pixel_phase                  : 4;
    unsigned int reg_00_hd21rx_pixel_default_phase          : 1;
    unsigned int reg_00_hd21rx_dc_operation                 : 2;
    unsigned int reg_00_hd21rx_vm_enable                    : 1;
    unsigned int reg_00_hd21rx_ph_diff_cnt_clr              : 1;
    unsigned int reg_00_hd21rx_video_fmt                    : 3;
    unsigned int reg_00_hd21rx_vid_colordepth_sel           : 1;
    unsigned int reg_00_hd21rx_pixel_phase_sel              : 1;
    unsigned int reg_00_hd21rx_video_fmt_sel                : 1;
    unsigned int reg_00_hd21rx_auto_vmute                   : 1;
    unsigned int reg_00_hd21rx_ph_diff_cnt_thres            : 8;
};
#define rx_hdmi21_rx_post_0_proc_00_1c(val) ((rs_rx_hdmi21_rx_post_0_proc_00_1c*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_20                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x20)

#define RX_HDMI21_RX_POST_0_PROC_00_20_struct                            rs_rx_hdmi21_rx_post_0_proc_00_20

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_20  rs_rx_hdmi21_rx_post_0_proc_00_20;
struct _rs_rx_hdmi21_rx_post_0_proc_00_20 {
    unsigned int reg_00_hd21rx_mute_value_r                 :16;
    unsigned int reg_00_hd21rx_mute_value_g                 :16;
};
#define rx_hdmi21_rx_post_0_proc_00_20(val) ((rs_rx_hdmi21_rx_post_0_proc_00_20*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_24                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x24)

#define RX_HDMI21_RX_POST_0_PROC_00_24_struct                            rs_rx_hdmi21_rx_post_0_proc_00_24

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_24  rs_rx_hdmi21_rx_post_0_proc_00_24;
struct _rs_rx_hdmi21_rx_post_0_proc_00_24 {
    unsigned int reg_00_hd21rx_mute_value_b                 :16;
    unsigned int reg_00_hd21rx_tmds4p_frm_trig_pos          :16;
};
#define rx_hdmi21_rx_post_0_proc_00_24(val) ((rs_rx_hdmi21_rx_post_0_proc_00_24*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_28                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x28)

#define RX_HDMI21_RX_POST_0_PROC_00_28_struct                            rs_rx_hdmi21_rx_post_0_proc_00_28

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_28  rs_rx_hdmi21_rx_post_0_proc_00_28;
struct _rs_rx_hdmi21_rx_post_0_proc_00_28 {
    unsigned int reg_00_hd21rx_pixelmode                    : 1;
    unsigned int reg_00_hd21rx_pvo1unmute                   : 1;
    unsigned int reg_00_hd21rx_4port_en                     : 1;
    unsigned int reg_00_hd21rx_pvoremap_clear               : 1;
    unsigned int reg_00_hd21rx_vid_afifo_en                 : 1;
    unsigned int reg_00_hd21rx_vid_afifo_vs_clr_en          : 1;
    unsigned int reg_00_hd21rx_use_hs_vs                    : 1;
    unsigned int reg_00_pixel_repeat_sel                    : 1;
    unsigned int reg_00_pixel_repeat_factor                 : 4;
    unsigned int reg_00_video_field_sel                     : 1;
    unsigned int reg_00_video_field_patt_clr                : 1;
    unsigned int reg_00_video_field_patt                    : 2;
    unsigned int reg_00_hd21rx_regen_de_pos_sel             : 1;
    unsigned int reg_00_hd21rx_regen_de_dly                 :13;
    unsigned int reg_00_video_field_inv                     : 1;
    unsigned int reg_00_hd21rx_keep_dc_redundant_pix        : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_28(val) ((rs_rx_hdmi21_rx_post_0_proc_00_28*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_2C                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x2C)

#define RX_HDMI21_RX_POST_0_PROC_00_2C_struct                            rs_rx_hdmi21_rx_post_0_proc_00_2c

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_2c  rs_rx_hdmi21_rx_post_0_proc_00_2c;
struct _rs_rx_hdmi21_rx_post_0_proc_00_2c {
    unsigned int reg_00_hd21rx_regen_de_sel                 : 1;
    unsigned int reg_00_hd21rx_regen_hs_sel                 : 1;
    unsigned int reg_00_hd21rx_regen_vs_sel                 : 1;
    unsigned int reg_00_hd21rx_regen_hact                   :14;
    unsigned int reg_00_hd21rx_regen_vact                   :14;
    unsigned int reg_00_video_interlaced_det_th             : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_2c(val) ((rs_rx_hdmi21_rx_post_0_proc_00_2c*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_30                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x30)

#define RX_HDMI21_RX_POST_0_PROC_00_30_struct                            rs_rx_hdmi21_rx_post_0_proc_00_30

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_30  rs_rx_hdmi21_rx_post_0_proc_00_30;
struct _rs_rx_hdmi21_rx_post_0_proc_00_30 {
    unsigned int reg_00_hd21rx_regen_hs_pos                 :10;
    unsigned int reg_00_hd21rx_regen_hs_width               :10;
    unsigned int reg_00_hd21rx_vid_afifo_wr2rd_th           : 3;
    unsigned int reg_00_hd21rx_tmds_timing_chg_mode         : 5;
    unsigned int reserved                                   : 4;
};
#define rx_hdmi21_rx_post_0_proc_00_30(val) ((rs_rx_hdmi21_rx_post_0_proc_00_30*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_34                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX_POST_0_PROC_00_34_struct                            rs_rx_hdmi21_rx_post_0_proc_00_34

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_34  rs_rx_hdmi21_rx_post_0_proc_00_34;
struct _rs_rx_hdmi21_rx_post_0_proc_00_34 {
    unsigned int reg_00_hd21rx_regen_frm_trig_pos           :16;
    unsigned int reg_00_hd21rx_fmt420_regen_de_pos          :12;
    unsigned int reg_00_hd21rx_fmt420_regen_vact_sel        : 1;
    unsigned int reg_00_hd21rx_video_remap_mode             : 1;
    unsigned int reserved                                   : 2;
};
#define rx_hdmi21_rx_post_0_proc_00_34(val) ((rs_rx_hdmi21_rx_post_0_proc_00_34*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_38                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX_POST_0_PROC_00_38_struct                            rs_rx_hdmi21_rx_post_0_proc_00_38

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_38  rs_rx_hdmi21_rx_post_0_proc_00_38;
struct _rs_rx_hdmi21_rx_post_0_proc_00_38 {
    unsigned int reg_00_clk_det_win                         :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_post_0_proc_00_38(val) ((rs_rx_hdmi21_rx_post_0_proc_00_38*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_3C                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX_POST_0_PROC_00_3C_struct                            rs_rx_hdmi21_rx_post_0_proc_00_3c

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_3c  rs_rx_hdmi21_rx_post_0_proc_00_3c;
struct _rs_rx_hdmi21_rx_post_0_proc_00_3c {
    unsigned int reg_00_clk_det_low                         :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_post_0_proc_00_3c(val) ((rs_rx_hdmi21_rx_post_0_proc_00_3c*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_40                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x40)

#define RX_HDMI21_RX_POST_0_PROC_00_40_struct                            rs_rx_hdmi21_rx_post_0_proc_00_40

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_40  rs_rx_hdmi21_rx_post_0_proc_00_40;
struct _rs_rx_hdmi21_rx_post_0_proc_00_40 {
    unsigned int reg_00_clk_det_high                        :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_post_0_proc_00_40(val) ((rs_rx_hdmi21_rx_post_0_proc_00_40*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_48                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x48)

#define RX_HDMI21_RX_POST_0_PROC_00_48_struct                            rs_rx_hdmi21_rx_post_0_proc_00_48

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_48  rs_rx_hdmi21_rx_post_0_proc_00_48;
struct _rs_rx_hdmi21_rx_post_0_proc_00_48 {
    unsigned int reg_00_clk_det_delta                       :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_post_0_proc_00_48(val) ((rs_rx_hdmi21_rx_post_0_proc_00_48*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_4C                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x4C)

#define RX_HDMI21_RX_POST_0_PROC_00_4C_struct                            rs_rx_hdmi21_rx_post_0_proc_00_4c

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_4c  rs_rx_hdmi21_rx_post_0_proc_00_4c;
struct _rs_rx_hdmi21_rx_post_0_proc_00_4c {
    unsigned int reg_00_pkt_error_int_mode                  : 1;
    unsigned int reg_00_pkt_error_int_cnt_clr               : 1;
    unsigned int reg_00_pkt_error_int_set_th                :16;
    unsigned int reg_00_pkt_error_int_clr_th                :14;
};
#define rx_hdmi21_rx_post_0_proc_00_4c(val) ((rs_rx_hdmi21_rx_post_0_proc_00_4c*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_50                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x50)

#define RX_HDMI21_RX_POST_0_PROC_00_50_struct                            rs_rx_hdmi21_rx_post_0_proc_00_50

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_50  rs_rx_hdmi21_rx_post_0_proc_00_50;
struct _rs_rx_hdmi21_rx_post_0_proc_00_50 {
    unsigned int reg_00_dvi_mode_det_th                     :16;
    unsigned int reg_00_hd21rx_regen_htotal_min_value       :14;
    unsigned int reg_00_hd21rx_regen_htotal_min_en          : 1;
    unsigned int reg_00_hd21rx_regen_htotal_min_flag_clr    : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_50(val) ((rs_rx_hdmi21_rx_post_0_proc_00_50*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_54                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x54)

#define RX_HDMI21_RX_POST_0_PROC_00_54_struct                            rs_rx_hdmi21_rx_post_0_proc_00_54

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_54  rs_rx_hdmi21_rx_post_0_proc_00_54;
struct _rs_rx_hdmi21_rx_post_0_proc_00_54 {
    unsigned int reg_00_hd21rx_regen_de_filter              :14;
    unsigned int reg_00_hd21rx_tmds_timing_stable_mode      : 5;
    unsigned int reg_00_hd21rx_tmds_timing_stable_th        : 4;
    unsigned int reserved                                   : 9;
};
#define rx_hdmi21_rx_post_0_proc_00_54(val) ((rs_rx_hdmi21_rx_post_0_proc_00_54*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_58                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x58)

#define RX_HDMI21_RX_POST_0_PROC_00_58_struct                            rs_rx_hdmi21_rx_post_0_proc_00_58

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_58  rs_rx_hdmi21_rx_post_0_proc_00_58;
struct _rs_rx_hdmi21_rx_post_0_proc_00_58 {
    unsigned int reg_00_hd21rx_frame_rate_chg_th            :24;
    unsigned int reg_00_hd21rx_h_timing_chg_th              : 4;
    unsigned int reg_00_hd21rx_v_timing_chg_th              : 4;
};
#define rx_hdmi21_rx_post_0_proc_00_58(val) ((rs_rx_hdmi21_rx_post_0_proc_00_58*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_5C                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0x5C)

#define RX_HDMI21_RX_POST_0_PROC_00_5C_struct                            rs_rx_hdmi21_rx_post_0_proc_00_5c

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_5c  rs_rx_hdmi21_rx_post_0_proc_00_5c;
struct _rs_rx_hdmi21_rx_post_0_proc_00_5c {
    unsigned int reg_00_pkt_error_mute_set_th               : 8;
    unsigned int reg_00_pkt_error_mute_clr_th               : 8;
    unsigned int reg_00_pkt_error_mute_en                   : 1;
    unsigned int reserved                                   :15;
};
#define rx_hdmi21_rx_post_0_proc_00_5c(val) ((rs_rx_hdmi21_rx_post_0_proc_00_5c*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_A4                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xA4)

#define RX_HDMI21_RX_POST_0_PROC_00_A4_struct                            rs_rx_hdmi21_rx_post_0_proc_00_a4

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_a4  rs_rx_hdmi21_rx_post_0_proc_00_a4;
struct _rs_rx_hdmi21_rx_post_0_proc_00_a4 {
    unsigned int regr_00_pkt_dec_error_cnt                  :16;
    unsigned int regr_00_pkt_dec_uncorrected_cnt            :16;
};
#define rx_hdmi21_rx_post_0_proc_00_a4(val) ((rs_rx_hdmi21_rx_post_0_proc_00_a4*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_A8                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xA8)

#define RX_HDMI21_RX_POST_0_PROC_00_A8_struct                            rs_rx_hdmi21_rx_post_0_proc_00_a8

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_a8  rs_rx_hdmi21_rx_post_0_proc_00_a8;
struct _rs_rx_hdmi21_rx_post_0_proc_00_a8 {
    unsigned int regr_00_hd21rx_frame_rate                  :24;
    unsigned int regr_00_hd21rx_no_timing                   : 1;
    unsigned int regr_00_hd21rx_tmds_timing_chg             : 1;
    unsigned int regr_00_hd21rx_tmds_timing_stable          : 1;
    unsigned int regr_00_mute_pkt_error                     : 1;
    unsigned int regr_00_int_pkt_error                      : 1;
    unsigned int reserved                                   : 3;
};
#define rx_hdmi21_rx_post_0_proc_00_a8(val) ((rs_rx_hdmi21_rx_post_0_proc_00_a8*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_AC                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xAC)

#define RX_HDMI21_RX_POST_0_PROC_00_AC_struct                            rs_rx_hdmi21_rx_post_0_proc_00_ac

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_ac  rs_rx_hdmi21_rx_post_0_proc_00_ac;
struct _rs_rx_hdmi21_rx_post_0_proc_00_ac {
    unsigned int regr_00_pkt_error_int_set_cnt              :16;
    unsigned int regr_00_pkt_error_int_clr_cnt              :16;
};
#define rx_hdmi21_rx_post_0_proc_00_ac(val) ((rs_rx_hdmi21_rx_post_0_proc_00_ac*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_B0                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xB0)

#define RX_HDMI21_RX_POST_0_PROC_00_B0_struct                            rs_rx_hdmi21_rx_post_0_proc_00_b0

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_b0  rs_rx_hdmi21_rx_post_0_proc_00_b0;
struct _rs_rx_hdmi21_rx_post_0_proc_00_b0 {
    unsigned int regr_00_hd21rx_dcm_phase_diff_cnt          : 8;
    unsigned int regr_00_hd21rx_dcm_last_pixel_phase_sts    : 4;
    unsigned int regr_00_hd21rx_dcm_current_mode            : 4;
    unsigned int regr_00_hd21rx_dcm_current_pp              : 4;
    unsigned int regr_00_hd21rx_ph_diff_cnt_overfl          : 1;
    unsigned int regr_00_hd21rx_dcm_gcp_zero_fields_pass    : 1;
    unsigned int regr_00_hd21rx_dc_change                   : 1;
    unsigned int reserved                                   : 9;
};
#define rx_hdmi21_rx_post_0_proc_00_b0(val) ((rs_rx_hdmi21_rx_post_0_proc_00_b0*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_B4                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xB4)

#define RX_HDMI21_RX_POST_0_PROC_00_B4_struct                            rs_rx_hdmi21_rx_post_0_proc_00_b4

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_b4  rs_rx_hdmi21_rx_post_0_proc_00_b4;
struct _rs_rx_hdmi21_rx_post_0_proc_00_b4 {
    unsigned int regr_00_data_period_cnt_0                  :16;
    unsigned int regr_00_data_period_cnt_1                  :16;
};
#define rx_hdmi21_rx_post_0_proc_00_b4(val) ((rs_rx_hdmi21_rx_post_0_proc_00_b4*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_B8                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xB8)

#define RX_HDMI21_RX_POST_0_PROC_00_B8_struct                            rs_rx_hdmi21_rx_post_0_proc_00_b8

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_b8  rs_rx_hdmi21_rx_post_0_proc_00_b8;
struct _rs_rx_hdmi21_rx_post_0_proc_00_b8 {
    unsigned int regr_00_clk_det_tmds4p_cnt                 :20;
    unsigned int regr_00_clk_det_tmds4p_nck                 : 1;
    unsigned int regr_00_clk_det_tmds4p_low                 : 1;
    unsigned int regr_00_clk_det_tmds4p_high                : 1;
    unsigned int regr_00_clk_det_tmds4p_nstb                : 1;
    unsigned int reserved                                   : 8;
};
#define rx_hdmi21_rx_post_0_proc_00_b8(val) ((rs_rx_hdmi21_rx_post_0_proc_00_b8*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_BC                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xBC)

#define RX_HDMI21_RX_POST_0_PROC_00_BC_struct                            rs_rx_hdmi21_rx_post_0_proc_00_bc

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_bc  rs_rx_hdmi21_rx_post_0_proc_00_bc;
struct _rs_rx_hdmi21_rx_post_0_proc_00_bc {
    unsigned int regr_00_clk_det_pix4p_cnt                  :20;
    unsigned int regr_00_clk_det_pix4p_nck                  : 1;
    unsigned int regr_00_clk_det_pix4p_low                  : 1;
    unsigned int regr_00_clk_det_pix4p_high                 : 1;
    unsigned int regr_00_clk_det_pix4p_nstb                 : 1;
    unsigned int regr_00_mr_period_current                  : 3;
    unsigned int regr_00_dvi_mode_det                       : 1;
    unsigned int regr_00_hd21rx_regen_htotal_min_flag       : 1;
    unsigned int reserved                                   : 3;
};
#define rx_hdmi21_rx_post_0_proc_00_bc(val) ((rs_rx_hdmi21_rx_post_0_proc_00_bc*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_C0                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xC0)

#define RX_HDMI21_RX_POST_0_PROC_00_C0_struct                            rs_rx_hdmi21_rx_post_0_proc_00_c0

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_c0  rs_rx_hdmi21_rx_post_0_proc_00_c0;
struct _rs_rx_hdmi21_rx_post_0_proc_00_c0 {
    unsigned int regr_00_mr_tmds_hact                       :15;
    unsigned int regr_00_mr_tmds_vact                       :15;
    unsigned int regr_00_video_interlaced_det               : 1;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_c0(val) ((rs_rx_hdmi21_rx_post_0_proc_00_c0*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_C4                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xC4)

#define RX_HDMI21_RX_POST_0_PROC_00_C4_struct                            rs_rx_hdmi21_rx_post_0_proc_00_c4

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_c4  rs_rx_hdmi21_rx_post_0_proc_00_c4;
struct _rs_rx_hdmi21_rx_post_0_proc_00_c4 {
    unsigned int regr_00_mr_tmds_htotal                     :15;
    unsigned int regr_00_mr_tmds_vtotal                     :15;
    unsigned int regr_00_video_field_det                    : 2;
};
#define rx_hdmi21_rx_post_0_proc_00_c4(val) ((rs_rx_hdmi21_rx_post_0_proc_00_c4*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_C8                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xC8)

#define RX_HDMI21_RX_POST_0_PROC_00_C8_struct                            rs_rx_hdmi21_rx_post_0_proc_00_c8

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_c8  rs_rx_hdmi21_rx_post_0_proc_00_c8;
struct _rs_rx_hdmi21_rx_post_0_proc_00_c8 {
    unsigned int regr_00_poladj_hs_pol_adj_sts              : 1;
    unsigned int regr_00_poladj_vs_pol_adj_sts              : 1;
    unsigned int regr_00_mr_htotal                          :15;
    unsigned int regr_00_mr_vtotal                          :15;
};
#define rx_hdmi21_rx_post_0_proc_00_c8(val) ((rs_rx_hdmi21_rx_post_0_proc_00_c8*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_CC                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xCC)

#define RX_HDMI21_RX_POST_0_PROC_00_CC_struct                            rs_rx_hdmi21_rx_post_0_proc_00_cc

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_cc  rs_rx_hdmi21_rx_post_0_proc_00_cc;
struct _rs_rx_hdmi21_rx_post_0_proc_00_cc {
    unsigned int regr_00_mr_hact                            :15;
    unsigned int regr_00_mr_vact                            :15;
    unsigned int regr_00_vs_phase                           : 2;
};
#define rx_hdmi21_rx_post_0_proc_00_cc(val) ((rs_rx_hdmi21_rx_post_0_proc_00_cc*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_D0                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xD0)

#define RX_HDMI21_RX_POST_0_PROC_00_D0_struct                            rs_rx_hdmi21_rx_post_0_proc_00_d0

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_d0  rs_rx_hdmi21_rx_post_0_proc_00_d0;
struct _rs_rx_hdmi21_rx_post_0_proc_00_d0 {
    unsigned int regr_00_pkt_dec_ph_corrected_cnt           :16;
    unsigned int regr_00_pkt_dec_sp0_corrected_cnt          :16;
};
#define rx_hdmi21_rx_post_0_proc_00_d0(val) ((rs_rx_hdmi21_rx_post_0_proc_00_d0*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_D4                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xD4)

#define RX_HDMI21_RX_POST_0_PROC_00_D4_struct                            rs_rx_hdmi21_rx_post_0_proc_00_d4

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_d4  rs_rx_hdmi21_rx_post_0_proc_00_d4;
struct _rs_rx_hdmi21_rx_post_0_proc_00_d4 {
    unsigned int regr_00_pkt_dec_sp1_corrected_cnt          :16;
    unsigned int regr_00_pkt_dec_sp2_corrected_cnt          :16;
};
#define rx_hdmi21_rx_post_0_proc_00_d4(val) ((rs_rx_hdmi21_rx_post_0_proc_00_d4*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_D8                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xD8)

#define RX_HDMI21_RX_POST_0_PROC_00_D8_struct                            rs_rx_hdmi21_rx_post_0_proc_00_d8

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_d8  rs_rx_hdmi21_rx_post_0_proc_00_d8;
struct _rs_rx_hdmi21_rx_post_0_proc_00_d8 {
    unsigned int regr_00_pkt_dec_sp3_corrected_cnt          :16;
    unsigned int regr_00_pkt_dec_ph_uncorrected_cnt         :16;
};
#define rx_hdmi21_rx_post_0_proc_00_d8(val) ((rs_rx_hdmi21_rx_post_0_proc_00_d8*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_DC                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xDC)

#define RX_HDMI21_RX_POST_0_PROC_00_DC_struct                            rs_rx_hdmi21_rx_post_0_proc_00_dc

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_dc  rs_rx_hdmi21_rx_post_0_proc_00_dc;
struct _rs_rx_hdmi21_rx_post_0_proc_00_dc {
    unsigned int regr_00_pkt_dec_sp0_uncorrected_cnt        :16;
    unsigned int regr_00_pkt_dec_sp1_uncorrected_cnt        :16;
};
#define rx_hdmi21_rx_post_0_proc_00_dc(val) ((rs_rx_hdmi21_rx_post_0_proc_00_dc*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_E0                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xE0)

#define RX_HDMI21_RX_POST_0_PROC_00_E0_struct                            rs_rx_hdmi21_rx_post_0_proc_00_e0

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_e0  rs_rx_hdmi21_rx_post_0_proc_00_e0;
struct _rs_rx_hdmi21_rx_post_0_proc_00_e0 {
    unsigned int regr_00_pkt_dec_sp2_uncorrected_cnt        :16;
    unsigned int regr_00_pkt_dec_sp3_uncorrected_cnt        :16;
};
#define rx_hdmi21_rx_post_0_proc_00_e0(val) ((rs_rx_hdmi21_rx_post_0_proc_00_e0*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_E4                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xE4)

#define RX_HDMI21_RX_POST_0_PROC_00_E4_struct                            rs_rx_hdmi21_rx_post_0_proc_00_e4

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_e4  rs_rx_hdmi21_rx_post_0_proc_00_e4;
struct _rs_rx_hdmi21_rx_post_0_proc_00_e4 {
    unsigned int regr_00_pkt_errors_per_frame               :16;
    unsigned int regr_00_pkt_errors_frame_gap               :16;
};
#define rx_hdmi21_rx_post_0_proc_00_e4(val) ((rs_rx_hdmi21_rx_post_0_proc_00_e4*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_E8                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xE8)

#define RX_HDMI21_RX_POST_0_PROC_00_E8_struct                            rs_rx_hdmi21_rx_post_0_proc_00_e8

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_e8  rs_rx_hdmi21_rx_post_0_proc_00_e8;
struct _rs_rx_hdmi21_rx_post_0_proc_00_e8 {
    unsigned int regr_00_audio_afif_fill_max                :16;
    unsigned int regr_00_audio_afif_fill_min                :16;
};
#define rx_hdmi21_rx_post_0_proc_00_e8(val) ((rs_rx_hdmi21_rx_post_0_proc_00_e8*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_EC                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xEC)

#define RX_HDMI21_RX_POST_0_PROC_00_EC_struct                            rs_rx_hdmi21_rx_post_0_proc_00_ec

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_ec  rs_rx_hdmi21_rx_post_0_proc_00_ec;
struct _rs_rx_hdmi21_rx_post_0_proc_00_ec {
    unsigned int regr_00_audio_afif_fill_state              :16;
    unsigned int regr_00_audio_pll_lock_stable              : 1;
    unsigned int regr_00_audio_afif_overfl_sts              : 1;
    unsigned int regr_00_audio_afif_th_max_sts              : 1;
    unsigned int regr_00_audio_afif_th_min_sts              : 1;
    unsigned int regr_00_audio_afif_ths_pass_sts            : 1;
    unsigned int regr_00_audio_afif_underfl_sts             : 1;
    unsigned int regr_00_audio_gcp_av_mute_chg              : 1;
    unsigned int regr_00_dec_audio_format                   : 3;
    unsigned int regr_00_dec_audio_hbr                      : 1;
    unsigned int regr_00_audio_mute_flag                    : 1;
    unsigned int regr_00_audio_mute_state                   : 4;
};
#define rx_hdmi21_rx_post_0_proc_00_ec(val) ((rs_rx_hdmi21_rx_post_0_proc_00_ec*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_F0                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xF0)

#define RX_HDMI21_RX_POST_0_PROC_00_F0_struct                            rs_rx_hdmi21_rx_post_0_proc_00_f0

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_f0  rs_rx_hdmi21_rx_post_0_proc_00_f0;
struct _rs_rx_hdmi21_rx_post_0_proc_00_f0 {
    unsigned int regr_00_dec_audio_pll_cts                  :20;
    unsigned int reserved                                   :12;
};
#define rx_hdmi21_rx_post_0_proc_00_f0(val) ((rs_rx_hdmi21_rx_post_0_proc_00_f0*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_F4                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xF4)

#define RX_HDMI21_RX_POST_0_PROC_00_F4_struct                            rs_rx_hdmi21_rx_post_0_proc_00_f4

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_f4  rs_rx_hdmi21_rx_post_0_proc_00_f4;
struct _rs_rx_hdmi21_rx_post_0_proc_00_f4 {
    unsigned int regr_00_dec_audio_pll_n                    :20;
    unsigned int regr_00_dec_audio_ch_speak_alloc           : 8;
    unsigned int regr_00_hd21rx_redundant_pix               : 3;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_f4(val) ((rs_rx_hdmi21_rx_post_0_proc_00_f4*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_F8                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xF8)

#define RX_HDMI21_RX_POST_0_PROC_00_F8_struct                            rs_rx_hdmi21_rx_post_0_proc_00_f8

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_f8  rs_rx_hdmi21_rx_post_0_proc_00_f8;
struct _rs_rx_hdmi21_rx_post_0_proc_00_f8 {
    unsigned int regr_00_hd21rx_htotal                      :16;
    unsigned int regr_00_hd21rx_vactive                     :15;
    unsigned int reserved                                   : 1;
};
#define rx_hdmi21_rx_post_0_proc_00_f8(val) ((rs_rx_hdmi21_rx_post_0_proc_00_f8*)&(val))



#define RX_HDMI21_RX_POST_0_PROC_00_FC                                   (HV_HDMI21_RX_POST_0_PROC_00_BASE_ADDRESS + 0xFC)

#define RX_HDMI21_RX_POST_0_PROC_00_FC_struct                            rs_rx_hdmi21_rx_post_0_proc_00_fc

typedef struct _rs_rx_hdmi21_rx_post_0_proc_00_fc  rs_rx_hdmi21_rx_post_0_proc_00_fc;
struct _rs_rx_hdmi21_rx_post_0_proc_00_fc {
    unsigned int regr_00_hd21rx_hactive                     :14;
    unsigned int regr_00_hd21rx_vid_afifo_underflow         : 1;
    unsigned int regr_00_hd21rx_vid_afifo_overflow          : 1;
    unsigned int regr_00_dec_video_format                   : 3;
    unsigned int regr_00_dec_video_colour_depth             : 4;
    unsigned int regr_00_dec_pixel_phase                    : 4;
    unsigned int regr_00_dec_default_phase                  : 1;
    unsigned int regr_00_dec_pixel_repeat_factor            : 4;
};
#define rx_hdmi21_rx_post_0_proc_00_fc(val) ((rs_rx_hdmi21_rx_post_0_proc_00_fc*)&(val))



#endif