#ifndef _HV_PAGE_HT7315_DPU_VDM_TBL_RD_01_H_
#define _HV_PAGE_HT7315_DPU_VDM_TBL_RD_01_H_

#ifndef HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS
    #define HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS                                         0x11022C00
#endif


#define DISP_TOP_DPU_VDM_TBL_RD_01_00                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_VDM_TBL_RD_01_00_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_00

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_00  rs_disp_top_dpu_vdm_tbl_rd_01_00;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_00 {
    unsigned int reg_01_dm_rd_buf_size                      : 7;
    unsigned int reserved                                   :25;
};
#define disp_top_dpu_vdm_tbl_rd_01_00(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_00*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_04                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_VDM_TBL_RD_01_04_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_04

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_04  rs_disp_top_dpu_vdm_tbl_rd_01_04;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_04 {
    unsigned int reg_01_dm_rd_4k_bound_en                   : 1;
    unsigned int reg_01_dm_rd_access_mode                   : 1;
    unsigned int reg_01_dm_rd_burst_len                     : 8;
    unsigned int reg_01_dm_rd_burst_rmd                     : 8;
    unsigned int reg_01_dm_rd_col_step_dir                  : 1;
    unsigned int reg_01_dm_rd_db_en                         : 1;
    unsigned int reg_01_dm_rd_enable                        : 1;
    unsigned int reg_01_dm_rd_head_prefetch_num             : 2;
    unsigned int reg_01_dm_rd_line_step_dir                 : 1;
    unsigned int reg_01_dm_rd_outstanding                   : 4;
    unsigned int reg_01_dm_rd_ovflow_clr                    : 1;
    unsigned int reg_01_dm_rd_udflow_clr                    : 1;
    unsigned int reserved                                   : 2;
};
#define disp_top_dpu_vdm_tbl_rd_01_04(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_04*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_08                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_VDM_TBL_RD_01_08_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_08

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_08  rs_disp_top_dpu_vdm_tbl_rd_01_08;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_08 {
    unsigned int reg_01_dm_rd_burst_num                     :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_08(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_08*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_0C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_0C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_0c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_0c  rs_disp_top_dpu_vdm_tbl_rd_01_0c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_0c {
    unsigned int reg_01_dm_rd_col_step                      :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_0c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_0c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_10                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_VDM_TBL_RD_01_10_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_10

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_10  rs_disp_top_dpu_vdm_tbl_rd_01_10;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_10 {
    unsigned int reg_01_dm_rd_line_step                     :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_10(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_10*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_14                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_VDM_TBL_RD_01_14_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_14

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_14  rs_disp_top_dpu_vdm_tbl_rd_01_14;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_14 {
    unsigned int reg_01_dm_rd_start_adr                     :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_14(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_14*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_18                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x18)

#define DISP_TOP_DPU_VDM_TBL_RD_01_18_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_18

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_18  rs_disp_top_dpu_vdm_tbl_rd_01_18;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_18 {
    unsigned int reg_01_dm_rd_col_dat_num                   :16;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_vdm_tbl_rd_01_18(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_18*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_1C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x1C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_1C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_1c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_1c  rs_disp_top_dpu_vdm_tbl_rd_01_1c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_1c {
    unsigned int reg_01_dm_rd_rdata_index                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_1c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_1c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_20                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x20)

#define DISP_TOP_DPU_VDM_TBL_RD_01_20_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_20

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_20  rs_disp_top_dpu_vdm_tbl_rd_01_20;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_20 {
    unsigned int reg_01_dm_rd_total_col_num                 :16;
    unsigned int reg_01_dm_rd_total_line_num                :16;
};
#define disp_top_dpu_vdm_tbl_rd_01_20(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_20*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_24                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x24)

#define DISP_TOP_DPU_VDM_TBL_RD_01_24_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_24

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_24  rs_disp_top_dpu_vdm_tbl_rd_01_24;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_24 {
    unsigned int regr_01_dm_rd_buf_space                    : 7;
    unsigned int reserved                                   :25;
};
#define disp_top_dpu_vdm_tbl_rd_01_24(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_24*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_28                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x28)

#define DISP_TOP_DPU_VDM_TBL_RD_01_28_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_28

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_28  rs_disp_top_dpu_vdm_tbl_rd_01_28;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_28 {
    unsigned int regr_01_dm_rd_afifo_ovflow                 : 1;
    unsigned int regr_01_dm_rd_afifo_udflow                 : 1;
    unsigned int regr_01_dm_rd_block_num                    :16;
    unsigned int regr_01_dm_rd_buf_ovflow                   : 1;
    unsigned int regr_01_dm_rd_buf_udflow                   : 1;
    unsigned int regr_01_dm_rd_bus_idle                     : 1;
    unsigned int regr_01_dm_rd_cmd_sent                     : 4;
    unsigned int reserved                                   : 7;
};
#define disp_top_dpu_vdm_tbl_rd_01_28(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_28*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_2C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x2C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_2C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_2c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_2c  rs_disp_top_dpu_vdm_tbl_rd_01_2c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_2c {
    unsigned int regr_01_dm_rd_cnt                          :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_2c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_2c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_30                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x30)

#define DISP_TOP_DPU_VDM_TBL_RD_01_30_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_30

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_30  rs_disp_top_dpu_vdm_tbl_rd_01_30;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_30 {
    unsigned int regr_01_dm_rd_dat_wait                     :12;
    unsigned int regr_01_dm_rd_line_num                     :16;
    unsigned int regr_01_dm_rd_st                           : 4;
};
#define disp_top_dpu_vdm_tbl_rd_01_30(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_30*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_34                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x34)

#define DISP_TOP_DPU_VDM_TBL_RD_01_34_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_34

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_34  rs_disp_top_dpu_vdm_tbl_rd_01_34;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_34 {
    unsigned int regr_01_dm_rd_rdata_0                      :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_34(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_34*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_38                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x38)

#define DISP_TOP_DPU_VDM_TBL_RD_01_38_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_38

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_38  rs_disp_top_dpu_vdm_tbl_rd_01_38;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_38 {
    unsigned int regr_01_dm_rd_rdata_1                      :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_38(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_38*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_3C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x3C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_3C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_3c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_3c  rs_disp_top_dpu_vdm_tbl_rd_01_3c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_3c {
    unsigned int regr_01_dm_rd_rdata_2                      :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_3c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_3c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_40                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x40)

#define DISP_TOP_DPU_VDM_TBL_RD_01_40_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_40

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_40  rs_disp_top_dpu_vdm_tbl_rd_01_40;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_40 {
    unsigned int regr_01_dm_rd_rdata_3                      :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_40(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_40*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_44                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x44)

#define DISP_TOP_DPU_VDM_TBL_RD_01_44_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_44

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_44  rs_disp_top_dpu_vdm_tbl_rd_01_44;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_44 {
    unsigned int reg_01_dm_tbl_hbp                          : 8;
    unsigned int reserved                                   :24;
};
#define disp_top_dpu_vdm_tbl_rd_01_44(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_44*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_48                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x48)

#define DISP_TOP_DPU_VDM_TBL_RD_01_48_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_48

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_48  rs_disp_top_dpu_vdm_tbl_rd_01_48;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_48 {
    unsigned int reg_01_dm_tbl_start_adr0                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_48(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_48*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_4C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x4C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_4C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_4c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_4c  rs_disp_top_dpu_vdm_tbl_rd_01_4c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_4c {
    unsigned int reg_01_dm_tbl_byte_len0                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_4c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_4c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_50                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x50)

#define DISP_TOP_DPU_VDM_TBL_RD_01_50_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_50

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_50  rs_disp_top_dpu_vdm_tbl_rd_01_50;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_50 {
    unsigned int reg_01_dm_tbl_start_adr1                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_50(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_50*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_54                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x54)

#define DISP_TOP_DPU_VDM_TBL_RD_01_54_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_54

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_54  rs_disp_top_dpu_vdm_tbl_rd_01_54;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_54 {
    unsigned int reg_01_dm_tbl_byte_len1                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_54(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_54*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_58                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x58)

#define DISP_TOP_DPU_VDM_TBL_RD_01_58_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_58

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_58  rs_disp_top_dpu_vdm_tbl_rd_01_58;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_58 {
    unsigned int reg_01_dm_tbl_start_adr2                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_58(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_58*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_5C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x5C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_5C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_5c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_5c  rs_disp_top_dpu_vdm_tbl_rd_01_5c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_5c {
    unsigned int reg_01_dm_tbl_byte_len2                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_5c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_5c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_60                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x60)

#define DISP_TOP_DPU_VDM_TBL_RD_01_60_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_60

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_60  rs_disp_top_dpu_vdm_tbl_rd_01_60;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_60 {
    unsigned int reg_01_dm_tbl_start_adr3                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_60(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_60*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_64                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x64)

#define DISP_TOP_DPU_VDM_TBL_RD_01_64_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_64

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_64  rs_disp_top_dpu_vdm_tbl_rd_01_64;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_64 {
    unsigned int reg_01_dm_tbl_byte_len3                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_64(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_64*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_68                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x68)

#define DISP_TOP_DPU_VDM_TBL_RD_01_68_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_68

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_68  rs_disp_top_dpu_vdm_tbl_rd_01_68;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_68 {
    unsigned int reg_01_dm_tbl_start_adr4                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_68(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_68*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_6C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x6C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_6C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_6c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_6c  rs_disp_top_dpu_vdm_tbl_rd_01_6c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_6c {
    unsigned int reg_01_dm_tbl_byte_len4                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_6c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_6c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_70                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x70)

#define DISP_TOP_DPU_VDM_TBL_RD_01_70_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_70

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_70  rs_disp_top_dpu_vdm_tbl_rd_01_70;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_70 {
    unsigned int reg_01_dm_tbl_start_adr5                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_70(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_70*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_74                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x74)

#define DISP_TOP_DPU_VDM_TBL_RD_01_74_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_74

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_74  rs_disp_top_dpu_vdm_tbl_rd_01_74;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_74 {
    unsigned int reg_01_dm_tbl_byte_len5                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_74(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_74*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_78                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x78)

#define DISP_TOP_DPU_VDM_TBL_RD_01_78_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_78

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_78  rs_disp_top_dpu_vdm_tbl_rd_01_78;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_78 {
    unsigned int reg_01_dm_tbl_start_adr6                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_78(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_78*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_7C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x7C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_7C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_7c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_7c  rs_disp_top_dpu_vdm_tbl_rd_01_7c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_7c {
    unsigned int reg_01_dm_tbl_byte_len6                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_7c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_7c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_80                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x80)

#define DISP_TOP_DPU_VDM_TBL_RD_01_80_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_80

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_80  rs_disp_top_dpu_vdm_tbl_rd_01_80;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_80 {
    unsigned int reg_01_dm_tbl_start_adr7                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_80(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_80*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_84                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x84)

#define DISP_TOP_DPU_VDM_TBL_RD_01_84_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_84

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_84  rs_disp_top_dpu_vdm_tbl_rd_01_84;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_84 {
    unsigned int reg_01_dm_tbl_byte_len7                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_84(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_84*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_88                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x88)

#define DISP_TOP_DPU_VDM_TBL_RD_01_88_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_88

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_88  rs_disp_top_dpu_vdm_tbl_rd_01_88;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_88 {
    unsigned int reg_01_dm_tbl_start_adr8                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_88(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_88*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_8C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x8C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_8C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_8c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_8c  rs_disp_top_dpu_vdm_tbl_rd_01_8c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_8c {
    unsigned int reg_01_dm_tbl_byte_len8                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_8c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_8c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_90                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x90)

#define DISP_TOP_DPU_VDM_TBL_RD_01_90_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_90

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_90  rs_disp_top_dpu_vdm_tbl_rd_01_90;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_90 {
    unsigned int reg_01_dm_tbl_start_adr9                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_90(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_90*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_94                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x94)

#define DISP_TOP_DPU_VDM_TBL_RD_01_94_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_94

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_94  rs_disp_top_dpu_vdm_tbl_rd_01_94;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_94 {
    unsigned int reg_01_dm_tbl_byte_len9                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_94(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_94*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_98                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x98)

#define DISP_TOP_DPU_VDM_TBL_RD_01_98_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_98

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_98  rs_disp_top_dpu_vdm_tbl_rd_01_98;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_98 {
    unsigned int reg_01_dm_tbl_start_adr10                  :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_98(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_98*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_9C                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0x9C)

#define DISP_TOP_DPU_VDM_TBL_RD_01_9C_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_9c

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_9c  rs_disp_top_dpu_vdm_tbl_rd_01_9c;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_9c {
    unsigned int reg_01_dm_tbl_byte_len10                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_9c(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_9c*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_A0                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xA0)

#define DISP_TOP_DPU_VDM_TBL_RD_01_A0_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_a0

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_a0  rs_disp_top_dpu_vdm_tbl_rd_01_a0;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_a0 {
    unsigned int reg_01_dm_tbl_start_adr11                  :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_a0(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_a0*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_A4                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xA4)

#define DISP_TOP_DPU_VDM_TBL_RD_01_A4_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_a4

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_a4  rs_disp_top_dpu_vdm_tbl_rd_01_a4;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_a4 {
    unsigned int reg_01_dm_tbl_byte_len11                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_a4(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_a4*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_A8                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xA8)

#define DISP_TOP_DPU_VDM_TBL_RD_01_A8_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_a8

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_a8  rs_disp_top_dpu_vdm_tbl_rd_01_a8;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_a8 {
    unsigned int reg_01_dm_tbl_start_adr12                  :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_a8(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_a8*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_AC                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xAC)

#define DISP_TOP_DPU_VDM_TBL_RD_01_AC_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_ac

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_ac  rs_disp_top_dpu_vdm_tbl_rd_01_ac;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_ac {
    unsigned int reg_01_dm_tbl_byte_len12                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_ac(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_ac*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_B0                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xB0)

#define DISP_TOP_DPU_VDM_TBL_RD_01_B0_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_b0

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_b0  rs_disp_top_dpu_vdm_tbl_rd_01_b0;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_b0 {
    unsigned int reg_01_dm_tbl_start_adr13                  :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_b0(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_b0*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_B4                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xB4)

#define DISP_TOP_DPU_VDM_TBL_RD_01_B4_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_b4

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_b4  rs_disp_top_dpu_vdm_tbl_rd_01_b4;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_b4 {
    unsigned int reg_01_dm_tbl_byte_len13                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_b4(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_b4*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_B8                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xB8)

#define DISP_TOP_DPU_VDM_TBL_RD_01_B8_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_b8

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_b8  rs_disp_top_dpu_vdm_tbl_rd_01_b8;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_b8 {
    unsigned int reg_01_dm_tbl_start_adr14                  :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_b8(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_b8*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_BC                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xBC)

#define DISP_TOP_DPU_VDM_TBL_RD_01_BC_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_bc

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_bc  rs_disp_top_dpu_vdm_tbl_rd_01_bc;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_bc {
    unsigned int reg_01_dm_tbl_byte_len14                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_bc(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_bc*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_C0                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xC0)

#define DISP_TOP_DPU_VDM_TBL_RD_01_C0_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_c0

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_c0  rs_disp_top_dpu_vdm_tbl_rd_01_c0;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_c0 {
    unsigned int reg_01_dm_tbl_start_adr15                  :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_c0(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_c0*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_C4                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xC4)

#define DISP_TOP_DPU_VDM_TBL_RD_01_C4_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_c4

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_c4  rs_disp_top_dpu_vdm_tbl_rd_01_c4;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_c4 {
    unsigned int reg_01_dm_tbl_byte_len15                   :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_c4(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_c4*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_C8                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xC8)

#define DISP_TOP_DPU_VDM_TBL_RD_01_C8_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_c8

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_c8  rs_disp_top_dpu_vdm_tbl_rd_01_c8;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_c8 {
    unsigned int reg_01_dm_tbl_burst_len                    : 8;
    unsigned int reg_01_dm_tbl_sw_vs                        : 1;
    unsigned int reg_01_dm_tbl_hw_vs_en                     : 1;
    unsigned int reg_01_dm_tbl_enable                       :16;
    unsigned int reg_01_dm_tbl_hw_sel                       : 1;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_vdm_tbl_rd_01_c8(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_c8*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_CC                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xCC)

#define DISP_TOP_DPU_VDM_TBL_RD_01_CC_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_cc

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_cc  rs_disp_top_dpu_vdm_tbl_rd_01_cc;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_cc {
    unsigned int reg_01_unpack_mon_width                    :20;
    unsigned int reg_01_unpack_mon_height                   :12;
};
#define disp_top_dpu_vdm_tbl_rd_01_cc(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_cc*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_D0                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xD0)

#define DISP_TOP_DPU_VDM_TBL_RD_01_D0_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_d0

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_d0  rs_disp_top_dpu_vdm_tbl_rd_01_d0;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_d0 {
    unsigned int reg_01_en                                  : 1;
    unsigned int reg_01_en_no_latch                         : 1;
    unsigned int reserved                                   :30;
};
#define disp_top_dpu_vdm_tbl_rd_01_d0(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_d0*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_D4                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xD4)

#define DISP_TOP_DPU_VDM_TBL_RD_01_D4_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_d4

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_d4  rs_disp_top_dpu_vdm_tbl_rd_01_d4;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_d4 {
    unsigned int mem_reg_01                                 : 8;
    unsigned int reg_01_mem_ema                             :16;
    unsigned int reserved                                   : 8;
};
#define disp_top_dpu_vdm_tbl_rd_01_d4(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_d4*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_D8                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xD8)

#define DISP_TOP_DPU_VDM_TBL_RD_01_D8_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_d8

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_d8  rs_disp_top_dpu_vdm_tbl_rd_01_d8;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_d8 {
    unsigned int regr_01_dm_tbl_fsm_st                      : 3;
    unsigned int regr_01_dm_tbl_lut_cnt                     : 5;
    unsigned int reserved                                   :24;
};
#define disp_top_dpu_vdm_tbl_rd_01_d8(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_d8*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_DC                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xDC)

#define DISP_TOP_DPU_VDM_TBL_RD_01_DC_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_dc

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_dc  rs_disp_top_dpu_vdm_tbl_rd_01_dc;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_dc {
    unsigned int regr_01_dm_rd_col_dat_num                  :16;
    unsigned int regr_01_dm_rd_burst_len                    : 8;
    unsigned int regr_01_dm_rd_burst_rmd                    : 8;
};
#define disp_top_dpu_vdm_tbl_rd_01_dc(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_dc*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_E0                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xE0)

#define DISP_TOP_DPU_VDM_TBL_RD_01_E0_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_e0

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_e0  rs_disp_top_dpu_vdm_tbl_rd_01_e0;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_e0 {
    unsigned int regr_01_dm_rd_burst_num                    :32;
};
#define disp_top_dpu_vdm_tbl_rd_01_e0(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_e0*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_E4                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xE4)

#define DISP_TOP_DPU_VDM_TBL_RD_01_E4_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_e4

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_e4  rs_disp_top_dpu_vdm_tbl_rd_01_e4;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_e4 {
    unsigned int reg_01_tbl_delay_htotal                    :14;
    unsigned int reserved                                   :18;
};
#define disp_top_dpu_vdm_tbl_rd_01_e4(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_e4*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_E8                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xE8)

#define DISP_TOP_DPU_VDM_TBL_RD_01_E8_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_e8

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_e8  rs_disp_top_dpu_vdm_tbl_rd_01_e8;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_e8 {
    unsigned int reg_01_tbl_vs_vdly                         :14;
    unsigned int reg_01_tbl_vs_hdly                         :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_vdm_tbl_rd_01_e8(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_e8*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_EC                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xEC)

#define DISP_TOP_DPU_VDM_TBL_RD_01_EC_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_ec

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_ec  rs_disp_top_dpu_vdm_tbl_rd_01_ec;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_ec {
    unsigned int reg_01_tbl_interval_vdly                   :14;
    unsigned int reg_01_tbl_interval_hdly                   :14;
    unsigned int reserved                                   : 4;
};
#define disp_top_dpu_vdm_tbl_rd_01_ec(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_ec*)&(val))



#define DISP_TOP_DPU_VDM_TBL_RD_01_FC                                    (HV_DPU_VDM_TBL_RD_01_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_VDM_TBL_RD_01_FC_struct                             rs_disp_top_dpu_vdm_tbl_rd_01_fc

typedef struct _rs_disp_top_dpu_vdm_tbl_rd_01_fc  rs_disp_top_dpu_vdm_tbl_rd_01_fc;
struct _rs_disp_top_dpu_vdm_tbl_rd_01_fc {
    unsigned int reg_01_mem_ro                              : 4;
    unsigned int reserved                                   :28;
};
#define disp_top_dpu_vdm_tbl_rd_01_fc(val) ((rs_disp_top_dpu_vdm_tbl_rd_01_fc*)&(val))



#endif