#ifndef _HV_PAGE_HT7315_RX_PHY_DFE_02_H_
#define _HV_PAGE_HT7315_RX_PHY_DFE_02_H_

#ifndef HV_RX_PHY_DFE_02_BASE_ADDRESS
    #define HV_RX_PHY_DFE_02_BASE_ADDRESS                                         0x11046600
#endif


#define RX_RX_PHY_DFE_02_00                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x00)

#define RX_RX_PHY_DFE_02_00_struct                                       rs_rx_rx_phy_dfe_02_00

typedef struct _rs_rx_rx_phy_dfe_02_00  rs_rx_rx_phy_dfe_02_00;
struct _rs_rx_rx_phy_dfe_02_00 {
    unsigned int reg_02_rx_phy_ctl_enable                   : 1;
    unsigned int reg_02_rx_phy_ctl_st_init_en               : 1;
    unsigned int reg_02_rx_phy_ctl_st_byp                   : 7;
    unsigned int reg_02_rx_phy_ctl_st_hold                  : 7;
    unsigned int reg_02_rx_phy_ctl_st_eq_en                 : 6;
    unsigned int reg_02_rx_phy_ctl_st_dfe_en                : 6;
    unsigned int reg_02_rx_phy_ctl_cr_done_en               : 1;
    unsigned int reg_02_rx_phy_ctl_eq_init_en               : 1;
    unsigned int reg_02_rx_phy_ctl_dfe_init_en              : 1;
    unsigned int reg_02_rx_phy_ctl_eq_done                  : 1;
};
#define rx_rx_phy_dfe_02_00(val) ((rs_rx_rx_phy_dfe_02_00*)&(val))



#define RX_RX_PHY_DFE_02_04                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x04)

#define RX_RX_PHY_DFE_02_04_struct                                       rs_rx_rx_phy_dfe_02_04

typedef struct _rs_rx_rx_phy_dfe_02_04  rs_rx_rx_phy_dfe_02_04;
struct _rs_rx_rx_phy_dfe_02_04 {
    unsigned int reg_02_rx_phy_ctl_eq_timer                 :32;
};
#define rx_rx_phy_dfe_02_04(val) ((rs_rx_rx_phy_dfe_02_04*)&(val))



#define RX_RX_PHY_DFE_02_08                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x08)

#define RX_RX_PHY_DFE_02_08_struct                                       rs_rx_rx_phy_dfe_02_08

typedef struct _rs_rx_rx_phy_dfe_02_08  rs_rx_rx_phy_dfe_02_08;
struct _rs_rx_rx_phy_dfe_02_08 {
    unsigned int reg_02_rx_phy_ctl_hold_timer               :32;
};
#define rx_rx_phy_dfe_02_08(val) ((rs_rx_rx_phy_dfe_02_08*)&(val))



#define RX_RX_PHY_DFE_02_0C                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x0C)

#define RX_RX_PHY_DFE_02_0C_struct                                       rs_rx_rx_phy_dfe_02_0c

typedef struct _rs_rx_rx_phy_dfe_02_0c  rs_rx_rx_phy_dfe_02_0c;
struct _rs_rx_rx_phy_dfe_02_0c {
    unsigned int reg_02_rx_phy_ctl_hold_mode                : 2;
    unsigned int reg_02_rx_phy_ctl_man_eq_ag_en             : 2;
    unsigned int reg_02_rx_phy_ctl_sw_lane_vld              : 4;
    unsigned int reg_02_rx_phy_ctl_sw_lane_mode             : 1;
    unsigned int reserved                                   :23;
};
#define rx_rx_phy_dfe_02_0c(val) ((rs_rx_rx_phy_dfe_02_0c*)&(val))



#define RX_RX_PHY_DFE_02_10                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x10)

#define RX_RX_PHY_DFE_02_10_struct                                       rs_rx_rx_phy_dfe_02_10

typedef struct _rs_rx_rx_phy_dfe_02_10  rs_rx_rx_phy_dfe_02_10;
struct _rs_rx_rx_phy_dfe_02_10 {
    unsigned int reg_02_rx_phy_ctl_eq_init_val              : 4;
    unsigned int reg_02_rx_phy_ctl_rst_timer                :20;
    unsigned int reg_02_rx_phy_ctl_pol                      : 1;
    unsigned int reg_02_rx_phy_ctl_phy_rst_en               : 1;
    unsigned int reg_02_rx_phy_ctl_man_en                   : 1;
    unsigned int reg_02_rx_phy_ctl_man_loop_en              : 2;
    unsigned int reg_02_rx_phy_ctl_man_init_cha             : 2;
    unsigned int reserved                                   : 1;
};
#define rx_rx_phy_dfe_02_10(val) ((rs_rx_rx_phy_dfe_02_10*)&(val))



#define RX_RX_PHY_DFE_02_14                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x14)

#define RX_RX_PHY_DFE_02_14_struct                                       rs_rx_rx_phy_dfe_02_14

typedef struct _rs_rx_rx_phy_dfe_02_14  rs_rx_rx_phy_dfe_02_14;
struct _rs_rx_rx_phy_dfe_02_14 {
    unsigned int reg_02_rx_phy_dfe_en                       : 3;
    unsigned int reg_02_rx_phy_dfe_rng                      : 3;
    unsigned int reg_02_rx_phy_dfe_swap                     : 2;
    unsigned int reg_02_rx_phy_dfe_owth                     : 8;
    unsigned int reg_02_rx_phy_dfe_win_sel                  : 2;
    unsigned int reg_02_rx_phy_dfe_thd_sel                  : 2;
    unsigned int reg_02_rx_phy_eq_en                        : 1;
    unsigned int reg_02_rx_phy_eq_loop_cnt                  : 4;
    unsigned int reg_02_rx_phy_dfe_rand_det                 : 1;
    unsigned int reg_02_rx_phy_ctl_trn_mode_sw_en           : 2;
    unsigned int reserved                                   : 4;
};
#define rx_rx_phy_dfe_02_14(val) ((rs_rx_rx_phy_dfe_02_14*)&(val))



#define RX_RX_PHY_DFE_02_18                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x18)

#define RX_RX_PHY_DFE_02_18_struct                                       rs_rx_rx_phy_dfe_02_18

typedef struct _rs_rx_rx_phy_dfe_02_18  rs_rx_rx_phy_dfe_02_18;
struct _rs_rx_rx_phy_dfe_02_18 {
    unsigned int reg_02_rx_phy_patt_cdr                     :20;
    unsigned int reserved                                   :12;
};
#define rx_rx_phy_dfe_02_18(val) ((rs_rx_rx_phy_dfe_02_18*)&(val))



#define RX_RX_PHY_DFE_02_64                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x64)

#define RX_RX_PHY_DFE_02_64_struct                                       rs_rx_rx_phy_dfe_02_64

typedef struct _rs_rx_rx_phy_dfe_02_64  rs_rx_rx_phy_dfe_02_64;
struct _rs_rx_rx_phy_dfe_02_64 {
    unsigned int reg_02_rx_phy_vos_flow_start               : 1;
    unsigned int reg_02_rx_phy_vos_rst_timer                :16;
    unsigned int reg_02_rx_phy_vos_enable                   : 1;
    unsigned int reg_02_rx_phy_vos_start_sw_en              : 1;
    unsigned int reg_02_rx_phy_vos_hold_mode                : 1;
    unsigned int reg_02_rx_phy_vos_timer                    : 4;
    unsigned int reg_02_rx_phy_vos_st_byp                   : 5;
    unsigned int reg_02_rx_phy_vos_pll_lock_en              : 1;
    unsigned int reserved                                   : 2;
};
#define rx_rx_phy_dfe_02_64(val) ((rs_rx_rx_phy_dfe_02_64*)&(val))



#define RX_RX_PHY_DFE_02_68                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x68)

#define RX_RX_PHY_DFE_02_68_struct                                       rs_rx_rx_phy_dfe_02_68

typedef struct _rs_rx_rx_phy_dfe_02_68  rs_rx_rx_phy_dfe_02_68;
struct _rs_rx_rx_phy_dfe_02_68 {
    unsigned int reg_02_rx_phy_vos_st_hold                  : 5;
    unsigned int reg_02_rx_phy_vos_st_en                    : 5;
    unsigned int reserved                                   :22;
};
#define rx_rx_phy_dfe_02_68(val) ((rs_rx_rx_phy_dfe_02_68*)&(val))



#define RX_RX_PHY_DFE_02_6C                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x6C)

#define RX_RX_PHY_DFE_02_6C_struct                                       rs_rx_rx_phy_dfe_02_6c

typedef struct _rs_rx_rx_phy_dfe_02_6c  rs_rx_rx_phy_dfe_02_6c;
struct _rs_rx_rx_phy_dfe_02_6c {
    unsigned int reg_02_rx_phy_vos_0_start                  : 1;
    unsigned int reg_02_rx_phy_vos_0_manual_sel             : 1;
    unsigned int reg_02_rx_phy_vos_0_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_02_rx_phy_vos_0_cycle_delay            : 4;
    unsigned int reg_02_rx_phy_vos_0_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_02_rx_phy_vos_0_lane_sel               : 8;
};
#define rx_rx_phy_dfe_02_6c(val) ((rs_rx_rx_phy_dfe_02_6c*)&(val))



#define RX_RX_PHY_DFE_02_70                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x70)

#define RX_RX_PHY_DFE_02_70_struct                                       rs_rx_rx_phy_dfe_02_70

typedef struct _rs_rx_rx_phy_dfe_02_70  rs_rx_rx_phy_dfe_02_70;
struct _rs_rx_rx_phy_dfe_02_70 {
    unsigned int reg_02_rx_phy_vos_0_lane_vos0              : 4;
    unsigned int reg_02_rx_phy_vos_0_lane_vos1              : 4;
    unsigned int reg_02_rx_phy_vos_0_lane_vos2              : 4;
    unsigned int reg_02_rx_phy_vos_0_lane_vos3              : 4;
    unsigned int reg_02_rx_phy_vos_0_lane_vos4              : 4;
    unsigned int reg_02_rx_phy_vos_0_lane_vos5              : 4;
    unsigned int reg_02_rx_phy_vos_0_lane_vos6              : 4;
    unsigned int reg_02_rx_phy_vos_0_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_02_70(val) ((rs_rx_rx_phy_dfe_02_70*)&(val))



#define RX_RX_PHY_DFE_02_74                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x74)

#define RX_RX_PHY_DFE_02_74_struct                                       rs_rx_rx_phy_dfe_02_74

typedef struct _rs_rx_rx_phy_dfe_02_74  rs_rx_rx_phy_dfe_02_74;
struct _rs_rx_rx_phy_dfe_02_74 {
    unsigned int reg_02_rx_phy_vos_1_start                  : 1;
    unsigned int reg_02_rx_phy_vos_1_manual_sel             : 1;
    unsigned int reg_02_rx_phy_vos_1_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_02_rx_phy_vos_1_cycle_delay            : 4;
    unsigned int reg_02_rx_phy_vos_1_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_02_rx_phy_vos_1_lane_sel               : 8;
};
#define rx_rx_phy_dfe_02_74(val) ((rs_rx_rx_phy_dfe_02_74*)&(val))



#define RX_RX_PHY_DFE_02_78                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x78)

#define RX_RX_PHY_DFE_02_78_struct                                       rs_rx_rx_phy_dfe_02_78

typedef struct _rs_rx_rx_phy_dfe_02_78  rs_rx_rx_phy_dfe_02_78;
struct _rs_rx_rx_phy_dfe_02_78 {
    unsigned int reg_02_rx_phy_vos_1_lane_vos0              : 4;
    unsigned int reg_02_rx_phy_vos_1_lane_vos1              : 4;
    unsigned int reg_02_rx_phy_vos_1_lane_vos2              : 4;
    unsigned int reg_02_rx_phy_vos_1_lane_vos3              : 4;
    unsigned int reg_02_rx_phy_vos_1_lane_vos4              : 4;
    unsigned int reg_02_rx_phy_vos_1_lane_vos5              : 4;
    unsigned int reg_02_rx_phy_vos_1_lane_vos6              : 4;
    unsigned int reg_02_rx_phy_vos_1_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_02_78(val) ((rs_rx_rx_phy_dfe_02_78*)&(val))



#define RX_RX_PHY_DFE_02_7C                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x7C)

#define RX_RX_PHY_DFE_02_7C_struct                                       rs_rx_rx_phy_dfe_02_7c

typedef struct _rs_rx_rx_phy_dfe_02_7c  rs_rx_rx_phy_dfe_02_7c;
struct _rs_rx_rx_phy_dfe_02_7c {
    unsigned int reg_02_rx_phy_vos_2_start                  : 1;
    unsigned int reg_02_rx_phy_vos_2_manual_sel             : 1;
    unsigned int reg_02_rx_phy_vos_2_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_02_rx_phy_vos_2_cycle_delay            : 4;
    unsigned int reg_02_rx_phy_vos_2_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_02_rx_phy_vos_2_lane_sel               : 8;
};
#define rx_rx_phy_dfe_02_7c(val) ((rs_rx_rx_phy_dfe_02_7c*)&(val))



#define RX_RX_PHY_DFE_02_80                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x80)

#define RX_RX_PHY_DFE_02_80_struct                                       rs_rx_rx_phy_dfe_02_80

typedef struct _rs_rx_rx_phy_dfe_02_80  rs_rx_rx_phy_dfe_02_80;
struct _rs_rx_rx_phy_dfe_02_80 {
    unsigned int reg_02_rx_phy_vos_2_lane_vos0              : 4;
    unsigned int reg_02_rx_phy_vos_2_lane_vos1              : 4;
    unsigned int reg_02_rx_phy_vos_2_lane_vos2              : 4;
    unsigned int reg_02_rx_phy_vos_2_lane_vos3              : 4;
    unsigned int reg_02_rx_phy_vos_2_lane_vos4              : 4;
    unsigned int reg_02_rx_phy_vos_2_lane_vos5              : 4;
    unsigned int reg_02_rx_phy_vos_2_lane_vos6              : 4;
    unsigned int reg_02_rx_phy_vos_2_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_02_80(val) ((rs_rx_rx_phy_dfe_02_80*)&(val))



#define RX_RX_PHY_DFE_02_84                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x84)

#define RX_RX_PHY_DFE_02_84_struct                                       rs_rx_rx_phy_dfe_02_84

typedef struct _rs_rx_rx_phy_dfe_02_84  rs_rx_rx_phy_dfe_02_84;
struct _rs_rx_rx_phy_dfe_02_84 {
    unsigned int reg_02_rx_phy_vos_3_start                  : 1;
    unsigned int reg_02_rx_phy_vos_3_manual_sel             : 1;
    unsigned int reg_02_rx_phy_vos_3_serial_sel             : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_02_rx_phy_vos_3_cycle_delay            : 4;
    unsigned int reg_02_rx_phy_vos_3_count_num              :10;
    unsigned int reserved_1                                 : 6;
    unsigned int reg_02_rx_phy_vos_3_lane_sel               : 8;
};
#define rx_rx_phy_dfe_02_84(val) ((rs_rx_rx_phy_dfe_02_84*)&(val))



#define RX_RX_PHY_DFE_02_88                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x88)

#define RX_RX_PHY_DFE_02_88_struct                                       rs_rx_rx_phy_dfe_02_88

typedef struct _rs_rx_rx_phy_dfe_02_88  rs_rx_rx_phy_dfe_02_88;
struct _rs_rx_rx_phy_dfe_02_88 {
    unsigned int reg_02_rx_phy_vos_3_lane_vos0              : 4;
    unsigned int reg_02_rx_phy_vos_3_lane_vos1              : 4;
    unsigned int reg_02_rx_phy_vos_3_lane_vos2              : 4;
    unsigned int reg_02_rx_phy_vos_3_lane_vos3              : 4;
    unsigned int reg_02_rx_phy_vos_3_lane_vos4              : 4;
    unsigned int reg_02_rx_phy_vos_3_lane_vos5              : 4;
    unsigned int reg_02_rx_phy_vos_3_lane_vos6              : 4;
    unsigned int reg_02_rx_phy_vos_3_lane_vos7              : 4;
};
#define rx_rx_phy_dfe_02_88(val) ((rs_rx_rx_phy_dfe_02_88*)&(val))



#define RX_RX_PHY_DFE_02_8C                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x8C)

#define RX_RX_PHY_DFE_02_8C_struct                                       rs_rx_rx_phy_dfe_02_8c

typedef struct _rs_rx_rx_phy_dfe_02_8c  rs_rx_rx_phy_dfe_02_8c;
struct _rs_rx_rx_phy_dfe_02_8c {
    unsigned int regr_02_rx_phy_vos_0_ds_vos0               : 4;
    unsigned int regr_02_rx_phy_vos_0_ds_vos1               : 4;
    unsigned int regr_02_rx_phy_vos_0_ds_vos2               : 4;
    unsigned int regr_02_rx_phy_vos_0_ds_vos3               : 4;
    unsigned int regr_02_rx_phy_vos_0_ds_vos4               : 4;
    unsigned int regr_02_rx_phy_vos_0_ds_vos5               : 4;
    unsigned int regr_02_rx_phy_vos_0_ds_vos6               : 4;
    unsigned int regr_02_rx_phy_vos_0_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_02_8c(val) ((rs_rx_rx_phy_dfe_02_8c*)&(val))



#define RX_RX_PHY_DFE_02_90                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x90)

#define RX_RX_PHY_DFE_02_90_struct                                       rs_rx_rx_phy_dfe_02_90

typedef struct _rs_rx_rx_phy_dfe_02_90  rs_rx_rx_phy_dfe_02_90;
struct _rs_rx_rx_phy_dfe_02_90 {
    unsigned int regr_02_rx_phy_vos_0_done                  : 8;
    unsigned int regr_02_rx_phy_vos_0_overflow              : 8;
    unsigned int regr_02_rx_phy_vos_0_ds_cnt                :10;
    unsigned int reserved                                   : 6;
};
#define rx_rx_phy_dfe_02_90(val) ((rs_rx_rx_phy_dfe_02_90*)&(val))



#define RX_RX_PHY_DFE_02_94                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x94)

#define RX_RX_PHY_DFE_02_94_struct                                       rs_rx_rx_phy_dfe_02_94

typedef struct _rs_rx_rx_phy_dfe_02_94  rs_rx_rx_phy_dfe_02_94;
struct _rs_rx_rx_phy_dfe_02_94 {
    unsigned int regr_02_rx_phy_vos_1_ds_vos0               : 4;
    unsigned int regr_02_rx_phy_vos_1_ds_vos1               : 4;
    unsigned int regr_02_rx_phy_vos_1_ds_vos2               : 4;
    unsigned int regr_02_rx_phy_vos_1_ds_vos3               : 4;
    unsigned int regr_02_rx_phy_vos_1_ds_vos4               : 4;
    unsigned int regr_02_rx_phy_vos_1_ds_vos5               : 4;
    unsigned int regr_02_rx_phy_vos_1_ds_vos6               : 4;
    unsigned int regr_02_rx_phy_vos_1_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_02_94(val) ((rs_rx_rx_phy_dfe_02_94*)&(val))



#define RX_RX_PHY_DFE_02_98                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x98)

#define RX_RX_PHY_DFE_02_98_struct                                       rs_rx_rx_phy_dfe_02_98

typedef struct _rs_rx_rx_phy_dfe_02_98  rs_rx_rx_phy_dfe_02_98;
struct _rs_rx_rx_phy_dfe_02_98 {
    unsigned int regr_02_rx_phy_vos_1_done                  : 8;
    unsigned int regr_02_rx_phy_vos_1_overflow              : 8;
    unsigned int regr_02_rx_phy_vos_1_ds_cnt                :10;
    unsigned int reserved                                   : 6;
};
#define rx_rx_phy_dfe_02_98(val) ((rs_rx_rx_phy_dfe_02_98*)&(val))



#define RX_RX_PHY_DFE_02_9C                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0x9C)

#define RX_RX_PHY_DFE_02_9C_struct                                       rs_rx_rx_phy_dfe_02_9c

typedef struct _rs_rx_rx_phy_dfe_02_9c  rs_rx_rx_phy_dfe_02_9c;
struct _rs_rx_rx_phy_dfe_02_9c {
    unsigned int regr_02_rx_phy_vos_2_ds_vos0               : 4;
    unsigned int regr_02_rx_phy_vos_2_ds_vos1               : 4;
    unsigned int regr_02_rx_phy_vos_2_ds_vos2               : 4;
    unsigned int regr_02_rx_phy_vos_2_ds_vos3               : 4;
    unsigned int regr_02_rx_phy_vos_2_ds_vos4               : 4;
    unsigned int regr_02_rx_phy_vos_2_ds_vos5               : 4;
    unsigned int regr_02_rx_phy_vos_2_ds_vos6               : 4;
    unsigned int regr_02_rx_phy_vos_2_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_02_9c(val) ((rs_rx_rx_phy_dfe_02_9c*)&(val))



#define RX_RX_PHY_DFE_02_A0                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xA0)

#define RX_RX_PHY_DFE_02_A0_struct                                       rs_rx_rx_phy_dfe_02_a0

typedef struct _rs_rx_rx_phy_dfe_02_a0  rs_rx_rx_phy_dfe_02_a0;
struct _rs_rx_rx_phy_dfe_02_a0 {
    unsigned int regr_02_rx_phy_vos_2_done                  : 8;
    unsigned int regr_02_rx_phy_vos_2_overflow              : 8;
    unsigned int regr_02_rx_phy_vos_2_ds_cnt                :10;
    unsigned int reserved                                   : 6;
};
#define rx_rx_phy_dfe_02_a0(val) ((rs_rx_rx_phy_dfe_02_a0*)&(val))



#define RX_RX_PHY_DFE_02_A4                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xA4)

#define RX_RX_PHY_DFE_02_A4_struct                                       rs_rx_rx_phy_dfe_02_a4

typedef struct _rs_rx_rx_phy_dfe_02_a4  rs_rx_rx_phy_dfe_02_a4;
struct _rs_rx_rx_phy_dfe_02_a4 {
    unsigned int regr_02_rx_phy_vos_3_ds_vos0               : 4;
    unsigned int regr_02_rx_phy_vos_3_ds_vos1               : 4;
    unsigned int regr_02_rx_phy_vos_3_ds_vos2               : 4;
    unsigned int regr_02_rx_phy_vos_3_ds_vos3               : 4;
    unsigned int regr_02_rx_phy_vos_3_ds_vos4               : 4;
    unsigned int regr_02_rx_phy_vos_3_ds_vos5               : 4;
    unsigned int regr_02_rx_phy_vos_3_ds_vos6               : 4;
    unsigned int regr_02_rx_phy_vos_3_ds_vos7               : 4;
};
#define rx_rx_phy_dfe_02_a4(val) ((rs_rx_rx_phy_dfe_02_a4*)&(val))



#define RX_RX_PHY_DFE_02_A8                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xA8)

#define RX_RX_PHY_DFE_02_A8_struct                                       rs_rx_rx_phy_dfe_02_a8

typedef struct _rs_rx_rx_phy_dfe_02_a8  rs_rx_rx_phy_dfe_02_a8;
struct _rs_rx_rx_phy_dfe_02_a8 {
    unsigned int regr_02_rx_phy_vos_3_done                  : 8;
    unsigned int regr_02_rx_phy_vos_3_overflow              : 8;
    unsigned int regr_02_rx_phy_vos_3_ds_cnt                :10;
    unsigned int regr_02_rx_phy_vos_state                   : 3;
    unsigned int reserved                                   : 3;
};
#define rx_rx_phy_dfe_02_a8(val) ((rs_rx_rx_phy_dfe_02_a8*)&(val))



#define RX_RX_PHY_DFE_02_C0                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xC0)

#define RX_RX_PHY_DFE_02_C0_struct                                       rs_rx_rx_phy_dfe_02_c0

typedef struct _rs_rx_rx_phy_dfe_02_c0  rs_rx_rx_phy_dfe_02_c0;
struct _rs_rx_rx_phy_dfe_02_c0 {
    unsigned int regr_02_rx_phy_dfe_lane0_win_cnt           :16;
    unsigned int regr_02_rx_phy_dfe_lane1_win_cnt           :16;
};
#define rx_rx_phy_dfe_02_c0(val) ((rs_rx_rx_phy_dfe_02_c0*)&(val))



#define RX_RX_PHY_DFE_02_C4                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xC4)

#define RX_RX_PHY_DFE_02_C4_struct                                       rs_rx_rx_phy_dfe_02_c4

typedef struct _rs_rx_rx_phy_dfe_02_c4  rs_rx_rx_phy_dfe_02_c4;
struct _rs_rx_rx_phy_dfe_02_c4 {
    unsigned int regr_02_rx_phy_dfe_lane2_win_cnt           :16;
    unsigned int regr_02_rx_phy_dfe_lane3_win_cnt           :16;
};
#define rx_rx_phy_dfe_02_c4(val) ((rs_rx_rx_phy_dfe_02_c4*)&(val))



#define RX_RX_PHY_DFE_02_C8                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xC8)

#define RX_RX_PHY_DFE_02_C8_struct                                       rs_rx_rx_phy_dfe_02_c8

typedef struct _rs_rx_rx_phy_dfe_02_c8  rs_rx_rx_phy_dfe_02_c8;
struct _rs_rx_rx_phy_dfe_02_c8 {
    unsigned int regr_02_rx_phy_dfe_lane0_tap1              : 6;
    unsigned int regr_02_rx_phy_dfe_lane0_tap2              : 5;
    unsigned int regr_02_rx_phy_dfe_lane0_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_02_rx_phy_dfe_lane0_dv1_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane0_dv1_abs           :15;
};
#define rx_rx_phy_dfe_02_c8(val) ((rs_rx_rx_phy_dfe_02_c8*)&(val))



#define RX_RX_PHY_DFE_02_CC                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xCC)

#define RX_RX_PHY_DFE_02_CC_struct                                       rs_rx_rx_phy_dfe_02_cc

typedef struct _rs_rx_rx_phy_dfe_02_cc  rs_rx_rx_phy_dfe_02_cc;
struct _rs_rx_rx_phy_dfe_02_cc {
    unsigned int regr_02_rx_phy_dfe_lane0_dv2_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane0_dv2_abs           :15;
    unsigned int regr_02_rx_phy_dfe_lane0_dv3_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane0_dv3_abs           :15;
};
#define rx_rx_phy_dfe_02_cc(val) ((rs_rx_rx_phy_dfe_02_cc*)&(val))



#define RX_RX_PHY_DFE_02_D0                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xD0)

#define RX_RX_PHY_DFE_02_D0_struct                                       rs_rx_rx_phy_dfe_02_d0

typedef struct _rs_rx_rx_phy_dfe_02_d0  rs_rx_rx_phy_dfe_02_d0;
struct _rs_rx_rx_phy_dfe_02_d0 {
    unsigned int regr_02_rx_phy_dfe_lane1_tap1              : 6;
    unsigned int regr_02_rx_phy_dfe_lane1_tap2              : 5;
    unsigned int regr_02_rx_phy_dfe_lane1_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_02_rx_phy_dfe_lane1_dv1_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane1_dv1_abs           :15;
};
#define rx_rx_phy_dfe_02_d0(val) ((rs_rx_rx_phy_dfe_02_d0*)&(val))



#define RX_RX_PHY_DFE_02_D4                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xD4)

#define RX_RX_PHY_DFE_02_D4_struct                                       rs_rx_rx_phy_dfe_02_d4

typedef struct _rs_rx_rx_phy_dfe_02_d4  rs_rx_rx_phy_dfe_02_d4;
struct _rs_rx_rx_phy_dfe_02_d4 {
    unsigned int regr_02_rx_phy_dfe_lane1_dv2_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane1_dv2_abs           :15;
    unsigned int regr_02_rx_phy_dfe_lane1_dv3_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane1_dv3_abs           :15;
};
#define rx_rx_phy_dfe_02_d4(val) ((rs_rx_rx_phy_dfe_02_d4*)&(val))



#define RX_RX_PHY_DFE_02_D8                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xD8)

#define RX_RX_PHY_DFE_02_D8_struct                                       rs_rx_rx_phy_dfe_02_d8

typedef struct _rs_rx_rx_phy_dfe_02_d8  rs_rx_rx_phy_dfe_02_d8;
struct _rs_rx_rx_phy_dfe_02_d8 {
    unsigned int regr_02_rx_phy_dfe_lane2_tap1              : 6;
    unsigned int regr_02_rx_phy_dfe_lane2_tap2              : 5;
    unsigned int regr_02_rx_phy_dfe_lane2_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_02_rx_phy_dfe_lane2_dv1_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane2_dv1_abs           :15;
};
#define rx_rx_phy_dfe_02_d8(val) ((rs_rx_rx_phy_dfe_02_d8*)&(val))



#define RX_RX_PHY_DFE_02_DC                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xDC)

#define RX_RX_PHY_DFE_02_DC_struct                                       rs_rx_rx_phy_dfe_02_dc

typedef struct _rs_rx_rx_phy_dfe_02_dc  rs_rx_rx_phy_dfe_02_dc;
struct _rs_rx_rx_phy_dfe_02_dc {
    unsigned int regr_02_rx_phy_dfe_lane2_dv2_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane2_dv2_abs           :15;
    unsigned int regr_02_rx_phy_dfe_lane2_dv3_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane2_dv3_abs           :15;
};
#define rx_rx_phy_dfe_02_dc(val) ((rs_rx_rx_phy_dfe_02_dc*)&(val))



#define RX_RX_PHY_DFE_02_E0                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xE0)

#define RX_RX_PHY_DFE_02_E0_struct                                       rs_rx_rx_phy_dfe_02_e0

typedef struct _rs_rx_rx_phy_dfe_02_e0  rs_rx_rx_phy_dfe_02_e0;
struct _rs_rx_rx_phy_dfe_02_e0 {
    unsigned int regr_02_rx_phy_dfe_lane3_tap1              : 6;
    unsigned int regr_02_rx_phy_dfe_lane3_tap2              : 5;
    unsigned int regr_02_rx_phy_dfe_lane3_tap3              : 4;
    unsigned int reserved                                   : 1;
    unsigned int regr_02_rx_phy_dfe_lane3_dv1_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane3_dv1_abs           :15;
};
#define rx_rx_phy_dfe_02_e0(val) ((rs_rx_rx_phy_dfe_02_e0*)&(val))



#define RX_RX_PHY_DFE_02_E4                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xE4)

#define RX_RX_PHY_DFE_02_E4_struct                                       rs_rx_rx_phy_dfe_02_e4

typedef struct _rs_rx_rx_phy_dfe_02_e4  rs_rx_rx_phy_dfe_02_e4;
struct _rs_rx_rx_phy_dfe_02_e4 {
    unsigned int regr_02_rx_phy_dfe_lane3_dv2_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane3_dv2_abs           :15;
    unsigned int regr_02_rx_phy_dfe_lane3_dv3_sig           : 1;
    unsigned int regr_02_rx_phy_dfe_lane3_dv3_abs           :15;
};
#define rx_rx_phy_dfe_02_e4(val) ((rs_rx_rx_phy_dfe_02_e4*)&(val))



#define RX_RX_PHY_DFE_02_E8                                              (HV_RX_PHY_DFE_02_BASE_ADDRESS + 0xE8)

#define RX_RX_PHY_DFE_02_E8_struct                                       rs_rx_rx_phy_dfe_02_e8

typedef struct _rs_rx_rx_phy_dfe_02_e8  rs_rx_rx_phy_dfe_02_e8;
struct _rs_rx_rx_phy_dfe_02_e8 {
    unsigned int regr_02_rx_phy_ctl_state                   : 3;
    unsigned int regr_02_rx_phy_ctl_permit_ca               : 4;
    unsigned int regr_02_rx_phy_ctl_init_val                :16;
    unsigned int reserved                                   : 9;
};
#define rx_rx_phy_dfe_02_e8(val) ((rs_rx_rx_phy_dfe_02_e8*)&(val))



#endif