/**
 * @file BOE_VBO_UV550QUB_N70_UHD60.h
 * @brief Header file of Panel Param.
 *
 * @verbatim
 * ==============================================================================
 *                        ##### How to use #####
 * ==============================================================================
 *
 *
 @ endverbatim
 *
 * @author HiView SoC Software Team
 * @version 0.0.1
 * @date 2024-04-07
 */


#ifndef __BOE_VBO_UV550QUB_N70_UHD60_H__
#define __BOE_VBO_UV550QUB_N70_UHD60_H__

/*Panel common*/
#define PANEL_NAME                         "BOE_VBO_UV550QUB_N70_UHD60"

/* UHD60 attribute */
#define PANEL_H_TOTAL_TYP                  4400
#define PANEL_H_TOTAL_MAX                  4560
#define PANEL_H_TOTAL_MIN                  4240
#define PANEL_V_TOTAL_TYP                  2250
#define PANEL_V_TOTAL_MAX                  2450
#define PANEL_V_TOTAL_MIN                  2180
#define PANEL_H_ACTIVE                     3840
#define PANEL_V_ACTIVE                     2160
#define PANEL_FRAME_RATE_TYP               60
#define PANEL_FRAME_RATE_MAX               62
#define PANEL_FRAME_RATE_MIN               57
#define PANEL_PIXEL_CLOCK_TYP              594000  /*KHZ*/
#define PANEL_PIXEL_CLOCK_MAX              616000  /*KHZ*/
#define PANEL_PIXEL_CLOCK_MIN              552000  /*KHZ*/
#define PANEL_H_SYNC_WIDTH                 8
#define PANEL_V_SYNC_WIDTH                 2
#define PANEL_H_SYNC_BACK_PORCH            73
#define PANEL_V_SYNC_BACK_PORCH            16

#define PANEL_COLOR_DEPTH                  10
#define PANEL_LANE_NUM                     8
#define PANEL_PORT_NUM                     1

/* EDP attribute */
#define PANEL_LANE_RATE                    20       /*for EDP(6:1.62Gbps 10:2.7Gbps 20 5.4Gbps)*/

/* Process */
#define PANEL_POWER_ON_TIME                 1500                           /*Panel��?��?*/
#define PANEL_DATA_ON_TIME                  200                         /*�䨰?adata*/
#define PANEL_BLK_ON_TIME                   100                         /*?a��31a*/
#define PANEL_BLK_OFF_TIME                  5                           /*1?��?data*/
#define PANEL_DATA_OF_TIME                  150                          /*1?��?��31a*/
#define PANEL_POWER_OFF_TIME                10                          /*Panel??��?*/
#define PANEL_KTX_PLL_LOCK_TIME             210                         /*KTX PLL LOCK*/
#define PANEL_IDLE_PATTERN_TIME             0           /*??idle pattern*/

/* SSC */
#define PANEL_SSC_EN                        0
#define PANEL_SSC_FREQ                      50       /*0-100(k)*/
#define PANEL_SSC_FRAC                      2        /*0-30(0%-3%)*/

#define PANEL_EDP_HPD0_SOFT_MODE            0  /*软件模式（强制HPD模式）, 2表示软件模式开并拉低，3表示软件模式开并拉高，0表示硬件模式*/
#define PANEL_EDP_HPD1_SOFT_MODE            0  /*软件模式（强制HPD模式）, 2表示软件模式开并拉低，3表示软件模式开并拉高，0表示硬件模式*/

/* PHY MUX attribute */
#define PANEL_EDP_AUX0_PN_SWAP_EN           0
#define PANEL_EDP_AUX1_PN_SWAP_EN           0

#define PANEL_PHY0_MUX_EN                  1
#define PANEL_PHY0_0_MUX_SEL               4
#define PANEL_PHY0_1_MUX_SEL               5
#define PANEL_PHY0_2_MUX_SEL               6
#define PANEL_PHY0_3_MUX_SEL               7
#define PANEL_PHY0_LANE0_PN_SWAP           0
#define PANEL_PHY0_LANE1_PN_SWAP           0
#define PANEL_PHY0_LANE2_PN_SWAP           0
#define PANEL_PHY0_LANE3_PN_SWAP           0

#define PANEL_PHY1_MUX_EN                  1
#define PANEL_PHY1_0_MUX_SEL               0
#define PANEL_PHY1_1_MUX_SEL               1
#define PANEL_PHY1_2_MUX_SEL               2
#define PANEL_PHY1_3_MUX_SEL               3
#define PANEL_PHY1_LANE0_PN_SWAP           0
#define PANEL_PHY1_LANE1_PN_SWAP           0
#define PANEL_PHY1_LANE2_PN_SWAP           0
#define PANEL_PHY1_LANE3_PN_SWAP           0

#define PANEL_PHY2_MUX_EN                  0
#define PANEL_PHY2_0_MUX_SEL               4
#define PANEL_PHY2_1_MUX_SEL               5
#define PANEL_PHY2_2_MUX_SEL               6
#define PANEL_PHY2_3_MUX_SEL               7
#define PANEL_PHY2_LANE0_PN_SWAP           0
#define PANEL_PHY2_LANE1_PN_SWAP           0
#define PANEL_PHY2_LANE2_PN_SWAP           0
#define PANEL_PHY2_LANE3_PN_SWAP           0

#endif
