#ifndef _HV_PAGE_HT7315_HDMI21_RX_MISC_00_H_
#define _HV_PAGE_HT7315_HDMI21_RX_MISC_00_H_

#ifndef HV_HDMI21_RX_MISC_00_BASE_ADDRESS
    #define HV_HDMI21_RX_MISC_00_BASE_ADDRESS                                         0x1104DF00
#endif


#define RX_HDMI21_RX_MISC_00_00                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x00)

#define RX_HDMI21_RX_MISC_00_00_struct                                   rs_rx_hdmi21_rx_misc_00_00

typedef struct _rs_rx_hdmi21_rx_misc_00_00  rs_rx_hdmi21_rx_misc_00_00;
struct _rs_rx_hdmi21_rx_misc_00_00 {
    unsigned int reg_00_misc_0x00                           :32;
};
#define rx_hdmi21_rx_misc_00_00(val) ((rs_rx_hdmi21_rx_misc_00_00*)&(val))



#define RX_HDMI21_RX_MISC_00_04                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x04)

#define RX_HDMI21_RX_MISC_00_04_struct                                   rs_rx_hdmi21_rx_misc_00_04

typedef struct _rs_rx_hdmi21_rx_misc_00_04  rs_rx_hdmi21_rx_misc_00_04;
struct _rs_rx_hdmi21_rx_misc_00_04 {
    unsigned int reg_00_misc_0x04                           :32;
};
#define rx_hdmi21_rx_misc_00_04(val) ((rs_rx_hdmi21_rx_misc_00_04*)&(val))



#define RX_HDMI21_RX_MISC_00_08                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x08)

#define RX_HDMI21_RX_MISC_00_08_struct                                   rs_rx_hdmi21_rx_misc_00_08

typedef struct _rs_rx_hdmi21_rx_misc_00_08  rs_rx_hdmi21_rx_misc_00_08;
struct _rs_rx_hdmi21_rx_misc_00_08 {
    unsigned int reg_00_misc_0x08                           :32;
};
#define rx_hdmi21_rx_misc_00_08(val) ((rs_rx_hdmi21_rx_misc_00_08*)&(val))



#define RX_HDMI21_RX_MISC_00_0C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x0C)

#define RX_HDMI21_RX_MISC_00_0C_struct                                   rs_rx_hdmi21_rx_misc_00_0c

typedef struct _rs_rx_hdmi21_rx_misc_00_0c  rs_rx_hdmi21_rx_misc_00_0c;
struct _rs_rx_hdmi21_rx_misc_00_0c {
    unsigned int reg_00_misc_0x0c                           :32;
};
#define rx_hdmi21_rx_misc_00_0c(val) ((rs_rx_hdmi21_rx_misc_00_0c*)&(val))



#define RX_HDMI21_RX_MISC_00_10                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x10)

#define RX_HDMI21_RX_MISC_00_10_struct                                   rs_rx_hdmi21_rx_misc_00_10

typedef struct _rs_rx_hdmi21_rx_misc_00_10  rs_rx_hdmi21_rx_misc_00_10;
struct _rs_rx_hdmi21_rx_misc_00_10 {
    unsigned int reg_00_misc_0x10                           :32;
};
#define rx_hdmi21_rx_misc_00_10(val) ((rs_rx_hdmi21_rx_misc_00_10*)&(val))



#define RX_HDMI21_RX_MISC_00_14                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x14)

#define RX_HDMI21_RX_MISC_00_14_struct                                   rs_rx_hdmi21_rx_misc_00_14

typedef struct _rs_rx_hdmi21_rx_misc_00_14  rs_rx_hdmi21_rx_misc_00_14;
struct _rs_rx_hdmi21_rx_misc_00_14 {
    unsigned int reg_00_misc_0x14                           :32;
};
#define rx_hdmi21_rx_misc_00_14(val) ((rs_rx_hdmi21_rx_misc_00_14*)&(val))



#define RX_HDMI21_RX_MISC_00_18                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x18)

#define RX_HDMI21_RX_MISC_00_18_struct                                   rs_rx_hdmi21_rx_misc_00_18

typedef struct _rs_rx_hdmi21_rx_misc_00_18  rs_rx_hdmi21_rx_misc_00_18;
struct _rs_rx_hdmi21_rx_misc_00_18 {
    unsigned int reg_00_misc_0x18                           :32;
};
#define rx_hdmi21_rx_misc_00_18(val) ((rs_rx_hdmi21_rx_misc_00_18*)&(val))



#define RX_HDMI21_RX_MISC_00_1C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x1C)

#define RX_HDMI21_RX_MISC_00_1C_struct                                   rs_rx_hdmi21_rx_misc_00_1c

typedef struct _rs_rx_hdmi21_rx_misc_00_1c  rs_rx_hdmi21_rx_misc_00_1c;
struct _rs_rx_hdmi21_rx_misc_00_1c {
    unsigned int reg_00_misc_0x1c                           :32;
};
#define rx_hdmi21_rx_misc_00_1c(val) ((rs_rx_hdmi21_rx_misc_00_1c*)&(val))



#define RX_HDMI21_RX_MISC_00_20                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x20)

#define RX_HDMI21_RX_MISC_00_20_struct                                   rs_rx_hdmi21_rx_misc_00_20

typedef struct _rs_rx_hdmi21_rx_misc_00_20  rs_rx_hdmi21_rx_misc_00_20;
struct _rs_rx_hdmi21_rx_misc_00_20 {
    unsigned int reg_00_misc_0x20                           :32;
};
#define rx_hdmi21_rx_misc_00_20(val) ((rs_rx_hdmi21_rx_misc_00_20*)&(val))



#define RX_HDMI21_RX_MISC_00_24                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x24)

#define RX_HDMI21_RX_MISC_00_24_struct                                   rs_rx_hdmi21_rx_misc_00_24

typedef struct _rs_rx_hdmi21_rx_misc_00_24  rs_rx_hdmi21_rx_misc_00_24;
struct _rs_rx_hdmi21_rx_misc_00_24 {
    unsigned int reg_00_misc_0x24                           :32;
};
#define rx_hdmi21_rx_misc_00_24(val) ((rs_rx_hdmi21_rx_misc_00_24*)&(val))



#define RX_HDMI21_RX_MISC_00_28                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x28)

#define RX_HDMI21_RX_MISC_00_28_struct                                   rs_rx_hdmi21_rx_misc_00_28

typedef struct _rs_rx_hdmi21_rx_misc_00_28  rs_rx_hdmi21_rx_misc_00_28;
struct _rs_rx_hdmi21_rx_misc_00_28 {
    unsigned int reg_00_misc_0x28                           :32;
};
#define rx_hdmi21_rx_misc_00_28(val) ((rs_rx_hdmi21_rx_misc_00_28*)&(val))



#define RX_HDMI21_RX_MISC_00_2C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x2C)

#define RX_HDMI21_RX_MISC_00_2C_struct                                   rs_rx_hdmi21_rx_misc_00_2c

typedef struct _rs_rx_hdmi21_rx_misc_00_2c  rs_rx_hdmi21_rx_misc_00_2c;
struct _rs_rx_hdmi21_rx_misc_00_2c {
    unsigned int reg_00_misc_0x2c                           :32;
};
#define rx_hdmi21_rx_misc_00_2c(val) ((rs_rx_hdmi21_rx_misc_00_2c*)&(val))



#define RX_HDMI21_RX_MISC_00_30                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x30)

#define RX_HDMI21_RX_MISC_00_30_struct                                   rs_rx_hdmi21_rx_misc_00_30

typedef struct _rs_rx_hdmi21_rx_misc_00_30  rs_rx_hdmi21_rx_misc_00_30;
struct _rs_rx_hdmi21_rx_misc_00_30 {
    unsigned int reg_00_misc_0x30                           :32;
};
#define rx_hdmi21_rx_misc_00_30(val) ((rs_rx_hdmi21_rx_misc_00_30*)&(val))



#define RX_HDMI21_RX_MISC_00_34                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x34)

#define RX_HDMI21_RX_MISC_00_34_struct                                   rs_rx_hdmi21_rx_misc_00_34

typedef struct _rs_rx_hdmi21_rx_misc_00_34  rs_rx_hdmi21_rx_misc_00_34;
struct _rs_rx_hdmi21_rx_misc_00_34 {
    unsigned int reg_00_misc_0x34                           :32;
};
#define rx_hdmi21_rx_misc_00_34(val) ((rs_rx_hdmi21_rx_misc_00_34*)&(val))



#define RX_HDMI21_RX_MISC_00_38                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x38)

#define RX_HDMI21_RX_MISC_00_38_struct                                   rs_rx_hdmi21_rx_misc_00_38

typedef struct _rs_rx_hdmi21_rx_misc_00_38  rs_rx_hdmi21_rx_misc_00_38;
struct _rs_rx_hdmi21_rx_misc_00_38 {
    unsigned int reg_00_misc_0x38                           :32;
};
#define rx_hdmi21_rx_misc_00_38(val) ((rs_rx_hdmi21_rx_misc_00_38*)&(val))



#define RX_HDMI21_RX_MISC_00_3C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x3C)

#define RX_HDMI21_RX_MISC_00_3C_struct                                   rs_rx_hdmi21_rx_misc_00_3c

typedef struct _rs_rx_hdmi21_rx_misc_00_3c  rs_rx_hdmi21_rx_misc_00_3c;
struct _rs_rx_hdmi21_rx_misc_00_3c {
    unsigned int reg_00_misc_0x3c                           :32;
};
#define rx_hdmi21_rx_misc_00_3c(val) ((rs_rx_hdmi21_rx_misc_00_3c*)&(val))



#define RX_HDMI21_RX_MISC_00_40                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x40)

#define RX_HDMI21_RX_MISC_00_40_struct                                   rs_rx_hdmi21_rx_misc_00_40

typedef struct _rs_rx_hdmi21_rx_misc_00_40  rs_rx_hdmi21_rx_misc_00_40;
struct _rs_rx_hdmi21_rx_misc_00_40 {
    unsigned int reg_00_misc_0x40                           :32;
};
#define rx_hdmi21_rx_misc_00_40(val) ((rs_rx_hdmi21_rx_misc_00_40*)&(val))



#define RX_HDMI21_RX_MISC_00_44                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x44)

#define RX_HDMI21_RX_MISC_00_44_struct                                   rs_rx_hdmi21_rx_misc_00_44

typedef struct _rs_rx_hdmi21_rx_misc_00_44  rs_rx_hdmi21_rx_misc_00_44;
struct _rs_rx_hdmi21_rx_misc_00_44 {
    unsigned int reg_00_misc_0x44                           :32;
};
#define rx_hdmi21_rx_misc_00_44(val) ((rs_rx_hdmi21_rx_misc_00_44*)&(val))



#define RX_HDMI21_RX_MISC_00_48                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x48)

#define RX_HDMI21_RX_MISC_00_48_struct                                   rs_rx_hdmi21_rx_misc_00_48

typedef struct _rs_rx_hdmi21_rx_misc_00_48  rs_rx_hdmi21_rx_misc_00_48;
struct _rs_rx_hdmi21_rx_misc_00_48 {
    unsigned int reg_00_misc_0x48                           :32;
};
#define rx_hdmi21_rx_misc_00_48(val) ((rs_rx_hdmi21_rx_misc_00_48*)&(val))



#define RX_HDMI21_RX_MISC_00_4C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x4C)

#define RX_HDMI21_RX_MISC_00_4C_struct                                   rs_rx_hdmi21_rx_misc_00_4c

typedef struct _rs_rx_hdmi21_rx_misc_00_4c  rs_rx_hdmi21_rx_misc_00_4c;
struct _rs_rx_hdmi21_rx_misc_00_4c {
    unsigned int reg_00_misc_0x4c                           :32;
};
#define rx_hdmi21_rx_misc_00_4c(val) ((rs_rx_hdmi21_rx_misc_00_4c*)&(val))



#define RX_HDMI21_RX_MISC_00_50                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x50)

#define RX_HDMI21_RX_MISC_00_50_struct                                   rs_rx_hdmi21_rx_misc_00_50

typedef struct _rs_rx_hdmi21_rx_misc_00_50  rs_rx_hdmi21_rx_misc_00_50;
struct _rs_rx_hdmi21_rx_misc_00_50 {
    unsigned int reg_00_misc_0x50                           :32;
};
#define rx_hdmi21_rx_misc_00_50(val) ((rs_rx_hdmi21_rx_misc_00_50*)&(val))



#define RX_HDMI21_RX_MISC_00_54                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x54)

#define RX_HDMI21_RX_MISC_00_54_struct                                   rs_rx_hdmi21_rx_misc_00_54

typedef struct _rs_rx_hdmi21_rx_misc_00_54  rs_rx_hdmi21_rx_misc_00_54;
struct _rs_rx_hdmi21_rx_misc_00_54 {
    unsigned int reg_00_misc_0x54                           :32;
};
#define rx_hdmi21_rx_misc_00_54(val) ((rs_rx_hdmi21_rx_misc_00_54*)&(val))



#define RX_HDMI21_RX_MISC_00_58                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x58)

#define RX_HDMI21_RX_MISC_00_58_struct                                   rs_rx_hdmi21_rx_misc_00_58

typedef struct _rs_rx_hdmi21_rx_misc_00_58  rs_rx_hdmi21_rx_misc_00_58;
struct _rs_rx_hdmi21_rx_misc_00_58 {
    unsigned int reg_00_misc_0x58                           :32;
};
#define rx_hdmi21_rx_misc_00_58(val) ((rs_rx_hdmi21_rx_misc_00_58*)&(val))



#define RX_HDMI21_RX_MISC_00_5C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x5C)

#define RX_HDMI21_RX_MISC_00_5C_struct                                   rs_rx_hdmi21_rx_misc_00_5c

typedef struct _rs_rx_hdmi21_rx_misc_00_5c  rs_rx_hdmi21_rx_misc_00_5c;
struct _rs_rx_hdmi21_rx_misc_00_5c {
    unsigned int reg_00_misc_0x5c                           :32;
};
#define rx_hdmi21_rx_misc_00_5c(val) ((rs_rx_hdmi21_rx_misc_00_5c*)&(val))



#define RX_HDMI21_RX_MISC_00_60                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x60)

#define RX_HDMI21_RX_MISC_00_60_struct                                   rs_rx_hdmi21_rx_misc_00_60

typedef struct _rs_rx_hdmi21_rx_misc_00_60  rs_rx_hdmi21_rx_misc_00_60;
struct _rs_rx_hdmi21_rx_misc_00_60 {
    unsigned int reg_00_misc_0x60                           :32;
};
#define rx_hdmi21_rx_misc_00_60(val) ((rs_rx_hdmi21_rx_misc_00_60*)&(val))



#define RX_HDMI21_RX_MISC_00_64                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x64)

#define RX_HDMI21_RX_MISC_00_64_struct                                   rs_rx_hdmi21_rx_misc_00_64

typedef struct _rs_rx_hdmi21_rx_misc_00_64  rs_rx_hdmi21_rx_misc_00_64;
struct _rs_rx_hdmi21_rx_misc_00_64 {
    unsigned int reg_00_misc_0x64                           :32;
};
#define rx_hdmi21_rx_misc_00_64(val) ((rs_rx_hdmi21_rx_misc_00_64*)&(val))



#define RX_HDMI21_RX_MISC_00_68                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x68)

#define RX_HDMI21_RX_MISC_00_68_struct                                   rs_rx_hdmi21_rx_misc_00_68

typedef struct _rs_rx_hdmi21_rx_misc_00_68  rs_rx_hdmi21_rx_misc_00_68;
struct _rs_rx_hdmi21_rx_misc_00_68 {
    unsigned int reg_00_misc_0x68                           :32;
};
#define rx_hdmi21_rx_misc_00_68(val) ((rs_rx_hdmi21_rx_misc_00_68*)&(val))



#define RX_HDMI21_RX_MISC_00_6C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x6C)

#define RX_HDMI21_RX_MISC_00_6C_struct                                   rs_rx_hdmi21_rx_misc_00_6c

typedef struct _rs_rx_hdmi21_rx_misc_00_6c  rs_rx_hdmi21_rx_misc_00_6c;
struct _rs_rx_hdmi21_rx_misc_00_6c {
    unsigned int reg_00_misc_0x6c                           :32;
};
#define rx_hdmi21_rx_misc_00_6c(val) ((rs_rx_hdmi21_rx_misc_00_6c*)&(val))



#define RX_HDMI21_RX_MISC_00_70                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x70)

#define RX_HDMI21_RX_MISC_00_70_struct                                   rs_rx_hdmi21_rx_misc_00_70

typedef struct _rs_rx_hdmi21_rx_misc_00_70  rs_rx_hdmi21_rx_misc_00_70;
struct _rs_rx_hdmi21_rx_misc_00_70 {
    unsigned int reg_00_misc_0x70                           :32;
};
#define rx_hdmi21_rx_misc_00_70(val) ((rs_rx_hdmi21_rx_misc_00_70*)&(val))



#define RX_HDMI21_RX_MISC_00_74                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x74)

#define RX_HDMI21_RX_MISC_00_74_struct                                   rs_rx_hdmi21_rx_misc_00_74

typedef struct _rs_rx_hdmi21_rx_misc_00_74  rs_rx_hdmi21_rx_misc_00_74;
struct _rs_rx_hdmi21_rx_misc_00_74 {
    unsigned int reg_00_misc_0x74                           :32;
};
#define rx_hdmi21_rx_misc_00_74(val) ((rs_rx_hdmi21_rx_misc_00_74*)&(val))



#define RX_HDMI21_RX_MISC_00_78                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x78)

#define RX_HDMI21_RX_MISC_00_78_struct                                   rs_rx_hdmi21_rx_misc_00_78

typedef struct _rs_rx_hdmi21_rx_misc_00_78  rs_rx_hdmi21_rx_misc_00_78;
struct _rs_rx_hdmi21_rx_misc_00_78 {
    unsigned int reg_00_misc_0x78                           :32;
};
#define rx_hdmi21_rx_misc_00_78(val) ((rs_rx_hdmi21_rx_misc_00_78*)&(val))



#define RX_HDMI21_RX_MISC_00_7C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x7C)

#define RX_HDMI21_RX_MISC_00_7C_struct                                   rs_rx_hdmi21_rx_misc_00_7c

typedef struct _rs_rx_hdmi21_rx_misc_00_7c  rs_rx_hdmi21_rx_misc_00_7c;
struct _rs_rx_hdmi21_rx_misc_00_7c {
    unsigned int reg_00_misc_0x7c                           :32;
};
#define rx_hdmi21_rx_misc_00_7c(val) ((rs_rx_hdmi21_rx_misc_00_7c*)&(val))



#define RX_HDMI21_RX_MISC_00_80                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x80)

#define RX_HDMI21_RX_MISC_00_80_struct                                   rs_rx_hdmi21_rx_misc_00_80

typedef struct _rs_rx_hdmi21_rx_misc_00_80  rs_rx_hdmi21_rx_misc_00_80;
struct _rs_rx_hdmi21_rx_misc_00_80 {
    unsigned int reg_00_misc_0x80                           :32;
};
#define rx_hdmi21_rx_misc_00_80(val) ((rs_rx_hdmi21_rx_misc_00_80*)&(val))



#define RX_HDMI21_RX_MISC_00_84                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x84)

#define RX_HDMI21_RX_MISC_00_84_struct                                   rs_rx_hdmi21_rx_misc_00_84

typedef struct _rs_rx_hdmi21_rx_misc_00_84  rs_rx_hdmi21_rx_misc_00_84;
struct _rs_rx_hdmi21_rx_misc_00_84 {
    unsigned int reg_00_misc_0x84                           :32;
};
#define rx_hdmi21_rx_misc_00_84(val) ((rs_rx_hdmi21_rx_misc_00_84*)&(val))



#define RX_HDMI21_RX_MISC_00_88                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x88)

#define RX_HDMI21_RX_MISC_00_88_struct                                   rs_rx_hdmi21_rx_misc_00_88

typedef struct _rs_rx_hdmi21_rx_misc_00_88  rs_rx_hdmi21_rx_misc_00_88;
struct _rs_rx_hdmi21_rx_misc_00_88 {
    unsigned int reg_00_misc_0x88                           :32;
};
#define rx_hdmi21_rx_misc_00_88(val) ((rs_rx_hdmi21_rx_misc_00_88*)&(val))



#define RX_HDMI21_RX_MISC_00_8C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x8C)

#define RX_HDMI21_RX_MISC_00_8C_struct                                   rs_rx_hdmi21_rx_misc_00_8c

typedef struct _rs_rx_hdmi21_rx_misc_00_8c  rs_rx_hdmi21_rx_misc_00_8c;
struct _rs_rx_hdmi21_rx_misc_00_8c {
    unsigned int reg_00_misc_0x8c                           :32;
};
#define rx_hdmi21_rx_misc_00_8c(val) ((rs_rx_hdmi21_rx_misc_00_8c*)&(val))



#define RX_HDMI21_RX_MISC_00_90                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x90)

#define RX_HDMI21_RX_MISC_00_90_struct                                   rs_rx_hdmi21_rx_misc_00_90

typedef struct _rs_rx_hdmi21_rx_misc_00_90  rs_rx_hdmi21_rx_misc_00_90;
struct _rs_rx_hdmi21_rx_misc_00_90 {
    unsigned int reg_00_misc_0x90                           :32;
};
#define rx_hdmi21_rx_misc_00_90(val) ((rs_rx_hdmi21_rx_misc_00_90*)&(val))



#define RX_HDMI21_RX_MISC_00_94                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x94)

#define RX_HDMI21_RX_MISC_00_94_struct                                   rs_rx_hdmi21_rx_misc_00_94

typedef struct _rs_rx_hdmi21_rx_misc_00_94  rs_rx_hdmi21_rx_misc_00_94;
struct _rs_rx_hdmi21_rx_misc_00_94 {
    unsigned int reg_00_misc_0x94                           :32;
};
#define rx_hdmi21_rx_misc_00_94(val) ((rs_rx_hdmi21_rx_misc_00_94*)&(val))



#define RX_HDMI21_RX_MISC_00_98                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x98)

#define RX_HDMI21_RX_MISC_00_98_struct                                   rs_rx_hdmi21_rx_misc_00_98

typedef struct _rs_rx_hdmi21_rx_misc_00_98  rs_rx_hdmi21_rx_misc_00_98;
struct _rs_rx_hdmi21_rx_misc_00_98 {
    unsigned int reg_00_misc_0x98                           :32;
};
#define rx_hdmi21_rx_misc_00_98(val) ((rs_rx_hdmi21_rx_misc_00_98*)&(val))



#define RX_HDMI21_RX_MISC_00_9C                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0x9C)

#define RX_HDMI21_RX_MISC_00_9C_struct                                   rs_rx_hdmi21_rx_misc_00_9c

typedef struct _rs_rx_hdmi21_rx_misc_00_9c  rs_rx_hdmi21_rx_misc_00_9c;
struct _rs_rx_hdmi21_rx_misc_00_9c {
    unsigned int reg_00_misc_0x9c                           :32;
};
#define rx_hdmi21_rx_misc_00_9c(val) ((rs_rx_hdmi21_rx_misc_00_9c*)&(val))



#define RX_HDMI21_RX_MISC_00_A0                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xA0)

#define RX_HDMI21_RX_MISC_00_A0_struct                                   rs_rx_hdmi21_rx_misc_00_a0

typedef struct _rs_rx_hdmi21_rx_misc_00_a0  rs_rx_hdmi21_rx_misc_00_a0;
struct _rs_rx_hdmi21_rx_misc_00_a0 {
    unsigned int regr_00_hd21rx_auto_eq_err_value_ch0       :15;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_hd21rx_auto_eq_err_value_ch1       :15;
    unsigned int reserved_1                                 : 1;
};
#define rx_hdmi21_rx_misc_00_a0(val) ((rs_rx_hdmi21_rx_misc_00_a0*)&(val))



#define RX_HDMI21_RX_MISC_00_A4                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xA4)

#define RX_HDMI21_RX_MISC_00_A4_struct                                   rs_rx_hdmi21_rx_misc_00_a4

typedef struct _rs_rx_hdmi21_rx_misc_00_a4  rs_rx_hdmi21_rx_misc_00_a4;
struct _rs_rx_hdmi21_rx_misc_00_a4 {
    unsigned int regr_00_hd21rx_auto_eq_err_value_ch2       :15;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_hd21rx_auto_eq_err_value_ch3       :15;
    unsigned int reserved_1                                 : 1;
};
#define rx_hdmi21_rx_misc_00_a4(val) ((rs_rx_hdmi21_rx_misc_00_a4*)&(val))



#define RX_HDMI21_RX_MISC_00_A8                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xA8)

#define RX_HDMI21_RX_MISC_00_A8_struct                                   rs_rx_hdmi21_rx_misc_00_a8

typedef struct _rs_rx_hdmi21_rx_misc_00_a8  rs_rx_hdmi21_rx_misc_00_a8;
struct _rs_rx_hdmi21_rx_misc_00_a8 {
    unsigned int regr_00_hd21rx_auto_eq_debug_phy_init_cnt  : 8;
    unsigned int regr_00_hd21rx_auto_eq1_debug_eq_permit_cnt:12;
    unsigned int regr_00_hd21rx_auto_eq0_debug_eq_permit_cnt: 8;
    unsigned int regr_00_hd21rx_frlrx_auto_eq_ctrl_state    : 4;
};
#define rx_hdmi21_rx_misc_00_a8(val) ((rs_rx_hdmi21_rx_misc_00_a8*)&(val))



#define RX_HDMI21_RX_MISC_00_AC                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xAC)

#define RX_HDMI21_RX_MISC_00_AC_struct                                   rs_rx_hdmi21_rx_misc_00_ac

typedef struct _rs_rx_hdmi21_rx_misc_00_ac  rs_rx_hdmi21_rx_misc_00_ac;
struct _rs_rx_hdmi21_rx_misc_00_ac {
    unsigned int regr_00_hd21rx_ltp_auto_eq_met_cnt_ln0     :15;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_hd21rx_ltp_auto_eq_met_cnt_ln1     :15;
    unsigned int reserved_1                                 : 1;
};
#define rx_hdmi21_rx_misc_00_ac(val) ((rs_rx_hdmi21_rx_misc_00_ac*)&(val))



#define RX_HDMI21_RX_MISC_00_B0                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xB0)

#define RX_HDMI21_RX_MISC_00_B0_struct                                   rs_rx_hdmi21_rx_misc_00_b0

typedef struct _rs_rx_hdmi21_rx_misc_00_b0  rs_rx_hdmi21_rx_misc_00_b0;
struct _rs_rx_hdmi21_rx_misc_00_b0 {
    unsigned int regr_00_hd21rx_ltp_auto_eq_met_cnt_ln2     :15;
    unsigned int reserved                                   : 1;
    unsigned int regr_00_hd21rx_ltp_auto_eq_met_cnt_ln3     :15;
    unsigned int reserved_1                                 : 1;
};
#define rx_hdmi21_rx_misc_00_b0(val) ((rs_rx_hdmi21_rx_misc_00_b0*)&(val))



#define RX_HDMI21_RX_MISC_00_B4                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xB4)

#define RX_HDMI21_RX_MISC_00_B4_struct                                   rs_rx_hdmi21_rx_misc_00_b4

typedef struct _rs_rx_hdmi21_rx_misc_00_b4  rs_rx_hdmi21_rx_misc_00_b4;
struct _rs_rx_hdmi21_rx_misc_00_b4 {
    unsigned int regr_00_misc_0xb4                          :32;
};
#define rx_hdmi21_rx_misc_00_b4(val) ((rs_rx_hdmi21_rx_misc_00_b4*)&(val))



#define RX_HDMI21_RX_MISC_00_B8                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xB8)

#define RX_HDMI21_RX_MISC_00_B8_struct                                   rs_rx_hdmi21_rx_misc_00_b8

typedef struct _rs_rx_hdmi21_rx_misc_00_b8  rs_rx_hdmi21_rx_misc_00_b8;
struct _rs_rx_hdmi21_rx_misc_00_b8 {
    unsigned int regr_00_misc_0xb8                          :32;
};
#define rx_hdmi21_rx_misc_00_b8(val) ((rs_rx_hdmi21_rx_misc_00_b8*)&(val))



#define RX_HDMI21_RX_MISC_00_BC                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xBC)

#define RX_HDMI21_RX_MISC_00_BC_struct                                   rs_rx_hdmi21_rx_misc_00_bc

typedef struct _rs_rx_hdmi21_rx_misc_00_bc  rs_rx_hdmi21_rx_misc_00_bc;
struct _rs_rx_hdmi21_rx_misc_00_bc {
    unsigned int regr_00_misc_0xbc                          :32;
};
#define rx_hdmi21_rx_misc_00_bc(val) ((rs_rx_hdmi21_rx_misc_00_bc*)&(val))



#define RX_HDMI21_RX_MISC_00_C0                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xC0)

#define RX_HDMI21_RX_MISC_00_C0_struct                                   rs_rx_hdmi21_rx_misc_00_c0

typedef struct _rs_rx_hdmi21_rx_misc_00_c0  rs_rx_hdmi21_rx_misc_00_c0;
struct _rs_rx_hdmi21_rx_misc_00_c0 {
    unsigned int regr_00_misc_0xc0                          :32;
};
#define rx_hdmi21_rx_misc_00_c0(val) ((rs_rx_hdmi21_rx_misc_00_c0*)&(val))



#define RX_HDMI21_RX_MISC_00_C4                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xC4)

#define RX_HDMI21_RX_MISC_00_C4_struct                                   rs_rx_hdmi21_rx_misc_00_c4

typedef struct _rs_rx_hdmi21_rx_misc_00_c4  rs_rx_hdmi21_rx_misc_00_c4;
struct _rs_rx_hdmi21_rx_misc_00_c4 {
    unsigned int regr_00_misc_0xc4                          :32;
};
#define rx_hdmi21_rx_misc_00_c4(val) ((rs_rx_hdmi21_rx_misc_00_c4*)&(val))



#define RX_HDMI21_RX_MISC_00_C8                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xC8)

#define RX_HDMI21_RX_MISC_00_C8_struct                                   rs_rx_hdmi21_rx_misc_00_c8

typedef struct _rs_rx_hdmi21_rx_misc_00_c8  rs_rx_hdmi21_rx_misc_00_c8;
struct _rs_rx_hdmi21_rx_misc_00_c8 {
    unsigned int regr_00_misc_0xc8                          :32;
};
#define rx_hdmi21_rx_misc_00_c8(val) ((rs_rx_hdmi21_rx_misc_00_c8*)&(val))



#define RX_HDMI21_RX_MISC_00_CC                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xCC)

#define RX_HDMI21_RX_MISC_00_CC_struct                                   rs_rx_hdmi21_rx_misc_00_cc

typedef struct _rs_rx_hdmi21_rx_misc_00_cc  rs_rx_hdmi21_rx_misc_00_cc;
struct _rs_rx_hdmi21_rx_misc_00_cc {
    unsigned int regr_00_misc_0xcc                          :32;
};
#define rx_hdmi21_rx_misc_00_cc(val) ((rs_rx_hdmi21_rx_misc_00_cc*)&(val))



#define RX_HDMI21_RX_MISC_00_D0                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xD0)

#define RX_HDMI21_RX_MISC_00_D0_struct                                   rs_rx_hdmi21_rx_misc_00_d0

typedef struct _rs_rx_hdmi21_rx_misc_00_d0  rs_rx_hdmi21_rx_misc_00_d0;
struct _rs_rx_hdmi21_rx_misc_00_d0 {
    unsigned int regr_00_misc_0xd0                          :32;
};
#define rx_hdmi21_rx_misc_00_d0(val) ((rs_rx_hdmi21_rx_misc_00_d0*)&(val))



#define RX_HDMI21_RX_MISC_00_D4                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xD4)

#define RX_HDMI21_RX_MISC_00_D4_struct                                   rs_rx_hdmi21_rx_misc_00_d4

typedef struct _rs_rx_hdmi21_rx_misc_00_d4  rs_rx_hdmi21_rx_misc_00_d4;
struct _rs_rx_hdmi21_rx_misc_00_d4 {
    unsigned int regr_00_misc_0xd4                          :32;
};
#define rx_hdmi21_rx_misc_00_d4(val) ((rs_rx_hdmi21_rx_misc_00_d4*)&(val))



#define RX_HDMI21_RX_MISC_00_D8                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xD8)

#define RX_HDMI21_RX_MISC_00_D8_struct                                   rs_rx_hdmi21_rx_misc_00_d8

typedef struct _rs_rx_hdmi21_rx_misc_00_d8  rs_rx_hdmi21_rx_misc_00_d8;
struct _rs_rx_hdmi21_rx_misc_00_d8 {
    unsigned int regr_00_misc_0xd8                          :32;
};
#define rx_hdmi21_rx_misc_00_d8(val) ((rs_rx_hdmi21_rx_misc_00_d8*)&(val))



#define RX_HDMI21_RX_MISC_00_DC                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xDC)

#define RX_HDMI21_RX_MISC_00_DC_struct                                   rs_rx_hdmi21_rx_misc_00_dc

typedef struct _rs_rx_hdmi21_rx_misc_00_dc  rs_rx_hdmi21_rx_misc_00_dc;
struct _rs_rx_hdmi21_rx_misc_00_dc {
    unsigned int regr_00_misc_0xdc                          :32;
};
#define rx_hdmi21_rx_misc_00_dc(val) ((rs_rx_hdmi21_rx_misc_00_dc*)&(val))



#define RX_HDMI21_RX_MISC_00_E0                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xE0)

#define RX_HDMI21_RX_MISC_00_E0_struct                                   rs_rx_hdmi21_rx_misc_00_e0

typedef struct _rs_rx_hdmi21_rx_misc_00_e0  rs_rx_hdmi21_rx_misc_00_e0;
struct _rs_rx_hdmi21_rx_misc_00_e0 {
    unsigned int regr_00_misc_0xe0                          :32;
};
#define rx_hdmi21_rx_misc_00_e0(val) ((rs_rx_hdmi21_rx_misc_00_e0*)&(val))



#define RX_HDMI21_RX_MISC_00_E4                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xE4)

#define RX_HDMI21_RX_MISC_00_E4_struct                                   rs_rx_hdmi21_rx_misc_00_e4

typedef struct _rs_rx_hdmi21_rx_misc_00_e4  rs_rx_hdmi21_rx_misc_00_e4;
struct _rs_rx_hdmi21_rx_misc_00_e4 {
    unsigned int regr_00_misc_0xe4                          :32;
};
#define rx_hdmi21_rx_misc_00_e4(val) ((rs_rx_hdmi21_rx_misc_00_e4*)&(val))



#define RX_HDMI21_RX_MISC_00_E8                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xE8)

#define RX_HDMI21_RX_MISC_00_E8_struct                                   rs_rx_hdmi21_rx_misc_00_e8

typedef struct _rs_rx_hdmi21_rx_misc_00_e8  rs_rx_hdmi21_rx_misc_00_e8;
struct _rs_rx_hdmi21_rx_misc_00_e8 {
    unsigned int regr_00_misc_0xe8                          :32;
};
#define rx_hdmi21_rx_misc_00_e8(val) ((rs_rx_hdmi21_rx_misc_00_e8*)&(val))



#define RX_HDMI21_RX_MISC_00_EC                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xEC)

#define RX_HDMI21_RX_MISC_00_EC_struct                                   rs_rx_hdmi21_rx_misc_00_ec

typedef struct _rs_rx_hdmi21_rx_misc_00_ec  rs_rx_hdmi21_rx_misc_00_ec;
struct _rs_rx_hdmi21_rx_misc_00_ec {
    unsigned int regr_00_misc_0xec                          :32;
};
#define rx_hdmi21_rx_misc_00_ec(val) ((rs_rx_hdmi21_rx_misc_00_ec*)&(val))



#define RX_HDMI21_RX_MISC_00_F0                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xF0)

#define RX_HDMI21_RX_MISC_00_F0_struct                                   rs_rx_hdmi21_rx_misc_00_f0

typedef struct _rs_rx_hdmi21_rx_misc_00_f0  rs_rx_hdmi21_rx_misc_00_f0;
struct _rs_rx_hdmi21_rx_misc_00_f0 {
    unsigned int regr_00_misc_0xf0                          :32;
};
#define rx_hdmi21_rx_misc_00_f0(val) ((rs_rx_hdmi21_rx_misc_00_f0*)&(val))



#define RX_HDMI21_RX_MISC_00_F4                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xF4)

#define RX_HDMI21_RX_MISC_00_F4_struct                                   rs_rx_hdmi21_rx_misc_00_f4

typedef struct _rs_rx_hdmi21_rx_misc_00_f4  rs_rx_hdmi21_rx_misc_00_f4;
struct _rs_rx_hdmi21_rx_misc_00_f4 {
    unsigned int regr_00_misc_0xf4                          :32;
};
#define rx_hdmi21_rx_misc_00_f4(val) ((rs_rx_hdmi21_rx_misc_00_f4*)&(val))



#define RX_HDMI21_RX_MISC_00_F8                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xF8)

#define RX_HDMI21_RX_MISC_00_F8_struct                                   rs_rx_hdmi21_rx_misc_00_f8

typedef struct _rs_rx_hdmi21_rx_misc_00_f8  rs_rx_hdmi21_rx_misc_00_f8;
struct _rs_rx_hdmi21_rx_misc_00_f8 {
    unsigned int regr_00_misc_0xf8                          :32;
};
#define rx_hdmi21_rx_misc_00_f8(val) ((rs_rx_hdmi21_rx_misc_00_f8*)&(val))



#define RX_HDMI21_RX_MISC_00_FC                                          (HV_HDMI21_RX_MISC_00_BASE_ADDRESS + 0xFC)

#define RX_HDMI21_RX_MISC_00_FC_struct                                   rs_rx_hdmi21_rx_misc_00_fc

typedef struct _rs_rx_hdmi21_rx_misc_00_fc  rs_rx_hdmi21_rx_misc_00_fc;
struct _rs_rx_hdmi21_rx_misc_00_fc {
    unsigned int regr_00_misc_0xfc                          :32;
};
#define rx_hdmi21_rx_misc_00_fc(val) ((rs_rx_hdmi21_rx_misc_00_fc*)&(val))



#endif