define r
    monitor mips32 cp0 status 0x00400106
    monitor reset
end
document r
    "reset MIPS"
end
define epc 
    monitor mips32 cp0 epc
end
define cause 
    monitor mips32 cp0 cause
end
define status 
    monitor mips32 cp0 status
end



define pec_b_debug_reg
    set *0xb0070040=$arg1 << 24
    set $val=*(unsigned int*)0xb0070044
    set $val=(($val>>24)&0xFF) | (($val>>8)&0xFF00) | (($val & 0xFF00) << 8) | ((($val) & 0xFF) << 24 )
    printf $arg0
    printf ": 0x%08X\n",$val
end

define read_pec_b
    # unlock
    set *0xb0200010=0xffffffff
    set *0xb0070154=0xE2C9243A
    set *0xb0070150=0xDECD0245
    set *0xb0070158=0x0B267835
    set *0xb007015C=0xD64F76E4

    pec_b_debug_reg "PC  " 0x00 
    pec_b_debug_reg "DPC " 0x04 
    pec_b_debug_reg "NPC " 0x08 
    pec_b_debug_reg "EPC " 0x0C 
    pec_b_debug_reg "EXC " 0x10 
    pec_b_debug_reg "PSW " 0x14 
    pec_b_debug_reg "ID  " 0x18 
    pec_b_debug_reg "TMP " 0x1C
    pec_b_debug_reg "VTB " 0x20 
end

define read_pec_b_all
    # unlock
    set *0xb0200010=0xffffffff
    set *0xb0070154=0xE2C9243A
    set *0xb0070150=0xDECD0245
    set *0xb0070158=0x0B267835
    set *0xb007015C=0xD64F76E4

    pec_b_debug_reg "PC  " 0x00 
    pec_b_debug_reg "DPC " 0x04 
    pec_b_debug_reg "NPC " 0x08 
    pec_b_debug_reg "EPC " 0x0C 
    pec_b_debug_reg "EXC " 0x10 
    pec_b_debug_reg "PSW " 0x14 
    pec_b_debug_reg "ID  " 0x18 
    pec_b_debug_reg "TMP " 0x1C
    pec_b_debug_reg "VTB " 0x20 
    pec_b_debug_reg "IMB " 0x24 
    pec_b_debug_reg "ICR0" 0x28 
    pec_b_debug_reg "ICR1" 0x2C 
    pec_b_debug_reg "ICR2" 0x30 
    pec_b_debug_reg "ICR3" 0x34 
    pec_b_debug_reg "DMB " 0x38 
    pec_b_debug_reg "DCR0" 0x3C 
    pec_b_debug_reg "DCR1" 0x40 
    pec_b_debug_reg "DCR2" 0x44 
    pec_b_debug_reg "DCR3" 0x48 
    pec_b_debug_reg "ICB " 0x4C 
    pec_b_debug_reg "CDR0" 0x50 
    pec_b_debug_reg "CDR1" 0x54
    pec_b_debug_reg "CDR2" 0x58 
    pec_b_debug_reg "CDR3" 0x5C 
    pec_b_debug_reg "CDR4" 0x60 
    pec_b_debug_reg "CDR5" 0x64 
    pec_b_debug_reg "CDR6" 0x68 
    pec_b_debug_reg "CDR7" 0x6C 
    pec_b_debug_reg "DBG0" 0x70
    pec_b_debug_reg "DBG1" 0x74
    pec_b_debug_reg "DBG2" 0x78 
end

define pec_c_debug_reg
    set *0xb0070080=$arg1 << 24
    set $val=*(unsigned int*)0xb0070084
    set $val=(($val>>24)&0xFF) | (($val>>8)&0xFF00) | (($val & 0xFF00) << 8) | ((($val) & 0xFF) << 24 )
    printf $arg0
    printf ": 0x%08X\n",$val
end

define read_pec_c
    # unlock
    set *0xb0200010=0xffffffff
    set *0xb007016c=0xC77C3712
    set *0xb0070164=0x72373A81
    set *0xb0070168=0x60AA2514
    set *0xb0070160=0x4AEF5DC6

    pec_c_debug_reg "PC  " 0x00 
    pec_c_debug_reg "DPC " 0x04 
    pec_c_debug_reg "NPC " 0x08 
    pec_c_debug_reg "EPC " 0x0C 
    pec_c_debug_reg "EXC " 0x10 
    pec_c_debug_reg "PSW " 0x14 
    pec_c_debug_reg "VTB " 0x20 
end

define read_pec_c_all
    # unlock
    set *0xb0200010=0xffffffff
    set *0xb007016c=0xC77C3712
    set *0xb0070164=0x72373A81
    set *0xb0070168=0x60AA2514
    set *0xb0070160=0x4AEF5DC6

    pec_c_debug_reg "PC  " 0x00 
    pec_c_debug_reg "DPC " 0x04 
    pec_c_debug_reg "NPC " 0x08 
    pec_c_debug_reg "EPC " 0x0C 
    pec_c_debug_reg "EXC " 0x10 
    pec_c_debug_reg "PSW " 0x14 
    pec_c_debug_reg "ID  " 0x18 
    pec_c_debug_reg "TMP " 0x1C
    pec_c_debug_reg "VTB " 0x20 
    pec_c_debug_reg "IMB " 0x24 
    pec_c_debug_reg "ICR0" 0x28 
    pec_c_debug_reg "ICR1" 0x2C 
    pec_c_debug_reg "ICR2" 0x30 
    pec_c_debug_reg "ICR3" 0x34 
    pec_c_debug_reg "DMB " 0x38 
    pec_c_debug_reg "DCR0" 0x3C 
    pec_c_debug_reg "DCR1" 0x40 
    pec_c_debug_reg "DCR2" 0x44 
    pec_c_debug_reg "DCR3" 0x48 
    pec_c_debug_reg "ICB " 0x4C 
    pec_c_debug_reg "CDR0" 0x50 
    pec_c_debug_reg "CDR1" 0x54
    pec_c_debug_reg "CDR2" 0x58 
    pec_c_debug_reg "CDR3" 0x5C 
    pec_c_debug_reg "CDR4" 0x60 
    pec_c_debug_reg "CDR5" 0x64 
    pec_c_debug_reg "CDR6" 0x68 
    pec_c_debug_reg "CDR7" 0x6C 
    pec_c_debug_reg "DBG0" 0x70
    pec_c_debug_reg "DBG1" 0x74
    pec_c_debug_reg "DBG2" 0x78 
end
