#ifndef _HV_PAGE_HT7315_DPU_ENC_VDM_TOP_01_H_
#define _HV_PAGE_HT7315_DPU_ENC_VDM_TOP_01_H_

#ifndef HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS
    #define HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS                                         0x11022A00
#endif


#define DISP_TOP_DPU_ENC_VDM_TOP_01_00                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x00)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_00_struct                            rs_disp_top_dpu_enc_vdm_top_01_00

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_00  rs_disp_top_dpu_enc_vdm_top_01_00;
struct _rs_disp_top_dpu_enc_vdm_top_01_00 {
    unsigned int reg_01_enc_start_address0                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_00(val) ((rs_disp_top_dpu_enc_vdm_top_01_00*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_04                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x04)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_04_struct                            rs_disp_top_dpu_enc_vdm_top_01_04

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_04  rs_disp_top_dpu_enc_vdm_top_01_04;
struct _rs_disp_top_dpu_enc_vdm_top_01_04 {
    unsigned int reg_01_enc_start_address1                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_04(val) ((rs_disp_top_dpu_enc_vdm_top_01_04*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_08                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x08)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_08_struct                            rs_disp_top_dpu_enc_vdm_top_01_08

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_08  rs_disp_top_dpu_enc_vdm_top_01_08;
struct _rs_disp_top_dpu_enc_vdm_top_01_08 {
    unsigned int reg_01_enc_start_address2                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_08(val) ((rs_disp_top_dpu_enc_vdm_top_01_08*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_0C                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x0C)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_0C_struct                            rs_disp_top_dpu_enc_vdm_top_01_0c

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_0c  rs_disp_top_dpu_enc_vdm_top_01_0c;
struct _rs_disp_top_dpu_enc_vdm_top_01_0c {
    unsigned int reg_01_enc_start_address3                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_0c(val) ((rs_disp_top_dpu_enc_vdm_top_01_0c*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_10                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x10)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_10_struct                            rs_disp_top_dpu_enc_vdm_top_01_10

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_10  rs_disp_top_dpu_enc_vdm_top_01_10;
struct _rs_disp_top_dpu_enc_vdm_top_01_10 {
    unsigned int reg_01_enc_start_address4                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_10(val) ((rs_disp_top_dpu_enc_vdm_top_01_10*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_14                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x14)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_14_struct                            rs_disp_top_dpu_enc_vdm_top_01_14

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_14  rs_disp_top_dpu_enc_vdm_top_01_14;
struct _rs_disp_top_dpu_enc_vdm_top_01_14 {
    unsigned int reg_01_enc_start_address5                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_14(val) ((rs_disp_top_dpu_enc_vdm_top_01_14*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_18                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x18)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_18_struct                            rs_disp_top_dpu_enc_vdm_top_01_18

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_18  rs_disp_top_dpu_enc_vdm_top_01_18;
struct _rs_disp_top_dpu_enc_vdm_top_01_18 {
    unsigned int reg_01_enc_start_address6                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_18(val) ((rs_disp_top_dpu_enc_vdm_top_01_18*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_1C                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x1C)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_1C_struct                            rs_disp_top_dpu_enc_vdm_top_01_1c

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_1c  rs_disp_top_dpu_enc_vdm_top_01_1c;
struct _rs_disp_top_dpu_enc_vdm_top_01_1c {
    unsigned int reg_01_enc_start_address7                  :32;
};
#define disp_top_dpu_enc_vdm_top_01_1c(val) ((rs_disp_top_dpu_enc_vdm_top_01_1c*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_20                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x20)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_20_struct                            rs_disp_top_dpu_enc_vdm_top_01_20

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_20  rs_disp_top_dpu_enc_vdm_top_01_20;
struct _rs_disp_top_dpu_enc_vdm_top_01_20 {
    unsigned int reg_01_enc_end_address0                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_20(val) ((rs_disp_top_dpu_enc_vdm_top_01_20*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_24                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x24)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_24_struct                            rs_disp_top_dpu_enc_vdm_top_01_24

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_24  rs_disp_top_dpu_enc_vdm_top_01_24;
struct _rs_disp_top_dpu_enc_vdm_top_01_24 {
    unsigned int reg_01_enc_end_address1                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_24(val) ((rs_disp_top_dpu_enc_vdm_top_01_24*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_28                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x28)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_28_struct                            rs_disp_top_dpu_enc_vdm_top_01_28

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_28  rs_disp_top_dpu_enc_vdm_top_01_28;
struct _rs_disp_top_dpu_enc_vdm_top_01_28 {
    unsigned int reg_01_enc_end_address2                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_28(val) ((rs_disp_top_dpu_enc_vdm_top_01_28*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_2C                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x2C)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_2C_struct                            rs_disp_top_dpu_enc_vdm_top_01_2c

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_2c  rs_disp_top_dpu_enc_vdm_top_01_2c;
struct _rs_disp_top_dpu_enc_vdm_top_01_2c {
    unsigned int reg_01_enc_end_address3                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_2c(val) ((rs_disp_top_dpu_enc_vdm_top_01_2c*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_30                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x30)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_30_struct                            rs_disp_top_dpu_enc_vdm_top_01_30

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_30  rs_disp_top_dpu_enc_vdm_top_01_30;
struct _rs_disp_top_dpu_enc_vdm_top_01_30 {
    unsigned int reg_01_enc_end_address4                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_30(val) ((rs_disp_top_dpu_enc_vdm_top_01_30*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_34                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x34)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_34_struct                            rs_disp_top_dpu_enc_vdm_top_01_34

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_34  rs_disp_top_dpu_enc_vdm_top_01_34;
struct _rs_disp_top_dpu_enc_vdm_top_01_34 {
    unsigned int reg_01_enc_end_address5                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_34(val) ((rs_disp_top_dpu_enc_vdm_top_01_34*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_38                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x38)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_38_struct                            rs_disp_top_dpu_enc_vdm_top_01_38

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_38  rs_disp_top_dpu_enc_vdm_top_01_38;
struct _rs_disp_top_dpu_enc_vdm_top_01_38 {
    unsigned int reg_01_enc_end_address6                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_38(val) ((rs_disp_top_dpu_enc_vdm_top_01_38*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_3C                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x3C)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_3C_struct                            rs_disp_top_dpu_enc_vdm_top_01_3c

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_3c  rs_disp_top_dpu_enc_vdm_top_01_3c;
struct _rs_disp_top_dpu_enc_vdm_top_01_3c {
    unsigned int reg_01_enc_end_address7                    :32;
};
#define disp_top_dpu_enc_vdm_top_01_3c(val) ((rs_disp_top_dpu_enc_vdm_top_01_3c*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_40                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x40)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_40_struct                            rs_disp_top_dpu_enc_vdm_top_01_40

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_40  rs_disp_top_dpu_enc_vdm_top_01_40;
struct _rs_disp_top_dpu_enc_vdm_top_01_40 {
    unsigned int reg_01_enc_line_offset_addr                :32;
};
#define disp_top_dpu_enc_vdm_top_01_40(val) ((rs_disp_top_dpu_enc_vdm_top_01_40*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_44                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x44)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_44_struct                            rs_disp_top_dpu_enc_vdm_top_01_44

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_44  rs_disp_top_dpu_enc_vdm_top_01_44;
struct _rs_disp_top_dpu_enc_vdm_top_01_44 {
    unsigned int reg_01_enc_alen                            : 8;
    unsigned int reg_01_enc_qos                             : 8;
    unsigned int reg_01_enc_cmdlen                          : 4;
    unsigned int reg_01_enc_write_enable                    : 1;
    unsigned int reg_01_enc_mode                            : 1;
    unsigned int reg_01_enc_disable_frame_hold              : 1;
    unsigned int reg_01_enc_dynamic_crc_enable              : 1;
    unsigned int reg_01_enc_write_err_clr                   : 1;
    unsigned int reg_01_en                                  : 1;
    unsigned int reg_01_en_no_latch                         : 1;
    unsigned int reserved                                   : 5;
};
#define disp_top_dpu_enc_vdm_top_01_44(val) ((rs_disp_top_dpu_enc_vdm_top_01_44*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_48                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x48)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_48_struct                            rs_disp_top_dpu_enc_vdm_top_01_48

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_48  rs_disp_top_dpu_enc_vdm_top_01_48;
struct _rs_disp_top_dpu_enc_vdm_top_01_48 {
    unsigned int reg_01_enc_threshold_m                     : 9;
    unsigned int reg_01_enc_threshold_n                     : 9;
    unsigned int reserved                                   :14;
};
#define disp_top_dpu_enc_vdm_top_01_48(val) ((rs_disp_top_dpu_enc_vdm_top_01_48*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_54                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x54)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_54_struct                            rs_disp_top_dpu_enc_vdm_top_01_54

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_54  rs_disp_top_dpu_enc_vdm_top_01_54;
struct _rs_disp_top_dpu_enc_vdm_top_01_54 {
    unsigned int reg_01_enc_vtotal                          :12;
    unsigned int reserved                                   :20;
};
#define disp_top_dpu_enc_vdm_top_01_54(val) ((rs_disp_top_dpu_enc_vdm_top_01_54*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_58                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x58)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_58_struct                            rs_disp_top_dpu_enc_vdm_top_01_58

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_58  rs_disp_top_dpu_enc_vdm_top_01_58;
struct _rs_disp_top_dpu_enc_vdm_top_01_58 {
    unsigned int reg_01_enc_mode422_enable                  : 1;
    unsigned int reg_01_enc_wr_clr_sel                      : 2;
    unsigned int reg_01_enc_debug_header_en                 : 1;
    unsigned int reserved                                   : 1;
    unsigned int reg_01_enc_4k_proc_enable                  : 1;
    unsigned int reg_01_enc_cmdlength_enable                : 1;
    unsigned int reg_01_enc_sram_ls_en                      : 1;
    unsigned int reg_01_enc_sram_ls_value                   : 1;
    unsigned int reg_01_enc_axibus_protect_en               : 1;
    unsigned int reserved_1                                 :22;
};
#define disp_top_dpu_enc_vdm_top_01_58(val) ((rs_disp_top_dpu_enc_vdm_top_01_58*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_5C                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x5C)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_5C_struct                            rs_disp_top_dpu_enc_vdm_top_01_5c

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_5c  rs_disp_top_dpu_enc_vdm_top_01_5c;
struct _rs_disp_top_dpu_enc_vdm_top_01_5c {
    unsigned int reg_01_enc_debug_head_ll                   :32;
};
#define disp_top_dpu_enc_vdm_top_01_5c(val) ((rs_disp_top_dpu_enc_vdm_top_01_5c*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_60                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x60)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_60_struct                            rs_disp_top_dpu_enc_vdm_top_01_60

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_60  rs_disp_top_dpu_enc_vdm_top_01_60;
struct _rs_disp_top_dpu_enc_vdm_top_01_60 {
    unsigned int reg_01_enc_debug_head_lh                   :32;
};
#define disp_top_dpu_enc_vdm_top_01_60(val) ((rs_disp_top_dpu_enc_vdm_top_01_60*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_64                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x64)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_64_struct                            rs_disp_top_dpu_enc_vdm_top_01_64

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_64  rs_disp_top_dpu_enc_vdm_top_01_64;
struct _rs_disp_top_dpu_enc_vdm_top_01_64 {
    unsigned int reg_01_enc_debug_head_hl                   :32;
};
#define disp_top_dpu_enc_vdm_top_01_64(val) ((rs_disp_top_dpu_enc_vdm_top_01_64*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_68                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x68)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_68_struct                            rs_disp_top_dpu_enc_vdm_top_01_68

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_68  rs_disp_top_dpu_enc_vdm_top_01_68;
struct _rs_disp_top_dpu_enc_vdm_top_01_68 {
    unsigned int reg_01_enc_debug_head_hh                   :32;
};
#define disp_top_dpu_enc_vdm_top_01_68(val) ((rs_disp_top_dpu_enc_vdm_top_01_68*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_6C                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x6C)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_6C_struct                            rs_disp_top_dpu_enc_vdm_top_01_6c

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_6c  rs_disp_top_dpu_enc_vdm_top_01_6c;
struct _rs_disp_top_dpu_enc_vdm_top_01_6c {
    unsigned int reg_01_enc_dm_frmbuf_num                   : 4;
    unsigned int reg_01_enc_dm_frmbuf_gap                   : 4;
    unsigned int reg_01_enc_dm_frmbuf_mode                  : 1;
    unsigned int reserved                                   : 7;
    unsigned int reg_01_enc_dm_00_frmbuf_hold_en            : 1;
    unsigned int reg_01_enc_dm_00_frmbuf_hold_idx           : 3;
    unsigned int reserved_1                                 :12;
};
#define disp_top_dpu_enc_vdm_top_01_6c(val) ((rs_disp_top_dpu_enc_vdm_top_01_6c*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_70                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x70)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_70_struct                            rs_disp_top_dpu_enc_vdm_top_01_70

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_70  rs_disp_top_dpu_enc_vdm_top_01_70;
struct _rs_disp_top_dpu_enc_vdm_top_01_70 {
    unsigned int mem_reg_01_0                               : 8;
    unsigned int mem_reg_01_1                               : 8;
    unsigned int mem_reg_01_2                               : 8;
    unsigned int mem_reg_01_3                               : 8;
};
#define disp_top_dpu_enc_vdm_top_01_70(val) ((rs_disp_top_dpu_enc_vdm_top_01_70*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_74                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x74)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_74_struct                            rs_disp_top_dpu_enc_vdm_top_01_74

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_74  rs_disp_top_dpu_enc_vdm_top_01_74;
struct _rs_disp_top_dpu_enc_vdm_top_01_74 {
    unsigned int reg_01_mem_ema_0                           :16;
    unsigned int reg_01_mem_ema_1                           :16;
};
#define disp_top_dpu_enc_vdm_top_01_74(val) ((rs_disp_top_dpu_enc_vdm_top_01_74*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_78                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0x78)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_78_struct                            rs_disp_top_dpu_enc_vdm_top_01_78

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_78  rs_disp_top_dpu_enc_vdm_top_01_78;
struct _rs_disp_top_dpu_enc_vdm_top_01_78 {
    unsigned int reg_01_mem_ema_2                           :16;
    unsigned int reg_01_mem_ema_3                           :16;
};
#define disp_top_dpu_enc_vdm_top_01_78(val) ((rs_disp_top_dpu_enc_vdm_top_01_78*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_F0                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0xF0)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_F0_struct                            rs_disp_top_dpu_enc_vdm_top_01_f0

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_f0  rs_disp_top_dpu_enc_vdm_top_01_f0;
struct _rs_disp_top_dpu_enc_vdm_top_01_f0 {
    unsigned int regr_01_enc_00_headernum                   :12;
    unsigned int regr_01_enc_00_headerfail                  : 1;
    unsigned int regr_01_enc_00_enc_no_last                 : 1;
    unsigned int regr_01_enc_00_wram_rw_err                 : 1;
    unsigned int regr_01_enc_00_fail                        : 1;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_enc_vdm_top_01_f0(val) ((rs_disp_top_dpu_enc_vdm_top_01_f0*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_F4                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0xF4)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_F4_struct                            rs_disp_top_dpu_enc_vdm_top_01_f4

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_f4  rs_disp_top_dpu_enc_vdm_top_01_f4;
struct _rs_disp_top_dpu_enc_vdm_top_01_f4 {
    unsigned int reg_01_enc_dynamic_crc_out_h               :32;
};
#define disp_top_dpu_enc_vdm_top_01_f4(val) ((rs_disp_top_dpu_enc_vdm_top_01_f4*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_F8                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0xF8)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_F8_struct                            rs_disp_top_dpu_enc_vdm_top_01_f8

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_f8  rs_disp_top_dpu_enc_vdm_top_01_f8;
struct _rs_disp_top_dpu_enc_vdm_top_01_f8 {
    unsigned int reg_01_enc_dynamic_crc_out_l               :32;
};
#define disp_top_dpu_enc_vdm_top_01_f8(val) ((rs_disp_top_dpu_enc_vdm_top_01_f8*)&(val))



#define DISP_TOP_DPU_ENC_VDM_TOP_01_FC                                   (HV_DPU_ENC_VDM_TOP_01_BASE_ADDRESS + 0xFC)

#define DISP_TOP_DPU_ENC_VDM_TOP_01_FC_struct                            rs_disp_top_dpu_enc_vdm_top_01_fc

typedef struct _rs_disp_top_dpu_enc_vdm_top_01_fc  rs_disp_top_dpu_enc_vdm_top_01_fc;
struct _rs_disp_top_dpu_enc_vdm_top_01_fc {
    unsigned int reg_01_mem_ro_0                            : 4;
    unsigned int reg_01_mem_ro_1                            : 4;
    unsigned int reg_01_mem_ro_2                            : 4;
    unsigned int reg_01_mem_ro_3                            : 4;
    unsigned int reserved                                   :16;
};
#define disp_top_dpu_enc_vdm_top_01_fc(val) ((rs_disp_top_dpu_enc_vdm_top_01_fc*)&(val))



#endif