/**
 * @file hv_chip_clk.h
 * @brief define clk for silicon platform
 * @details anyware
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-09-05
 * @copyright 版权信息
*/
#ifndef _HV_CHIP_CLK_H
#define _HV_CHIP_CLK_H

/**
 * @brief cpu clk \n
 * @details cpu clk is 594M for silicon
 * apb clk is 198M for silicon \n
 */

#define HV_CHIP_CLK_BASE           621000000
/* O0-7 O2-5 */
#define HV_CHIP_DELAY_CLK          124
#define HV_CHIP_CLK_CPU            HV_CHIP_CLK_BASE
#define HV_CHIP_CLK_AHB           (191000000)
#define HV_CHIP_CLK_APB           (191000000)
#define HV_CHIP_CLK_APB_INT_ACTUAL  (191)
#define HV_CHIP_CLK_APB_FRAC_ACTUAL (077)
#define HV_CHIP_CLK_DATAPATH_MAX   740000


#endif