/** * @file BoardConfig.h * @brief Header file of Board Config. * * @verbatim * ============================================================================== * ##### How to use ##### * ============================================================================== * * @ endverbatim * * @author HiView SoC Software Team * @version 1.0.0 * @date 2022-08-26 */ #ifndef __DEVICE_HI_VIEW_HT7315_BOARDCONFIG_H__ #define __DEVICE_HI_VIEW_HT7315_BOARDCONFIG_H__ /************************************************* Board Option *************************************************/ #define HV_BOARD_CONFIG_NAME "HV_HT7315_EVB_01" #define HV_BOARD_CONFIG_VER "0.01" /************************************************* Gpio config *************************************************/ #define HV_BOARD_CONFIG_GPIO_HF_DET_1 (57) #define HV_BOARD_CONFIG_GPIO_LED_B (61) #define HV_BOARD_CONFIG_GPIO_PA_MUTE_CTL (63) #define HV_BOARD_CONFIG_GPIO_PA_SHDN_CTL (64) #define HV_BOARD_CONFIG_GPIO_LED_R (161) #define HV_BOARD_CONFIG_GPIO_SCALER_EE_WP (162) #define HV_BOARD_CONFIG_GPIO_RX_AP_EN (162) /* samsung water drop */ #define HV_BOARD_CONFIG_GPIO_E2_WP (194) #define HV_BOARD_CONFIG_GPIO_HDMI1_RX_DDC1_SCL (208) #define HV_BOARD_CONFIG_GPIO_HDMI1_RX_DDC1_SDA (209) #define HV_BOARD_CONFIG_GPIO_PANEL_EN (210) #define HV_BOARD_CONFIG_GPIO_BLK_EN (96) #define HV_BOARD_CONFIG_GPIO_VBUS_DISCHA (211) #define HV_BOARD_CONFIG_GPIO_VBUS_PMU_EN (213) #define HV_BOARD_CONFIG_GPIO_GP_PD_PW_S (214) #define HV_BOARD_CONFIG_GPIO_CC_RD_CTL (216) #define HV_BOARD_CONFIG_GPIO_PANEL_SEQUENCE_TEST (0xFF) /* TODO customize define*/ /************************************************* Port Option *************************************************/ #define PORT_VALID 1 #define PORT_INVALID 0 #define HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM 2 #define HV_BOARD_CONFIG_MAX_HDCP_PORT_NUM 2 #define HV_BOARD_CONFIG_MAX_DP_PORT_NUM 2 #define HV_BOARD_CONFIG_MAX_RXPLL_PORT_NUM 2 #define HV_BOARD_CONFIG_MAX_TYPEC_PORT_NUM 2 #define HV_BOARD_CONFIG_DISPLAYPORT_0 PORT_VALID #define HV_BOARD_CONFIG_HDMI_0 PORT_VALID #define HV_BOARD_CONFIG_DISPLAYPORT_1 PORT_VALID #define HV_BOARD_CONFIG_HDMI_1 PORT_VALID #define HDMI_LANE0 0 #define HDMI_LANE1 1 #define HDMI_LANE2 2 #define HDMI_CLK 3 /* HDMI0 INNER LANE <----> OUTER LANE */ /*34,35 == Lane0 PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI0_LANE0 HDMI_LANE2 /*31,32 == Lane1 PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI0_LANE1 HDMI_LANE1 /*28,29 == Lane2 PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI0_LANE2 HDMI_LANE0 /*25,26 == Clock PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI0_CLK HDMI_CLK /* HDMI1 INNER LANE <----> OUTER LANE */ /*46,47 == Lane0 PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI1_LANE0 HDMI_LANE2 /*43,44 == Lane1 PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI1_LANE1 HDMI_LANE1 /*40,41 == Lane2 PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI1_LANE2 HDMI_LANE0 /*37,38 == Clock PIN for the outer HDMI Lane */ #define HV_BOARD_CONFIG_HDMI1_CLK HDMI_CLK #define HV_BOARD_CONFIG_HDMI0_INV_PN 0xF #define HV_BOARD_CONFIG_HDMI1_INV_PN 0xF #define HV_BOARD_CONFIG_HDMI0_LANE_SWP ((HV_BOARD_CONFIG_HDMI0_CLK << 6) |\ (HV_BOARD_CONFIG_HDMI0_LANE2 << 4) |\ (HV_BOARD_CONFIG_HDMI0_LANE1 << 2) |\ (HV_BOARD_CONFIG_HDMI0_LANE0)) #define HV_BOARD_CONFIG_HDMI1_LANE_SWP ((HV_BOARD_CONFIG_HDMI1_CLK << 6) |\ (HV_BOARD_CONFIG_HDMI1_LANE2 << 4) |\ (HV_BOARD_CONFIG_HDMI1_LANE1 << 2) |\ (HV_BOARD_CONFIG_HDMI1_LANE0)) #define HV_BOARD_CONFIG_HDMI_HPD_SOURCE_5V 0 #define HV_BOARD_CONFIG_HDMI_HPD_5V 0 #define CABLE_DETECT_WITH_GROUND_VOL 0 #define CABLE_DETECT_WITH_SOURCE_5V 1 #define HV_BOARD_CONFIG_HDMI_CABLE_DETECT CABLE_DETECT_WITH_GROUND_VOL #if ((HV_BOARD_CONFIG_HDMI0_CLK != HDMI_CLK) && (HV_BOARD_CONFIG_HDMI0_LANE0 != HDMI_CLK)) #error "HDMI0 lane swap ERROR" #endif #if ((HV_BOARD_CONFIG_HDMI1_CLK != HDMI_CLK) && (HV_BOARD_CONFIG_HDMI1_LANE0 != HDMI_CLK)) #error "HDMI1 lane swap ERROR" #endif #define DP_PORT_NORM 0 #define DP_PORT_ALTMODE 1 #define DP_LANE0 0 #define DP_LANE1 1 #define DP_LANE2 2 #define DP_LANE3 3 /* DP INNER LANE <----> OUTER LANE */ #define HV_BOARD_CONFIG_DP0_LANE0 DP_LANE0 #define HV_BOARD_CONFIG_DP0_LANE1 DP_LANE1 #define HV_BOARD_CONFIG_DP0_LANE2 DP_LANE3 #define HV_BOARD_CONFIG_DP0_LANE3 DP_LANE2 #define HV_BOARD_CONFIG_DP1_LANE0 DP_LANE3 #define HV_BOARD_CONFIG_DP1_LANE1 DP_LANE2 #define HV_BOARD_CONFIG_DP1_LANE2 DP_LANE1 #define HV_BOARD_CONFIG_DP1_LANE3 DP_LANE0 #define HV_BOARD_CONFIG_DP0_AUX_POLARITY 0x1 #define HV_BOARD_CONFIG_DP1_AUX_POLARITY 0x0 #define HV_BORAD_CONFIG_DP0_LANE_POLARITY 0xA #define HV_BORAD_CONFIG_DP1_LANE_POLARITY 0x0 #define HV_BOARD_CONFIG_DP0_TYPE DP_PORT_ALTMODE #define HV_BOARD_CONFIG_DP1_TYPE DP_PORT_NORM #define HV_BOARD_CONFIG_TYPEC0_TO_DP LINK_PORT_INDEX_DP_RX0 #define HV_BOARD_CONFIG_TYPEC1_TO_DP LINK_PORT_INDEX_DP_RX1 #define HV_BOARD_CONFIG_DP0_TO_TYPEC 0 #define HV_BOARD_CONFIG_DP1_TO_TYPEC 1 #define HV_BOARD_CONFIG_SPEAKER #define HV_BOARD_CONFIG_HEADSET_GPIO_STATE_PULL_OUT GPIO_LEVEL_HIGH #define HV_BOARD_CONFIG_HEADSET_GPIO_STATE_INSERT GPIO_LEVEL_LOW #define HV_BOARD_CONFIG_PA_MUTE_ENABLE GPIO_LEVEL_HIGH #define HV_BOARD_CONFIG_PA_MUTE_DISABLE GPIO_LEVEL_LOW #define HV_BOARD_CONFIG_PA_SHDN_ENABLE GPIO_LEVEL_HIGH #define HV_BOARD_CONFIG_PA_SHDN_DISABLE GPIO_LEVEL_LOW /************************************************* eeprom i2c config bus config: typedef enum _I2cBusID{ I2CM0, I2CS0, MI2C, SIMI2C0, SIMI2C1, SIMI2C2, }I2cBusID; *************************************************/ /* typec pmic */ #define PMIC_I2CM0 0 #define PMIC_SIMI2C0 1 #define PMIC_GPIO 2 #define HV_BOARD_CONFIG_PMIC_MODE PMIC_I2CM0 /* #define HV_BOARD_CONFIG_PMIC_SIMI2C SIMI2C1 */ #define HV_BOARD_CONFIG_PMIC_ADDR (0x60) /* scaler e2p */ #define HV_BOARD_CONFIG_E2P_USE_MI2C #define HV_BOARD_CONFIG_E2P_TYPE_2 E2P_TYPE_16K_128PAGES_16BYTE #define HV_BOARD_CONFIG_E2P_ADDR_2 (0xA8) #define HV_BOARD_CONFIG_E2P_WP_GPIO_2 HV_BOARD_CONFIG_GPIO_SCALER_EE_WP #define HV_BOARD_CONFIG_E2P_WP_PROTECT_LEVEL_2 1 /* hdmi0 edid */ #define HV_BOARD_CONFIG_E2P_USE_I2CS0 #define HV_BOARD_CONFIG_E2P_TYPE_1 E2P_TYPE_2K_16PAGES_16BYTE #define HV_BOARD_CONFIG_E2P_ADDR_1 (0x50) #define HV_BOARD_CONFIG_E2P_WP_GPIO_1 HV_BOARD_CONFIG_GPIO_E2_WP #define HV_BOARD_CONFIG_E2P_WP_PROTECT_LEVEL_1 1 /* hdmi1 edid */ #define HV_BOARD_CONFIG_E2P_USE_SIMI2C0 #define HV_BOARD_CONFIG_E2P_TYPE_3 E2P_TYPE_2K_16PAGES_16BYTE #define HV_BOARD_CONFIG_E2P_ADDR_3 (0xA0) #define HV_BOARD_CONFIG_E2P_WP_GPIO_3 HV_BOARD_CONFIG_GPIO_E2_WP #define HV_BOARD_CONFIG_E2P_WP_PROTECT_LEVEL_3 1 #define SIMI2C_SCL HV_BOARD_CONFIG_GPIO_HDMI1_RX_DDC1_SCL #define SIMI2C_SDA HV_BOARD_CONFIG_GPIO_HDMI1_RX_DDC1_SDA #define STORAGE_EEPROM 0 #define STORAGE_SPI_FLASH 1 #define HV_BOARD_CONFIG_DATABASE_STORAGE_TYPE STORAGE_SPI_FLASH #define HV_BOARD_CONFIG_LED_B_PWM 2 #define HV_BOARD_CONFIG_LED_B_POL 0 #endif