/*
 * set_gpr_boot_values.S
 *
*/
/*
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*/
#include <mips/asm.h>
#include <boot.h>
#include <mips/m32c0.h>
#include <mips/regdef.h>

// defines not yet in m32c0.h
#define C0_MVPCTL $0, 1
#define C0_MVPCONF0 $0, 2
#define C0_VPECTL $1, 1
#define C0_VPECONF0 $1, 2
#define C0_TCSTATUS $2, 1
#define C0_TCRESTART $2, 3
#define C0_TCHALT $2, 4
#define C0_TCBIND $2, 2

/**************************************************************************************
**************************************************************************************/
LEAF(set_gpr_boot_values)

    mfc0    a0, C0_EBASE                        // Read CP0 EBase
    ext        r23_cpu_num, a0, 0, 4                // Extract CPUNum

    la      gp, _gp                                // All vpe share globals.
    la      sp, __boot_stack                       // Set up stack base.
//  ins     sp, r23_cpu_num, STACK_SIZE_LOG2       // only one VPE, use arbitrary stack

    // Every vpe will set up the following to simplify resource initialization.
    mfc0    a0, C0_TCBIND                        // Read CP0 TCBind
    ext        r9_vpe_num, a0,  0, 4                // Extract CurVPE
    ext        r18_tc_num, a0, 21, 8                // Extract CurTC
    mfc0    a0, C0_MVPCONF0                        // C0_MVPConf0
    ext        r21_more_tcs, a0, 0, 8                // Extract PTC
    ext        r20_more_vpes, a0, 10, 4            // Extract VPE

is_not_cps: // This processor is not part of a Coherent Processing System. Set up valid defaults.
    li      r11_is_cps, 0
    li      r8_core_num, 0
    li         r19_more_cores, 0

done_init_gpr:
    jr      ra
END(set_gpr_boot_values)