/*
 * init_cp0.S
 *
 *  Common CP0 register initializations
*/
/*
Copyright (c) 2007-2018, MIPS Tech, LLC and/or its affiliated group companies or licensors

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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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*/
#include <mips/asm.h>
#include <core_config.h>
#include <mips/regdef.h>
#include <mips/m32c0.h>

/**************************************************************************************
**************************************************************************************/
LEAF(init_cp0)

    // Initialize Status
    li        a1, 0x00400404        // (M_StatusERL | M_StatusIPL1 | M_StatusBEV)
    mtc0    a1, C0_STATUS        // write C0_Status

    // Initialize Watch registers if implemented.
    mfc0    a0, C0_CONFIG1        // read C0_Config1
    ext        a1, a0, 3, 1        // extract bit 3 WR (Watch registers implemented)
    beq     a1, zero, done_wr

    li        a1, 0x7                // (M_WatchHiI | M_WatchHiR | M_WatchHiW)

    // Clear Watch Status bits and disable watch exceptions
    mtc0    a1, C0_WATCHHI        // write C0_WatchHi0
    mtc0    zero, C0_WATCHLO    // write C0_WatchLo0

    mtc0    a1, C0_WATCHHI, 1    // write C0_WatchHi1
    mtc0    zero, C0_WATCHLO, 1    // write C0_WatchLo1

    mtc0    a1, C0_WATCHHI, 2    // write C0_WatchHi2
    mtc0    zero, C0_WATCHLO, 2    // write C0_WatchLo2

    mtc0    a1, C0_WATCHHI, 3    // write C0_WatchHi3
    mtc0    zero, C0_WATCHLO, 3    // write C0_WatchLo3

    mtc0    a1, C0_WATCHHI, 4    // write C0_WatchHi4
    mtc0    zero, C0_WATCHLO, 4    // write C0_WatchLo4

    mtc0    a1, C0_WATCHHI, 5    // write C0_WatchHi5
    mtc0    zero, C0_WATCHLO, 5    // write C0_WatchLo5

    mtc0    a1, C0_WATCHHI, 6    // write C0_WatchHi6
    mtc0    zero, C0_WATCHLO, 6    // write C0_WatchLo6

    mtc0    a1, C0_WATCHHI, 7    // write C0_WatchHi7
    mtc0    zero, C0_WATCHLO, 7    // write C0_WatchLo7

done_wr:

    // Clear WP bit to avoid watch exception upon user code entry, IV, and software interrupts.
    mtc0    zero, C0_CAUSE        // write C0_Cause: Init AFTER init of CP0 WatchHi/Lo registers.

    // Clear timer interrupt. (Count was cleared at the reset vector to allow timing boot.)
    mtc0    zero, C0_COMPARE    // write C0_Compare

    jr      ra
END(init_cp0)