/**
 * @file hv_chip_debug.h
 * @brief define uart debug interface
 * @details anyware
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2023-02-27
 * @copyright Copyright(c),2023-2, Hiview Software. All rights reserved.
*/
#ifndef _HV_CHIP_DEBUG_DUMMY_H
#define _HV_CHIP_DEBUG_DUMMY_H

#define SW_DUMMY_DEBUG
/*****************************************************************/
/*                         SW0 BIGIN                             */
/*****************************************************************/

/* power state  sw0 00-1c */
#define SW_DUMMY_JTAG           SYS_REG_SH5_TOP2_00

/* flash address for some partition */
#define SW_DUMMY_CONFIG_DATA    SYS_REG_SH5_TOP2_04
#define SW_DUMMY_LOGO           SYS_REG_SH5_TOP2_08
#define SW_DUMMY_PQ_DATA        SYS_REG_SH5_TOP2_0C

#define SW_DUMMY_DUMMY1         SYS_REG_SH5_TOP2_10
#define SW_DUMMY_DUMMY2         SYS_REG_SH5_TOP2_14

/* cpu register sw0 20-dc */
#define SW_DUMMY_AT             SYS_REG_SH5_TOP2_24
#define SW_DUMMY_V0             SYS_REG_SH5_TOP2_28
#define SW_DUMMY_V1             SYS_REG_SH5_TOP2_2C
#define SW_DUMMY_A0             SYS_REG_SH5_TOP2_30
#define SW_DUMMY_A1             SYS_REG_SH5_TOP2_34
#define SW_DUMMY_A2             SYS_REG_SH5_TOP2_38
#define SW_DUMMY_A3             SYS_REG_SH5_TOP2_3C

#define SW_DUMMY_T0             SYS_REG_SH5_TOP2_40
#define SW_DUMMY_T1             SYS_REG_SH5_TOP2_44
#define SW_DUMMY_T2             SYS_REG_SH5_TOP2_48
#define SW_DUMMY_T3             SYS_REG_SH5_TOP2_4C
#define SW_DUMMY_T4             SYS_REG_SH5_TOP2_50
#define SW_DUMMY_T5             SYS_REG_SH5_TOP2_54
#define SW_DUMMY_T6             SYS_REG_SH5_TOP2_58
#define SW_DUMMY_T7             SYS_REG_SH5_TOP2_5C

#define SW_DUMMY_S0             SYS_REG_SH5_TOP2_60
#define SW_DUMMY_S1             SYS_REG_SH5_TOP2_64
#define SW_DUMMY_S2             SYS_REG_SH5_TOP2_68
#define SW_DUMMY_S3             SYS_REG_SH5_TOP2_6C
#define SW_DUMMY_S4             SYS_REG_SH5_TOP2_70
#define SW_DUMMY_S5             SYS_REG_SH5_TOP2_74
#define SW_DUMMY_S6             SYS_REG_SH5_TOP2_78
#define SW_DUMMY_S7             SYS_REG_SH5_TOP2_7C

#define SW_DUMMY_T8             SYS_REG_SH5_TOP2_80
#define SW_DUMMY_T9             SYS_REG_SH5_TOP2_84
#define SW_DUMMY_K0             SYS_REG_SH5_TOP2_88
#define SW_DUMMY_K1             SYS_REG_SH5_TOP2_8C

#define SW_DUMMY_GP             SYS_REG_SH5_TOP2_90
#define SW_DUMMY_SP             SYS_REG_SH5_TOP2_94
#define SW_DUMMY_FP             SYS_REG_SH5_TOP2_98
#define SW_DUMMY_RA             SYS_REG_SH5_TOP2_9C

#define SW_DUMMY_EPC            SYS_REG_SH5_TOP2_A0
#define SW_DUMMY_BADVADDR       SYS_REG_SH5_TOP2_A4
#define SW_DUMMY_STATUS         SYS_REG_SH5_TOP2_A8
#define SW_DUMMY_CAUSE          SYS_REG_SH5_TOP2_AC

#define SW_DUMMY_BADISTR        SYS_REG_SH5_TOP2_B0
#define SW_DUMMY_BADPISTR       SYS_REG_SH5_TOP2_B4

/* cpu int sw0 e0-fc */

/*****************************************************************/
/*                         SW1 BIGIN                             */
/*****************************************************************/

/* peripherial0     sw1 00-0c */

/* peripherial1     sw1 10-1c */

/* hdcp             sw1 20-28 */
#define SW_DUMMY_TYPEC_DEBUG    SYS_REG_SH5_TOP3_20
/* task             sw1 28-3c */
#define SW_DUMMY_URGENT_TASK    SYS_REG_SH5_TOP3_28
#define SW_DUMMY_SM_TASK        SYS_REG_SH5_TOP3_30
#define SW_DUMMY_OSD_TASK       SYS_REG_SH5_TOP3_34
#define SW_DUMMY_EVENT_TASK     SYS_REG_SH5_TOP3_38
#define SW_DUMMY_USB_TASK       SYS_REG_SH5_TOP3_3C
/* dprx             sw1 40-4c */
/* hdmirx           sw1 50-5c */
/* audio            sw1 60-6c */
/* osd              sw1 70-7c */
/* panel            sw1 80-8c */
#define SW_DUMMY_PQTOOL_EDID0    SYS_REG_SH5_TOP3_40//for debug
#define SW_DUMMY_PQTOOL_EDID1    SYS_REG_SH5_TOP3_44//for debug

#define SW_DUMMY_PQTOOL_FAC_HDMIEDID    SYS_REG_SH5_TOP3_50
#define SW_DUMMY_PQTOOL_FAC_DPEDID    SYS_REG_SH5_TOP3_54
#define SW_DUMMY_PQTOOL_FAC_HDMI1EDID    SYS_REG_SH5_TOP3_58
#define SW_DUMMY_PQTOOL_FAC_DP1EDID    SYS_REG_SH5_TOP3_5C

#define SW_DUMMY_PQTOOL_CMD     SYS_REG_SH5_TOP3_80
#define SW_DUMMY_PQTOOL_DATA0   SYS_REG_SH5_TOP3_84
#define SW_DUMMY_PQTOOL_DATA1   SYS_REG_SH5_TOP3_88
#define SW_DUMMY_PQTOOL_DATA2   SYS_REG_SH5_TOP3_8C
#define SW_DUMMY_PQTOOL_DATA3   SYS_REG_SH5_TOP3_90
#define SW_DUMMY_PQTOOL_DATA4   SYS_REG_SH5_TOP3_94
#define SW_DUMMY_PQTOOL_DATA5   SYS_REG_SH5_TOP3_98

/*TOOL*/
#define SW_DUMMY_PQTOOL_LDC_LUTUPDATE   SYS_REG_SH5_TOP3_A8
#define SW_DUMMY_PQTOOL_HDR_PATDETECT   SYS_REG_SH5_TOP3_AC
#define SW_DUMMY_PQTOOL_FAC_BRIGHTNESS  SYS_REG_SH5_TOP3_B0
#define SW_DUMMY_PQTOOL_FAC_LANGUAGE    SYS_REG_SH5_TOP3_B4
#define SW_DUMMY_PQTOOL_FAC_GAMUT       SYS_REG_SH5_TOP3_B8
#define SW_DUMMY_PQTOOL_FAC_CONTRAST    SYS_REG_SH5_TOP3_BC

#define SW_DUMMY_PQTOOL_CSC_BIN     SYS_REG_SH5_TOP3_C0
#define SW_DUMMY_PQTOOL_CSC_MAINHDB SYS_REG_SH5_TOP3_C4
#define SW_DUMMY_PQTOOL_CSC_SUBHDB  SYS_REG_SH5_TOP3_C8
#define SW_DUMMY_PQTOOL_GC_LUT      SYS_REG_SH5_TOP3_CC
#define SW_DUMMY_PQTOOL_LDC_LUT     SYS_REG_SH5_TOP3_D0
#define SW_DUMMY_PQTOOL_WCG_LUT     SYS_REG_SH5_TOP3_D4
#define SW_DUMMY_PQTOOL_GAMMA_LUT   SYS_REG_SH5_TOP3_D8
#define SW_DUMMY_PQTOOL_CM64        SYS_REG_SH5_TOP3_DC

/*For Factory Use*/
#define SW_DUMMY_PQTOOL_FAC_COLORTEMP   SYS_REG_SH5_TOP3_E0
#define SW_DUMMY_PQTOOL_FAC_GAMMA       SYS_REG_SH5_TOP3_E4
#define SW_DUMMY_PQTOOL_FAC_PSN         SYS_REG_SH5_TOP3_E8
#define SW_DUMMY_PQTOOL_FAC_HDCP        SYS_REG_SH5_TOP3_EC
#define SW_DUMMY_PQTOOL_FAC_WEEK        SYS_REG_SH5_TOP3_F0
#define SW_DUMMY_PQTOOL_FAC_MODIFY      SYS_REG_SH5_TOP3_F4
#define SW_DUMMY_PQTOOL_GAMMA_MODIFY    SYS_REG_SH5_TOP3_F8
#define SW_DUMMY_PQTOOL_FAC_FACTORYMODE SYS_REG_SH5_TOP3_FC


#endif