hv_drv_Flash.c 146 KB

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  1. /**
  2. * @file hv_drv_Flash.c
  3. * @brief flash driver api layer file.
  4. * @details This file provides the following functions: \n
  5. * (1) flash write\n
  6. * (2) flash read\n
  7. * (3) flash init \n
  8. *
  9. * @author HiView SoC Software Team
  10. * @version 1.0.0
  11. * @date 2023-05-11
  12. * @copyright Copyright(c),2023-5, Hiview Software. All rights reserved.
  13. * @par History:
  14. * <table>
  15. * <tr><th>Author <th>Date <th>Change Description
  16. * <tr><td>HiView SoC Software Team <td>2023-05-11 <td>init
  17. * </table>
  18. */
  19. #include "Common/hv_comm_DataType.h"
  20. #include "hv_comm_Define.h"
  21. #include "hv_cal_Dma.h"
  22. #include "hv_cal_Qspi.h"
  23. #include "hv_drv_FlashDB.h"
  24. #include "hv_chip_Config.h"
  25. #include "hv_vos_Comm.h"
  26. #include "hv_vos_Cache.h"
  27. #include "hv_drv_Eeprom.h"
  28. #include "hv_drv_Flash.h"
  29. #include "hv_comm_FlashConfig.h"
  30. #define SECTOR_SIZE (4*1024) //4KB
  31. #define ERASE_TYPE FLASH_ERASE_SECTOR
  32. #define ERASE_TYPE_SIZE SECTOR_SIZE
  33. #define PAGE_WRITE 256
  34. #define PAGE_READ 256
  35. #define FLASH_BUSY_FLAG 0x01
  36. #define FLASH_WAIT_INFINITE 0xFFFFFFFF
  37. #define FLASH_TIMEOUT 1000
  38. #define FLASH_WAITBUSY_TIMEOUT 1000
  39. #define FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT 20000
  40. #define FLASH_ERASECHIP_WAITBUSY_TIMEOUT 120000000
  41. struct _FlashSelf
  42. {
  43. QspiSelf* pstQspi;
  44. /*!< Flash Init parameters. */
  45. FlashInitParam InitParam;
  46. FlashAttribute flashAttr;
  47. UINT32 uiFlashID;
  48. };
  49. static FlashSelf g_stFlash;
  50. static FlashSelf* g_pFlash = NULL;
  51. static UCHAR8 g_ucReadBuf[PAGE_READ] = {0};
  52. static UCHAR8 g_ucSectorBuf[SECTOR_SIZE] = {0};
  53. static UCHAR8 g_ucWriteBuf[PAGE_WRITE] = {0};
  54. static UCHAR8 g_ucDmaUseFlag = HV_FALSE;
  55. static UCHAR8 g_ucIntUseFlag = HV_FALSE;
  56. static HV_VOS_SEMAPHORE_S *g_pstFlashSeamphone = NULL;
  57. static void Flash_OnlyRead(UINT32 uiReadAddr, UCHAR8* pucReadBuf, UINT32 uiLength);
  58. static Status Flash_Check(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength);
  59. static Status Flash_OnlyWrite(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength);
  60. static void Flash_CpltCallBack(FlashTransRW enTransType, void *pArg)
  61. {
  62. QspiSelf* pstQspi = (QspiSelf*)pArg;
  63. FlashSelf* pstFlash = (FlashSelf*)Hv_Cal_Qspi_GetFlashPoint(pstQspi);
  64. pstFlash->InitParam.FlashCpltCallback(enTransType, pstFlash);
  65. return;
  66. }
  67. static void Flash_SetCommonBaudRate(QspiInitParam* pstQspiInitParam, FlashInitParam *pstFlashInitParam)
  68. {
  69. if (pstFlashInitParam->RateMode == FLASH_STANDARD)
  70. {
  71. if (pstFlashInitParam->DataSize == FLASH_DATAWIDTH_8)
  72. {
  73. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_64;
  74. }
  75. else if (pstFlashInitParam->DataSize == FLASH_DATAWIDTH_16)
  76. {
  77. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_64;
  78. }
  79. else if (pstFlashInitParam->DataSize == FLASH_DATAWIDTH_32)
  80. {
  81. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_32;
  82. }
  83. }
  84. else if (pstFlashInitParam->RateMode == FLASH_DUAL)
  85. {
  86. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_256;
  87. }
  88. else if (pstFlashInitParam->RateMode == FLASH_QUAD)
  89. {
  90. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_256;
  91. }
  92. return;
  93. }
  94. static void Flash_SetDmaBaudRate(FlashSelf* pstFlash)
  95. {
  96. QspiSelf* pstQspi = pstFlash->pstQspi;
  97. FlashInitParam* InitParam = &pstFlash->InitParam;
  98. QspiDivideRatio qspiBaudDiv = QSPI_DIVRATIO_4;
  99. if (InitParam->RateMode == FLASH_STANDARD)
  100. {
  101. if (InitParam->DataSize == FLASH_DATAWIDTH_8)
  102. {
  103. qspiBaudDiv = QSPI_DIVRATIO_16;
  104. }
  105. else if (InitParam->DataSize == FLASH_DATAWIDTH_32)
  106. {
  107. qspiBaudDiv = QSPI_DIVRATIO_8;
  108. }
  109. }
  110. else if (InitParam->RateMode == FLASH_DUAL)
  111. {
  112. if (InitParam->DataSize == FLASH_DATAWIDTH_8)
  113. {
  114. qspiBaudDiv = QSPI_DIVRATIO_128;
  115. }
  116. else if (InitParam->DataSize == FLASH_DATAWIDTH_32)
  117. {
  118. qspiBaudDiv = QSPI_DIVRATIO_128;
  119. }
  120. }
  121. else if (InitParam->RateMode == FLASH_QUAD)
  122. {
  123. if (InitParam->DataSize == FLASH_DATAWIDTH_8)
  124. {
  125. qspiBaudDiv = QSPI_DIVRATIO_256;
  126. }
  127. else if (InitParam->DataSize == FLASH_DATAWIDTH_32)
  128. {
  129. qspiBaudDiv = QSPI_DIVRATIO_256;
  130. }
  131. }
  132. Hv_Cal_Qspi_SetBaudRate(pstQspi,qspiBaudDiv);
  133. return;
  134. }
  135. static void Flash_WriteEnable(FlashSelf* pstFlash)
  136. {
  137. QspiSelf* pstQspi = pstFlash->pstQspi;
  138. UCHAR8 ucWtEnableCmd = pstFlash->flashAttr.FlashWriteEnCmd;
  139. UINT32 uiLoop = 0;
  140. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  141. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  142. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  143. {
  144. Hv_Cal_Qspi_PollingWrite(pstQspi, &ucWtEnableCmd, 1, NULL, 0, FLASH_TIMEOUT);
  145. }
  146. else if (pstFlash->InitParam.RateMode == FLASH_DUAL || pstFlash->InitParam.RateMode == FLASH_QUAD)
  147. {
  148. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  149. {
  150. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  151. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  152. }
  153. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  154. {
  155. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,
  156. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  157. }
  158. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  159. {
  160. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_MULTI,
  161. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  162. }
  163. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &ucWtEnableCmd, 1, NULL, 0, FLASH_TIMEOUT);
  164. }
  165. for (uiLoop=0;uiLoop<2000;uiLoop++);
  166. return;
  167. }
  168. /************************************* Wait busy static API ********************************************/
  169. static Status Flash_ReadBusyFlagStandard(FlashSelf * pstFlash, UINT64 timeout)
  170. {
  171. QspiSelf* pstQspi = pstFlash->pstQspi;
  172. UINT64 tickstart = 0;
  173. UCHAR8 aucRdState[2] = {0xff, 0xff};
  174. UCHAR8 aucStateCmd[2] = {pstFlash->flashAttr.FlashReadStatusCmd, 0x00};
  175. tickstart = Hv_Vos_GetTick();
  176. while ((UCHAR8)((aucRdState[1] & FLASH_BUSY_FLAG)) != 0)
  177. {
  178. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  179. if ((timeout != FLASH_WAIT_INFINITE))
  180. {
  181. if ((Hv_Vos_GetTick() - tickstart ) > timeout)
  182. {
  183. HV_LOGI("Flash busy until timeout.\n");
  184. return HV_TIMEOUT;
  185. }
  186. }
  187. }
  188. return HV_SUCCESS;
  189. }
  190. static Status Flash_ReadBusyFlagMultiIo(FlashSelf * pstFlash, UINT64 timeout)
  191. {
  192. QspiSelf* pstQspi = pstFlash->pstQspi;
  193. UINT64 tickstart = 0;
  194. UCHAR8 ucRdState = 0xff;
  195. UCHAR8 ucStateCmd = pstFlash->flashAttr.FlashReadStatusCmd;
  196. tickstart = Hv_Vos_GetTick();
  197. while ((UCHAR8)((ucRdState & FLASH_BUSY_FLAG)) != 0)
  198. {
  199. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, &ucStateCmd, 1, &ucRdState, 1, FLASH_TIMEOUT);
  200. if ((timeout != FLASH_WAIT_INFINITE))
  201. {
  202. if ((Hv_Vos_GetTick() - tickstart ) > timeout)
  203. {
  204. HV_LOGI("Flash busy until timeout.\n");
  205. return HV_TIMEOUT;
  206. }
  207. }
  208. }
  209. return HV_SUCCESS;
  210. }
  211. static void Flash_WaitBusy(FlashSelf* pstFlash, UINT64 Timeout)
  212. {
  213. QspiSelf* pstQspi = pstFlash->pstQspi;
  214. QspiState enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  215. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  216. {
  217. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  218. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  219. Flash_ReadBusyFlagStandard(pstFlash, Timeout);
  220. }
  221. else if (pstFlash->InitParam.RateMode == FLASH_DUAL
  222. || pstFlash->InitParam.RateMode == FLASH_QUAD)
  223. {
  224. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  225. {
  226. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  227. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  228. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  229. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  230. Hv_Cal_Qspi_SetReadNumber(pstQspi, 1);
  231. Flash_ReadBusyFlagMultiIo(pstFlash, Timeout);
  232. }
  233. else if ((pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  234. ||(pstFlash->InitParam.TransType == FLASH_ADDR_4LINE))
  235. {
  236. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  237. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  238. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  239. Flash_ReadBusyFlagStandard(pstFlash,Timeout);
  240. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  241. }
  242. }
  243. return;
  244. }
  245. /************************************* Wait busy static API end*******************************************/
  246. /**************************************Read ID static function*******************************************/
  247. static UINT32 Flash_ReadID_Standard(FlashSelf* pstFlash)
  248. {
  249. QspiSelf* pstQspi = pstFlash->pstQspi;
  250. UCHAR8 aucReadID[4] = {0};
  251. UINT32 uiFlashID = 0;
  252. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  253. {
  254. UCHAR8 ucIdCmd = pstFlash->flashAttr.FlashReadIdStandardCmd;
  255. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  256. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  257. Hv_Cal_Qspi_PollingRead(pstQspi, &ucIdCmd, 1, aucReadID, 3, FLASH_TIMEOUT);
  258. uiFlashID = ( (((UINT32)aucReadID[0]) << 16) | ((UINT32)aucReadID[1] << 8) | ((UINT32)aucReadID[2]));
  259. }
  260. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  261. {
  262. UCHAR8 aucIdCmd[4]={pstFlash->flashAttr.FlashReadIdStandardCmd,0x00,0x00,0x00};
  263. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  264. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  265. Hv_Cal_Qspi_PollingRead(pstQspi, aucIdCmd, 4, aucReadID, 0, FLASH_TIMEOUT);
  266. uiFlashID = ( (((UINT32)aucReadID[1]) << 16) | ((UINT32)aucReadID[2] << 8) | ((UINT32)aucReadID[3]));
  267. }
  268. return uiFlashID;
  269. }
  270. static UINT32 Flash_ReadID_MutiIO(FlashSelf* pstFlash)
  271. {
  272. QspiSelf* pstQspi = pstFlash->pstQspi;
  273. UCHAR8 ucIdCmd = pstFlash->flashAttr.FlashReadIdMultiIoCmd;
  274. UCHAR8 aucReadID[4] = {0};
  275. UINT32 uiFlashID = 0;
  276. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  277. {
  278. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  279. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  280. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  281. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  282. Hv_Cal_Qspi_SetReadNumber(pstQspi, 3);
  283. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, &ucIdCmd, 1, aucReadID, 3, FLASH_TIMEOUT);
  284. uiFlashID = (((UINT32)aucReadID[0] << 16) | ((UINT32)aucReadID[1] << 8) | ((UINT32)aucReadID[2]) );
  285. }
  286. else if ((pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  287. ||(pstFlash->InitParam.TransType == FLASH_ADDR_4LINE))
  288. {
  289. QspiState enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  290. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  291. uiFlashID = Flash_ReadID_Standard(pstFlash);
  292. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  293. return uiFlashID;
  294. }
  295. return uiFlashID;
  296. }
  297. /**************************************Read ID static function end****************************************/
  298. /**************************************Erase static function**********************************************/
  299. static Status Flash_EraseStandard(FlashSelf* pstFlash, FlashEraseType enEraseType, UINT32 uiEraseAddr)
  300. {
  301. QspiSelf* pstQspi = pstFlash->pstQspi;
  302. UCHAR8 eraseSector[5] = {0};
  303. UCHAR8 eraseChip = 0;
  304. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  305. Flash_WriteEnable(pstFlash);
  306. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  307. {
  308. if (enEraseType == FLASH_ERASE_SECTOR)
  309. {
  310. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd;
  311. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  312. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  313. eraseSector[3] = (UCHAR8) uiEraseAddr;
  314. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  315. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  316. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  317. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  318. }
  319. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  320. {
  321. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd;
  322. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  323. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  324. eraseSector[3] = (UCHAR8) uiEraseAddr;
  325. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  326. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  327. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  328. Flash_WaitBusy(pstFlash,FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT);
  329. }
  330. else if (enEraseType == FLASH_ERASE_CHIP)
  331. {
  332. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  333. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  334. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  335. Hv_Cal_Qspi_PollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  336. Flash_WaitBusy(pstFlash,FLASH_ERASECHIP_WAITBUSY_TIMEOUT);
  337. }
  338. }
  339. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  340. {
  341. if (enEraseType == FLASH_ERASE_SECTOR)
  342. {
  343. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd_4ByteAddr;
  344. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  345. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  346. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  347. eraseSector[4] = (UCHAR8) uiEraseAddr;
  348. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  349. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  350. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  351. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  352. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  353. }
  354. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  355. {
  356. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd_4ByteAddr;
  357. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  358. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  359. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  360. eraseSector[4] = (UCHAR8) uiEraseAddr;
  361. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  362. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  363. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  364. Flash_WaitBusy(pstFlash,FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT);
  365. }
  366. else if (enEraseType == FLASH_ERASE_CHIP)
  367. {
  368. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  369. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  370. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  371. Hv_Cal_Qspi_PollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  372. Flash_WaitBusy(pstFlash,FLASH_ERASECHIP_WAITBUSY_TIMEOUT);
  373. }
  374. }
  375. Hv_Vos_MSleep(pstFlash->flashAttr.FlashEraseCompltWait);
  376. return HV_SUCCESS;
  377. }
  378. static Status Flash_EraseMultiIo(FlashSelf* pstFlash, FlashEraseType enEraseType, UINT32 uiEraseAddr)
  379. {
  380. QspiSelf* pstQspi = pstFlash->pstQspi;
  381. UCHAR8 eraseSector[5] = {0};
  382. UCHAR8 eraseChip = 0;
  383. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  384. {
  385. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  386. Flash_WriteEnable(pstFlash);
  387. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  388. {
  389. if (enEraseType == FLASH_ERASE_SECTOR)
  390. {
  391. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd;
  392. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  393. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  394. eraseSector[3] = (UCHAR8) uiEraseAddr;
  395. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  396. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  397. }
  398. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  399. {
  400. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd;
  401. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  402. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  403. eraseSector[3] = (UCHAR8) uiEraseAddr;
  404. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  405. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  406. }
  407. else if (enEraseType == FLASH_ERASE_CHIP)
  408. {
  409. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  410. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  411. }
  412. }
  413. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  414. {
  415. if (enEraseType == FLASH_ERASE_SECTOR)
  416. {
  417. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd_4ByteAddr;
  418. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  419. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  420. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  421. eraseSector[4] = (UCHAR8) uiEraseAddr;
  422. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  423. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  424. }
  425. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  426. {
  427. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd_4ByteAddr;
  428. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  429. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  430. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  431. eraseSector[4] = (UCHAR8) uiEraseAddr;
  432. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  433. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  434. }
  435. else if (enEraseType == FLASH_ERASE_CHIP)
  436. {
  437. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  438. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  439. }
  440. }
  441. if (enEraseType == FLASH_ERASE_SECTOR)
  442. {
  443. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  444. }
  445. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  446. {
  447. Flash_WaitBusy(pstFlash,FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT);
  448. }
  449. else if (enEraseType == FLASH_ERASE_CHIP)
  450. {
  451. Flash_WaitBusy(pstFlash,FLASH_ERASECHIP_WAITBUSY_TIMEOUT);
  452. }
  453. Hv_Vos_MSleep(pstFlash->flashAttr.FlashEraseCompltWait);
  454. }
  455. else if ((pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  456. ||(pstFlash->InitParam.TransType == FLASH_ADDR_4LINE))
  457. {
  458. QspiRateMode enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  459. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  460. Flash_EraseStandard(pstFlash,enEraseType,uiEraseAddr);
  461. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  462. }
  463. return HV_SUCCESS;
  464. }
  465. /**************************************Erase static function end********************************************/
  466. /************************************************ Standard API *********************************************/
  467. static Status Flash_SendStandard(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  468. {
  469. QspiSelf* pstQspi = pstFlash->pstQspi;
  470. UCHAR8 aucCmdAddr[8] = {0};
  471. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  472. {
  473. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  474. {
  475. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  476. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  477. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  478. aucCmdAddr[3] = uiWtAddr & 0xff;
  479. }
  480. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  481. {
  482. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd_4ByteAddr;
  483. aucCmdAddr[1] = (uiWtAddr >> 24) & 0xff;
  484. aucCmdAddr[2] = (uiWtAddr >> 16) & 0xff;
  485. aucCmdAddr[3] = (uiWtAddr >> 8) & 0xff;
  486. aucCmdAddr[4] = uiWtAddr & 0xff;
  487. }
  488. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  489. Flash_WriteEnable(pstFlash);
  490. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  491. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  492. {
  493. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize, FLASH_TIMEOUT);
  494. }
  495. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  496. {
  497. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 5, pucTxData, uiTxSize, FLASH_TIMEOUT);
  498. }
  499. }
  500. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_16)
  501. {
  502. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  503. {
  504. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  505. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  506. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  507. aucCmdAddr[3] = uiWtAddr & 0xff;
  508. }
  509. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  510. {
  511. HV_ASSERT(0);
  512. }
  513. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  514. Flash_WriteEnable(pstFlash);
  515. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  516. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize, FLASH_TIMEOUT);
  517. }
  518. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  519. {
  520. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  521. {
  522. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  523. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  524. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  525. aucCmdAddr[3] = uiWtAddr & 0xff;
  526. }
  527. else
  528. {
  529. HV_ASSERT(0);
  530. }
  531. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  532. Flash_WriteEnable(pstFlash);
  533. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  534. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize, FLASH_TIMEOUT);
  535. }
  536. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  537. return HV_SUCCESS;
  538. }
  539. static Status Flash_RecvStandard(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  540. {
  541. QspiSelf* pstQspi = pstFlash->pstQspi;
  542. UCHAR8 aucCmdAddr[8] = {0};
  543. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  544. {
  545. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  546. {
  547. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  548. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  549. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  550. aucCmdAddr[3] = uiRdAddr & 0xff;
  551. }
  552. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  553. {
  554. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd_4ByteAddr;
  555. aucCmdAddr[1] = (uiRdAddr >> 24) & 0xff;
  556. aucCmdAddr[2] = (uiRdAddr >> 16) & 0xff;
  557. aucCmdAddr[3] = (uiRdAddr >> 8) & 0xff;
  558. aucCmdAddr[4] = uiRdAddr & 0xff;
  559. }
  560. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  561. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  562. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  563. {
  564. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize, FLASH_TIMEOUT);
  565. }
  566. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  567. {
  568. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 5, pucRxData, uiRxSize, FLASH_TIMEOUT);
  569. }
  570. }
  571. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_16)
  572. {
  573. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  574. {
  575. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  576. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  577. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  578. aucCmdAddr[3] = uiRdAddr & 0xff;
  579. }
  580. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  581. {
  582. HV_ASSERT(0);
  583. }
  584. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  585. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  586. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize, FLASH_TIMEOUT);
  587. }
  588. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  589. {
  590. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  591. {
  592. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  593. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  594. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  595. aucCmdAddr[3] = uiRdAddr & 0xff;
  596. }
  597. else
  598. {
  599. HV_ASSERT(0);
  600. }
  601. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  602. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  603. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize,FLASH_TIMEOUT);
  604. }
  605. return HV_SUCCESS;
  606. }
  607. static Status Flash_SendStandardInt(FlashSelf* pstFlash,UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  608. {
  609. QspiSelf* pstQspi = pstFlash->pstQspi;
  610. UCHAR8 aucCmdAddr[8] = {0};
  611. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  612. {
  613. HV_LOGI("Standard Int send just support 32bits DataWidth.\n");
  614. HV_ASSERT(0);
  615. }
  616. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  617. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  618. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  619. aucCmdAddr[3] = uiWtAddr & 0xff;
  620. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  621. Flash_WriteEnable(pstFlash);
  622. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  623. Hv_Cal_Qspi_IntWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize);
  624. return HV_SUCCESS;
  625. }
  626. static Status Flash_RecvStandardInt(FlashSelf* pstFlash,UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  627. {
  628. QspiSelf* pstQspi = pstFlash->pstQspi;
  629. UCHAR8 aucCmdAddr[8] = {0};
  630. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  631. {
  632. HV_LOGI("Standard Int receive just support 32bits DataWidth.\n");
  633. HV_ASSERT(0);
  634. }
  635. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  636. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  637. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  638. aucCmdAddr[3] = uiRdAddr & 0xff;
  639. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  640. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  641. Hv_Cal_Qspi_IntRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize);
  642. return HV_SUCCESS;
  643. }
  644. static Status Flash_SendStandardDma(FlashSelf* pstFlash,UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  645. {
  646. QspiSelf* pstQspi = pstFlash->pstQspi;
  647. FlashTxMem* TxDataDma = NULL;
  648. TxDataDma = (FlashTxMem*) (pucTxData - 20);
  649. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  650. {
  651. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  652. {
  653. TxDataDma->cmdAddr[16] = pstFlash->flashAttr.FlashProgStandardCmd;
  654. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  655. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  656. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  657. }
  658. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  659. {
  660. TxDataDma->cmdAddr[15] = pstFlash->flashAttr.FlashProgStandardCmd;
  661. TxDataDma->cmdAddr[16] = (uiWtAddr >> 24) & 0xff;
  662. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  663. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  664. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  665. }
  666. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  667. Flash_WriteEnable(pstFlash);
  668. Flash_SetDmaBaudRate(pstFlash);
  669. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  670. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  671. {
  672. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  673. }
  674. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  675. {
  676. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[15], uiTxSize + 5);
  677. }
  678. }
  679. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  680. {
  681. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  682. {
  683. TxDataDma->cmdAddr[16] = uiWtAddr & 0xff;
  684. TxDataDma->cmdAddr[17] = (uiWtAddr >> 8) & 0xff;
  685. TxDataDma->cmdAddr[18] = (uiWtAddr >> 16) & 0xff;
  686. TxDataDma->cmdAddr[19] = pstFlash->flashAttr.FlashProgStandardCmd;
  687. }
  688. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  689. {
  690. HV_ASSERT(0);
  691. }
  692. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  693. Flash_WriteEnable(pstFlash);
  694. Flash_SetDmaBaudRate(pstFlash);
  695. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  696. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  697. }
  698. return HV_SUCCESS;
  699. }
  700. static Status Flash_RecvStandardDma(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  701. {
  702. QspiSelf* pstQspi = pstFlash->pstQspi;
  703. static UCHAR8 g_aucCmdAddrBuf[1029];
  704. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  705. {
  706. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  707. {
  708. g_aucCmdAddrBuf[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  709. g_aucCmdAddrBuf[1] = (uiRdAddr >> 16) & 0xff;
  710. g_aucCmdAddrBuf[2] = (uiRdAddr >> 8) & 0xff;
  711. g_aucCmdAddrBuf[3] = uiRdAddr & 0xff;
  712. }
  713. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  714. {
  715. g_aucCmdAddrBuf[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  716. g_aucCmdAddrBuf[1] = (uiRdAddr >> 24) & 0xff;
  717. g_aucCmdAddrBuf[2] = (uiRdAddr >> 16) & 0xff;
  718. g_aucCmdAddrBuf[3] = (uiRdAddr >> 8) & 0xff;
  719. g_aucCmdAddrBuf[4] = uiRdAddr & 0xff;
  720. }
  721. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  722. Flash_SetDmaBaudRate(pstFlash);
  723. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  724. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  725. {
  726. Hv_Cal_Qspi_DmaRead(pstQspi, g_aucCmdAddrBuf, 4, pucRxData, uiRxSize);
  727. }
  728. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  729. {
  730. Hv_Cal_Qspi_DmaRead(pstQspi, g_aucCmdAddrBuf, 5, pucRxData, uiRxSize);
  731. }
  732. }
  733. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  734. {
  735. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  736. {
  737. g_aucCmdAddrBuf[0] = uiRdAddr & 0xff;
  738. g_aucCmdAddrBuf[1] = (uiRdAddr >> 8) & 0xff;
  739. g_aucCmdAddrBuf[2] = (uiRdAddr >> 16) & 0xff;
  740. g_aucCmdAddrBuf[3] = pstFlash->flashAttr.FlashReadStandardCmd;
  741. }
  742. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  743. {
  744. HV_ASSERT(0);
  745. }
  746. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  747. Flash_SetDmaBaudRate(pstFlash);
  748. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  749. Hv_Cal_Qspi_DmaRead(pstQspi, g_aucCmdAddrBuf, 4, pucRxData, uiRxSize);
  750. }
  751. return HV_SUCCESS;
  752. }
  753. /************************************************ Standard API end******************************************/
  754. /*************************************************Dual API**************************************************/
  755. static Status Flash_SendDual(FlashSelf* pstFlash, UINT32 uiWtAddr,
  756. UCHAR8* pucTxData, UINT32 uiTxSize)
  757. {
  758. QspiSelf* pstQspi = pstFlash->pstQspi;
  759. UCHAR8 aucCmdAddr[8] = {0};
  760. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  761. {
  762. HV_LOGI("Dual Polling just support 32bits DataWidth.\n");
  763. HV_ASSERT(0);
  764. }
  765. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  766. {
  767. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  768. aucCmdAddr[4] = 0;
  769. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  770. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  771. aucCmdAddr[7] = uiWtAddr & 0xff;
  772. }
  773. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  774. {
  775. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  776. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  777. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  778. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  779. aucCmdAddr[7] = uiWtAddr & 0xff;
  780. }
  781. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  782. Flash_WriteEnable(pstFlash);
  783. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  784. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  785. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  786. {
  787. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  788. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  789. }
  790. else
  791. {
  792. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  793. pstFlash->InitParam.AddrWidth, 0);
  794. }
  795. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize, FLASH_TIMEOUT);
  796. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  797. return HV_SUCCESS;
  798. }
  799. static Status Flash_RecvDual(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  800. {
  801. QspiSelf* pstQspi = pstFlash->pstQspi;
  802. UCHAR8 aucCmdAddr[8] = {0};
  803. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  804. {
  805. HV_LOGI("Dual Polling just support 32bits DataWidth.\n");
  806. HV_ASSERT(0);
  807. }
  808. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  809. {
  810. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  811. aucCmdAddr[4] = 0;
  812. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  813. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  814. aucCmdAddr[7] = uiRdAddr & 0xff;
  815. }
  816. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  817. {
  818. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  819. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  820. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  821. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  822. aucCmdAddr[7] = uiRdAddr & 0xff;
  823. }
  824. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  825. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  826. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  827. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  828. {
  829. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  830. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastDual);
  831. }
  832. else
  833. {
  834. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  835. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleDual);
  836. }
  837. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  838. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize, FLASH_TIMEOUT);
  839. return HV_SUCCESS;
  840. }
  841. static Status Flash_SendDualInt(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  842. {
  843. QspiSelf* pstQspi = pstFlash->pstQspi;
  844. UCHAR8 aucCmdAddr[8] = {0};
  845. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  846. {
  847. HV_LOGI("Dual Int send just support 32bits DataWidth.\n");
  848. HV_ASSERT(0);
  849. }
  850. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  851. {
  852. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  853. aucCmdAddr[4] = 0;
  854. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  855. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  856. aucCmdAddr[7] = uiWtAddr & 0xff;
  857. }
  858. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  859. {
  860. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  861. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  862. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  863. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  864. aucCmdAddr[7] = uiWtAddr & 0xff;
  865. }
  866. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  867. Flash_WriteEnable(pstFlash);
  868. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  869. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  870. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  871. {
  872. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  873. pstFlash->InitParam.AddrWidth, 0);
  874. }
  875. else
  876. {
  877. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  878. pstFlash->InitParam.AddrWidth, 0);
  879. }
  880. Hv_Cal_Qspi_IntWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize);
  881. return HV_SUCCESS;
  882. }
  883. static Status Flash_RecvDualInt(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  884. {
  885. QspiSelf* pstQspi = pstFlash->pstQspi;
  886. UCHAR8 aucCmdAddr[8] = {0};
  887. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  888. {
  889. HV_LOGI("Dual Int receive just support 32bits DataWidth.\n");
  890. HV_ASSERT(0);
  891. }
  892. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  893. {
  894. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  895. aucCmdAddr[4] = 0;
  896. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  897. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  898. aucCmdAddr[7] = uiRdAddr & 0xff;
  899. }
  900. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  901. {
  902. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  903. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  904. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  905. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  906. aucCmdAddr[7] = uiRdAddr & 0xff;
  907. }
  908. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  909. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  910. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  911. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  912. {
  913. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND, pstFlash->flashAttr.FlashInstruWidth,
  914. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastDual);
  915. }
  916. else
  917. {
  918. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  919. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleDual);
  920. }
  921. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  922. Hv_Cal_Qspi_IntRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize);
  923. return HV_SUCCESS;
  924. }
  925. static Status Flash_SendDualDma(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  926. {
  927. QspiSelf* pstQspi = pstFlash->pstQspi;
  928. FlashTxMem* TxDataDma = NULL;
  929. UINT32 uiWtCmdTemp = 0;
  930. UINT64 wtAddrTemp = 0;
  931. UINT32 uiLoop = 0;
  932. TxDataDma = (FlashTxMem*) (pucTxData - 20);
  933. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  934. {
  935. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  936. {
  937. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  938. {
  939. TxDataDma->cmdAddr[16] = pstFlash->flashAttr.FlashProgDualCmd;
  940. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  941. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  942. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  943. }
  944. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  945. {
  946. for (uiLoop = 0;uiLoop < 24;uiLoop++ )
  947. {
  948. if (uiLoop < 8)
  949. {
  950. uiWtCmdTemp |= ((UINT32)(pstFlash->flashAttr.FlashProgDualCmd & (1 << uiLoop))) << uiLoop;
  951. uiWtCmdTemp |= ((UINT32)((1 << uiLoop))) << (uiLoop+1);
  952. }
  953. wtAddrTemp |= ((UINT64)(uiWtAddr & (1 << uiLoop))) << uiLoop;
  954. wtAddrTemp |= ((UINT64)((1 << uiLoop))) << (uiLoop+1);
  955. }
  956. TxDataDma->cmdAddr[12] = (uiWtCmdTemp >> 8) & 0xff;
  957. TxDataDma->cmdAddr[13] = uiWtCmdTemp & 0xff;
  958. TxDataDma->cmdAddr[14] = (wtAddrTemp >> 40) & 0xff ;
  959. TxDataDma->cmdAddr[15] = (wtAddrTemp >> 32) & 0xff;
  960. TxDataDma->cmdAddr[16] = (wtAddrTemp >> 24) & 0xff;
  961. TxDataDma->cmdAddr[17] = (wtAddrTemp >> 16) & 0xff;
  962. TxDataDma->cmdAddr[18] = (wtAddrTemp >> 8) & 0xff;
  963. TxDataDma->cmdAddr[19] = wtAddrTemp & 0xff;
  964. }
  965. }
  966. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  967. {
  968. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  969. {
  970. TxDataDma->cmdAddr[15] = pstFlash->flashAttr.FlashProgDualCmd;
  971. TxDataDma->cmdAddr[16] = (uiWtAddr >> 24) & 0xff;
  972. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  973. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  974. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  975. }
  976. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  977. {
  978. HV_ASSERT(1);
  979. }
  980. }
  981. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  982. Flash_WriteEnable(pstFlash);
  983. Flash_SetDmaBaudRate(pstFlash);
  984. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  985. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  986. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  987. {
  988. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  989. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  990. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  991. {
  992. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[12], uiTxSize + 8);
  993. }
  994. }
  995. else
  996. {
  997. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  998. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  999. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1000. {
  1001. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  1002. }
  1003. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1004. {
  1005. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[15], uiTxSize + 5);
  1006. }
  1007. }
  1008. }
  1009. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1010. {
  1011. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgDualCmd;
  1012. TxDataDma->cmdAddr[13] = 0x00;
  1013. TxDataDma->cmdAddr[14] = 0x00;
  1014. TxDataDma->cmdAddr[15] = 0x00;
  1015. TxDataDma->cmdAddr[16] = uiWtAddr & 0xff;
  1016. TxDataDma->cmdAddr[17] = (uiWtAddr >> 8) & 0xff;
  1017. TxDataDma->cmdAddr[18] = (uiWtAddr >> 16) & 0xff;
  1018. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1019. {
  1020. TxDataDma->cmdAddr[19] = 0;
  1021. }
  1022. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1023. {
  1024. TxDataDma->cmdAddr[19] = (uiWtAddr >> 24) & 0xff;
  1025. }
  1026. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1027. Flash_WriteEnable(pstFlash);
  1028. Flash_SetDmaBaudRate(pstFlash);
  1029. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1030. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1031. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1032. {
  1033. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1034. pstFlash->flashAttr.FlashInstruWidth,
  1035. pstFlash->InitParam.AddrWidth, 0);
  1036. }
  1037. else
  1038. {
  1039. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1040. pstFlash->flashAttr.FlashInstruWidth,
  1041. pstFlash->InitParam.AddrWidth, 0);
  1042. }
  1043. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[12], uiTxSize + 8);
  1044. }
  1045. return HV_SUCCESS;
  1046. }
  1047. static Status Flash_RecvDualDma(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1048. {
  1049. QspiSelf* pstQspi = pstFlash->pstQspi;
  1050. UCHAR8 aucCmdAddr[8] = {0};
  1051. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadDualCmd;
  1052. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1053. {
  1054. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  1055. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  1056. aucCmdAddr[3] = uiRdAddr & 0xff;
  1057. }
  1058. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1059. {
  1060. aucCmdAddr[1] = (uiRdAddr >> 24) & 0xff;
  1061. aucCmdAddr[2] = (uiRdAddr >> 16) & 0xff;
  1062. aucCmdAddr[3] = (uiRdAddr >> 8) & 0xff;
  1063. aucCmdAddr[4] = uiRdAddr & 0xff;
  1064. }
  1065. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1066. /* Here can set different BaudDiv for different flash type, such as GD25F128 can
  1067. support up to 166MHz dual fast read mode */
  1068. if (pstFlash->InitParam.FlashModel == FLASH_GD25)
  1069. {
  1070. Hv_Cal_Qspi_SetBaudRate(pstFlash->pstQspi, QSPI_DIVRATIO_2);
  1071. }
  1072. else
  1073. {
  1074. Flash_SetDmaBaudRate(pstFlash);
  1075. }
  1076. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  1077. {
  1078. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1079. }else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1080. {
  1081. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1082. }
  1083. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1084. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1085. {
  1086. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  1087. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastDual);
  1088. }
  1089. else
  1090. {
  1091. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1092. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleDual);
  1093. }
  1094. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1095. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1096. {
  1097. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize);
  1098. }
  1099. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1100. {
  1101. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 5, pucRxData, uiRxSize);
  1102. }
  1103. return HV_SUCCESS;
  1104. }
  1105. /*************************************************Dual API end***************************************/
  1106. /**********************************************Quad API***********************************************/
  1107. static Status Flash_SendQuad(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  1108. {
  1109. QspiSelf* pstQspi = pstFlash->pstQspi;
  1110. UCHAR8 aucCmdAddr[8] = {0};
  1111. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1112. {
  1113. HV_LOGI("Quad Polling just support 32bits DataWidth.\n");
  1114. HV_ASSERT(0);
  1115. }
  1116. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1117. {
  1118. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1119. {
  1120. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd;
  1121. }
  1122. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1123. {
  1124. aucCmdAddr[3] = pstFlash->flashAttr.FlashProg4xIoCmd;
  1125. }
  1126. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1127. {
  1128. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd;
  1129. }
  1130. aucCmdAddr[4] = 0x00;
  1131. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1132. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1133. aucCmdAddr[7] = uiWtAddr & 0xff;
  1134. }
  1135. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1136. {
  1137. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1138. {
  1139. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd_4ByteAddr;
  1140. }
  1141. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1142. {
  1143. aucCmdAddr[3] = pstFlash->flashAttr.FlashProg4xIoCmd_4ByteAddr;
  1144. }
  1145. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1146. {
  1147. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd_4ByteAddr;
  1148. }
  1149. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  1150. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1151. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1152. aucCmdAddr[7] = uiWtAddr & 0xff;
  1153. }
  1154. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1155. Flash_WriteEnable(pstFlash);
  1156. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1157. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1158. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1159. {
  1160. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1161. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1162. }
  1163. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1164. {
  1165. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1166. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1167. }
  1168. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1169. {
  1170. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_MULTI,
  1171. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1172. }
  1173. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize, FLASH_TIMEOUT);
  1174. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1175. return HV_SUCCESS;
  1176. }
  1177. static Status Flash_RecvQuad(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1178. {
  1179. QspiSelf* pstQspi = pstFlash->pstQspi;
  1180. UCHAR8 aucCmdAddr[8] = {0};
  1181. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1182. {
  1183. HV_LOGI("Quad Polling just support 32bits DataWidth.\n");
  1184. HV_ASSERT(0);
  1185. }
  1186. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1187. {
  1188. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1189. {
  1190. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd;
  1191. }
  1192. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1193. {
  1194. aucCmdAddr[3] = pstFlash->flashAttr.FlashRead4xIoCmd;
  1195. }
  1196. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1197. {
  1198. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd;
  1199. }
  1200. aucCmdAddr[4] = 0x00;
  1201. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1202. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1203. aucCmdAddr[7] = uiRdAddr & 0xff;
  1204. }
  1205. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1206. {
  1207. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1208. {
  1209. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd_4ByteAddr;
  1210. }
  1211. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1212. {
  1213. aucCmdAddr[3] = pstFlash->flashAttr.FlashRead4xIoCmd_4ByteAddr;
  1214. }
  1215. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1216. {
  1217. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd_4ByteAddr;
  1218. }
  1219. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  1220. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1221. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1222. aucCmdAddr[7] = uiRdAddr & 0xff;
  1223. }
  1224. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1225. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1226. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1227. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1228. {
  1229. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  1230. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastQuad);
  1231. }
  1232. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1233. {
  1234. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1235. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleQpi);
  1236. }
  1237. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1238. {
  1239. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1240. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycle4xIo);
  1241. }
  1242. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1243. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize, FLASH_TIMEOUT);
  1244. return HV_SUCCESS;
  1245. }
  1246. static Status Flash_SendQuadInt(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  1247. {
  1248. QspiSelf* pstQspi = pstFlash->pstQspi;
  1249. UCHAR8 aucCmdAddr[8] = {0};
  1250. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1251. {
  1252. HV_LOGI("Quad Int send just support 32bits DataWidth.\n");
  1253. HV_ASSERT(0);
  1254. }
  1255. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1256. {
  1257. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1258. {
  1259. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd;
  1260. }
  1261. else
  1262. {
  1263. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd;
  1264. }
  1265. aucCmdAddr[4] = 0x00;
  1266. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1267. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1268. aucCmdAddr[7] = uiWtAddr & 0xff;
  1269. }
  1270. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1271. {
  1272. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1273. {
  1274. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd;
  1275. }
  1276. else
  1277. {
  1278. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd;
  1279. }
  1280. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  1281. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1282. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1283. aucCmdAddr[7] = uiWtAddr & 0xff;
  1284. }
  1285. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1286. Flash_WriteEnable(pstFlash);
  1287. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1288. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1289. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1290. {
  1291. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1292. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1293. }
  1294. else
  1295. {
  1296. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  1297. pstFlash->InitParam.AddrWidth, 0);
  1298. }
  1299. Hv_Cal_Qspi_IntWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize);
  1300. return HV_SUCCESS;
  1301. }
  1302. static Status Flash_RecvQuadInt(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1303. {
  1304. QspiSelf* pstQspi = pstFlash->pstQspi;
  1305. UCHAR8 aucCmdAddr[8] = {0};
  1306. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1307. {
  1308. HV_LOGI("Quad Int receive just support 32bits DataWidth.\n");
  1309. HV_ASSERT(0);
  1310. }
  1311. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1312. {
  1313. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1314. {
  1315. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd;
  1316. }
  1317. else
  1318. {
  1319. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd;
  1320. }
  1321. aucCmdAddr[4] = 0x00;
  1322. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1323. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1324. aucCmdAddr[7] = uiRdAddr & 0xff;
  1325. }
  1326. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1327. {
  1328. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1329. {
  1330. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd;
  1331. }
  1332. else
  1333. {
  1334. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd;
  1335. }
  1336. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  1337. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1338. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1339. aucCmdAddr[7] = uiRdAddr & 0xff;
  1340. }
  1341. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1342. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1343. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1344. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1345. {
  1346. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND, pstFlash->flashAttr.FlashInstruWidth,
  1347. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastQuad);
  1348. }
  1349. else
  1350. {
  1351. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  1352. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleQpi);
  1353. }
  1354. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1355. Hv_Cal_Qspi_IntRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize);
  1356. return HV_SUCCESS;
  1357. }
  1358. static Status Flash_SendQuadDma(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  1359. {
  1360. QspiSelf* pstQspi = pstFlash->pstQspi;
  1361. FlashTxMem* TxDataDma = NULL;
  1362. UINT32 uiWtCmdTemp = 0;
  1363. UINT64 wtAddrTempHigh = 0;
  1364. UINT64 wtAddrTempLow = 0;
  1365. UINT32 uiLoop = 0;
  1366. TxDataDma = (FlashTxMem*) (pucTxData - 20);
  1367. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  1368. {
  1369. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1370. {
  1371. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1372. {
  1373. TxDataDma->cmdAddr[16] = pstFlash->flashAttr.FlashProgQpiCmd;
  1374. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  1375. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  1376. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  1377. }
  1378. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1379. {
  1380. for (uiLoop = 0;uiLoop < 16;uiLoop++)
  1381. {
  1382. wtAddrTempLow |= ((UINT64)(uiWtAddr & (1 << uiLoop))) << 3 * uiLoop;
  1383. wtAddrTempLow |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1384. if (uiLoop < 8)
  1385. {
  1386. uiWtCmdTemp |= ((UINT32)(pstFlash->flashAttr.FlashProgQuadCmd & (1 << uiLoop))) << 3 * uiLoop;
  1387. uiWtCmdTemp |= ((UINT32)((0xe << uiLoop))) << 3 * uiLoop;
  1388. wtAddrTempHigh |= ((UINT64)(((uiWtAddr >> 16) & (1 << uiLoop)))) << 3 * uiLoop;
  1389. wtAddrTempHigh |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1390. }
  1391. }
  1392. TxDataDma->cmdAddr[4] = (uiWtCmdTemp >> 24) & 0xff;
  1393. TxDataDma->cmdAddr[5] = (uiWtCmdTemp >> 16) & 0xff;
  1394. TxDataDma->cmdAddr[6] = (uiWtCmdTemp >> 8) & 0xff;
  1395. TxDataDma->cmdAddr[7] = uiWtCmdTemp & 0xff;
  1396. TxDataDma->cmdAddr[8] = (wtAddrTempHigh >> 24) & 0xff;
  1397. TxDataDma->cmdAddr[9] = (wtAddrTempHigh >> 16) & 0xff;
  1398. TxDataDma->cmdAddr[10] = (wtAddrTempHigh >> 8) & 0xff;
  1399. TxDataDma->cmdAddr[11] = wtAddrTempHigh & 0xff;
  1400. TxDataDma->cmdAddr[12] = (wtAddrTempLow >> 56) & 0xff;
  1401. TxDataDma->cmdAddr[13] = (wtAddrTempLow >> 48) & 0xff;
  1402. TxDataDma->cmdAddr[14] = (wtAddrTempLow >> 40) & 0xff;
  1403. TxDataDma->cmdAddr[15] = (wtAddrTempLow >> 32) & 0xff;
  1404. TxDataDma->cmdAddr[16] = (wtAddrTempLow >> 24) & 0xff;
  1405. TxDataDma->cmdAddr[17] = (wtAddrTempLow >> 16) & 0xff;
  1406. TxDataDma->cmdAddr[18] = (wtAddrTempLow >> 8) & 0xff;
  1407. TxDataDma->cmdAddr[19] = wtAddrTempLow & 0xff;
  1408. }
  1409. }
  1410. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1411. {
  1412. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1413. {
  1414. TxDataDma->cmdAddr[15] = pstFlash->flashAttr.FlashProgQpiCmd;
  1415. TxDataDma->cmdAddr[16] = (uiWtAddr >> 24) & 0xff;
  1416. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  1417. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  1418. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  1419. }
  1420. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1421. {
  1422. UINT32 uiWtCmdTemp = 0;
  1423. UINT64 wtAddrTempHigh = 0;
  1424. UINT64 wtAddrTempLow = 0;
  1425. UINT32 uiLoop = 0;
  1426. for (uiLoop = 0;uiLoop < 16;uiLoop++)
  1427. {
  1428. wtAddrTempLow |= ((UINT64)(uiWtAddr & (1 << uiLoop))) << 3 * uiLoop;
  1429. wtAddrTempLow |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1430. if (uiLoop < 8)
  1431. {
  1432. uiWtCmdTemp |= ((UINT32)(pstFlash->flashAttr.FlashProgQuadCmd & (1 << uiLoop))) << 3 * uiLoop;
  1433. uiWtCmdTemp |= ((UINT32)((0xe << uiLoop))) << 3 * uiLoop;
  1434. wtAddrTempHigh |= ((UINT64)(((uiWtAddr >> 16) & (1 << uiLoop)))) << 3 * uiLoop;
  1435. wtAddrTempHigh |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1436. }
  1437. }
  1438. TxDataDma->cmdAddr[0] = (uiWtCmdTemp >> 24) & 0xff;
  1439. TxDataDma->cmdAddr[1] = (uiWtCmdTemp >> 16) & 0xff;
  1440. TxDataDma->cmdAddr[2] = (uiWtCmdTemp >> 8) & 0xff;
  1441. TxDataDma->cmdAddr[3] = uiWtCmdTemp & 0xff;
  1442. TxDataDma->cmdAddr[4] = (wtAddrTempLow >> 56) & 0xff;
  1443. TxDataDma->cmdAddr[5] = (wtAddrTempLow >> 48) & 0xff;
  1444. TxDataDma->cmdAddr[6] = (wtAddrTempLow >> 40) & 0xff;
  1445. TxDataDma->cmdAddr[7] = (wtAddrTempLow >> 32) & 0xff;
  1446. TxDataDma->cmdAddr[8] = (wtAddrTempHigh >> 24) & 0xff;
  1447. TxDataDma->cmdAddr[9] = (wtAddrTempHigh >> 16) & 0xff;
  1448. TxDataDma->cmdAddr[10] = (wtAddrTempHigh >> 8) & 0xff;
  1449. TxDataDma->cmdAddr[11] = wtAddrTempHigh & 0xff;
  1450. TxDataDma->cmdAddr[12] = (wtAddrTempLow >> 56) & 0xff;
  1451. TxDataDma->cmdAddr[13] = (wtAddrTempLow >> 48) & 0xff;
  1452. TxDataDma->cmdAddr[14] = (wtAddrTempLow >> 40) & 0xff;
  1453. TxDataDma->cmdAddr[15] = (wtAddrTempLow >> 32) & 0xff;
  1454. TxDataDma->cmdAddr[16] = (wtAddrTempLow >> 24) & 0xff;
  1455. TxDataDma->cmdAddr[17] = (wtAddrTempLow >> 16) & 0xff;
  1456. TxDataDma->cmdAddr[18] = (wtAddrTempLow >> 8) & 0xff;
  1457. TxDataDma->cmdAddr[19] = wtAddrTempLow & 0xff;
  1458. }
  1459. }
  1460. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1461. Flash_WriteEnable(pstFlash);
  1462. Flash_SetDmaBaudRate(pstFlash);
  1463. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1464. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1465. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1466. {
  1467. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1468. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  1469. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1470. {
  1471. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[4], uiTxSize + 16);
  1472. }
  1473. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1474. {
  1475. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[0], uiTxSize + 20);
  1476. }
  1477. }
  1478. else
  1479. {
  1480. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1481. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  1482. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24){
  1483. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  1484. }
  1485. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1486. {
  1487. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[15], uiTxSize + 5);
  1488. }
  1489. }
  1490. }
  1491. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1492. {
  1493. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1494. {
  1495. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgQuadCmd;
  1496. }
  1497. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1498. {
  1499. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1500. {
  1501. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgQpiCmd;
  1502. }
  1503. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1504. {
  1505. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgQpiCmd_4ByteAddr;
  1506. }
  1507. }
  1508. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1509. {
  1510. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1511. {
  1512. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProg4xIoCmd;
  1513. }
  1514. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1515. {
  1516. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProg4xIoCmd_4ByteAddr;
  1517. }
  1518. }
  1519. TxDataDma->cmdAddr[13] = 0x00;
  1520. TxDataDma->cmdAddr[14] = 0x00;
  1521. TxDataDma->cmdAddr[15] = 0x00;
  1522. TxDataDma->cmdAddr[16] = uiWtAddr & 0xff;
  1523. TxDataDma->cmdAddr[17] = (uiWtAddr >> 8) & 0xff;
  1524. TxDataDma->cmdAddr[18] = (uiWtAddr >> 16) & 0xff;
  1525. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1526. {
  1527. TxDataDma->cmdAddr[19] = 0x00;
  1528. }
  1529. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1530. {
  1531. TxDataDma->cmdAddr[19] = (uiWtAddr >> 24) & 0xff;
  1532. }
  1533. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1534. Flash_WriteEnable(pstFlash);
  1535. Flash_SetDmaBaudRate(pstFlash);
  1536. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1537. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1538. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1539. {
  1540. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1541. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1542. }
  1543. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1544. {
  1545. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1546. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1547. }
  1548. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1549. {
  1550. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_MULTI,
  1551. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1552. }
  1553. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[12], uiTxSize + 8);
  1554. }
  1555. return HV_SUCCESS;
  1556. }
  1557. static Status Flash_RecvQuadDma(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1558. {
  1559. QspiSelf* pstQspi = pstFlash->pstQspi;
  1560. UINT32 uiLoop = 0;
  1561. UCHAR8 aucCmdAddr[8] = {0};
  1562. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1563. {
  1564. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadQuadCmd;
  1565. }
  1566. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1567. {
  1568. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1569. {
  1570. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadQpiCmd;
  1571. }
  1572. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1573. {
  1574. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadQpiCmd_4ByteAddr;
  1575. }
  1576. }
  1577. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1578. {
  1579. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1580. {
  1581. aucCmdAddr[0] = pstFlash->flashAttr.FlashRead4xIoCmd;
  1582. }
  1583. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1584. {
  1585. aucCmdAddr[0] = pstFlash->flashAttr.FlashRead4xIoCmd_4ByteAddr;
  1586. }
  1587. }
  1588. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1589. {
  1590. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  1591. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  1592. aucCmdAddr[3] = uiRdAddr & 0xff;
  1593. }
  1594. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1595. {
  1596. aucCmdAddr[1] = (uiRdAddr >> 24) & 0xff;
  1597. aucCmdAddr[2] = (uiRdAddr >> 16) & 0xff;
  1598. aucCmdAddr[3] = (uiRdAddr >> 8) & 0xff;
  1599. aucCmdAddr[4] = uiRdAddr & 0xff;
  1600. }
  1601. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1602. Flash_SetDmaBaudRate(pstFlash);
  1603. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  1604. {
  1605. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1606. }
  1607. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1608. {
  1609. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1610. }
  1611. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1612. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1613. {
  1614. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  1615. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastQuad);
  1616. }
  1617. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1618. {
  1619. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1620. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleQpi);
  1621. }
  1622. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1623. {
  1624. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1625. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycle4xIo);
  1626. }
  1627. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1628. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1629. {
  1630. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize);
  1631. }
  1632. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1633. {
  1634. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 5, pucRxData, uiRxSize);
  1635. }
  1636. return HV_SUCCESS;
  1637. }
  1638. /**********************************************Quad API end *************************************/
  1639. /**********************************************flash db opration ********************************/
  1640. static QspiSelf* Flash_GetQspi(FlashSelf* pstFlash)
  1641. {
  1642. QspiSelf* pstQspi = pstFlash->pstQspi;
  1643. return pstQspi;
  1644. }
  1645. static Status Flash_SetBaudRate(FlashSelf* pstFlash,USHORT16 baudRate)
  1646. {
  1647. QspiSelf* pstQspi = pstFlash->pstQspi;
  1648. Hv_Cal_Qspi_SetBaudRate(pstQspi,(QspiDivideRatio)baudRate);
  1649. return HV_SUCCESS;
  1650. }
  1651. static FlashMultiIOType Flash_GetTransType(FlashSelf* pstFlash)
  1652. {
  1653. return pstFlash->InitParam.TransType;
  1654. }
  1655. static FlashAddressWidth Flash_GetAddrWidth(void* arg)
  1656. {
  1657. FlashSelf* pstFlash = (FlashSelf*)arg;
  1658. return pstFlash->InitParam.AddrWidth;
  1659. }
  1660. static FlashDataWidth Flash_GetDataSize(FlashSelf* pstFlash)
  1661. {
  1662. return pstFlash->InitParam.DataSize;
  1663. }
  1664. static FlashRateMode Flash_GetRateMode(FlashSelf* pstFlash)
  1665. {
  1666. return pstFlash->InitParam.RateMode;
  1667. }
  1668. static FlashAttribute* Flash_GetFlashAttribute(void* arg)
  1669. {
  1670. FlashSelf* pstFlash = (FlashSelf*)arg;
  1671. return &pstFlash->flashAttr;
  1672. }
  1673. static Status Flash_FourLineEnable(FlashSelf* pstFlash,FlashModel enFlashModel)
  1674. {
  1675. QspiSelf* pstQspi = Flash_GetQspi(pstFlash);
  1676. UCHAR8 switchCmd[4] = {0};
  1677. if (enFlashModel == FLASH_GD25)
  1678. {
  1679. switchCmd[0] = GD25_Flash_QuadEnable & 0xff;
  1680. switchCmd[1] = 0x00 & 0xff;
  1681. switchCmd[2] = 0x02 & 0xff;
  1682. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1683. Flash_WriteEnable(pstFlash);
  1684. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  1685. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1686. //HV_LOGI("GD25 flash quad mode is enable.\n");
  1687. }
  1688. else if (enFlashModel == FLASH_P25Q)
  1689. {
  1690. switchCmd[0] = P25Q_Flash_QuadEnable & 0xff;
  1691. switchCmd[1] = 0x02 & 0xff;
  1692. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1693. Flash_WriteEnable(pstFlash);
  1694. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  1695. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1696. //HV_LOGI("P25Q flash quad mode is enable.\n");
  1697. }
  1698. else if (enFlashModel == FLASH_MX25)
  1699. {
  1700. if ((Flash_GetTransType(pstFlash) == FLASH_MULTIIO_FAST_TYPE)
  1701. ||(Flash_GetTransType(pstFlash) == FLASH_ADDR_4LINE))
  1702. {
  1703. UCHAR8 aucStateCmd[2] = {0x05,0x00};
  1704. UCHAR8 aucRdState[2] = {0xff,0xff};
  1705. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1706. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1707. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1708. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  1709. // HV_LOGI("regVal[0] is 0x%x,regVal[1] is 0x%x.\n",aucRdState[0],aucRdState[1]);
  1710. if ((aucRdState[1] & 0x40) != 0x40)
  1711. {
  1712. switchCmd[0]=0x01;
  1713. switchCmd[1]=0x40;
  1714. Flash_WriteEnable(pstFlash);
  1715. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1716. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  1717. }
  1718. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1719. //HV_LOGI("MX25Q flash quad mode is enable.\n");
  1720. }
  1721. else if (Flash_GetTransType(pstFlash) == FLASH_INSTRUCT_ADDR_4LINE)
  1722. {
  1723. switchCmd[0] = MX25_Flash_QpiEnable & 0xff;
  1724. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1725. Flash_WriteEnable(pstFlash);
  1726. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 1, NULL, 0, FLASH_TIMEOUT);
  1727. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1728. //HV_LOGI("MX25Q flash qpi mode is enable.\n");
  1729. }
  1730. }
  1731. else if (enFlashModel == FLASH_W25Q)
  1732. {
  1733. UCHAR8 aucStateCmd[2] = {0x35,0x00};
  1734. UCHAR8 aucRdState[2] = {0xff,0xff};
  1735. UCHAR8 RdStateVerify[2] = {0xff,0xff};
  1736. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1737. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1738. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1739. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  1740. HV_LOGI("regVal[0] is 0x%x,regVal[1] is 0x%x.\n",aucRdState[0],aucRdState[1]);
  1741. if ((aucRdState[1] & 0x02) != 0x02)
  1742. {
  1743. switchCmd[0]=0x01;
  1744. switchCmd[1]=0x00;
  1745. switchCmd[2]=0x02;
  1746. Flash_WriteEnable(pstFlash);
  1747. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1748. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  1749. }
  1750. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1751. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, RdStateVerify, 0, FLASH_TIMEOUT);
  1752. HV_LOGI("regVal[0] is 0x%x,regVal[1] is 0x%x.\n",RdStateVerify[0],RdStateVerify[1]);
  1753. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1754. HV_LOGI("W25Q flash quad mode is enable.\n");
  1755. }
  1756. return HV_SUCCESS;
  1757. }
  1758. static VOID Flash_ReadStatusReg(UCHAR8 ucReg, UCHAR8* pucVal, UCHAR8 ucLen)
  1759. {
  1760. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  1761. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  1762. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1763. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1764. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1765. Hv_Cal_Qspi_PollingRead(pstQspi, &ucReg, 1, pucVal, ucLen, FLASH_TIMEOUT);
  1766. Hv_Cal_Qspi_SetRateMode(pstQspi,RateMode);
  1767. HV_LOGV("read status is 0x%x:0x%x.\n",ucReg, *pucVal);
  1768. return;
  1769. }
  1770. static VOID Flash_WriteStatusReg(UCHAR8 ucReg, UCHAR8 ucVal)
  1771. {
  1772. UCHAR8 switchCmd[2] = {0};
  1773. switchCmd[0] = ucReg;
  1774. switchCmd[1] = ucVal;
  1775. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  1776. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  1777. Flash_WriteEnable(&g_stFlash);
  1778. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1779. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1780. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1781. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  1782. Hv_Cal_Qspi_SetRateMode(pstQspi,RateMode);
  1783. HV_LOGV("write status is 0x%x:0x%x.\n",ucReg, ucVal);
  1784. return;
  1785. }
  1786. static VOID Flash_WriteStatusRegDB(UCHAR8 ucReg, UCHAR8 pucLow, UCHAR8 pucHigh)
  1787. {
  1788. UCHAR8 switchCmd[3] = {0};
  1789. switchCmd[0] = ucReg;
  1790. switchCmd[1] = pucLow;
  1791. switchCmd[2] = pucHigh;
  1792. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  1793. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  1794. Flash_WriteEnable(&g_stFlash);
  1795. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1796. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1797. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1798. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  1799. Hv_Cal_Qspi_SetRateMode(pstQspi,RateMode);
  1800. HV_LOGV("write status is 0x%x:0x%x.0x%x\n",ucReg, pucLow, pucHigh);
  1801. return;
  1802. }
  1803. static VOID Flash_WriteAddrProtect(UINT32 uiFlashID, UINT32 uiAddr, UCHAR8 ucProtectDisable)
  1804. {
  1805. UCHAR8 ucStatus = 0;
  1806. UCHAR8 ucNeedWp = 0;
  1807. UCHAR8 aucStatus[3] = {0x0};
  1808. HV_LOGV("ucProtectDisable 0x%x:0x%x\n",ucProtectDisable, uiAddr);
  1809. switch (uiFlashID)
  1810. {
  1811. /* mx25v1635 bit2-bit5:bp0-bp3 tb bit use 0 default. */
  1812. case 0xc22315:
  1813. {
  1814. Flash_ReadStatusReg(0x05, &ucStatus, 1);
  1815. if (1 == ucProtectDisable)
  1816. {
  1817. /* 1 1 1 0 protect:0-30 */
  1818. if (uiAddr >= 0x1f0000)
  1819. {
  1820. ucStatus |= 0xe << 2;
  1821. ucStatus &= ~(0x1 << 2);
  1822. }
  1823. /* 1 1 0 1 protect:0-29 */
  1824. else if (uiAddr >= 0x1e0000)
  1825. {
  1826. ucStatus |= 0xd << 2;
  1827. ucStatus &= ~(0x2 << 2);
  1828. }
  1829. /* 1 1 0 0 protect:0-27 */
  1830. else if (uiAddr >= 0x1c0000)
  1831. {
  1832. ucStatus |= 0xc << 2;
  1833. ucStatus &= ~(0x3 << 2);
  1834. }
  1835. /* 1 0 1 1 protect:0-23 */
  1836. else if (uiAddr >= 0x180000)
  1837. {
  1838. ucStatus |= 0xb << 2;
  1839. ucStatus &= ~(0x4 << 2);
  1840. }
  1841. /* 1 0 1 0 protect:0-16 */
  1842. else if (uiAddr >= 0x100000)
  1843. {
  1844. ucStatus |= 0xc << 2;
  1845. ucStatus &= ~(0x5 << 2);
  1846. }
  1847. /* 0 1 0 1 protect:16-31 */
  1848. else
  1849. {
  1850. ucStatus |= 0x5 << 2;
  1851. ucStatus &= ~(0xa << 2);
  1852. }
  1853. /* set swrd bit. */
  1854. ucStatus |= 0x1 << 7;
  1855. Flash_WriteStatusRegDB(0x01, ucStatus, 0);
  1856. }
  1857. else if (0xaa == ucProtectDisable)
  1858. {
  1859. /* 0 0 0 0*/
  1860. ucStatus &= ~ (0xf << 2);
  1861. /* set swrd bit. */
  1862. ucStatus &= ~ (0x1 << 7);
  1863. Flash_WriteStatusRegDB(0x01, ucStatus, 0);
  1864. }
  1865. else
  1866. {
  1867. /* 1 1 1 1*/
  1868. ucStatus |= 0xf << 2;
  1869. /* set swrd bit. */
  1870. ucStatus |= 0x1 << 7;
  1871. Flash_WriteStatusRegDB(0x01, ucStatus, 0);
  1872. }
  1873. Hv_Vos_MSleep(40);
  1874. break;
  1875. }
  1876. /* mx25l1606e.mx25v16066 bit2-bit5:bp0-bp3 */
  1877. case 0xc22015:
  1878. {
  1879. Flash_ReadStatusReg(0x05, &ucStatus, 1);
  1880. if (1 == ucProtectDisable)
  1881. {
  1882. /* 1 1 1 0 protect:0-30 */
  1883. if (uiAddr >= 0x1f0000)
  1884. {
  1885. ucStatus |= 0xe << 2;
  1886. ucStatus &= ~(0x1 << 2);
  1887. }
  1888. /* 1 1 0 1 protect:0-29 */
  1889. else if (uiAddr >= 0x1e0000)
  1890. {
  1891. ucStatus |= 0xd << 2;
  1892. ucStatus &= ~(0x2 << 2);
  1893. }
  1894. /* 1 1 0 0 protect:0-27 */
  1895. else if (uiAddr >= 0x1c0000)
  1896. {
  1897. ucStatus |= 0xc << 2;
  1898. ucStatus &= ~(0x3 << 2);
  1899. }
  1900. /* 1 0 1 1 protect:0-23 */
  1901. else if (uiAddr >= 0x180000)
  1902. {
  1903. ucStatus |= 0xb << 2;
  1904. ucStatus &= ~(0x4 << 2);
  1905. }
  1906. /* 1 0 1 0 protect:0-16 */
  1907. else if (uiAddr >= 0x100000)
  1908. {
  1909. ucStatus |= 0xc << 2;
  1910. ucStatus &= ~(0x5 << 2);
  1911. }
  1912. /* 0 1 0 1 protect:16-31 */
  1913. else
  1914. {
  1915. ucStatus |= 0x5 << 2;
  1916. ucStatus &= ~(0xa << 2);
  1917. }
  1918. /* set swrd bit. */
  1919. ucStatus |= 0x1 << 7;
  1920. Flash_WriteStatusReg(0x01, ucStatus);
  1921. }
  1922. else if (0xaa == ucProtectDisable)
  1923. {
  1924. /* 0 0 0 0*/
  1925. ucStatus &= ~ (0xf << 2);
  1926. /* set swrd bit. */
  1927. ucStatus &= ~ (0x1 << 7);
  1928. Flash_WriteStatusReg(0x01, ucStatus);
  1929. }
  1930. else
  1931. {
  1932. /* 1 1 1 1*/
  1933. ucStatus |= 0xf << 2;
  1934. /* set swrd bit. */
  1935. ucStatus |= 0x1 << 7;
  1936. Flash_WriteStatusReg(0x01, ucStatus);
  1937. }
  1938. Hv_Vos_MSleep(40);
  1939. break;
  1940. }
  1941. /* XM25QH16C bit14:bmp bit2-bit6:bp0-bp4*/
  1942. /* BY25Q16ES bit14:bmp bit2-bit6:bp0-bp4*/
  1943. case 0x204015:
  1944. case 0x684015:
  1945. {
  1946. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  1947. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  1948. if (1 == ucProtectDisable)
  1949. {
  1950. /* cmp 1, 1 0 0 0 1 protect:0-31 */
  1951. if (uiAddr >= 0x1ff000)
  1952. {
  1953. aucStatus[0] |= 0x11 << 2;
  1954. aucStatus[0] &= ~(0xe << 2);
  1955. }
  1956. /* cmp 1, 1 0 0 1 0 protect:0-31 */
  1957. else if (uiAddr >= 0x1fe000)
  1958. {
  1959. aucStatus[0] |= 0x12 << 2;
  1960. aucStatus[0] &= ~(0xd << 2);
  1961. }
  1962. /* cmp 1, 1 0 0 1 1 protect:0-31 */
  1963. else if (uiAddr >= 0x1fc000)
  1964. {
  1965. aucStatus[0] |= 0x13 << 2;
  1966. aucStatus[0] &= ~(0xc << 2);
  1967. }
  1968. /* cmp 1, 1 0 1 0 x protect:0-31 */
  1969. else if (uiAddr >= 0x1f8000)
  1970. {
  1971. aucStatus[0] |= 0x14 << 2;
  1972. aucStatus[0] &= ~(0xa << 2);
  1973. }
  1974. /* cmp 1, 0 0 0 0 1 protect:0-30 */
  1975. else if (uiAddr >= 0x1f0000)
  1976. {
  1977. aucStatus[0] |= 0x1 << 2;
  1978. aucStatus[0] &= ~(0x1e << 2);
  1979. }
  1980. /* cmp 1, 0 0 0 1 0 protect:0-29 */
  1981. else if (uiAddr >= 0x1e0000)
  1982. {
  1983. aucStatus[0] |= 0x2 << 2;
  1984. aucStatus[0] &= ~(0x1d << 2);
  1985. }
  1986. /* cmp 1, 0 0 0 1 1 protect:0-27 */
  1987. else if (uiAddr >= 0x1c0000)
  1988. {
  1989. aucStatus[0] |= 0x3 << 2;
  1990. aucStatus[0] &= ~(0x1c << 2);
  1991. }
  1992. /* cmp 1, 0 0 1 0 0 protect:0-23 */
  1993. else if (uiAddr >= 0x180000)
  1994. {
  1995. aucStatus[0] |= 0x4 << 2;
  1996. aucStatus[0] &= ~(0x1b << 2);
  1997. }
  1998. /* cmp 1, 0 0 1 0 1 protect:0-15 */
  1999. else if (uiAddr >= 0x100000)
  2000. {
  2001. aucStatus[0] |= 0x5 << 2;
  2002. aucStatus[0] &= ~(0x1a << 2);
  2003. }
  2004. /* cmp 1, 1 1 0 0 1 protect:0-31 */
  2005. else if (uiAddr < 0x1000)
  2006. {
  2007. aucStatus[0] |= 0x19 << 2;
  2008. aucStatus[0] &= ~(0x6 << 2);
  2009. }
  2010. /* cmp 1, 1 1 0 1 0 protect:0-31 */
  2011. else if (uiAddr < 0x2000)
  2012. {
  2013. aucStatus[0] |= 0x1a << 2;
  2014. aucStatus[0] &= ~(0x5 << 2);
  2015. }
  2016. /* cmp 1, 1 1 0 1 1 protect:0-31 */
  2017. else if (uiAddr < 0x4000)
  2018. {
  2019. aucStatus[0] |= 0x1b << 2;
  2020. aucStatus[0] &= ~(0x4 << 2);
  2021. }
  2022. /* cmp 1, 1 1 1 0 x protect:0-31 */
  2023. else if (uiAddr < 0x8000)
  2024. {
  2025. aucStatus[0] |= 0x1c << 2;
  2026. aucStatus[0] &= ~(0x3 << 2);
  2027. }
  2028. /* cmp 1, 0 1 0 0 1 protect:1-31 */
  2029. else if (uiAddr < 0x10000)
  2030. {
  2031. aucStatus[0] |= 0x9 << 2;
  2032. aucStatus[0] &= ~(0x16 << 2);
  2033. }
  2034. /* cmp 1, 0 1 0 1 0 protect:2-31 */
  2035. else if (uiAddr < 0x20000)
  2036. {
  2037. aucStatus[0] |= 0xa << 2;
  2038. aucStatus[0] &= ~(0x15 << 2);
  2039. }
  2040. /* cmp 1, 0 1 0 1 1 protect:4-31 */
  2041. else if (uiAddr < 0x40000)
  2042. {
  2043. aucStatus[0] |= 0xb << 2;
  2044. aucStatus[0] &= ~(0x14 << 2);
  2045. }
  2046. /* cmp 1, 0 1 1 0 0 protect:8-31 */
  2047. else if (uiAddr < 0x80000)
  2048. {
  2049. aucStatus[0] |= 0xc << 2;
  2050. aucStatus[0] &= ~(0x13 << 2);
  2051. }
  2052. /* cmp 1, 0 1 1 0 1 protect:16-31 */
  2053. else //(uiAddr < 0x100000)
  2054. {
  2055. aucStatus[0] |= 0xd << 2;
  2056. aucStatus[0] &= ~(0x12 << 2);
  2057. }
  2058. /* set srp0 1 & srp1 0. */
  2059. aucStatus[0] |= 1 << 7;
  2060. aucStatus[1] &= ~ (0x1);
  2061. /* set cmp bit 1. */
  2062. aucStatus[1] |= 0x1 << 6;
  2063. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2064. Hv_Vos_MSleep(10);
  2065. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2066. Hv_Vos_MSleep(10);
  2067. }
  2068. else if (0xaa == ucProtectDisable)
  2069. {
  2070. /* cmp 0, x x 0 0 0 */
  2071. aucStatus[0] &= ~ (0x7 << 2);
  2072. aucStatus[1] &= ~(0x1 << 6);
  2073. /* set srp0 0 & srp1 0. */
  2074. aucStatus[0] &= ~ (1 << 7);
  2075. aucStatus[1] &= ~ (0x1);
  2076. Flash_WriteStatusReg(0x01, 0);
  2077. Hv_Vos_MSleep(10);
  2078. Flash_WriteStatusReg(0x31, 0);
  2079. }
  2080. else
  2081. {
  2082. /* cmp 0, x x 1 1 x */
  2083. aucStatus[0] |= 0x6 << 2;
  2084. aucStatus[1] &= ~(0x1 << 6);
  2085. /* set srp0 1 & srp1 0. */
  2086. aucStatus[0] |= 1 << 7;
  2087. aucStatus[1] &= ~ (0x1);
  2088. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2089. Hv_Vos_MSleep(10);
  2090. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2091. }
  2092. Hv_Vos_MSleep(50);
  2093. break;
  2094. }
  2095. /* GD25Q16E bit14:bmp bit2-bit6:bp0-bp4*/
  2096. case 0xc84015:
  2097. {
  2098. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2099. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2100. if (1 == ucProtectDisable)
  2101. {
  2102. /* cmp 1, 1 0 0 0 1 protect:0-31 */
  2103. if (uiAddr >= 0x1ff000)
  2104. {
  2105. aucStatus[0] |= 0x11 << 2;
  2106. aucStatus[0] &= ~(0xe << 2);
  2107. }
  2108. /* cmp 1, 1 0 0 1 0 protect:0-31 */
  2109. else if (uiAddr >= 0x1fe000)
  2110. {
  2111. aucStatus[0] |= 0x12 << 2;
  2112. aucStatus[0] &= ~(0xd << 2);
  2113. }
  2114. /* cmp 1, 1 0 0 1 1 protect:0-31 */
  2115. else if (uiAddr >= 0x1fc000)
  2116. {
  2117. aucStatus[0] |= 0x13 << 2;
  2118. aucStatus[0] &= ~(0xc << 2);
  2119. }
  2120. /* cmp 1, 1 0 1 0 x protect:0-31 */
  2121. else if (uiAddr >= 0x1f8000)
  2122. {
  2123. aucStatus[0] |= 0x14 << 2;
  2124. aucStatus[0] &= ~(0xa << 2);
  2125. }
  2126. /* cmp 1, 0 0 0 0 1 protect:0-30 */
  2127. else if (uiAddr >= 0x1f0000)
  2128. {
  2129. aucStatus[0] |= 0x1 << 2;
  2130. aucStatus[0] &= ~(0x1e << 2);
  2131. }
  2132. /* cmp 1, 0 0 0 1 0 protect:0-29 */
  2133. else if (uiAddr >= 0x1e0000)
  2134. {
  2135. aucStatus[0] |= 0x2 << 2;
  2136. aucStatus[0] &= ~(0x1d << 2);
  2137. }
  2138. /* cmp 1, 0 0 0 1 1 protect:0-27 */
  2139. else if (uiAddr >= 0x1c0000)
  2140. {
  2141. aucStatus[0] |= 0x3 << 2;
  2142. aucStatus[0] &= ~(0x1c << 2);
  2143. }
  2144. /* cmp 1, 0 0 1 0 0 protect:0-23 */
  2145. else if (uiAddr >= 0x180000)
  2146. {
  2147. aucStatus[0] |= 0x4 << 2;
  2148. aucStatus[0] &= ~(0x1b << 2);
  2149. }
  2150. /* cmp 1, 0 0 1 0 1 protect:0-15 */
  2151. else if (uiAddr >= 0x100000)
  2152. {
  2153. aucStatus[0] |= 0x5 << 2;
  2154. aucStatus[0] &= ~(0x1a << 2);
  2155. }
  2156. /* cmp 1, 1 1 0 0 1 protect:0-31 */
  2157. else if (uiAddr < 0x1000)
  2158. {
  2159. aucStatus[0] |= 0x19 << 2;
  2160. aucStatus[0] &= ~(0x6 << 2);
  2161. }
  2162. /* cmp 1, 1 1 0 1 0 protect:0-31 */
  2163. else if (uiAddr < 0x2000)
  2164. {
  2165. aucStatus[0] |= 0x1a << 2;
  2166. aucStatus[0] &= ~(0x5 << 2);
  2167. }
  2168. /* cmp 1, 1 1 0 1 1 protect:0-31 */
  2169. else if (uiAddr < 0x4000)
  2170. {
  2171. aucStatus[0] |= 0x1b << 2;
  2172. aucStatus[0] &= ~(0x4 << 2);
  2173. }
  2174. /* cmp 1, 1 1 1 0 x protect:0-31 */
  2175. else if (uiAddr < 0x8000)
  2176. {
  2177. aucStatus[0] |= 0x1c << 2;
  2178. aucStatus[0] &= ~(0x3 << 2);
  2179. }
  2180. /* cmp 1, 0 1 0 0 1 protect:1-31 */
  2181. else if (uiAddr < 0x10000)
  2182. {
  2183. aucStatus[0] |= 0x9 << 2;
  2184. aucStatus[0] &= ~(0x16 << 2);
  2185. }
  2186. /* cmp 1, 0 1 0 1 0 protect:2-31 */
  2187. else if (uiAddr < 0x20000)
  2188. {
  2189. aucStatus[0] |= 0xa << 2;
  2190. aucStatus[0] &= ~(0x15 << 2);
  2191. }
  2192. /* cmp 1, 0 1 0 1 1 protect:4-31 */
  2193. else if (uiAddr < 0x40000)
  2194. {
  2195. aucStatus[0] |= 0xb << 2;
  2196. aucStatus[0] &= ~(0x14 << 2);
  2197. }
  2198. /* cmp 1, 0 1 1 0 0 protect:8-31 */
  2199. else if (uiAddr < 0x80000)
  2200. {
  2201. aucStatus[0] |= 0xc << 2;
  2202. aucStatus[0] &= ~(0x13 << 2);
  2203. }
  2204. /* cmp 1, 0 1 1 0 1 protect:16-31 */
  2205. else //(uiAddr < 0x100000)
  2206. {
  2207. aucStatus[0] |= 0xd << 2;
  2208. aucStatus[0] &= ~(0x12 << 2);
  2209. }
  2210. /* set srp0 1 & srp1 0. */
  2211. aucStatus[0] |= 1 << 7;
  2212. aucStatus[1] &= ~ (0x1);
  2213. /* set cmp bit 1. */
  2214. aucStatus[1] |= 0x1 << 6;
  2215. Flash_WriteStatusRegDB(0x01, aucStatus[0], aucStatus[1]);
  2216. }
  2217. else if (0xaa == ucProtectDisable)
  2218. {
  2219. /* cmp 0, x x 0 0 0 */
  2220. aucStatus[0] &= ~ (0x7 << 2);
  2221. aucStatus[1] &= ~(0x1 << 6);
  2222. /* set srp0 0 & srp1 0. */
  2223. aucStatus[0] &= ~ (1 << 7);
  2224. aucStatus[1] &= ~ (0x1);
  2225. Flash_WriteStatusRegDB(0x01, aucStatus[0], aucStatus[1]);
  2226. }
  2227. else
  2228. {
  2229. /* cmp 0, x x 1 1 x */
  2230. if ((aucStatus[0] & 0x18) != 0x18)
  2231. {
  2232. ucNeedWp = 1;
  2233. }
  2234. if ((aucStatus[1] & 0x40) == 0x40)
  2235. {
  2236. ucNeedWp = 1;
  2237. }
  2238. HV_LOGV("wp status %x, %x", aucStatus[0], aucStatus[1]);
  2239. aucStatus[0] |= 0x6 << 2;
  2240. aucStatus[1] &= ~(0x1 << 6);
  2241. /* set srp0 1 & srp1 0. */
  2242. aucStatus[0] |= 1 << 7;
  2243. aucStatus[1] &= ~ (0x1);
  2244. if (ucNeedWp)
  2245. {
  2246. HV_LOGV("##need wp");
  2247. Flash_WriteStatusRegDB(0x01, aucStatus[0], aucStatus[1]);
  2248. Hv_Vos_MSleep(30);
  2249. }
  2250. }
  2251. break;
  2252. }
  2253. /* winbond w25q16 bit18:wps bit14:cmp bit2-bit6:sec,tb,bp0-bp3*/
  2254. case 0xef4015:
  2255. {
  2256. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2257. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2258. Flash_ReadStatusReg(0x15, &aucStatus[2], 1);
  2259. if (1 == ucProtectDisable)
  2260. {
  2261. #if 0
  2262. /* cmp 1, 1 0 0 0 1 protect:0-31 */
  2263. if (uiAddr >= 0x1ff000)
  2264. {
  2265. aucStatus[0] |= 0x11 << 2;
  2266. aucStatus[0] &= ~(0xe << 2);
  2267. }
  2268. /* cmp 1, 1 0 0 1 0 protect:0-31 */
  2269. else if (uiAddr >= 0x1fe000)
  2270. {
  2271. aucStatus[0] |= 0x12 << 2;
  2272. aucStatus[0] &= ~(0xd << 2);
  2273. }
  2274. /* cmp 1, 1 0 0 1 1 protect:0-31 */
  2275. else if (uiAddr >= 0x1fc000)
  2276. {
  2277. aucStatus[0] |= 0x13 << 2;
  2278. aucStatus[0] &= ~(0xc << 2);
  2279. }
  2280. /* cmp 1, 1 0 1 0 x protect:0-31 */
  2281. else if (uiAddr >= 0x1f8000)
  2282. {
  2283. aucStatus[0] |= 0x14 << 2;
  2284. aucStatus[0] &= ~(0xa << 2);
  2285. }
  2286. /* cmp 1, 0 0 0 0 1 protect:0-30 */
  2287. else if (uiAddr >= 0x1f0000)
  2288. {
  2289. aucStatus[0] |= 0x1 << 2;
  2290. aucStatus[0] &= ~(0x1e << 2);
  2291. }
  2292. /* cmp 1, 0 0 0 1 0 protect:0-29 */
  2293. else if (uiAddr >= 0x1e0000)
  2294. {
  2295. aucStatus[0] |= 0x2 << 2;
  2296. aucStatus[0] &= ~(0x1d << 2);
  2297. }
  2298. /* cmp 1, 0 0 0 1 1 protect:0-27 */
  2299. else if (uiAddr >= 0x1c0000)
  2300. {
  2301. aucStatus[0] |= 0x3 << 2;
  2302. aucStatus[0] &= ~(0x1c << 2);
  2303. }
  2304. /* cmp 1, 0 0 1 0 0 protect:0-23 */
  2305. else if (uiAddr >= 0x180000)
  2306. {
  2307. aucStatus[0] |= 0x4 << 2;
  2308. aucStatus[0] &= ~(0x1b << 2);
  2309. }
  2310. /* cmp 1, 0 0 1 0 1 protect:0-15 */
  2311. else if (uiAddr >= 0x100000)
  2312. {
  2313. aucStatus[0] |= 0x5 << 2;
  2314. aucStatus[0] &= ~(0x1a << 2);
  2315. }
  2316. /* cmp 1, 1 1 0 0 1 protect:0-31 */
  2317. else if (uiAddr < 0x1000)
  2318. {
  2319. aucStatus[0] |= 0x19 << 2;
  2320. aucStatus[0] &= ~(0x6 << 2);
  2321. }
  2322. /* cmp 1, 1 1 0 1 0 protect:0-31 */
  2323. else if (uiAddr < 0x2000)
  2324. {
  2325. aucStatus[0] |= 0x1a << 2;
  2326. aucStatus[0] &= ~(0x5 << 2);
  2327. }
  2328. /* cmp 1, 1 1 0 1 1 protect:0-31 */
  2329. else if (uiAddr < 0x4000)
  2330. {
  2331. aucStatus[0] |= 0x1b << 2;
  2332. aucStatus[0] &= ~(0x4 << 2);
  2333. }
  2334. /* cmp 1, 1 1 1 0 x protect:0-31 */
  2335. else if (uiAddr < 0x8000)
  2336. {
  2337. aucStatus[0] |= 0x1c << 2;
  2338. aucStatus[0] &= ~(0x3 << 2);
  2339. }
  2340. /* cmp 1, 0 1 0 0 1 protect:1-31 */
  2341. else if (uiAddr < 0x10000)
  2342. {
  2343. aucStatus[0] |= 0x9 << 2;
  2344. aucStatus[0] &= ~(0x16 << 2);
  2345. }
  2346. /* cmp 1, 0 1 0 1 0 protect:2-31 */
  2347. else if (uiAddr < 0x20000)
  2348. {
  2349. aucStatus[0] |= 0xa << 2;
  2350. aucStatus[0] &= ~(0x15 << 2);
  2351. }
  2352. /* cmp 1, 0 1 0 1 1 protect:4-31 */
  2353. else if (uiAddr < 0x40000)
  2354. {
  2355. aucStatus[0] |= 0xb << 2;
  2356. aucStatus[0] &= ~(0x14 << 2);
  2357. }
  2358. /* cmp 1, 0 1 1 0 0 protect:8-31 */
  2359. else if (uiAddr < 0x80000)
  2360. {
  2361. aucStatus[0] |= 0xc << 2;
  2362. aucStatus[0] &= ~(0x13 << 2);
  2363. }
  2364. /* cmp 1, 0 1 1 0 1 protect:16-31 */
  2365. else //(uiAddr < 0x100000)
  2366. {
  2367. aucStatus[0] |= 0xd << 2;
  2368. aucStatus[0] &= ~(0x12 << 2);
  2369. }
  2370. /* set srp0 1 & srp1 0. */
  2371. aucStatus[0] |= 1 << 7;
  2372. aucStatus[1] &= ~ (0x1);
  2373. /* set cmp bit 1. */
  2374. aucStatus[1] |= 0x1 << 6;
  2375. /* set wps 0 */
  2376. aucStatus[2] &= ~ (0x1 << 2);
  2377. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2378. Hv_Vos_MSleep(15);
  2379. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2380. Hv_Vos_MSleep(15);
  2381. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2382. #else
  2383. /* wps 0, cmp 0 , x x 0 0 0 srp: 0 srl: 0 */
  2384. aucStatus[0] &= ~ (0x7 << 2);
  2385. aucStatus[0] &= ~ (0x1 << 7);
  2386. aucStatus[1] &= ~ (0x1 << 0);
  2387. aucStatus[1] &= ~ (0x1 << 6);
  2388. aucStatus[2] &= ~ (0x1 << 2);
  2389. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2390. Hv_Vos_MSleep(15);
  2391. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2392. Hv_Vos_MSleep(15);
  2393. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2394. #endif
  2395. }
  2396. else if (0xaa == ucProtectDisable)
  2397. {
  2398. /* wps 0, cmp 0 , x x 0 0 0 srp: 0 srl: 0 */
  2399. aucStatus[0] &= ~ (0x7 << 2);
  2400. aucStatus[0] &= ~ (0x1 << 7);
  2401. aucStatus[1] &= ~ (0x1 << 0);
  2402. aucStatus[1] &= ~ (0x1 << 6);
  2403. aucStatus[2] &= ~ (0x1 << 2);
  2404. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2405. Hv_Vos_MSleep(15);
  2406. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2407. Hv_Vos_MSleep(15);
  2408. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2409. }
  2410. else
  2411. {
  2412. /* wps 0, cmp 0 , x x 1 1 1 srp: 1 srl: 0 */
  2413. aucStatus[0] |= 0x7 << 2;
  2414. aucStatus[0] |= 0x1 << 7;
  2415. aucStatus[1] &= ~ (0x1 << 0);
  2416. aucStatus[1] &= ~ (0x1 << 6);
  2417. aucStatus[2] &= ~ (0x1 << 2);
  2418. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2419. Hv_Vos_MSleep(15);
  2420. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2421. Hv_Vos_MSleep(15);
  2422. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2423. }
  2424. Hv_Vos_MSleep(15);
  2425. break;
  2426. }
  2427. /* BY25Q32ES bit14:bmp bit2-bit6:bp0-bp4*/
  2428. case 0x684016:
  2429. {
  2430. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2431. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2432. if (1 == ucProtectDisable)
  2433. {
  2434. /* cmp 1, 1 0 0 0 1 protect:0-31 */
  2435. if (uiAddr >= 0x3ff000)
  2436. {
  2437. aucStatus[0] |= 0x11 << 2;
  2438. aucStatus[0] &= ~(0xe << 2);
  2439. }
  2440. /* cmp 1, 1 0 0 1 0 protect:0-31 */
  2441. else if (uiAddr >= 0x3fe000)
  2442. {
  2443. aucStatus[0] |= 0x12 << 2;
  2444. aucStatus[0] &= ~(0xd << 2);
  2445. }
  2446. /* cmp 1, 1 0 0 1 1 protect:0-31 */
  2447. else if (uiAddr >= 0x3fc000)
  2448. {
  2449. aucStatus[0] |= 0x13 << 2;
  2450. aucStatus[0] &= ~(0xc << 2);
  2451. }
  2452. /* cmp 1, 1 0 1 0 x protect:0-31 */
  2453. else if (uiAddr >= 0x3f8000)
  2454. {
  2455. aucStatus[0] |= 0x14 << 2;
  2456. aucStatus[0] &= ~(0xa << 2);
  2457. }
  2458. /* cmp 1, 0 0 0 0 1 protect:0-30 */
  2459. else if (uiAddr >= 0x3f0000)
  2460. {
  2461. aucStatus[0] |= 0x1 << 2;
  2462. aucStatus[0] &= ~(0x1e << 2);
  2463. }
  2464. /* cmp 1, 0 0 0 1 0 protect:0-29 */
  2465. else if (uiAddr >= 0x3e0000)
  2466. {
  2467. aucStatus[0] |= 0x2 << 2;
  2468. aucStatus[0] &= ~(0x1d << 2);
  2469. }
  2470. /* cmp 1, 0 0 0 1 1 protect:0-27 */
  2471. else if (uiAddr >= 0x3c0000)
  2472. {
  2473. aucStatus[0] |= 0x3 << 2;
  2474. aucStatus[0] &= ~(0x1c << 2);
  2475. }
  2476. /* cmp 1, 0 0 1 0 0 protect:0-23 */
  2477. else if (uiAddr >= 0x380000)
  2478. {
  2479. aucStatus[0] |= 0x4 << 2;
  2480. aucStatus[0] &= ~(0x1b << 2);
  2481. }
  2482. /* cmp 1, 0 0 1 0 1 protect:0-15 */
  2483. else if (uiAddr >= 0x300000)
  2484. {
  2485. aucStatus[0] |= 0x5 << 2;
  2486. aucStatus[0] &= ~(0x1a << 2);
  2487. }
  2488. /* cmp 1, 0 0 1 1 0 protect:0-15 */
  2489. else if (uiAddr >= 0x200000)
  2490. {
  2491. aucStatus[0] |= 0x6 << 2;
  2492. aucStatus[0] &= ~(0x19 << 2);
  2493. }
  2494. /* cmp 1, 1 1 0 0 1 protect:0-31 */
  2495. else if (uiAddr < 0x1000)
  2496. {
  2497. aucStatus[0] |= 0x19 << 2;
  2498. aucStatus[0] &= ~(0x6 << 2);
  2499. }
  2500. /* cmp 1, 1 1 0 1 0 protect:0-31 */
  2501. else if (uiAddr < 0x2000)
  2502. {
  2503. aucStatus[0] |= 0x1a << 2;
  2504. aucStatus[0] &= ~(0x5 << 2);
  2505. }
  2506. /* cmp 1, 1 1 0 1 1 protect:0-31 */
  2507. else if (uiAddr < 0x4000)
  2508. {
  2509. aucStatus[0] |= 0x1b << 2;
  2510. aucStatus[0] &= ~(0x4 << 2);
  2511. }
  2512. /* cmp 1, 1 1 1 0 x protect:0-31 */
  2513. else if (uiAddr < 0x8000)
  2514. {
  2515. aucStatus[0] |= 0x1c << 2;
  2516. aucStatus[0] &= ~(0x3 << 2);
  2517. }
  2518. /* cmp 1, 0 1 0 0 1 protect:1-31 */
  2519. else if (uiAddr < 0x10000)
  2520. {
  2521. aucStatus[0] |= 0x9 << 2;
  2522. aucStatus[0] &= ~(0x16 << 2);
  2523. }
  2524. /* cmp 1, 0 1 0 1 0 protect:2-31 */
  2525. else if (uiAddr < 0x20000)
  2526. {
  2527. aucStatus[0] |= 0xa << 2;
  2528. aucStatus[0] &= ~(0x15 << 2);
  2529. }
  2530. /* cmp 1, 0 1 0 1 1 protect:4-31 */
  2531. else if (uiAddr < 0x40000)
  2532. {
  2533. aucStatus[0] |= 0xb << 2;
  2534. aucStatus[0] &= ~(0x14 << 2);
  2535. }
  2536. /* cmp 1, 0 1 1 0 0 protect:8-31 */
  2537. else if (uiAddr < 0x80000)
  2538. {
  2539. aucStatus[0] |= 0xc << 2;
  2540. aucStatus[0] &= ~(0x13 << 2);
  2541. }
  2542. /* cmp 1, 0 1 1 0 1 protect:16-31 */
  2543. else //(uiAddr < 0x100000)
  2544. {
  2545. aucStatus[0] |= 0xd << 2;
  2546. aucStatus[0] &= ~(0x12 << 2);
  2547. }
  2548. /* set srp0 1 & srp1 0. */
  2549. aucStatus[0] |= 1 << 7;
  2550. aucStatus[1] &= ~ (0x1);
  2551. /* set cmp bit 1. */
  2552. aucStatus[1] |= 0x1 << 6;
  2553. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2554. Hv_Vos_MSleep(10);
  2555. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2556. Hv_Vos_MSleep(10);
  2557. }
  2558. else if (0xaa == ucProtectDisable)
  2559. {
  2560. /* cmp 0, x x 0 0 0 */
  2561. aucStatus[0] &= ~ (0x7 << 2);
  2562. aucStatus[1] &= ~(0x1 << 6);
  2563. /* set srp0 0 & srp1 0. */
  2564. aucStatus[0] &= ~ (1 << 7);
  2565. aucStatus[1] &= ~ (0x1);
  2566. Flash_WriteStatusReg(0x01, 0);
  2567. Hv_Vos_MSleep(10);
  2568. Flash_WriteStatusReg(0x31, 0);
  2569. }
  2570. else
  2571. {
  2572. /* cmp 0, x x 1 1 x */
  2573. aucStatus[0] |= 0x6 << 2;
  2574. aucStatus[1] &= ~(0x1 << 6);
  2575. /* set srp0 1 & srp1 0. */
  2576. aucStatus[0] |= 1 << 7;
  2577. aucStatus[1] &= ~ (0x1);
  2578. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2579. Hv_Vos_MSleep(10);
  2580. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2581. }
  2582. Hv_Vos_MSleep(30);
  2583. break;
  2584. }
  2585. /* winbond w25q32 */
  2586. case 0xef4016:
  2587. {
  2588. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2589. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2590. Flash_ReadStatusReg(0x15, &aucStatus[2], 1);
  2591. if (1 == ucProtectDisable)
  2592. {
  2593. /* wps 0, cmp 0 , x x 0 0 0 srp: 1 srl: 0 */
  2594. aucStatus[0] &= ~ (0x7 << 2);
  2595. aucStatus[0] |= 0x1 << 7;
  2596. aucStatus[1] &= ~ (0x1 << 0);
  2597. aucStatus[1] &= ~ (0x1 << 6);
  2598. aucStatus[2] &= ~ (0x1 << 2);
  2599. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2600. Hv_Vos_MSleep(15);
  2601. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2602. Hv_Vos_MSleep(15);
  2603. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2604. }
  2605. else if (0xaa == ucProtectDisable)
  2606. {
  2607. /* wps 0, cmp 0 , x x 0 0 0 srp: 0 srl: 0 */
  2608. aucStatus[0] &= ~ (0x7 << 2);
  2609. aucStatus[0] &= ~ (0x1 << 7);
  2610. aucStatus[1] &= ~ (0x1 << 0);
  2611. aucStatus[1] &= ~ (0x1 << 6);
  2612. aucStatus[2] &= ~ (0x1 << 2);
  2613. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2614. Hv_Vos_MSleep(15);
  2615. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2616. Hv_Vos_MSleep(15);
  2617. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2618. }
  2619. else
  2620. {
  2621. /* wps 0, cmp 0 , x x 1 1 1 srp: 1 srl: 0 */
  2622. aucStatus[0] |= 0x7 << 2;
  2623. aucStatus[0] |= 0x1 << 7;
  2624. aucStatus[1] &= ~ (0x1 << 0);
  2625. aucStatus[1] &= ~ (0x1 << 6);
  2626. aucStatus[2] &= ~ (0x1 << 2);
  2627. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2628. Hv_Vos_MSleep(15);
  2629. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2630. Hv_Vos_MSleep(15);
  2631. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2632. }
  2633. Hv_Vos_MSleep(15);
  2634. break;
  2635. }
  2636. default:
  2637. {
  2638. break;
  2639. }
  2640. }
  2641. }
  2642. static UINT32 Flash_ReadFlashID(VOID)
  2643. {
  2644. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  2645. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  2646. UCHAR8 aucIDCmd[4] = {0x9f};
  2647. UCHAR8 aucReadID[4] = {0x0};
  2648. HV_LOGV("Flash_ReadFlashID.\n");
  2649. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2650. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  2651. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2652. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  2653. Hv_Cal_Qspi_PollingRead(pstQspi, aucIDCmd, 4, aucReadID, 0, FLASH_TIMEOUT);
  2654. Hv_Cal_Qspi_SetRateMode(pstQspi, RateMode);
  2655. HV_LOGI("flash id: 0x%x 0x%x 0x%x.\n",aucReadID[1], aucReadID[2], aucReadID[3]);
  2656. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2657. return (aucReadID[1]<<16 | aucReadID[2]<<8 | aucReadID[3]);
  2658. }
  2659. VOID Hv_Drv_Flash_ProtectDisable(VOID)
  2660. {
  2661. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2662. Flash_WriteAddrProtect(g_stFlash.uiFlashID, 0, 0xAA);
  2663. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2664. return;
  2665. }
  2666. VOID Hv_Drv_Flash_Info(VOID)
  2667. {
  2668. UCHAR8 aucStatus[3] = {0x0};
  2669. Flash_ReadFlashID();
  2670. Hv_Vos_MSleep(5);
  2671. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2672. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2673. Flash_ReadStatusReg(0x15, &aucStatus[2], 1);
  2674. HV_LOGI("status: %x,%x,%x.\n", aucStatus[0],aucStatus[1], aucStatus[2]);
  2675. return;
  2676. }
  2677. static Status Flash_WriteProtectEnable(VOID)
  2678. {
  2679. #ifdef HV_PROJECT_CONFIG_FLASH_PROTECT
  2680. HV_LOGV("Flash_WriteProtectEnable.\n");
  2681. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2682. Flash_WriteAddrProtect(g_stFlash.uiFlashID, 0, HV_FALSE);
  2683. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2684. #endif
  2685. return HV_SUCCESS;
  2686. }
  2687. static Status Flash_WriteProtectDisable(UINT32 uiAddr)
  2688. {
  2689. #ifdef HV_PROJECT_CONFIG_FLASH_PROTECT
  2690. HV_LOGV("Flash_WriteProtectDisable.\n");
  2691. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2692. Flash_WriteAddrProtect(g_stFlash.uiFlashID, uiAddr, HV_TRUE);
  2693. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2694. #endif
  2695. return HV_SUCCESS;
  2696. }
  2697. static Status Flash_FourLineDisable(FlashSelf* pstFlash, FlashModel enFlashModel)
  2698. {
  2699. QspiSelf* pstQspi = Flash_GetQspi(pstFlash);
  2700. UCHAR8 switchCmd[4] = {0};
  2701. if (enFlashModel == FLASH_GD25)
  2702. {
  2703. switchCmd[0] = GD25_Flash_QuadDisable & 0xff;
  2704. switchCmd[1] = 0x00 & 0xff;
  2705. switchCmd[2] = 0x00 & 0xff;
  2706. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2707. Flash_WriteEnable(pstFlash);
  2708. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  2709. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  2710. }
  2711. else if (enFlashModel == FLASH_P25Q)
  2712. {
  2713. switchCmd[0] = P25Q_Flash_QuadDisable & 0xff;
  2714. switchCmd[1] = 0x00 & 0xff;
  2715. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2716. Flash_WriteEnable(pstFlash);
  2717. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  2718. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  2719. }
  2720. else if (enFlashModel == FLASH_MX25)
  2721. {
  2722. if ((Flash_GetTransType(pstFlash) == FLASH_MULTIIO_FAST_TYPE)
  2723. || (Flash_GetTransType(pstFlash) == FLASH_ADDR_4LINE))
  2724. {
  2725. UCHAR8 aucStateCmd[2] = {0x05,0x00};
  2726. UCHAR8 aucRdState[2] = {0xff,0xff};
  2727. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2728. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2729. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  2730. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  2731. if ((aucRdState[1] & 0x40) == 0x40)
  2732. {
  2733. switchCmd[0]=0x01;
  2734. switchCmd[1]=0x00;
  2735. Flash_WriteEnable(pstFlash);
  2736. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  2737. // Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  2738. }
  2739. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  2740. //HV_LOGI("MX25Q flash quad mode is disable.\n");
  2741. }
  2742. else if (Flash_GetTransType(pstFlash) == FLASH_INSTRUCT_ADDR_4LINE)
  2743. {
  2744. switchCmd[0] = MX25_Flash_QpiDisable & 0xff;
  2745. Flash_WriteEnable(pstFlash);
  2746. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 1, NULL, 0, FLASH_TIMEOUT);
  2747. //HV_LOGI("MX25Q flash qpi mode is disable.\n");
  2748. }
  2749. }
  2750. return HV_SUCCESS;
  2751. }
  2752. static void Flash_DualFuctionJudge(FlashModel enFlashModel)
  2753. {
  2754. if (enFlashModel == FLASH_W25Q)
  2755. {
  2756. HV_LOGI("W25Q can't support dual mode fast write,can support dual mode fast read.\n");
  2757. }
  2758. else if (enFlashModel == FLASH_GD25)
  2759. {
  2760. HV_LOGI("GD25 can't support dual mode fast write,can support dual mode fast read.\n");
  2761. }
  2762. else if (enFlashModel == FLASH_MX25)
  2763. {
  2764. HV_LOGI("MX25 can't support dual mode fast write,can support dual mode fast read.\n");
  2765. }
  2766. return;
  2767. }
  2768. /**********************************************flash db opration end*****************************/
  2769. /****************************** Flash Common API ************************************************/
  2770. static void FLASH_SetCpltCallBack(FlashSelf* pstFlash, void* callbackFunc)
  2771. {
  2772. QspiSelf* pstQspi = pstFlash->pstQspi;
  2773. pstFlash->InitParam.FlashCpltCallback = (Flash_CpltCallback)callbackFunc;
  2774. Hv_Cal_Qspi_SetCpltCallBack(pstQspi,Flash_CpltCallBack);
  2775. }
  2776. UCHAR8 Hv_Drv_Flash_GetFlashStatus(FlashSelf* pstFlash)
  2777. {
  2778. QspiSelf* pstQspi = pstFlash->pstQspi;
  2779. UCHAR8 ucRegVal = 0;
  2780. UCHAR8 ucReadCmd = 0x05;
  2781. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2782. {
  2783. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2784. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2785. Hv_Cal_Qspi_PollingRead(pstQspi, &ucReadCmd, 1, &ucRegVal, 1, FLASH_TIMEOUT);
  2786. }
  2787. else if (pstFlash->InitParam.RateMode == FLASH_DUAL
  2788. ||pstFlash->InitParam.RateMode == FLASH_QUAD)
  2789. {
  2790. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  2791. {
  2792. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2793. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  2794. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  2795. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  2796. Hv_Cal_Qspi_SetReadNumber(pstQspi, 1);
  2797. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, &ucReadCmd, 1, &ucRegVal, 1, FLASH_TIMEOUT);
  2798. }
  2799. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  2800. {
  2801. QspiRateMode enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  2802. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2803. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2804. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2805. Hv_Cal_Qspi_PollingRead(pstQspi, &ucReadCmd, 1, &ucRegVal, 1, FLASH_TIMEOUT);
  2806. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  2807. }
  2808. }
  2809. return ucRegVal;
  2810. }
  2811. UCHAR8 Hv_Drv_Flash_WriteStatus(FlashSelf* pstFlash, UCHAR8 flashStatus)
  2812. {
  2813. QspiSelf* pstQspi = pstFlash->pstQspi;
  2814. UCHAR8 ucSendCmd = 0x01;
  2815. UCHAR8 ucSendData = flashStatus;
  2816. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2817. {
  2818. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  2819. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2820. Hv_Cal_Qspi_PollingWrite(pstQspi, &ucSendCmd, 1, &ucSendData, 1, FLASH_TIMEOUT);
  2821. }
  2822. else if (pstFlash->InitParam.RateMode == FLASH_DUAL ||pstFlash->InitParam.RateMode == FLASH_QUAD)
  2823. {
  2824. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2825. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  2826. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  2827. {
  2828. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  2829. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  2830. }
  2831. else
  2832. {
  2833. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,
  2834. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  2835. }
  2836. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &ucSendCmd, 1, &ucSendData, 1, FLASH_TIMEOUT);
  2837. }
  2838. return ucSendData;
  2839. }
  2840. static FlashSelf* Flash_InitParam(FlashInitParam* InitParam)
  2841. {
  2842. QspiSelf* pstQspi = NULL;
  2843. QspiInitParam qspiInitParam;
  2844. UINT32 uiFlashID = 0;
  2845. HV_MEMSET(&qspiInitParam,0, sizeof(qspiInitParam));
  2846. if (InitParam->RateMode == FLASH_QPI)
  2847. {
  2848. InitParam->RateMode = FLASH_QUAD;
  2849. InitParam->TransType = FLASH_INSTRUCT_ADDR_4LINE;
  2850. }
  2851. else if (InitParam->RateMode == FLASH_4XIO)
  2852. {
  2853. InitParam->RateMode = FLASH_QUAD;
  2854. InitParam->TransType = FLASH_ADDR_4LINE;
  2855. }
  2856. else
  2857. {
  2858. InitParam->TransType = FLASH_MULTIIO_FAST_TYPE;
  2859. }
  2860. qspiInitParam.RateMode = (QspiRateMode)InitParam->RateMode;
  2861. qspiInitParam.Direction = QSPI_DIRECTION_TXRX;
  2862. qspiInitParam.CLKPolarity = QSPI_POLARITY_LOW;
  2863. qspiInitParam.CLKPhase = QSPI_PHASE_EDGE1;
  2864. qspiInitParam.DataSize = (QspiBitWidth)(InitParam->DataSize - 1);
  2865. qspiInitParam.CsSel = (QspiCsSel)(InitParam->CsSel);
  2866. //Flash_SetCommonBaudRate(&qspiInitParam,InitParam);
  2867. qspiInitParam.BaudRatePrescaler = QSPI_DIVRATIO_8;
  2868. pstQspi = Hv_Cal_Qspi_Init(&qspiInitParam);
  2869. if(NULL != pstQspi)
  2870. {
  2871. g_stFlash.pstQspi = pstQspi;
  2872. }
  2873. else
  2874. {
  2875. return NULL;
  2876. }
  2877. Hv_Cal_Qspi_SetFlashPoint(pstQspi,(void*)&g_stFlash);
  2878. HV_MEMCPY(&(g_stFlash.InitParam), InitParam, sizeof(*InitParam));
  2879. if (InitParam->FlashCallback != NULL)
  2880. {
  2881. FLASH_SetCpltCallBack(&g_stFlash,InitParam->FlashCallback);
  2882. }
  2883. Hv_Drv_FlashDB_GetAttribute(&(g_stFlash.flashAttr),InitParam->FlashModel);
  2884. if (InitParam->RateMode == FLASH_DUAL)
  2885. {
  2886. Flash_DualFuctionJudge(InitParam->FlashModel);
  2887. }
  2888. uiFlashID = Flash_ReadFlashID();
  2889. g_stFlash.uiFlashID = uiFlashID;
  2890. if (InitParam->RateMode == FLASH_QUAD)
  2891. {
  2892. Flash_FourLineEnable(&g_stFlash,InitParam->FlashModel);
  2893. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi,qspiInitParam.DataSize);
  2894. }
  2895. #ifdef HV_PROJECT_CONFIG_FLASH_PROTECT
  2896. else
  2897. {
  2898. Hv_Cal_Qspi_WP_Init();
  2899. Flash_WriteProtectEnable();
  2900. }
  2901. #endif
  2902. return &g_stFlash;
  2903. }
  2904. static Status Flash_ReInit(FlashSelf* pstFlash, FlashWorkModeSel WorkModeSel,
  2905. FlashRateMode RateMode,FlashDataWidth DataSize)
  2906. {
  2907. QspiSelf* pstQspi = pstFlash->pstQspi;
  2908. QspiInitParam qspiInitParam;
  2909. HV_MEMSET(&qspiInitParam,0, sizeof(qspiInitParam));
  2910. pstFlash->InitParam.WorkModeSel = WorkModeSel;
  2911. pstFlash->InitParam.RateMode = RateMode;
  2912. pstFlash->InitParam.DataSize = DataSize;
  2913. if (pstFlash->InitParam.RateMode == FLASH_QPI)
  2914. {
  2915. pstFlash->InitParam.RateMode = FLASH_QUAD;
  2916. pstFlash->InitParam.TransType = FLASH_INSTRUCT_ADDR_4LINE;
  2917. }
  2918. else if (pstFlash->InitParam.RateMode == FLASH_4XIO)
  2919. {
  2920. pstFlash->InitParam.RateMode = FLASH_QUAD;
  2921. pstFlash->InitParam.TransType = FLASH_ADDR_4LINE;
  2922. }
  2923. else
  2924. {
  2925. pstFlash->InitParam.TransType = FLASH_MULTIIO_FAST_TYPE;
  2926. }
  2927. qspiInitParam.RateMode = (QspiRateMode)RateMode;
  2928. qspiInitParam.DataSize = (QspiBitWidth)(DataSize - 1);
  2929. Flash_SetCommonBaudRate(&qspiInitParam,&pstFlash->InitParam);
  2930. Hv_Cal_Qspi_SetRateMode(pstQspi,qspiInitParam.RateMode);
  2931. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi,qspiInitParam.DataSize);
  2932. Hv_Cal_Qspi_SetBaudRate(pstQspi,qspiInitParam.BaudRatePrescaler);
  2933. return HV_SUCCESS;
  2934. }
  2935. static Status _Flash_Cleanup(FlashSelf* pstFlash)
  2936. {
  2937. QspiSelf* pstQspi = pstFlash->pstQspi;
  2938. if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2939. {
  2940. Flash_FourLineDisable(pstFlash,pstFlash->InitParam.FlashModel);
  2941. }
  2942. Hv_Cal_Qspi_Cleanup(pstQspi);
  2943. return HV_SUCCESS;
  2944. }
  2945. UINT32 Hv_Drv_Flash_GetFlashID(FlashSelf* pstFlash)
  2946. {
  2947. UINT32 uiFlashID = 0;
  2948. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2949. {
  2950. uiFlashID = Flash_ReadID_Standard(pstFlash);
  2951. }
  2952. else if ((pstFlash->InitParam.RateMode == FLASH_DUAL)
  2953. || (pstFlash->InitParam.RateMode == FLASH_QUAD))
  2954. {
  2955. uiFlashID = Flash_ReadID_MutiIO(pstFlash);
  2956. }
  2957. return uiFlashID;
  2958. }
  2959. static Status _Flash_Erase(FlashSelf* pstFlash, FlashEraseType enEraseType,UINT32 uiEraseAddr)
  2960. {
  2961. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2962. {
  2963. Flash_EraseStandard(pstFlash, enEraseType, uiEraseAddr);
  2964. }
  2965. else if ((pstFlash->InitParam.RateMode == FLASH_DUAL)
  2966. || (pstFlash->InitParam.RateMode == FLASH_QUAD))
  2967. {
  2968. Flash_EraseMultiIo(pstFlash, enEraseType, uiEraseAddr);
  2969. }
  2970. return HV_SUCCESS;
  2971. }
  2972. static Status _Flash_Write(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  2973. {
  2974. if (pstFlash->InitParam.WorkModeSel == FLASH_USE_POLLING)
  2975. {
  2976. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2977. {
  2978. Flash_SendStandard(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2979. }
  2980. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2981. {
  2982. Flash_SendDual(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2983. }
  2984. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2985. {
  2986. Flash_SendQuad(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2987. }
  2988. }
  2989. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_INT)
  2990. {
  2991. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2992. {
  2993. Flash_SendStandardInt(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2994. }
  2995. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2996. {
  2997. Flash_SendDualInt(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2998. }
  2999. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  3000. {
  3001. Flash_SendQuadInt(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  3002. }
  3003. }
  3004. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_DMA)
  3005. {
  3006. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  3007. {
  3008. Flash_SendStandardDma(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  3009. }
  3010. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  3011. {
  3012. Flash_SendDualDma(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  3013. }
  3014. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  3015. {
  3016. Flash_SendQuadDma(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  3017. }
  3018. }
  3019. return HV_SUCCESS;
  3020. }
  3021. static Status _Flash_Read(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  3022. {
  3023. if (pstFlash->InitParam.WorkModeSel == FLASH_USE_POLLING)
  3024. {
  3025. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  3026. {
  3027. Flash_RecvStandard(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3028. }
  3029. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  3030. {
  3031. Flash_RecvDual(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3032. }
  3033. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  3034. {
  3035. Flash_RecvQuad(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3036. }
  3037. }
  3038. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_INT)
  3039. {
  3040. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  3041. {
  3042. Flash_RecvStandardInt(pstFlash, uiRdAddr, pucRxData,uiRxSize);
  3043. }
  3044. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  3045. {
  3046. Flash_RecvDualInt(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3047. }
  3048. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  3049. {
  3050. Flash_RecvQuadInt(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3051. }
  3052. }
  3053. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_DMA)
  3054. {
  3055. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  3056. {
  3057. Flash_RecvStandardDma(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3058. }
  3059. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  3060. {
  3061. Flash_RecvDualDma(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3062. }
  3063. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  3064. {
  3065. Flash_RecvQuadDma(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  3066. }
  3067. }
  3068. return HV_SUCCESS;
  3069. }
  3070. BOOL Hv_Drv_Flash_TransferIsComplete(FlashSelf *pstFlash)
  3071. {
  3072. QspiSelf* pstQspi = pstFlash->pstQspi;
  3073. return Hv_Cal_Qspi_TransferIsComplete(pstQspi);
  3074. }
  3075. static void Flash_Swap32(UCHAR8* pucSrc, UINT32 uiLength)
  3076. {
  3077. UINT32 uiLoop = 0;
  3078. if ((uiLength % 4) != 0)
  3079. {
  3080. return;
  3081. }
  3082. for (uiLoop = 0; uiLoop < uiLength / 4; uiLoop++)
  3083. {
  3084. *((UINT32 *)(pucSrc + uiLoop * 4)) = HV_SWAP32(*((UINT32 *)(pucSrc + uiLoop * 4)));
  3085. }
  3086. return;
  3087. }
  3088. static void Flash_TxDmaInit(void)
  3089. {
  3090. QspiSelf *pstQspi = Flash_GetQspi(g_pFlash);
  3091. DmaSelf* pstTxDma = NULL;
  3092. DmaInitParam TxInitParam;
  3093. Hv_Vos_Memset(&TxInitParam, 0, sizeof(DmaInitParam));
  3094. TxInitParam.PortChannelNum = DMA_PORT0_CHANNEL0;
  3095. TxInitParam.Application = DMA_APPLI_QSPI0_TX;
  3096. TxInitParam.transType = DMA_TYPE_SINGLE;
  3097. pstTxDma = Hv_Cal_Dma_ChannelInit(&TxInitParam);
  3098. Hv_Cal_Qspi_SetDmaTx(pstQspi, pstTxDma);
  3099. return;
  3100. }
  3101. static void Flash_RxDmaInit(void)
  3102. {
  3103. QspiSelf *pstQspi = Flash_GetQspi(g_pFlash);
  3104. DmaSelf* pstRxDma = NULL;
  3105. DmaInitParam RxInitParam;
  3106. Hv_Vos_Memset(&RxInitParam, 0, sizeof(DmaInitParam));
  3107. RxInitParam.PortChannelNum = DMA_PORT0_CHANNEL1;
  3108. RxInitParam.Application = DMA_APPLI_QSPI0_RX;
  3109. RxInitParam.transType = DMA_TYPE_SINGLE;
  3110. pstRxDma = Hv_Cal_Dma_ChannelInit(&RxInitParam);
  3111. Hv_Cal_Qspi_SetDmaRx(pstQspi,pstRxDma);
  3112. return;
  3113. }
  3114. static void Flash_Program(UINT32 uiWriteAddr, UCHAR8* pucWriteBuf, UINT32 uiLength)
  3115. {
  3116. FlashTxMem stFlashMem;
  3117. Hv_Vos_Memset(&stFlashMem, 0, sizeof(FlashTxMem));
  3118. if (((uiLength % 4) != 0) || (uiLength > PAGE_WRITE))
  3119. {
  3120. return;
  3121. }
  3122. if (g_ucDmaUseFlag == HV_TRUE)
  3123. {
  3124. Hv_Vos_Memcpy((UCHAR8 *)stFlashMem.txData, (UCHAR8*)pucWriteBuf, uiLength);
  3125. if (Flash_GetDataSize(g_pFlash) == FLASH_DATAWIDTH_32)
  3126. {
  3127. Flash_Swap32((UCHAR8 *)stFlashMem.txData,uiLength);
  3128. }
  3129. _Flash_Write(g_pFlash, uiWriteAddr, (UCHAR8 *)stFlashMem.txData, uiLength);
  3130. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash) == HV_FALSE);
  3131. }
  3132. else if (g_ucIntUseFlag == HV_TRUE)
  3133. {
  3134. _Flash_Write(g_pFlash, uiWriteAddr, pucWriteBuf, uiLength);
  3135. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash) == HV_FALSE);
  3136. }
  3137. else
  3138. {
  3139. _Flash_Write(g_pFlash, uiWriteAddr, pucWriteBuf, uiLength);
  3140. }
  3141. return;
  3142. }
  3143. static void Flash_Read(UINT32 uiReadAddr, UCHAR8 *pucReadBuf, UINT32 uiLength)
  3144. {
  3145. if (((uiLength % 4) != 0) ||(uiLength > PAGE_READ))
  3146. {
  3147. return;
  3148. }
  3149. if (g_ucDmaUseFlag == HV_TRUE)
  3150. {
  3151. _Flash_Read(g_pFlash, uiReadAddr, g_ucReadBuf, uiLength);
  3152. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash)== HV_FALSE);
  3153. Hv_Vos_MSleep(1);
  3154. if (Flash_GetRateMode(g_pFlash) == FLASH_STANDARD)
  3155. {
  3156. Hv_Vos_Memcpy(pucReadBuf, &g_ucReadBuf[4], uiLength);
  3157. }
  3158. else
  3159. {
  3160. Hv_Vos_Memcpy(pucReadBuf, g_ucReadBuf, uiLength);
  3161. }
  3162. if (Flash_GetDataSize(g_pFlash) == FLASH_DATAWIDTH_32)
  3163. {
  3164. Flash_Swap32(pucReadBuf,uiLength);
  3165. }
  3166. }
  3167. else if (g_ucIntUseFlag == HV_TRUE)
  3168. {
  3169. _Flash_Read(g_pFlash, uiReadAddr, pucReadBuf, uiLength);
  3170. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash)== HV_FALSE);
  3171. }
  3172. else
  3173. {
  3174. _Flash_Read(g_pFlash,uiReadAddr, pucReadBuf, uiLength);
  3175. }
  3176. return;
  3177. }
  3178. static void Flash_OnlyErase(UINT32 uiEraseAddr, UINT32 uiLength)
  3179. {
  3180. UINT32 uiLoop = 0;
  3181. for (uiLoop = 0;
  3182. uiLoop < (uiLength % ERASE_TYPE_SIZE == 0 ? (uiLength / ERASE_TYPE_SIZE) : (uiLength / ERASE_TYPE_SIZE + 1));
  3183. uiLoop++)
  3184. {
  3185. _Flash_Erase(g_pFlash, ERASE_TYPE, uiEraseAddr + uiLoop * ERASE_TYPE_SIZE);
  3186. }
  3187. }
  3188. static void Flash_OnlyEraseMultiSector(UINT32 uiEraseAddr)
  3189. {
  3190. _Flash_Erase(g_pFlash, FLASH_ERASE_MULTI_SECTOR, uiEraseAddr);
  3191. }
  3192. static Status Flash_Check(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength)
  3193. {
  3194. UINT32 uiLoop = 0;
  3195. UCHAR8 ucReadCrc = 0;
  3196. UCHAR8 ucWriteCrc = 0;
  3197. Flash_OnlyRead(uiWriteAddr, g_ucReadBuf, uiLength);
  3198. for (uiLoop = 0; uiLoop < uiLength; uiLoop++)
  3199. {
  3200. if (*pucWriteBuf != g_ucReadBuf[uiLoop])
  3201. {
  3202. HV_LOGI("[%2x]:need %x, act %x", uiLoop, *pucWriteBuf, g_ucReadBuf[uiLoop]);
  3203. return HV_FAILURE;
  3204. }
  3205. pucWriteBuf++;
  3206. }
  3207. return HV_SUCCESS;
  3208. }
  3209. static Status Flash_OnlyWrite(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength)
  3210. {
  3211. UINT32 uiLoop = 0;
  3212. UINT32 uiRemain = 0;
  3213. UINT32 uiTempLen = 0;
  3214. UINT32 uiTempAdd = 0;
  3215. UINT32 uiRetry = 3;
  3216. Status uiRet = HV_SUCCESS;
  3217. UCHAR8* pucTmpUseWriteBuf = g_ucWriteBuf;
  3218. HV_MEMSET(pucTmpUseWriteBuf, 0xff, PAGE_WRITE);
  3219. for (uiLoop=0; uiLoop< uiLength / PAGE_WRITE; uiLoop++)
  3220. {
  3221. Hv_Vos_Memcpy(pucTmpUseWriteBuf, (UCHAR8 *)((UINT32)pucWriteBuf + uiLoop * PAGE_WRITE), PAGE_WRITE);
  3222. Hv_Vos_InvalidAllDCache();
  3223. uiTempAdd = uiWriteAddr + uiLoop * PAGE_WRITE;
  3224. uiRetry = 1;
  3225. do
  3226. {
  3227. Flash_Program(uiTempAdd, pucTmpUseWriteBuf, PAGE_WRITE);
  3228. if (HV_SUCCESS == Flash_Check(uiTempAdd, pucTmpUseWriteBuf, PAGE_WRITE))
  3229. {
  3230. break;
  3231. }
  3232. HV_LOGV("flash write retry...\n");
  3233. uiRetry--;
  3234. } while (uiRetry);
  3235. if (0 == uiRetry)
  3236. {
  3237. uiRet = HV_FAILURE;
  3238. HV_LOGE("flash write fail address %x\n", uiTempAdd);
  3239. }
  3240. }
  3241. uiRemain = uiLength % PAGE_WRITE;
  3242. if ((uiRemain > 0) && (uiRet == HV_SUCCESS))
  3243. {
  3244. uiTempLen = (uiRemain % 4 == 0) ? (uiRemain / 4) : (uiRemain / 4 + 1);
  3245. Hv_Vos_Memcpy(pucTmpUseWriteBuf,
  3246. (UCHAR8 *)((UINT32)pucWriteBuf + (uiLength / PAGE_WRITE) * PAGE_WRITE),
  3247. uiRemain);
  3248. Hv_Vos_InvalidAllDCache();
  3249. uiRetry = 1;
  3250. uiTempAdd = uiWriteAddr + (uiLength / PAGE_WRITE) * PAGE_WRITE;
  3251. do
  3252. {
  3253. Flash_Program(uiTempAdd, pucTmpUseWriteBuf, uiTempLen * 4);
  3254. if (HV_SUCCESS == Flash_Check(uiTempAdd, pucTmpUseWriteBuf, uiTempLen * 4))
  3255. {
  3256. break;
  3257. }
  3258. HV_LOGV("flash write retry...\n");
  3259. } while ((uiRetry--) > 0);
  3260. if (0 == uiRetry)
  3261. {
  3262. uiRet = HV_FAILURE;
  3263. HV_LOGE("flash write fail address %x\n", uiTempAdd);
  3264. }
  3265. }
  3266. return uiRet;
  3267. }
  3268. static void Flash_OnlyRead(UINT32 uiReadAddr, UCHAR8* pucReadBuf, UINT32 uiLength)
  3269. {
  3270. UINT32 uiLoop = 0;
  3271. UINT32 uiRemain = 0;
  3272. UINT32 uiTempLen = 0;
  3273. UINT32 readCount = 0;
  3274. HV_MEMSET(g_ucReadBuf, 0xff, PAGE_READ);
  3275. Hv_Vos_InvalidAllDCache();
  3276. for (uiLoop=0; uiLoop < uiLength / PAGE_READ; uiLoop++)
  3277. {
  3278. Flash_Read(uiReadAddr + uiLoop * PAGE_READ,
  3279. (UCHAR8*)((UINT32)pucReadBuf + uiLoop * PAGE_READ), PAGE_READ);
  3280. readCount = readCount + PAGE_READ;
  3281. }
  3282. uiRemain = uiLength % PAGE_READ;
  3283. if (uiRemain > 0)
  3284. {
  3285. if (g_ucDmaUseFlag == HV_TRUE)
  3286. {
  3287. uiTempLen = (uiRemain % 32 == 0)?(uiRemain):(uiRemain / 32 + 1) * 32;
  3288. }
  3289. else
  3290. {
  3291. uiTempLen = (uiRemain % 4 == 0) ? (uiRemain) : (uiRemain / 4 + 1) * 4;
  3292. }
  3293. Flash_Read(uiReadAddr + readCount, (UCHAR8*)g_ucReadBuf, uiTempLen);
  3294. Hv_Vos_InvalidAllDCache();
  3295. Hv_Vos_Memcpy((UCHAR8*)((UINT32)pucReadBuf + readCount), g_ucReadBuf, uiRemain);
  3296. Hv_Vos_InvalidAllDCache();
  3297. }
  3298. return;
  3299. }
  3300. static BOOL Flash_EraseWrite(UINT32 uiWriteAddr, UCHAR8* pucWriteBuf, UINT32 uiLength)
  3301. {
  3302. UINT32 uiTempVal = 0;
  3303. UINT32 uiFirstWriteSize = 0;
  3304. UINT32 uiTempLen = uiLength;
  3305. UCHAR8* pucWbuf = (UCHAR8*)pucWriteBuf;
  3306. UCHAR8* pucTmpUseBuf = g_ucSectorBuf;
  3307. UINT32 uiWaddr = uiWriteAddr;
  3308. UINT32 uiCount = 0;
  3309. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3310. uiTempVal = uiWaddr & 0xfff;
  3311. if ((uiTempVal) != 0)
  3312. {
  3313. if ((uiTempVal +uiTempLen) < SECTOR_SIZE)
  3314. {
  3315. HV_MEMSET(pucTmpUseBuf, 0xff, SECTOR_SIZE);
  3316. Hv_Vos_InvalidAllDCache();
  3317. Flash_OnlyRead(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3318. Hv_Vos_Memcpy(&pucTmpUseBuf[uiTempVal],pucWbuf, uiTempLen);
  3319. Hv_Vos_InvalidAllDCache();
  3320. Flash_OnlyErase(uiWaddr & (~0xfff), SECTOR_SIZE);
  3321. Flash_OnlyWrite(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3322. uiTempLen = 0;
  3323. }
  3324. else
  3325. {
  3326. uiFirstWriteSize = SECTOR_SIZE - uiTempVal;
  3327. Flash_OnlyRead(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3328. Hv_Vos_Memcpy(&pucTmpUseBuf[uiTempVal],pucWbuf, uiFirstWriteSize);
  3329. Hv_Vos_InvalidAllDCache();
  3330. Flash_OnlyErase(uiWaddr & (~0xfff), SECTOR_SIZE);
  3331. Flash_OnlyWrite(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3332. uiTempLen = uiTempLen - uiFirstWriteSize;
  3333. uiWaddr = (uiWaddr & (~0xfff)) + SECTOR_SIZE;
  3334. pucWbuf = pucWbuf + uiFirstWriteSize;
  3335. }
  3336. }
  3337. while ((uiTempLen > SECTOR_SIZE) || (uiTempLen == SECTOR_SIZE))
  3338. {
  3339. uiTempLen = uiTempLen- SECTOR_SIZE;
  3340. uiCount++;
  3341. }
  3342. while (uiCount-- > 0)
  3343. {
  3344. Flash_OnlyErase(uiWaddr, SECTOR_SIZE * uiCount);
  3345. Flash_OnlyWrite(uiWaddr, pucWbuf, SECTOR_SIZE * uiCount);
  3346. uiWaddr = uiWaddr + SECTOR_SIZE * uiCount;
  3347. pucWbuf = pucWbuf + SECTOR_SIZE * uiCount;
  3348. }
  3349. if (uiTempLen > 0)
  3350. {
  3351. Flash_OnlyRead(uiWaddr, pucTmpUseBuf, SECTOR_SIZE);
  3352. Hv_Vos_Memcpy(pucTmpUseBuf, pucWbuf, uiTempLen);
  3353. Hv_Vos_InvalidAllDCache();
  3354. Flash_OnlyErase(uiWaddr, SECTOR_SIZE);
  3355. Flash_OnlyWrite(uiWaddr, pucTmpUseBuf, SECTOR_SIZE); //tmp fix
  3356. }
  3357. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3358. return HV_SUCCESS;
  3359. }
  3360. static void Flash_Init(FlashRateMode RateMode, FlashWorkModeSel workMode)
  3361. {
  3362. FlashInitParam InitParam;
  3363. InitParam.WorkModeSel = workMode;
  3364. InitParam.FlashModel = FLASH_W25Q;
  3365. InitParam.RateMode = RateMode;
  3366. InitParam.FlashCallback = NULL;
  3367. InitParam.CsSel = FLASH_CS_BY_GPIO;
  3368. if (InitParam.FlashModel == FLASH_MX25)
  3369. {
  3370. InitParam.AddrWidth = FLASH_ADDRESS_WIDTH_32;
  3371. if (InitParam.RateMode == FLASH_STANDARD)
  3372. {
  3373. InitParam.DataSize = FLASH_DATAWIDTH_8;
  3374. }
  3375. else if (InitParam.RateMode == FLASH_4XIO)
  3376. {
  3377. InitParam.DataSize = FLASH_DATAWIDTH_32;
  3378. }
  3379. else
  3380. {
  3381. HV_LOGI("MX25:Init config erro.\n");
  3382. HV_ASSERT(0);
  3383. }
  3384. }
  3385. else if (InitParam.FlashModel == FLASH_GD25)
  3386. {
  3387. InitParam.AddrWidth = FLASH_ADDRESS_WIDTH_24;
  3388. InitParam.DataSize = FLASH_DATAWIDTH_32;
  3389. if ((InitParam.RateMode != FLASH_STANDARD)
  3390. && (InitParam.RateMode != FLASH_DUAL)
  3391. && (InitParam.RateMode != FLASH_QUAD))
  3392. {
  3393. HV_LOGI("GD25:Init config erro.\n");
  3394. HV_ASSERT(0);
  3395. }
  3396. }
  3397. else
  3398. {
  3399. InitParam.FlashModel = FLASH_MT25;
  3400. InitParam.AddrWidth = FLASH_ADDRESS_WIDTH_24;
  3401. InitParam.DataSize = FLASH_DATAWIDTH_32;
  3402. if ((InitParam.RateMode != FLASH_STANDARD)
  3403. && (InitParam.RateMode != FLASH_DUAL)
  3404. && (InitParam.RateMode != FLASH_QUAD))
  3405. {
  3406. HV_LOGI("MT25:Init config erro.\n");
  3407. HV_ASSERT(0);
  3408. }
  3409. }
  3410. g_pFlash = Flash_InitParam(&InitParam);
  3411. if (InitParam.WorkModeSel == FLASH_USE_DMA)
  3412. {
  3413. Flash_TxDmaInit();
  3414. Flash_RxDmaInit();
  3415. g_ucDmaUseFlag = HV_TRUE;
  3416. g_ucIntUseFlag = HV_FALSE;
  3417. }
  3418. else if (InitParam.WorkModeSel == FLASH_USE_INT)
  3419. {
  3420. g_ucDmaUseFlag = HV_FALSE;
  3421. g_ucIntUseFlag = HV_TRUE;
  3422. }
  3423. else if (InitParam.WorkModeSel == FLASH_USE_POLLING)
  3424. {
  3425. g_ucDmaUseFlag = HV_FALSE;
  3426. g_ucIntUseFlag = HV_FALSE;
  3427. }
  3428. return;
  3429. }
  3430. static void Flash_CleanUp(void)
  3431. {
  3432. if (g_pFlash != NULL)
  3433. {
  3434. _Flash_Cleanup(g_pFlash);
  3435. g_pFlash = NULL;
  3436. }
  3437. }
  3438. /**
  3439. * @brief write config data to flash.
  3440. * @param uiAddress write offset at flash
  3441. * @param pucData address write data to
  3442. * @param uiDataSize write data size
  3443. * @retval Status
  3444. */
  3445. Status Hv_Drv_Flash_WriteMonitorData(UINT32 uiAddress, UCHAR8 *pucData, UINT32 uiDataSize)
  3446. {
  3447. Status sRet = HV_FAILURE;
  3448. HV_LOGV("_Flash_Write uiAddress=%x,pucData=%x, uiDataSize= %d", uiAddress, pucData, uiDataSize);
  3449. Flash_WriteProtectDisable(uiAddress);
  3450. if (uiAddress >= HV_FLASH_CONFIG_MONITOR_DATA_PART_START)
  3451. {
  3452. sRet = Flash_EraseWrite(uiAddress, pucData, uiDataSize);
  3453. }
  3454. Flash_WriteProtectEnable();
  3455. return sRet;
  3456. }
  3457. /**
  3458. * @brief read data from flash.
  3459. * @param uiAddress read offset at flash
  3460. * @param pucData address for read data
  3461. * @param uiDataSize size to read data
  3462. * @retval Status
  3463. */
  3464. Status Hv_Drv_Flash_ReadMonitorData(UINT32 uiAddress, UCHAR8 *pucData, UINT32 uiDataSize)
  3465. {
  3466. HV_LOGV("_Flash_Read uiAddress=%x,pucData=0x%x, uiDataSize=%d", uiAddress, pucData, uiDataSize);
  3467. if (uiAddress >= HV_FLASH_CONFIG_LOGO_PART_START)
  3468. {
  3469. Flash_OnlyRead(uiAddress, pucData, uiDataSize);
  3470. return HV_SUCCESS;
  3471. }
  3472. return HV_FAILURE;
  3473. }
  3474. /**
  3475. * @brief read data from flash in xip mode.
  3476. * @param uiAddress read offset at flash
  3477. * @param pucData address for read data
  3478. * @param uiDataSize size to read data
  3479. * @retval Status
  3480. */
  3481. Status Hv_Drv_Flash_ReadXIP(UINT32 uiAddress, UCHAR8 *pucData, UINT32 uiDataSize)
  3482. {
  3483. UINT32 iLoop = 0;
  3484. HV_LOGV("Hv_Drv_Flash_ReadXIP uiAddress=%x,pucData=0x%x, uiDataSize=%d", uiAddress, pucData, uiDataSize);
  3485. {
  3486. for (iLoop = 0; iLoop < uiDataSize; iLoop++)
  3487. {
  3488. *pucData = *((UCHAR8 *)(uiAddress + HV_FLASH_CONFIG_START_XIP + iLoop));
  3489. pucData++;
  3490. }
  3491. }
  3492. return HV_SUCCESS;
  3493. }
  3494. /**
  3495. * @brief int flash interface.
  3496. */
  3497. void Hv_Drv_Flash_SetQspiMode(FlashRateMode RateMode, FlashWorkModeSel workMode)
  3498. {
  3499. g_pstFlashSeamphone = Hv_Vos_InitSemaphore(1, 1);
  3500. Flash_CleanUp();
  3501. Flash_Init(RateMode, workMode);
  3502. }
  3503. /**
  3504. * @brief deint flash interface.
  3505. */
  3506. void Hv_Drv_Flash_SetXipMode(void)
  3507. {
  3508. Flash_CleanUp();
  3509. return;
  3510. }
  3511. /**
  3512. * @brief config logo data and pq etc data partition flag
  3513. */
  3514. void Hv_Drv_Flash_ConfigPartFlag(void)
  3515. {
  3516. #ifdef SW_DUMMY_DEBUG
  3517. /* add flash partition config */
  3518. HV_WT32(SW_DUMMY_LOGO, HV_FLASH_CONFIG_LOGO_PART_START);
  3519. HV_WT32(SW_DUMMY_CONFIG_DATA, HV_FLASH_CONFIG_MONITOR_DATA_PART_START);
  3520. HV_WT32(SW_DUMMY_PQ_DATA, HV_FLASH_CONFIG_PQ_DATA_PART_START);
  3521. #endif
  3522. return;
  3523. }
  3524. /**
  3525. * @brief erase flash.
  3526. * @param[in] uiWriteAddr Address of flash to do erase.
  3527. * @param[in] uiLength Date length to be written.
  3528. * @return None
  3529. */
  3530. void Hv_Drv_Flash_OnlyErase(UINT32 uiReadAddr, UINT32 uiLength)
  3531. {
  3532. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3533. Flash_WriteProtectDisable(uiReadAddr);
  3534. Flash_OnlyErase(uiReadAddr, uiLength);
  3535. Flash_WriteProtectEnable();
  3536. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3537. return;
  3538. }
  3539. /**
  3540. * @brief Erase flash by a 64K Bytes(Multi Sector) length.
  3541. Warning: Always erase 64K bytes, please be sure to keep your data safe.
  3542. * @param[in] uiAddr Address of flash to do erase.
  3543. * @return None
  3544. */
  3545. void Hv_Drv_Flash_OnlyEraseMultiSector(UINT32 uiAddr)
  3546. {
  3547. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3548. Flash_WriteProtectDisable(uiAddr);
  3549. Flash_OnlyEraseMultiSector(uiAddr);
  3550. Flash_WriteProtectEnable();
  3551. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3552. return;
  3553. }
  3554. /**
  3555. * @brief Write flash.
  3556. * @param[in] uiWriteAddr Address of flash to do write.
  3557. * @param[in] pucWriteBuf Date buffer to be written.
  3558. * @param[in] uiLength Date length to be written.
  3559. * @return None
  3560. */
  3561. Status Hv_Drv_Flash_OnlyWrite(UINT32 uiWriteAddr, UCHAR8* pucWriteBuf, UINT32 uiLength)
  3562. {
  3563. UINT32 uiPreIdx = 0;
  3564. UINT32 uiPreDat = 0;
  3565. Status uiRet = HV_SUCCESS;
  3566. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3567. Flash_WriteProtectDisable(uiWriteAddr);
  3568. uiPreIdx = uiWriteAddr % PAGE_WRITE;
  3569. HV_LOGV("Hv_Drv_Flash_OnlyWrite uiWriteAddr %x uiPreIdx %x, length %d\n", uiWriteAddr, uiPreIdx,uiLength);
  3570. if (uiPreIdx)
  3571. {
  3572. uiPreDat = PAGE_WRITE - uiPreIdx;
  3573. if (uiLength < uiPreDat)
  3574. {
  3575. uiPreDat = uiLength;
  3576. }
  3577. HV_MEMSET(g_ucReadBuf, 0xff, PAGE_READ);
  3578. HV_MEMSET(g_ucWriteBuf, 0xff, PAGE_READ);
  3579. Hv_Vos_InvalidAllDCache();
  3580. uiWriteAddr &= ~0xff;
  3581. Flash_OnlyRead(uiWriteAddr, g_ucReadBuf, uiPreIdx);
  3582. Hv_Vos_Memcpy(&g_ucReadBuf[uiPreIdx], pucWriteBuf, uiPreDat);
  3583. uiRet = Flash_OnlyWrite(uiWriteAddr, g_ucReadBuf, PAGE_WRITE);
  3584. uiLength = uiLength - uiPreDat;
  3585. uiWriteAddr += PAGE_WRITE;
  3586. pucWriteBuf += uiPreDat;
  3587. }
  3588. if ((uiLength > 0) && (uiRet == HV_SUCCESS))
  3589. {
  3590. uiRet = Flash_OnlyWrite(uiWriteAddr, pucWriteBuf, uiLength);
  3591. }
  3592. Flash_WriteProtectEnable();
  3593. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3594. return uiRet;
  3595. }
  3596. /**
  3597. * @brief Write flash.
  3598. * @param[in] uiReadAddr Address of flash to do read.
  3599. * @param[in] pucReadBuf Buffer for saving read back data.
  3600. * @param[in] uiLength Date length to be read.
  3601. * @return None
  3602. */
  3603. void Hv_Drv_Flash_OnlyRead(UINT32 uiReadAddr, UCHAR8* pucReadBuf, UINT32 uiLength)
  3604. {
  3605. UINT32 uiPreIdx = 0;
  3606. UINT32 uiPreDat = 0;
  3607. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3608. HV_MEMSET(g_ucReadBuf, 0xff, PAGE_READ);
  3609. Hv_Vos_InvalidAllDCache();
  3610. uiPreIdx = uiReadAddr % PAGE_READ;
  3611. HV_LOGV("Hv_Drv_Flash_OnlyRead uiReadAddr %x uiPreIdx %x, length %d\n", uiReadAddr, uiPreIdx,uiLength);
  3612. if (uiPreIdx)
  3613. {
  3614. uiPreDat = PAGE_READ - uiPreIdx;
  3615. uiReadAddr &= ~0xff;
  3616. if (uiLength < uiPreDat)
  3617. {
  3618. uiPreDat = uiLength;
  3619. }
  3620. Flash_OnlyRead(uiReadAddr, g_ucReadBuf, PAGE_READ);
  3621. Hv_Vos_Memcpy(pucReadBuf, g_ucReadBuf+uiPreIdx, uiPreDat);
  3622. uiLength = uiLength - uiPreDat;
  3623. uiReadAddr += PAGE_READ;
  3624. pucReadBuf += uiPreDat;
  3625. }
  3626. if (uiLength > 0)
  3627. {
  3628. Flash_OnlyRead(uiReadAddr, pucReadBuf, uiLength);
  3629. }
  3630. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3631. return;
  3632. }
  3633. /**
  3634. * @brief whether w/r is ongoing.
  3635. * @return w/r state
  3636. */
  3637. UCHAR8 Hv_Drv_Flash_InWritting(void)
  3638. {
  3639. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3640. return 0;
  3641. }
  3642. /**
  3643. * @brief Flash chip erase.
  3644. * @param[in] None.
  3645. * @return None
  3646. */
  3647. void Hv_Drv_Flash_EraseChip(void)
  3648. {
  3649. Hv_Drv_Flash_ProtectDisable();
  3650. _Flash_Erase(g_pFlash, FLASH_ERASE_CHIP, 0);
  3651. Flash_WriteProtectEnable();
  3652. }