hv_drv_UsbMusbHsDma.h 2.5 KB

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  1. /*
  2. * @file hv_drv_UsbMusbHsDma.h
  3. * @brief Header of MUSB OTG driver - support for Mentor's DMA controller.
  4. *
  5. * @author HiView SoC Software Team
  6. * @version 1.0.0
  7. * @date 2022-06-15
  8. */
  9. #ifndef __HV_DRV_USB_MUSB_HS_DMA_H_
  10. #define __HV_DRV_USB_MUSB_HS_DMA_H_
  11. #define MUSB_HSDMA_BASE 0x200
  12. #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
  13. #define MUSB_HSDMA_CONTROL 0x4
  14. #define MUSB_HSDMA_ADDRESS 0x8
  15. #define MUSB_HSDMA_COUNT 0xc
  16. #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
  17. (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
  18. #define musb_read_hsdma_addr(mbase, bchannel) \
  19. musb_readl(mbase, \
  20. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
  21. #define musb_write_hsdma_addr(mbase, bchannel, addr) \
  22. musb_writel(mbase, \
  23. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
  24. addr)
  25. #define musb_read_hsdma_count(mbase, bchannel) \
  26. musb_readl(mbase, \
  27. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
  28. #define musb_write_hsdma_count(mbase, bchannel, len) \
  29. musb_writel(mbase, \
  30. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
  31. len)
  32. /* control register (16-bit): */
  33. #define MUSB_HSDMA_ENABLE_SHIFT 0
  34. #define MUSB_HSDMA_TRANSMIT_SHIFT 1
  35. #define MUSB_HSDMA_MODE1_SHIFT 2
  36. #define MUSB_HSDMA_IRQENABLE_SHIFT 3
  37. #define MUSB_HSDMA_ENDPOINT_SHIFT 4
  38. #define MUSB_HSDMA_BUSERROR_SHIFT 8
  39. #define MUSB_HSDMA_BURSTMODE_SHIFT 9
  40. #define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
  41. #define MUSB_HSDMA_BURSTMODE_UNSPEC 0
  42. #define MUSB_HSDMA_BURSTMODE_INCR4 1
  43. #define MUSB_HSDMA_BURSTMODE_INCR8 2
  44. #define MUSB_HSDMA_BURSTMODE_INCR16 3
  45. #define MUSB_HSDMA_CHANNELS 8
  46. struct musb_dma_controller;
  47. struct musb_dma_channel {
  48. struct dma_channel channel;
  49. struct musb_dma_controller *controller;
  50. u32 start_addr;
  51. u32 len;
  52. u16 max_packet_sz;
  53. u8 idx;
  54. u8 epnum;
  55. u8 transmit;
  56. };
  57. struct musb_dma_controller {
  58. struct dma_controller controller;
  59. struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
  60. void *private_data;
  61. void *base;
  62. u8 channel_count;
  63. u8 used_channels;
  64. int irq;
  65. };
  66. irqreturn_t dma_controller_irq(int irq, void *private_data);
  67. #endif