HT7315_MonitorSOC/sdk/Driver/UsbHost/musb/inc/hv_drv_UsbMusbRegs.h

/*
* @file hv_drv_UsbMusbRegs.h
* @brief Header file of MUSB OTG driver register defines
*
* @author HiView SoC Software Team
* @version 1.0.0
* @date 2022-06-15
*/

#ifndef __HV_DRV_USB_MUSB_REGS_H
#define __HV_DRV_USB_MUSB_REGS_H


#define MUSB_EP0_FIFOSIZE   64  /* This is non-configurable */

#define MUSB_DMA_IRQ        25
#define MUSB_MC_IRQ         26

/*
 * MUSB Register bits
 */

/* POWER */
#define MUSB_POWER_ISOUPDATE    0x80
#define MUSB_POWER_SOFTCONN     0x40
#define MUSB_POWER_HSENAB       0x20
#define MUSB_POWER_HSMODE       0x10
#define MUSB_POWER_RESET        0x08
#define MUSB_POWER_RESUME       0x04
#define MUSB_POWER_SUSPENDM     0x02
#define MUSB_POWER_ENSUSPEND    0x01

/* INTRUSB */
#define MUSB_INTR_SUSPEND       0x01
#define MUSB_INTR_RESUME        0x02
#define MUSB_INTR_RESET         0x04
#define MUSB_INTR_BABBLE        0x04
#define MUSB_INTR_SOF           0x08
#define MUSB_INTR_CONNECT       0x10
#define MUSB_INTR_DISCONNECT    0x20
#define MUSB_INTR_SESSREQ       0x40
#define MUSB_INTR_VBUSERROR     0x80    /* For SESSION end */

/* DEVCTL */
/*
This Read-only bit indicates whether the MUSBHDRC is operating as the ��A�� device or the ��B��
device. 0 => ��A�� device; 1 => ��B�� device. Only valid while a session is in progress.
Note: If the core is in Force_Host mode (i.e. a session has been started with Testmode.D7 = 1), this
bit will indicate the state of the HOSTDISCON input signal from the PHY.
*/
#define MUSB_DEVCTL_BDEVICE     0x80
/*
This Read-only bit is set when a full-speed or high-speed device has been detected being connected
to the port. (High-speed devices are distinguished from full-speed by checking for high-speed
chirps when the device is reset.) Only valid in Host mode.
*/
#define MUSB_DEVCTL_FSDEV       0x40
/*
This Read-only bit is set when a low-speed device has been detected being connected to the port.
Only valid in Host mode.
*/
#define MUSB_DEVCTL_LSDEV       0x20
/*
These Read-only bits encode the current VBus level as follows:
D4  D3  Meaning
0  0  Below SessionEnd
0  1  Above SessionEnd, below AValid
1  0  Above AValid, below VBusValid
1  1  Above VBusValid
*/
#define MUSB_DEVCTL_VBUS        0x18
#define MUSB_DEVCTL_VBUS_SHIFT  3

/* This Read-only bit is set when the MUSBHDRC is acting as a Host. */
#define MUSB_DEVCTL_HM          0x04
/*
When set, the MUSBHDRC will initiate the Host Negotiation when Suspend mode is entered. It is
cleared when Host Negotiation is completed. See Section 15. (��B�� device only)
*/
#define MUSB_DEVCTL_HR          0x02
/*
When operating as an ��A�� device, this bit is set or cleared by the CPU to start or end a session.
When operating as a ��B�� device, this bit is set/cleared by the MUSBHDRC when a session starts/ends.
It is also set by the CPU to initiate the Session Request Protocol, or cleared by the CPU when in
Suspend mode to perform a software disconnect. Note: Clearing this bit when the core is not
suspended will result in undefined behavior.
*/
#define MUSB_DEVCTL_SESSION     0x01

/* MUSB ULPI VBUSCONTROL */
#define MUSB_ULPI_USE_EXTVBUS   0x01
#define MUSB_ULPI_USE_EXTVBUSIND 0x02
/* ULPI_REG_CONTROL */
#define MUSB_ULPI_REG_REQ   (1 << 0)
#define MUSB_ULPI_REG_CMPLT (1 << 1)
#define MUSB_ULPI_RDN_WR    (1 << 2)

/* TESTMODE */
#define MUSB_TEST_FORCE_HOST    0x80
#define MUSB_TEST_FIFO_ACCESS   0x40
#define MUSB_TEST_FORCE_FS      0x20
#define MUSB_TEST_FORCE_HS      0x10
#define MUSB_TEST_PACKET        0x08
#define MUSB_TEST_K             0x04
#define MUSB_TEST_J             0x02
#define MUSB_TEST_SE0_NAK       0x01

/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
#define MUSB_FIFOSZ_DPB         0x10
/* Allocation size (8, 16, 32, ... 4096) */
#define MUSB_FIFOSZ_SIZE        0x0f

/* CSR0 */
#define MUSB_CSR0_FLUSHFIFO     0x0100
#define MUSB_CSR0_TXPKTRDY      0x0002
#define MUSB_CSR0_RXPKTRDY      0x0001

/* CSR0 in Peripheral mode */
#define MUSB_CSR0_P_SVDSETUPEND 0x0080
#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
#define MUSB_CSR0_P_SENDSTALL   0x0020
#define MUSB_CSR0_P_SETUPEND    0x0010
#define MUSB_CSR0_P_DATAEND     0x0008
#define MUSB_CSR0_P_SENTSTALL   0x0004

/* CSR0 in Host mode */
#define MUSB_CSR0_H_DIS_PING    0x0800
#define MUSB_CSR0_H_NAKTIMEOUT  0x0080
#define MUSB_CSR0_H_STATUSPKT   0x0040
#define MUSB_CSR0_H_REQPKT      0x0020
#define MUSB_CSR0_H_ERROR       0x0010
#define MUSB_CSR0_H_SETUPPKT    0x0008
#define MUSB_CSR0_H_RXSTALL     0x0004

/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_CSR0_P_WZC_BITS    \
    (MUSB_CSR0_P_SENTSTALL)
#define MUSB_CSR0_H_WZC_BITS    \
    (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
    | MUSB_CSR0_RXPKTRDY)
#define MUSB_CSR0_H_ERR_BITS  \
    (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_ERROR \
     | MUSB_CSR0_H_RXSTALL)

/* TxType/RxType */
#define MUSB_TYPE_SPEED         0xc0
#define MUSB_TYPE_SPEED_SHIFT   6
#define MUSB_TYPE_PROTO         0x30    /* Implicitly zero for ep0 */
#define MUSB_TYPE_PROTO_SHIFT   4
#define MUSB_TYPE_REMOTE_END    0xf /* Implicitly zero for ep0 */

/* CONFIGDATA */
#define MUSB_CONFIGDATA_MPRXE       0x80    /* Auto bulk pkt combining */
#define MUSB_CONFIGDATA_MPTXE       0x40    /* Auto bulk pkt splitting */
#define MUSB_CONFIGDATA_BIGENDIAN   0x20
#define MUSB_CONFIGDATA_HBRXE       0x10    /* HB-ISO for RX */
#define MUSB_CONFIGDATA_HBTXE       0x08    /* HB-ISO for TX */
#define MUSB_CONFIGDATA_DYNFIFO     0x04    /* Dynamic FIFO sizing */
#define MUSB_CONFIGDATA_SOFTCONE    0x02    /* SoftConnect */
#define MUSB_CONFIGDATA_UTMIDW      0x01    /* Data width 0/1 => 8/16bits */

/* TXCSR in Peripheral and Host mode */
#define MUSB_TXCSR_AUTOSET          0x8000
#define MUSB_TXCSR_DMAENAB          0x1000
#define MUSB_TXCSR_FRCDATATOG       0x0800
#define MUSB_TXCSR_DMAMODE          0x0400
#define MUSB_TXCSR_CLRDATATOG       0x0040
#define MUSB_TXCSR_FLUSHFIFO        0x0008
#define MUSB_TXCSR_FIFONOTEMPTY     0x0002
#define MUSB_TXCSR_TXPKTRDY         0x0001

/* TXCSR in Peripheral mode */
#define MUSB_TXCSR_P_ISO            0x4000
#define MUSB_TXCSR_P_INCOMPTX       0x0080
#define MUSB_TXCSR_P_SENTSTALL      0x0020
#define MUSB_TXCSR_P_SENDSTALL      0x0010
#define MUSB_TXCSR_P_UNDERRUN       0x0004

/* TXCSR in Host mode */
#define MUSB_TXCSR_H_WR_DATATOGGLE  0x0200
#define MUSB_TXCSR_H_DATATOGGLE     0x0100
#define MUSB_TXCSR_H_NAKTIMEOUT     0x0080
#define MUSB_TXCSR_H_RXSTALL        0x0020
#define MUSB_TXCSR_H_ERROR          0x0004

/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_TXCSR_P_WZC_BITS   \
    (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
    | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
#define MUSB_TXCSR_H_WZC_BITS   \
    (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
    | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
#define MUSB_TXCSR_H_ERR_BITS   \
    (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
    | MUSB_TXCSR_H_ERROR)

/* RXCSR in Peripheral and Host mode */
#define MUSB_RXCSR_AUTOCLEAR        0x8000
#define MUSB_RXCSR_DMAENAB          0x2000
#define MUSB_RXCSR_DISNYET          0x1000
#define MUSB_RXCSR_PID_ERR          0x1000
#define MUSB_RXCSR_DMAMODE          0x0800
#define MUSB_RXCSR_INCOMPRX         0x0100
#define MUSB_RXCSR_CLRDATATOG       0x0080
#define MUSB_RXCSR_FLUSHFIFO        0x0010
#define MUSB_RXCSR_DATAERROR        0x0008
#define MUSB_RXCSR_FIFOFULL         0x0002
#define MUSB_RXCSR_RXPKTRDY         0x0001

/* RXCSR in Peripheral mode */
#define MUSB_RXCSR_P_ISO            0x4000
#define MUSB_RXCSR_P_SENTSTALL      0x0040
#define MUSB_RXCSR_P_SENDSTALL      0x0020
#define MUSB_RXCSR_P_OVERRUN        0x0004

/* RXCSR in Host mode */
#define MUSB_RXCSR_H_AUTOREQ        0x4000
#define MUSB_RXCSR_H_WR_DATATOGGLE  0x0400
#define MUSB_RXCSR_H_DATATOGGLE     0x0200
#define MUSB_RXCSR_H_RXSTALL        0x0040
#define MUSB_RXCSR_H_REQPKT         0x0020
#define MUSB_RXCSR_H_ERROR          0x0004

/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_RXCSR_P_WZC_BITS   \
    (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
    | MUSB_RXCSR_RXPKTRDY)
#define MUSB_RXCSR_H_WZC_BITS   \
    (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
    | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
#define MUSB_RXCSR_H_ERR_BITS   \
    (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
    | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_INCOMPRX)

/* HUBADDR */
#define MUSB_HUBADDR_MULTI_TT       0x80

/* ANAREG2 */
#define MUSB_ANAREG2_OTGAVFILTER    0x7000
#define MUSB_ANAREG2_EXCHECKENABLE  0x200000


/*
 * Common USB registers
 */

#define MUSB_FADDR              0x00    /* 8-bit */
#define MUSB_POWER              0x01    /* 8-bit */

#define MUSB_INTRTX             0x02    /* 16-bit */
#define MUSB_INTRRX             0x04
#define MUSB_INTRTXE            0x06
#define MUSB_INTRRXE            0x08
#define MUSB_INTRUSB            0x0A    /* 8 bit */
#define MUSB_INTRUSBE           0x0B    /* 8 bit */
#define MUSB_FRAME              0x0C
#define MUSB_INDEX              0x0E    /* 8 bit */
#define MUSB_TESTMODE           0x0F    /* 8 bit */

/*
 * Additional Control Registers
 */

#define MUSB_DEVCTL             0x60    /* 8 bit */

/* These are always controlled through the INDEX register */
#define MUSB_TXFIFOSZ           0x62    /* 8-bit (see masks) */
#define MUSB_RXFIFOSZ           0x63    /* 8-bit (see masks) */
#define MUSB_TXFIFOADD          0x64    /* 16-bit offset shifted right 3 */
#define MUSB_RXFIFOADD          0x66    /* 16-bit offset shifted right 3 */

/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
#define MUSB_HWVERS             0x6C    /* 8 bit */
#define MUSB_ULPI_BUSCONTROL    0x70    /* 8 bit */
#define MUSB_ULPI_INT_MASK      0x72    /* 8 bit */
#define MUSB_ULPI_INT_SRC       0x73    /* 8 bit */
#define MUSB_ULPI_REG_DATA      0x74    /* 8 bit */
#define MUSB_ULPI_REG_ADDR      0x75    /* 8 bit */
#define MUSB_ULPI_REG_CONTROL   0x76    /* 8 bit */
#define MUSB_ULPI_RAW_DATA      0x77    /* 8 bit */

#define MUSB_EPINFO             0x78    /* 8 bit */
#define MUSB_RAMINFO            0x79    /* 8 bit */
#define MUSB_LINKINFO           0x7a    /* 8 bit */
#define MUSB_VPLEN              0x7b    /* 8 bit */
#define MUSB_HS_EOF1            0x7c    /* 8 bit */
#define MUSB_FS_EOF1            0x7d    /* 8 bit */
#define MUSB_LS_EOF1            0x7e    /* 8 bit */

#define MUSB_ANAREG2            0x90    /* 32 bit */

/* Offsets to endpoint registers */
#define MUSB_TXMAXP             0x10
#define MUSB_TXCSR              0x12
#define MUSB_CSR0               MUSB_TXCSR  /* Re-used for EP0 */
#define MUSB_RXMAXP             0x14
#define MUSB_RXCSR              0x16
#define MUSB_RXCOUNT            0x18
#define MUSB_COUNT0             MUSB_RXCOUNT/* Re-used for EP0 */
#define MUSB_TXTYPE             0x1A
#define MUSB_TYPE0              MUSB_TXTYPE /* Re-used for EP0 */
#define MUSB_TXINTERVAL         0x1B
#define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
#define MUSB_RXTYPE             0x1C
#define MUSB_RXINTERVAL         0x1D
#define MUSB_FIFOSIZE           0x1F        /* Endpoints 1 �C 15 only */
#define MUSB_CONFIGDATA         0x1F        /* Re-used for EP0 */

/* Offsets to endpoint registers in indexed model (using INDEX register) */
#define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
    (0x10 + (_offset))

/* Offsets to endpoint registers in flat models */
#define MUSB_FLAT_OFFSET(_epnum, _offset)   \
    (0x100 + (0x10*(_epnum)) + (_offset))

#define MUSB_TXCSR_MODE     0x2000

/* "bus control"/target registers, for host side multipoint (external hubs) */
#define MUSB_TXFUNCADDR     0x00
#define MUSB_TXHUBADDR      0x02
#define MUSB_TXHUBPORT      0x03

#define MUSB_RXFUNCADDR     0x04
#define MUSB_RXHUBADDR      0x06
#define MUSB_RXHUBPORT      0x07

#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
    (0x80 + (8*(_epnum)) + (_offset))
    
//#define REG_USB_CONTROLLER_RESET 0x10003E04
#define MUSB_REGS_PHY_ADDR_BASE         0x11090400
#define MUSB_REGS_IP_RESET_ADDR         0x11011008

#define MUSB_REGS_ADDR_BASE             0x11090000  //0x41002000
//USB2
//#define MUSB_REGS_ADDR_BASE 0x1C000400

#define MUSB_REQ_PKT_COUNT(epnum, count) \
    USB_W32(MUSB_REGS_ADDR_BASE + 0x300 + 4 * epnum, count)

INLINE u16 musb_readw(u16 offset) {
    return USB_R16(MUSB_REGS_ADDR_BASE + offset);
}

INLINE u32 musb_readl(u16 offset) {
    return USB_R32(MUSB_REGS_ADDR_BASE + offset);
}

INLINE void musb_writew(u16 offset, u16 data) {
    USB_W16(MUSB_REGS_ADDR_BASE + offset, data);
}

INLINE void musb_writew_lo(u16 offset, u16 data) {
    USB_W8(MUSB_REGS_ADDR_BASE + offset, (u8)(data & 0xff));
}

INLINE void musb_writew_hi(u16 offset, u16 data) {
    USB_W8(MUSB_REGS_ADDR_BASE + offset + 1, (u8)(data >> 8));
}

INLINE void musb_writel(u16 offset, u32 data) {
    USB_W32(MUSB_REGS_ADDR_BASE + offset, data);
}

INLINE u8 musb_readb(u16 offset) {
    return USB_R8(MUSB_REGS_ADDR_BASE + offset);
}

INLINE void musb_writeb(u16 offset, u8 data) {
    USB_W8(MUSB_REGS_ADDR_BASE + offset, data);
}

INLINE void musb_write_txfifosz(u8 c_size) {
    musb_writeb(MUSB_TXFIFOSZ, c_size);
}

INLINE void musb_write_txfifoadd(u16 c_off) {
    musb_writew(MUSB_TXFIFOADD, c_off);
}

INLINE void musb_write_rxfifosz(u8 c_size) {
    musb_writeb(MUSB_RXFIFOSZ, c_size);
}

INLINE void  musb_write_rxfifoadd(u16 c_off) {
    musb_writew(MUSB_RXFIFOADD, c_off);
}

INLINE void musb_write_ulpi_buscontrol(u8 val) {
    musb_writeb(MUSB_ULPI_BUSCONTROL, val);
}

INLINE u8 musb_read_txfifosz() {
    return musb_readb(MUSB_TXFIFOSZ);
}

INLINE u16 musb_read_txfifoadd() {
    return musb_readw(MUSB_TXFIFOADD);
}

INLINE u8 musb_read_rxfifosz() {
    return musb_readb(MUSB_RXFIFOSZ);
}

INLINE u16  musb_read_rxfifoadd() {
    return musb_readw(MUSB_RXFIFOADD);
}

INLINE u8 musb_read_ulpi_buscontrol(void) {
    return musb_readb(MUSB_ULPI_BUSCONTROL);
}

INLINE u8 musb_read_configdata(void) {
    musb_writeb(MUSB_INDEX, 0);
    return musb_readb(0x10 + MUSB_CONFIGDATA);
}

INLINE u16 musb_read_hwvers() {
    return musb_readw(MUSB_HWVERS);
}

INLINE void *musb_read_target_reg_base(u8 i) {
    return (void *)(MUSB_BUSCTL_OFFSET(i, 0));
}

#define musb_ep_select(_epnum) \
    musb_writeb(MUSB_INDEX, (_epnum))

static inline void  musb_write_txfunaddr(u8 epnum,
        u8 qh_addr_reg)
{
    musb_writeb(MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
            qh_addr_reg);
}

static inline void  musb_write_txhubaddr(u8 epnum,
        u8 qh_addr_reg)
{
    musb_writeb(MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
            qh_addr_reg);
}

static inline void  musb_write_txhubport(u8 epnum,
        u8 qh_h_port_reg)
{
    musb_writeb(MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
            qh_h_port_reg);
}


static inline void musb_write_rxfunaddr(u8 epnum, u8 qh_addr_reg)
{
    musb_writeb(MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR),
            qh_addr_reg);
}

static inline void musb_write_rxhubaddr(u8 epnum,
        u8 qh_h_addr_reg)
{
    musb_writeb(MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR),
            qh_h_addr_reg);
}

static inline void musb_write_rxhubport(u8 epnum,
        u8 qh_h_port_reg)
{
    musb_writeb(MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT),
            qh_h_port_reg);
}
#endif  /* __MUSB_REGS_H__ */