HT7315_MonitorSOC/sdk/PM/ht7315/project/common/hv_pm51_Reg.h

/*
 * @file hv_pm51_Reg.h
 * @brief PM51 register related define.
 *
 * @verbatim
 * ==============================================================================
 *                        ##### How to use #####
 * ==============================================================================
 * (+) Use ()
 *
 * @endverbatim
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2023-03-01
 */

#ifndef __HV_PM51_REG_H__
#define __HV_PM51_REG_H__

#include "hv_pm51_Base.h"

#define XDATABYTE(regaddr) *((UCHAR8 xdata *)(regaddr))
#define XDATADWORD(regaddr) *((ULONG32 xdata *)(regaddr))

#define Write_XDATAReg(regaddr, value)             XDATABYTE(regaddr) = (value)
#define Read_XDATAReg(regaddr)                    XDATABYTE(regaddr)

#define Write_XDATARegDWORD(regaddr, value)     XDATADWORD(regaddr) = (value)
#define Read_XDATARegDWORD(regaddr)             XDATADWORD(regaddr)

/* dma register define */
/* dma transfer xram start addr */
#define reg_xram_startaddr_low_byte        (0x8000)
#define reg_xram_startaddr_high_byte    (reg_xram_startaddr_low_byte + 1)

/* dma transfer data length */
#define reg_lenth_count_low_byte        (0x8002)
#define reg_lenth_count_high_byte        (reg_lenth_count_low_byte + 1)

/* dma transfer eerpom start address */
#define reg_code_startaddr_byte0        (0x8005)
#define reg_code_startaddr_byte1        (reg_code_startaddr_byte0 + 1)
#define reg_code_startaddr_byte2        (reg_code_startaddr_byte1 + 1)

/* dma trigger reg */
#define reg_length_cnt_flag                (0x8004)        /* 0x8004[7] set 1 to trigger dma, hw clear to 0 after dma done */

/* sfr & esfr register define */
/* Timer divider ,keep default */
sfr ET10USL     =   0xA6;
sfr ET10USH     =   0xA7;
/* Timer WDG Enable */
/* [0]: timer0 [1]: timer1 [2]: watchdog [7]: 1 = read reg counter 0= read setting value */
sfr ETEA        =   0xA9;
/* Timer value set */
sfr ET0L        =   0xAA;
sfr ET0H        =   0xAB;
sfr ET1L        =   0xAC;
sfr ET1H        =   0xAD;
/* WDG valuse set */
sfr EWDG        =   0xAE;
/* APB Addr High 16bit offset for 8051 */
sfr APB_AddrReg_Low     = 0xC4;
sfr APB_AddrReg_High    = 0xC5;
/* std 8051 sfr */
sfr T2CON   =   0xC8;
sfr RCP2L   =   0xCA;
sfr RCP2H   =   0xCB;
sfr TL2     =   0xCC;
sfr TH2     =   0xCD;

sfr EI1     =   0xE8;
/* int proirity */
sfr IPH     =   0xB9;
sfr IP1     =   0xF8;
sfr IPH1    =   0xF9;

#endif