hv_drv_HdmiRx.c 20 KB

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  1. /**
  2. * @file hv_drv_HdmiRx.c
  3. * @brief HDMI RX 模块提供的驱动层
  4. * @details 该模块接口提供给Hiview-Madia-Ware及其他上层应用使用。
  5. * @author HiView SoC Software team
  6. * @version 0.0.1
  7. * @date 20220822
  8. * @copyright Copyright(c),2022-8, Hiview Software. All rights reserved.
  9. * @par History:
  10. * <table>
  11. * <tr><th>作者 <th>日期 <th>描述
  12. * <tr><td>HiView SoC Software team <td>20220822 <td>Create and first Version.
  13. * </table>
  14. **/
  15. #include "hv_comm_Assert.h"
  16. #include "hv_comm_Define.h"
  17. #include "hv_drv_HdmiRx.h"
  18. #include "hv_drv_HdmiInc.h"
  19. #include "hv_cal_HdmiInc.h"
  20. #include "hv_comm_TimingDatabase.h"
  21. #include "hv_chip_Clk.h"
  22. #include "hv_comm_DataBase.h"
  23. Status Hv_Drv_HdmiRx_TmdsInit(UCHAR8 ucPortIndex, UCHAR8 ucLaneSwap)
  24. {
  25. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  26. HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_SetHdmi21Enable(ucPortIndex, HV_FALSE));
  27. Hv_Cal_HdmiRx_TmdsCharacterAlignInit(ucPortIndex);
  28. Hv_Cal_HdmiRx_TmdsDeskewInit(ucPortIndex);
  29. //Hv_Cal_HdmiRx_TmdsLinkInit(ucPortIndex);
  30. Hv_Cal_HdmiRx_TmdsLaneClockInit(ucPortIndex);
  31. Hv_Cal_HdmiRx_Tmds4LaneMode(ucPortIndex, ucLaneSwap);
  32. Hv_Cal_HdmiRx_OpenTmdsAutoEq(ucPortIndex);
  33. return HV_SUCCESS;
  34. }
  35. Status Hv_Drv_HdmiRx_GetAVIPara(UCHAR8 ucPortIndex, VideoColorParam *pstVideoAVIPara, VideoTimingParam *pstTimingPara)
  36. {
  37. /*检查入参*/
  38. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  39. HV_ASSERT_VALID_PTR(pstVideoAVIPara);
  40. CalVideoColorParam stVideoPara = {0};
  41. Status uiResult = Hv_Cal_HdmiRx_GetAVIPara(ucPortIndex, &stVideoPara);
  42. HV_MEMCPY(pstVideoAVIPara, &stVideoPara, sizeof(VideoColorParam));
  43. return uiResult;
  44. }
  45. Status Hv_Drv_HdmiRx_GetTimingPara(UCHAR8 ucPortIndex, VideoTimingParam *pstTimingPara)
  46. {
  47. /*检查入参*/
  48. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  49. ColorDepthType ucColorDepth = ColorDepthType_8Bit;
  50. ColorFormatType ucColorFormat = ColorFormatType_RGB;
  51. CalVideoTimingParam stTimingInfo = {0};
  52. UINT32 uiPixelRep = 0;
  53. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  54. HV_ASSERT_VALID_PTR(pstTimingPara);
  55. UINT32 uiResult = Hv_Cal_HdmiRx_GetTimingHVInfo(ucPortIndex, &stTimingInfo, ucLaneSwap);
  56. if(HV_SUCCESS != uiResult)
  57. {
  58. HV_LOG_INFO(HDMI, "HDMI%d Get Timing Failed Result: %d", ucPortIndex, uiResult);
  59. return HV_FAILURE;
  60. }
  61. HV_MEMCPY(pstTimingPara, &stTimingInfo, sizeof(VideoTimingParam));
  62. //pstTimingPara->uiRxDpllSetFreqKHz = 0;
  63. ucColorDepth = Hv_Cal_HdmiRx_GetColorDepth(ucPortIndex);
  64. switch (ucColorDepth)
  65. {
  66. case ColorDepthType_6Bit:
  67. case ColorDepthType_8Bit:
  68. {
  69. /*No need to do any*/
  70. break;
  71. }
  72. case ColorDepthType_10Bit:
  73. {
  74. pstTimingPara->usHTotal = (pstTimingPara->usHTotal << 2) / 5;
  75. pstTimingPara->usHActive = (pstTimingPara->usHActive << 2) / 5;
  76. pstTimingPara->uiRxDpllSetFreqKHz = (pstTimingPara->uiRxDpllSetFreqKHz << 2) / 5;
  77. break;
  78. }
  79. case ColorDepthType_12Bit:
  80. {
  81. pstTimingPara->usHTotal = (pstTimingPara->usHTotal << 1) / 3;
  82. pstTimingPara->usHActive = (pstTimingPara->usHActive << 1) / 3;
  83. pstTimingPara->uiRxDpllSetFreqKHz = (pstTimingPara->uiRxDpllSetFreqKHz << 1) / 3;
  84. break;
  85. }
  86. case ColorDepthType_16Bit:
  87. {
  88. pstTimingPara->usHTotal = (pstTimingPara->usHTotal) >> 1;
  89. pstTimingPara->usHActive = (pstTimingPara->usHActive) >> 1;
  90. pstTimingPara->uiRxDpllSetFreqKHz = (pstTimingPara->uiRxDpllSetFreqKHz) >> 1;
  91. break;
  92. }
  93. default:
  94. {
  95. HV_LOG_ERROR(HDMI, "Get HDMI%d Pixel Color Depth Error", ucPortIndex);
  96. break;
  97. }
  98. }
  99. ucColorFormat = Hv_Cal_HdmiRx_GetColorFormat(ucPortIndex);
  100. if (ucColorFormat == ColorFormatType_YCbCr420)
  101. {
  102. pstTimingPara->usHTotal = (pstTimingPara->usHTotal) << 1;
  103. pstTimingPara->usHActive = (pstTimingPara->usHActive) << 1;
  104. pstTimingPara->uiRxDpllSetFreqKHz = (pstTimingPara->uiRxDpllSetFreqKHz) << 1;
  105. }
  106. /* Pixel Repeation handle */
  107. uiPixelRep = Hv_Cal_HdmiRx_GetPixelRepeatFactor(ucPortIndex);
  108. if(uiPixelRep < 10)
  109. {
  110. pstTimingPara->usHTotal = (pstTimingPara->usHTotal) / (uiPixelRep + 1);
  111. pstTimingPara->usHActive = (pstTimingPara->usHActive) / (uiPixelRep + 1);
  112. pstTimingPara->uiRxDpllSetFreqKHz = (pstTimingPara->uiRxDpllSetFreqKHz) / (uiPixelRep + 1);
  113. }
  114. pstTimingPara->uiFreqKHz = (UINT32)((DOUBLE64)((DOUBLE64)(pstTimingPara->usHTotal) * (DOUBLE64)(pstTimingPara->usVTotal)) * (pstTimingPara->fFrameRate) / 1000);
  115. pstTimingPara->uiHFreqHz = (UINT32)((FLOAT32)(pstTimingPara->usVTotal) * (pstTimingPara->fFrameRate));
  116. return HV_SUCCESS;
  117. }
  118. Status Hv_Drv_HdmiRx_InterruptInit(UCHAR8 ucPortIndex)
  119. {
  120. /* 检查入参 */
  121. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  122. HdmiRxIntStatus stHdmiIntRxStatus = {HV_HDMIRX_INT_1_EVENT_FRL_RATE_CHG, HV_HDMIRX_INT_2_EVENT_STANDBY_DDC};
  123. /* Set the Trigger mode as edge p */
  124. Hv_Cal_HdmiRx_SetInterruptTriggerRule(ucPortIndex);
  125. /* 初始化关闭所有中断 */
  126. HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_InterruptClearEvent(ucPortIndex, &stHdmiIntRxStatus));
  127. return HV_SUCCESS;
  128. }
  129. Status Hv_Drv_HdmiRx_PortInit(UCHAR8 ucPortIndex)
  130. {
  131. /*检查入参*/
  132. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  133. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  134. USHORT16 ausAutoEqValue[4] = {0x178, 0x178, 0x178, 0x00};
  135. HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_Init(ucPortIndex, ucLaneSwap));
  136. #if (HV_PROJECT_CONFIG_CTS == HV_CONFIG_ON)
  137. Hv_Cal_HdmiRx_InitWithCtsOn(ucPortIndex);
  138. #endif
  139. /* HPD 初始化 */
  140. //HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_HPDIOInit(ucPortIndex));
  141. /* 5V 检测初始化 */
  142. HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_CableConnectInit(ucPortIndex));
  143. /* 中断初始化 */
  144. HV_ASSERT_SUCCESS(Hv_Drv_HdmiRx_InterruptInit(ucPortIndex));
  145. Hv_Drv_HdmiRx_CecInit(ucPortIndex);
  146. Hv_Cal_HdmiRx_DdcInit(ucPortIndex);
  147. /* TMDS init */
  148. HV_ASSERT_SUCCESS(Hv_Drv_HdmiRx_TmdsInit(ucPortIndex, ucLaneSwap));
  149. Hv_Cal_HdmiRx_FrlInit(ucPortIndex);
  150. Hv_Cal_HdmiRx_OpenFrlAutoEq(ucPortIndex);
  151. HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_PhyInit(ucPortIndex, ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_INV_PN : HV_BOARD_CONFIG_HDMI1_INV_PN)));
  152. HV_ASSERT_PEEK_SUCCESS(Hv_Cal_HdmiRx_AudioInit(ucPortIndex));
  153. Hv_Cal_HdmiRx_SetSwEqValue(ucPortIndex, ausAutoEqValue, ucLaneSwap);
  154. Hv_Cal_HdmiRX_SwitchAutoEqTable(ucPortIndex, HV_TRUE);
  155. #if (HV_PROJECT_CONFIG_CTS == HV_CONFIG_ON)
  156. Hv_Cal_HdmiRx_ConfigurePhyRterm(ucPortIndex, 0xF);
  157. #endif
  158. HV_LOG_DEBUG(HDMI, "Hv_Drv_HdmiRx_PortInit SUCCESS with Port:%d.",ucPortIndex);
  159. return HV_SUCCESS;
  160. }
  161. Status Hv_Drv_HdmiRx_HPDCtrol(UCHAR8 ucPortIndex, BOOL bSwitch)
  162. {
  163. /*检查入参*/
  164. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  165. /* 对HPD进行配置 */
  166. if (bSwitch == HV_TRUE)
  167. {
  168. Hv_Drv_HdmiRx_TmdsPreReset(ucPortIndex);
  169. Hv_Cal_HdmiRx_ClrMrTiming(ucPortIndex);
  170. Hv_Cal_HdmiRx_ControlScdcByHPDSwitch(ucPortIndex, bSwitch);
  171. #if (HV_BOARD_CONFIG_HDMI_HPD_SOURCE_5V == 1)
  172. return Hv_Cal_HdmiRx_HPDOnWithSource5V(ucPortIndex);
  173. #else
  174. return Hv_Cal_HdmiRx_HPDOn(ucPortIndex);
  175. #endif
  176. }
  177. else
  178. {
  179. /* 协议里面规定HPD拉低的时候SCDC需要恢复到默认状态 */
  180. Hv_Drv_HdmiRx_TmdsPreReset(ucPortIndex);
  181. Hv_Cal_HdmiRx_ClrMrTiming(ucPortIndex);
  182. Hv_Cal_HdmiRx_ControlScdcByHPDSwitch(ucPortIndex, bSwitch);
  183. #if (HV_BOARD_CONFIG_HDMI_HPD_SOURCE_5V == 1)
  184. return Hv_Cal_HdmiRx_HPDOffWithSource5V(ucPortIndex);
  185. #else
  186. return Hv_Cal_HdmiRx_HPDOff(ucPortIndex);
  187. #endif
  188. }
  189. }
  190. #if (HV_PROJECT_CONFIG_FRL)
  191. /**
  192. * @brief frl rate change indicate frl or tmds
  193. *
  194. * FRL Rate 4 Bit
  195. * 0 : No FRL, TMDS Only
  196. * 1 : 3G @ 3Lane
  197. * 2 : 6G @ 3Lane
  198. * 3 : 6G @ 4Lane
  199. * 4 : 8G @ 4Lane
  200. * 5 : 10G @ 4Lane
  201. * 6 : 12G @ 4Lane
  202. * 7 - 15 :reserved
  203. */
  204. UCHAR8 Hv_Drv_HdmiFRLRateChange(UCHAR8 ucPortIndex)
  205. {
  206. UCHAR8 ucFRLRate = 0;
  207. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  208. /*检查入参*/
  209. HV_ASSERT_TRUE_RET_NO_LOG(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM,HV_FAILURE);
  210. ucFRLRate = Hv_Cal_HdmiRx_GetFrlRate(ucPortIndex);
  211. if (ucFRLRate == 0)
  212. {
  213. /* TMDS mode */
  214. Hv_Cal_HdmiRx_SWCfgReset(ucPortIndex);
  215. Hv_Cal_HdmiRx_SetHdmi21Enable(ucPortIndex, HV_FALSE);
  216. Hv_Cal_HdmiRX_PhyClockInit(ucPortIndex, E_D4LANETMDS, ucLaneSwap);
  217. }
  218. else
  219. {
  220. Hv_Cal_HdmiRx_SWCfgReset(ucPortIndex);
  221. Hv_Cal_HdmiRX_SwitchAutoEqTable(ucPortIndex, HV_FALSE);
  222. /* FRL mode */
  223. Hv_Cal_HdmiRx_SetHdmi21Enable(ucPortIndex, HV_TRUE);
  224. if ((ucFRLRate == 1) || (ucFRLRate == 2))
  225. {
  226. Hv_Cal_HdmiRX_PhyClockInit(ucPortIndex, E_D3LANEFRL, ucLaneSwap);
  227. }
  228. else
  229. {
  230. Hv_Cal_HdmiRX_PhyClockInit(ucPortIndex, E_D4LANEFRL, ucLaneSwap);
  231. }
  232. }
  233. //Hv_Cal_HdmiRx_SetFrlRateFreq(ucPortIndex,ucFRLRate);
  234. return ucFRLRate;
  235. }
  236. #endif
  237. HdmiRxGearMode Hv_Drv_HdmiRx_GetRatioType(UCHAR8 ucPortIndex, HdmiRxGearMode emGearModeCfg)
  238. {
  239. /*检查入参*/
  240. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  241. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  242. #if (HV_PROJECT_CONFIG_FRL == HV_CONFIG_ON)
  243. if(Hv_Cal_HdmiRx_GetFrlRate(ucPortIndex) != 0)
  244. {
  245. return E_FRLMODE;
  246. }
  247. #endif
  248. if (Hv_Cal_HdmiRx_GetScdcTmdsBitClkRatio(ucPortIndex, ucLaneSwap))
  249. {
  250. return E_RATIOGEAR;
  251. }
  252. else
  253. {
  254. return Hv_Cal_HdmiRx_GetGearMode(ucPortIndex, emGearModeCfg, ucLaneSwap);
  255. }
  256. }
  257. UINT32 Hv_Drv_HdmiRx_InterruptEnPrint(UCHAR8 ucPortIndex, UCHAR8 ucIntr)
  258. {
  259. /*检查入参*/
  260. HV_ASSERT_TRUE_RET(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, 0);
  261. HV_ASSERT_TRUE_RET(ucIntr < 2, 0);
  262. return Hv_Cal_HdmiRx_InterruptEnPrint(ucPortIndex, ucIntr);
  263. }
  264. VOID HV_Drv_HdmirRx_ResetScdcWith5V(UCHAR8 ucPortIndex)
  265. {
  266. if(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM)
  267. {
  268. #if (HV_PROJECT_CONFIG_CTS == HV_CONFIG_OFF)
  269. HV_Cal_HdmirRx_ResetScdcWith5V(ucPortIndex);
  270. #else
  271. HV_Cal_HdmirRx_ResetScdcWith5VCtsOn(ucPortIndex);
  272. #endif
  273. }
  274. return;
  275. }
  276. Status Hv_Drv_HdmiRx_EnterStandby(UCHAR8 ucPortIndex, BOOL bEnterStandby)
  277. {
  278. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  279. return Hv_Cal_HdmiRx_EnterStandby(ucPortIndex, bEnterStandby);
  280. }
  281. Status Hv_Drv_HdmiRx_DdcSend(UCHAR8 ucPortIndex, UCHAR8 *data, UINT32 len)
  282. {
  283. HV_ASSERT_TRUE_RET_NO_LOG(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, HV_FAILURE);
  284. return Hv_Cal_HdmiRx_SendDdcMsg(ucPortIndex, len, data);
  285. }
  286. UCHAR8 Hv_Drv_HdmiRx_DdcRecv(UCHAR8 ucPortIndex, UCHAR8 *ucBuf)
  287. {
  288. UCHAR8 aucFreesyncData[5] = {0x51, 0x82, 0x01, 0xE6, 0x5A};
  289. UCHAR8 aucReplyData[11] = {0x6E, 0x88, 0x02, 0x00, 0xE6, 0x01, 0x00, 0x01, 0x00, 0x00, 0x53};
  290. HV_ASSERT_TRUE_RET_NO_LOG(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, HV_FAILURE);
  291. UCHAR8 ucRecvLen = Hv_Cal_HdmiRx_RecvDdcMsg(ucPortIndex, ucBuf);
  292. if(ucRecvLen == 5)
  293. {
  294. if (0 == HV_MEMCMP(aucFreesyncData, ucBuf, 5))
  295. {
  296. if (HV_ON == HV_COMMON_DATABASE_GET(UserData, ucFreeSync))
  297. {
  298. aucReplyData[9] = 0x01;
  299. aucReplyData[10] = 0x52;
  300. }
  301. else
  302. {
  303. aucReplyData[9] = 0x00;
  304. aucReplyData[10] = 0x53;
  305. }
  306. Hv_Cal_HdmiRx_SendDdcMsg(ucPortIndex, sizeof(aucReplyData), aucReplyData);
  307. }
  308. }
  309. return ucRecvLen;
  310. }
  311. Status Hv_Drv_HdmiRx_InitEdidConf(UCHAR8 ucPortIndex)
  312. {
  313. /*检查入参*/
  314. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  315. #if (HV_PROJECT_CONFIG_EDID_EXTER_EEPROM == HV_CONFIG_ON)
  316. /* 关闭 EDID on Register. */
  317. Hv_Cal_HdmiRx_CloseRegisterEdid(ucPortIndex);
  318. #else
  319. /* 开启 EDID on Register. */
  320. #if (HV_PROJECT_CONFIG_ESEGMENT == HV_CONFIG_ON)
  321. Hv_Cal_HdmiRx_OpenRegisterEdid(ucPortIndex, 1);
  322. #else
  323. Hv_Cal_HdmiRx_OpenRegisterEdid(ucPortIndex, 0);
  324. #endif
  325. #endif
  326. return HV_SUCCESS;
  327. }
  328. Status Hv_Drv_HdmiRx_TmdsPreReset(UCHAR8 ucPortIndex)
  329. {
  330. /*检查入参*/
  331. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  332. Hv_Cal_HdmiRx_BusSwReset(ucPortIndex);
  333. Hv_Cal_HdmiRx_TmdsSwReset(ucPortIndex);
  334. return HV_SUCCESS;
  335. }
  336. VOID Hv_Drv_HdmiRx_AudioCheck(UCHAR8 ucPortId)
  337. {
  338. HV_ASSERT_TRUE_VOID(ucPortId <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  339. Hv_Cal_HdmiRx_AudioCheck(ucPortId);
  340. return;
  341. }
  342. VOID Hv_Drv_HdmiRx_ReloadColorDepth(UCHAR8 ucPortIndex)
  343. {
  344. HV_ASSERT_TRUE_VOID(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  345. Hv_Cal_HdmiRx_ReloadColorDepth(ucPortIndex);
  346. return;
  347. }
  348. Status Hv_Drv_HdmiRx_GetMDVrrPara(UCHAR8 ucPortIndex, VRRInfoParam* pstVrrMdPara)
  349. {
  350. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  351. HV_ASSERT_VALID_PTR(pstVrrMdPara);
  352. CalVRRInfoParam stMDPara = {0};
  353. HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_GetMDVrrPara(ucPortIndex, &stMDPara));
  354. HV_MEMCPY(pstVrrMdPara, &stMDPara, sizeof(VRRInfoParam));
  355. return HV_SUCCESS;
  356. }
  357. Status Hv_Drv_HdmiRx_GetAMDVendSpecInfoPara(UCHAR8 ucPortIndex, VRRInfoParam *pstVendSpecInfoPara)
  358. {
  359. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  360. HV_ASSERT_VALID_PTR(pstVendSpecInfoPara);
  361. CalVRRInfoParam stVSIPara = {0};
  362. HV_ASSERT_SUCCESS(Hv_Cal_HdmiRx_GetAMDVendSpecInfoPara(ucPortIndex, &stVSIPara));
  363. HV_MEMCPY(pstVendSpecInfoPara, &stVSIPara, sizeof(VRRInfoParam));
  364. return HV_SUCCESS;
  365. }
  366. Status Hv_Drv_HdmiRx_GetAudioPara(UCHAR8 ucPortIndex, AudioPara *pstAudioPara)
  367. {
  368. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  369. HV_ASSERT_VALID_PTR(pstAudioPara);
  370. CalAudioPara stAudioInfo = {0};
  371. Hv_Cal_HdmiRx_GetAudioPara(ucPortIndex, &stAudioInfo);
  372. HV_MEMCPY(pstAudioPara, &stAudioInfo, sizeof(AudioPara));
  373. return HV_SUCCESS;
  374. }
  375. Status Hv_Drv_HdmiRx_GetHDRPara(UCHAR8 ucPortIndex, HDRParam *pstHDRPara)
  376. {
  377. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  378. HV_ASSERT_VALID_PTR(pstHDRPara);
  379. CalHDRParam stHdrInfo = {0};
  380. Hv_Cal_HdmiRx_GetHDRPara(ucPortIndex, &stHdrInfo);
  381. HV_MEMCPY(pstHDRPara, &stHdrInfo, sizeof(HDRParam));
  382. return HV_SUCCESS;
  383. }
  384. BOOL Hv_Drv_HdmiRX_RobustCheckRatioMode(UCHAR8 ucPortIndex)
  385. {
  386. HV_ASSERT_TRUE_RET(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, HV_FALSE);
  387. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  388. return Hv_Cal_HdmiRX_RobustCheckRatioMode(ucPortIndex, ucLaneSwap);
  389. }
  390. BOOL Hv_Drv_HdmiRx_IsClockStable(UCHAR8 ucPortIndex)
  391. {
  392. HV_ASSERT_TRUE_RET(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, HV_FALSE);
  393. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  394. return Hv_Cal_HdmiRx_IsClockStable(ucPortIndex, ucLaneSwap);
  395. }
  396. Status Hv_Drv_HdmiRx_GetLaneCEDValue(UCHAR8 ucPortIndex, HdmiRxLaneCED *pstLaneCedValue)
  397. {
  398. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  399. HV_ASSERT_VALID_PTR(pstLaneCedValue);
  400. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  401. return Hv_Cal_HdmiRx_GetLaneCEDValue(ucPortIndex, pstLaneCedValue, ucLaneSwap);
  402. }
  403. Status Hv_Drv_HdmiRx_SetSwEqValue(UCHAR8 ucPortIndex, const USHORT16 *pusSwEqValue)
  404. {
  405. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  406. HV_ASSERT_VALID_PTR(pusSwEqValue);
  407. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  408. return Hv_Cal_HdmiRx_SetSwEqValue(ucPortIndex, pusSwEqValue, ucLaneSwap);
  409. }
  410. BOOL Hv_Drv_HdmiRx_IsTimingStable(UCHAR8 ucPortIndex)
  411. {
  412. HV_ASSERT_TRUE_RET(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, HV_FALSE);
  413. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  414. return Hv_Cal_HdmiRx_IsTimingStable(ucPortIndex, ucLaneSwap);
  415. }
  416. Status Hv_Drv_HdmiRx_CableConnectAction(UCHAR8 ucPortIndex, BOOL bCableSta)
  417. {
  418. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  419. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  420. return Hv_Cal_HdmiRx_CableConnectAction(ucPortIndex, bCableSta, ucLaneSwap);
  421. }
  422. VOID Hv_Drv_HdmiRX_SwitchPhyGearMode(UCHAR8 ucPortIndex, HdmiRxGearMode ucGrearMode)
  423. {
  424. HV_ASSERT_TRUE_VOID(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  425. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  426. #if (HV_PROJECT_CONFIG_CTS == HV_CONFIG_OFF)
  427. if(ucGrearMode < E_HIGHGEAR || ucGrearMode == E_UNLOCKED)
  428. {
  429. Hv_Cal_HdmiRX_SwitchAutoEqTable(ucPortIndex, HV_TRUE);
  430. }
  431. else
  432. {
  433. Hv_Cal_HdmiRX_SwitchAutoEqTable(ucPortIndex, HV_FALSE);
  434. }
  435. #endif
  436. return Hv_Cal_HdmiRX_SwitchPhyGearMode(ucPortIndex, ucGrearMode, ucLaneSwap);
  437. }
  438. /**
  439. * @brief If the PHY is fast locked.
  440. * @param[in] Port Number used for the HDMI RX.
  441. * @return TRUE is Loced False is unlocked.
  442. */
  443. BOOL Hv_Drv_HdmiRX_IsPhyFastLocked(UCHAR8 ucPortIndex)
  444. {
  445. HV_ASSERT_TRUE_RET(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, HV_FALSE);
  446. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  447. return Hv_Cal_HdmiRX_IsPhyFastLocked(ucPortIndex, ucLaneSwap);
  448. }
  449. /**
  450. * @brief If the PHY TMDS Clock Is OverFlow.
  451. * @param[in] Port Number used for the HDMI RX.
  452. * @return TRUE is OverFlow False is not OverFlow.
  453. */
  454. BOOL Hv_Drv_HdmiRX_IsTMDSClockOverFlow(UCHAR8 ucPortIndex)
  455. {
  456. HV_ASSERT_TRUE_RET(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM, HV_FALSE);
  457. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  458. return Hv_Cal_HdmiRX_IsTMDSClockOverFlow(ucPortIndex, ucLaneSwap);
  459. }
  460. Status Hv_Drv_HdmiRx_Hdcp1XInitForAuth(UCHAR8 ucPortIndex)
  461. {
  462. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  463. UCHAR8 ucTryCnt = 10;
  464. Hv_Cal_HdmiRx_SetHDCPHdmiMode(ucPortIndex, HV_FALSE);
  465. do
  466. {
  467. if(Hv_Cal_HdmiRx_DdcCurStateIsIdle(ucPortIndex))
  468. {
  469. #if (HV_PROJECT_CONFIG_CTS == HV_CONFIG_ON)
  470. Hv_Cal_HdmiRx_SetHdcp1XRiSel(ucPortIndex, 0x0);
  471. #endif
  472. /* 配置到HDMI模式到非HDMI模式 */
  473. Hv_Cal_HdmiRx_SetHDCP1Xstatus(ucPortIndex, HV_FALSE);
  474. if(Hv_Cal_HdmiRx_DdcCurStateIsIdle(ucPortIndex))
  475. {
  476. break;
  477. }
  478. }
  479. Hv_Vos_Delayus(500);
  480. } while (ucTryCnt--);
  481. if (!ucTryCnt)
  482. {
  483. HV_LOG_ERROR(HDMI, "ddc busy when proc hdcp 1x, %u", ucPortIndex);
  484. #if (HV_PROJECT_CONFIG_CTS == HV_CONFIG_ON)
  485. Hv_Cal_HdmiRx_SetHdcp1XRiSel(ucPortIndex, 0x0);
  486. #endif
  487. /* 配置到HDMI模式到非HDMI模式 */
  488. Hv_Cal_HdmiRx_SetHDCP1Xstatus(ucPortIndex, HV_FALSE);
  489. }
  490. return HV_SUCCESS;
  491. }
  492. BOOL Hv_Drv_HdmiRx_CheckTmdsClockAbnormal(UCHAR8 ucPortIndex)
  493. {
  494. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  495. UCHAR8 ucLaneSwap = ((ucPortIndex == 0) ? HV_BOARD_CONFIG_HDMI0_LANE_SWP : HV_BOARD_CONFIG_HDMI1_LANE_SWP);
  496. return Hv_Cal_HdmiRx_CheckTmdsClockAbnormal(ucPortIndex, ucLaneSwap);
  497. }
  498. BOOL Hv_Drv_HdmiRx_GetCableStatus(UCHAR8 ucPortIndex)
  499. {
  500. HV_ASSERT_TRUE(ucPortIndex <= HV_BOARD_CONFIG_MAX_HDMI_PORT_NUM);
  501. #if (HV_BOARD_CONFIG_HDMI_CABLE_DETECT == CABLE_DETECT_WITH_SOURCE_5V)
  502. return (!Hv_Cal_HdmiRx_GetCableStatus(ucPortIndex));
  503. #else
  504. return Hv_Cal_HdmiRx_GetCableStatus(ucPortIndex);
  505. #endif
  506. }