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- /*
- * core_config.h
- */
- /*
- Copyright (c) 2007-2018, MIPS Tech, LLC and/or its affiliated group companies or licensors
- All rights reserved.
- Redistribution and use in source and binary forms, with or without modification, are
- permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this list of
- conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice, this list
- of conditions and the following disclaimer in the documentation and/or other materials
- provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors may be
- used to endorse or promote products derived from this software without specific prior
- written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- #include <boot.h>
- #define ILINE_SIZE 32 // L1 instruction cache line size
- #define DLINE_SIZE 32 // L1 data cache line size
- #define L2LINE_SIZE 32 // L2 line size could be 32 or 64
- #define HCI 18 // Hardware Cache Initialization bit
- #define LA la // use load address (32 bit) to load address
- #define CORE_FPGA6_MIG 0xbbc00004
- #define BOSTON_PLAT_BASE 0xffffffffb7ffd000
- #define BOSTON_PLAT_DDR3STAT 0x14
- #define BOSTON_PLAT_DDR3STAT_CALIB (1 << 2)
- #define BOSTON_LCD_BASE 0xffffffffb7fff000
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