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- /*
- * set_gpr_boot_values.S
- *
- */
- /*
- Copyright (c) 2007-2018, MIPS Tech, LLC and/or its affiliated group companies or licensors
- All rights reserved.
- Redistribution and use in source and binary forms, with or without modification, are
- permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this list of
- conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice, this list
- of conditions and the following disclaimer in the documentation and/or other materials
- provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors may be
- used to endorse or promote products derived from this software without specific prior
- written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- #include <mips/asm.h>
- #include <boot.h>
- #include <mips/m32c0.h>
- #include <mips/regdef.h>
- // defines not yet in m32c0.h
- #define C0_MVPCTL $0, 1
- #define C0_MVPCONF0 $0, 2
- #define C0_VPECTL $1, 1
- #define C0_VPECONF0 $1, 2
- #define C0_TCSTATUS $2, 1
- #define C0_TCRESTART $2, 3
- #define C0_TCHALT $2, 4
- #define C0_TCBIND $2, 2
- /**************************************************************************************
- **************************************************************************************/
- LEAF(set_gpr_boot_values)
- mfc0 a0, C0_EBASE // Read CP0 EBase
- ext r23_cpu_num, a0, 0, 4 // Extract CPUNum
- la gp, _gp // All vpe share globals.
- la sp, __boot_stack // Set up stack base.
- // ins sp, r23_cpu_num, STACK_SIZE_LOG2 // only one VPE, use arbitrary stack
- // Every vpe will set up the following to simplify resource initialization.
- mfc0 a0, C0_TCBIND // Read CP0 TCBind
- ext r9_vpe_num, a0, 0, 4 // Extract CurVPE
- ext r18_tc_num, a0, 21, 8 // Extract CurTC
- mfc0 a0, C0_MVPCONF0 // C0_MVPConf0
- ext r21_more_tcs, a0, 0, 8 // Extract PTC
- ext r20_more_vpes, a0, 10, 4 // Extract VPE
- is_not_cps: // This processor is not part of a Coherent Processing System. Set up valid defaults.
- li r11_is_cps, 0
- li r8_core_num, 0
- li r19_more_cores, 0
- done_init_gpr:
- jr ra
- END(set_gpr_boot_values)
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