HT7315_MonitorSOC/sdk/Driver/HDCP/drv/inc/hv_drv_HdcpRx.h

/**
 * @file hv_drv_HdcpRx.h
 * @brief Header file of drv module.
 *
 * @verbatim
 * ==============================================================================
 *                        ##### How to use #####
 * ==============================================================================
 * (+) Use Hv_Drv_Hdcp_GetComIrqFlag(...) Get Hdcp Irq Flag.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxGetMsgState(...) Get Hdmi Msg State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiGetKmStoreStat(...) Get Stored Km State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiSetKmStoreStat(...) Set Stored Km State.
 * (+) Use Hv_Drv_Hdcp2x_DpGetKmStoreStat(...) Get Stored Km State.
 * (+) Use Hv_Drv_Hdcp_DpSetVersion(...) Set Hdcp Version.
 * (+) Use Hv_Drv_Hdcp_HdmiGetRole(...) Get Hdcp Rx Role.
 * (+) Use Hv_Drv_Hdcp1x_DpSetBcaps(...) Set Hdcp Bcaps.
 * (+) Use Hv_Drv_Hdcp1x_DrvDpRxSetState(...) Set Hdcp1x state.
 * (+) Use Hv_Drv_Hdcp1x_DpRxB1Computations(...) Hdcp2x action process for WrAksv state.
 * (+) Use Hv_Drv_Hdcp1x_HdmiRxB1Computations(...) Hdcp2x action process for WrAksv state.
 * (+) Use Hv_Drv_Hdcp1x_HdmiRxInit(...) Hdcp1x init for Hdmi.
 * (+) Use Hv_Drv_Hdcp1x_DpRxInit(...) Hdcp1x init for Dp.
 * (+) Use Hv_Drv_Hdcp2x_DpRxB0ProcMsgAKESendCert(...) Hdcp2x Action process for WrAKEInit State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxB0ProcMsgAKESendCert(...) Hdcp2x Action process for WrAKEInit State.
 * (+) Use Hv_Drv_Hdcp2x_DpRxB1ProcMsgAKENoStoredKm(...) Hdcp2x Action process for WrNoStoredKm State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxB1ProcMsgAKENoStoredKm(...) Hdcp2x Action process for WrNoStoredKm State.
 * (+) Use Hv_Drv_Hdcp2x_DpRxB1ProcMsgAKEStoredKm(...) Hdcp2x Action process for WrStoredKm State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxB1ProcMsgAKEStoredKm(...) Hdcp2x Action process for WrStoredKm State.
 * (+) Use Hv_Drv_Hdcp2x_DpRxB1ProcAKEPairing(...) Hdcp2x Action process for RdHPrime State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxB1ProcAKEPairing(...) Hdcp2x Action process for RdHPrime State.
 * (+) Use Hv_Drv_Hdcp2x_DpRxB2LCSendLPrime(...) Hdcp2x Action process for WrLPrime State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxB2LCSendLPrime(...) Hdcp2x Action process for WrLPrime State.
 * (+) Use Hv_Drv_Hdcp2x_DpRxB3ComputeKs(...) Hdcp2x Action process for WrAKESendEks State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxB3ComputeKs(...) Hdcp2x Action process for WrAKESendEks State.
 * (+) Use Hv_Drv_Hdcp2x_DpRxB4Authenticated(...) Hdcp2x Action process for ComputeEksDone State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxB4Authenticated(...) Hdcp2x Action process for ComputeEksDone State.
 * (+) Use Hv_Drv_Hdcp2x_HdmiRxInit(...) Hdcp2x init for Hdmi.
 * (+) Use Hv_Drv_Hdcp2x_DpRxInit(...) Hdcp2x init for Dp.
 * (+) Use Hv_Drv_Hdcp2x_DpSetKmStoreStat(...) Hdcp2x Set Km Stored State for Dp.
 * (+) Use Hv_Drv_Hdcp2x_DpResetLinkIntegrityFailure(...) Reset Link Integrity Failure state.
 * (+) Use Hv_Drv_Hdcp2x_HdmiResetLinkIntegrityFailure(...) Reset Link Integrity Failure state.
 * (+) Use Hv_Drv_Hdcp_SetProcFlag(...) Set Hdcp Process Flag.
 * (+) Use Hv_Drv_Hdcp_GetProcFlag(...) Get Hdcp Process Flag.
 *
 * @endverbatim
 *
 * @author HiView SoC Software Team
 * @version 1.0.0
 * @date 2022-08-30
 */


#ifndef _HV_DRV_HDCP_RX_H
#define _HV_DRV_HDCP_RX_H

#include "hv_drv_Hdcp1xRx.h"
#include "hv_drv_Hdcp2xRx.h"
#include "hv_comm_Log.h"
#include "hv_comm_Assert.h"
#include "Common/hv_comm_DataType.h"
#include "hv_chip_Config.h"
#include "hv_comm_Define.h"


#define HV_HDCP_1X_SIZE_AKSV        0x05   /**< Aksv Size          */
#define HV_HDCP_1X_SIZE_AN          0x08   /**< An Size            */
#define HV_HDCP_1X_SIZE_KM          0x02   /**< KM Key Set Size  */
#define HV_HDCP_1X_SIZE_KS          0x02   /**< Ks Size  */
#define HV_HDCP_1X_SIZE_M0          0x02   /**< M0 Size  */
  
//#define GET_HDCP_IRQ_OK 1
//#define GET_HDCP_IRQ_NOK 0

/************DP HDCP2x RxStatus Status************ */
typedef enum _Hdcp2xDpRxStatusMask
{
    HV_HDCP_2X_RX_STATUS_READY                   = 0x1,
    HV_HDCP_2X_RX_STATUS_H_AVAILABLE             = 0x2,
    HV_HDCP_2X_RX_STATUS_PAIRING_AVAILABLE       = 0x4,
    HV_HDCP_2X_RX_STATUS_REAUTH_REQ              = 0x8,
    HV_HDCP_2X_RX_STATUS_LINK_INTERGITY_FAILTURE = 0x10,
    HV_HDCP_2X_RX_STATUS_MASK                    = 0x1F,
    HV_HDCP_2X_RX_STATUS_UNDEFIEND               = 0xE0
} Hdcp2xDpRxStatusMask;

typedef enum _Hdcp1xRxStatusMask
{
    HV_HDCP_1X_RX_STATUS_READY                   = 0x1,
    HV_HDCP_1X_RX_STATUS_R0_AVAILABLE            = 0x2,
    HV_HDCP_1X_RX_STATUS_LINK_INTERGITY_FAILTURE = 0x4,
    HV_HDCP_1X_RX_STATUS_REAUTH_REQ              = 0x8,
    HV_HDCP_1X_RX_STATUS_MASK                    = 0xF,
    HV_HDCP_1X_RX_STATUS_UNDEFIEND               =0xF0
} Hdcp1xRxStatusMask;

/**************HDMI HDCP INT MASK BEGIN**************************** */
typedef enum
{
    HV_HDCP_HDMI_1X_READ_00 = 0,
    HV_HDCP_HDMI_1X_READ_RI,
    HV_HDCP_HDMI_1X_READ_PJ,
    HV_HDCP_HDMI_1X_WRITE_AKSV,
    HV_HDCP_HDMI_1X_WRITE_AINFO,
    HV_HDCP_HDMI_1X_WRITE_An,
    HV_HDCP_HDMI_1X_READ_V,
    HV_HDCP_HDMI_1X_READ_BAPS,
    HV_HDCP_HDMI_1X_KSV_INFO,
    HV_HDCP_HDMI_2X_READ_VERSION,
    HV_HDCP_HDMI_2X_UNUSED,
    HV_HDCP_HDMI_2X_WRITE_MSG,
    HV_HDCP_HDMI_2X_READ_RXSTATUS,
    HV_HDCP_HDMI_2X_READ_MSG,
    HV_HDCP_HDMI_2X_WRITE_AKEINIT,
    HV_HDCP_HDMI_2X_WRITE_AKENOSTOREDKM,
    HV_HDCP_HDMI_2X_WRITE_AKESTOREDKM,
    HV_HDCP_HDMI_2X_WRITE_LCINIT,
    HV_HDCP_HDMI_2X_WRITE_SKESENDEKS,
    HV_HDCP_HDMI_2X_WRITE_REPEATERAUTHSENDACK,
    HV_HDCP_HDMI_2X_WRITE_REPEATERAUTHSTREAMMANAGE
} HdcpRxHdmiIntBit;

typedef enum
{
    HV_HDCP_HDMI_1X_READ_00_DONE_INT                     =    (1 <<(HV_HDCP_HDMI_1X_READ_00)),
    HV_HDCP_HDMI_1X_READ_RI_DONE_INT                     =    (1 <<(HV_HDCP_HDMI_1X_READ_RI)),
    HV_HDCP_HDMI_1X_READ_PJ_DONE_INT                     =    (1 <<(HV_HDCP_HDMI_1X_READ_PJ)),
    HV_HDCP_HDMI_1X_WRITE_AKSV_DONE_INT                  =    (1 <<(HV_HDCP_HDMI_1X_WRITE_AKSV)),
    HV_HDCP_HDMI_1X_WRITE_AINFO_DONE_INT                 =    (1 <<(HV_HDCP_HDMI_1X_WRITE_AINFO)),
    HV_HDCP_HDMI_1X_WRITE_AN_DONE_INT                    =    (1 <<(HV_HDCP_HDMI_1X_WRITE_An)),
    HV_HDCP_HDMI_1X_READ_V_DONE_INT                      =    (1 <<(HV_HDCP_HDMI_1X_READ_V)),
    HV_HDCP_HDMI_1X_READ_BAPS_DONE_INT                   =    (1 <<(HV_HDCP_HDMI_1X_READ_BAPS)),
    HV_HDCP_HDMI_1X_KSV_FIFO_DONE_INT                    =    (1 <<(HV_HDCP_HDMI_1X_KSV_INFO)),
    HV_HDCP_HDMI_2X_READ_HDCP_VERSION_DONE_INT           =    (1 <<(HV_HDCP_HDMI_2X_READ_VERSION)),
    HV_HDCP_HDMI_2X_UNUSED_INT                           =    (1 <<(HV_HDCP_HDMI_2X_UNUSED)),
    HV_HDCP_HDMI_2X_WTITE_MSG_DONE_INT                   =    (1 <<(HV_HDCP_HDMI_2X_WRITE_MSG)),
    HV_HDCP_HDMI_2X_READ_RXSTATUS_DONE_INT               =    (1 <<(HV_HDCP_HDMI_2X_READ_RXSTATUS)),
    HV_HDCP_HDMI_2X_READ_MSG_DONE_INT                    =    (1 <<(HV_HDCP_HDMI_2X_READ_MSG)),
    HV_HDCP_HDMI_2X_WRITE_AKEINIT_DONE_INT               =    (1 <<(HV_HDCP_HDMI_2X_WRITE_AKEINIT)),
    HV_HDCP_HDMI_2X_WRITE_AKENOSTOREDKM_DONE_INT         =    (1 <<(HV_HDCP_HDMI_2X_WRITE_AKENOSTOREDKM)),
    HV_HDCP_HDMI_2X_WRITE_AKESTOREDKM_DONE_INT           =    (1 <<(HV_HDCP_HDMI_2X_WRITE_AKESTOREDKM)),
    HV_HDCP_HDMI_2X_WRITE_LCINIT_DONE_INT                =    (1 <<(HV_HDCP_HDMI_2X_WRITE_LCINIT)),
    HV_HDCP_HDMI_2X_WRITE_SKESENDEKS_DONE_INT            =    (1 <<(HV_HDCP_HDMI_2X_WRITE_SKESENDEKS)),
    HV_HDCP_HDMI_2X_WRITE_REPEATERAUTHSENDACK_DONE_INT           =    (1 <<(HV_HDCP_HDMI_2X_WRITE_REPEATERAUTHSENDACK)),
    HV_HDCP_HDMI_2X_WRITE_REPEATERAUTHSTREAMMANAGE_DONE_INT      =    (1 <<(HV_HDCP_HDMI_2X_WRITE_REPEATERAUTHSTREAMMANAGE)),
    HV_HDCP_HDMI_INT_ALL_ENABLE                                  =    (0x001FE7FF),
    HV_HDCP_HDMI_INT_1X_ALL_ENABLE                               =    (0x000001FF),
    HV_HDCP_HDMI_INT_2X_ALL_ENABLE                               =    (0x001FE600)
} HdcpRxHdmiIntBitMask;

/**************HDMI HDCP INT MASK END**************************** */

/************HDCP IRQ Bit Index************ */
typedef enum _HdcpComIrqNum
{
    HDCP0_COM_IRQ_DP_LIC = 0,
    HDCP0_COM_IRQ_CM,
    HDCP_COM_IRQ_AES,
    HDCP_COM_IRQ_EME_OAEP_DECRYPY,
    HDCP_COM_IRQ_SHA1,
    HDCP_COM_IRQ_KMCALC,
    HDCP_COM_IRQ_SHA256,
    HDCP_COM_IRQ_EME_OAEP_ENCRYPY,
    HDCP_COM_IRQ_EME_CERT_SRM,
    HDCP_COM_IRQ_WRITE_OFFSET,
    HDCP0_COM_IRQ_LOAD_PJ,
    HDCP0_COM_IRQ_LOAD_RI,
    HDCP0_COM_IRQ_FIRST_INT,
    HDCP1_COM_IRQ_LOAD_PJ,
    HDCP1_COM_IRQ_LOAD_RI,
    HDCP1_COM_IRQ_CM,
    HDCP1_COM_IRQ_DP_LIC,
    HDCP1_COM_IRQ_FIRST_INT,
} HdcpComIrqNum;

/************HDCP IRQ Bit Mask************ */
typedef enum _HdcpComIrqMask
{
    HV_HDCP0_COM_IRQ_DP_LIC_DONE           = 0x1,
    HV_HDCP0_COM_IRQ_CM_DONE               = 0x2,
    HV_HDCP_COM_IRQ_AES_DONE               = 0x4,
    HV_HDCP_COM_IRQ_EME_OAEP_DECRYPY_DONE  = 0x8,
    HV_HDCP_COM_IRQ_SHA1_DONE              = 0x10,
    HV_HDCP_COM_IRQ_KMCALC_DONE            = 0x20,
    HV_HDCP_COM_IRQ_SHA256_DONE            = 0x40,
    HV_HDCP_COM_IRQ_EME_OAEP_ENCRYPY_DONE  = 0x80,
    HV_HDCP_COM_IRQ_CERT_SRM_DONE          = 0x0100,
    HV_HDCP_COM_IRQ_WRITE_OFFSET_DONE      = 0x0200,
    HV_HDCP0_COM_IRQ_LOAD_PJ_DONE          = 0x0400,
    HV_HDCP0_COM_IRQ_LOAD_RI_DONE          = 0x0800,
    HV_HDCP0_COM_IRQ_FIRST_INT_DONE        = 0x1000,
    HV_HDCP1_COM_IRQ_LOAD_PJ_DONE          = 0x2000,
    HV_HDCP1_COM_IRQ_LOAD_RI_DONE          = 0x4000,
    HV_HDCP1_COM_IRQ_CM_DONE               = 0x8000,
    HV_HDCP1_COM_IRQ_DP_LIC_DONE           = 0x010000,
    HV_HDCP1_COM_IRQ_FIRST_INT_DONE        = 0x020000,
    //HV_HDCP_COM_IRQ_MASK = 0x00FFFF,
    HV_HDCP_COM_IRQ_MASK                   = 0x01C0FF,
} HdcpComIrqMask;


/************HDCP CallBack Func************ */
typedef void (*HdcpRxCallBack)(UINT32 uiRxState, void *arg);

/************HDCP Init Params************ */
typedef struct
{
    HdcpPortType                 enPortType;
    HdcpVersion                  enVersion;
    HdcpRole                     enRole;
    HdcpRxCallBack               pfRxStateFunc;
} HdcpInitParams;

/************HDCP Rx Struct************ */

typedef enum _HdcpExistStat
{
    HDCP_EXIST    = 0x01,
    HDCP_NO_EXIST = 0xFF
}HdcpExistStat;

typedef enum _HdcpLinkStat
{
    HDCP_LINK_NONE = 0xFF,
    HDCP_LINK_OK   = 0x01,
}HdcpLinkStat;

typedef struct _HdcpControl
{
    UCHAR8 ucExist;
    UCHAR8 ucLinkStatus;
    UCHAR8 ucWorkStatus;
}HdcpControl;

#define HS_HAL_HDMI_HDCP_RXSTAT_SIZE 2

typedef enum _Hdcp2xHdmiRxStatusMask
{
    HV_HDCP_2X_HDMI_RX_MSG_SIZE_MASK          = 0x03FF,
    HV_HDCP_2X_HDMI_RX_STATUS_READY_MASK      = 0x0400,
    HV_HDCP_2X_HDMI_RX_STATUS_REAUTH_REQ_MASK = 0x0800,
    HV_HDCP_2X_HDMI_RX_STATUS_MASK            = 0x0FFF,
    HV_HDCP_2X_HDMI_RX_STATUS_UNDEFIEND       = 0xF000,
    HV_HDCP_2X_HDMI_RX_VERSION_MASK           = 0x04
} Hdcp2xHdmiRxStatusMask;

/*******HDCP 1.X***********************/
typedef struct _Hdcp1xRxParams
{
    UCHAR8 AKsv[HV_HDCP_1X_SIZE_AKSV];
    UCHAR8 An[HV_HDCP_1X_SIZE_AN];
    UINT32 Km[HV_HDCP_1X_SIZE_KM];
    UINT32 Ks[HV_HDCP_1X_SIZE_KS];
    UINT32 M0[HV_HDCP_1X_SIZE_M0];
    USHORT16 R0;
} Hdcp1xRxParams;


typedef struct
{
    Hdcp1xRxParams stParams;
    UCHAR8 *DKS;
    UCHAR8 *BKsv;
    UCHAR8 BCaps;   /* DP(1) And Hdmi(0) Is Not the same */
} Hdcp1xRx;


/************HDCP Rx Stored Km State************ */
typedef enum _HdcpKmStoreState
{
    HV_HDCP_RX_STORED_KM = 0,
    HV_HDCP_NO_STORED_KM,
    HV_HDCP_STORED_KM_INVALID
} HdcpKmStoreState;

/**********HDCP Event Begin******************* */
typedef enum _HdcpRxEvtId
{
    HdcpRxEvt_Invalid,
    /*HDCP 2X Start*/
    Hdcp2xRxEvt_WrAKEInit,
    Hdcp2xRxEvt_WrAKENoStoredKm,
    Hdcp2xRxEvt_WrAKEStoredKm,
    Hdcp2xRxEvt_RdHPrime,
    Hdcp2xRxEvt_WrLcInit,
    Hdcp2xRxEvt_WrAKESendEks,
    Hdcp2xRxEvt_ComputeEksDone,
    Hdcp2xRxEvt_UpdateStreamType,
    Hdcp2xRxEvt_LinkIntegrityFailure,
    Hdcp2xRxEvt_Max,
    /*HDCP 2X End*/

    /*HDCP 1X Start*/
    Hdcp1xRxEvt_WrAksv,
    Hdcp1xRxEvt_Max,
    /*HDCP 1X End*/

}HdcpRxEvtId;

/**********HDCP Event End******************* */

typedef struct _HdcpRx
{
    /*HDCP2X RX*/
    Hdcp2xRxMsgState                enHdcp2xMsgState;
    Hdcp2xRx                        stHdcp2xRx;
    HdcpKmStoreState                enKmStoreState;
    /*HDCP1X RX*/
    Hdcp1xRx                        stHdcp1xRx;
}HdcpRx;

/**
 * @brief Get Hdcp Irq Flag.
 * @param[in] enComIrqType: Hdcp Irq Mask for bit.
 * @return HV_TRUE--Get Int Enable Falg, HV_FALSE--Not Get Int Enable Falg.
 */
BOOL Hv_Drv_Hdcp_GetComIrqFlag(HdcpComIrqMask enComIrqType);

/**
 * @brief Clear Hdcp Irq Flag of Engine.
 * @param[in] None.
 * @return None.
 */
VOID Hv_Drv_Hdcp_ClrIrqMask( );

/**
 * @brief Set Hdcp version.
 * @param[in] HdcpVersion: HDCP Version.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp_HdmiSetVersion(UINT32 HdcpVersion, UCHAR8 ucPortIndex);


/**
 * @brief Enable HDCP Irq.
 * @param[in] void.
 * @return None.
 */
VOID Hv_Drv_Hdcp_ComIrqEnable(void);

/**
 * @brief Get Hdcp Rx Version.
 * @param[in] ucPortIndex: Port index.
 * @return Hdcp Version.
 */
UINT32 Hv_Drv_Hdcp_HdmiGetVersion(UCHAR8 ucPortIndex);

/**
 * @brief Get Hdcp Rx Role.
 * @param[in] ucPortIndex: Port index.
 * @return Hdcp Role.
 */
UINT32 Hv_Drv_Hdcp_HdmiGetRole(UCHAR8 ucPortIndex);

/**
 * @brief Get Hdcp Interrupt flag Mask.
 * @param[in] None.
 * @return Flag Value of the HDCP Interrupt.
 */
UINT32 Hv_Drv_Hdcp_GetIrqFlag(VOID);

/**
 * @brief Hdcp Rx Module init.
 * @param[in] None.
 * @return None.
 */
VOID Hv_Drv_Hdcp_RxModuleInit(UCHAR8 ucHdcpPortIndex);

/**
 * @brief Hdcp Rx initi for Hdmi.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
//VOID Hv_Drv_Hdcp_HdmiSetHdcpPath(UCHAR8 ucHdcpPortIndex);

/**
 * @brief Hdcp Rx initi for Hdmi.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_HdmiSetHdcpPath(UCHAR8 ucHdcpPortIndex);

/**
 * @brief Hdcp Rx initi for Hdmi.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_HdmiSetHdcpPath(UCHAR8 ucHdcpPortIndex);

/**
 * @brief Hdcp Rx initi for DP.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_DpSetHdcpPath(UCHAR8 ucHdcpPortIndex);
/**
 * @brief Hdcp Rx initi for DP.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_DpSetHdcpPath(UCHAR8 ucHdcpPortIndex);

/**
 * @brief Hdcp Rx initi for Dp.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp_DpRxInit(UCHAR8 ucPortIndex);

/**
 * @brief Load Hdcp Keys.
 * @param[in] ucPortIndex: Port index.
 * @param[in] enPortType: Port Type DP/HDMI.
 * @return None.
 */
//VOID Hv_Drv_Hdcp_LoadKeys(HdcpPortType enPortType, UCHAR8 ucPortIndex);

/**
 * @brief Get Dp Irq Event.
 * @param[in] puiIrqMask: Hdcp Irq mask for Dp.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
HdcpRxEvtId Hv_Drv_Hdcp_DpGetIrqEvent(const UINT32* puiIrqMask, UCHAR8 ucPortIndex, HdcpKmStoreState enStoreState);

/**
 * @brief Get Hdmi Irq Event.
 * @param[in] uiIrqMask: Hdcp Irq mask for Hdmi.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
HdcpRxEvtId Hv_Drv_Hdcp_HdmiGetIrqEvent(const UINT32 uiIrqMask, UCHAR8 ucPortIndex, HdcpKmStoreState enKmState, Hdcp2xRxMsgState enMsgState);

/**
 * @brief Set Hdcp Process Flag.
 * @param[in] bProcFlag: True -- Active Process, False--Nor active Process.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_HdmiGetRxMsgFromReg(UCHAR8 *pucData, USHORT16 usMsgSize, UCHAR8 ucPortIndex);

/**
 * @brief Get Hdcp Process Flag.
 * @param[in] None.
 * @return Process Flag.
 */
//BOOL Hv_Drv_Hdcp_GetProcFlag(VOID);

/**
 * @brief Set Hdcp port mask.
 * @param[in] Port index.
 * @param[in] Port Type DP or Hdmi.
 * @param[in] Dp Port index.
 * @return HV_SUCCESS or HV_FAILURE.
 */
Status Hv_Drv_Hdcp_SetPortMask(UCHAR8 ucPortIndex, HdcpPortType enPortType, UCHAR8 ucHdcpPortIndex);

/**
 * @brief Set Hdcp port mask.
 * @param[in] Port index.
 * @param[in] Port Type DP or Hdmi.
 * @return HV_SUCCESS or HV_FAILURE.
 */
//Status Hv_Drv_Hdcp_RmPortMask(LinkPortIndex enPortIndex, UINT32 uiHdcpWorkStat);

/**
 * @brief Get Valid Hdcp.
 * @param[in] Port index.
 * @param[in] Port Type DP or Hdmi.
 * @return Hdcp port.
 */
//UCHAR8 Hv_Drv_Hdcp_GetValidHdcp(LinkPortIndex enPortIndex, UINT32 uiHdcpWorkStat, UCHAR8 ucPxpFlag);

/**
 * @brief Hdcp Auto Mux select.
 * @param[in] Port index.
 * @param[in] Hdcp Work Status.
 * @return Hdcp port.
 */
//UCHAR8 Hv_Drv_Hdcp_AutoMuxSel(LinkPortIndex enPortIndex, UINT32 uiHdcpWorkStat);

/**
 * @brief Hdcp Get Active Port.
 * @return Hdcp port.
 */
Status Hv_Drv_Hdcp2x_DpRxGetMsg(HdcpRx* pstHdcpRxIns, HV_HDCP_2X_RX_MSG_ID enMsgId, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp Dp Mix Clear.
 * @param[in] Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp_DpMixClr(UCHAR8 ucHdcpPortIndex);
/*******************Hdcp 1x Function Begin***********************************/

/**
 * @brief Get Hdcp Rx state.
 * @param[in] ucPortIndex: Port index.
 * @return Hdcp Rx state.
 */
//UINT32 Hv_Drv_Hdcp1x_DpRxGetState(UCHAR8 ucPortIndex);

/**
 * @brief Get Hdcp Rx state.
 * @param[in] ucPortIndex: Port index.
 * @return Hdcp Rx state.
 */
//UINT32 Hv_Drv_Hdcp1x_HdmiRxGetState(UCHAR8 ucPortIndex);

/**
 * @brief Set Hdcp Bcaps.
 * @param[in] Bcaps: HDCP Bcaps Msg.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_DpSetBcaps(UCHAR8 Bcaps, UCHAR8 ucPortIndex);

/**
 * @brief Set Hdcp Bcaps.
 * @param[in] Bcaps: HDCP Bcaps Msg.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_HdmiSetBcaps(UCHAR8 Bcaps, UCHAR8 ucPortIndex);

/**
 * @brief Set Hdcp1x State.
 * @param[in] Hdcp1xRxState: Hdcp1x state.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
//VOID Hv_Drv_Hdcp1x_DpRxSetState(UINT32 Hdcp1xRxState, UCHAR8 ucPortIndex);

/**
 * @brief Set Hdcp1x State.
 * @param[in] Hdcp1xRxState: Hdcp1x state.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_DpRxSetRI(USHORT16 usRI, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp1x action process for WrAksv state.
 * @param[in] enPortType: Port Type.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp1x_RxB1Computations(HdcpPortType enPortType, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp1x action process for WrAksv state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp1x_DpRxGetMsg(HdcpRx* pstHdcpRxIns, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp1x action process for WrAksv state.
 * @param[in] ucPortIndex: RX Port Index.
 * @param[in] ucHdcpIndex: HDCP Port Index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
VOID Hv_Drv_Hdcp1x_NotifyTxIrq(Hdcp1xRxStatusMask enStatusType, UCHAR8 ucPortIndex, UCHAR8 ucHdcpIndex);

/**
 * @brief Reset Hdcp Rx Auth state.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_DpRxAuthStart(UCHAR8 ucPortIndex, UCHAR8 ucHdcpPortIndex);

/**
 * @brief Hdcp1x init for Hdmi.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_HdmiRxInit(UCHAR8 ucPortIndex);

VOID Hv_Drv_Hdcp1x_DpResetLinkIntegrityFailure(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp1x init for Dp.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1x_HdmiRxSetRI(USHORT16 usRI, UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp1x_HdmiRxSetRiSelToHw(UCHAR8 ucPortIndex, UCHAR8 ucHdcpPortIndex);

VOID Hv_Drv_Hdcp1x_HdmiRxAuthStart(UCHAR8 ucPortIndex, UCHAR8 ucHdcpPortIndex);
VOID Hv_Drv_Hdcp1x_HdmiRxSetEessQstc(UCHAR8 ucHdcpPortIndex);
VOID Hv_Drv_Hdcp_HdmiRxClearMsgAfterAutherDone(UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp_HdmiCommInit();
VOID Hv_Drv_Hdcp_SetHdmiHdcpVersion(UCHAR8 ucHdcpVersion);
VOID Hv_Drv_Hdcp_RealseDpPath(UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp_AttachDpPath(UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp_RealseStatus(UCHAR8 ucHdcpPortIndex);
VOID Hv_Drv_Hdcp_RealseHdmiPath(UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp_AttachHdmiPath(UCHAR8 ucPortIndex);

/*******************Hdcp 1x Function End***********************************/


/*******************Hdcp 2x Function Begin***********************************/
/**
 * @brief Set Rrx Random Value and Rx Caps Role Value.
 * @param[in] ucCapRole: Hdcp Rx Caps Role Value.
 * @param[out] pstHdcpRxIns : Caps and Rrx Value in the parameter.
 * @return 1--Get Int Enable Falg, 0--Not Get Int Enable Falg.
 */
VOID Hv_Drv_Hdcp2x_RxGenRrxAndCaps(HdcpRx* pstHdcpRxIns, UCHAR8 ucCapRole);

/**
 * @brief Get Hdcp Rx state.
 * @param[in] ucPortIndex: Port index.
 * @return Hdcp Rx state.
 */
Status Hv_Drv_Hdcp2x_RxResetParams(Hdcp2xRx *pstHdcp2xRxIns);

/**
 * @brief Get Km Store state.
 * @param[in] ucPortIndex: Port index.
 * @return Km Store state.
 */
//UINT32 Hv_Drv_Hdcp2x_DpGetKmStoreStat(UCHAR8 ucPortIndex);

/**
 * @brief Set Km Store state.
 * @param[in] KmStoreState: Km Store State.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
//VOID Hv_Drv_Hdcp2x_HdmiSetKmStoreStat(UINT32 KmStoreState, UCHAR8 ucPortIndex);

/**
 * @brief Get Km Store state.
 * @param[in] ucPortIndex: Port index.
 * @return Km Store state.
 */
UINT32 Hv_Drv_Hdcp2x_HdmiGetKmStoreStat(UCHAR8 ucPortIndex);

/**
 * @brief Get Hdcp2x Msg send state.
 * @param[in] ucPortIndex: Port index.
 * @return Hdcp send Msg State.
 */
//UINT32 Hv_Drv_Hdcp2x_HdmiRxGetMsgState(UCHAR8 ucPortIndex);


/**
 * @brief Set Hdcp2x RxCaps.
 * @param[in] pU8RxCaps: Hdcp RxCaps.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_DpSetRxCaps(const UCHAR8* pU8RxCaps, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKEInit state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_RxB0ProcMsgAKESendCert(HdcpPortType enPortType, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKEInit state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
VOID Hv_Drv_Hdcp2x_DpRxSaveRrxToReg(UCHAR8* pucRrx, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKEInit state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp2x_HdmiRxB0ProcMsgAKESendCert(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKENoStoredKm state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_RxB1ProcMsgAKENoStoredKm(HdcpPortType enPortType, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKENoStoredKm state.
 * @param[in] ucPortIndex: RX Port Index.
 * @param[in] ucHdcpIndex: HDCP Port Index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
VOID Hv_Drv_Hdcp2x_NotifyTxIrq(Hdcp2xDpRxStatusMask enStatusType, UCHAR8 ucPortIndex, UCHAR8 ucHdcpIndex);

/**
 * @brief Hdcp2x process for WrAKENoStoredKm state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_HdmiRxB1ProcMsgAKENoStoredKm(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKEStoredKm state.
 * @param[in] enPortType: Port Type.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
VOID Hv_Drv_Hdcp2x_DpSaveHPrimeToReg(UCHAR8* pucHPrime, UCHAR8 ucPortIndex);


/**
 * @brief Hdcp2x process for WrAKEStoredKm state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_DpRxB1ProcMsgAKEStoredKm(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKEStoredKm state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_HdmiRxB1ProcMsgAKEStoredKm(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for RdHPrime state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_RxB1ProcAKEPairing(HdcpPortType enPortType, UCHAR8 ucPortIndex);
//Status Hv_Drv_Hdcp2x_HdmiRxGetMsg(HdcpRx* pstHdcpRxIns, USHORT16 usMsgSize, UCHAR8 ucPortIndex);


/**
 * @brief Hdcp2x process for RdHPrime state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_DpRxB1ProcAKEPairing(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for RdHPrime state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
VOID Hv_Drv_Hdcp2x_DpSavePairingToReg(UCHAR8* pucEkhKm, UCHAR8 ucPortIndex);


/**
 * @brief Clear HDCP Msg Size for Hdcp2x.
 * @param[in] ucPortIndex: Port Index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_HdmiClrRxStatSize(UCHAR8 ucPortIndex);

/**
 * @brief Set HDCP Re Authered Bit(11).
 * @param[in] ucPortIndex: Port Index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_HdmiSetRxStatusReAuth(UCHAR8 ucPortIndex);

/**
 * @brief Get HDCP Re Authered Bit(11).
 * @param[in] ucPortIndex: Port Index.
 * @return UCHAR8.
 */
UCHAR8 Hv_Drv_Hdcp_HdmiGetReAuthStatus(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrLcInit state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
VOID Hv_Drv_Hdcp2x_DpSaveLPrimeToReg(UCHAR8* pucLPrime, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrLcInit state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_HdmiRxB2LCSendLPrime(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKESendEks state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_HdmiRxB3ComputeKsB4Authented(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKESendEks state.
 * @param[in] enPortType: Port Type.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_RxB3ComputeKs(HdcpPortType enPortType, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKESendEks state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_DpRxB3ComputeKs(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for WrAKESendEks state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp2x_HdmiRxB3ComputeKs(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for ComputeEksDone state.
 * @param[in] enPortType: Port Type.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp2x_RxB4Authenticated(HdcpPortType enPortType, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x Link Integrity Check Failure.
 * @param[in] enPortType: Port Type.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp2x_RxB4LinkIntegrityFailure(HdcpPortType enPortType, UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x Link Integrity Check Failure.
 * @param[in] enPortType: Port Type.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
//Status Hv_Drv_Hdcp2x_HdmiRxB4LinkIntegrityFailure(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for ComputeEksDone state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp2x_DpRxB4Authenticated(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x process for ComputeEksDone state.
 * @param[in] ucPortIndex: Port index.
 * @return Status, 0-HV_SUCCESS, 1-HV_FAILURE.
 */
Status Hv_Drv_Hdcp2x_HdmiRxB4Authenticated(UCHAR8 ucPortIndex);


/**
 * @brief Hdcp2x init for Hdmi.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_HdmiRxInit(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp2x init for Dp.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_DpUpdateStreamType(UCHAR8 ucPortIndex, UCHAR8 ucHdcpPortIndex);

/**
 * @brief Hdcp2x Set Km Stored State for Dp.
 * @param[in] KmStoreState: Km stored state.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
//VOID Hv_Drv_Hdcp2x_DpSetKmStoreStat(UINT32 KmStoreState, UCHAR8 ucPortIndex);

/**
 * @brief Set Hdcp2x State.
 * @param[in] Hdcp2xRxState: Hdcp2x state.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_DpRxAuthStart(UCHAR8 ucPortIndex, UCHAR8 ucHdcpPortIndex);


/**
 * @brief Reset Hdcp Rx Auth state.
 * @param[in] ucPortIndex: Port index.
 * @return None.
 */
//VOID Hv_Drv_Hdcp2x_ResetAuthStat(UCHAR8 ucPortIndex, HdcpPortType enPortType);

/**
 * @brief Reset Link Integrity Failure state.
 * @param[in] None.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_DpResetLinkIntegrityFailure(UCHAR8 ucPortIndex);

/**
 * @brief Reset Link Integrity Failure state.
 * @param[in] None.
 * @return None.
 */
VOID Hv_Drv_Hdcp2x_HdmiResetLinkIntegrityFailure(UCHAR8 ucPortIndex);

/**
 * @brief Hdcp select for dp and hdmi.
 * @param[in] ucPortIndex: Port index.
 * @param[in] enPortType: Port Type DP/HDMI.
 * @return None.
 */
VOID Hv_Drv_Hdcp_InitSel(UCHAR8 ucHdcpPortIndex, UCHAR8 ucValueSet);

/**
 * @brief Set Hdcp Lane Clk.
 * @param[in] ucPortIndex: Dp Port Index.
 * @param[in] ucHdcpPortIndex: Hdcp Port Index.
 * @param[in] enPortType: Port Type DP or Hdmi.
 * @return None.
 */
VOID Hv_Drv_Hdcp_SetLaneClk(UCHAR8 ucValueSet, UCHAR8 ucHdcpPortIndex);

/**
 * @brief Update Stream Type.
 * @param[in] enPortType: Port Type DP or Hdmi.
 * @param[in] ucPortIndex: Dp Port Index.
 * @return HV_SUCCESS or HV_FAILURE.
 */
VOID Hv_Drv_Hdcp2x_HdmiSetRxStatSize(USHORT16 usMsgSize, UCHAR8 ucPortIndex);

/**
 * @brief Check Hdcp exist.
 * @param[in] ucPortIndex: Hdcp Port Index.
 * @return HV_SUCCESS or HV_FAILURE.
 */
Status Hv_Drv_Hdcp_CheckExist(UCHAR8 ucPortIndex);

/**
 * @brief Reset HDCP.
 * @param[in] ucHdcpPortIndex: HDCP Port Index.
 * @return None.
 */
VOID Hv_Drv_Hdcp_Reset(UCHAR8 ucHdcpPortIndex);

/**
 * @brief HDCP1X clear dp fifo.
 * @param[in] ucHdcpPortIndex: HDCP Port Index.
 * @return None.
 */
VOID Hv_Drv_Hdcp1X_ClrDpFifo(UCHAR8 ucHdcpPortIndex);

/**
 * @brief HDCP2X clear dp fifo.
 * @param[in] ucHdcpPortIndex: HDCP Port Index.
 * @return None.
 */
VOID Hv_Drv_Hdcp2X_ClrDpFifo(UCHAR8 ucHdcpPortIndex);

//Status Hv_Drv_Hdcp_DpIsrHandler(UINT32 uiIrqMask, HdcpVersion enVersion);
VOID Hv_Drv_Hdcp2x_HdmiSetRxMsgToReg(UCHAR8 *pucData, USHORT16 usMsgSize, UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp1x_HdmiGetRxAksvFromReg(UCHAR8 *pucAKsv, UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp1x_HdmiGetRxAnFromReg(UCHAR8 *pucAn, UCHAR8 ucPortIndex);
Status Hv_Drv_Hdcp_LoadLc128(const UCHAR8 *pucLc128);
Status Hv_Drv_Hdcp_LoadPrivateKey(Hdcp2xRxMmult* pstmmult, const HDCP2X_RX_KPriv *PrivateKey);
VOID Hv_Drv_Hdcp_HdmiSaveBksvtoReg(const UCHAR8 *pucBKsv, UCHAR8 ucPortIndex);
Status Hv_Drv_Hdcp_LoadDKSTable(UCHAR8 *pucDKS);
VOID Hv_Drv_Hdcp_DpMuxSel(UCHAR8 ucPortIndex, UCHAR8 ucHdcpPortIndex);
VOID Hv_Drv_Hdcp_HdmiMuxSel(UCHAR8 ucPortIndex, UCHAR8 ucHdcpPortIndex);
VOID Hv_Drv_Hdcp2x_RxSaveKsRivToReg(const UCHAR8* pucKs, const UCHAR8* pucRiv, UCHAR8 ucHdcpPortIndex);
VOID Hv_Drv_Hdcp2x_StartRxAuth(UCHAR8 ucHdcpPortIndex);
VOID Hv_Drv_Hdcp2x_HdmiStartRxAuthCallBack(UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp_DpCommInit();
VOID Hv_Drv_Hdcp2x_SetDpHdcpVersion(UCHAR8 ucHdcpVersion);
VOID Hv_Drv_Hdcp_DpLoadPublicCert(const UCHAR8 *pucPubCert, UCHAR8 ucPortIndex);
VOID Hv_Drv_Hdcp_DpSaveBksvtoReg(const UCHAR8 *pucBKsv, UCHAR8 ucPortIndex);

/*******************Hdcp 2x Function End***********************************/



#endif