hv_drv_Flash.c 141 KB

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  1. /**
  2. * @file hv_drv_Flash.c
  3. * @brief flash driver api layer file.
  4. * @details This file provides the following functions: \n
  5. * (1) flash write\n
  6. * (2) flash read\n
  7. * (3) flash init \n
  8. *
  9. * @author HiView SoC Software Team
  10. * @version 1.0.0
  11. * @date 2023-05-11
  12. * @copyright Copyright(c),2023-5, Hiview Software. All rights reserved.
  13. * @par History:
  14. * <table>
  15. * <tr><th>Author <th>Date <th>Change Description
  16. * <tr><td>HiView SoC Software Team <td>2023-05-11 <td>init
  17. * </table>
  18. */
  19. #include "Common/hv_comm_DataType.h"
  20. #include "hv_comm_Define.h"
  21. #include "hv_cal_Dma.h"
  22. #include "hv_cal_Qspi.h"
  23. #include "hv_drv_FlashDB.h"
  24. #include "hv_chip_Config.h"
  25. #include "hv_vos_Comm.h"
  26. #include "hv_vos_Cache.h"
  27. #include "hv_drv_Eeprom.h"
  28. #include "hv_drv_Flash.h"
  29. #include "hv_comm_FlashConfig.h"
  30. #define SECTOR_SIZE (4*1024) //4KB
  31. #define ERASE_TYPE FLASH_ERASE_SECTOR
  32. #define ERASE_TYPE_SIZE SECTOR_SIZE
  33. #define PAGE_WRITE 256
  34. #define PAGE_READ 256
  35. #define FLASH_BUSY_FLAG 0x01
  36. #define FLASH_WAIT_INFINITE 0xFFFFFFFF
  37. #define FLASH_TIMEOUT 1000
  38. #define FLASH_WAITBUSY_TIMEOUT 1000
  39. #define FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT 20000
  40. #define FLASH_ERASECHIP_WAITBUSY_TIMEOUT 120000000
  41. struct _FlashSelf
  42. {
  43. QspiSelf* pstQspi;
  44. /*!< Flash Init parameters. */
  45. FlashInitParam InitParam;
  46. FlashAttribute flashAttr;
  47. UINT32 uiFlashID;
  48. };
  49. static FlashSelf g_stFlash;
  50. static FlashSelf* g_pFlash = NULL;
  51. static UCHAR8 g_ucReadBuf[PAGE_READ] = {0};
  52. static UCHAR8 g_ucSectorBuf[SECTOR_SIZE] = {0};
  53. static UCHAR8 g_ucWriteBuf[PAGE_WRITE] = {0};
  54. static UCHAR8 g_ucDmaUseFlag = HV_FALSE;
  55. static UCHAR8 g_ucIntUseFlag = HV_FALSE;
  56. static HV_VOS_SEMAPHORE_S *g_pstFlashSeamphone = NULL;
  57. static void Flash_OnlyRead(UINT32 uiReadAddr, UCHAR8* pucReadBuf, UINT32 uiLength);
  58. static Status Flash_Check(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength);
  59. static Status Flash_OnlyWrite(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength);
  60. static void Flash_CpltCallBack(FlashTransRW enTransType, void *pArg)
  61. {
  62. QspiSelf* pstQspi = (QspiSelf*)pArg;
  63. FlashSelf* pstFlash = (FlashSelf*)Hv_Cal_Qspi_GetFlashPoint(pstQspi);
  64. pstFlash->InitParam.FlashCpltCallback(enTransType, pstFlash);
  65. return;
  66. }
  67. static void Flash_SetCommonBaudRate(QspiInitParam* pstQspiInitParam, FlashInitParam *pstFlashInitParam)
  68. {
  69. if (pstFlashInitParam->RateMode == FLASH_STANDARD)
  70. {
  71. if (pstFlashInitParam->DataSize == FLASH_DATAWIDTH_8)
  72. {
  73. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_64;
  74. }
  75. else if (pstFlashInitParam->DataSize == FLASH_DATAWIDTH_16)
  76. {
  77. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_64;
  78. }
  79. else if (pstFlashInitParam->DataSize == FLASH_DATAWIDTH_32)
  80. {
  81. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_32;
  82. }
  83. }
  84. else if (pstFlashInitParam->RateMode == FLASH_DUAL)
  85. {
  86. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_256;
  87. }
  88. else if (pstFlashInitParam->RateMode == FLASH_QUAD)
  89. {
  90. pstQspiInitParam->BaudRatePrescaler = QSPI_DIVRATIO_256;
  91. }
  92. return;
  93. }
  94. static void Flash_SetDmaBaudRate(FlashSelf* pstFlash)
  95. {
  96. QspiSelf* pstQspi = pstFlash->pstQspi;
  97. FlashInitParam* InitParam = &pstFlash->InitParam;
  98. QspiDivideRatio qspiBaudDiv = QSPI_DIVRATIO_4;
  99. if (InitParam->RateMode == FLASH_STANDARD)
  100. {
  101. if (InitParam->DataSize == FLASH_DATAWIDTH_8)
  102. {
  103. qspiBaudDiv = QSPI_DIVRATIO_16;
  104. }
  105. else if (InitParam->DataSize == FLASH_DATAWIDTH_32)
  106. {
  107. qspiBaudDiv = QSPI_DIVRATIO_8;
  108. }
  109. }
  110. else if (InitParam->RateMode == FLASH_DUAL)
  111. {
  112. if (InitParam->DataSize == FLASH_DATAWIDTH_8)
  113. {
  114. qspiBaudDiv = QSPI_DIVRATIO_128;
  115. }
  116. else if (InitParam->DataSize == FLASH_DATAWIDTH_32)
  117. {
  118. qspiBaudDiv = QSPI_DIVRATIO_128;
  119. }
  120. }
  121. else if (InitParam->RateMode == FLASH_QUAD)
  122. {
  123. if (InitParam->DataSize == FLASH_DATAWIDTH_8)
  124. {
  125. qspiBaudDiv = QSPI_DIVRATIO_256;
  126. }
  127. else if (InitParam->DataSize == FLASH_DATAWIDTH_32)
  128. {
  129. qspiBaudDiv = QSPI_DIVRATIO_256;
  130. }
  131. }
  132. Hv_Cal_Qspi_SetBaudRate(pstQspi,qspiBaudDiv);
  133. return;
  134. }
  135. static void Flash_WriteEnable(FlashSelf* pstFlash)
  136. {
  137. QspiSelf* pstQspi = pstFlash->pstQspi;
  138. UCHAR8 ucWtEnableCmd = pstFlash->flashAttr.FlashWriteEnCmd;
  139. UINT32 uiLoop = 0;
  140. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  141. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  142. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  143. {
  144. Hv_Cal_Qspi_PollingWrite(pstQspi, &ucWtEnableCmd, 1, NULL, 0, FLASH_TIMEOUT);
  145. }
  146. else if (pstFlash->InitParam.RateMode == FLASH_DUAL || pstFlash->InitParam.RateMode == FLASH_QUAD)
  147. {
  148. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  149. {
  150. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  151. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  152. }
  153. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  154. {
  155. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,
  156. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  157. }
  158. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  159. {
  160. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_MULTI,
  161. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  162. }
  163. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &ucWtEnableCmd, 1, NULL, 0, FLASH_TIMEOUT);
  164. }
  165. for (uiLoop=0;uiLoop<2000;uiLoop++);
  166. return;
  167. }
  168. /************************************* Wait busy static API ********************************************/
  169. static Status Flash_ReadBusyFlagStandard(FlashSelf * pstFlash, UINT64 timeout)
  170. {
  171. QspiSelf* pstQspi = pstFlash->pstQspi;
  172. UINT64 tickstart = 0;
  173. UCHAR8 aucRdState[2] = {0xff, 0xff};
  174. UCHAR8 aucStateCmd[2] = {pstFlash->flashAttr.FlashReadStatusCmd, 0x00};
  175. tickstart = Hv_Vos_GetTick();
  176. while ((UCHAR8)((aucRdState[1] & FLASH_BUSY_FLAG)) != 0)
  177. {
  178. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  179. if ((timeout != FLASH_WAIT_INFINITE))
  180. {
  181. if ((Hv_Vos_GetTick() - tickstart ) > timeout)
  182. {
  183. HV_LOGI("Flash busy until timeout.\n");
  184. return HV_TIMEOUT;
  185. }
  186. }
  187. }
  188. return HV_SUCCESS;
  189. }
  190. static Status Flash_ReadBusyFlagMultiIo(FlashSelf * pstFlash, UINT64 timeout)
  191. {
  192. QspiSelf* pstQspi = pstFlash->pstQspi;
  193. UINT64 tickstart = 0;
  194. UCHAR8 ucRdState = 0xff;
  195. UCHAR8 ucStateCmd = pstFlash->flashAttr.FlashReadStatusCmd;
  196. tickstart = Hv_Vos_GetTick();
  197. while ((UCHAR8)((ucRdState & FLASH_BUSY_FLAG)) != 0)
  198. {
  199. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, &ucStateCmd, 1, &ucRdState, 1, FLASH_TIMEOUT);
  200. if ((timeout != FLASH_WAIT_INFINITE))
  201. {
  202. if ((Hv_Vos_GetTick() - tickstart ) > timeout)
  203. {
  204. HV_LOGI("Flash busy until timeout.\n");
  205. return HV_TIMEOUT;
  206. }
  207. }
  208. }
  209. return HV_SUCCESS;
  210. }
  211. static void Flash_WaitBusy(FlashSelf* pstFlash, UINT64 Timeout)
  212. {
  213. QspiSelf* pstQspi = pstFlash->pstQspi;
  214. QspiState enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  215. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  216. {
  217. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  218. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  219. Flash_ReadBusyFlagStandard(pstFlash, Timeout);
  220. }
  221. else if (pstFlash->InitParam.RateMode == FLASH_DUAL
  222. || pstFlash->InitParam.RateMode == FLASH_QUAD)
  223. {
  224. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  225. {
  226. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  227. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  228. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  229. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  230. Hv_Cal_Qspi_SetReadNumber(pstQspi, 1);
  231. Flash_ReadBusyFlagMultiIo(pstFlash, Timeout);
  232. }
  233. else if ((pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  234. ||(pstFlash->InitParam.TransType == FLASH_ADDR_4LINE))
  235. {
  236. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  237. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  238. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  239. Flash_ReadBusyFlagStandard(pstFlash,Timeout);
  240. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  241. }
  242. }
  243. return;
  244. }
  245. /************************************* Wait busy static API end*******************************************/
  246. /**************************************Read ID static function*******************************************/
  247. static UINT32 Flash_ReadID_Standard(FlashSelf* pstFlash)
  248. {
  249. QspiSelf* pstQspi = pstFlash->pstQspi;
  250. UCHAR8 aucReadID[4] = {0};
  251. UINT32 uiFlashID = 0;
  252. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  253. {
  254. UCHAR8 ucIdCmd = pstFlash->flashAttr.FlashReadIdStandardCmd;
  255. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  256. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  257. Hv_Cal_Qspi_PollingRead(pstQspi, &ucIdCmd, 1, aucReadID, 3, FLASH_TIMEOUT);
  258. uiFlashID = ( (((UINT32)aucReadID[0]) << 16) | ((UINT32)aucReadID[1] << 8) | ((UINT32)aucReadID[2]));
  259. }
  260. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  261. {
  262. UCHAR8 aucIdCmd[4]={pstFlash->flashAttr.FlashReadIdStandardCmd,0x00,0x00,0x00};
  263. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  264. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  265. Hv_Cal_Qspi_PollingRead(pstQspi, aucIdCmd, 4, aucReadID, 0, FLASH_TIMEOUT);
  266. uiFlashID = ( (((UINT32)aucReadID[1]) << 16) | ((UINT32)aucReadID[2] << 8) | ((UINT32)aucReadID[3]));
  267. }
  268. return uiFlashID;
  269. }
  270. static UINT32 Flash_ReadID_MutiIO(FlashSelf* pstFlash)
  271. {
  272. QspiSelf* pstQspi = pstFlash->pstQspi;
  273. UCHAR8 ucIdCmd = pstFlash->flashAttr.FlashReadIdMultiIoCmd;
  274. UCHAR8 aucReadID[4] = {0};
  275. UINT32 uiFlashID = 0;
  276. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  277. {
  278. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  279. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  280. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  281. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  282. Hv_Cal_Qspi_SetReadNumber(pstQspi, 3);
  283. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, &ucIdCmd, 1, aucReadID, 3, FLASH_TIMEOUT);
  284. uiFlashID = (((UINT32)aucReadID[0] << 16) | ((UINT32)aucReadID[1] << 8) | ((UINT32)aucReadID[2]) );
  285. }
  286. else if ((pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  287. ||(pstFlash->InitParam.TransType == FLASH_ADDR_4LINE))
  288. {
  289. QspiState enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  290. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  291. uiFlashID = Flash_ReadID_Standard(pstFlash);
  292. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  293. return uiFlashID;
  294. }
  295. return uiFlashID;
  296. }
  297. /**************************************Read ID static function end****************************************/
  298. /**************************************Erase static function**********************************************/
  299. static Status Flash_EraseStandard(FlashSelf* pstFlash, FlashEraseType enEraseType, UINT32 uiEraseAddr)
  300. {
  301. QspiSelf* pstQspi = pstFlash->pstQspi;
  302. UCHAR8 eraseSector[5] = {0};
  303. UCHAR8 eraseChip = 0;
  304. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  305. Flash_WriteEnable(pstFlash);
  306. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  307. {
  308. if (enEraseType == FLASH_ERASE_SECTOR)
  309. {
  310. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd;
  311. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  312. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  313. eraseSector[3] = (UCHAR8) uiEraseAddr;
  314. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  315. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  316. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  317. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  318. }
  319. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  320. {
  321. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd;
  322. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  323. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  324. eraseSector[3] = (UCHAR8) uiEraseAddr;
  325. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  326. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  327. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  328. Flash_WaitBusy(pstFlash,FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT);
  329. }
  330. else if (enEraseType == FLASH_ERASE_CHIP)
  331. {
  332. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  333. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  334. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  335. Hv_Cal_Qspi_PollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  336. Flash_WaitBusy(pstFlash,FLASH_ERASECHIP_WAITBUSY_TIMEOUT);
  337. }
  338. }
  339. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  340. {
  341. if (enEraseType == FLASH_ERASE_SECTOR)
  342. {
  343. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd_4ByteAddr;
  344. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  345. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  346. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  347. eraseSector[4] = (UCHAR8) uiEraseAddr;
  348. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  349. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  350. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  351. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  352. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  353. }
  354. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  355. {
  356. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd_4ByteAddr;
  357. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  358. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  359. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  360. eraseSector[4] = (UCHAR8) uiEraseAddr;
  361. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  362. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  363. Hv_Cal_Qspi_PollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  364. Flash_WaitBusy(pstFlash,FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT);
  365. }
  366. else if (enEraseType == FLASH_ERASE_CHIP)
  367. {
  368. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  369. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  370. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  371. Hv_Cal_Qspi_PollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  372. Flash_WaitBusy(pstFlash,FLASH_ERASECHIP_WAITBUSY_TIMEOUT);
  373. }
  374. }
  375. Hv_Vos_MSleep(pstFlash->flashAttr.FlashEraseCompltWait);
  376. return HV_SUCCESS;
  377. }
  378. static Status Flash_EraseMultiIo(FlashSelf* pstFlash, FlashEraseType enEraseType, UINT32 uiEraseAddr)
  379. {
  380. QspiSelf* pstQspi = pstFlash->pstQspi;
  381. UCHAR8 eraseSector[5] = {0};
  382. UCHAR8 eraseChip = 0;
  383. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  384. {
  385. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  386. Flash_WriteEnable(pstFlash);
  387. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  388. {
  389. if (enEraseType == FLASH_ERASE_SECTOR)
  390. {
  391. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd;
  392. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  393. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  394. eraseSector[3] = (UCHAR8) uiEraseAddr;
  395. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  396. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  397. }
  398. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  399. {
  400. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd;
  401. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 16);
  402. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 8);
  403. eraseSector[3] = (UCHAR8) uiEraseAddr;
  404. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  405. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 4, NULL, 0, FLASH_TIMEOUT);
  406. }
  407. else if (enEraseType == FLASH_ERASE_CHIP)
  408. {
  409. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  410. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  411. }
  412. }
  413. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  414. {
  415. if (enEraseType == FLASH_ERASE_SECTOR)
  416. {
  417. eraseSector[0] = pstFlash->flashAttr.FlashSectionEraseCmd_4ByteAddr;
  418. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  419. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  420. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  421. eraseSector[4] = (UCHAR8) uiEraseAddr;
  422. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  423. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  424. }
  425. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  426. {
  427. eraseSector[0] = pstFlash->flashAttr.FlashMultiSectionEraseCmd_4ByteAddr;
  428. eraseSector[1] = (UCHAR8)((uiEraseAddr) >> 24);
  429. eraseSector[2] = (UCHAR8)((uiEraseAddr) >> 16);
  430. eraseSector[3] = (UCHAR8)((uiEraseAddr) >> 8);
  431. eraseSector[4] = (UCHAR8) uiEraseAddr;
  432. Hv_Cal_Qspi_SetBaudRate(pstQspi,QSPI_DIVRATIO_256);
  433. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, eraseSector, 5, NULL, 0, FLASH_TIMEOUT);
  434. }
  435. else if (enEraseType == FLASH_ERASE_CHIP)
  436. {
  437. eraseChip = pstFlash->flashAttr.FlashChipEraseCmd;
  438. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &eraseChip, 1, NULL, 0, FLASH_TIMEOUT);
  439. }
  440. }
  441. if (enEraseType == FLASH_ERASE_SECTOR)
  442. {
  443. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  444. }
  445. else if (enEraseType == FLASH_ERASE_MULTI_SECTOR)
  446. {
  447. Flash_WaitBusy(pstFlash,FLASH_ERASE_MULTI_SECTOR_WAITBUSY_TIMEOUT);
  448. }
  449. else if (enEraseType == FLASH_ERASE_CHIP)
  450. {
  451. Flash_WaitBusy(pstFlash,FLASH_ERASECHIP_WAITBUSY_TIMEOUT);
  452. }
  453. Hv_Vos_MSleep(pstFlash->flashAttr.FlashEraseCompltWait);
  454. }
  455. else if ((pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  456. ||(pstFlash->InitParam.TransType == FLASH_ADDR_4LINE))
  457. {
  458. QspiRateMode enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  459. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  460. Flash_EraseStandard(pstFlash,enEraseType,uiEraseAddr);
  461. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  462. }
  463. return HV_SUCCESS;
  464. }
  465. /**************************************Erase static function end********************************************/
  466. /************************************************ Standard API *********************************************/
  467. static Status Flash_SendStandard(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  468. {
  469. QspiSelf* pstQspi = pstFlash->pstQspi;
  470. UCHAR8 aucCmdAddr[8] = {0};
  471. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  472. {
  473. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  474. {
  475. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  476. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  477. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  478. aucCmdAddr[3] = uiWtAddr & 0xff;
  479. }
  480. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  481. {
  482. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd_4ByteAddr;
  483. aucCmdAddr[1] = (uiWtAddr >> 24) & 0xff;
  484. aucCmdAddr[2] = (uiWtAddr >> 16) & 0xff;
  485. aucCmdAddr[3] = (uiWtAddr >> 8) & 0xff;
  486. aucCmdAddr[4] = uiWtAddr & 0xff;
  487. }
  488. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  489. Flash_WriteEnable(pstFlash);
  490. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  491. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  492. {
  493. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize, FLASH_TIMEOUT);
  494. }
  495. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  496. {
  497. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 5, pucTxData, uiTxSize, FLASH_TIMEOUT);
  498. }
  499. }
  500. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_16)
  501. {
  502. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  503. {
  504. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  505. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  506. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  507. aucCmdAddr[3] = uiWtAddr & 0xff;
  508. }
  509. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  510. {
  511. HV_ASSERT(0);
  512. }
  513. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  514. Flash_WriteEnable(pstFlash);
  515. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  516. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize, FLASH_TIMEOUT);
  517. }
  518. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  519. {
  520. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  521. {
  522. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  523. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  524. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  525. aucCmdAddr[3] = uiWtAddr & 0xff;
  526. }
  527. else
  528. {
  529. HV_ASSERT(0);
  530. }
  531. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  532. Flash_WriteEnable(pstFlash);
  533. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  534. Hv_Cal_Qspi_PollingWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize, FLASH_TIMEOUT);
  535. }
  536. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  537. return HV_SUCCESS;
  538. }
  539. static Status Flash_RecvStandard(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  540. {
  541. QspiSelf* pstQspi = pstFlash->pstQspi;
  542. UCHAR8 aucCmdAddr[8] = {0};
  543. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  544. {
  545. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  546. {
  547. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  548. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  549. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  550. aucCmdAddr[3] = uiRdAddr & 0xff;
  551. }
  552. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  553. {
  554. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd_4ByteAddr;
  555. aucCmdAddr[1] = (uiRdAddr >> 24) & 0xff;
  556. aucCmdAddr[2] = (uiRdAddr >> 16) & 0xff;
  557. aucCmdAddr[3] = (uiRdAddr >> 8) & 0xff;
  558. aucCmdAddr[4] = uiRdAddr & 0xff;
  559. }
  560. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  561. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  562. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  563. {
  564. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize, FLASH_TIMEOUT);
  565. }
  566. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  567. {
  568. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 5, pucRxData, uiRxSize, FLASH_TIMEOUT);
  569. }
  570. }
  571. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_16)
  572. {
  573. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  574. {
  575. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  576. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  577. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  578. aucCmdAddr[3] = uiRdAddr & 0xff;
  579. }
  580. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  581. {
  582. HV_ASSERT(0);
  583. }
  584. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  585. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  586. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize, FLASH_TIMEOUT);
  587. }
  588. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  589. {
  590. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  591. {
  592. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  593. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  594. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  595. aucCmdAddr[3] = uiRdAddr & 0xff;
  596. }
  597. else
  598. {
  599. HV_ASSERT(0);
  600. }
  601. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  602. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  603. Hv_Cal_Qspi_PollingRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize,FLASH_TIMEOUT);
  604. }
  605. return HV_SUCCESS;
  606. }
  607. static Status Flash_SendStandardInt(FlashSelf* pstFlash,UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  608. {
  609. QspiSelf* pstQspi = pstFlash->pstQspi;
  610. UCHAR8 aucCmdAddr[8] = {0};
  611. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  612. {
  613. HV_LOGI("Standard Int send just support 32bits DataWidth.\n");
  614. HV_ASSERT(0);
  615. }
  616. aucCmdAddr[0] = pstFlash->flashAttr.FlashProgStandardCmd;
  617. aucCmdAddr[1] = (uiWtAddr >> 16) & 0xff;
  618. aucCmdAddr[2] = (uiWtAddr >> 8) & 0xff;
  619. aucCmdAddr[3] = uiWtAddr & 0xff;
  620. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  621. Flash_WriteEnable(pstFlash);
  622. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  623. Hv_Cal_Qspi_IntWrite(pstQspi, aucCmdAddr, 4, pucTxData, uiTxSize);
  624. return HV_SUCCESS;
  625. }
  626. static Status Flash_RecvStandardInt(FlashSelf* pstFlash,UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  627. {
  628. QspiSelf* pstQspi = pstFlash->pstQspi;
  629. UCHAR8 aucCmdAddr[8] = {0};
  630. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  631. {
  632. HV_LOGI("Standard Int receive just support 32bits DataWidth.\n");
  633. HV_ASSERT(0);
  634. }
  635. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  636. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  637. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  638. aucCmdAddr[3] = uiRdAddr & 0xff;
  639. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  640. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  641. Hv_Cal_Qspi_IntRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize);
  642. return HV_SUCCESS;
  643. }
  644. static Status Flash_SendStandardDma(FlashSelf* pstFlash,UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  645. {
  646. QspiSelf* pstQspi = pstFlash->pstQspi;
  647. FlashTxMem* TxDataDma = NULL;
  648. TxDataDma = (FlashTxMem*) (pucTxData - 20);
  649. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  650. {
  651. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  652. {
  653. TxDataDma->cmdAddr[16] = pstFlash->flashAttr.FlashProgStandardCmd;
  654. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  655. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  656. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  657. }
  658. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  659. {
  660. TxDataDma->cmdAddr[15] = pstFlash->flashAttr.FlashProgStandardCmd;
  661. TxDataDma->cmdAddr[16] = (uiWtAddr >> 24) & 0xff;
  662. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  663. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  664. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  665. }
  666. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  667. Flash_WriteEnable(pstFlash);
  668. Flash_SetDmaBaudRate(pstFlash);
  669. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  670. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  671. {
  672. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  673. }
  674. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  675. {
  676. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[15], uiTxSize + 5);
  677. }
  678. }
  679. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  680. {
  681. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  682. {
  683. TxDataDma->cmdAddr[16] = uiWtAddr & 0xff;
  684. TxDataDma->cmdAddr[17] = (uiWtAddr >> 8) & 0xff;
  685. TxDataDma->cmdAddr[18] = (uiWtAddr >> 16) & 0xff;
  686. TxDataDma->cmdAddr[19] = pstFlash->flashAttr.FlashProgStandardCmd;
  687. }
  688. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  689. {
  690. HV_ASSERT(0);
  691. }
  692. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  693. Flash_WriteEnable(pstFlash);
  694. Flash_SetDmaBaudRate(pstFlash);
  695. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  696. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  697. }
  698. return HV_SUCCESS;
  699. }
  700. static Status Flash_RecvStandardDma(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  701. {
  702. QspiSelf* pstQspi = pstFlash->pstQspi;
  703. static UCHAR8 g_aucCmdAddrBuf[1029];
  704. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  705. {
  706. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  707. {
  708. g_aucCmdAddrBuf[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  709. g_aucCmdAddrBuf[1] = (uiRdAddr >> 16) & 0xff;
  710. g_aucCmdAddrBuf[2] = (uiRdAddr >> 8) & 0xff;
  711. g_aucCmdAddrBuf[3] = uiRdAddr & 0xff;
  712. }
  713. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  714. {
  715. g_aucCmdAddrBuf[0] = pstFlash->flashAttr.FlashReadStandardCmd;
  716. g_aucCmdAddrBuf[1] = (uiRdAddr >> 24) & 0xff;
  717. g_aucCmdAddrBuf[2] = (uiRdAddr >> 16) & 0xff;
  718. g_aucCmdAddrBuf[3] = (uiRdAddr >> 8) & 0xff;
  719. g_aucCmdAddrBuf[4] = uiRdAddr & 0xff;
  720. }
  721. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  722. Flash_SetDmaBaudRate(pstFlash);
  723. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  724. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  725. {
  726. Hv_Cal_Qspi_DmaRead(pstQspi, g_aucCmdAddrBuf, 4, pucRxData, uiRxSize);
  727. }
  728. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  729. {
  730. Hv_Cal_Qspi_DmaRead(pstQspi, g_aucCmdAddrBuf, 5, pucRxData, uiRxSize);
  731. }
  732. }
  733. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  734. {
  735. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  736. {
  737. g_aucCmdAddrBuf[0] = uiRdAddr & 0xff;
  738. g_aucCmdAddrBuf[1] = (uiRdAddr >> 8) & 0xff;
  739. g_aucCmdAddrBuf[2] = (uiRdAddr >> 16) & 0xff;
  740. g_aucCmdAddrBuf[3] = pstFlash->flashAttr.FlashReadStandardCmd;
  741. }
  742. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  743. {
  744. HV_ASSERT(0);
  745. }
  746. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  747. Flash_SetDmaBaudRate(pstFlash);
  748. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  749. Hv_Cal_Qspi_DmaRead(pstQspi, g_aucCmdAddrBuf, 4, pucRxData, uiRxSize);
  750. }
  751. return HV_SUCCESS;
  752. }
  753. /************************************************ Standard API end******************************************/
  754. /*************************************************Dual API**************************************************/
  755. static Status Flash_SendDual(FlashSelf* pstFlash, UINT32 uiWtAddr,
  756. UCHAR8* pucTxData, UINT32 uiTxSize)
  757. {
  758. QspiSelf* pstQspi = pstFlash->pstQspi;
  759. UCHAR8 aucCmdAddr[8] = {0};
  760. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  761. {
  762. HV_LOGI("Dual Polling just support 32bits DataWidth.\n");
  763. HV_ASSERT(0);
  764. }
  765. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  766. {
  767. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  768. aucCmdAddr[4] = 0;
  769. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  770. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  771. aucCmdAddr[7] = uiWtAddr & 0xff;
  772. }
  773. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  774. {
  775. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  776. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  777. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  778. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  779. aucCmdAddr[7] = uiWtAddr & 0xff;
  780. }
  781. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  782. Flash_WriteEnable(pstFlash);
  783. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  784. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  785. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  786. {
  787. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  788. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  789. }
  790. else
  791. {
  792. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  793. pstFlash->InitParam.AddrWidth, 0);
  794. }
  795. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize, FLASH_TIMEOUT);
  796. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  797. return HV_SUCCESS;
  798. }
  799. static Status Flash_RecvDual(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  800. {
  801. QspiSelf* pstQspi = pstFlash->pstQspi;
  802. UCHAR8 aucCmdAddr[8] = {0};
  803. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  804. {
  805. HV_LOGI("Dual Polling just support 32bits DataWidth.\n");
  806. HV_ASSERT(0);
  807. }
  808. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  809. {
  810. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  811. aucCmdAddr[4] = 0;
  812. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  813. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  814. aucCmdAddr[7] = uiRdAddr & 0xff;
  815. }
  816. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  817. {
  818. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  819. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  820. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  821. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  822. aucCmdAddr[7] = uiRdAddr & 0xff;
  823. }
  824. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  825. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  826. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  827. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  828. {
  829. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  830. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastDual);
  831. }
  832. else
  833. {
  834. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  835. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleDual);
  836. }
  837. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  838. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize, FLASH_TIMEOUT);
  839. return HV_SUCCESS;
  840. }
  841. static Status Flash_SendDualInt(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  842. {
  843. QspiSelf* pstQspi = pstFlash->pstQspi;
  844. UCHAR8 aucCmdAddr[8] = {0};
  845. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  846. {
  847. HV_LOGI("Dual Int send just support 32bits DataWidth.\n");
  848. HV_ASSERT(0);
  849. }
  850. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  851. {
  852. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  853. aucCmdAddr[4] = 0;
  854. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  855. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  856. aucCmdAddr[7] = uiWtAddr & 0xff;
  857. }
  858. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  859. {
  860. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgDualCmd;
  861. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  862. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  863. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  864. aucCmdAddr[7] = uiWtAddr & 0xff;
  865. }
  866. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  867. Flash_WriteEnable(pstFlash);
  868. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  869. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  870. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  871. {
  872. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  873. pstFlash->InitParam.AddrWidth, 0);
  874. }
  875. else
  876. {
  877. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  878. pstFlash->InitParam.AddrWidth, 0);
  879. }
  880. Hv_Cal_Qspi_IntWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize);
  881. return HV_SUCCESS;
  882. }
  883. static Status Flash_RecvDualInt(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  884. {
  885. QspiSelf* pstQspi = pstFlash->pstQspi;
  886. UCHAR8 aucCmdAddr[8] = {0};
  887. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  888. {
  889. HV_LOGI("Dual Int receive just support 32bits DataWidth.\n");
  890. HV_ASSERT(0);
  891. }
  892. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  893. {
  894. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  895. aucCmdAddr[4] = 0;
  896. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  897. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  898. aucCmdAddr[7] = uiRdAddr & 0xff;
  899. }
  900. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  901. {
  902. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadDualCmd;
  903. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  904. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  905. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  906. aucCmdAddr[7] = uiRdAddr & 0xff;
  907. }
  908. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  909. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  910. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  911. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  912. {
  913. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND, pstFlash->flashAttr.FlashInstruWidth,
  914. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastDual);
  915. }
  916. else
  917. {
  918. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  919. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleDual);
  920. }
  921. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  922. Hv_Cal_Qspi_IntRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize);
  923. return HV_SUCCESS;
  924. }
  925. static Status Flash_SendDualDma(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  926. {
  927. QspiSelf* pstQspi = pstFlash->pstQspi;
  928. FlashTxMem* TxDataDma = NULL;
  929. UINT32 uiWtCmdTemp = 0;
  930. UINT64 wtAddrTemp = 0;
  931. UINT32 uiLoop = 0;
  932. TxDataDma = (FlashTxMem*) (pucTxData - 20);
  933. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  934. {
  935. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  936. {
  937. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  938. {
  939. TxDataDma->cmdAddr[16] = pstFlash->flashAttr.FlashProgDualCmd;
  940. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  941. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  942. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  943. }
  944. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  945. {
  946. for (uiLoop = 0;uiLoop < 24;uiLoop++ )
  947. {
  948. if (uiLoop < 8)
  949. {
  950. uiWtCmdTemp |= ((UINT32)(pstFlash->flashAttr.FlashProgDualCmd & (1 << uiLoop))) << uiLoop;
  951. uiWtCmdTemp |= ((UINT32)((1 << uiLoop))) << (uiLoop+1);
  952. }
  953. wtAddrTemp |= ((UINT64)(uiWtAddr & (1 << uiLoop))) << uiLoop;
  954. wtAddrTemp |= ((UINT64)((1 << uiLoop))) << (uiLoop+1);
  955. }
  956. TxDataDma->cmdAddr[12] = (uiWtCmdTemp >> 8) & 0xff;
  957. TxDataDma->cmdAddr[13] = uiWtCmdTemp & 0xff;
  958. TxDataDma->cmdAddr[14] = (wtAddrTemp >> 40) & 0xff ;
  959. TxDataDma->cmdAddr[15] = (wtAddrTemp >> 32) & 0xff;
  960. TxDataDma->cmdAddr[16] = (wtAddrTemp >> 24) & 0xff;
  961. TxDataDma->cmdAddr[17] = (wtAddrTemp >> 16) & 0xff;
  962. TxDataDma->cmdAddr[18] = (wtAddrTemp >> 8) & 0xff;
  963. TxDataDma->cmdAddr[19] = wtAddrTemp & 0xff;
  964. }
  965. }
  966. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  967. {
  968. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  969. {
  970. TxDataDma->cmdAddr[15] = pstFlash->flashAttr.FlashProgDualCmd;
  971. TxDataDma->cmdAddr[16] = (uiWtAddr >> 24) & 0xff;
  972. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  973. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  974. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  975. }
  976. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  977. {
  978. HV_ASSERT(1);
  979. }
  980. }
  981. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  982. Flash_WriteEnable(pstFlash);
  983. Flash_SetDmaBaudRate(pstFlash);
  984. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  985. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  986. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  987. {
  988. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  989. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  990. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  991. {
  992. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[12], uiTxSize + 8);
  993. }
  994. }
  995. else
  996. {
  997. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  998. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  999. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1000. {
  1001. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  1002. }
  1003. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1004. {
  1005. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[15], uiTxSize + 5);
  1006. }
  1007. }
  1008. }
  1009. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1010. {
  1011. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgDualCmd;
  1012. TxDataDma->cmdAddr[13] = 0x00;
  1013. TxDataDma->cmdAddr[14] = 0x00;
  1014. TxDataDma->cmdAddr[15] = 0x00;
  1015. TxDataDma->cmdAddr[16] = uiWtAddr & 0xff;
  1016. TxDataDma->cmdAddr[17] = (uiWtAddr >> 8) & 0xff;
  1017. TxDataDma->cmdAddr[18] = (uiWtAddr >> 16) & 0xff;
  1018. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1019. {
  1020. TxDataDma->cmdAddr[19] = 0;
  1021. }
  1022. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1023. {
  1024. TxDataDma->cmdAddr[19] = (uiWtAddr >> 24) & 0xff;
  1025. }
  1026. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1027. Flash_WriteEnable(pstFlash);
  1028. Flash_SetDmaBaudRate(pstFlash);
  1029. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1030. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1031. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1032. {
  1033. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1034. pstFlash->flashAttr.FlashInstruWidth,
  1035. pstFlash->InitParam.AddrWidth, 0);
  1036. }
  1037. else
  1038. {
  1039. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1040. pstFlash->flashAttr.FlashInstruWidth,
  1041. pstFlash->InitParam.AddrWidth, 0);
  1042. }
  1043. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[12], uiTxSize + 8);
  1044. }
  1045. return HV_SUCCESS;
  1046. }
  1047. static Status Flash_RecvDualDma(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1048. {
  1049. QspiSelf* pstQspi = pstFlash->pstQspi;
  1050. UCHAR8 aucCmdAddr[8] = {0};
  1051. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadDualCmd;
  1052. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1053. {
  1054. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  1055. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  1056. aucCmdAddr[3] = uiRdAddr & 0xff;
  1057. }
  1058. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1059. {
  1060. aucCmdAddr[1] = (uiRdAddr >> 24) & 0xff;
  1061. aucCmdAddr[2] = (uiRdAddr >> 16) & 0xff;
  1062. aucCmdAddr[3] = (uiRdAddr >> 8) & 0xff;
  1063. aucCmdAddr[4] = uiRdAddr & 0xff;
  1064. }
  1065. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1066. /* Here can set different BaudDiv for different flash type, such as GD25F128 can
  1067. support up to 166MHz dual fast read mode */
  1068. if (pstFlash->InitParam.FlashModel == FLASH_GD25)
  1069. {
  1070. Hv_Cal_Qspi_SetBaudRate(pstFlash->pstQspi, QSPI_DIVRATIO_2);
  1071. }
  1072. else
  1073. {
  1074. Flash_SetDmaBaudRate(pstFlash);
  1075. }
  1076. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  1077. {
  1078. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1079. }else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1080. {
  1081. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1082. }
  1083. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1084. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1085. {
  1086. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  1087. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastDual);
  1088. }
  1089. else
  1090. {
  1091. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1092. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleDual);
  1093. }
  1094. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1095. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1096. {
  1097. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize);
  1098. }
  1099. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1100. {
  1101. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 5, pucRxData, uiRxSize);
  1102. }
  1103. return HV_SUCCESS;
  1104. }
  1105. /*************************************************Dual API end***************************************/
  1106. /**********************************************Quad API***********************************************/
  1107. static Status Flash_SendQuad(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  1108. {
  1109. QspiSelf* pstQspi = pstFlash->pstQspi;
  1110. UCHAR8 aucCmdAddr[8] = {0};
  1111. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1112. {
  1113. HV_LOGI("Quad Polling just support 32bits DataWidth.\n");
  1114. HV_ASSERT(0);
  1115. }
  1116. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1117. {
  1118. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1119. {
  1120. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd;
  1121. }
  1122. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1123. {
  1124. aucCmdAddr[3] = pstFlash->flashAttr.FlashProg4xIoCmd;
  1125. }
  1126. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1127. {
  1128. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd;
  1129. }
  1130. aucCmdAddr[4] = 0x00;
  1131. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1132. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1133. aucCmdAddr[7] = uiWtAddr & 0xff;
  1134. }
  1135. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1136. {
  1137. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1138. {
  1139. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd_4ByteAddr;
  1140. }
  1141. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1142. {
  1143. aucCmdAddr[3] = pstFlash->flashAttr.FlashProg4xIoCmd_4ByteAddr;
  1144. }
  1145. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1146. {
  1147. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd_4ByteAddr;
  1148. }
  1149. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  1150. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1151. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1152. aucCmdAddr[7] = uiWtAddr & 0xff;
  1153. }
  1154. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1155. Flash_WriteEnable(pstFlash);
  1156. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1157. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1158. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1159. {
  1160. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1161. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1162. }
  1163. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1164. {
  1165. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1166. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1167. }
  1168. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1169. {
  1170. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_MULTI,
  1171. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1172. }
  1173. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize, FLASH_TIMEOUT);
  1174. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1175. return HV_SUCCESS;
  1176. }
  1177. static Status Flash_RecvQuad(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1178. {
  1179. QspiSelf* pstQspi = pstFlash->pstQspi;
  1180. UCHAR8 aucCmdAddr[8] = {0};
  1181. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1182. {
  1183. HV_LOGI("Quad Polling just support 32bits DataWidth.\n");
  1184. HV_ASSERT(0);
  1185. }
  1186. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1187. {
  1188. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1189. {
  1190. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd;
  1191. }
  1192. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1193. {
  1194. aucCmdAddr[3] = pstFlash->flashAttr.FlashRead4xIoCmd;
  1195. }
  1196. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1197. {
  1198. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd;
  1199. }
  1200. aucCmdAddr[4] = 0x00;
  1201. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1202. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1203. aucCmdAddr[7] = uiRdAddr & 0xff;
  1204. }
  1205. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1206. {
  1207. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1208. {
  1209. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd_4ByteAddr;
  1210. }
  1211. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1212. {
  1213. aucCmdAddr[3] = pstFlash->flashAttr.FlashRead4xIoCmd_4ByteAddr;
  1214. }
  1215. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1216. {
  1217. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd_4ByteAddr;
  1218. }
  1219. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  1220. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1221. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1222. aucCmdAddr[7] = uiRdAddr & 0xff;
  1223. }
  1224. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1225. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1226. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1227. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1228. {
  1229. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  1230. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastQuad);
  1231. }
  1232. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1233. {
  1234. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1235. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleQpi);
  1236. }
  1237. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1238. {
  1239. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1240. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycle4xIo);
  1241. }
  1242. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1243. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize, FLASH_TIMEOUT);
  1244. return HV_SUCCESS;
  1245. }
  1246. static Status Flash_SendQuadInt(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  1247. {
  1248. QspiSelf* pstQspi = pstFlash->pstQspi;
  1249. UCHAR8 aucCmdAddr[8] = {0};
  1250. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1251. {
  1252. HV_LOGI("Quad Int send just support 32bits DataWidth.\n");
  1253. HV_ASSERT(0);
  1254. }
  1255. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1256. {
  1257. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1258. {
  1259. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd;
  1260. }
  1261. else
  1262. {
  1263. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd;
  1264. }
  1265. aucCmdAddr[4] = 0x00;
  1266. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1267. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1268. aucCmdAddr[7] = uiWtAddr & 0xff;
  1269. }
  1270. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1271. {
  1272. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1273. {
  1274. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQuadCmd;
  1275. }
  1276. else
  1277. {
  1278. aucCmdAddr[3] = pstFlash->flashAttr.FlashProgQpiCmd;
  1279. }
  1280. aucCmdAddr[4] = (uiWtAddr >> 24) & 0xff;
  1281. aucCmdAddr[5] = (uiWtAddr >> 16) & 0xff;
  1282. aucCmdAddr[6] = (uiWtAddr >> 8) & 0xff;
  1283. aucCmdAddr[7] = uiWtAddr & 0xff;
  1284. }
  1285. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1286. Flash_WriteEnable(pstFlash);
  1287. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1288. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1289. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1290. {
  1291. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1292. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1293. }
  1294. else
  1295. {
  1296. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  1297. pstFlash->InitParam.AddrWidth, 0);
  1298. }
  1299. Hv_Cal_Qspi_IntWrite(pstQspi, aucCmdAddr, 8, pucTxData, uiTxSize);
  1300. return HV_SUCCESS;
  1301. }
  1302. static Status Flash_RecvQuadInt(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1303. {
  1304. QspiSelf* pstQspi = pstFlash->pstQspi;
  1305. UCHAR8 aucCmdAddr[8] = {0};
  1306. if (pstFlash->InitParam.DataSize != FLASH_DATAWIDTH_32)
  1307. {
  1308. HV_LOGI("Quad Int receive just support 32bits DataWidth.\n");
  1309. HV_ASSERT(0);
  1310. }
  1311. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1312. {
  1313. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1314. {
  1315. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd;
  1316. }
  1317. else
  1318. {
  1319. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd;
  1320. }
  1321. aucCmdAddr[4] = 0x00;
  1322. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1323. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1324. aucCmdAddr[7] = uiRdAddr & 0xff;
  1325. }
  1326. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1327. {
  1328. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1329. {
  1330. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQuadCmd;
  1331. }
  1332. else
  1333. {
  1334. aucCmdAddr[3] = pstFlash->flashAttr.FlashReadQpiCmd;
  1335. }
  1336. aucCmdAddr[4] = (uiRdAddr >> 24) & 0xff;
  1337. aucCmdAddr[5] = (uiRdAddr >> 16) & 0xff;
  1338. aucCmdAddr[6] = (uiRdAddr >> 8) & 0xff;
  1339. aucCmdAddr[7] = uiRdAddr & 0xff;
  1340. }
  1341. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1342. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1343. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1344. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1345. {
  1346. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND, pstFlash->flashAttr.FlashInstruWidth,
  1347. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastQuad);
  1348. }
  1349. else
  1350. {
  1351. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI, pstFlash->flashAttr.FlashInstruWidth,
  1352. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleQpi);
  1353. }
  1354. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1355. Hv_Cal_Qspi_IntRead(pstQspi, aucCmdAddr, 8, pucRxData, uiRxSize);
  1356. return HV_SUCCESS;
  1357. }
  1358. static Status Flash_SendQuadDma(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  1359. {
  1360. QspiSelf* pstQspi = pstFlash->pstQspi;
  1361. FlashTxMem* TxDataDma = NULL;
  1362. UINT32 uiWtCmdTemp = 0;
  1363. UINT64 wtAddrTempHigh = 0;
  1364. UINT64 wtAddrTempLow = 0;
  1365. UINT32 uiLoop = 0;
  1366. TxDataDma = (FlashTxMem*) (pucTxData - 20);
  1367. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  1368. {
  1369. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1370. {
  1371. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1372. {
  1373. TxDataDma->cmdAddr[16] = pstFlash->flashAttr.FlashProgQpiCmd;
  1374. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  1375. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  1376. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  1377. }
  1378. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1379. {
  1380. for (uiLoop = 0;uiLoop < 16;uiLoop++)
  1381. {
  1382. wtAddrTempLow |= ((UINT64)(uiWtAddr & (1 << uiLoop))) << 3 * uiLoop;
  1383. wtAddrTempLow |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1384. if (uiLoop < 8)
  1385. {
  1386. uiWtCmdTemp |= ((UINT32)(pstFlash->flashAttr.FlashProgQuadCmd & (1 << uiLoop))) << 3 * uiLoop;
  1387. uiWtCmdTemp |= ((UINT32)((0xe << uiLoop))) << 3 * uiLoop;
  1388. wtAddrTempHigh |= ((UINT64)(((uiWtAddr >> 16) & (1 << uiLoop)))) << 3 * uiLoop;
  1389. wtAddrTempHigh |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1390. }
  1391. }
  1392. TxDataDma->cmdAddr[4] = (uiWtCmdTemp >> 24) & 0xff;
  1393. TxDataDma->cmdAddr[5] = (uiWtCmdTemp >> 16) & 0xff;
  1394. TxDataDma->cmdAddr[6] = (uiWtCmdTemp >> 8) & 0xff;
  1395. TxDataDma->cmdAddr[7] = uiWtCmdTemp & 0xff;
  1396. TxDataDma->cmdAddr[8] = (wtAddrTempHigh >> 24) & 0xff;
  1397. TxDataDma->cmdAddr[9] = (wtAddrTempHigh >> 16) & 0xff;
  1398. TxDataDma->cmdAddr[10] = (wtAddrTempHigh >> 8) & 0xff;
  1399. TxDataDma->cmdAddr[11] = wtAddrTempHigh & 0xff;
  1400. TxDataDma->cmdAddr[12] = (wtAddrTempLow >> 56) & 0xff;
  1401. TxDataDma->cmdAddr[13] = (wtAddrTempLow >> 48) & 0xff;
  1402. TxDataDma->cmdAddr[14] = (wtAddrTempLow >> 40) & 0xff;
  1403. TxDataDma->cmdAddr[15] = (wtAddrTempLow >> 32) & 0xff;
  1404. TxDataDma->cmdAddr[16] = (wtAddrTempLow >> 24) & 0xff;
  1405. TxDataDma->cmdAddr[17] = (wtAddrTempLow >> 16) & 0xff;
  1406. TxDataDma->cmdAddr[18] = (wtAddrTempLow >> 8) & 0xff;
  1407. TxDataDma->cmdAddr[19] = wtAddrTempLow & 0xff;
  1408. }
  1409. }
  1410. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1411. {
  1412. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1413. {
  1414. TxDataDma->cmdAddr[15] = pstFlash->flashAttr.FlashProgQpiCmd;
  1415. TxDataDma->cmdAddr[16] = (uiWtAddr >> 24) & 0xff;
  1416. TxDataDma->cmdAddr[17] = (uiWtAddr >> 16) & 0xff;
  1417. TxDataDma->cmdAddr[18] = (uiWtAddr >> 8) & 0xff;
  1418. TxDataDma->cmdAddr[19] = uiWtAddr & 0xff;
  1419. }
  1420. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1421. {
  1422. UINT32 uiWtCmdTemp = 0;
  1423. UINT64 wtAddrTempHigh = 0;
  1424. UINT64 wtAddrTempLow = 0;
  1425. UINT32 uiLoop = 0;
  1426. for (uiLoop = 0;uiLoop < 16;uiLoop++)
  1427. {
  1428. wtAddrTempLow |= ((UINT64)(uiWtAddr & (1 << uiLoop))) << 3 * uiLoop;
  1429. wtAddrTempLow |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1430. if (uiLoop < 8)
  1431. {
  1432. uiWtCmdTemp |= ((UINT32)(pstFlash->flashAttr.FlashProgQuadCmd & (1 << uiLoop))) << 3 * uiLoop;
  1433. uiWtCmdTemp |= ((UINT32)((0xe << uiLoop))) << 3 * uiLoop;
  1434. wtAddrTempHigh |= ((UINT64)(((uiWtAddr >> 16) & (1 << uiLoop)))) << 3 * uiLoop;
  1435. wtAddrTempHigh |= ((UINT64)((0xe << uiLoop))) << 3 * uiLoop;
  1436. }
  1437. }
  1438. TxDataDma->cmdAddr[0] = (uiWtCmdTemp >> 24) & 0xff;
  1439. TxDataDma->cmdAddr[1] = (uiWtCmdTemp >> 16) & 0xff;
  1440. TxDataDma->cmdAddr[2] = (uiWtCmdTemp >> 8) & 0xff;
  1441. TxDataDma->cmdAddr[3] = uiWtCmdTemp & 0xff;
  1442. TxDataDma->cmdAddr[4] = (wtAddrTempLow >> 56) & 0xff;
  1443. TxDataDma->cmdAddr[5] = (wtAddrTempLow >> 48) & 0xff;
  1444. TxDataDma->cmdAddr[6] = (wtAddrTempLow >> 40) & 0xff;
  1445. TxDataDma->cmdAddr[7] = (wtAddrTempLow >> 32) & 0xff;
  1446. TxDataDma->cmdAddr[8] = (wtAddrTempHigh >> 24) & 0xff;
  1447. TxDataDma->cmdAddr[9] = (wtAddrTempHigh >> 16) & 0xff;
  1448. TxDataDma->cmdAddr[10] = (wtAddrTempHigh >> 8) & 0xff;
  1449. TxDataDma->cmdAddr[11] = wtAddrTempHigh & 0xff;
  1450. TxDataDma->cmdAddr[12] = (wtAddrTempLow >> 56) & 0xff;
  1451. TxDataDma->cmdAddr[13] = (wtAddrTempLow >> 48) & 0xff;
  1452. TxDataDma->cmdAddr[14] = (wtAddrTempLow >> 40) & 0xff;
  1453. TxDataDma->cmdAddr[15] = (wtAddrTempLow >> 32) & 0xff;
  1454. TxDataDma->cmdAddr[16] = (wtAddrTempLow >> 24) & 0xff;
  1455. TxDataDma->cmdAddr[17] = (wtAddrTempLow >> 16) & 0xff;
  1456. TxDataDma->cmdAddr[18] = (wtAddrTempLow >> 8) & 0xff;
  1457. TxDataDma->cmdAddr[19] = wtAddrTempLow & 0xff;
  1458. }
  1459. }
  1460. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1461. Flash_WriteEnable(pstFlash);
  1462. Flash_SetDmaBaudRate(pstFlash);
  1463. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1464. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1465. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1466. {
  1467. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1468. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  1469. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1470. {
  1471. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[4], uiTxSize + 16);
  1472. }
  1473. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1474. {
  1475. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[0], uiTxSize + 20);
  1476. }
  1477. }
  1478. else
  1479. {
  1480. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1481. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  1482. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24){
  1483. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[16], uiTxSize + 4);
  1484. }
  1485. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1486. {
  1487. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[15], uiTxSize + 5);
  1488. }
  1489. }
  1490. }
  1491. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1492. {
  1493. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1494. {
  1495. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgQuadCmd;
  1496. }
  1497. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1498. {
  1499. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1500. {
  1501. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgQpiCmd;
  1502. }
  1503. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1504. {
  1505. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProgQpiCmd_4ByteAddr;
  1506. }
  1507. }
  1508. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1509. {
  1510. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1511. {
  1512. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProg4xIoCmd;
  1513. }
  1514. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1515. {
  1516. TxDataDma->cmdAddr[12] = pstFlash->flashAttr.FlashProg4xIoCmd_4ByteAddr;
  1517. }
  1518. }
  1519. TxDataDma->cmdAddr[13] = 0x00;
  1520. TxDataDma->cmdAddr[14] = 0x00;
  1521. TxDataDma->cmdAddr[15] = 0x00;
  1522. TxDataDma->cmdAddr[16] = uiWtAddr & 0xff;
  1523. TxDataDma->cmdAddr[17] = (uiWtAddr >> 8) & 0xff;
  1524. TxDataDma->cmdAddr[18] = (uiWtAddr >> 16) & 0xff;
  1525. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1526. {
  1527. TxDataDma->cmdAddr[19] = 0x00;
  1528. }
  1529. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1530. {
  1531. TxDataDma->cmdAddr[19] = (uiWtAddr >> 24) & 0xff;
  1532. }
  1533. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1534. Flash_WriteEnable(pstFlash);
  1535. Flash_SetDmaBaudRate(pstFlash);
  1536. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1537. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  1538. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1539. {
  1540. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_STAND,
  1541. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1542. }
  1543. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1544. {
  1545. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_MULTI_ADDR_MULTI,
  1546. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1547. }
  1548. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1549. {
  1550. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi,QSPI_INSTRU_STAND_ADDR_MULTI,
  1551. pstFlash->flashAttr.FlashInstruWidth, pstFlash->InitParam.AddrWidth, 0);
  1552. }
  1553. Hv_Cal_Qspi_DmaWrite(pstQspi, &TxDataDma->cmdAddr[12], uiTxSize + 8);
  1554. }
  1555. return HV_SUCCESS;
  1556. }
  1557. static Status Flash_RecvQuadDma(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  1558. {
  1559. QspiSelf* pstQspi = pstFlash->pstQspi;
  1560. UINT32 uiLoop = 0;
  1561. UCHAR8 aucCmdAddr[8] = {0};
  1562. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1563. {
  1564. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadQuadCmd;
  1565. }
  1566. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1567. {
  1568. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1569. {
  1570. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadQpiCmd;
  1571. }
  1572. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1573. {
  1574. aucCmdAddr[0] = pstFlash->flashAttr.FlashReadQpiCmd_4ByteAddr;
  1575. }
  1576. }
  1577. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1578. {
  1579. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1580. {
  1581. aucCmdAddr[0] = pstFlash->flashAttr.FlashRead4xIoCmd;
  1582. }
  1583. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1584. {
  1585. aucCmdAddr[0] = pstFlash->flashAttr.FlashRead4xIoCmd_4ByteAddr;
  1586. }
  1587. }
  1588. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1589. {
  1590. aucCmdAddr[1] = (uiRdAddr >> 16) & 0xff;
  1591. aucCmdAddr[2] = (uiRdAddr >> 8) & 0xff;
  1592. aucCmdAddr[3] = uiRdAddr & 0xff;
  1593. }
  1594. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1595. {
  1596. aucCmdAddr[1] = (uiRdAddr >> 24) & 0xff;
  1597. aucCmdAddr[2] = (uiRdAddr >> 16) & 0xff;
  1598. aucCmdAddr[3] = (uiRdAddr >> 8) & 0xff;
  1599. aucCmdAddr[4] = uiRdAddr & 0xff;
  1600. }
  1601. Flash_WaitBusy(pstFlash,FLASH_WAITBUSY_TIMEOUT);
  1602. Flash_SetDmaBaudRate(pstFlash);
  1603. if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_8)
  1604. {
  1605. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1606. }
  1607. else if (pstFlash->InitParam.DataSize == FLASH_DATAWIDTH_32)
  1608. {
  1609. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  1610. }
  1611. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  1612. if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  1613. {
  1614. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,pstFlash->flashAttr.FlashInstruWidth,
  1615. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleFastQuad);
  1616. }
  1617. else if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  1618. {
  1619. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1620. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycleQpi);
  1621. }
  1622. else if (pstFlash->InitParam.TransType == FLASH_ADDR_4LINE)
  1623. {
  1624. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_MULTI,pstFlash->flashAttr.FlashInstruWidth,
  1625. pstFlash->InitParam.AddrWidth, pstFlash->flashAttr.FlashCycle4xIo);
  1626. }
  1627. Hv_Cal_Qspi_SetReadNumber(pstQspi, uiRxSize);
  1628. if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_24)
  1629. {
  1630. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 4, pucRxData, uiRxSize);
  1631. }
  1632. else if (pstFlash->InitParam.AddrWidth == FLASH_ADDRESS_WIDTH_32)
  1633. {
  1634. Hv_Cal_Qspi_DmaRead(pstQspi, aucCmdAddr, 5, pucRxData, uiRxSize);
  1635. }
  1636. return HV_SUCCESS;
  1637. }
  1638. /**********************************************Quad API end *************************************/
  1639. /**********************************************flash db opration ********************************/
  1640. static QspiSelf* Flash_GetQspi(FlashSelf* pstFlash)
  1641. {
  1642. QspiSelf* pstQspi = pstFlash->pstQspi;
  1643. return pstQspi;
  1644. }
  1645. static Status Flash_SetBaudRate(FlashSelf* pstFlash,USHORT16 baudRate)
  1646. {
  1647. QspiSelf* pstQspi = pstFlash->pstQspi;
  1648. Hv_Cal_Qspi_SetBaudRate(pstQspi,(QspiDivideRatio)baudRate);
  1649. return HV_SUCCESS;
  1650. }
  1651. static FlashMultiIOType Flash_GetTransType(FlashSelf* pstFlash)
  1652. {
  1653. return pstFlash->InitParam.TransType;
  1654. }
  1655. static FlashAddressWidth Flash_GetAddrWidth(void* arg)
  1656. {
  1657. FlashSelf* pstFlash = (FlashSelf*)arg;
  1658. return pstFlash->InitParam.AddrWidth;
  1659. }
  1660. static FlashDataWidth Flash_GetDataSize(FlashSelf* pstFlash)
  1661. {
  1662. return pstFlash->InitParam.DataSize;
  1663. }
  1664. static FlashRateMode Flash_GetRateMode(FlashSelf* pstFlash)
  1665. {
  1666. return pstFlash->InitParam.RateMode;
  1667. }
  1668. static FlashAttribute* Flash_GetFlashAttribute(void* arg)
  1669. {
  1670. FlashSelf* pstFlash = (FlashSelf*)arg;
  1671. return &pstFlash->flashAttr;
  1672. }
  1673. static Status Flash_FourLineEnable(FlashSelf* pstFlash,FlashModel enFlashModel)
  1674. {
  1675. QspiSelf* pstQspi = Flash_GetQspi(pstFlash);
  1676. UCHAR8 switchCmd[4] = {0};
  1677. if (enFlashModel == FLASH_GD25)
  1678. {
  1679. switchCmd[0] = GD25_Flash_QuadEnable & 0xff;
  1680. switchCmd[1] = 0x00 & 0xff;
  1681. switchCmd[2] = 0x02 & 0xff;
  1682. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1683. Flash_WriteEnable(pstFlash);
  1684. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  1685. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1686. //HV_LOGI("GD25 flash quad mode is enable.\n");
  1687. }
  1688. else if (enFlashModel == FLASH_P25Q)
  1689. {
  1690. switchCmd[0] = P25Q_Flash_QuadEnable & 0xff;
  1691. switchCmd[1] = 0x02 & 0xff;
  1692. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1693. Flash_WriteEnable(pstFlash);
  1694. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  1695. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1696. //HV_LOGI("P25Q flash quad mode is enable.\n");
  1697. }
  1698. else if (enFlashModel == FLASH_MX25)
  1699. {
  1700. if ((Flash_GetTransType(pstFlash) == FLASH_MULTIIO_FAST_TYPE)
  1701. ||(Flash_GetTransType(pstFlash) == FLASH_ADDR_4LINE))
  1702. {
  1703. UCHAR8 aucStateCmd[2] = {0x05,0x00};
  1704. UCHAR8 aucRdState[2] = {0xff,0xff};
  1705. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1706. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1707. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1708. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  1709. // HV_LOGI("regVal[0] is 0x%x,regVal[1] is 0x%x.\n",aucRdState[0],aucRdState[1]);
  1710. if ((aucRdState[1] & 0x40) != 0x40)
  1711. {
  1712. switchCmd[0]=0x01;
  1713. switchCmd[1]=0x40;
  1714. Flash_WriteEnable(pstFlash);
  1715. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1716. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  1717. }
  1718. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1719. //HV_LOGI("MX25Q flash quad mode is enable.\n");
  1720. }
  1721. else if (Flash_GetTransType(pstFlash) == FLASH_INSTRUCT_ADDR_4LINE)
  1722. {
  1723. switchCmd[0] = MX25_Flash_QpiEnable & 0xff;
  1724. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  1725. Flash_WriteEnable(pstFlash);
  1726. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 1, NULL, 0, FLASH_TIMEOUT);
  1727. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1728. //HV_LOGI("MX25Q flash qpi mode is enable.\n");
  1729. }
  1730. }
  1731. else if (enFlashModel == FLASH_W25Q)
  1732. {
  1733. UCHAR8 aucStateCmd[2] = {0x35,0x00};
  1734. UCHAR8 aucRdState[2] = {0xff,0xff};
  1735. UCHAR8 RdStateVerify[2] = {0xff,0xff};
  1736. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1737. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1738. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1739. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  1740. HV_LOGI("regVal[0] is 0x%x,regVal[1] is 0x%x.\n",aucRdState[0],aucRdState[1]);
  1741. if ((aucRdState[1] & 0x02) != 0x02)
  1742. {
  1743. switchCmd[0]=0x01;
  1744. switchCmd[1]=0x00;
  1745. switchCmd[2]=0x02;
  1746. Flash_WriteEnable(pstFlash);
  1747. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1748. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  1749. }
  1750. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  1751. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, RdStateVerify, 0, FLASH_TIMEOUT);
  1752. HV_LOGI("regVal[0] is 0x%x,regVal[1] is 0x%x.\n",RdStateVerify[0],RdStateVerify[1]);
  1753. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  1754. HV_LOGI("W25Q flash quad mode is enable.\n");
  1755. }
  1756. return HV_SUCCESS;
  1757. }
  1758. static VOID Flash_ReadStatusReg(UCHAR8 ucReg, UCHAR8* pucVal, UCHAR8 ucLen)
  1759. {
  1760. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  1761. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  1762. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1763. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1764. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1765. Hv_Cal_Qspi_PollingRead(pstQspi, &ucReg, 1, pucVal, ucLen, FLASH_TIMEOUT);
  1766. Hv_Cal_Qspi_SetRateMode(pstQspi,RateMode);
  1767. HV_LOGV("read status is 0x%x:0x%x.\n",ucReg, *pucVal);
  1768. return;
  1769. }
  1770. static VOID Flash_WriteStatusReg(UCHAR8 ucReg, UCHAR8 ucVal)
  1771. {
  1772. UCHAR8 switchCmd[2] = {0};
  1773. switchCmd[0] = ucReg;
  1774. switchCmd[1] = ucVal;
  1775. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  1776. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  1777. Flash_WriteEnable(&g_stFlash);
  1778. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1779. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1780. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1781. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  1782. Hv_Cal_Qspi_SetRateMode(pstQspi,RateMode);
  1783. HV_LOGV("write status is 0x%x:0x%x.\n",ucReg, ucVal);
  1784. return;
  1785. }
  1786. static VOID Flash_WriteStatusRegDB(UCHAR8 ucReg, UCHAR8 pucLow, UCHAR8 pucHigh)
  1787. {
  1788. UCHAR8 switchCmd[3] = {0};
  1789. switchCmd[0] = ucReg;
  1790. switchCmd[1] = pucLow;
  1791. switchCmd[2] = pucHigh;
  1792. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  1793. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  1794. Flash_WriteEnable(&g_stFlash);
  1795. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  1796. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  1797. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  1798. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  1799. Hv_Cal_Qspi_SetRateMode(pstQspi,RateMode);
  1800. HV_LOGV("write status is 0x%x:0x%x.0x%x\n",ucReg, pucLow, pucHigh);
  1801. return;
  1802. }
  1803. static VOID Flash_WriteAddrProtect(UINT32 uiFlashID, UINT32 uiAddr, UCHAR8 ucProtectDisable)
  1804. {
  1805. UCHAR8 ucStatus = 0;
  1806. UCHAR8 ucNeedWp = 0;
  1807. UCHAR8 aucStatus[3] = {0x0};
  1808. HV_LOGV("ucProtectDisable 0x%x:0x%x\n",ucProtectDisable, uiAddr);
  1809. switch (uiFlashID)
  1810. {
  1811. /* mx25v1635 bit2-bit5:bp0-bp3 tb bit use 0 default. */
  1812. case 0xc22315:
  1813. {
  1814. Flash_ReadStatusReg(0x05, &ucStatus, 1);
  1815. if (1 == ucProtectDisable)
  1816. {
  1817. /* 1 1 1 0 protect:0-30 */
  1818. if (uiAddr >= 0x1f0000)
  1819. {
  1820. ucStatus |= 0xe << 2;
  1821. ucStatus &= ~(0x1 << 2);
  1822. }
  1823. /* 1 1 0 1 protect:0-29 */
  1824. else if (uiAddr >= 0x1e0000)
  1825. {
  1826. ucStatus |= 0xd << 2;
  1827. ucStatus &= ~(0x2 << 2);
  1828. }
  1829. /* 1 1 0 0 protect:0-27 */
  1830. else if (uiAddr >= 0x1c0000)
  1831. {
  1832. ucStatus |= 0xc << 2;
  1833. ucStatus &= ~(0x3 << 2);
  1834. }
  1835. /* 1 0 1 1 protect:0-23 */
  1836. else if (uiAddr >= 0x180000)
  1837. {
  1838. ucStatus |= 0xb << 2;
  1839. ucStatus &= ~(0x4 << 2);
  1840. }
  1841. /* 1 0 1 0 protect:0-16 */
  1842. else if (uiAddr >= 0x100000)
  1843. {
  1844. ucStatus |= 0xc << 2;
  1845. ucStatus &= ~(0x5 << 2);
  1846. }
  1847. /* 0 1 0 1 protect:16-31 */
  1848. else
  1849. {
  1850. ucStatus |= 0x5 << 2;
  1851. ucStatus &= ~(0xa << 2);
  1852. }
  1853. /* set swrd bit. */
  1854. ucStatus |= 0x1 << 7;
  1855. Flash_WriteStatusRegDB(0x01, ucStatus, 0);
  1856. }
  1857. else if (0xaa == ucProtectDisable)
  1858. {
  1859. /* 0 0 0 0*/
  1860. ucStatus &= ~ (0xf << 2);
  1861. /* set swrd bit. */
  1862. ucStatus &= ~ (0x1 << 7);
  1863. Flash_WriteStatusRegDB(0x01, ucStatus, 0);
  1864. }
  1865. else
  1866. {
  1867. /* 1 1 1 1*/
  1868. ucStatus |= 0xf << 2;
  1869. /* set swrd bit. */
  1870. ucStatus |= 0x1 << 7;
  1871. Flash_WriteStatusRegDB(0x01, ucStatus, 0);
  1872. }
  1873. Hv_Vos_MSleep(40);
  1874. break;
  1875. }
  1876. /* mx25l1606e.mx25v16066 bit2-bit5:bp0-bp3 */
  1877. case 0xc22015:
  1878. {
  1879. Flash_ReadStatusReg(0x05, &ucStatus, 1);
  1880. if (1 == ucProtectDisable)
  1881. {
  1882. /* 1 1 1 0 protect:0-30 */
  1883. if (uiAddr >= 0x1f0000)
  1884. {
  1885. ucStatus |= 0xe << 2;
  1886. ucStatus &= ~(0x1 << 2);
  1887. }
  1888. /* 1 1 0 1 protect:0-29 */
  1889. else if (uiAddr >= 0x1e0000)
  1890. {
  1891. ucStatus |= 0xd << 2;
  1892. ucStatus &= ~(0x2 << 2);
  1893. }
  1894. /* 1 1 0 0 protect:0-27 */
  1895. else if (uiAddr >= 0x1c0000)
  1896. {
  1897. ucStatus |= 0xc << 2;
  1898. ucStatus &= ~(0x3 << 2);
  1899. }
  1900. /* 1 0 1 1 protect:0-23 */
  1901. else if (uiAddr >= 0x180000)
  1902. {
  1903. ucStatus |= 0xb << 2;
  1904. ucStatus &= ~(0x4 << 2);
  1905. }
  1906. /* 1 0 1 0 protect:0-16 */
  1907. else if (uiAddr >= 0x100000)
  1908. {
  1909. ucStatus |= 0xc << 2;
  1910. ucStatus &= ~(0x5 << 2);
  1911. }
  1912. /* 0 1 0 1 protect:16-31 */
  1913. else
  1914. {
  1915. ucStatus |= 0x5 << 2;
  1916. ucStatus &= ~(0xa << 2);
  1917. }
  1918. /* set swrd bit. */
  1919. ucStatus |= 0x1 << 7;
  1920. Flash_WriteStatusReg(0x01, ucStatus);
  1921. }
  1922. else if (0xaa == ucProtectDisable)
  1923. {
  1924. /* 0 0 0 0*/
  1925. ucStatus &= ~ (0xf << 2);
  1926. /* set swrd bit. */
  1927. ucStatus &= ~ (0x1 << 7);
  1928. Flash_WriteStatusReg(0x01, ucStatus);
  1929. }
  1930. else
  1931. {
  1932. /* 1 1 1 1*/
  1933. ucStatus |= 0xf << 2;
  1934. /* set swrd bit. */
  1935. ucStatus |= 0x1 << 7;
  1936. Flash_WriteStatusReg(0x01, ucStatus);
  1937. }
  1938. Hv_Vos_MSleep(40);
  1939. break;
  1940. }
  1941. /* XM25QH16C bit14:bmp bit2-bit6:bp0-bp4*/
  1942. case 0x204015:
  1943. {
  1944. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  1945. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  1946. if (1 == ucProtectDisable)
  1947. {
  1948. /* cmp 1, 1 0 0 0 1 protect:0-31 */
  1949. if (uiAddr >= 0x1ff000)
  1950. {
  1951. aucStatus[0] |= 0x11 << 2;
  1952. aucStatus[0] &= ~(0xe << 2);
  1953. }
  1954. /* cmp 1, 1 0 0 1 0 protect:0-31 */
  1955. else if (uiAddr >= 0x1fe000)
  1956. {
  1957. aucStatus[0] |= 0x12 << 2;
  1958. aucStatus[0] &= ~(0xd << 2);
  1959. }
  1960. /* cmp 1, 1 0 0 1 1 protect:0-31 */
  1961. else if (uiAddr >= 0x1fc000)
  1962. {
  1963. aucStatus[0] |= 0x13 << 2;
  1964. aucStatus[0] &= ~(0xc << 2);
  1965. }
  1966. /* cmp 1, 1 0 1 0 x protect:0-31 */
  1967. else if (uiAddr >= 0x1f8000)
  1968. {
  1969. aucStatus[0] |= 0x14 << 2;
  1970. aucStatus[0] &= ~(0xa << 2);
  1971. }
  1972. /* cmp 1, 0 0 0 0 1 protect:0-30 */
  1973. else if (uiAddr >= 0x1f0000)
  1974. {
  1975. aucStatus[0] |= 0x1 << 2;
  1976. aucStatus[0] &= ~(0x1e << 2);
  1977. }
  1978. /* cmp 1, 0 0 0 1 0 protect:0-29 */
  1979. else if (uiAddr >= 0x1e0000)
  1980. {
  1981. aucStatus[0] |= 0x2 << 2;
  1982. aucStatus[0] &= ~(0x1d << 2);
  1983. }
  1984. /* cmp 1, 0 0 0 1 1 protect:0-27 */
  1985. else if (uiAddr >= 0x1c0000)
  1986. {
  1987. aucStatus[0] |= 0x3 << 2;
  1988. aucStatus[0] &= ~(0x1c << 2);
  1989. }
  1990. /* cmp 1, 0 0 1 0 0 protect:0-23 */
  1991. else if (uiAddr >= 0x180000)
  1992. {
  1993. aucStatus[0] |= 0x4 << 2;
  1994. aucStatus[0] &= ~(0x1b << 2);
  1995. }
  1996. /* cmp 1, 0 0 1 0 1 protect:0-15 */
  1997. else if (uiAddr >= 0x100000)
  1998. {
  1999. aucStatus[0] |= 0x5 << 2;
  2000. aucStatus[0] &= ~(0x1a << 2);
  2001. }
  2002. /* cmp 1, 1 1 0 0 1 protect:0-31 */
  2003. else if (uiAddr < 0x1000)
  2004. {
  2005. aucStatus[0] |= 0x19 << 2;
  2006. aucStatus[0] &= ~(0x6 << 2);
  2007. }
  2008. /* cmp 1, 1 1 0 1 0 protect:0-31 */
  2009. else if (uiAddr < 0x2000)
  2010. {
  2011. aucStatus[0] |= 0x1a << 2;
  2012. aucStatus[0] &= ~(0x5 << 2);
  2013. }
  2014. /* cmp 1, 1 1 0 1 1 protect:0-31 */
  2015. else if (uiAddr < 0x4000)
  2016. {
  2017. aucStatus[0] |= 0x1b << 2;
  2018. aucStatus[0] &= ~(0x4 << 2);
  2019. }
  2020. /* cmp 1, 1 1 1 0 x protect:0-31 */
  2021. else if (uiAddr < 0x8000)
  2022. {
  2023. aucStatus[0] |= 0x1c << 2;
  2024. aucStatus[0] &= ~(0x3 << 2);
  2025. }
  2026. /* cmp 1, 0 1 0 0 1 protect:1-31 */
  2027. else if (uiAddr < 0x10000)
  2028. {
  2029. aucStatus[0] |= 0x9 << 2;
  2030. aucStatus[0] &= ~(0x16 << 2);
  2031. }
  2032. /* cmp 1, 0 1 0 1 0 protect:2-31 */
  2033. else if (uiAddr < 0x20000)
  2034. {
  2035. aucStatus[0] |= 0xa << 2;
  2036. aucStatus[0] &= ~(0x15 << 2);
  2037. }
  2038. /* cmp 1, 0 1 0 1 1 protect:4-31 */
  2039. else if (uiAddr < 0x40000)
  2040. {
  2041. aucStatus[0] |= 0xb << 2;
  2042. aucStatus[0] &= ~(0x14 << 2);
  2043. }
  2044. /* cmp 1, 0 1 1 0 0 protect:8-31 */
  2045. else if (uiAddr < 0x80000)
  2046. {
  2047. aucStatus[0] |= 0xc << 2;
  2048. aucStatus[0] &= ~(0x13 << 2);
  2049. }
  2050. /* cmp 1, 0 1 1 0 1 protect:16-31 */
  2051. else //(uiAddr < 0x100000)
  2052. {
  2053. aucStatus[0] |= 0xd << 2;
  2054. aucStatus[0] &= ~(0x12 << 2);
  2055. }
  2056. /* set srp0 1 & srp1 0. */
  2057. aucStatus[0] |= 1 << 7;
  2058. aucStatus[1] &= ~ (0x1);
  2059. /* set cmp bit 1. */
  2060. aucStatus[1] |= 0x1 << 6;
  2061. /* close qe */
  2062. aucStatus[1] &= ~ (0x1 << 1);
  2063. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2064. Hv_Vos_MSleep(10);
  2065. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2066. Hv_Vos_MSleep(10);
  2067. }
  2068. else if (0xaa == ucProtectDisable)
  2069. {
  2070. /* cmp 0, x x 0 0 0 */
  2071. aucStatus[0] &= ~ (0x7 << 2);
  2072. aucStatus[1] &= ~(0x1 << 6);
  2073. /* set srp0 0 & srp1 0. */
  2074. aucStatus[0] &= ~ (1 << 7);
  2075. aucStatus[1] &= ~ (0x1);
  2076. /* close qe */
  2077. aucStatus[1] &= ~ (0x1 << 1);
  2078. Flash_WriteStatusReg(0x01, 0);
  2079. Hv_Vos_MSleep(10);
  2080. Flash_WriteStatusReg(0x31, 0);
  2081. }
  2082. else
  2083. {
  2084. /* cmp 0, x x 1 1 x */
  2085. aucStatus[0] |= 0x6 << 2;
  2086. aucStatus[1] &= ~(0x1 << 6);
  2087. /* set srp0 1 & srp1 0. */
  2088. aucStatus[0] |= 1 << 7;
  2089. aucStatus[1] &= ~ (0x1);
  2090. /* close qe */
  2091. aucStatus[1] &= ~ (0x1 << 1);
  2092. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2093. Hv_Vos_MSleep(10);
  2094. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2095. }
  2096. Hv_Vos_MSleep(50);
  2097. break;
  2098. }
  2099. /* GD25Q16E bit14:bmp bit2-bit6:bp0-bp4*/
  2100. case 0xc84015:
  2101. {
  2102. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2103. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2104. if (1 == ucProtectDisable)
  2105. {
  2106. /* cmp 1, 1 0 0 0 1 protect:0-31 */
  2107. if (uiAddr >= 0x1ff000)
  2108. {
  2109. aucStatus[0] |= 0x11 << 2;
  2110. aucStatus[0] &= ~(0xe << 2);
  2111. }
  2112. /* cmp 1, 1 0 0 1 0 protect:0-31 */
  2113. else if (uiAddr >= 0x1fe000)
  2114. {
  2115. aucStatus[0] |= 0x12 << 2;
  2116. aucStatus[0] &= ~(0xd << 2);
  2117. }
  2118. /* cmp 1, 1 0 0 1 1 protect:0-31 */
  2119. else if (uiAddr >= 0x1fc000)
  2120. {
  2121. aucStatus[0] |= 0x13 << 2;
  2122. aucStatus[0] &= ~(0xc << 2);
  2123. }
  2124. /* cmp 1, 1 0 1 0 x protect:0-31 */
  2125. else if (uiAddr >= 0x1f8000)
  2126. {
  2127. aucStatus[0] |= 0x14 << 2;
  2128. aucStatus[0] &= ~(0xa << 2);
  2129. }
  2130. /* cmp 1, 0 0 0 0 1 protect:0-30 */
  2131. else if (uiAddr >= 0x1f0000)
  2132. {
  2133. aucStatus[0] |= 0x1 << 2;
  2134. aucStatus[0] &= ~(0x1e << 2);
  2135. }
  2136. /* cmp 1, 0 0 0 1 0 protect:0-29 */
  2137. else if (uiAddr >= 0x1e0000)
  2138. {
  2139. aucStatus[0] |= 0x2 << 2;
  2140. aucStatus[0] &= ~(0x1d << 2);
  2141. }
  2142. /* cmp 1, 0 0 0 1 1 protect:0-27 */
  2143. else if (uiAddr >= 0x1c0000)
  2144. {
  2145. aucStatus[0] |= 0x3 << 2;
  2146. aucStatus[0] &= ~(0x1c << 2);
  2147. }
  2148. /* cmp 1, 0 0 1 0 0 protect:0-23 */
  2149. else if (uiAddr >= 0x180000)
  2150. {
  2151. aucStatus[0] |= 0x4 << 2;
  2152. aucStatus[0] &= ~(0x1b << 2);
  2153. }
  2154. /* cmp 1, 0 0 1 0 1 protect:0-15 */
  2155. else if (uiAddr >= 0x100000)
  2156. {
  2157. aucStatus[0] |= 0x5 << 2;
  2158. aucStatus[0] &= ~(0x1a << 2);
  2159. }
  2160. /* cmp 1, 1 1 0 0 1 protect:0-31 */
  2161. else if (uiAddr < 0x1000)
  2162. {
  2163. aucStatus[0] |= 0x19 << 2;
  2164. aucStatus[0] &= ~(0x6 << 2);
  2165. }
  2166. /* cmp 1, 1 1 0 1 0 protect:0-31 */
  2167. else if (uiAddr < 0x2000)
  2168. {
  2169. aucStatus[0] |= 0x1a << 2;
  2170. aucStatus[0] &= ~(0x5 << 2);
  2171. }
  2172. /* cmp 1, 1 1 0 1 1 protect:0-31 */
  2173. else if (uiAddr < 0x4000)
  2174. {
  2175. aucStatus[0] |= 0x1b << 2;
  2176. aucStatus[0] &= ~(0x4 << 2);
  2177. }
  2178. /* cmp 1, 1 1 1 0 x protect:0-31 */
  2179. else if (uiAddr < 0x8000)
  2180. {
  2181. aucStatus[0] |= 0x1c << 2;
  2182. aucStatus[0] &= ~(0x3 << 2);
  2183. }
  2184. /* cmp 1, 0 1 0 0 1 protect:1-31 */
  2185. else if (uiAddr < 0x10000)
  2186. {
  2187. aucStatus[0] |= 0x9 << 2;
  2188. aucStatus[0] &= ~(0x16 << 2);
  2189. }
  2190. /* cmp 1, 0 1 0 1 0 protect:2-31 */
  2191. else if (uiAddr < 0x20000)
  2192. {
  2193. aucStatus[0] |= 0xa << 2;
  2194. aucStatus[0] &= ~(0x15 << 2);
  2195. }
  2196. /* cmp 1, 0 1 0 1 1 protect:4-31 */
  2197. else if (uiAddr < 0x40000)
  2198. {
  2199. aucStatus[0] |= 0xb << 2;
  2200. aucStatus[0] &= ~(0x14 << 2);
  2201. }
  2202. /* cmp 1, 0 1 1 0 0 protect:8-31 */
  2203. else if (uiAddr < 0x80000)
  2204. {
  2205. aucStatus[0] |= 0xc << 2;
  2206. aucStatus[0] &= ~(0x13 << 2);
  2207. }
  2208. /* cmp 1, 0 1 1 0 1 protect:16-31 */
  2209. else //(uiAddr < 0x100000)
  2210. {
  2211. aucStatus[0] |= 0xd << 2;
  2212. aucStatus[0] &= ~(0x12 << 2);
  2213. }
  2214. /* set srp0 1 & srp1 0. */
  2215. aucStatus[0] |= 1 << 7;
  2216. aucStatus[1] &= ~ (0x1);
  2217. /* set cmp bit 1. */
  2218. aucStatus[1] |= 0x1 << 6;
  2219. /* close qe */
  2220. aucStatus[1] &= ~ (0x1 << 1);
  2221. Flash_WriteStatusRegDB(0x01, aucStatus[0], aucStatus[1]);
  2222. }
  2223. else if (0xaa == ucProtectDisable)
  2224. {
  2225. /* cmp 0, x x 0 0 0 */
  2226. aucStatus[0] &= ~ (0x7 << 2);
  2227. aucStatus[1] &= ~(0x1 << 6);
  2228. /* set srp0 0 & srp1 0. */
  2229. aucStatus[0] &= ~ (1 << 7);
  2230. aucStatus[1] &= ~ (0x1);
  2231. /* close qe */
  2232. aucStatus[1] &= ~ (0x1 << 1);
  2233. Flash_WriteStatusRegDB(0x01, aucStatus[0], aucStatus[1]);
  2234. }
  2235. else
  2236. {
  2237. /* cmp 0, x x 1 1 x */
  2238. if ((aucStatus[0] & 0x18) != 0x18)
  2239. {
  2240. ucNeedWp = 1;
  2241. }
  2242. if ((aucStatus[1] & 0x40) == 0x40)
  2243. {
  2244. ucNeedWp = 1;
  2245. }
  2246. HV_LOGV("wp status %x, %x", aucStatus[0], aucStatus[1]);
  2247. aucStatus[0] |= 0x6 << 2;
  2248. aucStatus[1] &= ~(0x1 << 6);
  2249. /* set srp0 1 & srp1 0. */
  2250. aucStatus[0] |= 1 << 7;
  2251. aucStatus[1] &= ~ (0x1);
  2252. /* close qe */
  2253. aucStatus[1] &= ~ (0x1 << 1);
  2254. if (ucNeedWp)
  2255. {
  2256. HV_LOGV("##need wp");
  2257. Flash_WriteStatusRegDB(0x01, aucStatus[0], aucStatus[1]);
  2258. Hv_Vos_MSleep(30);
  2259. }
  2260. }
  2261. break;
  2262. }
  2263. /* winbond w25q16 bit18:wps bit14:cmp bit2-bit6:sec,tb,bp0-bp3*/
  2264. case 0xef4015:
  2265. {
  2266. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2267. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2268. Flash_ReadStatusReg(0x15, &aucStatus[2], 1);
  2269. if (1 == ucProtectDisable)
  2270. {
  2271. #if 0
  2272. /* cmp 1, 1 0 0 0 1 protect:0-31 */
  2273. if (uiAddr >= 0x1ff000)
  2274. {
  2275. aucStatus[0] |= 0x11 << 2;
  2276. aucStatus[0] &= ~(0xe << 2);
  2277. }
  2278. /* cmp 1, 1 0 0 1 0 protect:0-31 */
  2279. else if (uiAddr >= 0x1fe000)
  2280. {
  2281. aucStatus[0] |= 0x12 << 2;
  2282. aucStatus[0] &= ~(0xd << 2);
  2283. }
  2284. /* cmp 1, 1 0 0 1 1 protect:0-31 */
  2285. else if (uiAddr >= 0x1fc000)
  2286. {
  2287. aucStatus[0] |= 0x13 << 2;
  2288. aucStatus[0] &= ~(0xc << 2);
  2289. }
  2290. /* cmp 1, 1 0 1 0 x protect:0-31 */
  2291. else if (uiAddr >= 0x1f8000)
  2292. {
  2293. aucStatus[0] |= 0x14 << 2;
  2294. aucStatus[0] &= ~(0xa << 2);
  2295. }
  2296. /* cmp 1, 0 0 0 0 1 protect:0-30 */
  2297. else if (uiAddr >= 0x1f0000)
  2298. {
  2299. aucStatus[0] |= 0x1 << 2;
  2300. aucStatus[0] &= ~(0x1e << 2);
  2301. }
  2302. /* cmp 1, 0 0 0 1 0 protect:0-29 */
  2303. else if (uiAddr >= 0x1e0000)
  2304. {
  2305. aucStatus[0] |= 0x2 << 2;
  2306. aucStatus[0] &= ~(0x1d << 2);
  2307. }
  2308. /* cmp 1, 0 0 0 1 1 protect:0-27 */
  2309. else if (uiAddr >= 0x1c0000)
  2310. {
  2311. aucStatus[0] |= 0x3 << 2;
  2312. aucStatus[0] &= ~(0x1c << 2);
  2313. }
  2314. /* cmp 1, 0 0 1 0 0 protect:0-23 */
  2315. else if (uiAddr >= 0x180000)
  2316. {
  2317. aucStatus[0] |= 0x4 << 2;
  2318. aucStatus[0] &= ~(0x1b << 2);
  2319. }
  2320. /* cmp 1, 0 0 1 0 1 protect:0-15 */
  2321. else if (uiAddr >= 0x100000)
  2322. {
  2323. aucStatus[0] |= 0x5 << 2;
  2324. aucStatus[0] &= ~(0x1a << 2);
  2325. }
  2326. /* cmp 1, 1 1 0 0 1 protect:0-31 */
  2327. else if (uiAddr < 0x1000)
  2328. {
  2329. aucStatus[0] |= 0x19 << 2;
  2330. aucStatus[0] &= ~(0x6 << 2);
  2331. }
  2332. /* cmp 1, 1 1 0 1 0 protect:0-31 */
  2333. else if (uiAddr < 0x2000)
  2334. {
  2335. aucStatus[0] |= 0x1a << 2;
  2336. aucStatus[0] &= ~(0x5 << 2);
  2337. }
  2338. /* cmp 1, 1 1 0 1 1 protect:0-31 */
  2339. else if (uiAddr < 0x4000)
  2340. {
  2341. aucStatus[0] |= 0x1b << 2;
  2342. aucStatus[0] &= ~(0x4 << 2);
  2343. }
  2344. /* cmp 1, 1 1 1 0 x protect:0-31 */
  2345. else if (uiAddr < 0x8000)
  2346. {
  2347. aucStatus[0] |= 0x1c << 2;
  2348. aucStatus[0] &= ~(0x3 << 2);
  2349. }
  2350. /* cmp 1, 0 1 0 0 1 protect:1-31 */
  2351. else if (uiAddr < 0x10000)
  2352. {
  2353. aucStatus[0] |= 0x9 << 2;
  2354. aucStatus[0] &= ~(0x16 << 2);
  2355. }
  2356. /* cmp 1, 0 1 0 1 0 protect:2-31 */
  2357. else if (uiAddr < 0x20000)
  2358. {
  2359. aucStatus[0] |= 0xa << 2;
  2360. aucStatus[0] &= ~(0x15 << 2);
  2361. }
  2362. /* cmp 1, 0 1 0 1 1 protect:4-31 */
  2363. else if (uiAddr < 0x40000)
  2364. {
  2365. aucStatus[0] |= 0xb << 2;
  2366. aucStatus[0] &= ~(0x14 << 2);
  2367. }
  2368. /* cmp 1, 0 1 1 0 0 protect:8-31 */
  2369. else if (uiAddr < 0x80000)
  2370. {
  2371. aucStatus[0] |= 0xc << 2;
  2372. aucStatus[0] &= ~(0x13 << 2);
  2373. }
  2374. /* cmp 1, 0 1 1 0 1 protect:16-31 */
  2375. else //(uiAddr < 0x100000)
  2376. {
  2377. aucStatus[0] |= 0xd << 2;
  2378. aucStatus[0] &= ~(0x12 << 2);
  2379. }
  2380. /* set srp0 1 & srp1 0. */
  2381. aucStatus[0] |= 1 << 7;
  2382. aucStatus[1] &= ~ (0x1);
  2383. /* set cmp bit 1. */
  2384. aucStatus[1] |= 0x1 << 6;
  2385. /* close qe */
  2386. aucStatus[1] &= ~ (0x1 << 1);
  2387. /* set wps 0 */
  2388. aucStatus[2] &= ~ (0x1 << 2);
  2389. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2390. Hv_Vos_MSleep(15);
  2391. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2392. Hv_Vos_MSleep(15);
  2393. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2394. #else
  2395. /* wps 0, cmp 0 , x x 0 0 0 srp: 0 srl: 0 qe:0 */
  2396. aucStatus[0] &= ~ (0x7 << 2);
  2397. aucStatus[0] &= ~ (0x1 << 7);
  2398. aucStatus[1] &= ~ (0x1 << 0);
  2399. aucStatus[1] &= ~ (0x1 << 1);
  2400. aucStatus[1] &= ~ (0x1 << 6);
  2401. aucStatus[2] &= ~ (0x1 << 2);
  2402. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2403. Hv_Vos_MSleep(15);
  2404. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2405. Hv_Vos_MSleep(15);
  2406. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2407. #endif
  2408. }
  2409. else if (0xaa == ucProtectDisable)
  2410. {
  2411. /* wps 0, cmp 0 , x x 0 0 0 srp: 0 srl: 0 qe:0 */
  2412. aucStatus[0] &= ~ (0x7 << 2);
  2413. aucStatus[0] &= ~ (0x1 << 7);
  2414. aucStatus[1] &= ~ (0x1 << 0);
  2415. aucStatus[1] &= ~ (0x1 << 1);
  2416. aucStatus[1] &= ~ (0x1 << 6);
  2417. aucStatus[2] &= ~ (0x1 << 2);
  2418. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2419. Hv_Vos_MSleep(15);
  2420. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2421. Hv_Vos_MSleep(15);
  2422. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2423. }
  2424. else
  2425. {
  2426. /* wps 0, cmp 0 , x x 1 1 1 srp: 1 srl: 0 qe:0 */
  2427. aucStatus[0] |= 0x7 << 2;
  2428. aucStatus[0] |= 0x1 << 7;
  2429. aucStatus[1] &= ~ (0x1 << 0);
  2430. aucStatus[1] &= ~ (0x1 << 1);
  2431. aucStatus[1] &= ~ (0x1 << 6);
  2432. aucStatus[2] &= ~ (0x1 << 2);
  2433. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2434. Hv_Vos_MSleep(15);
  2435. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2436. Hv_Vos_MSleep(15);
  2437. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2438. }
  2439. Hv_Vos_MSleep(15);
  2440. break;
  2441. }
  2442. /* winbond w25q32 */
  2443. case 0xef4016:
  2444. {
  2445. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2446. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2447. Flash_ReadStatusReg(0x15, &aucStatus[2], 1);
  2448. if (1 == ucProtectDisable)
  2449. {
  2450. /* wps 0, cmp 0 , x x 0 0 0 srp: 1 srl: 0 qe:0 */
  2451. aucStatus[0] &= ~ (0x7 << 2);
  2452. aucStatus[0] |= 0x1 << 7;
  2453. aucStatus[1] &= ~ (0x1 << 0);
  2454. aucStatus[1] &= ~ (0x1 << 1);
  2455. aucStatus[1] &= ~ (0x1 << 6);
  2456. aucStatus[2] &= ~ (0x1 << 2);
  2457. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2458. Hv_Vos_MSleep(15);
  2459. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2460. Hv_Vos_MSleep(15);
  2461. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2462. }
  2463. else if (0xaa == ucProtectDisable)
  2464. {
  2465. /* wps 0, cmp 0 , x x 0 0 0 srp: 0 srl: 0 qe:0 */
  2466. aucStatus[0] &= ~ (0x7 << 2);
  2467. aucStatus[0] &= ~ (0x1 << 7);
  2468. aucStatus[1] &= ~ (0x1 << 0);
  2469. aucStatus[1] &= ~ (0x1 << 1);
  2470. aucStatus[1] &= ~ (0x1 << 6);
  2471. aucStatus[2] &= ~ (0x1 << 2);
  2472. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2473. Hv_Vos_MSleep(15);
  2474. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2475. Hv_Vos_MSleep(15);
  2476. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2477. }
  2478. else
  2479. {
  2480. /* wps 0, cmp 0 , x x 1 1 1 srp: 1 srl: 0 qe:0 */
  2481. aucStatus[0] |= 0x7 << 2;
  2482. aucStatus[0] |= 0x1 << 7;
  2483. aucStatus[1] &= ~ (0x1 << 0);
  2484. aucStatus[1] &= ~ (0x1 << 1);
  2485. aucStatus[1] &= ~ (0x1 << 6);
  2486. aucStatus[2] &= ~ (0x1 << 2);
  2487. Flash_WriteStatusReg(0x01, aucStatus[0]);
  2488. Hv_Vos_MSleep(15);
  2489. Flash_WriteStatusReg(0x31, aucStatus[1]);
  2490. Hv_Vos_MSleep(15);
  2491. Flash_WriteStatusReg(0x11, aucStatus[2]);
  2492. }
  2493. Hv_Vos_MSleep(15);
  2494. break;
  2495. }
  2496. default:
  2497. {
  2498. break;
  2499. }
  2500. }
  2501. }
  2502. static UINT32 Flash_ReadFlashID(VOID)
  2503. {
  2504. QspiSelf* pstQspi = Flash_GetQspi(&g_stFlash);
  2505. FlashRateMode RateMode = g_stFlash.InitParam.RateMode;
  2506. UCHAR8 aucIDCmd[4] = {0x9f};
  2507. UCHAR8 aucReadID[4] = {0x0};
  2508. HV_LOGV("Flash_ReadFlashID.\n");
  2509. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2510. Hv_Cal_Qspi_SetRateMode(pstQspi, QSPI_STANDARD);
  2511. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2512. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_32);
  2513. Hv_Cal_Qspi_PollingRead(pstQspi, aucIDCmd, 4, aucReadID, 0, FLASH_TIMEOUT);
  2514. Hv_Cal_Qspi_SetRateMode(pstQspi, RateMode);
  2515. HV_LOGI("flash id: 0x%x 0x%x 0x%x.\n",aucReadID[1], aucReadID[2], aucReadID[3]);
  2516. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2517. return (aucReadID[1]<<16 | aucReadID[2]<<8 | aucReadID[3]);
  2518. }
  2519. VOID Hv_Drv_Flash_ProtectDisable(VOID)
  2520. {
  2521. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2522. Flash_WriteAddrProtect(g_stFlash.uiFlashID, 0, 0xAA);
  2523. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2524. return;
  2525. }
  2526. VOID Hv_Drv_Flash_Info(VOID)
  2527. {
  2528. UCHAR8 aucStatus[3] = {0x0};
  2529. Flash_ReadFlashID();
  2530. Hv_Vos_MSleep(5);
  2531. Flash_ReadStatusReg(0x05, &aucStatus[0], 1);
  2532. Flash_ReadStatusReg(0x35, &aucStatus[1], 1);
  2533. Flash_ReadStatusReg(0x15, &aucStatus[2], 1);
  2534. HV_LOGI("status: %x,%x,%x.\n", aucStatus[0],aucStatus[1], aucStatus[2]);
  2535. return;
  2536. }
  2537. static Status Flash_WriteProtectEnable(VOID)
  2538. {
  2539. #ifdef HV_PROJECT_CONFIG_FLASH_PROTECT
  2540. HV_LOGV("Flash_WriteProtectEnable.\n");
  2541. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2542. Flash_WriteAddrProtect(g_stFlash.uiFlashID, 0, HV_FALSE);
  2543. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2544. #endif
  2545. return HV_SUCCESS;
  2546. }
  2547. static Status Flash_WriteProtectDisable(UINT32 uiAddr)
  2548. {
  2549. #ifdef HV_PROJECT_CONFIG_FLASH_PROTECT
  2550. HV_LOGV("Flash_WriteProtectDisable.\n");
  2551. Hv_Cal_Qspi_WP_Enable(HV_FALSE);
  2552. Flash_WriteAddrProtect(g_stFlash.uiFlashID, uiAddr, HV_TRUE);
  2553. Hv_Cal_Qspi_WP_Enable(HV_TRUE);
  2554. #endif
  2555. return HV_SUCCESS;
  2556. }
  2557. static Status Flash_FourLineDisable(FlashSelf* pstFlash, FlashModel enFlashModel)
  2558. {
  2559. QspiSelf* pstQspi = Flash_GetQspi(pstFlash);
  2560. UCHAR8 switchCmd[4] = {0};
  2561. if (enFlashModel == FLASH_GD25)
  2562. {
  2563. switchCmd[0] = GD25_Flash_QuadDisable & 0xff;
  2564. switchCmd[1] = 0x00 & 0xff;
  2565. switchCmd[2] = 0x00 & 0xff;
  2566. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2567. Flash_WriteEnable(pstFlash);
  2568. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 3, NULL, 0, FLASH_TIMEOUT);
  2569. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  2570. }
  2571. else if (enFlashModel == FLASH_P25Q)
  2572. {
  2573. switchCmd[0] = P25Q_Flash_QuadDisable & 0xff;
  2574. switchCmd[1] = 0x00 & 0xff;
  2575. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2576. Flash_WriteEnable(pstFlash);
  2577. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  2578. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  2579. }
  2580. else if (enFlashModel == FLASH_MX25)
  2581. {
  2582. if ((Flash_GetTransType(pstFlash) == FLASH_MULTIIO_FAST_TYPE)
  2583. || (Flash_GetTransType(pstFlash) == FLASH_ADDR_4LINE))
  2584. {
  2585. UCHAR8 aucStateCmd[2] = {0x05,0x00};
  2586. UCHAR8 aucRdState[2] = {0xff,0xff};
  2587. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2588. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2589. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  2590. Hv_Cal_Qspi_PollingRead(pstQspi, aucStateCmd, 2, aucRdState, 0, FLASH_TIMEOUT);
  2591. if ((aucRdState[1] & 0x40) == 0x40)
  2592. {
  2593. switchCmd[0]=0x01;
  2594. switchCmd[1]=0x00;
  2595. Flash_WriteEnable(pstFlash);
  2596. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_16);
  2597. // Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 2, NULL, 0, FLASH_TIMEOUT);
  2598. }
  2599. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_QUAD);
  2600. //HV_LOGI("MX25Q flash quad mode is disable.\n");
  2601. }
  2602. else if (Flash_GetTransType(pstFlash) == FLASH_INSTRUCT_ADDR_4LINE)
  2603. {
  2604. switchCmd[0] = MX25_Flash_QpiDisable & 0xff;
  2605. Flash_WriteEnable(pstFlash);
  2606. Hv_Cal_Qspi_PollingWrite(pstQspi, switchCmd, 1, NULL, 0, FLASH_TIMEOUT);
  2607. //HV_LOGI("MX25Q flash qpi mode is disable.\n");
  2608. }
  2609. }
  2610. return HV_SUCCESS;
  2611. }
  2612. static void Flash_DualFuctionJudge(FlashModel enFlashModel)
  2613. {
  2614. if (enFlashModel == FLASH_W25Q)
  2615. {
  2616. HV_LOGI("W25Q can't support dual mode fast write,can support dual mode fast read.\n");
  2617. }
  2618. else if (enFlashModel == FLASH_GD25)
  2619. {
  2620. HV_LOGI("GD25 can't support dual mode fast write,can support dual mode fast read.\n");
  2621. }
  2622. else if (enFlashModel == FLASH_MX25)
  2623. {
  2624. HV_LOGI("MX25 can't support dual mode fast write,can support dual mode fast read.\n");
  2625. }
  2626. return;
  2627. }
  2628. /**********************************************flash db opration end*****************************/
  2629. /****************************** Flash Common API ************************************************/
  2630. static void FLASH_SetCpltCallBack(FlashSelf* pstFlash, void* callbackFunc)
  2631. {
  2632. QspiSelf* pstQspi = pstFlash->pstQspi;
  2633. pstFlash->InitParam.FlashCpltCallback = (Flash_CpltCallback)callbackFunc;
  2634. Hv_Cal_Qspi_SetCpltCallBack(pstQspi,Flash_CpltCallBack);
  2635. }
  2636. UCHAR8 Hv_Drv_Flash_GetFlashStatus(FlashSelf* pstFlash)
  2637. {
  2638. QspiSelf* pstQspi = pstFlash->pstQspi;
  2639. UCHAR8 ucRegVal = 0;
  2640. UCHAR8 ucReadCmd = 0x05;
  2641. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2642. {
  2643. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2644. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2645. Hv_Cal_Qspi_PollingRead(pstQspi, &ucReadCmd, 1, &ucRegVal, 1, FLASH_TIMEOUT);
  2646. }
  2647. else if (pstFlash->InitParam.RateMode == FLASH_DUAL
  2648. ||pstFlash->InitParam.RateMode == FLASH_QUAD)
  2649. {
  2650. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  2651. {
  2652. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2653. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_RX);
  2654. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  2655. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  2656. Hv_Cal_Qspi_SetReadNumber(pstQspi, 1);
  2657. Hv_Cal_Qspi_MultiIoPollingRead(pstQspi, &ucReadCmd, 1, &ucRegVal, 1, FLASH_TIMEOUT);
  2658. }
  2659. else if (pstFlash->InitParam.TransType == FLASH_MULTIIO_FAST_TYPE)
  2660. {
  2661. QspiRateMode enRateMode = Hv_Cal_Qspi_GetRateMode(pstQspi);
  2662. Hv_Cal_Qspi_SetRateMode(pstQspi,QSPI_STANDARD);
  2663. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TXRX);
  2664. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2665. Hv_Cal_Qspi_PollingRead(pstQspi, &ucReadCmd, 1, &ucRegVal, 1, FLASH_TIMEOUT);
  2666. Hv_Cal_Qspi_SetRateMode(pstQspi,enRateMode);
  2667. }
  2668. }
  2669. return ucRegVal;
  2670. }
  2671. UCHAR8 Hv_Drv_Flash_WriteStatus(FlashSelf* pstFlash, UCHAR8 flashStatus)
  2672. {
  2673. QspiSelf* pstQspi = pstFlash->pstQspi;
  2674. UCHAR8 ucSendCmd = 0x01;
  2675. UCHAR8 ucSendData = flashStatus;
  2676. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2677. {
  2678. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  2679. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2680. Hv_Cal_Qspi_PollingWrite(pstQspi, &ucSendCmd, 1, &ucSendData, 1, FLASH_TIMEOUT);
  2681. }
  2682. else if (pstFlash->InitParam.RateMode == FLASH_DUAL ||pstFlash->InitParam.RateMode == FLASH_QUAD)
  2683. {
  2684. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi, QSPI_BITWIDTH_8);
  2685. Hv_Cal_Qspi_SetDirection(pstQspi, QSPI_DIRECTION_TX);
  2686. if (pstFlash->InitParam.TransType == FLASH_INSTRUCT_ADDR_4LINE)
  2687. {
  2688. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_MULTI_ADDR_MULTI,
  2689. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  2690. }
  2691. else
  2692. {
  2693. Hv_Cal_Qspi_SetMultiIOCtrl(pstQspi, QSPI_INSTRU_STAND_ADDR_STAND,
  2694. pstFlash->flashAttr.FlashInstruWidth, 0, 0);
  2695. }
  2696. Hv_Cal_Qspi_MutiIoPollingWrite(pstQspi, &ucSendCmd, 1, &ucSendData, 1, FLASH_TIMEOUT);
  2697. }
  2698. return ucSendData;
  2699. }
  2700. static FlashSelf* Flash_InitParam(FlashInitParam* InitParam)
  2701. {
  2702. QspiSelf* pstQspi = NULL;
  2703. QspiInitParam qspiInitParam;
  2704. UINT32 uiFlashID = 0;
  2705. HV_MEMSET(&qspiInitParam,0, sizeof(qspiInitParam));
  2706. if (InitParam->RateMode == FLASH_QPI)
  2707. {
  2708. InitParam->RateMode = FLASH_QUAD;
  2709. InitParam->TransType = FLASH_INSTRUCT_ADDR_4LINE;
  2710. }
  2711. else if (InitParam->RateMode == FLASH_4XIO)
  2712. {
  2713. InitParam->RateMode = FLASH_QUAD;
  2714. InitParam->TransType = FLASH_ADDR_4LINE;
  2715. }
  2716. else
  2717. {
  2718. InitParam->TransType = FLASH_MULTIIO_FAST_TYPE;
  2719. }
  2720. qspiInitParam.RateMode = (QspiRateMode)InitParam->RateMode;
  2721. qspiInitParam.Direction = QSPI_DIRECTION_TXRX;
  2722. qspiInitParam.CLKPolarity = QSPI_POLARITY_LOW;
  2723. qspiInitParam.CLKPhase = QSPI_PHASE_EDGE1;
  2724. qspiInitParam.DataSize = (QspiBitWidth)(InitParam->DataSize - 1);
  2725. qspiInitParam.CsSel = (QspiCsSel)(InitParam->CsSel);
  2726. //Flash_SetCommonBaudRate(&qspiInitParam,InitParam);
  2727. qspiInitParam.BaudRatePrescaler = QSPI_DIVRATIO_16;
  2728. pstQspi = Hv_Cal_Qspi_Init(&qspiInitParam);
  2729. if(NULL != pstQspi)
  2730. {
  2731. g_stFlash.pstQspi = pstQspi;
  2732. }
  2733. else
  2734. {
  2735. return NULL;
  2736. }
  2737. Hv_Cal_Qspi_SetFlashPoint(pstQspi,(void*)&g_stFlash);
  2738. HV_MEMCPY(&(g_stFlash.InitParam), InitParam, sizeof(*InitParam));
  2739. if (InitParam->FlashCallback != NULL)
  2740. {
  2741. FLASH_SetCpltCallBack(&g_stFlash,InitParam->FlashCallback);
  2742. }
  2743. Hv_Drv_FlashDB_GetAttribute(&(g_stFlash.flashAttr),InitParam->FlashModel);
  2744. if (InitParam->RateMode == FLASH_DUAL)
  2745. {
  2746. Flash_DualFuctionJudge(InitParam->FlashModel);
  2747. }
  2748. uiFlashID = Flash_ReadFlashID();
  2749. g_stFlash.uiFlashID = uiFlashID;
  2750. if (InitParam->RateMode == FLASH_QUAD)
  2751. {
  2752. Flash_FourLineEnable(&g_stFlash,InitParam->FlashModel);
  2753. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi,qspiInitParam.DataSize);
  2754. }
  2755. #ifdef HV_PROJECT_CONFIG_FLASH_PROTECT
  2756. else
  2757. {
  2758. Hv_Cal_Qspi_WP_Init();
  2759. Flash_WriteProtectEnable();
  2760. }
  2761. #endif
  2762. return &g_stFlash;
  2763. }
  2764. static Status Flash_ReInit(FlashSelf* pstFlash, FlashWorkModeSel WorkModeSel,
  2765. FlashRateMode RateMode,FlashDataWidth DataSize)
  2766. {
  2767. QspiSelf* pstQspi = pstFlash->pstQspi;
  2768. QspiInitParam qspiInitParam;
  2769. HV_MEMSET(&qspiInitParam,0, sizeof(qspiInitParam));
  2770. pstFlash->InitParam.WorkModeSel = WorkModeSel;
  2771. pstFlash->InitParam.RateMode = RateMode;
  2772. pstFlash->InitParam.DataSize = DataSize;
  2773. if (pstFlash->InitParam.RateMode == FLASH_QPI)
  2774. {
  2775. pstFlash->InitParam.RateMode = FLASH_QUAD;
  2776. pstFlash->InitParam.TransType = FLASH_INSTRUCT_ADDR_4LINE;
  2777. }
  2778. else if (pstFlash->InitParam.RateMode == FLASH_4XIO)
  2779. {
  2780. pstFlash->InitParam.RateMode = FLASH_QUAD;
  2781. pstFlash->InitParam.TransType = FLASH_ADDR_4LINE;
  2782. }
  2783. else
  2784. {
  2785. pstFlash->InitParam.TransType = FLASH_MULTIIO_FAST_TYPE;
  2786. }
  2787. qspiInitParam.RateMode = (QspiRateMode)RateMode;
  2788. qspiInitParam.DataSize = (QspiBitWidth)(DataSize - 1);
  2789. Flash_SetCommonBaudRate(&qspiInitParam,&pstFlash->InitParam);
  2790. Hv_Cal_Qspi_SetRateMode(pstQspi,qspiInitParam.RateMode);
  2791. Hv_Cal_Qspi_SetFrameBitsWidth(pstQspi,qspiInitParam.DataSize);
  2792. Hv_Cal_Qspi_SetBaudRate(pstQspi,qspiInitParam.BaudRatePrescaler);
  2793. return HV_SUCCESS;
  2794. }
  2795. static Status _Flash_Cleanup(FlashSelf* pstFlash)
  2796. {
  2797. QspiSelf* pstQspi = pstFlash->pstQspi;
  2798. if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2799. {
  2800. Flash_FourLineDisable(pstFlash,pstFlash->InitParam.FlashModel);
  2801. }
  2802. Hv_Cal_Qspi_Cleanup(pstQspi);
  2803. return HV_SUCCESS;
  2804. }
  2805. UINT32 Hv_Drv_Flash_GetFlashID(FlashSelf* pstFlash)
  2806. {
  2807. UINT32 uiFlashID = 0;
  2808. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2809. {
  2810. uiFlashID = Flash_ReadID_Standard(pstFlash);
  2811. }
  2812. else if ((pstFlash->InitParam.RateMode == FLASH_DUAL)
  2813. || (pstFlash->InitParam.RateMode == FLASH_QUAD))
  2814. {
  2815. uiFlashID = Flash_ReadID_MutiIO(pstFlash);
  2816. }
  2817. return uiFlashID;
  2818. }
  2819. static Status _Flash_Erase(FlashSelf* pstFlash, FlashEraseType enEraseType,UINT32 uiEraseAddr)
  2820. {
  2821. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2822. {
  2823. Flash_EraseStandard(pstFlash, enEraseType, uiEraseAddr);
  2824. }
  2825. else if ((pstFlash->InitParam.RateMode == FLASH_DUAL)
  2826. || (pstFlash->InitParam.RateMode == FLASH_QUAD))
  2827. {
  2828. Flash_EraseMultiIo(pstFlash, enEraseType, uiEraseAddr);
  2829. }
  2830. return HV_SUCCESS;
  2831. }
  2832. static Status _Flash_Write(FlashSelf* pstFlash, UINT32 uiWtAddr, UCHAR8* pucTxData, UINT32 uiTxSize)
  2833. {
  2834. if (pstFlash->InitParam.WorkModeSel == FLASH_USE_POLLING)
  2835. {
  2836. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2837. {
  2838. Flash_SendStandard(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2839. }
  2840. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2841. {
  2842. Flash_SendDual(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2843. }
  2844. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2845. {
  2846. Flash_SendQuad(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2847. }
  2848. }
  2849. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_INT)
  2850. {
  2851. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2852. {
  2853. Flash_SendStandardInt(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2854. }
  2855. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2856. {
  2857. Flash_SendDualInt(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2858. }
  2859. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2860. {
  2861. Flash_SendQuadInt(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2862. }
  2863. }
  2864. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_DMA)
  2865. {
  2866. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2867. {
  2868. Flash_SendStandardDma(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2869. }
  2870. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2871. {
  2872. Flash_SendDualDma(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2873. }
  2874. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2875. {
  2876. Flash_SendQuadDma(pstFlash, uiWtAddr, pucTxData, uiTxSize);
  2877. }
  2878. }
  2879. return HV_SUCCESS;
  2880. }
  2881. static Status _Flash_Read(FlashSelf* pstFlash, UINT32 uiRdAddr, UCHAR8* pucRxData, UINT32 uiRxSize)
  2882. {
  2883. if (pstFlash->InitParam.WorkModeSel == FLASH_USE_POLLING)
  2884. {
  2885. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2886. {
  2887. Flash_RecvStandard(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2888. }
  2889. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2890. {
  2891. Flash_RecvDual(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2892. }
  2893. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2894. {
  2895. Flash_RecvQuad(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2896. }
  2897. }
  2898. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_INT)
  2899. {
  2900. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2901. {
  2902. Flash_RecvStandardInt(pstFlash, uiRdAddr, pucRxData,uiRxSize);
  2903. }
  2904. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2905. {
  2906. Flash_RecvDualInt(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2907. }
  2908. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2909. {
  2910. Flash_RecvQuadInt(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2911. }
  2912. }
  2913. else if (pstFlash->InitParam.WorkModeSel == FLASH_USE_DMA)
  2914. {
  2915. if (pstFlash->InitParam.RateMode == FLASH_STANDARD)
  2916. {
  2917. Flash_RecvStandardDma(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2918. }
  2919. else if (pstFlash->InitParam.RateMode == FLASH_DUAL)
  2920. {
  2921. Flash_RecvDualDma(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2922. }
  2923. else if (pstFlash->InitParam.RateMode == FLASH_QUAD)
  2924. {
  2925. Flash_RecvQuadDma(pstFlash, uiRdAddr, pucRxData, uiRxSize);
  2926. }
  2927. }
  2928. return HV_SUCCESS;
  2929. }
  2930. BOOL Hv_Drv_Flash_TransferIsComplete(FlashSelf *pstFlash)
  2931. {
  2932. QspiSelf* pstQspi = pstFlash->pstQspi;
  2933. return Hv_Cal_Qspi_TransferIsComplete(pstQspi);
  2934. }
  2935. static void Flash_Swap32(UCHAR8* pucSrc, UINT32 uiLength)
  2936. {
  2937. UINT32 uiLoop = 0;
  2938. if ((uiLength % 4) != 0)
  2939. {
  2940. return;
  2941. }
  2942. for (uiLoop = 0; uiLoop < uiLength / 4; uiLoop++)
  2943. {
  2944. *((UINT32 *)(pucSrc + uiLoop * 4)) = HV_SWAP32(*((UINT32 *)(pucSrc + uiLoop * 4)));
  2945. }
  2946. return;
  2947. }
  2948. static void Flash_TxDmaInit(void)
  2949. {
  2950. QspiSelf *pstQspi = Flash_GetQspi(g_pFlash);
  2951. DmaSelf* pstTxDma = NULL;
  2952. DmaInitParam TxInitParam;
  2953. Hv_Vos_Memset(&TxInitParam, 0, sizeof(DmaInitParam));
  2954. TxInitParam.PortChannelNum = DMA_PORT0_CHANNEL0;
  2955. TxInitParam.Application = DMA_APPLI_QSPI0_TX;
  2956. TxInitParam.transType = DMA_TYPE_SINGLE;
  2957. pstTxDma = Hv_Cal_Dma_ChannelInit(&TxInitParam);
  2958. Hv_Cal_Qspi_SetDmaTx(pstQspi, pstTxDma);
  2959. return;
  2960. }
  2961. static void Flash_RxDmaInit(void)
  2962. {
  2963. QspiSelf *pstQspi = Flash_GetQspi(g_pFlash);
  2964. DmaSelf* pstRxDma = NULL;
  2965. DmaInitParam RxInitParam;
  2966. Hv_Vos_Memset(&RxInitParam, 0, sizeof(DmaInitParam));
  2967. RxInitParam.PortChannelNum = DMA_PORT0_CHANNEL1;
  2968. RxInitParam.Application = DMA_APPLI_QSPI0_RX;
  2969. RxInitParam.transType = DMA_TYPE_SINGLE;
  2970. pstRxDma = Hv_Cal_Dma_ChannelInit(&RxInitParam);
  2971. Hv_Cal_Qspi_SetDmaRx(pstQspi,pstRxDma);
  2972. return;
  2973. }
  2974. static void Flash_Program(UINT32 uiWriteAddr, UCHAR8* pucWriteBuf, UINT32 uiLength)
  2975. {
  2976. FlashTxMem stFlashMem;
  2977. Hv_Vos_Memset(&stFlashMem, 0, sizeof(FlashTxMem));
  2978. if (((uiLength % 4) != 0) || (uiLength > PAGE_WRITE))
  2979. {
  2980. return;
  2981. }
  2982. if (g_ucDmaUseFlag == HV_TRUE)
  2983. {
  2984. Hv_Vos_Memcpy((UCHAR8 *)stFlashMem.txData, (UCHAR8*)pucWriteBuf, uiLength);
  2985. if (Flash_GetDataSize(g_pFlash) == FLASH_DATAWIDTH_32)
  2986. {
  2987. Flash_Swap32((UCHAR8 *)stFlashMem.txData,uiLength);
  2988. }
  2989. _Flash_Write(g_pFlash, uiWriteAddr, (UCHAR8 *)stFlashMem.txData, uiLength);
  2990. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash) == HV_FALSE);
  2991. }
  2992. else if (g_ucIntUseFlag == HV_TRUE)
  2993. {
  2994. _Flash_Write(g_pFlash, uiWriteAddr, pucWriteBuf, uiLength);
  2995. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash) == HV_FALSE);
  2996. }
  2997. else
  2998. {
  2999. _Flash_Write(g_pFlash, uiWriteAddr, pucWriteBuf, uiLength);
  3000. }
  3001. return;
  3002. }
  3003. static void Flash_Read(UINT32 uiReadAddr, UCHAR8 *pucReadBuf, UINT32 uiLength)
  3004. {
  3005. if (((uiLength % 4) != 0) ||(uiLength > PAGE_READ))
  3006. {
  3007. return;
  3008. }
  3009. if (g_ucDmaUseFlag == HV_TRUE)
  3010. {
  3011. _Flash_Read(g_pFlash, uiReadAddr, g_ucReadBuf, uiLength);
  3012. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash)== HV_FALSE);
  3013. Hv_Vos_MSleep(1);
  3014. if (Flash_GetRateMode(g_pFlash) == FLASH_STANDARD)
  3015. {
  3016. Hv_Vos_Memcpy(pucReadBuf, &g_ucReadBuf[4], uiLength);
  3017. }
  3018. else
  3019. {
  3020. Hv_Vos_Memcpy(pucReadBuf, g_ucReadBuf, uiLength);
  3021. }
  3022. if (Flash_GetDataSize(g_pFlash) == FLASH_DATAWIDTH_32)
  3023. {
  3024. Flash_Swap32(pucReadBuf,uiLength);
  3025. }
  3026. }
  3027. else if (g_ucIntUseFlag == HV_TRUE)
  3028. {
  3029. _Flash_Read(g_pFlash, uiReadAddr, pucReadBuf, uiLength);
  3030. while (Hv_Drv_Flash_TransferIsComplete(g_pFlash)== HV_FALSE);
  3031. }
  3032. else
  3033. {
  3034. _Flash_Read(g_pFlash,uiReadAddr, pucReadBuf, uiLength);
  3035. }
  3036. return;
  3037. }
  3038. static void Flash_OnlyErase(UINT32 uiEraseAddr, UINT32 uiLength)
  3039. {
  3040. UINT32 uiLoop = 0;
  3041. for (uiLoop = 0;
  3042. uiLoop < (uiLength % ERASE_TYPE_SIZE == 0 ? (uiLength / ERASE_TYPE_SIZE) : (uiLength / ERASE_TYPE_SIZE + 1));
  3043. uiLoop++)
  3044. {
  3045. _Flash_Erase(g_pFlash, ERASE_TYPE, uiEraseAddr + uiLoop * ERASE_TYPE_SIZE);
  3046. }
  3047. }
  3048. static void Flash_OnlyEraseMultiSector(UINT32 uiEraseAddr)
  3049. {
  3050. _Flash_Erase(g_pFlash, FLASH_ERASE_MULTI_SECTOR, uiEraseAddr);
  3051. }
  3052. static Status Flash_Check(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength)
  3053. {
  3054. UINT32 uiLoop = 0;
  3055. UCHAR8 ucReadCrc = 0;
  3056. UCHAR8 ucWriteCrc = 0;
  3057. Flash_OnlyRead(uiWriteAddr, g_ucReadBuf, uiLength);
  3058. for (uiLoop = 0; uiLoop < uiLength; uiLoop++)
  3059. {
  3060. if (*pucWriteBuf != g_ucReadBuf[uiLoop])
  3061. {
  3062. HV_LOGI("[%2x]:need %x, act %x", uiLoop, *pucWriteBuf, g_ucReadBuf[uiLoop]);
  3063. return HV_FAILURE;
  3064. }
  3065. pucWriteBuf++;
  3066. }
  3067. return HV_SUCCESS;
  3068. }
  3069. static Status Flash_OnlyWrite(UINT32 uiWriteAddr, UCHAR8 *pucWriteBuf, UINT32 uiLength)
  3070. {
  3071. UINT32 uiLoop = 0;
  3072. UINT32 uiRemain = 0;
  3073. UINT32 uiTempLen = 0;
  3074. UINT32 uiTempAdd = 0;
  3075. UINT32 uiRetry = 3;
  3076. Status uiRet = HV_SUCCESS;
  3077. UCHAR8* pucTmpUseWriteBuf = g_ucWriteBuf;
  3078. HV_MEMSET(pucTmpUseWriteBuf, 0xff, PAGE_WRITE);
  3079. for (uiLoop=0; uiLoop< uiLength / PAGE_WRITE; uiLoop++)
  3080. {
  3081. Hv_Vos_Memcpy(pucTmpUseWriteBuf, (UCHAR8 *)((UINT32)pucWriteBuf + uiLoop * PAGE_WRITE), PAGE_WRITE);
  3082. Hv_Vos_InvalidAllDCache();
  3083. uiTempAdd = uiWriteAddr + uiLoop * PAGE_WRITE;
  3084. uiRetry = 1;
  3085. do
  3086. {
  3087. Flash_Program(uiTempAdd, pucTmpUseWriteBuf, PAGE_WRITE);
  3088. if (HV_SUCCESS == Flash_Check(uiTempAdd, pucTmpUseWriteBuf, PAGE_WRITE))
  3089. {
  3090. break;
  3091. }
  3092. HV_LOGV("flash write retry...\n");
  3093. uiRetry--;
  3094. } while (uiRetry);
  3095. if (0 == uiRetry)
  3096. {
  3097. uiRet = HV_FAILURE;
  3098. HV_LOGE("flash write fail address %x\n", uiTempAdd);
  3099. }
  3100. }
  3101. uiRemain = uiLength % PAGE_WRITE;
  3102. if ((uiRemain > 0) && (uiRet == HV_SUCCESS))
  3103. {
  3104. uiTempLen = (uiRemain % 4 == 0) ? (uiRemain / 4) : (uiRemain / 4 + 1);
  3105. Hv_Vos_Memcpy(pucTmpUseWriteBuf,
  3106. (UCHAR8 *)((UINT32)pucWriteBuf + (uiLength / PAGE_WRITE) * PAGE_WRITE),
  3107. uiRemain);
  3108. Hv_Vos_InvalidAllDCache();
  3109. uiRetry = 1;
  3110. uiTempAdd = uiWriteAddr + (uiLength / PAGE_WRITE) * PAGE_WRITE;
  3111. do
  3112. {
  3113. Flash_Program(uiTempAdd, pucTmpUseWriteBuf, uiTempLen * 4);
  3114. if (HV_SUCCESS == Flash_Check(uiTempAdd, pucTmpUseWriteBuf, uiTempLen * 4))
  3115. {
  3116. break;
  3117. }
  3118. HV_LOGV("flash write retry...\n");
  3119. } while ((uiRetry--) > 0);
  3120. if (0 == uiRetry)
  3121. {
  3122. uiRet = HV_FAILURE;
  3123. HV_LOGE("flash write fail address %x\n", uiTempAdd);
  3124. }
  3125. }
  3126. return uiRet;
  3127. }
  3128. static void Flash_OnlyRead(UINT32 uiReadAddr, UCHAR8* pucReadBuf, UINT32 uiLength)
  3129. {
  3130. UINT32 uiLoop = 0;
  3131. UINT32 uiRemain = 0;
  3132. UINT32 uiTempLen = 0;
  3133. UINT32 readCount = 0;
  3134. HV_MEMSET(g_ucReadBuf, 0xff, PAGE_READ);
  3135. Hv_Vos_InvalidAllDCache();
  3136. for (uiLoop=0; uiLoop < uiLength / PAGE_READ; uiLoop++)
  3137. {
  3138. Flash_Read(uiReadAddr + uiLoop * PAGE_READ,
  3139. (UCHAR8*)((UINT32)pucReadBuf + uiLoop * PAGE_READ), PAGE_READ);
  3140. readCount = readCount + PAGE_READ;
  3141. }
  3142. uiRemain = uiLength % PAGE_READ;
  3143. if (uiRemain > 0)
  3144. {
  3145. if (g_ucDmaUseFlag == HV_TRUE)
  3146. {
  3147. uiTempLen = (uiRemain % 32 == 0)?(uiRemain):(uiRemain / 32 + 1) * 32;
  3148. }
  3149. else
  3150. {
  3151. uiTempLen = (uiRemain % 4 == 0) ? (uiRemain) : (uiRemain / 4 + 1) * 4;
  3152. }
  3153. Flash_Read(uiReadAddr + readCount, (UCHAR8*)g_ucReadBuf, uiTempLen);
  3154. Hv_Vos_InvalidAllDCache();
  3155. Hv_Vos_Memcpy((UCHAR8*)((UINT32)pucReadBuf + readCount), g_ucReadBuf, uiRemain);
  3156. Hv_Vos_InvalidAllDCache();
  3157. }
  3158. return;
  3159. }
  3160. static BOOL Flash_EraseWrite(UINT32 uiWriteAddr, UCHAR8* pucWriteBuf, UINT32 uiLength)
  3161. {
  3162. UINT32 uiTempVal = 0;
  3163. UINT32 uiFirstWriteSize = 0;
  3164. UINT32 uiTempLen = uiLength;
  3165. UCHAR8* pucWbuf = (UCHAR8*)pucWriteBuf;
  3166. UCHAR8* pucTmpUseBuf = g_ucSectorBuf;
  3167. UINT32 uiWaddr = uiWriteAddr;
  3168. UINT32 uiCount = 0;
  3169. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3170. uiTempVal = uiWaddr & 0xfff;
  3171. if ((uiTempVal) != 0)
  3172. {
  3173. if ((uiTempVal +uiTempLen) < SECTOR_SIZE)
  3174. {
  3175. HV_MEMSET(pucTmpUseBuf, 0xff, SECTOR_SIZE);
  3176. Hv_Vos_InvalidAllDCache();
  3177. Flash_OnlyRead(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3178. Hv_Vos_Memcpy(&pucTmpUseBuf[uiTempVal],pucWbuf, uiTempLen);
  3179. Hv_Vos_InvalidAllDCache();
  3180. Flash_OnlyErase(uiWaddr & (~0xfff), SECTOR_SIZE);
  3181. Flash_OnlyWrite(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3182. uiTempLen = 0;
  3183. }
  3184. else
  3185. {
  3186. uiFirstWriteSize = SECTOR_SIZE - uiTempVal;
  3187. Flash_OnlyRead(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3188. Hv_Vos_Memcpy(&pucTmpUseBuf[uiTempVal],pucWbuf, uiFirstWriteSize);
  3189. Hv_Vos_InvalidAllDCache();
  3190. Flash_OnlyErase(uiWaddr & (~0xfff), SECTOR_SIZE);
  3191. Flash_OnlyWrite(uiWaddr & (~0xfff), pucTmpUseBuf, SECTOR_SIZE);
  3192. uiTempLen = uiTempLen - uiFirstWriteSize;
  3193. uiWaddr = (uiWaddr & (~0xfff)) + SECTOR_SIZE;
  3194. pucWbuf = pucWbuf + uiFirstWriteSize;
  3195. }
  3196. }
  3197. while ((uiTempLen > SECTOR_SIZE) || (uiTempLen == SECTOR_SIZE))
  3198. {
  3199. uiTempLen = uiTempLen- SECTOR_SIZE;
  3200. uiCount++;
  3201. }
  3202. while (uiCount-- > 0)
  3203. {
  3204. Flash_OnlyErase(uiWaddr, SECTOR_SIZE * uiCount);
  3205. Flash_OnlyWrite(uiWaddr, pucWbuf, SECTOR_SIZE * uiCount);
  3206. uiWaddr = uiWaddr + SECTOR_SIZE * uiCount;
  3207. pucWbuf = pucWbuf + SECTOR_SIZE * uiCount;
  3208. }
  3209. if (uiTempLen > 0)
  3210. {
  3211. Flash_OnlyRead(uiWaddr, pucTmpUseBuf, SECTOR_SIZE);
  3212. Hv_Vos_Memcpy(pucTmpUseBuf, pucWbuf, uiTempLen);
  3213. Hv_Vos_InvalidAllDCache();
  3214. Flash_OnlyErase(uiWaddr, SECTOR_SIZE);
  3215. Flash_OnlyWrite(uiWaddr, pucTmpUseBuf, SECTOR_SIZE); //tmp fix
  3216. }
  3217. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3218. return HV_SUCCESS;
  3219. }
  3220. static void Flash_Init(FlashModel FlashModel, FlashRateMode RateMode, FlashWorkModeSel workMode)
  3221. {
  3222. FlashInitParam InitParam;
  3223. InitParam.WorkModeSel = workMode;
  3224. InitParam.FlashModel = FlashModel;
  3225. InitParam.RateMode = RateMode;
  3226. InitParam.FlashCallback = NULL;
  3227. InitParam.CsSel = FLASH_CS_BY_GPIO;
  3228. if (InitParam.FlashModel == FLASH_MX25)
  3229. {
  3230. InitParam.AddrWidth = FLASH_ADDRESS_WIDTH_32;
  3231. if (InitParam.RateMode == FLASH_STANDARD)
  3232. {
  3233. InitParam.DataSize = FLASH_DATAWIDTH_8;
  3234. }
  3235. else if (InitParam.RateMode == FLASH_4XIO)
  3236. {
  3237. InitParam.DataSize = FLASH_DATAWIDTH_32;
  3238. }
  3239. else
  3240. {
  3241. HV_LOGI("MX25:Init config erro.\n");
  3242. HV_ASSERT(0);
  3243. }
  3244. }
  3245. else if (InitParam.FlashModel == FLASH_GD25)
  3246. {
  3247. InitParam.AddrWidth = FLASH_ADDRESS_WIDTH_24;
  3248. InitParam.DataSize = FLASH_DATAWIDTH_32;
  3249. if ((InitParam.RateMode != FLASH_STANDARD)
  3250. && (InitParam.RateMode != FLASH_DUAL)
  3251. && (InitParam.RateMode != FLASH_QUAD))
  3252. {
  3253. HV_LOGI("GD25:Init config erro.\n");
  3254. HV_ASSERT(0);
  3255. }
  3256. }
  3257. else
  3258. {
  3259. InitParam.FlashModel = FLASH_MT25;
  3260. InitParam.AddrWidth = FLASH_ADDRESS_WIDTH_24;
  3261. InitParam.DataSize = FLASH_DATAWIDTH_32;
  3262. if ((InitParam.RateMode != FLASH_STANDARD)
  3263. && (InitParam.RateMode != FLASH_DUAL)
  3264. && (InitParam.RateMode != FLASH_QUAD))
  3265. {
  3266. HV_LOGI("MT25:Init config erro.\n");
  3267. HV_ASSERT(0);
  3268. }
  3269. }
  3270. g_pFlash = Flash_InitParam(&InitParam);
  3271. if (InitParam.WorkModeSel == FLASH_USE_DMA)
  3272. {
  3273. Flash_TxDmaInit();
  3274. Flash_RxDmaInit();
  3275. g_ucDmaUseFlag = HV_TRUE;
  3276. g_ucIntUseFlag = HV_FALSE;
  3277. }
  3278. else if (InitParam.WorkModeSel == FLASH_USE_INT)
  3279. {
  3280. g_ucDmaUseFlag = HV_FALSE;
  3281. g_ucIntUseFlag = HV_TRUE;
  3282. }
  3283. else if (InitParam.WorkModeSel == FLASH_USE_POLLING)
  3284. {
  3285. g_ucDmaUseFlag = HV_FALSE;
  3286. g_ucIntUseFlag = HV_FALSE;
  3287. }
  3288. return;
  3289. }
  3290. static void Flash_CleanUp(void)
  3291. {
  3292. if (g_pFlash != NULL)
  3293. {
  3294. _Flash_Cleanup(g_pFlash);
  3295. g_pFlash = NULL;
  3296. }
  3297. }
  3298. /**
  3299. * @brief write config data to flash.
  3300. * @param uiAddress write offset at flash
  3301. * @param pucData address write data to
  3302. * @param uiDataSize write data size
  3303. * @retval Status
  3304. */
  3305. Status Hv_Drv_Flash_WriteMonitorData(UINT32 uiAddress, UCHAR8 *pucData, UINT32 uiDataSize)
  3306. {
  3307. Status sRet = HV_FAILURE;
  3308. HV_LOGV("_Flash_Write uiAddress=%x,pucData=%x, uiDataSize= %d", uiAddress, pucData, uiDataSize);
  3309. Flash_WriteProtectDisable(uiAddress);
  3310. if (uiAddress >= HV_FLASH_CONFIG_MONITOR_DATA_PART_START)
  3311. {
  3312. sRet = Flash_EraseWrite(uiAddress, pucData, uiDataSize);
  3313. }
  3314. Flash_WriteProtectEnable();
  3315. return sRet;
  3316. }
  3317. /**
  3318. * @brief read data from flash.
  3319. * @param uiAddress read offset at flash
  3320. * @param pucData address for read data
  3321. * @param uiDataSize size to read data
  3322. * @retval Status
  3323. */
  3324. Status Hv_Drv_Flash_ReadMonitorData(UINT32 uiAddress, UCHAR8 *pucData, UINT32 uiDataSize)
  3325. {
  3326. HV_LOGV("_Flash_Read uiAddress=%x,pucData=0x%x, uiDataSize=%d", uiAddress, pucData, uiDataSize);
  3327. if (uiAddress >= HV_FLASH_CONFIG_LOGO_PART_START)
  3328. {
  3329. Flash_OnlyRead(uiAddress, pucData, uiDataSize);
  3330. return HV_SUCCESS;
  3331. }
  3332. return HV_FAILURE;
  3333. }
  3334. /**
  3335. * @brief read data from flash in xip mode.
  3336. * @param uiAddress read offset at flash
  3337. * @param pucData address for read data
  3338. * @param uiDataSize size to read data
  3339. * @retval Status
  3340. */
  3341. Status Hv_Drv_Flash_ReadXIP(UINT32 uiAddress, UCHAR8 *pucData, UINT32 uiDataSize)
  3342. {
  3343. UINT32 iLoop = 0;
  3344. HV_LOGV("Hv_Drv_Flash_ReadXIP uiAddress=%x,pucData=0x%x, uiDataSize=%d", uiAddress, pucData, uiDataSize);
  3345. {
  3346. for (iLoop = 0; iLoop < uiDataSize; iLoop++)
  3347. {
  3348. *pucData = *((UCHAR8 *)(uiAddress + HV_FLASH_CONFIG_START_XIP + iLoop));
  3349. pucData++;
  3350. }
  3351. }
  3352. return HV_SUCCESS;
  3353. }
  3354. /**
  3355. * @brief int flash interface.
  3356. */
  3357. void Hv_Drv_Flash_SetQspiMode(FlashModel FlashModel, FlashRateMode RateMode, FlashWorkModeSel workMode)
  3358. {
  3359. g_pstFlashSeamphone = Hv_Vos_InitSemaphore(1, 1);
  3360. Flash_CleanUp();
  3361. Flash_Init(FlashModel, RateMode, workMode);
  3362. }
  3363. /**
  3364. * @brief deint flash interface.
  3365. */
  3366. void Hv_Drv_Flash_SetXipMode(void)
  3367. {
  3368. Flash_CleanUp();
  3369. return;
  3370. }
  3371. /**
  3372. * @brief config logo data and pq etc data partition flag
  3373. */
  3374. void Hv_Drv_Flash_ConfigPartFlag(void)
  3375. {
  3376. #ifdef SW_DUMMY_DEBUG
  3377. /* add flash partition config */
  3378. HV_WT32(SW_DUMMY_LOGO, HV_FLASH_CONFIG_LOGO_PART_START);
  3379. HV_WT32(SW_DUMMY_CONFIG_DATA, HV_FLASH_CONFIG_MONITOR_DATA_PART_START);
  3380. HV_WT32(SW_DUMMY_PQ_DATA, HV_FLASH_CONFIG_PQ_DATA_PART_START);
  3381. #endif
  3382. return;
  3383. }
  3384. /**
  3385. * @brief erase flash.
  3386. * @param[in] uiWriteAddr Address of flash to do erase.
  3387. * @param[in] uiLength Date length to be written.
  3388. * @return None
  3389. */
  3390. void Hv_Drv_Flash_OnlyErase(UINT32 uiReadAddr, UINT32 uiLength)
  3391. {
  3392. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3393. Flash_WriteProtectDisable(uiReadAddr);
  3394. Flash_OnlyErase(uiReadAddr, uiLength);
  3395. Flash_WriteProtectEnable();
  3396. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3397. return;
  3398. }
  3399. /**
  3400. * @brief Erase flash by a 64K Bytes(Multi Sector) length.
  3401. Warning: Always erase 64K bytes, please be sure to keep your data safe.
  3402. * @param[in] uiAddr Address of flash to do erase.
  3403. * @return None
  3404. */
  3405. void Hv_Drv_Flash_OnlyEraseMultiSector(UINT32 uiAddr)
  3406. {
  3407. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3408. Flash_WriteProtectDisable(uiAddr);
  3409. Flash_OnlyEraseMultiSector(uiAddr);
  3410. Flash_WriteProtectEnable();
  3411. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3412. return;
  3413. }
  3414. /**
  3415. * @brief Write flash.
  3416. * @param[in] uiWriteAddr Address of flash to do write.
  3417. * @param[in] pucWriteBuf Date buffer to be written.
  3418. * @param[in] uiLength Date length to be written.
  3419. * @return None
  3420. */
  3421. Status Hv_Drv_Flash_OnlyWrite(UINT32 uiWriteAddr, UCHAR8* pucWriteBuf, UINT32 uiLength)
  3422. {
  3423. UINT32 uiPreIdx = 0;
  3424. UINT32 uiPreDat = 0;
  3425. Status uiRet = HV_SUCCESS;
  3426. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3427. Flash_WriteProtectDisable(uiWriteAddr);
  3428. uiPreIdx = uiWriteAddr % PAGE_WRITE;
  3429. HV_LOGV("Hv_Drv_Flash_OnlyWrite uiWriteAddr %x uiPreIdx %x, length %d\n", uiWriteAddr, uiPreIdx,uiLength);
  3430. if (uiPreIdx)
  3431. {
  3432. uiPreDat = PAGE_WRITE - uiPreIdx;
  3433. if (uiLength < uiPreDat)
  3434. {
  3435. uiPreDat = uiLength;
  3436. }
  3437. HV_MEMSET(g_ucReadBuf, 0xff, PAGE_READ);
  3438. HV_MEMSET(g_ucWriteBuf, 0xff, PAGE_READ);
  3439. Hv_Vos_InvalidAllDCache();
  3440. uiWriteAddr &= ~0xff;
  3441. Flash_OnlyRead(uiWriteAddr, g_ucReadBuf, uiPreIdx);
  3442. Hv_Vos_Memcpy(&g_ucReadBuf[uiPreIdx], pucWriteBuf, uiPreDat);
  3443. uiRet = Flash_OnlyWrite(uiWriteAddr, g_ucReadBuf, PAGE_WRITE);
  3444. uiLength = uiLength - uiPreDat;
  3445. uiWriteAddr += PAGE_WRITE;
  3446. pucWriteBuf += uiPreDat;
  3447. }
  3448. if ((uiLength > 0) && (uiRet == HV_SUCCESS))
  3449. {
  3450. uiRet = Flash_OnlyWrite(uiWriteAddr, pucWriteBuf, uiLength);
  3451. }
  3452. Flash_WriteProtectEnable();
  3453. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3454. return uiRet;
  3455. }
  3456. /**
  3457. * @brief Write flash.
  3458. * @param[in] uiReadAddr Address of flash to do read.
  3459. * @param[in] pucReadBuf Buffer for saving read back data.
  3460. * @param[in] uiLength Date length to be read.
  3461. * @return None
  3462. */
  3463. void Hv_Drv_Flash_OnlyRead(UINT32 uiReadAddr, UCHAR8* pucReadBuf, UINT32 uiLength)
  3464. {
  3465. UINT32 uiPreIdx = 0;
  3466. UINT32 uiPreDat = 0;
  3467. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3468. HV_MEMSET(g_ucReadBuf, 0xff, PAGE_READ);
  3469. Hv_Vos_InvalidAllDCache();
  3470. uiPreIdx = uiReadAddr % PAGE_READ;
  3471. HV_LOGV("Hv_Drv_Flash_OnlyRead uiReadAddr %x uiPreIdx %x, length %d\n", uiReadAddr, uiPreIdx,uiLength);
  3472. if (uiPreIdx)
  3473. {
  3474. uiPreDat = PAGE_READ - uiPreIdx;
  3475. uiReadAddr &= ~0xff;
  3476. if (uiLength < uiPreDat)
  3477. {
  3478. uiPreDat = uiLength;
  3479. }
  3480. Flash_OnlyRead(uiReadAddr, g_ucReadBuf, PAGE_READ);
  3481. Hv_Vos_Memcpy(pucReadBuf, g_ucReadBuf+uiPreIdx, uiPreDat);
  3482. uiLength = uiLength - uiPreDat;
  3483. uiReadAddr += PAGE_READ;
  3484. pucReadBuf += uiPreDat;
  3485. }
  3486. if (uiLength > 0)
  3487. {
  3488. Flash_OnlyRead(uiReadAddr, pucReadBuf, uiLength);
  3489. }
  3490. Hv_Vos_ReleaseSemaphore(g_pstFlashSeamphone);
  3491. return;
  3492. }
  3493. /**
  3494. * @brief whether w/r is ongoing.
  3495. * @return w/r state
  3496. */
  3497. UCHAR8 Hv_Drv_Flash_InWritting(void)
  3498. {
  3499. Hv_Vos_AcquireSemaphore(g_pstFlashSeamphone);
  3500. return 0;
  3501. }
  3502. /**
  3503. * @brief Flash chip erase.
  3504. * @param[in] None.
  3505. * @return None
  3506. */
  3507. void Hv_Drv_Flash_EraseChip(void)
  3508. {
  3509. Hv_Drv_Flash_ProtectDisable();
  3510. _Flash_Erase(g_pFlash, FLASH_ERASE_CHIP, 0);
  3511. Flash_WriteProtectEnable();
  3512. }