hv_app_DdcciFactory.h 10 KB

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  1. /*
  2. * @file hv_app_DdcciFactory.h
  3. * @brief Header file of hisense ddcci factory.
  4. *
  5. * @verbatim
  6. * ==============================================================================
  7. * ##### How to use #####
  8. * ==============================================================================
  9. * (+) Use
  10. *
  11. * @author HiView SoC Software Team
  12. * @version 1.0.0
  13. * @date 2023-12-20
  14. */
  15. #ifndef _HV_APP_DDCCI_HISENSE_FACTORY_H
  16. #define _HV_APP_DDCCI_HISENSE_FACTORY_H
  17. #include "hv_comm_DataType.h"
  18. #include "hv_vos_Comm.h"
  19. #include "hv_comm_Define.h"
  20. /*
  21. Standard Examples
  22. Read:
  23. ddc cmd: [7] = 51 84 01 f8 e1 54 f7
  24. ddc send long [11] = 6e 88 02 00 f8 00 00 00 00 00 4c
  25. Read:
  26. ddc cmd: [6] = 51 83 f3 01 04 4a
  27. ddc send long [32] =
  28. 00000000: 6e 9d e3 01 04 20 38 30 20 38 31 20 38 32 20 38
  29. 00000010: 33 20 38 34 20 38 35 20 38 36 20 38 37 20 38 5d
  30. Set:
  31. ddc cmd: [9] = 51 86 03 f8 e1 59 00 01 fb
  32. */
  33. //Read Reg: 51 CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb StartBit StopBit Crc (LenH LenL: 00 09)
  34. //response: 6E CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb StartBit StopBit ValMsb Val2nd Val3rd ValLsb Crc (LenH LenL: 00 0D)
  35. //Write Reg: 51 CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb StartBit StopBit ValMsb Val2nd Val3rd ValLsb Crc (LenH LenL: 00 0D)
  36. //response: 6E CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb StartBit StopBit RC Crc (LenH LenL: 00 0A)
  37. //Read DDR: 51 CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb ReadLenH ReadLenL Crc (LenH LenL: 00 09)
  38. //response: 6E CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb ReadLenH ReadLenL Data[ReadLen] Crc (LenH LenL: ReadLen + 9, Total:ReadLen + 9 + 4)
  39. //Write DDR: 51 CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb Data[WriteLen] Crc (LenH LenL: WriteLen + 7 + 4)
  40. //response: 6E CmdType CmdH CmdL LenH LenL AddrMsb Addr2nd Addr3rd AddrLsb RC Crc (LenH LenL: 00 08)
  41. //PQ CMD Read: 51 CmdType CmdH CmdL LenH LenL Crc (LenH LenL: 00 03)
  42. //response: 6E CmdType CmdH CmdL LenH LenL ValMsb Val2nd Val3rd ValLsb Crc (LenH LenL: 00 07)
  43. //PQ CMD Write: 51 CmdType CmdH CmdL LenH LenL ValMsb Val2nd Val3rd ValLsb Crc
  44. //response: 6E CmdType CmdH CmdL LenH LenL RC Crc (LenH LenL: 00 04)
  45. //PQ CMD Write Long: 51 CmdType CmdH CmdL LenH LenL Data[WriteLen] Crc
  46. //response: 6E CmdType CmdH CmdL LenH LenL RC Crc (LenH LenL: 00 04)
  47. //Write GammaLut: 51 CmdType CmdH CmdL LenH LenL Data[3 * 1025] Crc (LenH LenL: 3 * 1025 * 4 + 3)
  48. //response: 6E CmdType CmdH CmdL LenH LenL RC Crc (LenH LenL: 00 04)
  49. //Write Gamma Unit: 51 CmdType CmdH CmdL LenH LenL Val0 Val1 Val2 Val3 Row ColH ColL Crc
  50. //response: 6E CmdType CmdH CmdL LenH LenL RC Crc (LenH LenL: 00 04)
  51. #define DDCCI_FAC_RC_SUCCESS 0xE0
  52. #define DDCCI_FAC_RC_FAIL 0xCC
  53. #define DDCCI_FAC_DDC_HEADER_LEN 4 // 51 LenH LenL + CRC
  54. #define DDCCI_FAC_DDC_CMD_LEN 3 // CmdType CmdH CmdL
  55. #define DDCCI_FAC_DDC_CMD_FIX_LEN 7 // CmdType CmdH CmdL AddrMsb Addr2nd Addr3rd AddrLsb
  56. #define DDCCI_FAC_READ_REG_RSP_LEN 17
  57. #define DDCCI_FAC_WRITE_REG_RSP_LEN 14
  58. #define DDCCI_FAC_WRITE_DDR_RSP_LEN 12
  59. #define DDCCI_FAC_READ_PQ_CMD_RSP_LEN 11
  60. #define DDCCI_FAC_WRITE_PQ_CMD_RSP_LEN 8
  61. #define DDCCI_FAC_OFFSET_SRC 0 // 0x51
  62. #define DDCCI_FAC_OFFSET_CMD_TYPE 1
  63. #define DDCCI_FAC_OFFSET_CMD_HIGH 2
  64. #define DDCCI_FAC_OFFSET_CMD_LOW 3
  65. #define DDCCI_FAC_OFFSET_ADDR_MSB 6
  66. #define DDCCI_FAC_OFFSET_ADDR_2ND 7
  67. #define DDCCI_FAC_OFFSET_ADDR_3RD 8
  68. #define DDCCI_FAC_OFFSET_ADDR_LSB 9
  69. #define DDCCI_FAC_OFFSET_W_LONG_DATA 6
  70. #define DDCCI_FAC_OFFSET_W_DDR_DATA_START 10
  71. #define DDCCI_FAC_OFFSET_READ_DDR_LEN_HIGH 10
  72. #define DDCCI_FAC_OFFSET_READ_DDR_LEN_LOW 11
  73. #define DDCCI_FAC_OFFSET_R_DDR_RSP_DATA_START 12
  74. #define DDCCI_FAC_OFFSET_REG_START_BIT 10
  75. #define DDCCI_FAC_OFFSET_REG_STOP_BIT 11
  76. #define DDCCI_FAC_OFFSET_REG_VALUE_MSB 12
  77. #define DDCCI_FAC_OFFSET_REG_VALUE_2ND 13
  78. #define DDCCI_FAC_OFFSET_REG_VALUE_3RD 14
  79. #define DDCCI_FAC_OFFSET_REG_VALUE_LSB 15
  80. #define DDCCI_FAC_OFFSET_PQ_CMD_VALUE_MSB 6
  81. #define DDCCI_FAC_OFFSET_PQ_CMD_VALUE_2ND 7
  82. #define DDCCI_FAC_OFFSET_PQ_CMD_VALUE_3RD 8
  83. #define DDCCI_FAC_OFFSET_PQ_CMD_VALUE_LSB 9
  84. #define DDCCI_FAC_OFFSET_PQ_CMD_RC 6
  85. //PQ CMD Write: 51 LenH LenL CmdType CmdH CmdL Val Crc
  86. //response: 6E LenH LenL CmdType CmdH CmdL RC Crc (LenH LenL: 00 04)
  87. #define DDCCI_FAC_CMD_PQ_PREPARE 1
  88. #define DDCCI_FAC_CMD_PQ_FINISH 0
  89. typedef enum
  90. {
  91. DDCCI_FAC_CMD_GAMMAT = 0x00,
  92. DDCCI_FAC_CMD_HDCP = 0x01,
  93. DDCCI_FAC_CMD_SN = 0x02,
  94. DDCCI_FAC_CMD_FACWEEK = 0x03,
  95. DDCCI_FAC_CMD_FACYEAR = 0x04,
  96. DDCCI_FAC_CMD_HDMIEDID = 0x05,
  97. DDCCI_FAC_CMD_HDMI1EDID = 0x06,
  98. DDCCI_FAC_CMD_DPEDID = 0x07,
  99. DDCCI_FAC_CMD_DP1EDID = 0x08,
  100. DDCCI_FAC_CMD_COLORTEMP_COOL = 0x09,
  101. DDCCI_FAC_CMD_COLORTEMP_WARM = 0x0A,
  102. DDCCI_FAC_CMD_COLORTEMP_STANDARD = 0x0B,
  103. DDCCI_FAC_CMD_COLORTEMP_P3 = 0x0C,
  104. DDCCI_FAC_CMD_COLORTEMP_SRGB = 0x0D,
  105. DDCCI_FAC_CMD_COLORTEMP_EYECARE = 0x0E,
  106. DDCCI_FAC_CMD_GAMUT_NATIVE = 0x0F,
  107. DDCCI_FAC_CMD_GAMUT_SRGB = 0x10,
  108. DDCCI_FAC_CMD_GAMUT_709 = 0x11,
  109. DDCCI_FAC_CMD_GAMUT_P3 = 0x12,
  110. DDCCI_FAC_CMD_GAMUT_HDR = 0x13,
  111. DDCCI_FAC_CMD_GAMUT_ADOBE = 0x14,
  112. DDCCI_FAC_CMD_FACBRIGHTNESS = 0x15,
  113. DDCCI_FAC_CMD_FACCONTRAST = 0x16,
  114. DDCCI_FAC_CMD_ENERGY = 0x17,
  115. DDCCI_FAC_CMD_DEFAULT_LANG = 0x18,
  116. DDCCI_FAC_CMD_SHARPNESS = 0x19,
  117. DDCCI_FAC_CMD_DATABASE_SYNC = 0x1A,
  118. DDCCI_FAC_CMD_CM64 = 0x1B,
  119. DDCCI_FAC_CMD_GMACOMPRESS = 0x1C,
  120. DDCCI_FAC_CMD_HDCP_ALL = 0x1D,
  121. DDCCI_FAC_CMD_GAMUT_DISPLAY_P3 = 0x1E,
  122. DDCCI_FAC_CMD_GAMUT_USER0 = 0x1F,
  123. DDCCI_FAC_CMD_GAMUT_USER1 = 0x20,
  124. DDCCI_FAC_CMD_GAMUT_USER2 = 0x21,
  125. DDCCI_FAC_CMD_HUE = 0x200,
  126. DDCCI_FAC_CMD_SATURATION = 0x201,
  127. DDCCI_FAC_CMD_CONTRAST = 0x202,
  128. DDCCI_FAC_CMD_DLC = 0x203,
  129. DDCCI_FAC_CMD_DCR = 0x204,
  130. DDCCI_FAC_CMD_COLORSPACE = 0x205,
  131. DDCCI_FAC_CMD_RGAIN = 0x206,
  132. DDCCI_FAC_CMD_GGAIN = 0x207,
  133. DDCCI_FAC_CMD_BGAIN = 0x208,
  134. DDCCI_FAC_CMD_ROFFSET = 0x209,
  135. DDCCI_FAC_CMD_GOFFSET = 0x20A,
  136. DDCCI_FAC_CMD_BOFFSET = 0x20B,
  137. DDCCI_FAC_CMD_RED_HUE = 0x20C,
  138. DDCCI_FAC_CMD_RED_SAT = 0x20D,
  139. DDCCI_FAC_CMD_RED_LUM = 0x20E,
  140. DDCCI_FAC_CMD_GREEN_HUE = 0x20F,
  141. DDCCI_FAC_CMD_GREEN_SAT = 0x210,
  142. DDCCI_FAC_CMD_GREEN_LUM = 0x211,
  143. DDCCI_FAC_CMD_BLUE_HUE = 0x212,
  144. DDCCI_FAC_CMD_BLUE_SAT = 0x213,
  145. DDCCI_FAC_CMD_BLUE_LUM = 0x214,
  146. DDCCI_FAC_CMD_CYAN_HUE = 0x215,
  147. DDCCI_FAC_CMD_CYAN_SAT = 0x216,
  148. DDCCI_FAC_CMD_CYAN_LUM = 0x217,
  149. DDCCI_FAC_CMD_YELLOW_HUE = 0x218,
  150. DDCCI_FAC_CMD_YELLOW_SAT = 0x219,
  151. DDCCI_FAC_CMD_YELLOW_LUM = 0x21A,
  152. DDCCI_FAC_CMD_MAGENTA_HUE = 0x21B,
  153. DDCCI_FAC_CMD_MAGENTA_SAT = 0x21C,
  154. DDCCI_FAC_CMD_MAGENTA_LUM = 0x21D,
  155. DDCCI_FAC_CMD_PWM = 0x21E,
  156. DDCCI_FAC_CMD_SET_FR = 0x21F,
  157. DDCCI_FAC_CMD_SIMKEY0 = 0x220,
  158. DDCCI_FAC_CMD_SIMKEY1 = 0x221,
  159. DDCCI_FAC_CMD_SIMKEY2 = 0x222,
  160. DDCCI_FAC_CMD_SIMKEY3 = 0x223,
  161. DDCCI_FAC_CMD_SIMKEY4 = 0x224,
  162. DDCCI_FAC_CMD_GAMMA_MEA = 0x225,
  163. DDCCI_FAC_CMD_DELTAE_MEA = 0x226,
  164. DDCCI_FAC_CMD_DYNAMICPANEL = 0x227,
  165. DDCCI_FAC_CMD_FACTORYMODE = 0x228,
  166. DDCCI_FAC_CMD_LUTINIT = 0x229,
  167. DDCCI_FAC_CMD_BRIGHTNESS = 0x22A,
  168. DDCCI_FAC_CMD_BRIGHTNESS_NIT = 0x22B,
  169. DDCCI_FAC_CMD_WCG_3D_LUT = 0x22C,
  170. DDCCI_FAC_CMD_SETBURNOSD = 0x22D,
  171. DDCCI_FAC_CMD_SETEDIDSN = 0x22E,
  172. DDCCI_FAC_CMD_SWITCH_GAMMA = 0x239,
  173. DDCCI_FAC_CMD_REGISTER = 0x8881,
  174. DDCCI_FAC_CMD_DDR = 0x8883,
  175. DDCCI_FAC_CMD_GAMMA_LUT = 0x8884,
  176. DDCCI_FAC_CMD_GAMMA_UNIT_WRITE = 0x8885,
  177. DDCCI_FAC_CMD_GAMMA_ACTION = 0x8886, //0xEE,0x88,0x86+0x01:Prepare, 0x00:Finish
  178. DDCCI_FAC_CMD_COLORSPACE_ACTION = 0x8887, //0xEE,0x88,0x87+0x01:Prepare, 0x00:Finish
  179. DDCCI_FAC_CMD_WCG_ACTION = 0x8889, //0xEE,0x88,0x89+0x01:On, 0x00:Off
  180. DDCCI_FAC_CMD_COLORTEMP_ACTION = 0x8890, //0xEE,0x88,0x90+0x01:Prepare, 0x00:Finish
  181. DDCCI_FAC_CMD_PATTERN_ACTION = 0x8891, //0xEE,0x88,0x91+0x01:Prepare, 0x00:Finish
  182. DDCCI_FAC_CMD_COLORSPACE_DATA1 = 0x8892, //0xEE,0x88,0x92+18个16bit数值,高位在前
  183. DDCCI_FAC_CMD_COLORSPACE_DATA2 = 0x8893, //0xEE,0x88,0x93+18个16bit数值,高位在前
  184. DDCCI_FAC_CMD_COLORSPACE_DATA3 = 0x8894, //0xEE,0x88,0x94+18个16bit数值,高位在前
  185. DDCCI_FAC_CMD_COLORSPACE_DATA4 = 0x8895, //0xEE,0x88,0x95+18个16bit数值,高位在前
  186. DDCCI_FAC_CMD_COLORSPACE_DATA5 = 0x8896, //0xEE,0x88,0x96+18个16bit数值,高位在前
  187. DDCCI_FAC_CMD_PQ_TRAINING_START = 0x88A0, //0xEE,0x88,0xA0+0x01, training start; 0x00-training stop
  188. DDCCI_FAC_CMD_PQ_RGB_COEF = 0x88A1, //0xEE,0x88,0xA1+RHigh RLow GHigh GLow BHigh BLow
  189. DDCCI_FAC_CMD_PQ_WEEK_YEAR = 0x88A2, //0xEE,0x88,0xA2+week+year
  190. DDCCI_FAC_CMD_START_OR_END = 0x88F0,
  191. } DdcciFacCmdItem;
  192. VOID Hv_App_Ddcci_ProcFactoryMsg(UCHAR8 ucSource, UCHAR8 *pucData, USHORT16 usLen);
  193. UCHAR8 Hv_App_Ddcci_VerifyFactoryCheckSum(UCHAR8 *pucData);
  194. VOID Hv_App_GmaCompress(UINT32 *puiInput, UCHAR8 *pucOut);
  195. #endif