#define __read_32bit_c0_register(source, sel) \ ({ int __res; \ if (sel == 0) \ __asm__ __volatile__( \ "mfc0\t%0, " #source "\n\t" \ : "=r" (__res)); \ else \ __asm__ __volatile__( \ ".set\tmips32\n\t" \ "mfc0\t%0, " #source ", " #sel "\n\t" \ ".set\tmips0\n\t" \ : "=r" (__res)); \ __res; \ }) #define __write_32bit_c0_register(register, sel, value) \ do { \ if (sel == 0) \ __asm__ __volatile__( \ "mtc0\t%z0, " #register "\n\t" \ : : "Jr" ((unsigned int)(value))); \ else \ __asm__ __volatile__( \ ".set\tmips32\n\t" \ "mtc0\t%z0, " #register ", " #sel "\n\t" \ ".set\tmips0" \ : : "Jr" ((unsigned int)(value))); \ } while (0) #define read_c0_index() __read_32bit_c0_register($0, 0) #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) #define read_c0_random() __read_32bit_c0_register($1, 0) #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) #define read_c0_conf() __read_32bit_c0_register($3, 0) #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) #define read_c0_context() __read_ulong_c0_register($4, 0) #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) #define read_c0_contextconfig() __read_ulong_c0_register($4, 1) #define write_c0_contextconfig(val) __write_ulong_c0_register($4, 1, val) #define read_c0_userlocal() __read_ulong_c0_register($4, 2) #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) #define read_c0_wired() __read_32bit_c0_register($6, 0) #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) #define read_c0_info() __read_32bit_c0_register($7, 0) #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) #define read_c0_count() __read_32bit_c0_register($9, 0) #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) #define read_c0_entryhi() __read_ulong_c0_register($10, 0) #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) #define read_c0_compare() __read_32bit_c0_register($11, 0) #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) #define read_c0_status() __read_32bit_c0_register($12, 0) #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) #define read_c0_cause() __read_32bit_c0_register($13, 0) #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) #define read_c0_epc() __read_ulong_c0_register($14, 0) #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) #define read_c0_prid() __read_32bit_c0_register($15, 0) #define read_c0_config() __read_32bit_c0_register($16, 0) #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) #define read_c0_config3() __read_32bit_c0_register($16, 3) #define read_c0_config4() __read_32bit_c0_register($16, 4) #define read_c0_config5() __read_32bit_c0_register($16, 5) #define read_c0_config6() __read_32bit_c0_register($16, 6) #define read_c0_config7() __read_32bit_c0_register($16, 7) #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) /* * The WatchLo register. There may be upto 8 of them. */ #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* * The WatchHi register. There may be upto 8 of them. */ #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) #define read_c0_xcontext() __read_ulong_c0_register($20, 0) #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) #define read_c0_framemask() __read_32bit_c0_register($21, 0) #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) /* RM9000 PerfControl performance counter control register */ #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) #define read_c0_diag() __read_32bit_c0_register($22, 0) #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) #define read_c0_diag1() __read_32bit_c0_register($22, 1) #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) #define read_c0_diag2() __read_32bit_c0_register($22, 2) #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) #define read_c0_diag3() __read_32bit_c0_register($22, 3) #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) #define read_c0_diag4() __read_32bit_c0_register($22, 4) #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) #define read_c0_diag5() __read_32bit_c0_register($22, 5) #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) #define read_c0_debug() __read_32bit_c0_register($23, 0) #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) #define read_c0_depc() __read_ulong_c0_register($24, 0) #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) /* * MIPS32 / MIPS64 performance counters */ #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) /* RM9000 PerfCount performance counter register */ #define read_c0_perfcount() __read_64bit_c0_register($25, 0) #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) #define read_c0_ecc() __read_32bit_c0_register($26, 0) #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) #define read_c0_taglo() __read_32bit_c0_register($28, 0) #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) #define read_c0_taghi() __read_32bit_c0_register($29, 0) #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) #define read_c0_errorepc() __read_ulong_c0_register($30, 0) #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) /* MIPSR2 */ #define read_c0_hwrena() __read_32bit_c0_register($7, 0) #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) #define read_c0_intctl() __read_32bit_c0_register($12, 1) #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) #define read_c0_srsctl() __read_32bit_c0_register($12, 2) #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) #define read_c0_srsmap() __read_32bit_c0_register($12, 3) #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) #define read_c0_srsmap2() __read_32bit_c0_register($12, 5) #define write_c0_srsmap2(val) __write_32bit_c0_register($12, 5, val) #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) #define VS_0x20_intctl (1<<5) #define VS_0x20 (0x20)