#ifndef _ADC_INITTBL_H_
#define _ADC_INITTBL_H_	

UINT32 ADCModeTable[][2]=
{
	{PLF_VIDEO_TIMING_ID_DTV_480I60, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xe0},
		{ADC_REG_r_clamppdn_end, 0xc0},
		{ADC_REG_g_clamppdn_st, 0xe0},
		{ADC_REG_g_clamppdn_end, 0xc0},
		{ADC_REG_b_clamppdn_st, 0xe0},
		{ADC_REG_b_clamppdn_end, 0xc0},
		{ADC_REG_iir_fbpn1_i_7to0, 0x81},
		{ADC_REG_iir_fbpn1_i_8, 0},
		{ADC_REG_iir_fbppn1_i_7to0, 0xe0},
		{ADC_REG_iir_fbppn1_i_8, 0},
		{ADC_REG_coast200_start, 0x58},
	{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_480P60, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xb0},
		{ADC_REG_r_clamppdn_end, 0x80},
		{ADC_REG_g_clamppdn_st, 0xb0},
		{ADC_REG_g_clamppdn_end, 0x80},
		{ADC_REG_b_clamppdn_st, 0xb0},
		{ADC_REG_b_clamppdn_end, 0x80},
		{ADC_REG_coast200_start, 0x58},
	{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_576I50, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xe0},
		{ADC_REG_r_clamppdn_end, 0xc0},
		{ADC_REG_g_clamppdn_st, 0xe0},
		{ADC_REG_g_clamppdn_end, 0xc0},
		{ADC_REG_b_clamppdn_st, 0xe0},
		{ADC_REG_b_clamppdn_end, 0xc0},
		{ADC_REG_iir_fbpn1_i_7to0, 0x81},
		{ADC_REG_iir_fbpn1_i_8, 0},
		{ADC_REG_iir_fbppn1_i_7to0, 0xe0},
		{ADC_REG_iir_fbppn1_i_8, 0},
		{ADC_REG_coast200_start, 0x58},
	{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_576P50, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xb0},
		{ADC_REG_r_clamppdn_end, 0x80},
		{ADC_REG_g_clamppdn_st, 0xb0},
		{ADC_REG_g_clamppdn_end, 0x80},
		{ADC_REG_b_clamppdn_st, 0xb0},
		{ADC_REG_b_clamppdn_end, 0x80},
        {ADC_REG_coast200_start, 0x58},
		{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_720P50, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xa0},
		{ADC_REG_r_clamppdn_end, 0x50},
		{ADC_REG_g_clamppdn_st, 0xa0},
		{ADC_REG_g_clamppdn_end, 0x50},
		{ADC_REG_b_clamppdn_st, 0xa0},
		{ADC_REG_b_clamppdn_end, 0x50},
		{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_720P60, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xa0},
		{ADC_REG_r_clamppdn_end, 0x50},
		{ADC_REG_g_clamppdn_st, 0xa0},
		{ADC_REG_g_clamppdn_end, 0x50},
		{ADC_REG_b_clamppdn_st, 0xa0},
		{ADC_REG_b_clamppdn_end, 0x50},
		{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_1080I50, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xa0},
		{ADC_REG_r_clamppdn_end, 0x50},
		{ADC_REG_g_clamppdn_st, 0xa0},
		{ADC_REG_g_clamppdn_end, 0x50},
		{ADC_REG_b_clamppdn_st, 0xa0},
		{ADC_REG_b_clamppdn_end, 0x50},
	{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_1080I60, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xa0},
		{ADC_REG_r_clamppdn_end, 0x50},
		{ADC_REG_g_clamppdn_st, 0xa0},
		{ADC_REG_g_clamppdn_end, 0x50},
		{ADC_REG_b_clamppdn_st, 0xa0},
		{ADC_REG_b_clamppdn_end, 0x50},
	{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_1080P23, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xa0},
		{ADC_REG_r_clamppdn_end, 0x50},
		{ADC_REG_g_clamppdn_st, 0xa0},
		{ADC_REG_g_clamppdn_end, 0x50},
		{ADC_REG_b_clamppdn_st, 0xa0},
		{ADC_REG_b_clamppdn_end, 0x50},
	{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_1080P25, 0xff00},
		{ADC_REG_r_clamppdn_st, 0xa0},
		{ADC_REG_r_clamppdn_end, 0x50},
		{ADC_REG_g_clamppdn_st, 0xa0},
		{ADC_REG_g_clamppdn_end, 0x50},
		{ADC_REG_b_clamppdn_st, 0xa0},
		{ADC_REG_b_clamppdn_end, 0x50},
		{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_1080P30, 0xff00},
		{ADC_REG_r_clamppdn_st, 0x90},
		{ADC_REG_r_clamppdn_end, 0x40},
		{ADC_REG_g_clamppdn_st, 0x90},
		{ADC_REG_g_clamppdn_end, 0x40},
		{ADC_REG_b_clamppdn_st, 0x90},
		{ADC_REG_b_clamppdn_end, 0x40},
		{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_1080P50, 0xff00},
		{ADC_REG_r_clamppdn_st, 0x80},
		{ADC_REG_r_clamppdn_end, 0x30},
		{ADC_REG_g_clamppdn_st, 0x80},
		{ADC_REG_g_clamppdn_end, 0x30},
		{ADC_REG_b_clamppdn_st, 0x80},
		{ADC_REG_b_clamppdn_end, 0x30},
		{0xffff,0xffff},

	{PLF_VIDEO_TIMING_ID_DTV_1080P60, 0xff00},
		{ADC_REG_r_clamppdn_st, 0x80},
		{ADC_REG_r_clamppdn_end, 0x30},
		{ADC_REG_g_clamppdn_st, 0x80},
		{ADC_REG_g_clamppdn_end, 0x30},
		{ADC_REG_b_clamppdn_st, 0x80},
		{ADC_REG_b_clamppdn_end, 0x30},
		{ADC_REG_st_srch_filt_opt, 0x1},
		{ADC_REG_cpt_loss_range, 0x7},
		{0xffff,0xffff},

};


UINT32 ADCSouceInitBaseTable[][2]=
{
	{Adc_kSourceCOMP1, 0xff00},
		{ADC_REG_lcg_clamp_mode_rb, 1},
		{ADC_REG_cvbs_clamp_mode_rb, 1},
		{ADC_REG_cs_coast_pend, 0x58},
		{ADC_REG_loss_sync_opt, 3},

		//power down Y channel
		{ADC_REG_CVBSO_PWD12, 1},
		{ADC_REG_pwdny, 1},

		//YPP and CVBS share pin issue
		{ADC_REG_y_chsel, 0},

		//Differential mode setting
		{ADC_REG_y_pden12v, 0},
        
        {ADC_REG_pll_ref_sel, 0},
		{ADC_REG_o_pclk_sel, 0},
		{ADC_REG_csync_tcg_sel, 0},
		{ADC_REG_o_hsync_sel, 0x3},
		{ADC_REG_o_vsync_sel, 0},
		{ADC_REG_cs2_sog_sw_rst_sel, 0x1},
		{ADC_REG_vbg_i_ctrl, 0x9},
		{ADC_REG_sch_pbw_ctrl, 9},
		{ADC_REG_sch_ref_pbw_ctrl, 9},

		{ADC_REG_lcg_r33vcm_sel, 0x4},
		{ADC_REG_lcg_g33vcm_sel, 0x4},
		{ADC_REG_lcg_b33vcm_sel, 0x4},
		
		//ADC power 1.1v to 0.95v, adjust vcm range 0.55v to 0.5v
		{ADC_REG_r_12vcm_sel, 0x7},
		{ADC_REG_g_12vcm_sel, 0x7},
		{ADC_REG_b_12vcm_sel, 0x7},
		{ADC_REG_12vcm_sel_msb, 0},
		{ADC_REG_b_pg12v1, 2},
		{ADC_REG_dgain_r, 0x80},
		{ADC_REG_dgain_g, 0x80},
		{ADC_REG_dgain_b, 0x80},
		//ff chip and high temperature will let pll unstable, set 5(1.15v) to 3(1.05v)
		{ADC_REG_vbg_sel, 0x3},

		{ADC_REG_adjsifclr12v2, 0},
		{ADC_REG_cvbs_clamp_mode_g, 0},
		
		{ADC_REG_b_sypp12, 1},
		
		{ADC_REG_cs_rthd, 0xf},

		{ADC_REG_rwclampeco, 0},

		{ADC_REG_clamppdn_en, 1},

		{ADC_REG_dco_en_fdiv, 0x1},

		{ADC_REG_datain_ini_7to0, 0x01},
		{ADC_REG_datain_ini_15to8, 0},
		{ADC_REG_datain_ini_16, 0},
		{ADC_REG_dco_bx2, 0},
		{ADC_REG_dbgsela, 0},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_iir_fbpn1_f, 0xf6},
		{ADC_REG_iir_fbpn1_i_7to0, 0x81},
		{ADC_REG_iir_fbpn1_i_8, 0},
		{ADC_REG_iir_fbppn1_f, 0xf6},
		{ADC_REG_iir_fbppn1_i_7to0, 0x60},
		{ADC_REG_iir_fbppn1_i_8, 0x1},
		{ADC_REG_iir_fwn1_f, 0x4a},
		{ADC_REG_iir_fwn1_i_7to0, 0x18},
		{ADC_REG_iir_fwn1_i_8, 0},
		{ADC_REG_iir_fwpn1_f, 0x14},
		{ADC_REG_iir_fwpn1_i_7to0, 0},
		{ADC_REG_iir_fwpn1_i_8, 0},
		{ADC_REG_iir_fwppn1_f, 0x36},
		{ADC_REG_iir_fwppn1_i_7to0, 0x18},
		{ADC_REG_iir_fwppn1_i_8, 0},
		{ADC_REG_iirclk_div_sel, 0x3},

		{ADC_REG_sdmresetj, 0x1},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_dco_refdiv, 0},
		{ADC_REG_dlpll_pdiv_rstj, 0x0},
		{ADC_REG_dlpll_pdiv_rstj, 0x1},

		//digital gain & offset enable
		{ADC_REG_beofst_en0, 0x1},
		{ADC_REG_begain_en0, 0x1},
		{ADC_REG_dgain_op0, 0x1},

		//filter differential board noise
		{ADC_REG_refinsel12v, 1},
		

		//Hsync miss threshold
		{ADC_REG_cs2_rst_sog_maxhp_en_14to8, 0x7f},
		{ADC_REG_cs2_rst_sog_maxhp_en, 1},

		//k8880 hsync miss issue, modified filter 200ns to 80ns
		{ADC_REG_db_sel_ext, 0x1},

		{ADC_REG_r_clamppdn_mod, 2},
		{ADC_REG_g_clamppdn_mod, 3},
		{ADC_REG_b_clamppdn_mod, 2},

		{ADC_REG_r_sb1, 0x13},
		{ADC_REG_g_sb1, 0x19},
		{ADC_REG_b_sb1, 0x13},
		{ADC_REG_cs2_r_clamp_start, 1},
		{ADC_REG_cs2_r_clamp_width, 0},
		{ADC_REG_cs2_g_clamp_start, 1},
		{ADC_REG_cs2_g_clamp_width, 0},
		{ADC_REG_cs2_b_clamp_start, 1},
		{ADC_REG_cs2_b_clamp_width, 0},

		//pll hardware reset disable
		{ADC_REG_cs2_pll_rst_sel, 1},
        {ADC_REG_cs_coast_pend, 0x58},
		{ADC_REG_loss_sync_opt, 3},

		{ADC_REG_dofst_g_5to0, 0x3f},
		{ADC_REG_dofst_g_7to6, 3},
		{ADC_REG_dofst_g, 0},
		{ADC_REG_ini_sc_wdth, 0x4},
		{ADC_REG_cpt_range, 7},

		{ADC_REG_min_line_wdth_opt, 0x4},
		{ADC_REG_max_line_wdth_opt, 0xf},

		{ADC_REG_vblank_stb_length, 4},

		{ADC_REG_sc1_sc2_sel, 0},
		{ADC_reg_prev_mask_th, 0x6},
		{ADC_reg_prev_mask1_en, 0x1},
		{ADC_reg_vsync_mask_stb_cnt, 0x1},

		{ADC_REG_ini_sc_start, 0x0},
		{ADC_REG_ini_sc_wdth, 0xf},
		{ADC_REG_vblank_ini_length, 0x6},

		{ADC_REG_vsync_mask_start, 0x8},
		{ADC_REG_vsync_mask_end, 0x8},

		{ADC_REG_line, 0x4e},
		{ADC_REG_ini_sc_rlimit, 0},
		{ADC_REG_cpt_vol, 0x38},

		{ADC_REG_cpt_loss_range, 0x7},

		{ADC_REG_sog_cmp, 0x2},
		{ADC_REG_sogcomp_pwdn12v_0to7, 0xff},
		{ADC_REG_sogcomp_pwdn12v_8to15, 0xff},

		//coast 200
		{ADC_REG_hs_vld_f_wdth, 0x58},
		{ADC_REG_coast200_start, 0x28},
		{ADC_REG_coast200_line_update, 0x3},
		{ADC_REG_coast_out_sel, 0x1},
		{ADC_REG_coast200_start_opt, 0x1},
		{ADC_REG_coast200_end_opt, 0x1},
		{ADC_REG_refclk_db_sel, 0x0},
		{ADC_REG_refclk_cs_sel, 0x1},
		{ADC_REG_lwdth_skip_l2cnt, 0},
		{ADC_REG_hs_valid_fall, 0},
		{ADC_REG_sc_vblankt1, 3},
		{ADC_REG_sc_vblankt2, 3},
		//1080i@60 1080i@50 Flashing white line by Astro
		{ADC_REG_vs_sc_start, 0x2},
		{ADC_REG_vs_sc_wdth, 0xf},
		//Qisheng DVD 1080I Change mode to 1080P fail
		{ADC_REG_i2p_rise_lth, 0xf},
		{ADC_REG_i2p_rise_hth, 0xf},
		{ADC_REG_i2p_wdth_lth, 0xf},
		{ADC_REG_i2p_wdth_hth, 0xf},
		//CASA 480i 576i H-clamp disable at Vsync
		{ADC_REG_sc_vsync_skip, 1},

		{ADC_REG_st_fir1_strong, 0},
		{ADC_REG_st_top_exit_th, 0x5},
		{ADC_REG_cs_xor_opt, 0},
		{ADC_REG_sc_stb_vs_sth, 7},
		{ADC_REG_sog_smthr12v, 0x56},
		{ADC_REG_stb1_sc_wdth_opt, 1},
		
		// Setup SoG clamp charge duration
		{ADC_REG_sc1_start, 0xf},
		{ADC_REG_sc1_wdth, 0xf},
		{ADC_REG_sc2_start, 1},
		{ADC_REG_sc2_wdth, 1},
		
		{ADC_REG_sc_highbound, 0xb},
		{ADC_REG_cpt_loss_en, 1},
		//DVD player 1080i@50 can't distinguish "i mode"
		{ADC_REG_cs_vslp, 1},

		{ADC_REG_cs_coast_pstart, 0x50},

		{ADC_REG_cs_httl_sch_range, 0x8},
		// K-8257R 480i HSout & [Formal] CASA DVD player
		{ADC_REG_ushsp_pls_thold, 0x6},

		{ADC_REG_shsp_thold, 0x1f},
		{ADC_REG_dg_l2h_thold, 0xa},
		{ADC_REG_dg_h2l_thold, 0xa},
		
		{ADC_REG_hs_atout_ctrl, 0x2},


		{ADC_REG_smt_fir_th, 0x5},
		{ADC_REG_smt_fir_strong, 1},	
		{ADC_REG_source_sel, 0x2},	
		{ADC_REG_st_iir1_strength, 0},
		{ADC_REG_st_fir1_strong, 0},
		{ADC_REG_sog_clamp, 0x8},

		{ADC_REG_smt_auto_opt, 3},

		{ADC_REG_i2p_wdth_det_th, 0x0},
		{ADC_REG_i2p_opt, 0},
		{ADC_REG_ini_sc_extend, 0},
		{ADC_REG_csgen_vw_opt, 0},		

		//Input pattern presents three h-sync difference from Vsync to Vsync
		{ADC_REG_cs_vstable_thd, 7},

		{ADC_REG_synct_smt_sth, 0x3},
		{ADC_REG_synct_iir2_smt_mask, 1},
		{ADC_REG_synct_smt_opt, 0},
		
		{ADC_REG_hs_vld_r_maskb, 0xc},
		{ADC_REG_sc_stb_sth, 0},


		{ADC_REG_loss_sync_update, 0},
		{ADC_REG_wclamp_lcnt, 2},

		//csgen start sync real hsync
		{ADC_REG_csgen_start, 0x49},
		{ADC_REG_cs2_r_clamp_ref_edge, 1},
		{ADC_REG_cs2_g_clamp_ref_edge, 1},
		{ADC_REG_cs2_b_clamp_ref_edge, 1},

	{0xffff,0xffff},

	{Adc_kSourceCOMP2, 0xff00},
		{ADC_REG_lcg_clamp_mode_rb, 1},
		{ADC_REG_cvbs_clamp_mode_rb, 1},
		{ADC_REG_cs_coast_pend, 0x58},
		{ADC_REG_loss_sync_opt, 3},

		//power down Y channel
		{ADC_REG_CVBSO_PWD12, 1},
		{ADC_REG_pwdny, 1},

		//YPP and CVBS share pin issue
		{ADC_REG_y_chsel, 0},

		//Differential mode setting
		{ADC_REG_y_pden12v, 0},
        
        {ADC_REG_pll_ref_sel, 0},
		{ADC_REG_o_pclk_sel, 0},
		{ADC_REG_csync_tcg_sel, 0},
		{ADC_REG_o_hsync_sel, 0x3},
		{ADC_REG_o_vsync_sel, 0},
		{ADC_REG_cs2_sog_sw_rst_sel, 0x1},
		{ADC_REG_vbg_i_ctrl, 0x9},
		{ADC_REG_sch_pbw_ctrl, 9},
		{ADC_REG_sch_ref_pbw_ctrl, 9},

		{ADC_REG_lcg_r33vcm_sel, 0x4},
		{ADC_REG_lcg_g33vcm_sel, 0x4},
		{ADC_REG_lcg_b33vcm_sel, 0x4},
		
		//ADC power 1.1v to 0.95v, adjust vcm range 0.55v to 0.5v
		{ADC_REG_r_12vcm_sel, 0x7},
		{ADC_REG_g_12vcm_sel, 0x7},
		{ADC_REG_b_12vcm_sel, 0x7},
		{ADC_REG_12vcm_sel_msb, 0},
		{ADC_REG_b_pg12v1, 2},
		{ADC_REG_dgain_r, 0x80},
		{ADC_REG_dgain_g, 0x80},
		{ADC_REG_dgain_b, 0x80},
		//ff chip and high temperature will let pll unstable, set 5(1.15v) to 3(1.05v)
		{ADC_REG_vbg_sel, 0x3},


		{ADC_REG_adjsifclr12v2, 0},
		{ADC_REG_cvbs_clamp_mode_g, 0},
		
		{ADC_REG_b_sypp12, 1},
		
		{ADC_REG_cs_rthd, 0xf},

		{ADC_REG_rwclampeco, 0},

		{ADC_REG_clamppdn_en, 1},

		{ADC_REG_dco_en_fdiv, 0x1},

		{ADC_REG_datain_ini_7to0, 0x01},
		{ADC_REG_datain_ini_15to8, 0},
		{ADC_REG_datain_ini_16, 0},
		{ADC_REG_dco_bx2, 0},
		{ADC_REG_dbgsela, 0},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_iir_fbpn1_f, 0xf6},
		{ADC_REG_iir_fbpn1_i_7to0, 0x81},
		{ADC_REG_iir_fbpn1_i_8, 0},
		{ADC_REG_iir_fbppn1_f, 0xf6},
		{ADC_REG_iir_fbppn1_i_7to0, 0x60},
		{ADC_REG_iir_fbppn1_i_8, 0x1},
		{ADC_REG_iir_fwn1_f, 0x4a},
		{ADC_REG_iir_fwn1_i_7to0, 0x18},
		{ADC_REG_iir_fwn1_i_8, 0},
		{ADC_REG_iir_fwpn1_f, 0x14},
		{ADC_REG_iir_fwpn1_i_7to0, 0},
		{ADC_REG_iir_fwpn1_i_8, 0},
		{ADC_REG_iir_fwppn1_f, 0x36},
		{ADC_REG_iir_fwppn1_i_7to0, 0x18},
		{ADC_REG_iir_fwppn1_i_8, 0},
		{ADC_REG_iirclk_div_sel, 0x3},

		{ADC_REG_sdmresetj, 0x1},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_dco_refdiv, 0},
		{ADC_REG_dlpll_pdiv_rstj, 0x0},
		{ADC_REG_dlpll_pdiv_rstj, 0x1},

		//digital gain & offset enable
		{ADC_REG_beofst_en0, 0x1},
		{ADC_REG_begain_en0, 0x1},
		{ADC_REG_dgain_op0, 0x1},

		//filter differential board noise
		{ADC_REG_refinsel12v, 1},
		

		//Hsync miss threshold
		{ADC_REG_cs2_rst_sog_maxhp_en_14to8, 0x7f},
		{ADC_REG_cs2_rst_sog_maxhp_en, 1},

		//k8880 hsync miss issue, modified filter 200ns to 80ns
		{ADC_REG_db_sel_ext, 0x1},

		{ADC_REG_r_clamppdn_mod, 2},
		{ADC_REG_g_clamppdn_mod, 3},
		{ADC_REG_b_clamppdn_mod, 2},

		{ADC_REG_r_sb1, 0x13},
		{ADC_REG_g_sb1, 0x19},
		{ADC_REG_b_sb1, 0x13},
		{ADC_REG_cs2_r_clamp_start, 1},
		{ADC_REG_cs2_r_clamp_width, 0},
		{ADC_REG_cs2_g_clamp_start, 1},
		{ADC_REG_cs2_g_clamp_width, 0},
		{ADC_REG_cs2_b_clamp_start, 1},
		{ADC_REG_cs2_b_clamp_width, 0},

		//pll hardware reset disable
		{ADC_REG_cs2_pll_rst_sel, 1},
        {ADC_REG_cs_coast_pend, 0x58},
		{ADC_REG_loss_sync_opt, 3},

		{ADC_REG_dofst_g_5to0, 0x3f},
		{ADC_REG_dofst_g_7to6, 3},
		{ADC_REG_dofst_g, 0},
		{ADC_REG_ini_sc_wdth, 0x4},
		{ADC_REG_cpt_range, 7},

		{ADC_REG_min_line_wdth_opt, 0x4},
		{ADC_REG_max_line_wdth_opt, 0xf},

		{ADC_REG_vblank_stb_length, 4},

		{ADC_REG_sc1_sc2_sel, 0},
		{ADC_reg_prev_mask_th, 0x6},
		{ADC_reg_prev_mask1_en, 0x1},
		{ADC_reg_vsync_mask_stb_cnt, 0x1},

		{ADC_REG_ini_sc_start, 0x0},
		{ADC_REG_ini_sc_wdth, 0xf},
		{ADC_REG_vblank_ini_length, 0x6},

		{ADC_REG_vsync_mask_start, 0x8},
		{ADC_REG_vsync_mask_end, 0x8},

		{ADC_REG_line, 0x4e},
		{ADC_REG_ini_sc_rlimit, 0},
		{ADC_REG_cpt_vol, 0x38},

		{ADC_REG_cpt_loss_range, 0x7},

		{ADC_REG_sog_cmp, 0x2},
		{ADC_REG_sogcomp_pwdn12v_0to7, 0xff},
		{ADC_REG_sogcomp_pwdn12v_8to15, 0xff},

		//coast 200
		{ADC_REG_hs_vld_f_wdth, 0x58},
		{ADC_REG_coast200_start, 0x28},
		{ADC_REG_coast200_line_update, 0x3},
		{ADC_REG_coast_out_sel, 0x1},
		{ADC_REG_coast200_start_opt, 0x1},
		{ADC_REG_coast200_end_opt, 0x1},
		{ADC_REG_refclk_db_sel, 0x0},
		{ADC_REG_refclk_cs_sel, 0x1},
		{ADC_REG_lwdth_skip_l2cnt, 0},
		{ADC_REG_hs_valid_fall, 0},
		{ADC_REG_sc_vblankt1, 3},
		{ADC_REG_sc_vblankt2, 3},
		//1080i@60 1080i@50 Flashing white line by Astro
		{ADC_REG_vs_sc_start, 0x2},
		{ADC_REG_vs_sc_wdth, 0xf},
		//Qisheng DVD 1080I Change mode to 1080P fail
		{ADC_REG_i2p_rise_lth, 0xf},
		{ADC_REG_i2p_rise_hth, 0xf},
		{ADC_REG_i2p_wdth_lth, 0xf},
		{ADC_REG_i2p_wdth_hth, 0xf},
		//CASA 480i 576i H-clamp disable at Vsync
		{ADC_REG_sc_vsync_skip, 1},

		{ADC_REG_st_fir1_strong, 0},
		{ADC_REG_st_top_exit_th, 0x5},
		{ADC_REG_cs_xor_opt, 0},
		{ADC_REG_sc_stb_vs_sth, 7},
		{ADC_REG_sog_smthr12v, 0x56},
		{ADC_REG_stb1_sc_wdth_opt, 1},
		
		// Setup SoG clamp charge duration
		{ADC_REG_sc1_start, 0xf},
		{ADC_REG_sc1_wdth, 0xf},
		{ADC_REG_sc2_start, 1},
		{ADC_REG_sc2_wdth, 1},
		
		{ADC_REG_sc_highbound, 0xb},
		{ADC_REG_cpt_loss_en, 1},
		//DVD player 1080i@50 can't distinguish "i mode"
		{ADC_REG_cs_vslp, 1},

		{ADC_REG_cs_coast_pstart, 0x50},

		{ADC_REG_cs_httl_sch_range, 0x8},
		// K-8257R 480i HSout & [Formal] CASA DVD player
		{ADC_REG_ushsp_pls_thold, 0x6},

		{ADC_REG_shsp_thold, 0x1f},
		{ADC_REG_dg_l2h_thold, 0xa},
		{ADC_REG_dg_h2l_thold, 0xa},
		
		{ADC_REG_hs_atout_ctrl, 0x2},


		{ADC_REG_smt_fir_th, 0x5},
		{ADC_REG_smt_fir_strong, 1},	
		{ADC_REG_source_sel, 0x2},	
		{ADC_REG_st_iir1_strength, 0},
		{ADC_REG_st_fir1_strong, 0},
		{ADC_REG_sog_clamp, 0x8},

		{ADC_REG_smt_auto_opt, 3},

		{ADC_REG_i2p_wdth_det_th, 0x0},
		{ADC_REG_i2p_opt, 0},
		{ADC_REG_ini_sc_extend, 0},
		{ADC_REG_csgen_vw_opt, 0},		

		//Input pattern presents three h-sync difference from Vsync to Vsync
		{ADC_REG_cs_vstable_thd, 7},

		{ADC_REG_synct_smt_sth, 0x3},
		{ADC_REG_synct_iir2_smt_mask, 1},
		{ADC_REG_synct_smt_opt, 0},
		
		{ADC_REG_hs_vld_r_maskb, 0xc},
		{ADC_REG_sc_stb_sth, 0},


		{ADC_REG_loss_sync_update, 0},
		{ADC_REG_wclamp_lcnt, 2},

		//csgen start sync real hsync
		{ADC_REG_csgen_start, 0x49},
		{ADC_REG_cs2_r_clamp_ref_edge, 1},
		{ADC_REG_cs2_g_clamp_ref_edge, 1},
		{ADC_REG_cs2_b_clamp_ref_edge, 1},
	{0xffff,0xffff},

	{Adc_kSourceCOMP3, 0xff00},
		{ADC_REG_lcg_clamp_mode_rb, 1},
		{ADC_REG_cvbs_clamp_mode_rb, 1},
		{ADC_REG_cs_coast_pend, 0x58},
		{ADC_REG_loss_sync_opt, 3},

		//power down Y channel
		{ADC_REG_CVBSO_PWD12, 1},
		{ADC_REG_pwdny, 1},

		//YPP and CVBS share pin issue
		{ADC_REG_y_chsel, 0},

		//Differential mode setting
		{ADC_REG_y_pden12v, 0},
        
        {ADC_REG_pll_ref_sel, 0},
		{ADC_REG_o_pclk_sel, 0},
		{ADC_REG_csync_tcg_sel, 0},
		{ADC_REG_o_hsync_sel, 0x3},
		{ADC_REG_o_vsync_sel, 0},
		{ADC_REG_cs2_sog_sw_rst_sel, 0x1},
		{ADC_REG_vbg_i_ctrl, 0x9},
		{ADC_REG_sch_pbw_ctrl, 9},
		{ADC_REG_sch_ref_pbw_ctrl, 9},

		{ADC_REG_lcg_r33vcm_sel, 0x4},
		{ADC_REG_lcg_g33vcm_sel, 0x4},
		{ADC_REG_lcg_b33vcm_sel, 0x4},
		
		//ADC power 1.1v to 0.95v, adjust vcm range 0.55v to 0.5v
		{ADC_REG_r_12vcm_sel, 0x7},
		{ADC_REG_g_12vcm_sel, 0x7},
		{ADC_REG_b_12vcm_sel, 0x7},
		{ADC_REG_12vcm_sel_msb, 0},
		{ADC_REG_b_pg12v1, 2},
		{ADC_REG_dgain_r, 0x80},
		{ADC_REG_dgain_g, 0x80},
		{ADC_REG_dgain_b, 0x80},
		//ff chip and high temperature will let pll unstable, set 5(1.15v) to 3(1.05v)
		{ADC_REG_vbg_sel, 0x3},

		{ADC_REG_adjsifclr12v2, 0},
		{ADC_REG_cvbs_clamp_mode_g, 0},
		
		{ADC_REG_b_sypp12, 1},
		
		{ADC_REG_cs_rthd, 0xf},

		{ADC_REG_rwclampeco, 0},

		{ADC_REG_clamppdn_en, 1},

		{ADC_REG_dco_en_fdiv, 0x1},

		{ADC_REG_datain_ini_7to0, 0x01},
		{ADC_REG_datain_ini_15to8, 0},
		{ADC_REG_datain_ini_16, 0},
		{ADC_REG_dco_bx2, 0},
		{ADC_REG_dbgsela, 0},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_iir_fbpn1_f, 0xf6},
		{ADC_REG_iir_fbpn1_i_7to0, 0x81},
		{ADC_REG_iir_fbpn1_i_8, 0},
		{ADC_REG_iir_fbppn1_f, 0xf6},
		{ADC_REG_iir_fbppn1_i_7to0, 0x60},
		{ADC_REG_iir_fbppn1_i_8, 0x1},
		{ADC_REG_iir_fwn1_f, 0x4a},
		{ADC_REG_iir_fwn1_i_7to0, 0x18},
		{ADC_REG_iir_fwn1_i_8, 0},
		{ADC_REG_iir_fwpn1_f, 0x14},
		{ADC_REG_iir_fwpn1_i_7to0, 0},
		{ADC_REG_iir_fwpn1_i_8, 0},
		{ADC_REG_iir_fwppn1_f, 0x36},
		{ADC_REG_iir_fwppn1_i_7to0, 0x18},
		{ADC_REG_iir_fwppn1_i_8, 0},
		{ADC_REG_iirclk_div_sel, 0x3},

		{ADC_REG_sdmresetj, 0x1},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_dco_refdiv, 0},
		{ADC_REG_dlpll_pdiv_rstj, 0x0},
		{ADC_REG_dlpll_pdiv_rstj, 0x1},

		//digital gain & offset enable
		{ADC_REG_beofst_en0, 0x1},
		{ADC_REG_begain_en0, 0x1},
		{ADC_REG_dgain_op0, 0x1},

		//filter differential board noise
		{ADC_REG_refinsel12v, 1},
		

		//Hsync miss threshold
		{ADC_REG_cs2_rst_sog_maxhp_en_14to8, 0x7f},
		{ADC_REG_cs2_rst_sog_maxhp_en, 1},

		//k8880 hsync miss issue, modified filter 200ns to 80ns
		{ADC_REG_db_sel_ext, 0x1},

		{ADC_REG_r_clamppdn_mod, 2},
		{ADC_REG_g_clamppdn_mod, 3},
		{ADC_REG_b_clamppdn_mod, 2},

		{ADC_REG_r_sb1, 0x13},
		{ADC_REG_g_sb1, 0x19},
		{ADC_REG_b_sb1, 0x13},
		{ADC_REG_cs2_r_clamp_start, 1},
		{ADC_REG_cs2_r_clamp_width, 0},
		{ADC_REG_cs2_g_clamp_start, 1},
		{ADC_REG_cs2_g_clamp_width, 0},
		{ADC_REG_cs2_b_clamp_start, 1},
		{ADC_REG_cs2_b_clamp_width, 0},

		//pll hardware reset disable
		{ADC_REG_cs2_pll_rst_sel, 1},
        {ADC_REG_cs_coast_pend, 0x58},
		{ADC_REG_loss_sync_opt, 3},

		{ADC_REG_dofst_g_5to0, 0x3f},
		{ADC_REG_dofst_g_7to6, 3},
		{ADC_REG_dofst_g, 0},
		{ADC_REG_ini_sc_wdth, 0x4},
		{ADC_REG_cpt_range, 7},

		{ADC_REG_min_line_wdth_opt, 0x4},
		{ADC_REG_max_line_wdth_opt, 0xf},

		{ADC_REG_vblank_stb_length, 4},

		{ADC_REG_sc1_sc2_sel, 0},
		{ADC_reg_prev_mask_th, 0x6},
		{ADC_reg_prev_mask1_en, 0x1},
		{ADC_reg_vsync_mask_stb_cnt, 0x1},

		{ADC_REG_ini_sc_start, 0x0},
		{ADC_REG_ini_sc_wdth, 0xf},
		{ADC_REG_vblank_ini_length, 0x6},

		{ADC_REG_vsync_mask_start, 0x8},
		{ADC_REG_vsync_mask_end, 0x8},

		{ADC_REG_line, 0x4e},
		{ADC_REG_ini_sc_rlimit, 0},
		{ADC_REG_cpt_vol, 0x38},

		{ADC_REG_cpt_loss_range, 0x7},

		{ADC_REG_sog_cmp, 0x2},
		{ADC_REG_sogcomp_pwdn12v_0to7, 0xff},
		{ADC_REG_sogcomp_pwdn12v_8to15, 0xff},

		//coast 200
		{ADC_REG_hs_vld_f_wdth, 0x58},
		{ADC_REG_coast200_start, 0x28},
		{ADC_REG_coast200_line_update, 0x3},
		{ADC_REG_coast_out_sel, 0x1},
		{ADC_REG_coast200_start_opt, 0x1},
		{ADC_REG_coast200_end_opt, 0x1},
		{ADC_REG_refclk_db_sel, 0x0},
		{ADC_REG_refclk_cs_sel, 0x1},
		{ADC_REG_lwdth_skip_l2cnt, 0},
		{ADC_REG_hs_valid_fall, 0},
		{ADC_REG_sc_vblankt1, 3},
		{ADC_REG_sc_vblankt2, 3},
		//1080i@60 1080i@50 Flashing white line by Astro
		{ADC_REG_vs_sc_start, 0x2},
		{ADC_REG_vs_sc_wdth, 0xf},
		//Qisheng DVD 1080I Change mode to 1080P fail
		{ADC_REG_i2p_rise_lth, 0xf},
		{ADC_REG_i2p_rise_hth, 0xf},
		{ADC_REG_i2p_wdth_lth, 0xf},
		{ADC_REG_i2p_wdth_hth, 0xf},
		//CASA 480i 576i H-clamp disable at Vsync
		{ADC_REG_sc_vsync_skip, 1},

		{ADC_REG_st_fir1_strong, 0},
		{ADC_REG_st_top_exit_th, 0x5},
		{ADC_REG_cs_xor_opt, 0},
		{ADC_REG_sc_stb_vs_sth, 7},
		{ADC_REG_sog_smthr12v, 0x56},
		{ADC_REG_stb1_sc_wdth_opt, 1},
		
		// Setup SoG clamp charge duration
		{ADC_REG_sc1_start, 0xf},
		{ADC_REG_sc1_wdth, 0xf},
		{ADC_REG_sc2_start, 1},
		{ADC_REG_sc2_wdth, 1},
		
		{ADC_REG_sc_highbound, 0xb},
		{ADC_REG_cpt_loss_en, 1},
		//DVD player 1080i@50 can't distinguish "i mode"
		{ADC_REG_cs_vslp, 1},

		{ADC_REG_cs_coast_pstart, 0x50},

		{ADC_REG_cs_httl_sch_range, 0x8},
		// K-8257R 480i HSout & [Formal] CASA DVD player
		{ADC_REG_ushsp_pls_thold, 0x6},

		{ADC_REG_shsp_thold, 0x1f},
		{ADC_REG_dg_l2h_thold, 0xa},
		{ADC_REG_dg_h2l_thold, 0xa},
		
		{ADC_REG_hs_atout_ctrl, 0x2},


		{ADC_REG_smt_fir_th, 0x5},
		{ADC_REG_smt_fir_strong, 1},	
		{ADC_REG_source_sel, 0x2},	
		{ADC_REG_st_iir1_strength, 0},
		{ADC_REG_st_fir1_strong, 0},
		{ADC_REG_sog_clamp, 0x8},

		{ADC_REG_smt_auto_opt, 3},

		{ADC_REG_i2p_wdth_det_th, 0x0},
		{ADC_REG_i2p_opt, 0},
		{ADC_REG_ini_sc_extend, 0},
		{ADC_REG_csgen_vw_opt, 0},		

		//Input pattern presents three h-sync difference from Vsync to Vsync
		{ADC_REG_cs_vstable_thd, 7},

		{ADC_REG_synct_smt_sth, 0x3},
		{ADC_REG_synct_iir2_smt_mask, 1},
		{ADC_REG_synct_smt_opt, 0},
		
		{ADC_REG_hs_vld_r_maskb, 0xc},
		{ADC_REG_sc_stb_sth, 0},


		{ADC_REG_loss_sync_update, 0},
		{ADC_REG_wclamp_lcnt, 2},

		//csgen start sync real hsync
		{ADC_REG_csgen_start, 0x49},
		{ADC_REG_cs2_r_clamp_ref_edge, 1},
		{ADC_REG_cs2_g_clamp_ref_edge, 1},
		{ADC_REG_cs2_b_clamp_ref_edge, 1},
	{0xffff,0xffff},

	{Adc_kSourceVGA, 0xff00},
		{ADC_REG_lcg_clamp_mode_rb, 0},
        {ADC_REG_cvbs_clamp_mode_g, 0},
		{ADC_REG_cvbs_clamp_mode_rb, 0},
		
        //power down Y channel
		{ADC_REG_CVBSO_PWD12, 1},
		{ADC_REG_pwdny, 1},
        
        //Differential mode setting
		{ADC_REG_y_pden12v, 0},

		{ADC_REG_pll_ref_sel, 1},
		{ADC_REG_o_pclk_sel, 0},
		{ADC_REG_ohs_pll_sel, 1},
		{ADC_REG_csync_tcg_sel, 1},
		{ADC_REG_o_hsync_sel,0x1},
		{ADC_REG_o_vsync_sel,0x01},
		{ADC_REG_cs2_sog_sw_rst_sel, 0x1},

		{ADC_REG_vbg_i_ctrl, 0x9},
		{ADC_REG_sch_pbw_ctrl, 9},
		{ADC_REG_sch_ref_pbw_ctrl, 9},
		{ADC_REG_lcg_r33vcm_sel, 0x1},
		{ADC_REG_lcg_g33vcm_sel, 0x1},
		{ADC_REG_lcg_b33vcm_sel, 0x1},

		//ADC power 1.1v to 0.95v, adjust vcm range 0.55v to 0.5v
		{ADC_REG_r_12vcm_sel, 0x7},
		{ADC_REG_g_12vcm_sel, 0x7},
		{ADC_REG_b_12vcm_sel, 0x7},
		{ADC_REG_12vcm_sel_msb, 0},
		{ADC_REG_b_pg12v1, 2},
		{ADC_REG_dgain_r, 0x80},
		{ADC_REG_dgain_g, 0x80},
		{ADC_REG_dgain_b, 0x80},
		//ff chip and high temperature will let pll unstable, set 5(1.15v) to 3(1.05v)
		{ADC_REG_vbg_sel, 0x3},

		{ADC_REG_adjsifclr12v2, 0},
		
		{ADC_REG_b_sypp12, 0},
		{ADC_REG_cs2_r_clamp_start, 0},
		{ADC_REG_cs2_r_clamp_width, 3},
		{ADC_REG_cs2_g_clamp_start, 0},
		{ADC_REG_cs2_g_clamp_width, 3},
		{ADC_REG_cs2_b_clamp_start, 0},
		{ADC_REG_cs2_b_clamp_width, 3},
		{ADC_REG_cs_rthd, 0xf},
		{ADC_REG_csync_en_sw_ctrl, 0x3},
		{ADC_REG_rwclampeco, 0},
		//clamppdn
		{ADC_REG_clamppdn_en, 1},
		{ADC_REG_r_clamppdn_st, 0x10},
		{ADC_REG_r_clamppdn_end, 0x10},
		{ADC_REG_g_clamppdn_st, 0x10},
		{ADC_REG_g_clamppdn_end, 0x10},
		{ADC_REG_b_clamppdn_st, 0x10},
		{ADC_REG_b_clamppdn_end, 0x10},

		{ADC_REG_sdmresetj, 0},
		{ADC_REG_sdm_type_sel, 0},
		{ADC_REG_dco_en_fdiv, 0x1},
		{ADC_REG_dco_pdiv_rstj, 0x1},
		{ADC_REG_datain_ini_7to0, 0x01},
		{ADC_REG_datain_ini_15to8, 0},
		{ADC_REG_datain_ini_16, 0},
		{ADC_REG_dco_bx2, 0},
		{ADC_REG_dbgsela, 0},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_sdmresetj, 0},
		{ADC_REG_sdm_type_sel, 0},
		{ADC_REG_iir_fbpn1_f, 0xf6},
		{ADC_REG_iir_fbpn1_i_7to0, 0x81},
		{ADC_REG_iir_fbpn1_i_8, 0},
		{ADC_REG_iir_fbppn1_f, 0xf6},
		{ADC_REG_iir_fbppn1_i_7to0, 0x60},
		{ADC_REG_iir_fbppn1_i_8, 0x1},
		{ADC_REG_iir_fwn1_f, 0x4a},
		{ADC_REG_iir_fwn1_i_7to0, 0x18},
		{ADC_REG_iir_fwn1_i_8, 0},
		{ADC_REG_iir_fwpn1_f, 0x14},
		{ADC_REG_iir_fwpn1_i_7to0, 0},
		{ADC_REG_iir_fwpn1_i_8, 0},
		{ADC_REG_iir_fwppn1_f, 0x36},
		{ADC_REG_iir_fwppn1_i_7to0, 0x18},
		{ADC_REG_iir_fwppn1_i_8, 0},
		{ADC_REG_iirclk_div_sel, 0x3},

		//sog reset for PC mode
		{ADC_REG_cs2_sog_sw_rst, 0x1},

		//DLPLL phase detector reset
		{ADC_reg_vsync_mask_tpll_en, 0x3},
		{ADC_reg_vsync_mask_tpll_en, 0x1},

		{ADC_REG_sdmresetj, 0x1},
		{ADC_REG_sdm_type_sel, 0x1},
		{ADC_REG_dco_refdiv, 0},
		{ADC_REG_dlpll_pdiv_rstj, 0x0},
		{ADC_REG_dlpll_pdiv_rstj, 0x1},

		//digital gain & offset enable
		{ADC_REG_beofst_en0, 0x1},
		{ADC_REG_begain_en0, 0x1},
		{ADC_REG_dgain_op0, 0x1},
		{ADC_REG_r_sb1, 0x10},
		{ADC_REG_g_sb1, 0x10},
		{ADC_REG_b_sb1, 0x10},

		//filter differential board noise
		{ADC_REG_refinsel12v, 1},

		//always clamp power down enable before WB
		{ADC_REG_r_clamppdn_mod, 2},
		{ADC_REG_g_clamppdn_mod, 2},
		{ADC_REG_b_clamppdn_mod, 2},

		//Hsync miss threshold
		{ADC_REG_cs2_rst_sog_maxhp_en_14to8, 0x0f},
		{ADC_REG_cs2_rst_sog_maxhp_en, 1},

		//k8880 hsync miss issue, modified filter 200ns to 80ns
		{ADC_REG_db_sel_ext, 0x0},
		{ADC_REG_cs_debounce, 0x0},
		{ADC_REG_db_sel_ext1, 0x1},

		//VGA and YPP couple issue
		{ADC_REG_sog_ch1_sel, 0},
		{ADC_REG_sog_ch_sel, 0},

		//pll hardware reset disable
		{ADC_REG_cs2_pll_rst_sel, 1},

	{0xffff,0xffff},
};

#define ADCModeSettingTableSize 	sizeof(ADCModeTable)/sizeof(UINT32[2])
#define ADCSouceInitBaseTableSize sizeof(ADCSouceInitBaseTable)/sizeof(UINT32[2])

#endif