#ifndef _ADC_REG_H_ #define _ADC_REG_H_ #include #define Adc_kSourceCOMP1 YPP1 //YPP_INPUT #define Adc_kSourceCOMP2 YPP2 //YPP_INPUT2 #define Adc_kSourceCOMP3 YPP3 //YPP_INPUT3 #define Adc_kSourceSCART_RGB1 SCART_RGB1 #define Adc_kSourceVGA DSUB //VGA //ADC register #define I2cAddrADC 0x9A #define MMIOAddrADC 0xbe150000 //cs option /* 0x000[0] Reset all digital blocks */ #define ADC_REG_adi_reset 0x00000000 /* 0x000[1] 1: single direction debouncing (only low pulse) 0: double direction debouncing (high pulse and low pulse) */ #define ADC_REG_cs_debounce 0x00210000 /* 0x000[2] Csync input polarity adjust */ #define ADC_REG_adi_pol_cs 0x00420000 /* 0x000[3] 0: debouncing length controlled by sd_mode, 1: debouncing length controlled by register */ #define ADC_REG_cs_db_ctrl 0x00630000 /* 0x000[5:4] 3 types (use reg_cs_coast_sel and reg_cs_coast_every to form 5 combination) */ #define ADC_REG_cs_coast_sel 0x00a40000 /* 0x000[7:6] 0,3: both_stable = rstable_nom && fstable_nom 1: both_stable = rstable_nom 2: both_stable = fstable_nom */ #define ADC_REG_cs_stable_condition 0x00e60000 /* 0x001[4:0] Csync range stable threshold in rclk cycle(risng-to-risng, falling-to-falling) */ #define ADC_REG_cs_rthd 0x00800001 /* 0x001[7:5] Debounce delay select (only works when reg_cs_debounce = 1) 0: 4 cycles, 1: 9 cycles, 2: 14cycles, 3: 19 cycles, 4: 24cycles, 5: 29cycles, 6: 34cycles, 7: 39cycles */ #define ADC_REG_cs_db_sel 0x00e50001 /* 0x002[7:0] Csync number limitation for coast (Continuous stable line threshold), the value should larger than pulse-width of vsync and less than pulse-distance between two vsyncs */ #define ADC_REG_cs_count_rise_lim 0x00e00002 /* 0x003[5:0] Coast length */ #define ADC_REG_cs_coast_length 0x00a00003 /* 0x003[7:6] 1: dport 1 , others: dport 0 */ #define ADC_REG_cs_dport_sel 0x00e60003 /* 0x004[3:0] Post coast */ #define ADC_REG_cs_post_coast 0x00600004 /* 0x004[6:4] Pre coast */ #define ADC_REG_cs_pre_coast 0x00c40004 /* 0x004[7] 1: vs_level_cnt fast forwarded to its destination, when the threshold met */ #define ADC_REG_cs_vsff 0x00e70004 /* 0x005[2:0] Coast start line for type 0 */ #define ADC_REG_cs_coast_start 0x00400005 /* 0x005[3] 1:Set the coast output(coast_pw) to high until cs_stable_i2 */ #define ADC_REG_cs_coast_defaulth 0x00630005 /* 0x005[6:4] Csync (vsync) stable threshold in hsync count (for cs_stable_i) (stable threshold for field line count) */ #define ADC_REG_cs_vstable_thd 0x00c40005 // 0x005[7] reserved /* 0x006[7:0] Use "N" stable lines to search Htotal maximum value */ #define ADC_REG_cs_httl_sch_range 0x00e00006 /* 0x007[7:0] Coast start position for type 1 and 2 for indicating hsync */ #define ADC_REG_cs_coast_pstart 0x00e00007 /* 0x008[7:0] Coast end position for type 1 and 2 for indicating hsync */ #define ADC_REG_cs_coast_pend 0x00e00008 /* 0x009[0] Coast all except hsync */ #define ADC_REG_cs_coast_every 0x00000009 /* 0x009[1] Coast polarity adjust */ #define ADC_REG_cs_coast_pol 0x00210009 /* 0x009[2] Clamp polarity adjust */ #define ADC_REG_cs_clamp_pol 0x00420009 /* 0x009[3] Field polarity adjust */ #define ADC_REG_cs_field_pol 0x00630009 /* 0x009[7:4] Vsync inactive detection threshold 0: 2/16 htotal, 1: 3/16 htotal, 2: 4/16 htotal, 3: 5/16 htotal 4: 6/16 htotal, 5: 7/16 htotal, 6: 8/16 htotal, 7: 9/16 htotal 8: 1/16 htotal */ #define ADC_REG_cs_vshp 0x00e40009 /* 0x00a[7:0] Clamp start position after hsync (refer to Csync rising(second) edge) */ #define ADC_REG_cs_clamp_start 0x00e0000a /* 0x00b[7:0] Clamp duration */ #define ADC_REG_cs_clamp_width 0x00e0000b /* 0x00c[3:0] Vsync active detection threshold 0: 2/16 htotal, 1: 3/16 htotal, 2: 4/16 htotal, 3: 5/16 htotal 4: 6/16 htotal, 5: 7/16 htotal, 6: 8/16 htotal, 7: 9/16 htotal 8: 1/16 htotal */ #define ADC_REG_cs_vslp 0x0060000c /* 0x00c[7:4] The 4 extentsion bits (MSB) for reg_cs_rthd */ #define ADC_REG_cs_rthd_ms4b 0x00e4000c /* 0x00d[0] Select a field as output, 0: original, 1: alternative one */ #define ADC_REG_cs_field_sel 0x0000000d /* 0x00d[2:1] Set the line center threshold for alternative field, 0: 4/16~12/16, 1: 2/16~10/16, 2: 6/16~14/16, 3: 7/16~15/16 */ #define ADC_REG_dlc_thold_sel 0x0041000d /* 0x00d[5:4] Select a hsync as output, 0: hs masked by hs_filter, 1: hs masked by hs_filter_fpls_pass, 2: hs masked by hs_filter_spls_pass */ #define ADC_REG_cs_hs_out_sel 0x00a4000d // 0x00d[7:6] reserved /* 0x00e[2:0] Select a vsync as output, 0: vs_active_org, 2: vs_active_autoend, 3: vs_active_2thold, 5: rg_vsync*/ #define ADC_REG_cs_vs_sel 0x0040000e // 0x00e[5:3] reserved /* 0x00e[7:6] Set timeout for the coast-gen */ #define ADC_REG_adi_rclk_freq 0x00e6000e /* 0x00f[3:0] Set a range to distinguish the pulse width of hsync, vsync, mv pulse */ #define ADC_REG_cs_hpw_range 0x0060000f /* 0x00f[7:4] The stable count threshold to record the pulse width of hsync */ #define ADC_REG_cs_hpw_scount_thold 0x00e4000f //cs2 option /* 0x010[7:0] Clamp start position after the reference Hsync-edge */ #define ADC_REG_cs2_r_clamp_start 0x00e00010 /* 0x011[7:0] Clamp duration after clamp start */ #define ADC_REG_cs2_r_clamp_width 0x00e00011 /* 0x012[7:0] Clamp start position after the reference Hsync-edge (rising for falling edge) */ #define ADC_REG_cs2_g_clamp_start 0x00e00012 /* 0x013[7:0] Clamp duration after clamp start */ #define ADC_REG_cs2_g_clamp_width 0x00e00013 /* 0x014[7:0] Clamp start position after the reference Hsync-edge (rising for falling edge) */ #define ADC_REG_cs2_b_clamp_start 0x00e00014 /* 0x015[7:0] Clamp duration after clamp start */ #define ADC_REG_cs2_b_clamp_width 0x00e00015 /* 0x016[0] Reference edge of H-sync for start clamping, 0: rising edge, 1:falling (leading) edge */ #define ADC_REG_cs2_r_clamp_ref_edge 0x00000016 /* 0x016[1] Reference edge of H-sync for start clamping, 0: rising edge, 1:falling (leading) edge */ #define ADC_REG_cs2_g_clamp_ref_edge 0x00210016 /* 0x016[2] Reference edge of H-sync for start clamping, 0: rising edge, 1:falling (leading) edge*/ #define ADC_REG_cs2_b_clamp_ref_edge 0x00420016 // 0x016[3] reserved /* 0x016[4] Select the clamp-enable to r-channel, 0:clamp from clamp-gen, 1:external clamp*/ #define ADC_REG_o_rclamp_sel 0x00840016 /* 0x016[5] Select the clamp-enable to g-channel, 0:clamp from clamp-gen, 1:external clamp*/ #define ADC_REG_o_gclamp_sel 0x00a50016 /* 0x016[6] Select the clamp-enable to b-channel, 0:clamp from clamp-gen, 1:external clamp*/ #define ADC_REG_o_bclamp_sel 0x00c60016 /* 0x016[7] Extension for r,g,b clamp, when this bit is high, rgb_clamp = ! X_clamp_sel */ #define ADC_REG_o_rgbclamp_sel_extension 0x00e70016 /* 0x017[0] Control the polarity of the hsync from cg to pll (by xor) */ #define ADC_REG_ohs_pll_hsfcg_pol 0x00000017 /* 0x017[1] */ #define ADC_REG_icoast1_sel 0x00210017 /* 0x017[2] Select the coast to sog-slicer, 0: coast_pw from coast-gen, 1:external coast */ #define ADC_REG_icoast_sel 0x00420017 /* 0x017[3] Select the Hsync to PLL(as reference clock), 0: Hsync from coast -gen, 1: slected external Hsync */ #define ADC_REG_ohs_pll_sel 0x00630017 /* 0x017[4] */ #define ADC_REG_cs2_csync_tcg_sel 0x00840017 /* 0x017[6:5] Select a coast to pll, 0: coast_fss, 1: coast_fcg, 2: external coast, 3: 1'b0 */ #define ADC_REG_cs2_coast_tpll_sel 0x00c50017 // 0x017[7] reserved /* 0x018[14:0] (0x019[6:0] ~ 0x018[7:0]) Maximum H-sync period for SOG reset block */ #define ADC_REG_cs2_rst_sog_maxhp 0x01c00018 /* 0x019[6:0] Maximum H-sync period for SOG reset block bit 14~8 */ #define ADC_REG_cs2_rst_sog_maxhp_en_14to8 0x00c00019 /* 0x019[7] Enable the (maxhp) setting for SOG reset block, 0:disable, 1:enable */ #define ADC_REG_cs2_rst_sog_maxhp_en 0x00e70019 /* 0x01a[0] The second reset register for PLL, 0:non-active, 1:active (reset) */ #define ADC_REG_cs2_pll_sw_rst 0x0000001a /* 0x01a[1] Software reset for PLL block, 0: controled by PLL register, 1:controlled by previous bit */ #define ADC_REG_cs2_pll_rst_sel 0x0021001a /* 0x01a[2] Software reset for SOG digital circuit, 0:non-active, 1:active (reset) */ #define ADC_REG_cs2_sog_sw_rst 0x0042001a /* 0x01a[3] Software control for the reset to SOG digital circuit, 0: reset by hw, 1: sw_ctrl */ #define ADC_REG_cs2_sog_sw_rst_sel 0x0063001a /* 0x01a[3:2] */ #define ADC_REG_cs2_sog_rst 0x0062001a /* 0x01a[4] */ #define ADC_REG_cs2_pdiv_sw_rst 0x0084001a /* 0x01a[5] */ #define ADC_REG_cs2_pdiv_sw_rst_ctrl 0x00a5001a // 0x01a[7:6] reserved /* 0x01b[3:0] Loss sync reset mask */ #define ADC_REG_cs2_sog_lsync_rst_mask 0x0060001b /* 0x01b[5:4] Sogout select, 0: csync_tcg, 1: ext_hsync, 2: hsync_fcg, 3: hs_filter_fcg */ #define ADC_REG_o_sog_sel 0x00a4001b // 0x01b[7:6] reserved /* 0x01c[0] Polarity adjust for external weak clamp, 0: original, 1: inverse */ #define ADC_REG_ew_clamp_pol 0x0000001c /* 0x01c[1] Polarity adjust for external strong clamp, 0: original, 1: inverse */ #define ADC_REG_es_clamp_pol 0x0021001c /* 0x01c[2] Polarity adjust for external coast, 0: original, 1: inverse */ #define ADC_REG_e_coast_pol 0x0042001c // 0x01c[3] reserved /* 0x01c[4] Polarity adjust for external red clamp, 0: original, 1: inverse */ #define ADC_REG_er_clamp_pol 0x0084001c /* 0x01c[5] Polarity adjust for external green clamp, 0: original, 1: inverse */ #define ADC_REG_eg_clamp_pol 0x00a5001c /* 0x01c[6] Polarity adjust for external blue clamp, 0: original, 1: inverse */ #define ADC_REG_eb_clamp_pol 0x00c6001c // 0x01c[7] reserved /* 0x01d[0] External Hsync select, 0: Hsync0, 1: Hsync1 */ #define ADC_REG_e_hsync_sel 0x0000001d /* 0x01d[1] Polarity adjust for the selected external Hsync, 0: original, 1: inverse */ #define ADC_REG_e_hsync_pol 0x0021001d /* 0x01d[2] External Vsync select, 0: Vsync0, 1: Vsync1 */ #define ADC_REG_e_vsync_sel 0x0042001d /* 0x01d[3] Polarity adjust for the selected external Vsync, 0: original, 1: inverse */ #define ADC_REG_e_vsync_pol 0x0063001d // 0x01d[7:4] reserved /* 0x01e[2:0] Select the output for hsout, 0: hsync_fpll, 1: external hsync, 2: hsync_fcg, 3: hs_filter_fcg, 4: ckpll_bf */ #define ADC_REG_o_hsync_sel 0x0040001e /* 0x01e[3] Polarity adjust for the output Hsync, 0: original, 1: inverse */ #define ADC_REG_o_hsync_pol 0x0063001e /* 0x01e[4] Pixel clock output select, 0: inverse-green clk, 1:green clock */ #define ADC_REG_o_pclk_sel 0x00a4001e // 0x01e[7:6] reserved /* 0x01f[0] Vsync output select, 0: Vsync from coast-gen, 1: the selected external Vsync */ #define ADC_REG_o_vsync_sel 0x0000001f /* 0x01f[1] Polarity adjust for the selected output Vsync, 0: original, 1: inverse */ #define ADC_REG_o_vsync_pol 0x0021001f /* 0x01f[2] Vsync output select, 0: vsync_selected, 1: vsync_masked */ #define ADC_REG_o_vsync_win_en 0x0042001f /* 0x01f[3] Polarity adjust for the output SOG, 0: original, 1: inverse */ #define ADC_REG_o_sog_pol 0x0063001f /* 0x01f[5:4] Select a coast to mask sog, 0: coast_fss, 1: coast_fcg, 2: external coast, 3: 1'b0 */ #define ADC_REG_o_coast_sel 0x00a4001f // 0x01f[7:6] reserved //cs3 option /* 0x020[11:0] (0x021[3:0] ~ 0x020[7:0]) The delay of the pll-reset to sync-buffer reset (24MHz) */ #define ADC_REG_sbuf_rst_dly 0x01600020 /* 0x021[4] Enable the delay option for sync-buffer */ #define ADC_REG_sbuf_rst_dly_en 0x00840021 // 0x021[7:5] reserved // 0x022[7:0] reserved #define ADC_REG_dbg_temp 0x00e00022 // 0x023[7:0] reserved /* 0x024[6:0] The 16LSBs of the debug port selection */ #define ADC_REG_dbg_port_lw_sel 0x00c00024 // 0x024[7] reserved /* 0x025[6:0] The 16MSBs of the debug port selection */ #define ADC_REG_dbg_port_hw_sel 0x00c00025 // 0x025[7] reserved /* 0x026[15:0] (0x027[7:0] ~ 0x026[7:0]) The two clear bytes for clearing the interrupt vector bits */ #define ADC_REG_int_clear_byte 0x01e00026 /* 0x028[15:0] (0x029[7:0] ~ 0x028[7:0]) The two mask bytes for masking the interrupt vector bits */ #define ADC_REG_int_mask_byte 0x01e00028 /* 0x02a[7:0] The timeout threshold for the cg-interrupt module */ #define ADC_REG_cg_int_timeout 0x00e0002a /* 0x02b[7:0] The threshold for fast-coast interrupt */ #define ADC_REG_cg_int_fcoast_period 0x00e0002b /* 0x02c[7:0] The threshold for unstable-coast interrupt */ #define ADC_REG_cg_int_stable_coast_range 0x00e0002c /* 0x02d[3:0] Vsync window start */ #define ADC_REG_vwindow_start 0x0060002d /* 0x02d[7:4] Vsync window start */ #define ADC_REG_vwindow_width 0x00e4002d // 0x02e[7:0] reserved // 0x02f[7:0] reserved //PLL+VBG /* 0x030[7:0] The version of the p333 ADC */ #define ADC_REG_revision 0x00e00030 /* 0x032[0] ADC PLL reset, 0: reset, 1: normal */ #define ADC_REG_pll_rstn 0x00000032 /* 0x032[1] ADC PLL power control, 0: power down, 1: normal */ #define ADC_REG_pll_pwdn 0x00210032 /* 0x032[2] Independent PLL post divider reset pin, 0: reset, 1: normal */ #define ADC_REG_pdiv_rstn 0x00420032 /* 0x032[3] Independent PLL post divider reset pin, 0: disable, 1: enable */ #define ADC_REG_pll_pdiv_en 0x00630032 /* 0x032[7:4] */ #define ADC_REG_pll_i2ctrl 0x00e40032 /* 0x033[1:0] */ #define ADC_REG_pll_gb_vb 0x00200033 /* 0x033[2] */ #define ADC_REG_pll_pout_rstj 0x00420033 // 0x033[3] reserved /* 0x033[7:4] */ #define ADC_REG_pll_ictrl 0x00e40033 // 0x034[0] reserved /* 0x034[5:1] Clock to R channel phase selector(131: 3-ch phase selector). */ #define ADC_REG_pll_phase_r_sel 0x00a10034 // 0x034[7:6] reserved // 0x035[0] reserved /* 0x035[5:1] Clock to G channel phase selector(131: removed). */ #define ADC_REG_pll_phase_g_sel 0x00a10035 // 0x035[7:6] reserved // 0x036[0] reserved /* 0x036[5:1] Clock to B channel phase selector(131: removed). */ #define ADC_REG_pll_phase_b_sel 0x00a10036 // 0x036[7:6] reserved /* 0x037[7:0] */ #define ADC_REG_pll_mul_LSBs 0x00e00037 /* 0x038[4:0] ADC PLL Multiplier N. */ #define ADC_REG_pll_mul_MSBs 0x00600038 // 0x038[7:5] reserved /* 0x039[1:0] Phase divider stage1 setting, its value is 2^x, where x is reg value. b'00: 1, b'01: 2, b'10: 4, b'11: 8 */ #define ADC_REG_pll_div_sel 0x00200039 /* 0x039[3:2] Phase divider stage2 setting, its value is 2+x, where x is reg value. b'00: 2, b'01: 3, b'10: 4, b'11: 5 */ #define ADC_REG_pll_divb_sel 0x00620039 /* 0x039[4] External pixel clock select, 0: PLL-SOG pixel sampling clock, 1: external pixel clock input mode. */ #define ADC_REG_pll_extpclk_sel 0x00840039 // 0x039[7:5] reserved /* 0x03a[6:0] */ #define ADC_REG_pll_gb_vc 0x00c0003a // 0x03a[7] reserved // 0x03b[7:0] reserved /* 0x03c[3:0] Bandgap voltage control. 0: max, f: min. */ #define ADC_REG_vbg_v_ctrl 0x0060003c /* 0x03c[7:4] Bias current control, need 4-16 decoder. 0: max, f: min. */ #define ADC_REG_vbg_i_ctrl 0x00e4003c /* 0x03d[0] Bandgap power down control. */ #define ADC_REG_vbg_pwdn 0x0000003d // 0x03d[7:1] reserved /* 0x03e[5:0] */ #define ADC_REG_pll_ext_pclk_dly 0x00a0003e // 0x03e[7:6] reserved /* 0x03f[3:0] (removed) Setting the pulse with, by pixel clock. */ #define ADC_REG_pll_hsync_pw 0x0060003f /* 0x03f[5:4] ADCPLL reference select. 0: ckpll_bf(YPbPr), 1: ext_hsync(VGA), 2: reg_dco_bx2(AV), 3: reg_dco_bx2(AV). */ #define ADC_REG_pll_ref_sel 0x00a4003f /* 0x03f[7:6] */ #define ADC_REG_pll_refdiv 0x00e6003f //cs4 option /* 0x040[5:0] Second clamp_en for RGB channels, the start is set when the clamp should be start after vsync pass, this value can't larger than the reg_cs_count_rise_lim in cg-register*/ #define ADC_REG_cs_clamp2nd_start 0x00a00040 // 0x040[6] reserved /* 0x040[7] The clamp enable select, 0: original, 1: clamp_en_2nd */ #define ADC_REG_cs_clamp_sel 0x00e70040 /* 0x041[4:0] Stable hsout period threshold for the unstable hsout period estimation. */ #define ADC_REG_shsp_thold 0x00800041 /* 0x041[7:5] The number of unstable hsout pulses to assert interrupt for unstable hsout period. */ #define ADC_REG_ushsp_pls_thold 0x00e50041 /* 0x042[7:0] Max macro vision period, this should not >= 1080p h-period. */ #define ADC_REG_mv_period_thold 0x00e00042 /* 0x043[7:0] Stable range for the mv pulse periods. */ #define ADC_REG_mv_srange 0x00e00043 /* 0x044[1:0] Timeout control for macro vision detector, 0: 36ms, 1: 72ms, 2: 144ms, 3: 18ms */ #define ADC_REG_mv_tout_thold 0x00200044 // 0x044[7:2] reserved /* 0x045[3:0] How many mv pulses to reckon as macro vision signal detected. */ #define ADC_REG_mv_pls_thold 0x00600045 /* 0x045[4] The polarity control for the csync input of coast-gen. */ #define ADC_REG_csync_in_cg_pol_ctrl 0x00840045 /* 0x045[5] Select a input for coast-gen block, 0: sog from sog-slicer, 1: C-sync from external H,V-sync (pc_mode) */ #define ADC_REG_csync_tcg_sel 0x00a50045 // 0x045[7:6] reserved /* 0x046[0] Extend the debug port of coast-gen. */ #define ADC_REG_cg_dport_ext 0x00000046 // 0x046[1] reserved /* 0x046[3:2] Timeout control for cih (Csync In Hsync) detector, 0: 36ms, 1: 72ms, 2: 144ms, 3: 18ms */ #define ADC_REG_cstout_ctrl 0x00620046 /* 0x046[5:4] Timeout control for v-sync active detector, 0: 36ms, 1: 72ms, 2: 144ms, 3: 18ms */ #define ADC_REG_vs_atout_ctrl 0x00a40046 /* 0x046[7:6] Timeout control for h-sync active detector, 0: 36ms, 1: 72ms, 2: 144ms, 3: 18ms */ #define ADC_REG_hs_atout_ctrl 0x00e60046 /* 0x047[7:0] Timeout threshold for clamp interrupt, the computing formula is 40ns * (reg_clamp_int_tout_thold<<8 | 0x64) */ #define ADC_REG_clamp_int_tout_thold 0x00e00047 /* 0x048[7:0] High to low threshold for degiltch module. */ #define ADC_REG_dg_h2l_thold 0x00e00048 /* 0x049[7:0] Low to high threshold for degiltch module. */ #define ADC_REG_dg_l2h_thold 0x00e00049 /* 0x04a[0] Extension to the reg_cs_debounce, 0: two direction, 1: one_direction, 2: regen csync, 3: deglitched csync */ #define ADC_REG_db_sel_ext 0x0000004a /* 0x04a[1] Disable the auto-detection of csync in hsync. */ #define ADC_REG_pc_cs_dtor_ctrl_disable 0x0021004a /* 0x04a[3:2] */ #define ADC_REG_csync_pcmode_sw_ctrl 0x0062004a /* 0x04a[4] Priority of the auto source select, 1: pcmode, 0: ypp */ #define ADC_REG_ss_priority 0x0084004a /* 0x04a[5] Auto source select mode, 0:auto, 1:manual */ #define ADC_REG_ss_mode 0x00a5004a /* 0x04a[7:6] Software control for the csync enable fromm sslicer,*/ #define ADC_REG_csync_en_sw_ctrl 0x00e6004a /* 0x04b[0] reg_csync_en_sw_ctrl[1] ? reg_csync_en_sw_ctrl[0] : csync_en */ #define ADC_REG_8b_10b_ctrl 0x0000004b /* 0x04b[1] Postive glitch elimination option, 1: on, 0: off */ #define ADC_REG_hs_samples_clk_sel 0x0021004b /* 0x04b[3:2] Select a source for degitch block, 0:csync, 1:synct, 2:cs_gen */ #define ADC_REG_source_sel 0x0062004b /* 0x04b[6:4] Multi-edge counter reset */ #define ADC_REG_mecounter_max 0x00c4004b /* 0x04b[7] 0: cs2_llpll, 1: rg_hsync */ #define ADC_REG_hs_fcg_sel 0x00e7004b /* 0x04c[5:0] Stable range for regen block, based on 20ns */ #define ADC_REG_stable_range_for_rg 0x00a0004c /* 0x04c[7:6] Select a source to regen-csync block, 0: auto, 1: csync_fpls (deglitched), 2: a, 3: b */ #define ADC_REG_psfedge_sw_ctrl 0x00e6004c /* 0x04d[1:0] Pulse width control for regenerated hsync. */ #define ADC_REG_rg_hwidth_ctrl 0x0020004d /* 0x04d[3:2] Select the pulse to stable edge detector, 0: fpls, 1: rpls, 2: valid_rise, 3: valid_fall */ #define ADC_REG_edge_pls_tsetdor_ctrl 0x0062004d /* 0x04d[6:4] The threshold for regenerated-vsync */ #define ADC_REG_rg_vsthold_ctrl 0x00c4004d // 0x04d[7] reserved /* 0x04e[1:0] 0: auto, 1: vsync, 2: a, 3: b */ #define ADC_REG_rg_vs_sel 0x0020004e /* 0x04e[3:2] Status register select for address c0-cf. */ #define ADC_REG_cg_st_reg_sel 0x0062004e /* 0x04e[4] Select a period for regen block, 0: dynamic, */ #define ADC_REG_ref_period_sel 0x0084004e /* 0x04e[5] */ #define ADC_REG_vs_for_pwc_sel 0x00a5004e /* 0x04e[6] */ #define ADC_REG_vs_for_pwc_pol 0x00c6004e // 0x04e[7] reserved /* 0x04f[0] */ #define ADC_REG_extn_wclamp 0x0000004f /* 0x04f[1] */ #define ADC_REG_extn_sclamp 0x0021004f /* 0x04f[2] */ #define ADC_REG_7b_10b_ctrl 0x0042004f /* 0x04f[3] */ #define ADC_REG_6b_10b_ctrl 0x0063004f /* 0x04f[5:4] */ #define ADC_REG_cg_source_sel 0x00a4004f /* 0x04f[6] 1080p option */ #define ADC_REG_db_sel_ext1 0x00c6004f /* 0x04f[7] */ #define ADC_REG_calibration_sel 0x00c6004f //LCG_SCH /* 0x050[0] */ #define ADC_REG_lcg_pwdn 0x00000050 /* 0x050[1] Atuo gain control. */ #define ADC_REG_lcg_autogain 0x00210050 // 0x050[3:2] reserved /* 0x050[6:4] Red channel input select. 0: VGA, 1: YPbPr, 6: internal(AWB) */ #define ADC_REG_lcg_rch_sel 0x00c40050 // 0x050[7] reserved /* 0x051[2:0] Green channel input select. 0: VGA, 1: YPbPr, 6: internal(AWB) */ #define ADC_REG_lcg_gch_sel 0x00400051 // 0x051[3] reserved /* 0x051[6:4] Red channel input select. 0: VGA, 1: YPbPr, 6: internal(AWB) */ #define ADC_REG_lcg_bch_sel 0x00c40051 // 0x051[7] reserved /* 0x052[4:0] Red channel clamping voltage select(See STG1 clamp table). */ #define ADC_REG_r_sb1 0x00800052 // 0x052[7:5] reserved /* 0x053[4:0] Green channel clamping voltage select(See STG1 clamp table). */ #define ADC_REG_g_sb1 0x00800053 // 0x053[7:5] reserved /* 0x054[4:0] Blue channel clamping voltage select(See STG1 clamp table). */ #define ADC_REG_b_sb1 0x00800054 // 0x054[7:5] reserved /* 0x055[3:0] Red channel clamping voltage select, LSB. */ #define ADC_REG_r_sb2 0x00600055 /* 0x055[7:4] Green channel clamping voltage select, LSB. 00: VREFP, 01: VCM, 10: VREFN */ #define ADC_REG_g_sb2 0x00e40055 /* 0x056[3:0] Blue channel clamping voltage select, LSB. */ #define ADC_REG_b_sb2 0x00600056 /* 0x056[4] */ #define ADC_REG_lcg_clamp_mode_rb 0x00840056 // 0x056[7:5] reserved // 0x057[7:0] reserved /* 0x058[3:0] Signal bandwidth control, its value is determined by the pixel clock of current timing. (i.e. the PixelClock of timing table multiply reference sampling enlarge rate) */ #define ADC_REG_sch_pbw_ctrl 0x00600058 /* 0x058[7:4] Reference bandwidth control, its value is determined by the pixel clock of current timing. (i.e. the PixelClock of timing table multiply reference sampling enlarge rate) */ #define ADC_REG_sch_ref_pbw_ctrl 0x00e40058 /* 0x059[0] R channel power down. */ #define ADC_REG_sch_pwdn_r 0x00000059 /* 0x059[1] G channel power down. */ #define ADC_REG_sch_pwdn_g 0x00210059 /* 0x059[2] B channel power down. */ #define ADC_REG_sch_pwdn_b 0x00420059 // 0x059[3] reserved /* 0x059[4] */ #define ADC_REG_sch_e15db_r 0x00840059 /* 0x059[5] */ #define ADC_REG_sch_e15db_g 0x00a50059 /* 0x059[6] */ #define ADC_REG_sch_e15db_b 0x00c60059 // 0x059[7] reserved /* 0x05a[2:0] Red channel ADC common mode select. From 0.56V to 0.63V, 10mv each step. */ #define ADC_REG_lcg_r33vcm_sel 0x0040005a // 0x05a[3] reserved /* 0x05a[6:4] Green channel ADC common mode select. From 0.56V to 0.63V, 10mv each step. */ #define ADC_REG_lcg_g33vcm_sel 0x00c4005a // 0x05a[7] reserved /* 0x05b[2:0] Blue channel ADC common mode select. From 0.56V to 0.63V, 10mv each step. */ #define ADC_REG_lcg_b33vcm_sel 0x0040005b // 0x05b[3] reserved /* 0x05b[6:4] Red channel ADC common mode select. From 0.47V to 0.54V, 10mv each step */ #define ADC_REG_r_12vcm_sel 0x00c4005b // 0x05b[7] reserved /* 0x05c[2:0] Green channel ADC common mode select. From 0.47V to 0.54V, 10mv each step */ #define ADC_REG_g_12vcm_sel 0x0040005c // 0x05c[3] reserved /* 0x05c[6:4] Blue channel ADC common mode select. From 0.47V to 0.54V, 10mv each step */ #define ADC_REG_b_12vcm_sel 0x00c4005c // 0x05c[7] reserved /* 0x05d[0] VCMI option, 0: tracking VCMI(default), 1: external VCMI */ #define ADC_REG_12vcm_sel_msb 0x0000005d // 0x05d[3:1] reserved /* 0x05d[4] */ #define ADC_REG_sch_clamp_mode_g 0x0084005d // 0x05d[7:5] reserved /* 0x05e[2:0] Auto-gain reference voltage select. 000: 1050mv, 001: 1040mv, 010: 560mv, 011: 550mv, 100: 800mv */ #define ADC_REG_lcg_awbsel12v 0x0040005e // 0x05e[3] reserved /* 0x05e[4] Enhance pull down(when signal channel not selected). 1= enable, 0=disable. */ #define ADC_REG_r_epd12v 0x0084005e /* 0x05e[5] Enhance pull down(when signal channel not selected). 1= enable, 0=disable. */ #define ADC_REG_g_epd12v 0x00a5005e /* 0x05e[6] Enhance pull down(when signal channel not selected). 1= enable, 0=disable. */ #define ADC_REG_b_epd12v 0x00c6005e // 0x05e[7] reserved // 0x05f[7:0] reserved /* 0x060[2:0] Red channel gain control, MSB. */ #define ADC_REG_lcg_rmp1 0x00400060 // 0x060[3] reserved /* 0x060[6:4] reserved */ #define ADC_REG_lcg_rmn1 0x00c40060 // 0x060[7] reserved /* 0x061[5:0] Red channel gain control, MSB. */ #define ADC_REG_lcg_rmp2 0x00a00061 // 0x061[7:6] reserved /* 0x062[5:0] reserved */ #define ADC_REG_lcg_rmn2 0x00a00062 // 0x062[7:6] reserved /* 0x063[2:0] Green channel gain control, MSB. */ #define ADC_REG_lcg_gmp1 0x00400063 // 0x063[3] reserved /* 0x0x63[6:4] reserved */ #define ADC_REG_lcg_gmn1 0x00c40063 // 0x063[7] reserved /* 0x064[5:0] Green channel gain control, MSB. */ #define ADC_REG_lcg_gmp2 0x00a00064 // 0x064[7:6] reserved /* 0x065[5:0] reserved */ #define ADC_REG_lcg_gmn2 0x00a00065 // 0x065[7:6] reserved /* 0x066[2:0] Blue channel gain control, MSB. */ #define ADC_REG_lcg_bmp1 0x00400066 // 0x066[3] reserved /* 0x0x66[6:4] reserved */ #define ADC_REG_lcg_bmn1 0x00c40066 // 0x066[7] reserved /* 0x067[5:0] Blue channel gain control, MSB. */ #define ADC_REG_lcg_bmp2 0x00a00067 // 0x067[7:6] reserved /* 0x068[5:0] reserved */ #define ADC_REG_lcg_bmn2 0x00a00068 // 0x068[7:6] reserved /* 0x069[0] (removed) Enable ADC reference output mode. Connect to register. 1= enable. At this mode. All channel clamping voltage select should all be "0". */ #define ADC_REG_lcg_refdbg_en 0x00000069 /* 0x069[1] External reference voltage input mode. At this mode, All channel gain control should all be "0".*/ #define ADC_REG_lcg_extref_in_en 0x00210069 // 0x069[3:2] reserved /* 0x069[5:4] ADC reference output select. Connec to register. 00: VREFP, 01: VCM, 10: VREFN, 11: AWB */ #define ADC_REG_lcg_refdbg_sel_temp 0x00a40069 // 0x069[7:6] reserved /* 0x06a[3:0] Efuse write enable. */ #define ADC_REG_efuse_en_th 0x0060006a // 0x06a[7:4] reserved // 0x06b[7:0] reserved /* 0x06c[3:0] Schmitt trigger high threshold voltage select.(See ref_stg1_table2_p131 file) */ #define ADC_REG_sog_smth12v 0x0060006c /* 0x06c[7:4] Schmitt trigger low threshold voltage select.(See ref_stg1_table2_p131 file) */ #define ADC_REG_sog_smtl12v 0x00e4006c /* 0x6c[7:0] Combine Schmitt trigger low and high threshold voltage select.(See ref_stg1_table2_p131 file) */ #define ADC_REG_sog_smthr12v 0x00e0006c /* 0x06d[3:0] SOG Clamp Voltage Select, from 1.433v to 1.183v, 16.67mV/step.(See ref_stg1_table2_p131 file) */ #define ADC_REG_sog_clamp 0x0060006d /* 0x06d[6:4] {129[7], 6d[4]}, 00=2 close, 01=ch1, 10=ch2, 11=ch3 */ #define ADC_REG_sog_ch_sel 0x00c4006d // 0x06d[7] reserved /* 0x06e[1:0] SOG Comparator Reference Voltage Select, from 1.86v to 1.23v, 10mV/step. */ #define ADC_REG_sog_cmp 0x0020006e // 0x06e[2] reserved /* 0x06e[3] */ #define ADC_REG_sog_pwdn_ef 0x0063006e /* 0x06e[4] SOG Power down. */ #define ADC_REG_sog_pwdn 0x0084006e /* 0x06e[5] */ #define ADC_REG_smt_high_sel 0x00a5006e /* 0x06e[6] */ #define ADC_REG_smt_low_sel 0x00c6006e /* 0x06e[7] */ #define ADC_REG_smt_out_sel 0x00e7006e /* 0x070[2:0] Sync tip find top enter offset. */ #define ADC_REG_st_top_enter_offset 0x00400070 //0x070[3] reserved /* 0x070[7:4] Sync tip find top enter threshold. */ #define ADC_REG_st_top_enter_th 0x00e40070 /* 0x071[2:0] Sync tip find top exit offset. */ #define ADC_REG_st_top_exit_offset 0x00400071 // 0x071[3] reserved /* 0x071[7:4] Sync tip find top exit threshold. */ #define ADC_REG_st_top_exit_th 0x00e40071 /* 0x072[4:0] Sync tip find bottom threshold. */ #define ADC_REG_st_bot_range 0x00800072 /* 0x072[7:5] Add cs_gen timing plus on sync tip top threshold. */ #define ADC_REG_st_top_cgplus 0x00e50072 /* 0x073[2:0] synct_smt option on cur_state=D, fir & iir1 & iir2. */ #define ADC_REG_synct_smt_sth 0x00400073 /* 0x073[3] Disable synct accumalate. */ #define ADC_REG_synct_acc_dis 0x00630073 /* 0x073[4] synct_smt option on cur_state!=D, 0: fir, 1: fir & iir1. */ #define ADC_REG_synct_smt_ini 0x00840073 /* 0x073[5] synct_iir2_smt long tail mask. */ #define ADC_REG_synct_iir2_smt_mask 0x00a50073 /* 0x073[7:6] synct option, 0: org, 1: smt, 2: org+smt, 3: 1'b0. " */ #define ADC_REG_synct_smt_opt 0x00e60073 /* 0x074[2:0] */ #define ADC_REG_smt_fir_th 0x00400074 /* 0x074[3] */ #define ADC_REG_smt_fir_strong 0x00630074 /* 0x074[7:4] Accumulate synct exit threshold. */ #define ADC_REG_st_acc_exit_th 0x00e40074 /* 0x075[5:0] Accumulate synct enter threshold. */ #define ADC_REG_st_acc_enter_th 0x00a00075 // 0x075[7:6] reserved /* 0x076[3:0] Set minimum line width. */ #define ADC_REG_min_line_wdth_opt 0x00600076 /* 0x076[7:4] Set maximum line width. */ #define ADC_REG_max_line_wdth_opt 0x00e40076 /* 0x077[3:0] Set minimum low width.*/ #define ADC_REG_min_line_wdth 0x00600077 /* 0x077[7:4] Set maximum low width. */ #define ADC_REG_max_line_wdth 0x00e40077 /* 0x078[3:0] Low width threshold for sync valid rising. */ #define ADC_REG_synct_low_wdth 0x00600078 // 0x078[7:4] reserved /* 0x079[3:0] Line counter threshold A for sync valid rising. */ #define ADC_REG_hs_vld_r_maska 0x00600079 /* 0x079[7:4] Line counter threshold B for sync valid rising. */ #define ADC_REG_hs_vld_r_maskb 0x00e40079 /* 0x07a[0] Enable sync valid rise reset to avoid too early rising. */ #define ADC_REG_hs_vld_1rst_en 0x0000007a /* 0x07a[1] In line_wdth decision, skip line_cnt=line2_cnt. */ #define ADC_REG_lwdth_skip_l2cnt 0x0021007a // 0x07a[2] reserved /* 0x07a[3] Enable re-caculate line width on cur_state=C. */ #define ADC_REG_rewidth_en 0x0063007a /* 0x07a[4] Skip post vsync blanking during re-caculate line width state. */ #define ADC_REG_rewidth_skip_postvb 0x0084007a /* 0x07a[5] Enable accumulated sync low counter. */ #define ADC_REG_low_cnt_acc_en 0x00a5007a /* 0x07a[6] Enable sync low width mask on vsync blanking. */ #define ADC_REG_low_wdth_vblank_mask 0x00c6007a /* 0x07a[7] */ #define ADC_REG_ml_dis 0x00e7007a /* 0x07b[3:0] Stable line width threshold range. */ #define ADC_REG_line_stable_thd 0x0060007b /* 0x07b[4] Enable check mline_wdth=min_line_wdth. */ #define ADC_REG_mlwdth_chk_lw 0x0084007b /* 0x07b[5] Skip line_wdth_fstable for mline_wdth. */ #define ADC_REG_mlwdth_skip_lfw 0x00a5007b /* 0x07b[6] Skip line_wdth_tstable for mline_wdth. */ #define ADC_REG_mlwdth_skip_tlw 0x00c6007b /* 0x07b[7] */ #define ADC_REG_mlwdth_skip_l2w 0x00e7007b /* 0x07c[1:0] Base threshold of vsync detect vs_synct base source : (quad_min_find+st_find)/2 */ #define ADC_REG_vs_synct_base_opt 0x0020007c // 0x07c[2] reserved /* 0x07c[3] Top threshold of vsync detect 0: vsync_top, 1: synct_top */ #define ADC_REG_vs_synct_top_opt 0x0063007c /* 0x07c[7:4] Sync tip find threshold on vsync. */ #define ADC_REG_vs_synct_th 0x00e4007c /* 0x07d[3:0] Accumulated enter threshold of vsync detect. */ #define ADC_REG_vs_acc_enter_th 0x0060007d /* 0x07d[7:4] Accumulated exit threshold of vsync detect. */ #define ADC_REG_vs_acc_exit_th 0x00e4007d /* 0x07e[0] Sub pass_t end option. */ #define ADC_REG_sub_pass_end_opt 0x0000007e /* 0x07e[1] Enable max sync tip detect on cur_stae=6. */ #define ADC_REG_wait_v_max_tip_en 0x0021007e // 0x07e[3:2] /* 0x07e[4] Skip vsync rising toggle constraint in vsync detect. */ #define ADC_REG_vs_skip_vtog_cnt 0x0084007e /* 0x07e[5] Skip line width constraint in vsync detect. */ #define ADC_REG_vs_skip_mline_wdth 0x00a5007e /* 0x07e[6] Skip low width constraint in vsync detect. */ #define ADC_REG_vs_skip_mlow_wdth 0x00c6007e // 0x07e[7] reserved /* 0x07f[0] Enable iir1 filter in middle level search in vsync. */ #define ADC_REG_mid_mask_iir1_sel 0x0000007f /* 0x07f[1] Tip height option 0: Initial tip height 'h10, 1: Initial tip height 'h14 */ #define ADC_REG_tip_height_opt 0x0021007f // 0x07f[3:2] reserved /* 0x07f[5:4] Macro-vision height check 0: disable check, 1: >1.25 tip height, 2: >1.50 tip height, 3: >2.00 tip height */ #define ADC_REG_mv_height_chk 0x00a4007f /* 0x07f[7:6] Tip height shrink option 0: tri_height > 8/16 * tip_heigh, 1: tri_height > 7/16 * tip_heigh, 2: tri_height > 6/16 * tip_heigh, 3: tri_height > 5/16 * tip_heigh */ #define ADC_REG_tip_h_sh_opt 0x00e6007f //SOG /* 0x080[7:0] Set up line, >576i line period(64us); default=80us. */ #define ADC_REG_line 0x00e00080 /* 0x081[4:0] Signal in/off detect threshold. */ #define ADC_REG_det_on_th 0x00800081 // 0x081[5] reserved /* 0x081[7:6] Options of stay period on cur_state3, 0: 2ms, 1: 4ms, 2: 8ms, 3: 16ms */ #define ADC_REG_det_period_opt 0x00e60081 /* 0x082[2:0] Siync loss voltage range on cur_state=D. */ #define ADC_REG_cpt_loss_range 0x00400082 /* 0x082[3] Enable sync loss voltage detect fucntion. */ #define ADC_REG_cpt_loss_en 0x00630082 /* 0x082[7:4] Sync loss timing range on cur_state=D. */ #define ADC_REG_vblank_ini_length 0x00e40082 /* 0x083[1:0] Length option of passing vsync & post-EQ & MV for clamping. */ #define ADC_REG_loss_sync_opt 0x00200083 /* 0x083[2] Vsync front proch detect. */ #define ADC_REG_vs_fp_wdth 0x00420083 /* 0x083[3] Skip of vsync front porch detect. */ #define ADC_REG_skip_vs_fp 0x00630083 /* 0x083[4] Skip of twice vsync detect which can get more reliable tip height. */ #define ADC_REG_skip_twice_vsync 0x00840083 // 0x083[7:5] reserved /* 0x084[3:0] Signal sum clip limit. */ #define ADC_REG_st_sum_clip_limit 0x00600084 /* 0x084[7:4] Signal sum clip threshold of strong increase. */ #define ADC_REG_st_sum_clip_sith 0x00e40084 /* 0x085[3:0] Signal sum clip threshold of weak increase. */ #define ADC_REG_st_sum_clip_with 0x00600085 /* 0x085[7:4] Signal sum clip threshold of decrease. */ #define ADC_REG_st_sum_clip_dth 0x00e40085 /* 0x086[0] Enable signal sum clip threshold of decrease. */ #define ADC_REG_st_sum_clip_dec 0x00000086 /* 0x086[1] Enable signal sum clip threshold of strong increase. */ #define ADC_REG_st_sum_clip_sinc 0x00210086 /* 0x086[2] Enable signal sum clip threshold of weak increase. */ #define ADC_REG_st_sum_clip_winc 0x00420086 // 0x086[3] reserved /* 0x086[4] 0/1 8tap/16tap FIR1 filter(filter signal sum). */ #define ADC_REG_st_fir1_strong 0x00840086 /* 0x086[5] 0/1 8tap/16tap FIR2 filter(filter FIR1 filter). */ #define ADC_REG_st_fir2_strong 0x00a50086 /* 0x086[7:6] FIR1/FIR2 filter option, add one bit in 55nm. */ #define ADC_REG_st_filt_opt 0x00e60086 /* 0x087[1:0] IIR1 filter strength st_iir1_filt alpha = 4/32(weak), 2/32, 1/32 (strong). */ #define ADC_REG_st_iir1_strength 0x00200087 /* 0x087[3:2] IIR2 filter strength st_iir2_filt alpha = 4/128(strong), 2/128, 1/128 (strong++). */ #define ADC_REG_st_iir2_strength 0x00620087 /* 0x087[5:4] Filter option for sync tip search, 0: auto (st_filt as Vblank & HD), 1: auto (st_filt as HD), 2: st_iir1_filt, 3: st_filt */ #define ADC_REG_st_srch_filt_opt 0x00a40087 // 0x087[7:6] reserved /* 0x088[0] Enable stable strong clamp start. */ #define ADC_REG_stb_sc_1st_update 0x00000088 /* 0x088[1] Enable stable strong clamp vsync rising. */ #define ADC_REG_stb_sc_vs_update 0x00210088 /* 0x088[2] Enable stable strong clamp vsync update. */ #define ADC_REG_stb_vs_sc_update 0x00420088 /* 0x088[3] Enable initial strong clamp vsync update. */ #define ADC_REG_ini_vs_sc_update 0x00630088 /* 0x088[4] Enable tip average update. */ #define ADC_REG_tip_ave_update 0x00840088 /* 0x088[5] Enable high minimun tip value update. */ #define ADC_REG_high_min_update 0x00a50088 /* 0x088[6] Enable wide tip update. */ #define ADC_REG_wide_low_update 0x00c60088 /* 0x088[7] Enable loss sync update. */ #define ADC_REG_loss_sync_update 0x00e70088 /* 0x089[0] Enable too low sync tip update. */ #define ADC_REG_synct_too_low_update 0x00000089 // 0x089[1] reserved /* 0x089[2] High minimum find option, 0: normal, 1: strong */ #define ADC_REG_high_min_strong 0x00420089 /* 0x089[3] Sync tip average find option, 0: normal, 1: strong */ #define ADC_REG_tip_ave_strong 0x00630089 /* 0x089[5:4] Sync minimum find option on cur_state=D. */ #define ADC_REG_st_stb_src 0x00a40089 /* 0x089[7:6] Sync minimum type on cur_state=D. */ #define ADC_REG_st_cpt_find_opt 0x00e60089 /* 0x08a[7:0] HD sync bottom level ratio(hsync/line ratio). */ #define ADC_REG_stbot_wdth_hd 0x00e0008a /* 0x08b[7:0] SD sync bottom level ratio(hsync/line ratio). */ #define ADC_REG_stbot_wdth_sd 0x00e0008b /* 0x08c[0] Enable sync bottom level find. */ #define ADC_REG_st_bot_find_en 0x0000008c /* 0x08c[3:1] Vsync mask width using in tip average find. */ #define ADC_REG_tip_ave_vmask_wdth 0x0061008c /* 0x08c[5:4] HD mode detect option. */ #define ADC_REG_hd_mode_det_opt 0x00a4008c // 0x08c[7:6] reserved /* 0x08d[2:0] Tip average rise mask. */ #define ADC_REG_tip_ave_rise_mask 0x0040008d /* 0x08d[3] Enable vsync mask in tip average find. */ #define ADC_REG_tip_ave_vsync_mask 0x0063008d /* 0x08d[5:4] Falling to rising(sync width) option for tip average. */ #define ADC_REG_tip_ave_f2r_opt 0x00a4008d /* 0x08d[7:6] Minimum sync width for tip average. */ #define ADC_REG_tip_ave_min_wdth 0x00e6008d /* 0x08e[1:0] Tip average offset. */ #define ADC_REG_tip_ave_offset 0x0020008e // 0x08e[3:2] reserved /* 0x08e[7:4] Stable range of sync minimum value. */ #define ADC_REG_cpt_range 0x00e4008e /* 0x08f[6:0] Sync tip comparator voltage. */ #define ADC_REG_cpt_vol 0x00c0008f /* 0x08f[7] Enable dynamic comparator voltage. */ #define ADC_REG_dyn_cpt_vol_en 0x00e7008f //auto phase /* 0x090[9:0] (0x091[1:0] ~ 0x090[7:0]) */ #define ADC_REG_aphase_es_hthold 0x01200090 // 0x091[7:2] reserved /* 0x092[9:0] (0x093[1:0] ~ 0x092[7:0]) */ #define ADC_REG_aphase_es_lthold 0x01200092 // 0x093[7:2] reserved /* 0x094[3:0] the times for edge search, max:8, 1: search one edge and return the value, 2: search edge twice and return the average, 3: search three edges and return accumulated value, 4: ?? */ #define ADC_REG_aphase_es_accnumber 0x00600094 /* 0x094[4] Start to edge-search, the rising edge of this signal is used to start edge search. */ #define ADC_REG_aphase_es_start 0x00840094 // 0x094[7:5] reserved /* 0x095[4:0] [4]: dump scheme, 0: value-based, 1: hsync-based [3:0]: latch point after hsync, counted by pixel clock */ #define ADC_REG_aphase_es_hdelay 0x00800095 // 0x095[7:5] reserved // 0x096[7:0] reserved // 0x097[7:0] reserved /* 0x098[7:0] Start point of csync-like generator. */ #define ADC_REG_csgen_start 0x00e00098 /* 0x099[0] Enable cs_gen mode by hs_valid rise, 0: csgen1 base on hs_valid_fall, 1: csgen1 base on hs_valid_rise */ #define ADC_REG_csgen_hs_vld_r 0x00000099 /* 0x099[3:1] Vsync mask end threshold count by vblank_t. */ #define ADC_REG_vsync_mask_vb_th 0x00610099 /* 0x099[7:4] Vsync mask width in cs_gen mode. */ #define ADC_REG_csgen_vblk_total 0x00e40099 /* 0x09a[3:0] Csync xor start. */ #define ADC_REG_cs_xor_start 0x0060009a /* 0x09a[7:4] Csync xor width. */ #define ADC_REG_cs_xor_wdth 0x00e4009a /* 0x09b[1:0] Option for start & width counter. */ #define ADC_REG_cs_xor_opt 0x0020009b /* 0x09b[2] */ #define ADC_REG_hs_vldf_th_en 0x0042009b /* 0x09b[3] */ #define ADC_REG_hs_vldf_th_ext 0x0063009b /* 0x09b[5:4] Threshold to enable smt by tip_height. */ #define ADC_REG_smt_auto_opt 0x00a4009b /* 0x09b[6] Vtotal counter edge select, 0: hs_valid_fall, 1: hs_valid_rise */ #define ADC_REG_vttl_edge_sel 0x00c6009b /* 0x09b[7] Manaul tip_height threshold to enable smt. */ #define ADC_REG_smt_manual_en 0x00e7009b /* 0x09c[0] Enable pre-coast mask. */ #define ADC_REG_pre_coast_mask_en 0x0000009c /* 0x09c[1] Enable post-coast mask. */ #define ADC_REG_pst_coast_msk_en 0x0021009c /* 0x09c[2] Msb vsync mask end threshold. */ #define ADC_REG_vsync_mask_endex 0x0042009c /* 0x09c[3] Vsync mask end count by 0:vtotal_cnt, 1: vblank_t. */ #define ADC_REG_vsync_mask_vb_en 0x0063009c /* 0x09c[7:4] Post-coast mask start. */ #define ADC_REG_pst_coast_msk_start 0x00e4009c /* 0x09d[7:0] Post-coast mask end. */ #define ADC_REG_pst_coast_msk_end 0x00e0009d /* 0x09e[3:0] Vsync mask start, 9*2 valid edge(line). */ #define ADC_REG_vsync_mask_start 0x0060009e /* 0x09e[7:4] Vsync mask end, f*2 valid edge(line). */ #define ADC_REG_vsync_mask_end 0x00e4009e /* 0x09f[0] */ #define ADC_REG_debug_out_b 0x0000009f /* 0x09f[1] */ #define ADC_REG_debug_out_c 0x0021009f /* 0x09f[2] */ #define ADC_REG_debug_out_i 0x0042009f /* 0x09f[3] */ #define ADC_REG_debug_out_j 0x0063009f /* 0x09f[4] */ #define ADC_REG_debug_out_k 0x0084009f /* 0x09f[5] */ #define ADC_REG_debug_out_m 0x00a5009f /* 0x09f[6] */ #define ADC_REG_debug_out_n 0x00c6009f /* 0x09f[5] */ #define ADC_REG_debug_out_o 0x00e7009f //CVBS /* 0x0a0[1:0] G channel SIF model clamp current select. */ #define ADC_REG_adjsifclr12v2 0x002000a0 /* 0x0a0[3:2] R channel SIF model clamp current select. */ #define ADC_REG_adjsifclr12v3 0x006200a0 /* 0x0a0[5:4] G channel clamp model select(See STG1 clamp table), 0: RGB mode, 1: Component mode. */ #define ADC_REG_cvbs_clamp_mode_g 0x00a400a0 // 0x0a0[7:6] reserved /* 0x0a1[1:0] Red and blue channel clamp mode select.(See STG1 clamp table). 0: RGB mode, 1: Component mode. */ #define ADC_REG_cvbs_clamp_mode_rb 0x002000a1 // 0x0a1[3:2] reserved /* 0x0a1[4] Select B channel AFE mode */ #define ADC_REG_b_scvbs12 0x008400a1 /* 0x0a1[5] */ #define ADC_REG_b_sypp12 0x00a500a1 // 0x0a1[7:6] reserved /* 0x0a2[7:0] */ #define ADC_REG_cs_clamp_width_ns 0x00e000a2 /* 0x0a3[0] Select R channel AFE mode */ #define ADC_REG_R_SYPP120 0x000000a3 /* 0x0a3[1] Select R channel AFE mode */ #define ADC_REG_R_SYPP121 0x002100a3 /* 0x0a3[2] */ #define ADC_REG_R_SCVBS12 0x004200a3 /* 0x0a3[3] Select G channel AFE mode */ #define ADC_REG_G_SYPP120 0x006300a3 /* 0x0a3[4] Select G channel AFE mode */ #define ADC_REG_G_SYPP121 0x008400a3 /* 0x0a3[5] */ #define ADC_REG_G_SCVBS12 0x00a500a3 /* 0x0a3[6] Select B channel AFE mode */ #define ADC_REG_B_SYPP120 0x00c600a3 /* 0x0a3[7] Select B channel AFE mode */ #define ADC_REG_B_SYPP121 0x00e700a3 /* 0x0a4[2:0] */ #define ADC_REG_CHR_SIFCLK_SEL 0x004000a4 // 0x0a4[3] reserved /* 0x0a4[4] SIF clock select */ #define ADC_REG_PLL12V10 0x008400a4 /* 0x0a4[5] */ #define ADC_REG_PLL12V11 0x00a500a4 /* 0x0a4[6] */ #define ADC_REG_PLL12V20 0x00c600a4 /* 0x0a4[7] */ #define ADC_REG_PLL12V21 0x00e700a4 /* 0x0a4[7:4] */ #define ADC_REG_PLL12V 0x00e400a4 /* 0x0a5[0] */ #define ADC_REG_CVBSO_PWD12 0x000000a5 /* 0x0a5[1] */ #define ADC_REG_COMPVSEL12V 0x002100a5 /* 0x0a5[2] */ #define ADC_REG_C5SWEN12V 0x004200a5 // 0x0a5[3] reserved /* 0x0a5[4] */ #define ADC_REG_ADCPLL12V30 0x008400a5 /* 0x0a5[5] */ #define ADC_REG_ADCPLL12V31 0x00a500a5 // 0x0a5[7:6] reserved /* 0x0a6[1:0] */ #define ADC_REG_pll_12v 0x002000a6 /* 0x0a6[3:2] (removed) Adjust PLL OP bias current. */ #define ADC_REG_pll_opctr 0x006200a6 /* 0x0a6[5:4] (removed) Adjust PLL bias current. */ #define ADC_REG_pll_vb2str 0x00a400a6 /* 0x0a6[7:6] Pll Gain bit. */ #define ADC_REG_pll_gb_MSBs 0x00e600a6 /* 0x0a7[1:0] PLL charge pump, set PLL band width. */ #define ADC_REG_pll_i2ctrl_MSBs 0x002000a7 /* 0x0a7[3:2] PLL charge pump, set PLL band width. */ #define ADC_REG_pll_ictrl_MSBs 0x006200a7 /* 0x0a7[5:4] External pixel clock mode, 0: ext_pxclk, 1: cvbs_clk (XTAL 24.576 MHz), 2: cvbs_49M (49.152 MHz), 3: NC */ #define ADC_REG_ext_clk_muxsel 0x00a400a7 /* 0x0a7[7:6] B channel SIF model clamp current select */ #define ADC_REG_adjsifclr12v1 0x00e600a7 /* 0x0a8[3:0] When to enable the blank-diff after the first vsync, the unit is 16 lines. */ #define ADC_REG_diff_en_start 0x006000a8 /* 0x0a8[5:4] */ #define ADC_REG_adc_mode 0x00a400a8 /* 0x0a8[6] */ #define ADC_REG_av_clamp_mode 0x00c600a8 /* 0x0a8[7] */ #define ADC_REG_clamp_mode 0x00e700a8 /* 0x0a9[2:0] */ #define ADC_REG_av_r_pg12v1 0x004000a9 // 0x0a9[3] reserved /* 0x0a9[6:4] */ #define ADC_REG_av_g_pg12v1 0x00c400a9 // 0x0a9[7] reserved /* 0x0aa[2:0] External VCMI level (10mV each step), b'000: 380mV, b'100: 400mV(default), b'111: 450mV */ #define ADC_REG_b_pg12v1 0x004000aa // 0x0aa[3] reserved /* 0x0aa[4] */ #define ADC_REG_cvclamp_en 0x008400aa /* 0x0aa[5] */ #define ADC_REG_wclamp_disable 0x00a500aa /* 0x0aa[6] Software control for the diff-enable signal. */ #define ADC_REG_diff_en_sw_ctrl 0x00c600aa /* 0x0aa[7] Software control for the the strong clamp of cvbs, 0: strong clamp after weak clamp, 1: strong clamp is unconcerned with weak clamp */ #define ADC_REG_sclamp_sw_ctrl 0x00e700aa /* 0x0ab[4:0] */ #define ADC_REG_av_r_pg12v2 0x008000ab // 0x0ab[7:5] reserved /* 0x0ac[4:0] */ #define ADC_REG_av_g_pg12v2 0x008000ac // 0x0ac[7:5] reserved /* 0x0ad[4:0] */ #define ADC_REG_av_b_pg12v2 0x008000ad // 0x0ad[5] reserved /* 0x0ad[6] */ #define ADC_REG_y_out_mode 0x00c600ad /* 0x0ad[7] */ #define ADC_REG_y_out_switch_mode 0x00e700ad /* 0x0ae[0] */ #define ADC_REG_y_sifclampen12v 0x000000ae /* 0x0ae[1] */ #define ADC_REG_r_sifclampen12v 0x002100ae /* 0x0ae[2] */ #define ADC_REG_g_sifclampen12v 0x004200ae /* 0x0ae[3] */ #define ADC_REG_b_sifclampen12v 0x006300ae /* 0x0ae[4] Negative the diff value in 2's complement. */ #define ADC_REG_diff_negative 0x008400ae /* 0x0ae[5] Polarity control for the vsync_t, 1: inversed vsync_t */ #define ADC_REG_vsyncct_pol_ctrl 0x00a500ae /* 0x0ae[6] Polarity control for the cpump_t, 1: inversed cpump_t */ #define ADC_REG_cpumpt_pol_ctrl 0x00c600ae /* 0x0ae[7] Mask the cpump_t during the vsync_t is active (low). */ #define ADC_REG_cpumpt_maskiv 0x00e700ae /* 0x0af[1:0] When to de-assert the weak clamp when the no_signal_flag = 0, 0: immediately, 1: the rising edge, 2: the falling edge, 3: the rising edge of the vsync_t */ #define ADC_REG_wclamp_ref_edge 0x002000af /* 0x0af[2] Weak clamp is the strong clamp of the g-channel when this bit is set */ #define ADC_REG_wclamp_byg 0x004200af /* 0x0af[3] Mask the rgb-clamp with no-signal_flag, 0:non-mask, 1: mask */ #define ADC_REG_scout_mask 0x006300af // 0x0af[7:4] reserved /* 0x0b0[1:0] 0: component1, 1: component2, 2: component3 */ #define ADC_REG_sog_clamp_sel 0x002000b0 /* 0x0b0[2] External weak clamp. */ #define ADC_REG_extn_wc 0x004200b0 /* 0x0b0[3] External strong clamp. */ #define ADC_REG_extn_sc 0x006300b0 /* 0x0b0[6:4] Weak clamp turn on width on cur_state=1. */ #define ADC_REG_wclamp_lcnt 0x00c400b0 // 0x0b0[7] reserved /* 0x0b1[3:0] Strong clamp mask end. */ #define ADC_REG_sclamp_mask_end 0x006000b1 /* 0x0b1[6:4] Strong clamp mask start. */ #define ADC_REG_sclamp_mask_start 0x00c400b1 /* 0x0b1[7] Enable strong clamp mask. */ #define ADC_REG_sclamp_mask_en 0x00e700b1 /* 0x0b2[3:0] Sum threshold of conditional strong clamp on cur_state=1. */ #define ADC_REG_cond_sc_sum_th 0x006000b2 /* 0x0b2[7:4] Filter threshold of conditional strong clamp on cur_state=1. */ #define ADC_REG_cond_sc_filt_th 0x00e400b2 /* 0x0b3[3:0] Initial strong clamp start on cur_state=9. */ #define ADC_REG_ini_sc_start 0x006000b3 /* 0x0b3[7:4] Initial strong clamp width on cur_state=9. */ #define ADC_REG_ini_sc_wdth 0x00e400b3 /* 0x0b4[5:0] Initial strong clamp latency on cur_state=9. */ #define ADC_REG_ini_sc_latency 0x00a000b4 /* 0x0b4[7:6] Round count limimt of initial strong clamp, 0: f, 1: 1f, 2: 3f, 3: 7f */ #define ADC_REG_ini_sc_rlimit 0x00e600b4 /* 0x0b5[0] Enable vsync strong clamp. */ #define ADC_REG_vs_sclamp_en 0x000000b5 /* 0x0b5[1] Enable vsync strong clamp on cur_state=D. */ #define ADC_REG_stb_vs_sclamp_en 0x002100b5 /* 0x0b5[2] Enable csync check of strong clamp. */ #define ADC_REG_sc_smt_chk 0x004200b5 /* 0x0b5[3] Enable synct check of strong clamp. */ #define ADC_REG_sc_synct_chk 0x006300b5 /* 0x0b5[4] Skip vsync strong clamp or not, 0: always clamp, 1: skip V. */ #define ADC_REG_sc_vsync_skip 0x008400b5 /* 0x0b5[5] */ #define ADC_REG_vssc_smt_chk 0x00a500b5 /* 0x0b5[7:6] Stable strong clamp width option. */ #define ADC_REG_stb1_sc_wdth_opt 0x00e600b5 /* 0x0b6[3:0] Vsync strong clamp start on cur_state=D. */ #define ADC_REG_vs_sc_start 0x006000b6 /* 0x0b6[7:4] Vsync strong clamp width on cur_state=D. */ #define ADC_REG_vs_sc_wdth 0x00e400b6 /* 0x0b7[3:0] Strong clamp1 start on cur_state=D. */ #define ADC_REG_sc1_start 0x006000b7 /* 0x0b7[7:4] Strong clamp1 width on cur_state=D. */ #define ADC_REG_sc1_wdth 0x00e400b7 /* 0x0b8[3:0] Strong clamp2 start on cur_state=D. */ #define ADC_REG_sc2_start 0x006000b8 /* 0x0b8[7:4] Strong clamp2 width on cur_state=D. */ #define ADC_REG_sc2_wdth 0x00e400b8 /* 0x0b9[1:0] Strong clamp throttling option, 0: contiguous 1T, 1: contiguous 2T, 2: contiguous 4T, 3: contiguous 4T */ #define ADC_REG_sc_throt_opt 0x002000b9 /* 0x0b9[2] Stable strong clamp select, 0: en_stb1_sclamp | en_stb2_sclamp, 1: en_stb1_sclamp */ #define ADC_REG_sc1_sc2_sel 0x004200b9 // 0x0b9[3] reserved /* 0x0b9[6:4] Vsync initial strong clamp throttling option. */ #define ADC_REG_sc_ini_vs_sth 0x00c400b9 // 0x0b9[7] reserved /* 0x0ba[2:0] Vsync stable strong clamp throttling option. */ #define ADC_REG_sc_stb_vs_sth 0x004000ba // 0x0ba[3] reserved /* 0x0ba[6:4] Stable strong clamp throttling option. */ #define ADC_REG_sc_stb_sth 0x00c400ba // 0x0ba[7] reserved /* 0x0bb[3:0] FIR1 filter low boundary for stable strong clamp. */ #define ADC_REG_sc_lowbound 0x006000bb /* 0x0bb[7:4] FIR1 filter high boundary for stable strong clamp. */ #define ADC_REG_sc_highbound 0x00e400bb /* 0x0bc[3:0] i2p-mode rising edge detect low threshold. */ #define ADC_REG_i2p_rise_lth 0x006000bc /* 0x0bc[7:4] i2p-mode rising edge detect high threshold. */ #define ADC_REG_i2p_rise_hth 0x00e400bc /* 0x0bd[3:0] i2p-mode line width detect low threshold. */ #define ADC_REG_i2p_wdth_lth 0x006000bd /* 0x0bd[7:4] i2p-mode line width detect high threshold. */ #define ADC_REG_i2p_wdth_hth 0x00e400bd /* 0x0be[3:0] i2p-mode line detect threshold. */ #define ADC_REG_i2p_wdth_det_th 0x006000be /* 0xbe[4] i2p-mode detect option, 0: rising, 1: width. */ #define ADC_REG_i2p_opt 0x008400be /* 0xbe[5] Round count extend of initila strong clamp. */ #define ADC_REG_ini_sc_extend 0x00a500be /* 0xbe[6] cs_gen shape select in vsync, 0: smt, 1: synct. */ #define ADC_REG_csgen_vw_opt 0x00c600be // 0x0be[7] reserved /* 0x0bf[1:0] */ #define ADC_REG_sc_vblankt1 0x002000bf /* 0x0bf[3:2] Vsync strong clamp blank number. */ #define ADC_REG_sc_vblankt2 0x006200bf /* 0x0bf[7:4] Stable vsync strong clamp blank number. */ #define ADC_REG_vblank_stb_length 0x00e400bf //coast-gen with 4e[3:2] = 0(default) /* 0x0c0[15:0] (0x0c1[7:0] ~ 0x0c0[7:0]) */ #define ADC_STA_shp_width 0x01e000c0 /* 0x0c2[0] */ #define ADC_STA_field_i 0x000000c2 /* 0x0c2[1] */ #define ADC_STA_cstable_i2 0x002100c2 /* 0x0c2[2] */ #define ADC_STA_cstable_i 0x004200c2 /* 0x0c2[3] */ #define ADC_STA_cs_active 0x006300c2 /* 0x0c2[4] */ #define ADC_STA_cs_fall 0x008400c2 /* 0x0c2[5] */ #define ADC_STA_cs_rise 0x00a500c2 /* 0x0c2[6] */ #define ADC_STA_csync_en 0x00c600c2 /* 0x0c2[7] */ #define ADC_STA_timeout 0x00e700c2 /* 0x0c3[7:0] */ #define ADC_STA_tou_vcnt 0x00e000c3 /* 0x0c4[15:0] (0x0c5[7:0] ~ 0x0c4[7:0]) */ #define ADC_STA_lvcnt 0x01e000c4 /* 0x0c6[15:0] (0x0c7[7:0] ~ 0x0c6[7:0]) */ #define ADC_STA_htotal 0x01e000c6 /* 0x0c8[15:0] (0x0c9[7:0] ~ 0x0c8[7:0]) */ #define ADC_STA_latched_stable_vtotal 0x01e000c8 /* 0x0ca[15:0] (0x0cb[7:0] ~ 0x0ca[7:0]) */ #define ADC_STA_latched_stable_htotal 0x01e000ca /* 0x0cc[0] */ #define ADC_STA_rstable_nom 0x000000cc /* 0x0cc[1] */ #define ADC_STA_fstable_nom 0x002100cc /* 0x0cc[2] */ #define ADC_STA_both_stable 0x004200cc /* 0x0cc[63:8] ( 0xcf[7:0] ~ 0xce[7:0] ~ 0xcd[7:0] ) */ #define ADC_STA_svp_width 0x03e800cc //coast-gen with 4e[3:2] = 2 /* 0x0c0[15:0] (0x0c1[7:0] ~ 0x0c0[7:0]) */ #define ADC_STA_oe_period_current 0x01e000c0 /* 0x0c2[15:0] (0x0c3[7:0] ~ 0x0c2[7:0]) */ #define ADC_STA_sp_conf 0x01e000c2 /* 0x0c4[15:0] (0x0c5[7:0] ~ 0x0c4[7:0]) */ #define ADC_STA_stable_period 0x01e000c4 /* 0x0c6[15:0] (0x0c7[7:0] ~ 0x0c6[7:0]) */ #define ADC_STA_hp_counter 0x01e000c6 /* 0x0c8[15:0] (0x0c9[7:0] ~ 0x0c8[7:0]) */ #define ADC_STA_hw_counter 0x01e000c8 /* 0x0ca[15:0] (0x0cb[7:0] ~ 0x0ca[7:0]) */ #define ADC_STA_vs_counter 0x01e000ca /* 0x0cc[15:0] (0x0cd[7:0] ~ 0x0cc[7:0]) */ #define ADC_STA_vs_redge_thold 0x01e000cc //coast-gen with 4e[3:2] = 3 /* 0x0c0[15:0] (0x0c1[7:0] ~ 0x0c0[7:0]) */ #define ADC_STA_counta_576i 0x01e000c0 /* 0x0c2[15:0] (0x0c3[7:0] ~ 0x0c2[7:0]) */ #define ADC_STA_counta_480i 0x01e000c2 /* 0x0c4[15:0] (0x0c5[7:0] ~ 0x0c4[7:0]) */ #define ADC_STA_counta_1080i 0x01e000c4 /* 0x0c6[15:0] (0x0c7[7:0] ~ 0x0c6[7:0]) */ #define ADC_STA_vs_lcounter_a 0x01e000c6 //SOG slicer /* 0x0d0[7:0] Current SoG state 1: clamp signal to working zone(700mV~1650mV) 2: check device signal swing, [swing<75mV] => state 3 [swing>75mV] => state 4 3: redetect clamp after short period of time, the waiting time is controled by reg_sog_loss_sync_opt(0x83[1:0]) 4: stmin_find 5: stbot_find 6: waiting for Vsync, this will check SoG low count 7: Vsync is found, and Vsync strong clamp will pull the lowest signal voltage to 1.066V 8: find a Hsync rising edge for confirming the correctness of clamping result 9: clamp the bottom of Hsync to improve the signal stability, the target is 1.066V+50mV a: stmin_refind b: stbot_refind c: check the lowest level of Hsync [lowest = 1.066V+50mV] => state d [lowest ??1.066V+50mV] => state 8 d: signal stable e: ? f: signal unstable, its judging rule are - there are no Hsync for 40??in state 6 c d - repeat state 8 9 a b c loop for 32 times*/ #define ADC_STA_cur_state 0x00e000d0 /* 0x0d1[4:0] */ #define ADC_STA_int_sc_rcnt 0x008000d1 // 0x0d1[7:5] reserved // 0x0d2[7:0] reserved // 0x0d3[7:0] reserved /* 0x0d4[9:0] (0x0d5[1:0] ~ 0x0d4[7:0]) */ #define ADC_STA_mlow_wdth 0x012000d4 /* 0x0d4[19:10] (0x0d6[3:0] ~ 0x0d5[7:2]) */ #define ADC_STA_low_wdth 0x016200d5 // 0x0d6[7:4] reserved /* 0x0d7[7:0] */ #define ADC_STA_sine_moise_acc_cnt 0x00e000d7 /* 0x0d8[7:0] */ #define ADC_STA_sta_hs_slew 0x00e000d8 /* 0x0d9[7:0] */ #define ADC_STA_min_find 0x00e000d9 /* 0x0da[7:0] */ #define ADC_STA_mid_find 0x00e000da /* 0x0db[7:0] */ #define ADC_STA_max_find 0x00e000db /* 0x0dc[12:0] (0x0dd[4:0] ~ 0x0dc[7:0]) */ #define ADC_STA_mline_wdth 0x01a000dc // 0x0dd[7:5] reserved /* 0x0dc[28:16] (0x0df[4:0] ~ 0x0de[7:0]) */ #define ADC_STA_line_wdth 0x01a000de // 0x0df[7:5] reserved //auto phase /* 0x0e0[15:0] */ #define ADC_STA_pd1_dout 0x01e000e0 /* 0x0e2[15:0] */ #define ADC_STA_pd2_dout 0x01e000e2 /* 0x0e4[15:0] */ #define ADC_STA_pd3_dout 0x01e000e4 /* 0x0e6[15:0] */ #define ADC_STA_pd4_dout 0x01e000e6 /* 0x0e8[15:0] */ #define ADC_STA_pd5_dout 0x01e000e8 /* 0x0ea[15:0] */ #define ADC_STA_pd6_dout 0x01e000ea /* 0x0ec[15:0] */ #define ADC_STA_pd7_dout 0x01e000ec /* 0x0ee[7:0] */ #define ADC_STA_d2h_counter 0x00e000ee /* 0x0ef[0] */ #define ADC_STA_esearch_done 0x000000ef // 0x0ef[7:1] reserved //-------Read only------- //interrupt /* 0x0f0[3:0] Sync lost interrupt [0]: Input signal swing is smaller than 75mV, indicating no signal. [1]: Input signal swing is more than 75mV, indicating signal in. [2]: There is no hsync edge detected in 80ms period, and SOG state is 0xf6,0xf8 or 0xfd [3]: There is no hsync edge detected in 40ms period, or the DC level of Hsync decreasing 30mV */ #define ADC_STA_loss_sync 0x006000f0 /* 0x0f0[4] Inverse of STA_ext_hsync_active (for VGA). */ #define ADC_STA_ext_hsync_non_active 0x008400f0 /* 0x0f0[5] Continuous 3 external hsync rising edges are detected (for VGA). */ #define ADC_STA_ext_hsync_active 0x00a500f0 /* 0x0f0[6] Time out interrupt for clamp processing(clamp failed due to hsync lost). The timeout threshold reference to reg_clamp_int_tout_thold(0x47[7:0]). */ #define ADC_STA_clamp_int 0x00c600f0 /* 0x0f0[7] Detect whether Hsync for VIP is stable or not. The judging rule is continuous 4 hsync edges(0x04[7:5]) are bigger than the reference threshold (0x04[4:0]). */ #define ADC_STA_us_hsout 0x00e700f0 /* 0x0f1[0] Inverse of STA_fast_coast. */ #define ADC_STA_unstable_coast 0x000000f1 /* 0x0f1[1] Continuous 3 hsync rising edges are detected after SoG stable. */ #define ADC_STA_fast_coast 0x002100f1 /* 0x0f1[2] Interrupt for I-mode to P-mode tansfering. */ #define ADC_STA_coast_ntimer 0x004200f1 /* 0x0f1[3] */ #define ADC_STA_coast_etimer 0x006300f1 /* 0x0f1[4] There is no hsync detected in the time period of (0x0d[7:6]). */ #define ADC_STA_cs_stable_i2_fedge 0x008400f1 /* 0x0f1[5] Check whether current Vtotal is equal to the previous Vtotal. */ #define ADC_STA_cs_stable_i2_redge 0x00a500f1 /* 0x0f1[6] smt out miss. This interrupt is enabled by reg_cs2_rst_sog_maxhp_en(0x19[7]) and its threshold is reg_cs2_rst_sog_maxhp(0x19[6:0]~0x18[7:0]). */ #define ADC_STA_hsync_miss 0x00c600f1 /* 0x0f1[7] coast period is unstable (rising edge for coast period < 11.5μs) */ #define ADC_STA_clear_pll_rst_rbit 0x00e700f1 /* 0x0f0[15:0] (0x0f1[7:0] ~ 0x0f0[7:0]) */ #define ADC_STA_interrupt 0x01e000f0 //interrupt status /* 0x0f2[11:0] (0x0f3[3:0] ~ 0x0f2[7:0]) */ #define ADC_STA_prev_coast_period 0x018000f2 /* 0x0f4[11:0] (0x0f5[3:0] ~ 0x0f4[7:0]) */ #define ADC_STA_coast_period_counter 0x018000f4 // 0x0f5[7:4] reserved /* 0x0f6[7:0] */ #define ADC_STA_normal_timer 0x00e000f6 /* 0x0f7[2:0] */ #define ADC_STA_urc_counter 0x004000f7 // 0x0f7[3] reserved /* 0x0f7[6:4] */ #define ADC_STA_cs_pls_counter 0x00c400f7 /* 0x0f7[7] */ #define ADC_STA_cs_stable_i2 0x00e700f7 /* 0x0f8[7:0] */ #define ADC_STA_edge_timer 0x00e000f8 // 0x0f9[7:0] reserved //active /* 0x0fa[0] */ #define ADC_STA_clamp_active 0x000000fa /* 0x0fa[1] */ #define ADC_STA_clamp_interrupt 0x002100fa // 0x0fa[7:2] reserved // 0x0fb[7:0] reserved /* 0x0fc[0] */ #define ADC_STA_csync_plrty 0x000000fc /* 0x0fc[1] */ #define ADC_STA_csync_active 0x002100fc /* 0x0fc[2] */ #define ADC_STA_csync_flag_fcsdtor 0x004200fc // 0x0fc[3] reserved /* 0x0fc[4] */ #define ADC_STA_hs_plrty 0x008400fc /* 0x0fc[5] */ #define ADC_STA_hs_active 0x00a500fc /* 0x0fc[6] */ #define ADC_STA_csync_in_hsync_flag 0x00c600fc // 0x0fc[7] reserved /* 0x0fd[0] */ #define ADC_STA_vs_plrty 0x000000fd /* 0x0fd[1] */ #define ADC_STA_vs_active 0x002100fd // 0x0fd[7:2] reserved /* 0x0fe[7:0] */ #define ADC_STA_ctp_compout 0x00e000fe /* 0x0fe[3:0] */ #define ADC_STA_ctp_range 0x006000fe // 0x0fe[7:4] reserved // 0x0ff[7:0] reserved //10x for 9561 /* 0x100[7:0] Deglitch High to Low threshold. */ #define ADC_REG_hvdg_h2l_thold 0x00e00100 /* 0x101[7:0] Deglitch Low to High threshold. */ #define ADC_REG_hvdg_l2h_thold 0x00e00101 /* 0x102[7:0] */ #define ADC_REG_hvcs_httl_sch_range 0x00e00102 /* 0x103[0] Adi polarity. */ #define ADC_REG_hvadi_pol_cs 0x00000103 /* 0x103[2:1] */ #define ADC_REG_hvdg_source_sel 0x00410103 // 0x103[7:3] reserved /* 0x104[7:0] R channel clamp power down start. */ #define ADC_REG_r_clamppdn_st 0x00e00104 /* 0x105[7:0] R channel clamp power down end. */ #define ADC_REG_r_clamppdn_end 0x00e00105 /* 0x106[7:0] G channel clamp power down start. */ #define ADC_REG_g_clamppdn_st 0x00e00106 /* 0x107[7:0] G channel clamp power down end. */ #define ADC_REG_g_clamppdn_end 0x00e00107 /* 0x108[7:0] B channel clamp power down start. */ #define ADC_REG_b_clamppdn_st 0x00e00108 /* 0x109[7:0] B channel clamp power down end. */ #define ADC_REG_b_clamppdn_end 0x00e00109 /* 0x10a[1:0] 10: output 0, 11: output 1, 0x: output R clamp power down. */ #define ADC_REG_r_clamppdn_mod 0x0020010a /* 0x10a[3:2] 10: output 0, 11: output 1, 0x: output G clamp power down. */ #define ADC_REG_g_clamppdn_mod 0x0062010a /* 0x10a[5:4] 10: output 0, 11: output 1, 0x: output B clamp power down. */ #define ADC_REG_b_clamppdn_mod 0x00a4010a /* 0x10a[6] Rising edge or falling edge. */ #define ADC_REG_clamppdn_edge 0x00c6010a /* 0x10a[7] RGB clamp power down enable. */ #define ADC_REG_clamppdn_en 0x00e7010a /* 0x10b[0] R clamp power down polarity. */ #define ADC_REG_r_clamppdn_pol 0x0000010b /* 0x10b[1] G clamp power down polarity. */ #define ADC_REG_g_clamppdn_pol 0x0021010b /* 0x10b[2] B clamp power down polarity. */ #define ADC_REG_b_clamppdn_pol 0x0042010b // 0x10b[7:3] reserved /* 0x10c[7:0] Y channel clamp power down start. */ #define ADC_REG_y_clamppdn_st 0x00e0010c /* 0x10d[7:0] Y channel clamp power down end. */ #define ADC_REG_y_clamppdn_end 0x00e0010d /* 0x10e[1:0] 10: output 0, 11: output 1, 0x: output Y clamp power down. */ #define ADC_REG_y_clamppdn_mod 0x0020010e /* 0x10e[2] Y clamp power down polarity. */ #define ADC_REG_y_clamppdn_pol 0x0042010e /* 0x10e[3] nsignal polarity. */ #define ADC_REG_nsignal_pol 0x0063010e /* 0x10e[4] Y clamp power down enable. */ #define ADC_REG_yclamppdn_en 0x0084010e // 0x10e[7:5] reserved /* 0x10f[7:0] */ #define ADC_REG_vsynth 0x00e0010f // 0x110 ~ 0x11f reserved //12x for 9561 /* 0x120[1:0] */ #define ADC_REG_adjdmclr12v1 0x00200120 /* 0x120[3:2] Y channel SIF model clamp current select. */ #define ADC_REG_adjsifclr12v4 0x00620120 /* 0x120[4] */ #define ADC_REG_dmclampen12v 0x00840120 /* 0x120[5] */ #define ADC_REG_e15dby 0x00a50120 /* 0x120[7:6] */ #define ADC_REG_clamp_mode_y 0x00e60120 /* 0x121[0] */ #define ADC_REG_pwdny 0x00000121 /* 0x121[3:1] */ #define ADC_REG_y_12vcm_sel 0x00610121 /* 0x121[6:4] */ #define ADC_REG_y_33vcm_sel 0x00c40121 /* 0x121[7] */ #define ADC_REG_refinsel12v 0x00e70121 /* 0x122[2:0] */ #define ADC_REG_y_chsel 0x00400122 /* 0x122[3] */ #define ADC_REG_y_ffadj12v 0x00630122 /* 0x122[4] */ #define ADC_REG_y_lgadj12v 0x00840122 /* 0x122[5] */ #define ADC_REG_y_mn10y 0x00a50122 /* 0x122[9:6] (0x123[1:0] ~ 0x122[7:6])*/ #define ADC_REG_y_mn1 0x01260122 /* 0x123[7:2] */ #define ADC_REG_y_mn2 0x00e20123 /* 0x124[3:0] */ #define ADC_REG_y_mp1 0x00600124 /* 0x124[4] */ #define ADC_REG_y_mp10y 0x00840124 /* 0x124[5] */ #define ADC_REG_av_y_pgmsb 0x00c50124 // 0x124[7:6] reserved /* 0x125[3:0] */ #define ADC_REG_y_pga12v1 0x00600125 /* 0x125[7:4] */ #define ADC_REG_y_pga12v2_bit0to3 0x00e40125 /* 0x126[0] */ #define ADC_REG_y_pga12v2_bit4 0x00000126 /* 0x126[1] */ #define ADC_REG_y_pden12v 0x00210126 /* 0x126[3:2] */ #define ADC_REG_y_refch12v 0x00620126 /* 0x126[4] */ #define ADC_REG_y_tswmiden12v 0x00840126 /* 0x126[5] */ #define ADC_REG_y_refclampsel12v 0x00a50126 /* 0x126[6] */ #define ADC_REG_y_intrefen12v 0x00c60126 // 0x126[7] reserved /* 0x127[1:0] */ #define ADC_REG_y_pga12v3 0x00200127 // 0x127[3:2] reserved /* 0x127[7:4] */ #define ADC_REG_y_sb2 0x00e40127 /* 0x128[4:0] */ #define ADC_REG_y_sb1 0x00800128 /* 0x128[6:5] */ #define ADC_REG_y_sypp12 0x00c50128 /* 0x128[7] */ #define ADC_REG_y_clamp_en 0x00e70128 /* 0x129[1:0] */ #define ADC_REG_y_scvbs12 0x00200129 // 0x129[3:2] reserved /* 0x129[5:4] */ #define ADC_REG_lpfmod12v 0x00a40129 /* 0x129[6] */ #define ADC_REG_vbgren 0x00c60129 /* 0x129[7] */ #define ADC_REG_sog_ch1_sel 0x00e70129 //coast200 for debounce // 0x12a[2:0] reserved /* 0x12a[3] */ #define ADC_REG_refclk_db_sel 0x0063012a // 0x12a[7:4] reserved /* 0x12b[0] */ #define ADC_REG_refclk_cs_sel 0x0000012b // 0x12b[7:1] reserved /* 0x12c[5:0] */ #define ADC_REG_diffin_max 0x00a0012c /* 0x12c[7:6] */ #define ADC_REG_diffmod 0x00e6012c /* 0x12d[5:0] */ #define ADC_REG_diffinc_max 0x00a0012d /* 0x12d[6] */ #define ADC_REG_rwclampeco 0x00c6012d /* 0x12d[7] */ #define ADC_REG_sog_gaincomp_en 0x00e7012d /* 0x12e[0] */ #define ADC_REG_sog_smtl_dbsen 0x0000012e /* 0x12e[1] */ #define ADC_REG_gainop 0x0021012e // 0x12e[3:2] reserved /* 0x12e[7:4] {R_SMTH_CAP_H, R_SMTH_CAP_L, R_SMTL_CAP_H, R_SMTL_CAP_L} */ #define ADC_REG_smt_cap // 0c12f[7:0] reserved /* 0x130[0] Auto offset function enable; 0: disable, 1: enable*/ #define ADC_REG_auto_ofsen 0x00000130 // 0x130[1] reserved /* 0x130[3:2] Debug select. */ #define ADC_REG_aofs_dbg_sel 0x00620130 /* 0x130[4] Auto offset function enable. */ #define ADC_REG_auto_ofs0op 0x00840130 // 0x130[7:5] reserved /* 0x130[6] Hsync polarity adjustment. */ #define ADC_REG_aof_hpol 0x00c60130 /* 0x130[7] Vsync polarity adjustment. */ #define ADC_REG_aof_vpol 0x00e70130 /* 0x131[7:0] To get RGB value in blank region from the programmed line count. */ #define ADC_REG_aof_lstart 0x00e00131 /* 0x132[7:0] To get RGB value in blank region from the programmed pixel count. */ #define ADC_REG_aof_pstart 0x00e00132 /* 0x133[3:0] Number of pixel to get average value of RGB in blank region. */ #define ADC_REG_aof_pwidth 0x00600133 /* 0x133[7:4] Number of lines to get average value of RGB in blank region. */ #define ADC_REG_aof_lwidth 0x00e40133 /* 0x135[1:0] ~ 0x134[7:0] R channel target value in blank region. */ #define ADC_REG_r_target 0x01200134 // 0x135[7:2] reserved /* 0x137[1:0] ~ 0x136[7:0] G channel target value in blank region. */ #define ADC_REG_reg_g_target 0x01200136 // 0x137[7:2] reserved /* 0x139[1:0] ~ 0x138[7:0] G channel target value in blank region. */ #define ADC_REG_reg_b_target 0x01200138 // 0x139[7:2] reserved /* 0x13a[1:0] Alpha parameter (1/8, 1/16, 1/32, and 1/64). */ #define ADC_REG_power 0x0020013a // 0x13a[2] reserved /* 0x13a[3] Auto offset software reset. */ #define ADC_REG_sw_rst 0x0063013a // 0x13a[7:4] reserved // 0x13b ~ 0x13f reserved //PLL Reg 14x /* 0x140[7:0] Decide by fraction part of divider. */ #define ADC_REG_datain_ini_7to0 0x00e00140 /* 0x141[7:0] Decide by fraction part of divider. */ #define ADC_REG_datain_ini_15to8 0x00e00141 /* 0x142[0] Decide by fraction part of divider. */ #define ADC_REG_datain_ini_16 0x00000142 /* 0x142[1] PLL reference for AV source. */ #define ADC_REG_dco_bx2 0x00210142 /* 0x142[2] Enable clock for dram, 0: off, 1: on */ #define ADC_REG_dco_en_fdiv 0x00420142 // 0x142[3] reserved /* 0x142[7:4] Selection of debug information. */ #define ADC_REG_dbgsela 0x00e40142 /* 0x143[7:0] DCO divider for feedback clock(N+1), its value is calcultaed according to formula, febdiv = (VCO / [system CLK] ) - 1 */ #define ADC_REG_dco_febdiv 0x00e00143 /* 0x144[5:0] DCO gain bit, its value might adopt different settings according to VCO range, where the VCO is computation result of the formula below, VCO = [pixel clock] x [multiply value of 3 stages pxDiv(0x146)] [5]: removed, [4]: EN_CAP, [3:0]: Gain bit */ #define ADC_REG_dco_gb 0x00a00144 /* 0x144[6] Reset of DCO divider 0: reset , 1: normal. */ #define ADC_REG_dco_pdiv_rstj 0x00c60144 /* 0x144[7] Reference signal for DCO 0: off, 1: on */ #define ADC_REG_dco_refin 0x00e70144 /* 0x145[7:0] Current of pump, its value might adopt different settings according to VCO range, where the VCO is computation result of the formula VCO = [pixel clock] x [multipy value of 3 stages pxDiv] [3:0] 0: min, f: max, [7:4] removed from 40nm */ #define ADC_REG_dco_ictrl 0x00e00145 /* 0x146[7:0] Dual loop divider for pixel clock(N+1), there are 3 stage dividers, - 1st divider is setup in pll_div_sel(0x39[1:0]), - 2nd divider is setup in pll_divb_sel(0x39[3:2]), - 3rd divider is constant value 4, and the formula of dlpll_pxdiv is dlpll_pxdiv = ([1st div] x [2nd div] x [3rd div]) -1 */ #define ADC_REG_dlpll_pxdiv 0x00e00146 /* 0x147[4:0] DCO divider for reference clock. [0]: N+1, [4:1]: removed. */ #define ADC_REG_dco_refdiv 0x00800147 /* 0x147[5] Reset for dual loop divider. 0: reset, 1: normal */ #define ADC_REG_dlpll_pdiv_rstj 0x00a50147 /* 0x147[7:6] Dual loop line divider MSB 2bits. */ #define ADC_REG_r_pll_opi 0x00e60147 /* 0x148[7:0] Dual loop line divider LSB [7:0] of 12bits12bits, the value is equal to (Htotal -1), where Htotal value comes from h_total of timing table and multiply its sampling enlarge rate. */ #define ADC_REG_pll_febdiv_7to0 0x00e00148 /* 0x149[3:0] Dual loop line divider LSB [11:8] of 12bits12bits, the value is equal to (Htotal -1), where Htotal value comes from h_total of timing table and multiply its sampling enlarge rate. */ #define ADC_REG_pll_febdiv_11to8 0x00600149 //digital offset enable /* 0x149[6] */ #define ADC_REG_beofst_en0 0x00c60149 /* 0x149[7] */ #define ADC_REG_beofst_en1 0x00e70149 /* 0x14a[0] LDO's power down2. */ #define ADC_REG_ldo_pwd 0x0000014a /* 0x14a[1] LDO's power down1 lead over power down2. */ #define ADC_REG_ldo_pwde 0x0021014a /* 0x14a[2] Reset for sigma delta modulator(SDM). */ #define ADC_REG_sdmresetj 0x0042014a /* 0x14a[3] Achitecture selection for SDM */ #define ADC_REG_sdm_type_sel 0x0063014a /* 0x14a[6:4] Selection for bandgap voltage(131 removed) */ #define ADC_REG_vbg_sel 0x00c4014a /* 0x14a[7] Sign of datain ini. */ #define ADC_REG_sign_datain_ini 0x00e7014a //digital offset value /* 0x14b[7:0] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_r_7to0 0x00e0014b /* 0x14c[1:0] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_r 0x0020014c /* 0x14c[7:2] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_g_5to0 0x00e2014c /* 0x14d[1:0] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_g_7to6 0x0020014d /* 0x14d[3:2] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_g 0x0062014d /* 0x14d[7:4] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_b_3to0 0x00e4014d /* 0x14e[3:0] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_b_7to4 0x0060014e /* 0x14e[5:4] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REG_dofst_b 0x00c4014e /* 0x14e[7:6] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REGdofst_y_1to0 0x00e6014e /* 0x14f[5:0] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REGdofst_y_7to2 0x00c0014f /* 0x14f[7:6] Only uses 9 bits, MSB for sign bit: 0 means "-" and 1 means "+", other bits mean offset values. */ #define ADC_REGdofst_y 0x00e6014f //PLL Reg 15x /* 0x150[7:0] Fraction part of iir_fbpn1's multiplier. */ #define ADC_REG_iir_fbpn1_f 0x00e00150 /* 0x151[7:0] Integer part of iir_fbpn1's multiplier. */ #define ADC_REG_iir_fbpn1_i_7to0 0x00e00151 /* 0x152[0] Integer part of iir_fbpn1's multiplier. */ #define ADC_REG_iir_fbpn1_i_8 0x00000152 // 0x152[3:1] reserved /* 0x152[7:4] */ #define ADC_REG_dlpll_dbgselb 0x00e40152 /* 0x153[7:0] Fraction part of iir_fbppn1's multiplier. */ #define ADC_REG_iir_fbppn1_f 0x00e00153 /* 0x154[7:0] Integer part of iir_fbppn1's multiplier. */ #define ADC_REG_iir_fbppn1_i_7to0 0x00e00154 /* 0x155[0] Integer part of iir_fbppn1's multiplier. */ #define ADC_REG_iir_fbppn1_i_8 0x00000155 // 0x155[7:1] reserved /* 0x156[7:0] Fraction part of iir_fwn1's multiplier. */ #define ADC_REG_iir_fwn1_f 0x00e00156 /* 0x157[7:0] Integer part of iir_fwn1's multiplier. */ #define ADC_REG_iir_fwn1_i_7to0 0x00e00157 /* 0x158[0] Integer part of iir_fwn1's multiplier. */ #define ADC_REG_iir_fwn1_i_8 0x00000158 // 0x158[7:1] reserved /* 0x159[7:0] Fraction part of iir_fwpn1's multiplier. */ #define ADC_REG_iir_fwpn1_f 0x00e00159 /* 0x15a[7:0] Integer part of iir_fwpn1's multiplier. */ #define ADC_REG_iir_fwpn1_i_7to0 0x00e0015a /* 0x15b[0] Integer part of iir_fwpn1's multiplier. */ #define ADC_REG_iir_fwpn1_i_8 0x0000015b // 0x15b[7:1] reserved /* 0x15c[7:0] Fraction part of iir_fwppn1's multiplier. */ #define ADC_REG_iir_fwppn1_f 0x00e0015c /* 0x15d[7:0] Integer part of iir_fwppn1's multiplier. */ #define ADC_REG_iir_fwppn1_i_7to0 0x00e0015d /* 0x15e[7:0] Integer part of iir_fwppn1's multiplier. */ #define ADC_REG_iir_fwppn1_i_8 0x00e0015e /* 0x15f[1:0] IIR_DFF clock selection 00: sdmsyn, 01: sdmsyn/2, 10: sdmsyn/4, 11: sdmsyn/8 */ #define ADC_REG_iirclk_div_sel 0x0020015f // 0x15f[7:2] reserved //digital gain enable 16x /* 0x161[1:0] ~ 0x160[7:0] ref_stg1 R-channel differential reference positive-negative level option, b'0000: 540mV, b'0010: 500mV(default) , ... (-20mV for each step on high 4 bits) b'1111: 240mV */ #define ADC_REG_dgain_r 0x01200160 /* 0x162[3:0] ~ 0x161[7:2] ref_stg1 G-channel differential reference positive-negative level option, b'0000: 540mV, b'0010: 500mV(default) , ... (-20mV for each step on high 4 bits) b'1111: 240mV */ #define ADC_REG_dgain_g 0x02220161 /* 0x163[5:0] ~ 0x162[7:4] ref_stg1 B-channel differential reference positive-negative level option, b'0000: 540mV, b'0010: 500mV(default) , ... (-20mV for each step on high 4 bits) b'1111: 240mV */ #define ADC_REG_dgain_b 0x01a40162 // 0c163[7:6] reserved /* 0x165[1:0] ~ 0x164[7:0] */ #define ADC_REG_dgain_y 0x01200164 /* 0x166[0] */ #define ADC_REG_begain_en0 0x00000166 /* 0x166[1] */ #define ADC_REG_begain_en1 0x00210166 /* 0x166[2] */ #define ADC_REG_dgain_op0 0x00420166 /* 0x166[3] */ #define ADC_REG_dgain_op1 0x00630166 /* 0x166[4] */ #define ADC_REG_dgain_dbgsel 0x00840166 /* 0x166[5] */ #define ADC_REG_gcvbsen 0x00a50166 /* 0x166[6] */ #define ADC_REG_yclk_gcvbsen 0x00c60166 /* 0x166[7] */ #define ADC_REG_invyclk_gcvbsen 0x00e70166 //for 330CA /* 0x167[1:0] 2'b00 sel vga; 2'b01 sel ypp1; 2'b10 sel ypp2_ref; 2'b11 sel av_ref */ #define ADC_REG_r_refch12v 0x00200167 /* 0x167[3:2] 2'b00 sel vga; 2'b01 sel ypp1; 2'b10 sel ypp2_ref; 2'b11 sel av_ref */ #define ADC_REG_g_refch12v 0x00620167 /* 0x167[5:4] 2'b00 sel vga; 2'b01 sel ypp1; 2'b10 sel ypp2_ref; 2'b11 sel av_ref */ #define ADC_REG_b_refch12v 0x00a40167 // 0x167[7:6] reserved /* 0x168[0] R channel low pass filter mode. */ #define ADC_REG_r_lpfmod12v 0x00000168 /* 0x168[1] G channel low pass filter mode. */ #define ADC_REG_g_lpfmod12v 0x00210168 /* 0x168[2] B channel low pass filter mode. */ #define ADC_REG_b_lpfmod12v 0x00420168 // 0x168[3] reserved /* 0x168[4] 1'b0: CVBS mode;1'b1 RGB mode */ #define ADC_REG_r_refclampsel12v 0x00840168 /* 0x168[5] 1'b0: CVBS mode;1'b1 RGB mode */ #define ADC_REG_g_refclampsel12v 0x00a50168 /* 0x168[6] 1'b0: CVBS mode;1'b1 RGB mode */ #define ADC_REG_b_refclampsel12v 0x00c60168 // 0x168[7] reserved /* 0x169[0] R channel interal/external reference enable. 0: internal reference; 1: externel reference */ #define ADC_REG_r_intrefen12v 0x00000169 /* 0x169[1] G channel interal/external reference enable. 0: internal reference; 1: externel reference */ #define ADC_REG_g_intrefen12v 0x00210169 /* 0x169[2] B channel interal/external reference enable. 0: internal reference; 1: externel reference */ #define ADC_REG_b_intrefen12v 0x00420169 // 0x169[3] reserved /* 0x169[4] av_ref pull down enable */ #define ADC_REG_epdy_12v 0x00840169 /* 0x169[5] */ #define ADC_REG_clamp_ictrl12v 0x00a50169 // 0x169[7:5] reserved //331_g0 /* 0x16a[0] */ #define ADC_REG_r_pden12v 0x0000016a /* 0x16a[1] */ #define ADC_REG_g_pden12v 0x0021016a /* 0x16a[2] */ #define ADC_REG_b_pden12v 0x0042016a // 0x16a[3] reserved /* 0x16a[4] */ #define ADC_REG_r_tswmiden12v 0x0084016a /* 0x16a[5] */ #define ADC_REG_g_tswmiden12v 0x00a5016a /* 0x16a[6] */ #define ADC_REG_b_tswmiden12v 0x00c6016a // 0x16a[7] reserved /* 0x16b[5:0] */ #define ADC_REG_cal_manual_th 0x00a0016b /* 0x16b[6] Enable VBG source selection according to HW control. */ #define ADC_REG_cal_manual_en 0x00c6016b /* 0x16b[7] */ #define ADC_REG_cal_rstn 0x00e7016b /* 0x16c[3:0] LVDS current calibration adjuster stop threshold. */ #define ADC_REG_cal_stop_th 0x0060016c // 0x16c[7:4] reserved /* 0x16d[5:0] [4]: VBG source selection. 0: from DEMOD, 1: from AUDIO */ #define ADC_REG_cal_sw_ctrl_th 0x00a0016d /* 0x16d[6] Enable VBG source selection according to SW control. */ #define ADC_REG_cal_sw_ctrl_en 0x00c6016d /* 0x16d[7] */ #define ADC_REG_sden12v 0x00e7016d /* 0x16e[1:0] */ #define ADC_REG_g_vr_sel 0x0021016e /* 0x16e[3:2] */ #define ADC_REG_y_vr_sel 0x0062016e // 0x16e[7:4] reserved // 0x16f[7:0] reserved /* 0x171[1:0] ~ 0x170[7:0] The parameter of tap 0. */ #define ADC_REG_r_fir_z0m 0x01200170 /* 0x172[3:0] ~ 0x171[7:2] The parameter of tap 1. */ #define ADC_REG_r_fir_z1m 0x02220171 /* 0x173[5:0] ~ 0x172[7:4] The parameter of tap 2. */ #define ADC_REG_r_fir_z2m 0x01a40172 // 0c173[7:6] reserved /* 0x175[1:0] ~ 0x174[7:0] The parameter of tap 3. */ #define ADC_REG_r_fir_z3m 0x01200174 /* 0x176[3:0] ~ 0x175[7:2] The parameter of tap 4. */ #define ADC_REG_r_fir_z4m 0x02220175 /* 0x177[5:0] ~ 0x176[7:4] The parameter of tap 5. */ #define ADC_REG_r_fir_z5m 0x01a40176 // 0c177[7:6] reserved /* 0x179[1:0] ~ 0x178[7:0] The parameter of tap 6. */ #define ADC_REG_r_fir_z6m 0x01200178 /* 0x17a[3:0] ~ 0x179[7:2] The parameter of tap 7. */ #define ADC_REG_r_fir_z7m 0x02220179 // 0x17a[7:4] reserved /* 0x17b[0] The sign bit of tap 0. */ #define ADC_REG_r_sign_fir_z0 0x0000017b /* 0x17b[1] The sign bit of tap 1. */ #define ADC_REG_r_sign_fir_z1 0x0021017b /* 0x17b[2] The sign bit of tap 2. */ #define ADC_REG_r_sign_fir_z2 0x0042017b /* 0x17b[3] The sign bit of tap 3. */ #define ADC_REG_r_sign_fir_z3 0x0063017b /* 0x17b[4] The sign bit of tap 4. */ #define ADC_REG_r_sign_fir_z4 0x0084017b /* 0x17b[5] The sign bit of tap 5. */ #define ADC_REG_r_sign_fir_z5 0x00a5017b /* 0x17b[6] The sign bit of tap 6. */ #define ADC_REG_r_sign_fir_z6 0x00c6017b /* 0x17b[7] The sign bit of tap 7. */ #define ADC_REG_r_sign_fir_z7 0x00e7017b /* 0x17c[1:0] 00: 1X fs, 01: 2X fs. */ #define ADC_REG_r_clk_rate 0x0020017c /* 0x17c[2] Bypass the FIR filter. */ #define ADC_REG_r_bypass_fir 0x0042017c /* 0x17c[3] Rising/failing edge trigger for decimation filter. */ #define ADC_REG_r_data_sel 0x0063017c // 0x17c[7:4] reserved // 0x17d[7:0] reserved /* 0x17e[7:0] Power down the No. 15~0 SOG-comparator. */ #define ADC_REG_sogcomp_pwdn12v_0to7 0x00e0017e /* 0x17f[7:0] Power down the No. 15~0 SOG-comparator. */ #define ADC_REG_sogcomp_pwdn12v_8to15 0x00e0017f /* 0x181[1:0] ~ 0x180[7:0] The parameter of tap 0. */ #define ADC_REG_g_fir_z0m 0x01200180 /* 0x182[3:0] ~ 0x181[7:2] The parameter of tap 1. */ #define ADC_REG_g_fir_z1m 0x02220181 /* 0x183[5:0] ~ 0x182[7:4] The parameter of tap 2. */ #define ADC_REG_g_fir_z2m 0x01a40182 // 0c183[7:6] reserved /* 0x185[1:0] ~ 0x184[7:0] The parameter of tap 3. */ #define ADC_REG_g_fir_z3m 0x01200184 /* 0x186[3:0] ~ 0x185[7:2] The parameter of tap 4. */ #define ADC_REG_g_fir_z4m 0x02220185 /* 0x187[5:0] ~ 0x186[7:4] The parameter of tap 5. */ #define ADC_REG_g_fir_z5m 0x01a40186 // 0c187[7:6] reserved /* 0x189[1:0] ~ 0x188[7:0] The parameter of tap 6. */ #define ADC_REG_g_fir_z6m 0x01200188 /* 0x18a[3:0] ~ 0x189[7:2] The parameter of tap 7. */ #define ADC_REG_g_fir_z7m 0x02220189 // 0x18a[7:4] reserved /* 0x18b[0] The sign bit of tap 0. */ #define ADC_REG_g_sign_fir_z0 0x0000018b /* 0x18b[1] The sign bit of tap 1. */ #define ADC_REG_g_sign_fir_z1 0x0021018b /* 0x18b[2] The sign bit of tap 2. */ #define ADC_REG_g_sign_fir_z2 0x0042018b /* 0x18b[3] The sign bit of tap 3. */ #define ADC_REG_g_sign_fir_z3 0x0063018b /* 0x18b[4] The sign bit of tap 4. */ #define ADC_REG_g_sign_fir_z4 0x0084018b /* 0x18b[5] The sign bit of tap 5. */ #define ADC_REG_g_sign_fir_z5 0x00a5018b /* 0x18b[6] The sign bit of tap 6. */ #define ADC_REG_g_sign_fir_z6 0x00c6018b /* 0x18b[7] The sign bit of tap 7. */ #define ADC_REG_g_sign_fir_z7 0x00e7018b /* 0x18c[1:0] 00: 1X fs, 01: 2X fs. */ #define ADC_REG_g_clk_rate 0x0020018c /* 0x18c[2] Bypass the FIR filter. */ #define ADC_REG_g_bypass_fir 0x0042018c /* 0x18c[3] Rising/failing edge trigger for decimation filter. */ #define ADC_REG_g_data_sel 0x0063018c // 0x18c[7:4] reserved // 0x18d[7:0] reserved // 0x18e[7:0] reserved // 0x18f[7:0] reserved /* 0x191[1:0] ~ 0x190[7:0] The parameter of tap 0. */ #define ADC_REG_b_fir_z0m 0x01200190 /* 0x192[3:0] ~ 0x191[7:2] The parameter of tap 1. */ #define ADC_REG_b_fir_z1m 0x02220191 /* 0x193[5:0] ~ 0x192[7:4] The parameter of tap 2. */ #define ADC_REG_b_fir_z2m 0x01a40192 // 0c193[7:6] reserved /* 0x195[1:0] ~ 0x194[7:0] The parameter of tap 3. */ #define ADC_REG_b_fir_z3m 0x01200194 /* 0x196[3:0] ~ 0x195[7:2] The parameter of tap 4. */ #define ADC_REG_b_fir_z4m 0x02220195 /* 0x197[5:0] ~ 0x196[7:4] The parameter of tap 5. */ #define ADC_REG_b_fir_z5m 0x01a40196 // 0c197[7:6] reserved /* 0x199[1:0] ~ 0x198[7:0] The parameter of tap 6. */ #define ADC_REG_b_fir_z6m 0x01200198 /* 0x19a[3:0] ~ 0x199[7:2] The parameter of tap 7. */ #define ADC_REG_b_fir_z7m 0x02220199 // 0x19a[7:4] reserved /* 0x19b[0] The sign bit of tap 0. */ #define ADC_REG_b_sign_fir_z0 0x0000019b /* 0x19b[1] The sign bit of tap 1. */ #define ADC_REG_b_sign_fir_z1 0x0021019b /* 0x19b[2] The sign bit of tap 2. */ #define ADC_REG_b_sign_fir_z2 0x0042019b /* 0x19b[3] The sign bit of tap 3. */ #define ADC_REG_b_sign_fir_z3 0x0063019b /* 0x19b[4] The sign bit of tap 4. */ #define ADC_REG_b_sign_fir_z4 0x0084019b /* 0x19b[5] The sign bit of tap 5. */ #define ADC_REG_b_sign_fir_z5 0x00a5019b /* 0x19b[6] The sign bit of tap 6. */ #define ADC_REG_b_sign_fir_z6 0x00c6019b /* 0x19b[7] The sign bit of tap 7. */ #define ADC_REG_b_sign_fir_z7 0x00e7019b /* 0x19c[1:0] 00: 1X fs, 01: 2X fs. */ #define ADC_REG_b_clk_rate 0x0020019c /* 0x19c[2] Bypass the FIR filter. */ #define ADC_REG_b_bypass_fir 0x0042019c /* 0x19c[3] Rising/failing edge trigger for decimation filter. */ #define ADC_REG_b_data_sel 0x0063019c // 0x19c[7:4] reserved // 0x19d[7:0] reserved // 0x19e[7:0] reserved // 0x19f[7:0] reserved /* 0x1a1[1:0] ~ 0x1a0[7:0] The parameter of tap 0. */ #define ADC_REG_y_fir_z0m 0x012001a0 /* 0x1a2[3:0] ~ 0x1a1[7:2] The parameter of tap 1. */ #define ADC_REG_y_fir_z1m 0x022201a1 /* 0x1a3[5:0] ~ 0x1a2[7:4] The parameter of tap 2. */ #define ADC_REG_y_fir_z2m 0x01a401a2 // 0c1a3[7:6] reserved /* 0x1a5[1:0] ~ 0x1a4[7:0] The parameter of tap 3. */ #define ADC_REG_y_fir_z3m 0x012001a4 /* 0x196[3:0] ~ 0x1a5[7:2] The parameter of tap 4. */ #define ADC_REG_y_fir_z4m 0x022201a5 /* 0x1a7[5:0] ~ 0x1a6[7:4] The parameter of tap 5. */ #define ADC_REG_y_fir_z5m 0x01a401a6 // 0c1a7[7:6] reserved /* 0x1a9[1:0] ~ 0x1a8[7:0] The parameter of tap 6. */ #define ADC_REG_y_fir_z6m 0x012001a8 /* 0x1aa[3:0] ~ 0x1a9[7:2] The parameter of tap 7. */ #define ADC_REG_y_fir_z7m 0x022201a9 // 0x1aa[7:4] reserved /* 0x1ab[0] The sign bit of tap 0. */ #define ADC_REG_y_sign_fir_z0 0x000001ab /* 0x1ab[1] The sign bit of tap 1. */ #define ADC_REG_y_sign_fir_z1 0x002101ab /* 0x1ab[2] The sign bit of tap 2. */ #define ADC_REG_y_sign_fir_z2 0x004201ab /* 0x1ab[3] The sign bit of tap 3. */ #define ADC_REG_y_sign_fir_z3 0x006301ab /* 0x1ab[4] The sign bit of tap 4. */ #define ADC_REG_y_sign_fir_z4 0x008401ab /* 0x1ab[5] The sign bit of tap 5. */ #define ADC_REG_y_sign_fir_z5 0x00a501ab /* 0x1ab[6] The sign bit of tap 6. */ #define ADC_REG_y_sign_fir_z6 0x00c601ab /* 0x1ab[7] The sign bit of tap 7. */ #define ADC_REG_y_sign_fir_z7 0x00e701ab /* 0x1ac[1:0] 00: 1X fs, 01: 2X fs. */ #define ADC_REG_y_clk_rate 0x002001ac /* 0x1ac[2] Bypass the FIR filter. */ #define ADC_REG_y_bypass_fir 0x004201ac /* 0x1ac[3] Rising/failing edge trigger for decimation filter. */ #define ADC_REG_y_data_sel 0x006301ac // 0x1ac[7:4] reserved // 0x1ad[7:0] reserved // 0x1ae[7:0] reserved // 0x1af[7:0] reserved #define ADC_REG_coast_pw_resize 0x006201b0 //coast 200 /* 0x1b0[1:0] Line update mode, 0: line_fall_wdth, 1: line_wdth, 2: mline_wdth, 3: line_fwdth_avg */ #define ADC_REG_coast200_line_update 0x002001b0 /* 0x1b0[3:2] Coast out select, 0: 200|resize, 1: 200&resize, 2: 200, 3: resize */ #define ADC_REG_coast_out_sel 0x006201b0 /* 0x1b0[5:4] Coast200 start option, 0: fall_cnt, 1: smt_dly&fall_cnt, 2: dg_fall, 3: pw_fall */ #define ADC_REG_coast200_start_opt 0x00a401b0 /* 0x1b0[7:6] Coast200 end option, 0: smt_fall, 1: smt_dg_fall, 2: forward count(end1), 3: backward count(end2) */ #define ADC_REG_coast200_end_opt 0x00e601b0 /* 0x1b1[7:0] Coast200 start with backward count. */ #define ADC_REG_coast200_start 0x00e001b1 /* 0x1b2[3:0] End with forward count. */ #define ADC_REG_coast200_end1 0x006001b2 /* 0x1b2[7:4] End with backward count. */ #define ADC_REG_coast200_end2 0x00e401b2 /* 0x1b3[3:0] Coast200 have to subtract filter offset. */ #define ADC_REG_filt_offset 0x006001b3 /* 0x1b3[5:4] Smt coast select. */ #define ADC_REG_coast_smt_sel 0x00a401b3 /* 0x1b3[7:6] Hsync valid fall decision. */ #define ADC_REG_hs_valid_fall 0x00e601b3 /* 0x1b4[7:0] Line threshold of hsync valid fall decision. */ #define ADC_REG_hs_vld_f_wdth 0x00e001b4 /* 0x1b5[3:0] Prev mask start threshold, 6*2 valid edge(line). */ #define ADC_reg_prev_mask_th 0x006001b5 /* 0x1b5[4] Prev mask enable for en_stb1_sclamp. */ #define ADC_reg_prev_mask1_en 0x008401b5 /* 0x1b5[5] Prev mask enable for throttling. */ #define ADC_reg_prev_mask2_en 0x00a501b5 /* 0x1b5[7:6] Enable vsync mask to pll, 0: ~vsync_mask, 1: 1'b1, 2: vsync_mask, 3: 1'b0 */ #define ADC_reg_vsync_mask_tpll_en 0x00e601b5 /* 0x1b6[2:0] Prev mask strong clamp throttling type. */ #define ADC_reg_sc_stb_pv_sth 0x004001b6 // 0x1b6[3] reserved /* 0x1b6[4] Vsync mask for line_wdth, low_wdth, line_fall_wdth. */ #define ADC_reg_vsync_mask_en1 0x008401b6 /* 0x1b6[5] Vsync mask for coast200_line_update. */ #define ADC_reg_vsync_mask_en2 0x00a501b6 /* 0x1b6[7:6] When to enable vsync_mask, 0: can't use, 1: means start vsync mask in 3rd V, ""stb_vcnt <= reg_vsync_mask_stb_cnt. */ #define ADC_reg_vsync_mask_stb_cnt 0x00e601b6 /* 0x1b7[7:0] Sign of 8 terms */ #define ADC_REG_bwmfir_sign 0x00e001b7 /* 0x1b8[7:0] 1st term(0+15) coeffient. */ #define ADC_REG_bwmfir_coeff0 0x00e001b8 /* 0x1b9[7:0] 2nd term(1+14) coeffient. */ #define ADC_REG_bwmfir_coeff1 0x00e001b9 /* 0x1ba[7:0] 3rd term(2+13) coeffient. */ #define ADC_REG_bwmfir_coeff2 0x00e001ba /* 0x1bb[7:0] 4th term(3+12) coeffient. */ #define ADC_REG_bwmfir_coeff3 0x00e001bb /* 0x1bc[7:0] 5th term(4+11) coeffient. */ #define ADC_REG_bwmfir_coeff4 0x00e001bc /* 0x1bd[7:0] 6th term(5+10) coeffient. */ #define ADC_REG_bwmfir_coeff5 0x00e001bd /* 0x1be[7:0] 7th term(6+9) coeffient. */ #define ADC_REG_bwmfir_coeff6 0x00e001be /* 0x1bf[7:0] 8th term(7+8) coeffient. */ #define ADC_REG_bwmfir_coeff7 0x00e001bf //system aux register #define GLB_REG_ALWAYS_HSI 0x10000039 //system main register #define GLB_REG_VCLK_DIV_RSTN 0x1021012f //0x12f[1] ADC_PLL reference divider reset #define GLB_REG_global_reset 0x10e7014b //[31] global reset #define GLB_REG_ECO_FIELD_SEL 0x10e70149 // 0x149[7] #define GLB_REG_VADC_REF_SEL_24M 0x10c60149 // 0x149[6] 24 MHz reference selector. 0: CPLL, 1: Crystal #define GLB_REG_YPP200MCLK_DIV 0x1060015c #define GLB_REG_YPP200MCLK_DIV_VALID 0x1084015c #define GLB_REG_YPP200MCLK_DIV_RSTN 0x10a5015c #define GLB_REG_A1ECO_CPLL_CEN_COMP 0x10e701b1 // 0x1b1[7] #define GLB_REG_A1ECO_CPLL_PTXCLK_DIV 0x10c001b1 // 0x1b1[6:0] #define GLB_REG_DEMOD_PWDN_BG 0x10e70215 //0x215[7] DMADC's BGP //OffsetComposation #define COMOFFSET_REG_cal_str 0x10422017 //[2] enable read data #define COMOFFSET_REG_even_odd_data 0x13e001dc //[31:0] read even and odd data #define COMOFFSET_REG_h_str 0x10602016 //[3:0] position #define COMOFFSET_REG_cal_adc_sel 0x10202017 //[1:0] channel selection #define COMOFFSET_REG_tst_en 0x10602019 //[3:0] [0] Enable coast_period //Debug port #define DEBUG_PROT_20 0x11e00020 //[15:0] #endif