#ifndef MARK_SISIDCT_H
#define MARK_SISIDCT_H

#ifdef __KERNEL__
#include <drv_devices.h>
#endif
#include <drv_types.h>


#define SISIDCT_DEV_FILE		"/dev/sisidct0"
//#define SISIDCT_DEV_MAJOR		99     						// sisidct device major code
#define SISIDCT_DEV_MAJOR		SISJPEG_DECODER_DEV_MAJOR
#define SISIDCT_DEV_MINOR		0
#define SISIDCT_DEV_NUM			1       					// Max number of device
#define IDCT					1 

// Driver option
#define SW_MODE_OPTIMAL			0
#define SW_MODE					1
#define HW_DSP_DECODER			2
#define HW_IDCT_ONLY			3
#define HW_ZZ_DEQUANT_IDCT		4
#define HW_JPEG_DECODER			5

#define VIP_PANORAMIC			0
#define VIP_THUMBNAIL			1

#define DSP_Enable				1
#if DSP_Enable
#define DSP_DEBUG				0
#define DSP_DATA_DEBUG			0
#define QTBL_DEBUG				0
#define HUFF_DEBUG				0
#define BITSTREAM_DEBUG			0
#define OutputY_DEBUG			0
#define OutputUV_DEBUG			0
#define MPO_DEBUG				0
#endif

typedef struct _IDCT_IOC_IOData
{
	// for reallocated I/O
	UINT16	port;
	UINT8	index;
	UINT8	value;
} IDCT_IOC_IOData, *IDCT_IOC_IODataPtr;

typedef struct _IDCT_IOC_MMIOData
{
	UINT32   addr;
	UINT32   value;
} IDCT_IOC_MMIOData, *IDCT_IOC_MMIODataPtr;

typedef enum
{
	ILF,
	QPEL,
	Rx0,
	Rx1,
}DSP_LD_SPACE;

typedef enum
{
	FMT_444 = 0x00020000,
	FMT_411 = 0x00000000,
	FMT_400 = 0x00040000,
	FMT_422MH = 0x00050000,
	FMT_422MV = 0x00060000,
	FMT_422H = 0x00010000,
	FMT_422V = 0x00030000,
}Encode_mod;

typedef enum
{
	DC_0 = 0x00000000,
	DC_1 = 0x00000040,
	AC_0 = 0x00000080,
	AC_1 = 0x00000540,
}Huff_table_no;

typedef enum
{
	SCL_1_1 = 0,
	SCL_1_2 = 1,
	SCL_1_4 = 2,
	SCL_1_8 = 3,
}Scale_num;

typedef struct 
{
	INT32 index;
	DSP_LD_SPACE LD_Space;
	UINT32 data;
} DSP_LD_4B, *pDSP_LD_4B;

typedef struct _DSP_Decode_Data
{
	UINT16		MCUs_in_width;
	UINT8		*Quant_table;
	UINT16		Quant_Len;
	UINT8		*Huff_table;
	UINT16		Huff_Len;
	UINT8		*outputY;
	UINT32		outputY_Len;
	UINT8		*outputUV;
	UINT32		outputUV_Len;
	UINT8		*BitStream;
	UINT32		BitStream_Len;
	pDSP_LD_4B 	DRI;				//Rx0 index 18: {DRI}
	pDSP_LD_4B 	MCUs_IMCUs_Rx1;		//Rx1, lif index 0: {MCUs, IMCUs}
	pDSP_LD_4B 	MCUs_IMCUs_ilf;
	pDSP_LD_4B 	color_format;		//Rx0 index 19: {format, 0x0000} 400=> 0004, 411=> 0000, 422_H==> 0001, 422_V=> 0003, 444=> 0002, 422MH=> 0005, 422MV=> 0006
	pDSP_LD_4B 	cformat_downsample;	//ilf index 1: (format, downsample} downsample: 0->1/1, 1->1/2, 2->1/4, 3->1/8
	pDSP_LD_4B 	sram_first_CMD[4];	//Rx0 index 2(DC_Y),3(AC_Y),4(DC_UV),5(AC_UV):{XX first bit X, XXXX} 1==>0, 2==>1, 3==>2, 4==>3
    pDSP_LD_4B 	comp_huff_tbl_no[6];	//Rx0 index 25:30      [0]:DC_Y, [1]:AC_Y,  [2]:DC_U, [3]:AC_V, [4]:DC_V, [5]:AC_V,
	UINT32	   	Remap_Total_Len;

	UINT8 		isAndroid;
	UINT8 		MPOPicIdx;
	
	UINT16		output_width;
	UINT16 		output_height;
	UINT8 		HwDecodeTimes;
	UINT8		HwSpecialDecode;
}DSP_Decode_Data, *DSP_Decode_DataPtr;

typedef struct _IDCT_IOC_DEVData
{
	UINT32		num_MCUs;
	UINT8		Y_Scale;
	UINT32		Y_H;
	UINT32		Y_V;

	UINT8		HW_mode;		//SW_MODE, HW_DSP_DECODER
	UINT8		pic_scale;		//used for ZZ_QUANT_IDCT with scale

	UINT8		*pVIPBuf;
	UINT32		pic_width;
	UINT32		pic_height;
	UINT32		ith_row;
	UINT32		ith_iMCU_row;		//used for SIS_JPEG_DECODER only, begin from 0

	//Add by Jason 
	UINT8		*pSrcBuf;
	UINT32		ith_dest_row;
	UINT32		pic_dest_width;
	UINT32		pic_dest_height;
											//hardware will wirte one iMCU_rows data into physical address
	//==> 01.10 New feature
	UINT16		driver_debug;		//0: disable, 1: enable
	UINT16		vip_resolution_X;
	UINT16		vip_resolution_Y;
	UINT16		vip_thumbnail_X;
	UINT16		vip_thumbnail_Y;

	INT16		vip_display_mode;		//VIP_PANORAMIC or VIP_THUMBNAIL
	INT16		thumb_index;
	UINT16 		thumb_upper_scope;
	UINT16		thumb_lower_scope;
	UINT16		thumb_left_scope;
	UINT16		thumb_right_scope;
	UINT16		thumb_tunnel;
	UINT16		thumb_x_items;
	UINT16		thumb_y_items;

	//=>software thumbnail_scaling	
	UINT16		thumb_delta_x;
	UINT16		thumb_delta_y;
	UINT16		thumb_dx_counts;
	UINT16		thumb_dy_counts;;
	UINT16		*pthumb_dx_order;
	UINT16		*pthumb_dy_order;
	UINT32		thumbpic_offset;		//starting address of thumbnail picture
	//<=
	UINT32		vip_lineoffset;
	UINT32		vip_address;
	UINT32		rotate_address;			//used for hardware pSrc, pDest and pQuant	
	UINT32		progressive_mode;
	UINT16		b_mp3_playing;
	//<==
	UINT8		haveJPEGEffects;
}IDCT_IOC_DEVData, *IDCT_IOC_DEVDataPtr;

// SiS Defined I/O Control Signal
#define IDCT_IOC_MAGIC     'i'
#define IDCT_IOC_BASE      192

#define IDCT_IOC_R_IO			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x01, IDCT_IOC_IOData)
#define IDCT_IOC_W_IO			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x02, IDCT_IOC_IOData)
#define IDCT_IOC_R_MIO			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x03, IDCT_IOC_MMIOData)
#define IDCT_IOC_W_MIO			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x04, IDCT_IOC_MMIOData)
#if DSP_Enable
#define DSP_HW_INIT				_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x05, DSP_Decode_Data)
#define DSP_Initial_MMIO		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x06, DSP_Decode_Data)
#define DSP_Deinitial_MMIO		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x07, DSP_Decode_Data)
#define DSP_RESET				_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x08, DSP_Decode_Data)
#define DSP_Load_Table			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x09, DSP_Decode_Data)
#define DSP_update_LD			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x010, DSP_Decode_Data)
#define DSP_Load_LP_LD			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x011, DSP_Decode_Data)
#define DSP_Set_Output_Info		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x012, DSP_Decode_Data)
#define DSP_Fire				_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x015, DSP_Decode_Data)
#ifndef CONFIG_JPG_MFD_Module
#define Get_OutputY_Addr		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x016, unsigned long)
#define Get_OutputUV_Addr		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x017, unsigned long)
#endif
#define Display_Image			_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x018, IDCT_IOC_DEVData)
#ifndef CONFIG_JPG_MFD_Module
#define Get_PhysBase_Addr		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x019, unsigned long)
#endif
#define Get_output_Width        _IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x01b, unsigned long)
#define Get_output_Height       _IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x01c, unsigned long)
#define Get_Bitstream_Addr		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x01e, unsigned long)
#define Get_DecodeErrFlag		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x021, JPEG_Decode_Data)
#define Set_DecodeErrFlag		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x022, JPEG_Decode_Data)
#endif

#define HW_VIP_DISPLAY_CRCBY		_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x013, IDCT_IOC_DEVData)
#ifndef CONFIG_JPG_MFD_Module
#define IDCT_IOC_HW_VIP_MEM_MODE	_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x014, UINT8)
#endif
#define IDCT_IOC_GET_MEMORY_SIZE	_IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x01a, long)
#define IDCT_IOC_SET_SOURCE_TYPE    _IOWR(IDCT_IOC_MAGIC, IDCT_IOC_BASE+0x01d, UINT32)


#endif // MARK_SISIDCT_H