#ifndef _ROM_SETTING #define _ROM_SETTING #include "../../project.h" /*** *********************************************************** * rom_setting.h * * 1. define all system register setting * 2. compiler option please refer CCopts.h * ************************************************************************/ #if (CONFIG_CHIPID==0x533) #define MCLK_DIV MCLK_DIV_6 #define CPUBCLK_DIV CPUCLK_DIV_4 #define DRAM_CPLL 0xD6F4222F //24.576*(0x2f+1)/(0+1) = 1179 #define DRAM_SSC1 0xf005 #define DRAM_SSC2 0x0428 #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_12 | ECLK_DIV_12 | SPICLK_DIV_12 | R_CPU_CLK_MUX_SEL #define ICLK_POST_DIV VIPX2ICLK_DIV_1179 #define IPCLK_DIV IPCLK_DIV_1179 #define CARDRCLK_DIV CARDRCLK_DIV_1179 #define BLTCLK_DIV BLTCLK_DIV_85 #if defined(CONFIG_CHIP_533) #define PHY_00 0x10880401 #define PHY_04 0xd6cc0688 #define PHY_08 0x06880600 #define PHY_0C 0x00000600 #define PHY_10 0x80000000 #define PHY_14 0x05000805 #define PHY_1C 0x0 #define MCTL_00 0x00000081 #define MCTL_04 0x84d10240 #define MCTL_200 0x0040b601 #define MCTL_208 0x21184999 #define MCTL_210 0x0052e5ae #elif defined(CONFIG_CHIP_512L) #define PHY_00 0x10880401 #define PHY_04 0xd6cc0688 #define PHY_08 0x06880600 #define PHY_0C 0x00000600 #define PHY_10 0x80000000 #define PHY_14 0x05000805 #define PHY_1C 0x0 #define MCTL_00 0x00000101 #define MCTL_04 0x02c10330 #define MCTL_200 0x00100001 #define MCTL_208 0x23145777 #define MCTL_210 0x1046b1be #endif #elif (CONFIG_CHIPID==0x531) #define MCLK_DIV MCLK_DIV_7 #define CPUBCLK_DIV CPUCLK_DIV_4 #define DRAM_CPLL 0x46502032 //24.576*(0x2f+1)/(0+1) = 1179 #define DRAM_SSC1 0xf010 #define DRAM_SSC2 0x0624 #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_12 | ECLK_DIV_12 | SPICLK_DIV_12 #define ICLK_POST_DIV VIPX2ICLK_DIV_1179 #define IPCLK_DIV IPCLK_DIV_1179 #define CARDRCLK_DIV CARDRCLK_DIV_1179 #define BLTCLK_DIV BLTCLK_DIV_85 #define PHY_00 0x10770c01 #define PHY_04 0x00440044 #define PHY_08 0x00440044 #define PHY_0C 0x00440044 #define PHY_10 0x48001000 #define PHY_14 0x00000001 #define PHY_1C 0x44444444 #define MCTL_00 0x00000081 #define MCTL_04 0x84d10258 #define MCTL_200 0x00208501 #define MCTL_208 0x000c3666 #define MCTL_210 0x004881ae #elif (CONFIG_CHIPID==0x331) #define DRAM_CPLL 0x46502032 //24.576*(0x2f+1)/(0+1) = 1179 #define PHY_00 0x10440401 #define PHY_08 0x00440044 #define PHY_10 0x48001000 #define PHY_14 0x00000001 #define PHY_1C 0x0 #if defined(CONFIG_CHIP_506) #define MCLK_DIV MCLK_DIV_7 #define CPUBCLK_DIV CPUCLK_DIV_4 #define DRAM_SSC1 0xf054 #define DRAM_SSC2 0x1eb8 #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_12 | ECLK_DIV_12 | SPICLK_DIV_12 #define ICLK_POST_DIV VIPX2ICLK_DIV_1179 #define IPCLK_DIV IPCLK_DIV_1179 #define CARDRCLK_DIV CARDRCLK_DIV_1179 #define BLTCLK_DIV BLTCLK_DIV_85 #define PHY_04 0x10440044 #define PHY_0C 0x00550044 #define MCTL_00 0x00000081 #define MCTL_04 0x84d10358 #define MCTL_200 0x00209501 #define MCTL_208 0x100e3777 #define MCTL_210 0x005081ae #elif defined(CONFIG_CHIP_307) || defined(CONFIG_CHIP_8501) #define MCLK_DIV MCLK_DIV_7 #define CPUBCLK_DIV CPUCLK_DIV_4 #define DRAM_SSC1 0xf04b #define DRAM_SSC2 0x1b85 #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_11 | ECLK_DIV_12 | SPICLK_DIV_12 #define ICLK_POST_DIV VIPX2ICLK_DIV_1179 #define IPCLK_DIV IPCLK_DIV_1179 #define CARDRCLK_DIV CARDRCLK_DIV_1179 #define BLTCLK_DIV BLTCLK_DIV_85 #define PHY_04 0x00570044 #define PHY_0C 0x00440044 #define MCTL_00 0x00000101 #define MCTL_04 0x02c10330 #define MCTL_200 0x00107701 #define MCTL_208 0x210d4555 #define MCTL_210 0x103d71be #elif defined(CONFIG_CHIP_305) #define MCLK_DIV MCLK_DIV_6 #define CPUBCLK_DIV CPUCLK_DIV_4 #define DRAM_SSC1 0xf03f #define DRAM_SSC2 0x170a #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_10 | ECLK_DIV_9 | SPICLK_DIV_9 #define ICLK_POST_DIV VIPX2ICLK_DIV_5 #define IPCLK_DIV IPCLK_DIV_5 #define CARDRCLK_DIV CARDRCLK_DIV_800 #define BLTCLK_DIV BLTCLK_DIV_84 #define PHY_04 0x00570044 #define PHY_0C 0x00440044 #define MCTL_00 0x00000101 #define MCTL_04 0x02c10330 #define MCTL_200 0x00107701 #define MCTL_208 0x310d4555 #define MCTL_210 0x103d71be #endif #elif (CONFIG_CHIPID==0x131) #define DRAM_CPLL 0x46502032 //24.576*(0x2f+1)/(0+1) = 1179 #define PHY_00 0x10880401 #define PHY_08 0x00880088 #define PHY_10 0x00001088 #define PHY_14 0x24000001 #define PHY_1C 0x0 #define MCLK_DIV MCLK_DIV_7 #define DRAM_SSC1 0xf04b #define DRAM_SSC2 0x1b85 #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_11 | ECLK_DIV_12 | SPICLK_DIV_12 #define ICLK_POST_DIV VIPX2ICLK_DIV_1179 #define IPCLK_DIV IPCLK_DIV_1179 #define CARDRCLK_DIV CARDRCLK_DIV_1179 #define PHY_04 0x00570088 #define PHY_0C 0x00880088 #define MCTL_00 0x00000101 #define MCTL_04 0x02c10328 #define MCTL_200 0x00207700 #define MCTL_208 0x310e4777 #define MCTL_210 0x103d71be #ifdef CONFIG_PLL_FRACTIONAL_MODE #define PREPLL_VALUE 0x308c2ebe #define CPLL_VALUE 0x80f00000 #define DIV_YPP_200M 0x5 #define DIV_MCLK 0x7 #define DIV_URCLK 0x61 #define DIV_CPUA 0x2 #define DIV_MMIO_CLK 0xb #define DIV_E_CLK 0xb #define DIV_SPI_CLK 0xb #define DIV_X2ICLK 0X5 #define DIV_F24576 0x17 #define CPUBCLK_DIV CPUCLK_DIV_3 #define BLTCLK_DIV BLTCLK_DIV_85 #else #define PREPLL_VALUE 0x7f8c0100 #define CPLL_VALUE 0xc811015f #define DIV_YPP_200M 0x3 #define DIV_MCLK 0x4 #define DIV_URCLK 0x3e #define DIV_CPUA 0x1 #define DIV_MMIO_CLK 0x7 #define DIV_E_CLK 0x7 #define DIV_SPI_CLK 0x7 #define DIV_X2ICLK 0X3 #define DIV_F24576 0x1d #define CPUBCLK_DIV CPUCLK_DIV_2 #define BLTCLK_DIV BLTCLK_DIV_83 #endif #elif (CONFIG_CHIPID==0x6710) #ifdef CONFIG_ENABLE_TCON_OVERDRIVE //DRAM 1200MHz #define DRAM_CPLL 0x318000a0 #define PHY_0C 0x0055c088 #define PHY_10 0x00000055 #else #define DRAM_CPLL 0x2b8000a0 #define PHY_0C 0x00ffc088 #define PHY_10 0x00000088 #endif #define PHY_00 0x10880401 #define PHY_08 0x00880088 #define PHY_14 0x24000001 #define PHY_1C 0x0 #define MCLK_DIV MCLK_DIV_7 #define DRAM_SSC1 0x0003 #define DRAM_SSC2 0x0226 #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_11 | ECLK_DIV_12 | SPICLK_DIV_12 #define ICLK_POST_DIV VIPX2ICLK_DIV_1179 #define IPCLK_DIV IPCLK_DIV_1179 #define CARDRCLK_DIV CARDRCLK_DIV_1179 #define PHY_04 0x00570088 #define MCTL_00 0x00000101 #define MCTL_04 0x02c10300 #ifdef CONFIG_ENABLE_TCON_OVERDRIVE //DRAM 1200MHz #define MCTL_200 0xc0200100 #define MCTL_208 0x31125888 #define MCTL_210 0x1043a1be #else #define MCTL_200 0x00207700 #define MCTL_208 0x310e4777 #define MCTL_210 0x103d71be #endif #ifdef _CCOPTS_ #if PLL_FRACTIONAL_MODE_1474M #define CPLL_VALUE 0x0585003c #define DIV_YPP_200M 0x7 #ifdef CONFIG_ENABLE_TCON_OVERDRIVE #define DIV_MCLK 0x8 #else #define DIV_MCLK 0x9 #endif #define DIV_URCLK 0x7a #define DIV_CPUA 0x3 #define DIV_MMIO_CLK 0xe #define DIV_E_CLK 0xe #define DIV_SPI_CLK 0xe #define DIV_X2ICLK 0x7 #define DIV_F24576 0x3b #define CPUBCLK_DIV CPUCLK_DIV_4 #define BLTCLK_DIV BLTCLK_DIV_86 #else #define CPLL_VALUE 0x05850030 #define DIV_YPP_200M 0x5 #ifdef CONFIG_ENABLE_TCON_OVERDRIVE #define DIV_MCLK 0x6 #else #define DIV_MCLK 0x7 #endif #define DIV_URCLK 0x61 #define DIV_CPUA 0x2 #define DIV_MMIO_CLK 0xb #define DIV_E_CLK 0xb #define DIV_SPI_CLK 0xb #define DIV_X2ICLK 0x5 #define DIV_F24576 0x2f #define CPUBCLK_DIV CPUCLK_DIV_3 #define BLTCLK_DIV BLTCLK_DIV_85 #endif #endif #elif (CONFIG_CHIPID==0x8506) #define DRAM_CPLL 0x46502032 //24.576*(0x2f+1)/(0+1) = 1179 #define PHY_00 0x1c880401 #define PHY_08 0x08880888 #define PHY_10 0x00001088 #define PHY_14 0x24000001 #define PHY_1C 0x0 #define MCLK_DIV MCLK_DIV_7 #define DRAM_SSC1 0xf04b #define DRAM_SSC2 0x1b85 #define MAIN_DIV CPUCLK_DIV_3 | CCLK_DIV_VALID | MMIO_CLK_DIV_11 | ECLK_DIV_12 | SPICLK_DIV_12 #define ICLK_POST_DIV VIPX2ICLK_DIV_1179 #define IPCLK_DIV IPCLK_DIV_1179 #define CARDRCLK_DIV CARDRCLK_DIV_1179 #define PHY_04 0x00570088 #define PHY_0C 0x00880888 #define MCTL_00 0x00000101 #define MCTL_04 0x02c10328 #ifdef CONFIG_ENABLE_TCON_OVERDRIVE //DRAM 1200MHz #define MCTL_200 0xc0200100 #define MCTL_208 0x31125888 #define MCTL_210 0x1043a1be #else //DRAM 1081MHz #define MCTL_200 0x00207700 #define MCTL_208 0x310e4777 #define MCTL_210 0x103d71be #endif #ifdef CONFIG_PLL_FRACTIONAL_MODE #ifdef _CCOPTS_ #if PLL_FRACTIONAL_MODE_1474M #define PREPLL_VALUE 0x3c832ebe #define CPLL_VALUE 0xc0b00000 #define DIV_YPP_200M 0x7 #define DIV_MCLK 0x9 #define DIV_URCLK 0x7a #define DIV_CPUA 0x3 #define DIV_MMIO_CLK 0xe #define DIV_E_CLK 0xe #define DIV_SPI_CLK 0xe #define DIV_X2ICLK 0x7 #define DIV_F24576 0x1d #define CPUBCLK_DIV CPUCLK_DIV_4 #define BLTCLK_DIV BLTCLK_DIV_86 #else #define PREPLL_VALUE 0x61833ebe #define CPLL_VALUE 0x80f00000 #define DIV_YPP_200M 0x5 #define DIV_MCLK 0x7 #define DIV_URCLK 0x61 #define DIV_CPUA 0x2 #define DIV_MMIO_CLK 0xb #define DIV_E_CLK 0xb #define DIV_SPI_CLK 0xb #define DIV_X2ICLK 0x5 #define DIV_F24576 0x17 #define CPUBCLK_DIV CPUCLK_DIV_3 #define BLTCLK_DIV BLTCLK_DIV_85 #endif #endif #else #define PREPLL_VALUE 0x7f8c0100 #define CPLL_VALUE 0xc811215f #define DIV_YPP_200M 0x3 #define DIV_MCLK 0x4 #define DIV_URCLK 0x3e #define DIV_CPUA 0x1 #define DIV_MMIO_CLK 0x7 #define DIV_E_CLK 0x7 #define DIV_SPI_CLK 0x7 #define DIV_X2ICLK 0X3 #define DIV_F24576 0x1d #define CPUBCLK_DIV CPUCLK_DIV_2 #define BLTCLK_DIV BLTCLK_DIV_83 #endif #endif #if ( CONFIG_DRAMSIZE == 64 ) #define MCTL_110 0x00300400 #define MCTL_20F 0x35 #define EDQS_LOOP 0x39fe #define MCTL_300 0x09010100 #elif( CONFIG_DRAMSIZE == 128 ) #define MCTL_110 0x00000010 #define MCTL_20F 0x48 #define EDQS_LOOP 0x3ece #define MCTL_300 0x0 #else #define MCTL_110 0x00305020 //256 #define MCTL_20F 0x5d #define EDQS_LOOP 0x3ece #define MCTL_300 0x0 #endif /**************************** be0001a4 [31:30]|R_MEM_PLL_OPI[1:0] [29:24]|R_MEM_PLL_GB[5:0] [23:16]|R_MEM_PLL_ICTRL[7:0] [13] |R_MEM_PLL_DIV2_ENA [12:8] |R_MEM_PLL_DIV[4:0] [7:0] |R_MEM_PLL_MUL[7:0] 24.576*(R_MEM_PLL_MUL[7:0]+1)/(R_MEM_PLL_DIV[4:0],+1) 1352 = 0xeb882036 1327 = 0xeb882035 1008 = 0xd0442028 1179 = 0xd999202f 800 = 0xd0442020 1400 = 0xeb882038 ****************************/ #if defined(CONFIG_CHIP_531) || defined(CONFIG_CHIP_506) #define R_MEM_PLL_OPI (0) #define R_MEM_PLL_GB (0x16) #define R_MEM_PLL_ICTRL (0xa0) #define R_MEM_PLL_DIV (1) #define R_MEM_PLL_MUL (0x5f) #elif defined(CONFIG_CHIP_533) #define R_MEM_PLL_OPI (0) #define R_MEM_PLL_GB (0x46) #define R_MEM_PLL_ICTRL (0x09) #define R_MEM_PLL_DIV (8) #define R_MEM_PLL_MUL (0x3c) #elif defined(CONFIG_CHIP_512L) #define R_MEM_PLL_OPI (0) #define R_MEM_PLL_GB (0x46) #define R_MEM_PLL_ICTRL (0x09) #define R_MEM_PLL_DIV (8) #define R_MEM_PLL_MUL (0x32) #elif defined(CONFIG_CHIP_307) || defined(CONFIG_CHIP_8501) #define R_MEM_PLL_OPI (0) #define R_MEM_PLL_GB (0x0d) #define R_MEM_PLL_ICTRL (0x20) #define R_MEM_PLL_DIV (1) #define R_MEM_PLL_MUL (0x55) #elif defined(CONFIG_CHIP_305) #define R_MEM_PLL_OPI (0) #define R_MEM_PLL_GB (0x08) #define R_MEM_PLL_ICTRL (0x20) #define R_MEM_PLL_DIV (1) #define R_MEM_PLL_MUL (0x47) #elif defined(CONFIG_CHIP_8503) || defined(CONFIG_CHIP_8506) #define R_MEM_PLL_OPI (2) #define R_MEM_PLL_GB (0x09) #define R_MEM_PLL_ICTRL (0x06) #define R_MEM_PLL_DIV (0) #ifdef CONFIG_ENABLE_TCON_OVERDRIVE //DRAM 1200MHz #define R_MEM_PLL_MUL (0x32) #else //DRAM 1081MHz #define R_MEM_PLL_MUL (0x2b) #endif #else #define R_MEM_PLL_OPI (0x3) #define R_MEM_PLL_GB (0x19) #define R_MEM_PLL_ICTRL (0x99) #define R_MEM_PLL_DIV (0) #define R_MEM_PLL_MUL (0x2f) #endif #if defined(CONFIG_CHIP_8503) || defined(CONFIG_CHIP_8506) #define R_MEM_PLL_DIV2_ENA (0) #else #define R_MEM_PLL_DIV2_ENA (1) #endif #define MEMPLL_SETTING \ ((R_MEM_PLL_OPI << 30) | \ (R_MEM_PLL_GB << 24) | \ (R_MEM_PLL_ICTRL << 16) | \ (R_MEM_PLL_DIV2_ENA << 13) | \ (R_MEM_PLL_DIV << 8) | \ R_MEM_PLL_MUL) #endif