#ifndef _REG_HDMIRX_DEF_H_ #define _REG_HDMIRX_DEF_H_ /* *@Address: 0xBE0E1000[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1000_DW_1000 0x48001000 /* *@Address: 0xBE0E1000[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PAT_PHYCD_7_0_ 0x42001000 /* *@Address: 0xBE0E1000[9:8] *@Range: 0~3 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PLLGB_PHYCD_1_0_ 0x40801001 /* *@Address: 0xBE0E1000[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_PHYCD_39_32_ 0x42001002 /* *@Address: 0xBE0E1000[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_PHYCD_47_40_ 0x42001003 /* *@Address: 0xBE0E1004[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1004_DW_1004 0x48001004 /* *@Address: 0xBE0E1004[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_PHYCD_7_0_ 0x42001004 /* *@Address: 0xBE0E1004[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_PHYCD_15_8_ 0x42001005 /* *@Address: 0xBE0E1004[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_PHYCD_23_16_ 0x42001006 /* *@Address: 0xBE0E1004[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_PHYCD_31_24_ 0x42001007 /* *@Address: 0xBE0E1008[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1008_DW_1008 0x48001008 /* *@Address: 0xBE0E1008[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * PHY freq detection setting */ #define HDMIRX_R_DETECT_START_PHYCD 0x40401008 /* *@Address: 0xBE0E1008[7:4] *@Range: 0~15 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PC_CTRL_PHYCD_3_0_ 0x41041008 /* *@Address: 0xBE0E1008[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_LOCK_START_PHYCD 0x40401009 /* *@Address: 0xBE0E1008[12] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_ERR_CLRN_PHYCD 0x40441009 /* *@Address: 0xBE0E1008[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_LOCK_ABORT_PHYCD 0x4040100A /* *@Address: 0xBE0E1008[23:20] *@Range: 0~15 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PAT_PHYCD_11_8_ 0x4104100A /* *@Address: 0xBE0E1008[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PAT_PHYCD_19_12_ 0x4200100B /* *@Address: 0xBE0E100C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_100C_DW_100C 0x4800100C /* *@Address: 0xBE0E100C[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_FA_CNT_PHYCD_7_0_ 0x4200100C /* *@Address: 0xBE0E100C[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_FB_CNT_PHYCD_7_0_ 0x4200100D /* *@Address: 0xBE0E100C[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_FC_CNT_PHYCD_7_0_ 0x4200100E /* *@Address: 0xBE0E100C[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_FD_CNT_PHYCD_7_0_ 0x4200100F /* *@Address: 0xBE0E1010[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1010_DW_1010 0x48001010 /* *@Address: 0xBE0E1010[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_FE_CNT_PHYCD_7_0_ 0x42001010 /* *@Address: 0xBE0E1010[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_FF_CNT_PHYCD_7_0_ 0x42001011 /* *@Address: 0xBE0E1010[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_C_PHYCD_31_24_ 0x42001013 /* *@Address: 0xBE0E1014[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1014_DW_1014 0x48001014 /* *@Address: 0xBE0E1014[5:0] *@Range: 0~63 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_LOCK_RANGE_PHYCD_5_0_ 0x41801014 /* *@Address: 0xBE0E1014[11:8] *@Range: 0~15 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_LOCK_CNT_PHYCD_3_0_ 0x41001015 /* *@Address: 0xBE0E1014[21:16] *@Range: 0~63 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_UNLOCK_RANGE_PHYCD_5_0_ 0x41801016 /* *@Address: 0xBE0E1014[27:24] *@Range: 0~15 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_UNLOCK_CNT_PHYCD_3_0_ 0x41001017 /* *@Address: 0xBE0E1018[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1018_DW_1018 0x48001018 /* *@Address: 0xBE0E1018[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_B_PHYCD_7_0_ 0x42001018 /* *@Address: 0xBE0E1018[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_B_PHYCD_15_8_ 0x42001019 /* *@Address: 0xBE0E1018[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_B_PHYCD_23_16_ 0x4200101A /* *@Address: 0xBE0E1018[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_B_PHYCD_31_24_ 0x4200101B /* *@Address: 0xBE0E101C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_101C_DW_101C 0x4800101C /* *@Address: 0xBE0E101C[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_ALIGN_CNT_PHYCD_7_0_ 0x4200101C /* *@Address: 0xBE0E101C[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_C_PHYCD_7_0_ 0x4200101D /* *@Address: 0xBE0E101C[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_C_PHYCD_15_8_ 0x4200101E /* *@Address: 0xBE0E101C[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_PHY_CTL_C_PHYCD_23_16_ 0x4200101F /* *@Address: 0xBE0E1020[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_1020_DW_1020 0x48001020 /* *@Address: 0xBE0E1020[0] *@Range: 0~1 *@Default: *@Access: *@Description: * (useless) */ #define HDMIRX_IN_RANGE_CD 0x40401020 /* *@Address: 0xBE0E1020[3] *@Range: 0~1 *@Default: *@Access: R *@Description: * (useless) */ #define HDMIRX_ALIGN_CD 0x40431020 /* *@Address: 0xBE0E1020[8] *@Range: 0~1 *@Default: *@Access: *@Description: None */ #define HDMIRX_PHYPLLLOCK_CD 0x40401021 /* *@Address: 0xBE0E1020[12] *@Range: 0~1 *@Default: *@Access: R *@Description: * (useless) */ #define HDMIRX_PHYDBG_CDRRSTJ_CD 0x40441021 /* *@Address: 0xBE0E1020[17:16] *@Range: 0~3 *@Default: *@Access: R *@Description: * (useless) */ #define HDMIRX_PHYDBG_PLLGB_1_0_ 0x40801022 /* *@Address: 0xBE0E1020[24] *@Range: 0~1 *@Default: *@Access: *@Description: * (useless) */ #define HDMIRX_PHYDBG_CMPZI_CD 0x40401023 /* *@Address: 0xBE0E1020[28] *@Range: 0~1 *@Default: *@Access: R *@Description: * (useless) */ #define HDMIRX_PHYDBG_S0RCTL_CD 0x40441023 /* *@Address: 0xBE0E1024[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_1024_DW_1024 0x48001024 /* *@Address: 0xBE0E1024[2:0] *@Range: 0~7 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_PHY_MHL_MODE 0x40C01024 /* *@Address: 0xBE0E1024[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_ref_freq_cnt 0x42001025 /* *@Address: 0xBE0E1024[28:24] *@Range: 0~31 *@Default: *@Access: R *@Description: * [2:0]: mhl clk mode, [3]: mhl_path_en, [4]: mhl_muted */ #define HDMIRX_cbus_mode_pathen_muted 0x41401027 /* *@Address: 0xBE0E1028[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_1028_DW_1028 0x48001028 /* *@Address: 0xBE0E1028[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_RTTDBG_7_0_ 0x42001028 /* *@Address: 0xBE0E1028[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_RTTDBG_15_8_ 0x42001029 /* *@Address: 0xBE0E1050[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_1050_DW_1050 0x48001050 /* *@Address: 0xBE0E1050[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP0_RTT_CAL_DBG_7_0_ 0x42001050 /* *@Address: 0xBE0E1050[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP0_RTT_CAL_DBG_15_8_ 0x42001051 /* *@Address: 0xBE0E1050[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP1_FREQ_CNT_OUT_7_0_ 0x42001052 /* *@Address: 0xBE0E1050[28:24] *@Range: 0~31 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP1_FREQ_CNT_OUT_12_8_ 0x41401053 /* *@Address: 0xBE0E1054[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_1054_DW_1054 0x48001054 /* *@Address: 0xBE0E1054[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP1_DBG_OUT_7_0_ 0x42001054 /* *@Address: 0xBE0E1054[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP2_FREQ_CNT_OUT_7_0_ 0x42001055 /* *@Address: 0xBE0E1054[20:16] *@Range: 0~31 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP2_FREQ_CNT_OUT_12_8_ 0x41401056 /* *@Address: 0xBE0E1054[31:24] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP2_DBG_OUT_7_0_ 0x42001057 /* *@Address: 0xBE0E1058[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_1058_DW_1058 0x48001058 /* *@Address: 0xBE0E1058[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_DBG_PIDO_P0_DBG_D0_P0_7_0_ 0x42001058 /* *@Address: 0xBE0E1058[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_DBG_PIDO_P1_DBG_D0_P1_7_0_ 0x42001059 /* *@Address: 0xBE0E1058[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP_DBG_7_0_ 0x4200105A /* *@Address: 0xBE0E1058[24] *@Range: 0~1 *@Default: *@Access: R *@Description: None */ #define HDMIRX_REG_HDMIP_DBG_8_ 0x4040105B /* *@Address: 0xBE0E0020[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0020_DW_0020 0x48000020 /* *@Address: 0xBE0E0020[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * [0]:PHYDBG_IN_RANGE_PHYAB, */ #define HDMIRX_IN_RANGE 0x40400020 /* *@Address: 0xBE0E0020[3] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * [3]:ALIGN_PHYAB */ #define HDMIRX_ALIGN 0x40430020 /* *@Address: 0xBE0E0020[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * [8]:PLLLOCK_PHYAB */ #define HDMIRX_PHYPLLLOCK 0x40400021 /* *@Address: 0xBE0E0020[12] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * [12]: PHYDBG_CDRRSTJ_PHYAB */ #define HDMIRX_PHYDBG_CDRRSTJ 0x40440021 /* *@Address: 0xBE0E0020[17:16] *@Range: 0~3 *@Default: *@Access: R/W *@Description: * [17:16]: PHYDBG_PLLGB_PHYAB, */ #define HDMIRX_PHYDBG_PLLGB 0x40800022 /* *@Address: 0xBE0E0020[21:20] *@Range: 0~3 *@Default: *@Access: R/W *@Description: * [21:20]:R_DIV_SEL_PHYAB */ #define HDMIRX_DIV_SEL 0x40840022 /* *@Address: 0xBE0E0020[24] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * [24]:PHYDBG_CMPZI_PHYAB */ #define HDMIRX_PHYDBG_CMPZI 0x40400023 /* *@Address: 0xBE0E0020[28] *@Range: 0~1 *@Default: *@Access: *@Description: * [28]: PHYDBG_S0RCTL_PHYAB */ #define HDMIRX_PHYDBG_S0RCTL 0x40440023 /* *@Address: 0xBE0E0024[31:0] *@Range: 0~4294967295 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_0024_DW_0024 0x48000024 /* *@Address: 0xBE0E0024[2:0] *@Range: 0~7 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_inter_alignment_once 0x40C00024 /* *@Address: 0xBE0E0024[10:8] *@Range: 0~7 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_always_align_proc 0x40C00025 /* *@Address: 0xBE0E0024[18:16] *@Range: 0~7 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_unalign_rst_FIFO 0x40C00026 /* *@Address: 0xBE0E0024[26:24] *@Range: 0~7 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_no_inter_alignment 0x40C00027 /* *@Address: 0xBE0E0028[31:0] *@Range: 0~4294967295 *@Default: 0x3030000 *@Access: R/W *@Description: None */ #define HDMIRX_0028_DW_0028 0x48000028 /* *@Address: 0xBE0E0028[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 0: gb value come from register (R_PHY_SEL=0 ? PHYAB : PHYCD) */ #define HDMIRX_R_err_det_en 0x40400028 /* *@Address: 0xBE0E0028[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 0: gb value come from register (R_PHY_SEL=0 ? PHYAB : PHYCD) */ #define HDMIRX_R_auto_err_det 0x40400029 /* *@Address: 0xBE0E0028[18:16] *@Range: 0~7 *@Default: 0x3 *@Access: R/W *@Description: None */ #define HDMIRX_R_scan_min 0x40C0002A /* *@Address: 0xBE0E0028[26:24] *@Range: 0~7 *@Default: 0x3 *@Access: R/W *@Description: None */ #define HDMIRX_R_scan_max 0x40C0002B /* *@Address: 0xBE0E002C[31:0] *@Range: 0~4294967295 *@Default: 0x2ff00 *@Access: RW *@Description: None */ #define HDMIRX_002C_DW_002C 0x4800002C /* *@Address: 0xBE0E002C[2:0] *@Range: 0~7 *@Default: 0x0 *@Access: RW *@Description: None */ #define HDMIRX_R_all_err_prefer_value 0x40C0002C /* *@Address: 0xBE0E002C[17:8] *@Range: 0~1023 *@Default: 0xff *@Access: R/W *@Description: None */ #define HDMIRX_R_video_lenght_rule 0x4288002C /* *@Address: 0xBE0E002C[24] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Select phy interrupt source: 0:PHYAB, 1:PHYCD */ #define HDMIRX_R_PHY_SEL 0x4040002F /* *@Address: 0xBE0E0030[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0030_DW_0030 0x48000030 /* *@Address: 0xBE0E0030[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_cnt_pat_fail_0 0x42000030 /* *@Address: 0xBE0E0030[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_cnt_rule_fail_0 0x42000031 /* *@Address: 0xBE0E0030[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_cnt_pat_fail_1 0x42000032 /* *@Address: 0xBE0E0030[31:24] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_cnt_rule_fail_1 0x42000033 /* *@Address: 0xBE0E0034[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0034_DW_0034 0x48000034 /* *@Address: 0xBE0E0034[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_cnt_pat_fail_2 0x42000034 /* *@Address: 0xBE0E0034[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_cnt_rule_fail_2 0x42000035 /* *@Address: 0xBE0E0034[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * PLL lock det : 0:digital HW detect, 1:PHY detect */ #define HDMIRX_R_phy_freq_det 0x40400036 /* *@Address: 0xBE0E0034[26:24] *@Range: 0~7 *@Default: 0x0 *@Access: R/W *@Description: * Change channel order: * 0: {ch0,ch1,ch2},1: {ch0,ch2,ch1},2: {ch1,ch0,ch2}, * 3: {ch1,ch2,ch0},4: {ch2,ch0,ch1},5: {ch2,ch1,ch0} */ #define HDMIRX_R_ch_order 0x40C00037 /* *@Address: 0xBE0E0038[31:0] *@Range: 0~4294967295 *@Default: 0x10000 *@Access: R/W *@Description: None */ #define HDMIRX_0038_DW_0038 0x48000038 /* *@Address: 0xBE0E0038[31:0] *@Range: 0~4294967295 *@Default: 0x10000 *@Access: R/W *@Description: * Time rule detect */ #define HDMIRX_R_time_rule_det 0x48000038 /* *@Address: 0xBE0E003C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_003C_DW_003C 0x4800003C /* *@Address: 0xBE0E003C[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: * Debug port A select */ #define HDMIRX_R_sel_A 0x4200003D /* *@Address: 0xBE0E003C[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: * Debug port B select */ #define HDMIRX_R_sel_B 0x4200003E /* *@Address: 0xBE0E0040[31:0] *@Range: 0~4294967295 *@Default: 0x1B010100 *@Access: R/W *@Description: None */ #define HDMIRX_0040_DW_0040 0x48000040 /* *@Address: 0xBE0E0040[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * HDMI Software reset (active low) */ #define HDMIRX_R_rst_n 0x40400040 /* *@Address: 0xBE0E0040[8] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: * 1:HDCP ready */ #define HDMIRX_R_hdcp_always_rdy 0x40400041 /* *@Address: 0xBE0E0040[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: * 1: HW set phy pd value when DDC5V=0 */ #define HDMIRX_R_auto_phypd 0x40400042 /* *@Address: 0xBE0E0040[28:24] *@Range: 0~31 *@Default: 0x1B *@Access: R/W *@Description: * Inactive condition check: [0]: R_rst_n, [1]: DDC5V, [2]: PLLLOCK,[3]: DATARSTJ * [4]: inter channel alignment */ #define HDMIRX_R_inactive_level 0x41400043 /* *@Address: 0xBE0E0044[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_0044_DW_0044 0x48000044 /* *@Address: 0xBE0E0044[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1: CDRRSTJ=1 */ #define HDMIRX_R_no_cdrrst 0x40400045 /* *@Address: 0xBE0E0044[31:16] *@Range: 0~65535 *@Default: 0x0 *@Access: R/W *@Description: * HDCP control register: * [0]:hdcp enable, [1]:hdcp test mode, [2]: SW_key type (1:mmio IF, 0:eeprom IF),[3]:read bksv[7:4]: hdcp encryption count threshold,[12:8]:i2c period, [13]:eeprom_chksum,[14]:i2c rst(Master),[15]:1.1_FEATURES(Bcaps) */ #define HDMIRX_R_HDCP_CTL 0x44100044 /* *@Address: 0xBE0E0048[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R *@Description: None */ #define HDMIRX_0048_DW_0048 0x48000048 /* *@Address: 0xBE0E0048[9:8] *@Range: 0~3 *@Default: 0x0 *@Access: R/W *@Description: * Select which HDMI port work (00:Link 0, 01:Link 1, 10:Link2) */ #define HDMIRX_R_HDMI_LinkS 0x40800049 /* *@Address: 0xBE0E0048[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Disable HDMI decode function ( for debug) */ #define HDMIRX_R_HDMI_disable 0x4040004A /* *@Address: 0xBE0E0048[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * HDMI enable ( 1: HDMI 0: DVI ) */ #define HDMIRX_R_HDMI_en 0x4040004B /* *@Address: 0xBE0E004C[31:0] *@Range: 0~4294967295 *@Default: 0x14 *@Access: R/W *@Description: None */ #define HDMIRX_004C_DW_004C 0x4800004C /* *@Address: 0xBE0E004C[31:0] *@Range: 0~4294967295 *@Default: 0x14 *@Access: R/W *@Description: * Power on sequence Timer */ #define HDMIRX_R_stable_time 0x4800004C /* *@Address: 0xBE0E0050[31:0] *@Range: 0~4294967295 *@Default: 0x10 *@Access: R/W *@Description: None */ #define HDMIRX_0050_DW_0050 0x48000050 /* *@Address: 0xBE0E0050[31:0] *@Range: 0~4294967295 *@Default: 0x10 *@Access: R/W *@Description: * Power on sequence Timer */ #define HDMIRX_R_unknown_time 0x48000050 /* *@Address: 0xBE0E0054[31:0] *@Range: 0~4294967295 *@Default: 0x14 *@Access: R/W *@Description: None */ #define HDMIRX_0054_DW_0054 0x48000054 /* *@Address: 0xBE0E0054[31:0] *@Range: 0~4294967295 *@Default: 0x14 *@Access: R/W *@Description: * Power on sequence Timer */ #define HDMIRX_R_output_chg_time 0x48000054 /* *@Address: 0xBE0E0058[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0058_DW_0058 0x48000058 /* *@Address: 0xBE0E0058[2:0] *@Range: 0~7 *@Default: *@Access: R *@Description: * DDC5V detection for link: [0]:linkA,[1]linkB,[2]:linkC */ #define HDMIRX_R_DDC5V 0x40C00058 /* *@Address: 0xBE0E0058[10:8] *@Range: 0~7 *@Default: *@Access: R *@Description: * Hot Plug setting for link: [0]:linkA,[1]linkB,[2]:linkC */ #define HDMIRX_R_Hot_plug 0x40C00059 /* *@Address: 0xBE0E005C[31:0] *@Range: 0~4294967295 *@Default: 0x400 *@Access: R/W *@Description: None */ #define HDMIRX_005C_DW_005C 0x4800005C /* *@Address: 0xBE0E005C[10:0] *@Range: 0~2047 *@Default: 0x40 *@Access: R/W *@Description: * Freq fail threshold */ #define HDMIRX_R_freq_fail_th 0x42C0005C /* *@Address: 0xBE0E005C[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: * write 1 clear */ #define HDMIRX_unstable_align_cnt 0x4200005E /* *@Address: 0xBE0E0060[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0060_DW_0060 0x48000060 /* *@Address: 0xBE0E0060[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * PHY reset status */ #define HDMIRX_R_DATARSTJ_status 0x40400061 /* *@Address: 0xBE0E0060[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * HDMI reset status */ #define HDMIRX_R_HDMI_rst_n 0x40400062 /* *@Address: 0xBE0E0060[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * HDCP reset status */ #define HDMIRX_R_HDCP_rst_n 0x40400063 /* *@Address: 0xBE0E0064[31:0] *@Range: 0~4294967295 *@Default: 0x4 *@Access: R/W *@Description: None */ #define HDMIRX_0064_DW_0064 0x48000064 /* *@Address: 0xBE0E0064[3:0] *@Range: 0~15 *@Default: 0x4 *@Access: R/W *@Description: * Character boundary align counter (1~15) (for symlock) */ #define HDMIRX_R_ALIGN_CNT 0x41000064 /* *@Address: 0xBE0E0064[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * Ch0 symbol lock */ #define HDMIRX_R_Symlock0 0x40400065 /* *@Address: 0xBE0E0064[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * Ch1 symbol lock */ #define HDMIRX_R_Symlock1 0x40400066 /* *@Address: 0xBE0E0064[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * Ch2 symbol lock */ #define HDMIRX_R_Symlock2 0x40400067 /* *@Address: 0xBE0E0068[31:0] *@Range: 0~4294967295 *@Default: 0x1010404 *@Access: R/W *@Description: None */ #define HDMIRX_0068_DW_0068 0x48000068 /* *@Address: 0xBE0E0068[3:0] *@Range: 0~15 *@Default: 0x4 *@Access: R/W *@Description: * Inter-channel align counter (0~15) (interalign th) */ #define HDMIRX_R_BYTE_ALIGN_CNT1 0x41000068 /* *@Address: 0xBE0E0068[11:8] *@Range: 0~15 *@Default: 0x4 *@Access: R/W *@Description: * Inter-channel unalign counter (0~15) */ #define HDMIRX_R_BYTE_ALIGN_CNT2 0x41000069 /* *@Address: 0xBE0E0068[23:16] *@Range: 0~255 *@Default: 0x01 *@Access: R/W *@Description: * Timeout value 1 (timeout_unsymlock */ #define HDMIRX_R_REALIGN_TIMER1 0x4200006A /* *@Address: 0xBE0E0068[31:24] *@Range: 0~255 *@Default: 0x01 *@Access: R/W *@Description: * Timeout value 2 (timeout_unalign) */ #define HDMIRX_R_REALIGN_TIMER2 0x4200006B /* *@Address: 0xBE0E006C[31:0] *@Range: 0~4294967295 *@Default: 0x407 *@Access: R/W *@Description: None */ #define HDMIRX_006C_DW_006C 0x4800006C /* *@Address: 0xBE0E006C[2:0] *@Range: 0~7 *@Default: 0x7 *@Access: R/W *@Description: * Bit boundaries realign enable ( [0]: retry_align_th (align_cnt_2) * [1]: retry_symlock_unalign (timer2) [2]: retry_unsymlock (timer1) ) */ #define HDMIRX_R_REALIGN_EN 0x40C0006C /* *@Address: 0xBE0E006C[11:8] *@Range: 0~15 *@Default: 0x4 *@Access: R/W *@Description: * Bit boundaries realign counter (0~15) (PLL_reset_th for realign_en[2]) */ #define HDMIRX_R_REALIGN_CNT 0x4100006D /* *@Address: 0xBE0E006C[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Transition HDMI mode to DVI mode when Receiver has not seen at least one Data Island within 30 video frame. ( 1: enable) */ #define HDMIRX_R_frame_cnt30 0x4040006E /* *@Address: 0xBE0E006C[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * Inter-channel alignment status */ #define HDMIRX_R_Inter_channel_alignment 0x4040006F /* *@Address: 0xBE0E0070[31:0] *@Range: 0~4294967295 *@Default: 0x200 *@Access: R/W *@Description: None */ #define HDMIRX_0070_DW_0070 0x48000070 /* *@Address: 0xBE0E0070[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Inverse RX Data Input port [9:0] -> [0:9] */ #define HDMIRX_R_INV_RX 0x40400070 /* *@Address: 0xBE0E0070[10:8] *@Range: 0~7 *@Default: 0x2 *@Access: R/W *@Description: * Inter-channel alignment¡¦s write buffer threshold (start to inter_alignment) */ #define HDMIRX_R_InterCA_TH 0x40C00071 /* *@Address: 0xBE0E0070[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Detect video preamble to become HDMI mode */ #define HDMIRX_R_video_preamble 0x40400072 /* *@Address: 0xBE0E0074[31:0] *@Range: 0~4294967295 *@Default: 0x1010404 *@Access: R/W *@Description: None */ #define HDMIRX_0074_DW_0074 0x48000074 /* *@Address: 0xBE0E0074[4:0] *@Range: 0~31 *@Default: 0x8 *@Access: R/W *@Description: None */ #define HDMIRX_R_freq_stable_th 0x41400074 /* *@Address: 0xBE0E0074[12:8] *@Range: 0~31 *@Default: 0x8 *@Access: R/W *@Description: None */ #define HDMIRX_R_freq_unstable_th 0x41400075 /* *@Address: 0xBE0E0074[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_freq_con_match 0x40400076 /* *@Address: 0xBE0E0074[24] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_DDC5V_reset 0x40400077 /* *@Address: 0xBE0E0078[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0078_DW_0078 0x48000078 /* *@Address: 0xBE0E0078[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * [0]: chksum_pass [1]: chksum_done [2]: authenticated [3]: feature1.1_rxtx * [13:4]: enc_state [15:14]: I2C_done_status */ #define HDMIRX_R_HDCP_status 0x48000078 /* *@Address: 0xBE0E007C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_007C_DW_007C 0x4800007C /* *@Address: 0xBE0E007C[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Tie DATARSTJ to high */ #define HDMIRX_R_DATATRSTJ_HIGH 0x4040007C /* *@Address: 0xBE0E007C[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Strict hdmi detection */ #define HDMIRX_R_strict_hdmi_det 0x4040007D /* *@Address: 0xBE0E007C[24] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * HDMI_en chg only at vsync */ #define HDMIRX_R_HDMI_out_vsync 0x4040007F /* *@Address: 0xBE0E0080[31:0] *@Range: 0~4294967295 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_0080_DW_0080 0x48000080 /* *@Address: 0xBE0E0080[0] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: * Automatic adjust the sync polarity (1: enable) */ #define HDMIRX_R_Auto_sync_adjust 0x40400080 /* *@Address: 0xBE0E0080[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Inverse Input Hsync polarity */ #define HDMIRX_R_InverseHsync 0x40400081 /* *@Address: 0xBE0E0080[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Inverse Input Vsync polarity */ #define HDMIRX_R_InverseVsync 0x40400082 /* *@Address: 0xBE0E0084[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0084_DW_0084 0x48000084 /* *@Address: 0xBE0E0084[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * Input Hsync polarity */ #define HDMIRX_R_Hsync_Polarity 0x40400084 /* *@Address: 0xBE0E0084[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * Input Vsync polarity */ #define HDMIRX_R_Vsync_Polarity 0x40400085 /* *@Address: 0xBE0E0084[19:16] *@Range: 0~15 *@Default: *@Access: R *@Description: * HDMI quality */ #define HDMIRX_R_quality 0x41000086 /* *@Address: 0xBE0E0084[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * Generated control output signal ready */ #define HDMIRX_R_out_ready 0x40400087 /* *@Address: 0xBE0E0088[31:0] *@Range: 0~4294967295 *@Default: 0x8010001 *@Access: R/W *@Description: None */ #define HDMIRX_0088_DW_0088 0x48000088 /* *@Address: 0xBE0E0088[1:0] *@Range: 0~3 *@Default: 0x1 *@Access: R/W *@Description: * Preamble can allow how many errors */ #define HDMIRX_R_ROBUST_TH 0x40800088 /* *@Address: 0xBE0E0088[17:8] *@Range: 0~1023 *@Default: 0x10 *@Access: R/W *@Description: * Threshold of detecting hsync polarity */ #define HDMIRX_R_HSYNC_POL_TH 0x42880088 /* *@Address: 0xBE0E0088[28:24] *@Range: 0~31 *@Default: 0x8 *@Access: R/W *@Description: * Threshold of detecting vsync polarity */ #define HDMIRX_R_VSYNC_POL_TH 0x4140008B /* *@Address: 0xBE0E008C[31:0] *@Range: 0~4294967295 *@Default: 0x10300 *@Access: R/W *@Description: None */ #define HDMIRX_008C_DW_008C 0x4800008C /* *@Address: 0xBE0E008C[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Enable video mute (1: enable) */ #define HDMIRX_R_VIDEO_MUTE 0x4040008C /* *@Address: 0xBE0E008C[11:8] *@Range: 0~15 *@Default: 0x3 *@Access: R/W *@Description: * The level of the DE generation function */ #define HDMIRX_R_LEVEL 0x4100008D /* *@Address: 0xBE0E008C[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: * Enable pixel repetition (1: enable) */ #define HDMIRX_R_PR_EN 0x4040008E /* *@Address: 0xBE0E0090[31:0] *@Range: 0~4294967295 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_0090_DW_0090 0x48000090 /* *@Address: 0xBE0E0090[0] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: * Upsampling use interpolation method */ #define HDMIRX_R_interpolation_en 0x40400090 /* *@Address: 0xBE0E00AC[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_00AC_DW_00AC 0x480000AC /* *@Address: 0xBE0E00AC[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Byte Swap audio nonlinear parsing output data */ #define HDMIRX_R_byte_swap 0x404000AE /* *@Address: 0xBE0E00AC[24] *@Range: 0~1 *@Default: 0x0 *@Access: W *@Description: * Clear HDMI quality register (write 1 clear) */ #define HDMIRX_Clr_quality 0x404000AF /* *@Address: 0xBE0E00B0[31:0] *@Range: 0~4294967295 *@Default: 0x1000000 *@Access: R/W *@Description: None */ #define HDMIRX_00B0_DW_00B0 0x480000B0 /* *@Address: 0xBE0E00B0[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * Interlace mode */ #define HDMIRX_R_Interlace 0x404000B0 /* *@Address: 0xBE0E00B0[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Set Polarity of FIELD output */ #define HDMIRX_R_FIELD_POL 0x404000B1 /* *@Address: 0xBE0E00B0[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * Audio layout status */ #define HDMIRX_R_layout 0x404000B2 /* *@Address: 0xBE0E00B0[27:24] *@Range: 0~15 *@Default: 0x1 *@Access: R/W *@Description: * Audio channel status unlock detect threshold */ #define HDMIRX_R_unlock_th 0x410000B3 /* *@Address: 0xBE0E00B4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00B4_DW_00B4 0x480000B4 /* *@Address: 0xBE0E00B4[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Horizontal Total */ #define HDMIRX_R_HT 0x434000B4 /* *@Address: 0xBE0E00B4[28:16] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Horizontal Data Enable Start */ #define HDMIRX_R_HDES 0x435000B4 /* *@Address: 0xBE0E00B8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00B8_DW_00B8 0x480000B8 /* *@Address: 0xBE0E00B8[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Horizontal Data Enable End */ #define HDMIRX_R_HDEE 0x434000B8 /* *@Address: 0xBE0E00B8[28:16] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Odd Field Vertical Data Enable Start */ #define HDMIRX_R_TOP_VDES 0x435000B8 /* *@Address: 0xBE0E00BC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00BC_DW_00BC 0x480000BC /* *@Address: 0xBE0E00BC[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Odd Field Vertical Data Enable End */ #define HDMIRX_R_TOP_VDEE 0x434000BC /* *@Address: 0xBE0E00BC[28:16] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Even Field Vertical Data Enable Start */ #define HDMIRX_R_BTM_VDES 0x435000BC /* *@Address: 0xBE0E00C0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00C0_DW_00C0 0x480000C0 /* *@Address: 0xBE0E00C0[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Even Field Data Enable End */ #define HDMIRX_R_BTM_VDEE 0x434000C0 /* *@Address: 0xBE0E00C0[28:16] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Odd Field Vertical Total */ #define HDMIRX_R_TOP_VT 0x435000C0 /* *@Address: 0xBE0E00C4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_00C4_DW_00C4 0x480000C4 /* *@Address: 0xBE0E00C4[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Even Field Vertical Total */ #define HDMIRX_R_BTM_VT 0x434000C4 /* *@Address: 0xBE0E00C4[16] *@Range: 0~1 *@Default: *@Access: W *@Description: None */ #define HDMIRX_R_BTM_PROG 0x404000C6 /* *@Address: 0xBE0E00C4[24] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Enable down sampling (YCC 4:4:4 -> YCC 4:2:2) */ #define HDMIRX_R_DnSAMPLING_EN 0x404000C7 /* *@Address: 0xBE0E00C8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00C8_DW_00C8 0x480000C8 /* *@Address: 0xBE0E00C8[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * Horizontal Total ready */ #define HDMIRX_R_HT_ready 0x404000C8 /* *@Address: 0xBE0E00C8[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * Horizontal Data Enable Start ready */ #define HDMIRX_R_HDES_ready 0x404000C9 /* *@Address: 0xBE0E00C8[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * Horizontal Data Enable End ready */ #define HDMIRX_R_HDEE_ready 0x404000CA /* *@Address: 0xBE0E00C8[24] *@Range: 0~1 *@Default: *@Access: R *@Description: None */ #define HDMIRX_R_interlace_ready 0x404000CB /* *@Address: 0xBE0E00CC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00CC_DW_00CC 0x480000CC /* *@Address: 0xBE0E00CC[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * Odd Field Vertical Data Enable Start ready */ #define HDMIRX_R_TOP_VDES_ready 0x404000CC /* *@Address: 0xBE0E00CC[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * Odd Field Vertical Data Enable End ready */ #define HDMIRX_R_TOP_VDEE_ready 0x404000CD /* *@Address: 0xBE0E00CC[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * Even Field Vertical Data Enable Start ready */ #define HDMIRX_R_BTM_VDES_ready 0x404000CE /* *@Address: 0xBE0E00CC[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * Even Field Vertical Data Enable End ready */ #define HDMIRX_R_BTM_VDEE_ready 0x404000CF /* *@Address: 0xBE0E00D0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00D0_DW_00D0 0x480000D0 /* *@Address: 0xBE0E00D0[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * Odd Field Vertical Total ready */ #define HDMIRX_R_TOP_VT_ready 0x404000D0 /* *@Address: 0xBE0E00D0[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * Even Field Vertical Total ready */ #define HDMIRX_R_BTM_VT_ready 0x404000D1 /* *@Address: 0xBE0E00D0[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: * Horizontal sync pulse width (useless) */ #define HDMIRX_R_hsync_width 0x420000D2 /* *@Address: 0xBE0E00D0[31:24] *@Range: 0~255 *@Default: *@Access: R *@Description: * Vertical sync pulse width (useless) */ #define HDMIRX_R_vsync_width 0x420000D3 /* *@Address: 0xBE0E00D4[31:0] *@Range: 0~4294967295 *@Default: 0x1010000 *@Access: R/W *@Description: None */ #define HDMIRX_00D4_DW_00D4 0x480000D4 /* *@Address: 0xBE0E00D4[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * use fixed version of hsync/vsync to detect video information */ #define HDMIRX_R_det_fix 0x404000D4 /* *@Address: 0xBE0E00D4[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_sw_hdcp_rst_en 0x404000D5 /* *@Address: 0xBE0E00D4[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_sw_hdcp_rstn 0x404000D6 /* *@Address: 0xBE0E00D4[24] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_hpd_low_nocon 0x404000D7 /* *@Address: 0xBE0E00D8[31:0] *@Range: 0~4294967295 *@Default: 0x10001 *@Access: R/W *@Description: None */ #define HDMIRX_00D8_DW_00D8 0x480000D8 /* *@Address: 0xBE0E00D8[0] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_AVMUTE_blk_screen 0x404000D8 /* *@Address: 0xBE0E00D8[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_sync_duty_det 0x404000D9 /* *@Address: 0xBE0E00D8[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_keep_aksv 0x404000DA /* *@Address: 0xBE0E00D8[24] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_force_blk_screen 0x404000DB /* *@Address: 0xBE0E00DC[31:0] *@Range: 0~4294967295 *@Default: 0x10100 *@Access: R/W *@Description: None */ #define HDMIRX_00DC_DW_00DC 0x480000DC /* *@Address: 0xBE0E00DC[1:0] *@Range: 0~3 *@Default: *@Access: R *@Description: * Deep Color Mode debug for gcp command. */ #define HDMIRX_dcm 0x408000DC /* *@Address: 0xBE0E00DC[8] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_LATCH_GCP_CD 0x404000DD /* *@Address: 0xBE0E00DC[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_DEGEN_by_valid 0x404000DE /* *@Address: 0xBE0E00DC[24] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 0: timeout_mclk, 1: timeout_sclk */ #define HDMIRX_R_dis_timeout_mux 0x404000DF /* *@Address: 0xBE0E00E0[31:0] *@Range: 0~4294967295 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_00E0_DW_00E0 0x480000E0 /* *@Address: 0xBE0E00E0[0] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_auto_blk_msb 0x404000E0 /* *@Address: 0xBE0E00E0[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_R_blk_msb 0x404000E1 /* *@Address: 0xBE0E00E0[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_G_blk_msb 0x404000E2 /* *@Address: 0xBE0E00E0[24] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_B_blk_msb 0x404000E3 /* *@Address: 0xBE0E00E4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00E4_DW_00E4 0x480000E4 /* *@Address: 0xBE0E00E4[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Top field vertical vsync start */ #define HDMIRX_R_TOP_VsyncS 0x434000E4 /* *@Address: 0xBE0E00E4[28:16] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Bottom field vertical vsycn start */ #define HDMIRX_R_BOT_VsyncS 0x435000E4 /* *@Address: 0xBE0E00E8[31:0] *@Range: 0~4294967295 *@Default: 0x10001 *@Access: R/W *@Description: None */ #define HDMIRX_00E8_DW_00E8 0x480000E8 /* *@Address: 0xBE0E00E8[0] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: * Use default phase when gcp_cd=0, default_phase=1 */ #define HDMIRX_R_default_phase_no_cd 0x404000E8 /* *@Address: 0xBE0E00E8[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Use default phase when default_phase=1 */ #define HDMIRX_R_default_phase_first 0x404000E9 /* *@Address: 0xBE0E00E8[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_bubble_out 0x404000EA /* *@Address: 0xBE0E00E8[24] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 0: 1/2 Htotal, 1: 1/4 Htotal */ #define HDMIRX_R_half_quarter_HT 0x404000EB /* *@Address: 0xBE0E00EC[31:0] *@Range: 0~4294967295 *@Default: 0x10000 *@Access: R/W *@Description: None */ #define HDMIRX_00EC_DW_00EC 0x480000EC /* *@Address: 0xBE0E00EC[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_dither_en 0x404000EC /* *@Address: 0xBE0E00EC[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_dither_depth 0x404000ED /* *@Address: 0xBE0E00EC[21:16] *@Range: 0~63 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_frame_seed 0x418000EE /* *@Address: 0xBE0E00EC[24] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_dither2_en 0x404000EF /* *@Address: 0xBE0E00F0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_00F0_DW_00F0 0x480000F0 /* *@Address: 0xBE0E00F0[9:0] *@Range: 0~1023 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_ref_length 0x428000F0 /* *@Address: 0xBE0E00F0[25:16] *@Range: 0~1023 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_freq_tolerate 0x429000F0 /* *@Address: 0xBE0E00F4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_00F4_DW_00F4 0x480000F4 /* *@Address: 0xBE0E00F4[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_freq_tolerance_abs 0x404000F4 /* *@Address: 0xBE0E00FC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_00FC_DW_00FC 0x480000FC /* *@Address: 0xBE0E00FC[2:0] *@Range: 0~7 *@Default: *@Access: R *@Description: None */ #define HDMIRX_fifo_write_state 0x40C000FC /* *@Address: 0xBE0E00FC[12:8] *@Range: 0~31 *@Default: *@Access: R *@Description: None */ #define HDMIRX_fifo_read_state 0x414000FD /* *@Address: 0xBE0E00FC[18:16] *@Range: 0~7 *@Default: *@Access: R *@Description: None */ #define HDMIRX_as_rptr_3 0x40C000FE /* *@Address: 0xBE0E00FC[31:24] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_dma_state 0x420000FF /* *@Address: 0xBE0E0100[31:0] *@Range: 0~4294967295 *@Default: 0xc0800 *@Access: R/W *@Description: None */ #define HDMIRX_0100_DW_0100 0x48000100 /* *@Address: 0xBE0E0100[6:0] *@Range: 0~127 *@Default: *@Access: R *@Description: * HDCP ready key mmio address */ #define HDMIRX_mmio_raddr 0x41C00100 /* *@Address: 0xBE0E0100[15:8] *@Range: 0~255 *@Default: 0x8 *@Access: R/W *@Description: * Clear mute timer. (refer to 108[16] = HDMIRX_0042[16]) */ #define HDMIRX_R_Clear_mute_timer 0x42000101 /* *@Address: 0xBE0E0100[23:16] *@Range: 0~255 *@Default: 0xc *@Access: R/W *@Description: * I2C slave clock divider factor */ #define HDMIRX_R_CLK_DIV 0x42000102 /* *@Address: 0xBE0E0100[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * HDCP BKSV ready */ #define HDMIRX_R_BKSYRdy 0x40400103 /* *@Address: 0xBE0E0104[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0104_DW_0104 0x48000104 /* *@Address: 0xBE0E0104[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: * HDCP ready key mmio data (KSV / KEY) */ #define HDMIRX_mmio_rdata 0x48000104 /* *@Address: 0xBE0E0108[31:0] *@Range: 0~4294967295 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_0108_DW_0108 0x48000108 /* *@Address: 0xBE0E0108[0] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: None */ #define HDMIRX_R_subpacket_identical_en 0x40400108 /* *@Address: 0xBE0E0108[8] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_bch_opt 0x40400109 /* *@Address: 0xBE0E0108[16] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * 1: soft clear AV mute. */ #define HDMIRX_Soft_Clear_Mute 0x4040010A /* *@Address: 0xBE0E0108[24] *@Range: 0~1 *@Default: *@Access: R *@Description: None */ #define HDMIRX_R_AV_Mute 0x4040010B /* *@Address: 0xBE0E010C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_010C_DW_010C 0x4800010C /* *@Address: 0xBE0E010C[19:0] *@Range: 0~1048575 *@Default: *@Access: R *@Description: * Audio Clock Regeneration factor (CTS) */ #define HDMIRX_R_ACR_CTS 0x4500010C /* *@Address: 0xBE0E0110[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0110_DW_0110 0x48000110 /* *@Address: 0xBE0E0110[19:0] *@Range: 0~1048575 *@Default: *@Access: R *@Description: * Audio Clock Regeneration factor (N) */ #define HDMIRX_R_ACR_N 0x45000110 /* *@Address: 0xBE0E0114[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0114_DW_0114 0x48000114 /* *@Address: 0xBE0E0114[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * Audio FIFO Full */ #define HDMIRX_R_fifo_full 0x40400114 /* *@Address: 0xBE0E0114[10:8] *@Range: 0~7 *@Default: *@Access: R *@Description: * Audio FIFO write pointer */ #define HDMIRX_R_wptr 0x40C00115 /* *@Address: 0xBE0E0114[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * Audio FIFO empty */ #define HDMIRX_R_fifo_empty 0x40400116 /* *@Address: 0xBE0E0114[26:24] *@Range: 0~7 *@Default: *@Access: R *@Description: * Audio FIFO read pointer */ #define HDMIRX_R_rptr 0x40C00117 /* *@Address: 0xBE0E0118[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0118_DW_0118 0x48000118 /* *@Address: 0xBE0E0118[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_burst_spacing 0x40400118 /* *@Address: 0xBE0E0118[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_parsing_bypass 0x40400119 /* *@Address: 0xBE0E0118[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * Audio Sample exist(write 1, clear) */ #define HDMIRX_AS_exist 0x4040011A /* *@Address: 0xBE0E0118[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * High-Bit_Rage Audio Sample exist (write 1, clear) */ #define HDMIRX_HBRAS_exist 0x4040011B /* *@Address: 0xBE0E011C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_011C_DW_011C 0x4800011C /* *@Address: 0xBE0E011C[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * Audio Channel Status */ #define HDMIRX_R_ACS_CSts 0x4200011C /* *@Address: 0xBE0E011C[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: * Audio Channel Status Category Code */ #define HDMIRX_R_ACS_CatC 0x4200011D /* *@Address: 0xBE0E011C[19:16] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio Channel Status Source Number */ #define HDMIRX_R_ACS_Snum 0x4100011E /* *@Address: 0xBE0E011C[27:24] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio Channel Status Channel Number */ #define HDMIRX_R_ACS_Cnum 0x4100011F /* *@Address: 0xBE0E0120[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0120_DW_0120 0x48000120 /* *@Address: 0xBE0E0120[3:0] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio Channel Status Sample Frequency */ #define HDMIRX_R_ACS_Sfeq 0x41000120 /* *@Address: 0xBE0E0120[11:8] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio Channel Status Clock Accuracy */ #define HDMIRX_R_ACS_Cacc 0x41000121 /* *@Address: 0xBE0E0120[19:16] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio Channel Status Word Length */ #define HDMIRX_R_ACS_Wlen 0x41000122 /* *@Address: 0xBE0E0120[27:24] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio Channel Status Original Sample */ #define HDMIRX_R_ACS_OSFeq 0x41000123 /* *@Address: 0xBE0E0124[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0124_DW_0124 0x48000124 /* *@Address: 0xBE0E0124[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: * Audio discontinuous timeout */ #define HDMIRX_R_disc_tout 0x48000124 /* *@Address: 0xBE0E0128[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0128_DW_0128 0x48000128 /* *@Address: 0xBE0E0128[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * Audio InfoFrame Version */ #define HDMIRX_R_Ado_Ver 0x42000128 /* *@Address: 0xBE0E0128[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: * Audio InforFrame Channel/Speaker Allocation */ #define HDMIRX_R_Ado_CA 0x42000129 /* *@Address: 0xBE0E0128[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: * Audio InfoFrame Data Byte3 value */ #define HDMIRX_R_Ado_DB3 0x4200012A /* *@Address: 0xBE0E0128[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * Audio InfoFrame Sample Frequency */ #define HDMIRX_R_Ado_DMInh 0x4040012B /* *@Address: 0xBE0E012C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_012C_DW_012C 0x4800012C /* *@Address: 0xBE0E012C[3:0] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio InfoFrame Coding Type */ #define HDMIRX_R_Ado_CT 0x4100012C /* *@Address: 0xBE0E012C[11:8] *@Range: 0~15 *@Default: *@Access: R *@Description: * Audio InfoFrame Level Shift Value */ #define HDMIRX_R_Ado_LSV 0x4100012D /* *@Address: 0xBE0E012C[18:16] *@Range: 0~7 *@Default: *@Access: R *@Description: * Audio InfoFrame Channel Count (0: refer to stream 1: 2ch 2:3ch ¡K) */ #define HDMIRX_R_Ado_CC 0x40C0012E /* *@Address: 0xBE0E012C[26:24] *@Range: 0~7 *@Default: *@Access: R *@Description: * Audio InfoFrame Sample Frequency */ #define HDMIRX_R_Ado_SF 0x40C0012F /* *@Address: 0xBE0E0130[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0130_DW_0130 0x48000130 /* *@Address: 0xBE0E0130[1:0] *@Range: 0~3 *@Default: *@Access: R *@Description: * Audio InfoFrame Sample Size */ #define HDMIRX_R_Ado_SS 0x40800130 /* *@Address: 0xBE0E0134[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0134_DW_0134 0x48000134 /* *@Address: 0xBE0E0134[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * AVI InfoFrame version */ #define HDMIRX_R_AVI_Ver 0x42000134 /* *@Address: 0xBE0E0134[11:8] *@Range: 0~15 *@Default: *@Access: R *@Description: * AVI InfoFrame Active Format Aspect Ratio */ #define HDMIRX_R_AVI_R 0x41000135 /* *@Address: 0xBE0E0134[19:16] *@Range: 0~15 *@Default: *@Access: R *@Description: * AVI InfoFrame Pixel Repetition factor */ #define HDMIRX_R_AVI_PR 0x41000136 /* *@Address: 0xBE0E0134[30:24] *@Range: 0~127 *@Default: *@Access: R *@Description: * AVI InforFrame Video Format ID code */ #define HDMIRX_R_AVI_VIC 0x41C00137 /* *@Address: 0xBE0E0138[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0138_DW_0138 0x48000138 /* *@Address: 0xBE0E0138[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * AVI InfoFrame information present */ #define HDMIRX_R_AVI_A 0x40400138 /* *@Address: 0xBE0E0138[9:8] *@Range: 0~3 *@Default: *@Access: R *@Description: * AVI InfoFrame Non-uniform Picture Scaling */ #define HDMIRX_R_AVI_SC 0x40800139 /* *@Address: 0xBE0E0138[17:16] *@Range: 0~3 *@Default: *@Access: R *@Description: * AVI InfoFrame RGB and YCbCr indicator (0: RGB 1: YCC422 2: YCC444 ) */ #define HDMIRX_R_AVI_Y 0x4080013A /* *@Address: 0xBE0E0138[25:24] *@Range: 0~3 *@Default: *@Access: R *@Description: * AVI InfoFrame Bar Infomation */ #define HDMIRX_R_AVI_B 0x4080013B /* *@Address: 0xBE0E013C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_013C_DW_013C 0x4800013C /* *@Address: 0xBE0E013C[1:0] *@Range: 0~3 *@Default: *@Access: R *@Description: * AVI InfoFrame Scan Information */ #define HDMIRX_R_AVI_S 0x4080013C /* *@Address: 0xBE0E013C[9:8] *@Range: 0~3 *@Default: *@Access: R *@Description: * AVI InfoFrame Colorimetry (0: no data 1: BT601 2:BT709) */ #define HDMIRX_R_AVI_C 0x4080013D /* *@Address: 0xBE0E013C[17:16] *@Range: 0~3 *@Default: *@Access: R *@Description: * AVI InfoFrame Picture Aspect Ratio */ #define HDMIRX_R_AVI_M 0x4080013E /* *@Address: 0xBE0E0140[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0140_DW_0140 0x48000140 /* *@Address: 0xBE0E0140[15:0] *@Range: 0~65535 *@Default: *@Access: R *@Description: * AVI InfoFrame Start Line number */ #define HDMIRX_R_AVI_SLN 0x44000140 /* *@Address: 0xBE0E0140[31:16] *@Range: 0~65535 *@Default: *@Access: R *@Description: * AVI InfoFrame End Line number */ #define HDMIRX_R_AVI_ELN 0x44100140 /* *@Address: 0xBE0E0144[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0144_DW_0144 0x48000144 /* *@Address: 0xBE0E0144[15:0] *@Range: 0~65535 *@Default: *@Access: R *@Description: * AVI InfoFrame Start Pixel Number */ #define HDMIRX_R_AVI_SPN 0x44000144 /* *@Address: 0xBE0E0144[31:16] *@Range: 0~65535 *@Default: *@Access: R *@Description: * AVI InfoFrame End Pixel Number */ #define HDMIRX_R_AVI_EPN 0x44100144 /* *@Address: 0xBE0E0148[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0148_DW_0148 0x48000148 /* *@Address: 0xBE0E0148[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * MPEG Source InfoFrame Version */ #define HDMIRX_R_MS_Ver 0x42000148 /* *@Address: 0xBE0E0148[9:8] *@Range: 0~3 *@Default: *@Access: R *@Description: * MPEG Source InfoFrame MPEG Frame */ #define HDMIRX_R_MS_MF 0x40800149 /* *@Address: 0xBE0E0148[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * MPEG Source InfoFrame Field Repeat */ #define HDMIRX_R_MS_FR 0x4040014A /* *@Address: 0xBE0E014C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_014C_DW_014C 0x4800014C /* *@Address: 0xBE0E014C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * MPEG Source InfoFrame MB 0~3 */ #define HDMIRX_R_MS_MB 0x4800014C /* *@Address: 0xBE0E0150[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0150_DW_0150 0x48000150 /* *@Address: 0xBE0E0150[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * SPD InfoFrame Version */ #define HDMIRX_R_SPD_Ver 0x42000150 /* *@Address: 0xBE0E0150[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: * SPD InfoFrame Source Device Information */ #define HDMIRX_R_SPD_SDI 0x42000151 /* *@Address: 0xBE0E0154[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0154_DW_0154 0x48000154 /* *@Address: 0xBE0E0154[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * SPD InfoFrame Vender Name Character 1~4 */ #define HDMIRX_R_SPD_VN_31_0_ 0x48000154 /* *@Address: 0xBE0E0158[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0158_DW_0158 0x48000158 /* *@Address: 0xBE0E0158[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * SPD InfoFrame Vender Name Character 5~8 */ #define HDMIRX_R_SPD_VN_63_32_ 0x48000158 /* *@Address: 0xBE0E015C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_015C_DW_015C 0x4800015C /* *@Address: 0xBE0E015C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * SPD InfoFrame Product Description Character 1~4 */ #define HDMIRX_R_SPD_PD_31_0_ 0x4800015C /* *@Address: 0xBE0E0160[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0160_DW_0160 0x48000160 /* *@Address: 0xBE0E0160[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * SPD InfoFrame Product Description Character 5~8 */ #define HDMIRX_R_SPD_PD_63_32_ 0x48000160 /* *@Address: 0xBE0E0164[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0164_DW_0164 0x48000164 /* *@Address: 0xBE0E0164[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * SPD InfoFrame Product Description Character 9~12 */ #define HDMIRX_R_SPD_PD_95_64_ 0x48000164 /* *@Address: 0xBE0E0168[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0168_DW_0168 0x48000168 /* *@Address: 0xBE0E0168[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * SPD InfoFrame Product Description Character 13~16 */ #define HDMIRX_R_SPD_PD_127_96_ 0x48000168 /* *@Address: 0xBE0E016C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_016C_DW_016C 0x4800016C /* *@Address: 0xBE0E016C[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * Audio Content Protect Packet Type */ #define HDMIRX_R_ACP_Type 0x4200016C /* *@Address: 0xBE0E0170[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0170_DW_0170 0x48000170 /* *@Address: 0xBE0E0170[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * Audio Content Protect Packet 1~4 */ #define HDMIRX_R_ACP_PB_31_0_ 0x48000170 /* *@Address: 0xBE0E0174[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0174_DW_0174 0x48000174 /* *@Address: 0xBE0E0174[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * Audio Content Protect Packet 5~8 */ #define HDMIRX_R_ACP_PB_63_32_ 0x48000174 /* *@Address: 0xBE0E0178[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0178_DW_0178 0x48000178 /* *@Address: 0xBE0E0178[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * Audio Content Protect Packet 9~12 */ #define HDMIRX_R_ACP_PB_95_64_ 0x48000178 /* *@Address: 0xBE0E017C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_017C_DW_017C 0x4800017C /* *@Address: 0xBE0E017C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * Audio Content Protect Packet 13~16 */ #define HDMIRX_R_ACP_PB_127_96_ 0x4800017C /* *@Address: 0xBE0E0180[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R *@Description: None */ #define HDMIRX_0180_DW_0180 0x48000180 /* *@Address: 0xBE0E0180[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R *@Description: * Audio Content Protect Packet 17~20 */ #define HDMIRX_R_ACP_PB_159_128_ 0x48000180 /* *@Address: 0xBE0E0184[31:0] *@Range: 0~4294967295 *@Default: 0X0 *@Access: R *@Description: None */ #define HDMIRX_0184_DW_0184 0x48000184 /* *@Address: 0xBE0E0184[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R *@Description: * Audio Content Protect Packet 21~24 */ #define HDMIRX_R_ACP_PB_191_160_ 0x48000184 /* *@Address: 0xBE0E0188[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R *@Description: None */ #define HDMIRX_0188_DW_0188 0x48000188 /* *@Address: 0xBE0E0188[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R *@Description: * Audio Content Protect Packet 25~28 */ #define HDMIRX_R_ACP_PB_223_192_ 0x48000188 /* *@Address: 0xBE0E018C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_018C_DW_018C 0x4800018C /* *@Address: 0xBE0E018C[2:0] *@Range: 0~7 *@Default: *@Access: R *@Description: * ISRC1 Packet Status value */ #define HDMIRX_R_ISRC1_Sts 0x40C0018C /* *@Address: 0xBE0E018C[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * ISRC1 Packet Continued value */ #define HDMIRX_R_ISRC1_Cont 0x4040018D /* *@Address: 0xBE0E018C[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * ISRC1 Packet Valid value */ #define HDMIRX_R_ISRC1_Vld 0x4040018E /* *@Address: 0xBE0E0190[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0190_DW_0190 0x48000190 /* *@Address: 0xBE0E0190[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 1 Packet Byte 1~4 */ #define HDMIRX_R_ISRC1_PB_31_0_ 0x48000190 /* *@Address: 0xBE0E0194[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0194_DW_0194 0x48000194 /* *@Address: 0xBE0E0194[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 1 Packet Byte 5~8 */ #define HDMIRX_R_ISRC1_PB_63_32_ 0x48000194 /* *@Address: 0xBE0E0198[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0198_DW_0198 0x48000198 /* *@Address: 0xBE0E0198[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 1 Packet Byte 9~12 */ #define HDMIRX_R_ISRC1_PB_95_64_ 0x48000198 /* *@Address: 0xBE0E019C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_019C_DW_019C 0x4800019C /* *@Address: 0xBE0E019C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 1 Packet Byte 13~16 */ #define HDMIRX_R_ISRC1_PB_127_96_ 0x4800019C /* *@Address: 0xBE0E01A0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01A0_DW_01A0 0x480001A0 /* *@Address: 0xBE0E01A0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 2 Packet Byte 1~4 */ #define HDMIRX_R_ISRC2_PB_31_0_ 0x480001A0 /* *@Address: 0xBE0E01A4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01A4_DW_01A4 0x480001A4 /* *@Address: 0xBE0E01A4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 2 Packet Byte 5~8 */ #define HDMIRX_R_ISRC2_PB_63_32_ 0x480001A4 /* *@Address: 0xBE0E01A8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01A8_DW_01A8 0x480001A8 /* *@Address: 0xBE0E01A8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 2 Packet Byte 9~12 */ #define HDMIRX_R_ISRC2_PB_95_64_ 0x480001A8 /* *@Address: 0xBE0E01AC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01AC_DW_01AC 0x480001AC /* *@Address: 0xBE0E01AC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * ISRC 2 Packet Byte 13~16 */ #define HDMIRX_R_ISRC2_PB_127_96_ 0x480001AC /* *@Address: 0xBE0E01B0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_01B0_DW_01B0 0x480001B0 /* *@Address: 0xBE0E01B0[0] *@Range: 0~1 *@Default: *@Access: W *@Description: * Clear bch error counter (write 1 clear) */ #define HDMIRX_Clr_bch_epcnt 0x404001B0 /* *@Address: 0xBE0E01B0[11:8] *@Range: 0~15 *@Default: *@Access: R *@Description: * Buffer change counter */ #define HDMIRX_Buffer_chg_cnt 0x410001B1 /* *@Address: 0xBE0E01B0[16] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_dma_safe_en 0x404001B2 /* *@Address: 0xBE0E01B4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_01B4_DW_01B4 0x480001B4 /* *@Address: 0xBE0E01B4[23:0] *@Range: 0~16777215 *@Default: *@Access: R/W *@Description: * Audio sample write to fifo timeout value */ #define HDMIRX_R_as_w_timeout 0x460001B4 /* *@Address: 0xBE0E01B4[24] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Enable layout detected */ #define HDMIRX_R_layout_detect 0x404001B7 /* *@Address: 0xBE0E01B8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_01B8_DW_01B8 0x480001B8 /* *@Address: 0xBE0E01B8[4:0] *@Range: 0~31 *@Default: *@Access: R *@Description: * Nonlinear Audio Sample Type */ #define HDMIRX_R_sp_non_linear_type 0x414001B8 /* *@Address: 0xBE0E01B8[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Memory auto-precharge enable */ #define HDMIRX_R_mem_ap_en 0x404001B9 /* *@Address: 0xBE0E01B8[17:16] *@Range: 0~3 *@Default: *@Access: R/W *@Description: * Memory write burst mode ( 0: 128-bit 1: 256-bit 2/3: 512-bit ) */ #define HDMIRX_R_as_mem_mode 0x408001BA /* *@Address: 0xBE0E01B8[27:24] *@Range: 0~15 *@Default: *@Access: R/W *@Description: * Detect layout miss threshold */ #define HDMIRX_R_layout_th 0x410001BB /* *@Address: 0xBE0E01BC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_01BC_DW_01BC 0x480001BC /* *@Address: 0xBE0E01BC[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_HBRAS_sel 0x404001BC /* *@Address: 0xBE0E01BC[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Enable nonlinear audio parsing mode */ #define HDMIRX_R_parsing_en 0x404001BD /* *@Address: 0xBE0E01BC[16] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Enable DMA function */ #define HDMIRX_R_dma_w_enable 0x404001BE /* *@Address: 0xBE0E01BC[24] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Enable Audio function */ #define HDMIRX_R_audio_enable 0x404001BF /* *@Address: 0xBE0E01C0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_01C0_DW_01C0 0x480001C0 /* *@Address: 0xBE0E01C0[30:4] *@Range: 0~134217727 *@Default: *@Access: R/W *@Description: * DMA Start Address [30:4] */ #define HDMIRX_R_dma_start_addr 0x46C401C0 /* *@Address: 0xBE0E01C4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_01C4_DW_01C4 0x480001C4 /* *@Address: 0xBE0E01C4[7:0] *@Range: 0~255 *@Default: *@Access: R/W *@Description: * Write buffer number */ #define HDMIRX_R_wbuf_num 0x420001C4 /* *@Address: 0xBE0E01C4[9:8] *@Range: 0~3 *@Default: *@Access: R/W *@Description: * Set linear audio channel ( 0: 2 channel 1: 5.1 channel 2/3: 7.1 channel ) */ #define HDMIRX_R_rx_ch_set 0x408001C5 /* *@Address: 0xBE0E01C4[31:16] *@Range: 0~65535 *@Default: *@Access: R *@Description: * BCH error count value (refer to 1B0[0] = HDMIRX_006C[0]) */ #define HDMIRX_R_bch_ep_cnt 0x441001C4 /* *@Address: 0xBE0E01C8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01C8_DW_01C8 0x480001C8 /* *@Address: 0xBE0E01C8[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet version */ #define HDMIRX_R_VSI_ver 0x420001C8 /* *@Address: 0xBE0E01C8[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet length */ #define HDMIRX_R_VSI_len 0x420001C9 /* *@Address: 0xBE0E01C8[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet IEEE ID[7:0] */ #define HDMIRX_R_VSI_IEEE_7_0_ 0x420001CA /* *@Address: 0xBE0E01C8[31:24] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet IEEE ID[15:8] */ #define HDMIRX_R_VSI_IEEE_15_8_ 0x420001CB /* *@Address: 0xBE0E01CC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01CC_DW_01CC 0x480001CC /* *@Address: 0xBE0E01CC[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet IEEE ID[23:16] */ #define HDMIRX_R_VSI_IEEE_23_16_ 0x420001CC /* *@Address: 0xBE0E01CC[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[7:0] */ #define HDMIRX_R_VSI_PB_7_0_ 0x420001CD /* *@Address: 0xBE0E01CC[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[15:8] */ #define HDMIRX_R_VSI_PB_15_8_ 0x420001CE /* *@Address: 0xBE0E01CC[31:24] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[23:16] */ #define HDMIRX_R_VSI_PB_23_16_ 0x420001CF /* *@Address: 0xBE0E01D0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01D0_DW_01D0 0x480001D0 /* *@Address: 0xBE0E01D0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[55:24] */ #define HDMIRX_R_VSI_PB_55_24_ 0x480001D0 /* *@Address: 0xBE0E01D4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01D4_DW_01D4 0x480001D4 /* *@Address: 0xBE0E01D4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[87:56] */ #define HDMIRX_R_VSI_PB_87_56_ 0x480001D4 /* *@Address: 0xBE0E01D8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01D8_DW_01D8 0x480001D8 /* *@Address: 0xBE0E01D8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[119:88] */ #define HDMIRX_R_VSI_PB_119_88_ 0x480001D8 /* *@Address: 0xBE0E01DC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01DC_DW_01DC 0x480001DC /* *@Address: 0xBE0E01DC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[151:120] */ #define HDMIRX_R_VSI_PB_151_120_ 0x480001DC /* *@Address: 0xBE0E01E0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01E0_DW_01E0 0x480001E0 /* *@Address: 0xBE0E01E0[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[183:152] */ #define HDMIRX_R_VSI_PB_183_152_ 0x480001E0 /* *@Address: 0xBE0E01E4[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01E4_DW_01E4 0x480001E4 /* *@Address: 0xBE0E01E4[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * VSI Packet Data Payload[191:184] */ #define HDMIRX_R_VSI_PB_191_184_ 0x420001E4 /* *@Address: 0xBE0E01E8[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01E8_DW_01E8 0x480001E8 /* *@Address: 0xBE0E01E8[0] *@Range: 0~1 *@Default: *@Access: R *@Description: None */ #define HDMIRX_AVI_ITC 0x404001E8 /* *@Address: 0xBE0E01E8[10:8] *@Range: 0~7 *@Default: *@Access: R *@Description: None */ #define HDMIRX_AVI_EC 0x40C001E9 /* *@Address: 0xBE0E01E8[17:16] *@Range: 0~3 *@Default: *@Access: R *@Description: None */ #define HDMIRX_AVI_Q 0x408001EA /* *@Address: 0xBE0E01EC[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_01EC_DW_01EC 0x480001EC /* *@Address: 0xBE0E01EC[3:0] *@Range: 0~15 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GCP_CD 0x410001EC /* *@Address: 0xBE0E01EC[11:8] *@Range: 0~15 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GCP_PP 0x410001ED /* *@Address: 0xBE0E01EC[16] *@Range: 0~1 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GCP_Default_Phase 0x404001EE /* *@Address: 0xBE0E0200[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define R_INTR_en_DW_0200 0x48000200 /* *@Address: 0xBE0E0200[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: * Interrupt : * [0] : AVI InfoFrame * [1] : ACP InfoFrame * [2] : Audio InfoFrame * [3] : ISRC 1 packet * [4] : ISRC 2 packet * [5] : SPD InfoFrame * [6] : MPEG Source InfoFrame * [7] : AV Mute * [8] : Clear AV Mute * [9] : Buffer Change Pulse * [10] : Audio channel status lock pulse * [11] : Audio channel status unlock pulse * [12] : HDMI video inactive -> active * [13] : HDMI video active -> inactive * [14] : VSI packet * [15] : audio layout change * [16] : HDCP key request * [17] : HDMI enable * [18] : DVI enable * [19] : audio sample coming * [20] : HBR audio sample coming * [21] : * [22] : deep color mode change * [23] : hdcp_try_intr * [24] : GamutBoundaryData * [25] : mode change * [26] : PLLLOCK * [27] : ctrl first pulse (one channel symbol lock) * [28] : phy PLL rstj int * [29] : phy in range int * [30] : phy CDR RSTJ int * [31] : phy PLL lock int */ #define HDMIRX_R_INTR_en 0x48000200 /* *@Address: 0xBE0E0204[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define R_INTR_Status_DW_0204 0x48000204 /* *@Address: 0xBE0E0204[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: * Interrupt : (write 1 clear) * [0] : AVI InfoFrame * [1] : ACP InfoFrame * [2] : Audio InfoFrame * [3] : ISRC 1 packet * [4] : ISRC 2 packet * [5] : SPD InfoFrame * [6] : MPEG Source InfoFrame * [7] : AV Mute * [8] : Clear AV Mute * [9] : Buffer Change Pulse * [10] : Audio channel status lock pulse * [11] : Audio channel status unlock pulse * [12] : HDMI video inactive -> active * [13] : HDMI video active -> inactive * [14] : VSI packet * [15] : audio layout change * [16] : HDCP key request * [17] : HDMI enable * [18] : DVI enable * [19] : audio sample coming * [20] : HBR audio sample coming * [21] : * [22] : deep color mode change * [23] : hdcp_try_intr * [24] : GamutBoundaryData * [25] : mode change * [26] : PLLLOCK * [27] : ctrl first pulse (one channel symbol lock) * [28] : phy PLL rstj int * [29] : phy in range int * [30] : phy CDR RSTJ int * [31] : phy PLL lock int * * The level of HDMI going to active : * 0 : DE stable 1 : HSYNC stable 2 : VSYNC stable 3 : FRAME stable */ #define HDMIRX_R_INTR_Status 0x48000204 /* *@Address: 0xBE0E0208[31:0] *@Range: 0~4294967295 *@Default: 0x1ff00 *@Access: R/W *@Description: None */ #define HDMIRX_0208_DW_0208 0x48000208 /* *@Address: 0xBE0E0208[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * Audio sample overflow counter */ #define HDMIRX_R_overflow_cnt 0x42000208 /* *@Address: 0xBE0E0208[15:8] *@Range: 0~255 *@Default: 0xff *@Access: R/W *@Description: * Clear ACP timer (600 ms) */ #define HDMIRX_R_clear_ACP_timer 0x42000209 /* *@Address: 0xBE0E0208[16] *@Range: 0~1 *@Default: 0x1 *@Access: R/W *@Description: * Sub-packet identical enable for ACR */ #define HDMIRX_R_subpacket_identical_en2 0x4040020A /* *@Address: 0xBE0E0208[24] *@Range: 0~1 *@Default: *@Access: W *@Description: * Software clear ACP */ #define HDMIRX_Soft_Clear_ACP 0x4040020B /* *@Address: 0xBE0E020C[31:0] *@Range: 0~4294967295 *@Default: 0x14ff0000 *@Access: R/W *@Description: None */ #define HDMIRX_020C_DW_020C 0x4800020C /* *@Address: 0xBE0E020C[15:0] *@Range: 0~65535 *@Default: *@Access: R/W *@Description: * HDCP control 2 [15:0] * [0]: feature1.1_tx(Ainfo) */ #define HDMIRX_R_HDCP_CTL2 0x4400020C /* *@Address: 0xBE0E020C[23:16] *@Range: 0~255 *@Default: 0xff *@Access: R/W *@Description: * System clock count[7:0] */ #define HDMIRX_R_system_clk_cnt 0x4200020E /* *@Address: 0xBE0E020C[28:24] *@Range: 0~31 *@Default: 0x14 *@Access: R/W *@Description: * DE_GEN th: [0]:wait h total, [1]:wait v total, [2] wait display range, [3]: wait de(de start and de end), [4]wait interlace */ #define HDMIRX_R_HDMI_level 0x4140020F /* *@Address: 0xBE0E0210[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0210_DW_0210 0x48000210 /* *@Address: 0xBE0E0210[15:0] *@Range: 0~65535 *@Default: *@Access: R/W *@Description: * Pixel clock count[15:0] * Pixel clk frequency = (pixel_rat_cnt / system_clk_cnt) * system clk frequency * (system clock frequency = 24.576MHz) */ #define HDMIRX_R_pixel_rate_cnt 0x44000210 /* *@Address: 0xBE0E0214[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0214_DW_0214 0x48000214 /* *@Address: 0xBE0E0214[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Clear AVI info interrupt and AVI info data */ #define HDMIRX_R_AVIint_clr 0x40400214 /* *@Address: 0xBE0E0214[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Clear audio info interrupt and audio info data */ #define HDMIRX_R_Adoint_clr 0x40400215 /* *@Address: 0xBE0E0214[16] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Clear mepg source info interrupt and mepg source info data */ #define HDMIRX_R_MSIint_clr 0x40400216 /* *@Address: 0xBE0E0214[24] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Clear source product descriptor info interrupt and source product descriptor data */ #define HDMIRX_R_SPDint_clr 0x40400217 /* *@Address: 0xBE0E0218[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0218_DW_0218 0x48000218 /* *@Address: 0xBE0E0218[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: * Clear VS info interrupt and VS info data */ #define HDMIRX_R_VSIint_clr 0x40400218 /* *@Address: 0xBE0E021C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_021C_DW_021C 0x4800021C /* *@Address: 0xBE0E021C[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_GBD_update_once 0x4040021C /* *@Address: 0xBE0E021C[8] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_GBD_update_always 0x4040021D /* *@Address: 0xBE0E021C[16] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_GBD_int_diff 0x4040021E /* *@Address: 0xBE0E021C[24] *@Range: 0~1 *@Default: *@Access: R *@Description: * GBD exist (write 1, clear) */ #define HDMIRX_R_GBD_exist 0x4040021F /* *@Address: 0xBE0E0220[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0220_DW_0220 0x48000220 /* *@Address: 0xBE0E0220[3:0] *@Range: 0~15 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_current_num 0x41000220 /* *@Address: 0xBE0E0220[11:8] *@Range: 0~15 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_affected_num 0x41000221 /* *@Address: 0xBE0E0220[16] *@Range: 0~1 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_next_field 0x40400222 /* *@Address: 0xBE0E0220[24] *@Range: 0~1 *@Default: *@Access: *@Description: None */ #define HDMIRX_GBD_no_current_gdb 0x40400223 /* *@Address: 0xBE0E0224[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0224_DW_0224 0x48000224 /* *@Address: 0xBE0E0224[2:0] *@Range: 0~7 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_profile_2_0_ 0x40C00224 /* *@Address: 0xBE0E0224[10:8] *@Range: 0~7 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_pkt_seq_2_0_ 0x40C00225 /* *@Address: 0xBE0E0228[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0228_DW_0228 0x48000228 /* *@Address: 0xBE0E0228[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_data_31_0_ 0x48000228 /* *@Address: 0xBE0E022C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_022C_DW_022C 0x4800022C /* *@Address: 0xBE0E022C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_data_63_32_ 0x4800022C /* *@Address: 0xBE0E0230[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0230_DW_0230 0x48000230 /* *@Address: 0xBE0E0230[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_data_95_64_ 0x48000230 /* *@Address: 0xBE0E0234[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0234_DW_0234 0x48000234 /* *@Address: 0xBE0E0234[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_data_127_96_ 0x48000234 /* *@Address: 0xBE0E0238[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0238_DW_0238 0x48000238 /* *@Address: 0xBE0E0238[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_data_159_128_ 0x48000238 /* *@Address: 0xBE0E023C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_023C_DW_023C 0x4800023C /* *@Address: 0xBE0E023C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_data_191_160_ 0x4800023C /* *@Address: 0xBE0E0240[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0240_DW_0240 0x48000240 /* *@Address: 0xBE0E0240[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_GBD_data_223_192_ 0x48000240 /* *@Address: 0xBE0E0244[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0244_DW_0244 0x48000244 /* *@Address: 0xBE0E0244[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * When R_HDMI_level[2]=1, refer to them. * H active width */ #define HDMIRX_de_h_width_lock 0x43400244 /* *@Address: 0xBE0E0244[28:16] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Top field active lines */ #define HDMIRX_top_de_v_width_lock 0x43500244 /* *@Address: 0xBE0E0248[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0248_DW_0248 0x48000248 /* *@Address: 0xBE0E0248[12:0] *@Range: 0~8191 *@Default: *@Access: R *@Description: * Bottom field active lines */ #define HDMIRX_btn_de_v_width_lock 0x43400248 /* *@Address: 0xBE0E024C[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_024C_DW_024C 0x4800024C /* *@Address: 0xBE0E024C[0] *@Range: 0~1 *@Default: *@Access: R *@Description: * H active width ready (refer to 244[12:0]) */ #define HDMIRX_de_h_ready 0x4040024C /* *@Address: 0xBE0E024C[8] *@Range: 0~1 *@Default: *@Access: R *@Description: * Top field active lines (refer to 244[28:16]) */ #define HDMIRX_top_de_v_ready 0x4040024D /* *@Address: 0xBE0E024C[16] *@Range: 0~1 *@Default: *@Access: R *@Description: * Bottom field active lines (refer to 248[12:0]) */ #define HDMIRX_btn_de_v_ready 0x4040024E /* *@Address: 0xBE0E0250[31:0] *@Range: 0~4294967295 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_0250_DW_0250 0x48000250 /* *@Address: 0xBE0E0250[0] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_CDRRSTJ_man_ctl 0x40400250 /* *@Address: 0xBE0E0250[1] *@Range: 0~1 *@Default: *@Access: R/W *@Description: None */ #define HDMIRX_R_CDRRSTJ_man_val 0x40410250 /* *@Address: 0xBE0E0254[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0254_DW_0254 0x48000254 /* *@Address: 0xBE0E0254[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_PHYDBG_ERRCNT_7_0_ 0x42000254 /* *@Address: 0xBE0E0254[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_PHYDBG_ERRCNT_15_8_ 0x42000255 /* *@Address: 0xBE0E0254[23:16] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_PHYDBG_ERRCNT_23_16_ 0x42000256 /* *@Address: 0xBE0E0254[31:24] *@Range: 0~255 *@Default: *@Access: R *@Description: None */ #define HDMIRX_PHYDBG_ERRCNT_31_24_ 0x42000257 /* *@Address: 0xBE0E0308[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_0308_DW_0308 0x48000308 /* *@Address: 0xBE0E0308[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1:Strict symbol lock */ #define HDMIRX_R_strict_symlock_a 0x4040030A /* *@Address: 0xBE0E0308[17] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Useless */ #define HDMIRX_R_strict_symlock_b 0x4041030A /* *@Address: 0xBE0E0308[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * Useless */ #define HDMIRX_R_strict_symlock_c 0x4042030A /* *@Address: 0xBE0E0308[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * 1:align chk is dependent on last status. */ #define HDMIRX_R_pre_align_chk_a 0x4044030A /* *@Address: 0xBE0E0308[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * Useless */ #define HDMIRX_R_pre_align_chk_b 0x4045030A /* *@Address: 0xBE0E0308[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * Useless */ #define HDMIRX_R_pre_align_chk_c 0x4046030A /* *@Address: 0xBE0E0308[25:24] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: * 00:portA, 01:portB, 10:portC */ #define HDMIRX_R_hdmi_port_sel 0x4080030B /* *@Address: 0xBE0E0308[27:26] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: * 00:portA, 01:portB, 10:portC */ #define HDMIRX_R_mhl_port_sel 0x4082030B /* *@Address: 0xBE0E0308[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * 1:inter-alignment state will be locked if inter-alignment happens. */ #define HDMIRX_R_align_hold 0x4044030B /* *@Address: 0xBE0E0308[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * 1:inter-alignment changes only at Vsync. */ #define HDMIRX_R_align_change_vs 0x4045030B /* *@Address: 0xBE0E030C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_030C_DW_030C 0x4800030C /* *@Address: 0xBE0E030C[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Select HDCP data part reset: 0:HDCP rstn (00D4[8],[16]), 1:HDMI rstn (0040[0]) */ #define HDMIRX_R_HDCP_tclk_rst_sel 0x4040030C /* *@Address: 0xBE0E0A00[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0A00_DW_0A00 0x48000A00 /* *@Address: 0xBE0E0A00[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * HDCP register (00) */ #define HDMIRX_R_read_data_7_0_ 0x42000A00 /* *@Address: 0xBE0E0A00[15:8] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (01) */ #define HDMIRX_R_read_data_15_8_ 0x42000A01 /* *@Address: 0xBE0E0A00[23:16] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (02) */ #define HDMIRX_R_read_data_23_16_ 0x42000A02 /* *@Address: 0xBE0E0A00[31:24] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (03) */ #define HDMIRX_R_read_data_31_24_ 0x42000A03 /* *@Address: 0xBE0E0A04[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0A04_DW_0A04 0x48000A04 /* *@Address: 0xBE0E0A04[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * HDCP register (04) */ #define HDMIRX_R_read_data_39_32_ 0x42000A04 /* *@Address: 0xBE0E0A04[15:8] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (08) */ #define HDMIRX_R_read_data_47_40_ 0x42000A05 /* *@Address: 0xBE0E0A04[23:16] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (09) */ #define HDMIRX_R_read_data_55_48_ 0x42000A06 /* *@Address: 0xBE0E0A04[31:24] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (0a) */ #define HDMIRX_R_read_data_63_56_ 0x42000A07 /* *@Address: 0xBE0E0A08[31:0] *@Range: 0~4294967295 *@Default: *@Access: R *@Description: None */ #define HDMIRX_0A08_DW_0A08 0x48000A08 /* *@Address: 0xBE0E0A08[7:0] *@Range: 0~255 *@Default: *@Access: R *@Description: * HDCP register (40) */ #define HDMIRX_R_read_data_71_64_ 0x42000A08 /* *@Address: 0xBE0E0A08[15:8] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (41) */ #define HDMIRX_R_read_data_79_72_ 0x42000A09 /* *@Address: 0xBE0E0A08[23:16] *@Range: 0~255 *@Default: *@Access: *@Description: * HDCP register (42) */ #define HDMIRX_R_read_data_87_80_ 0x42000A0A /* *@Address: 0xBE0E0A10[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_0A10_DW_0A10 0x48000A10 /* *@Address: 0xBE0E0A10[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_write_Aksv_mio 0x40400A10 /* *@Address: 0xBE0E0A14[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_0A14_DW_0A14 0x48000A14 /* *@Address: 0xBE0E0A14[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_write_Ainfo_mio 0x40400A14 /* *@Address: 0xBE0E0A18[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_0A18_DW_0A18 0x48000A18 /* *@Address: 0xBE0E0A18[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_write_An_mio 0x40400A18 /* *@Address: 0xBE0E0A1C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_0A1C_DW_0A1C 0x48000A1C /* *@Address: 0xBE0E0A1C[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_read_Ri_mio 0x40400A1C /* *@Address: 0xBE0E0A20[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_0A20_DW_0A20 0x48000A20 /* *@Address: 0xBE0E0A20[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Swap received data. 1:{rx_in[9:0],rx_in[19:10]}, 0:rx_in[19:0] */ #define HDMIRX_R_swap_byte_a 0x40400A20 /* *@Address: 0xBE0E1030[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1030_DW_1030 0x48001030 /* *@Address: 0xBE0E1030[0] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1:mhl mode, 0:hdmi mode */ #define HDMIRX_R_hdmi_mhl 0x40401030 /* *@Address: 0xBE0E1030[1] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1: sw controls mhl mode or hdmi mode.(1030[0]) */ #define HDMIRX_R_mmio_cbus 0x40411030 /* *@Address: 0xBE0E1030[2] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1:path_en */ #define HDMIRX_R_path_en 0x40421030 /* *@Address: 0xBE0E1030[3] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1:muted */ #define HDMIRX_R_muted 0x40431030 /* *@Address: 0xBE0E1030[6:4] *@Range: 0~7 *@Default: 0x0 *@Access: R/W *@Description: * 011: 24-bit,010:pixelpacked mode */ #define HDMIRX_R_mhl_mode 0x40C41030 /* *@Address: 0xBE0E1030[7] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1:ainfo, An and aksv come from registers, 0: come from cbus */ #define HDMIRX_R_mhl_hdcp_in 0x40471030 /* *@Address: 0xBE0E1030[11:8] *@Range: 0~15 *@Default: 0x0 *@Access: R/W *@Description: * Align counter of 24-bit mode */ #define HDMIRX_R_align_cnt_24 0x41001031 /* *@Address: 0xBE0E1030[15:12] *@Range: 0~15 *@Default: 0x0 *@Access: R/W *@Description: * Align counter of pp mode */ #define HDMIRX_R_align_cnt_pp 0x41041031 /* *@Address: 0xBE0E1030[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: * Ainfo for mhl mode */ #define HDMIRX_R_mhl_ainfo 0x42001032 /* *@Address: 0xBE0E1030[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: * Aksv for mhl mode */ #define HDMIRX_R_mhl_Aksv_7_0_ 0x42001033 /* *@Address: 0xBE0E1034[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1034_DW_1034 0x48001034 /* *@Address: 0xBE0E1034[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: * Aksv for mhl mode */ #define HDMIRX_R_mhl_Aksv_15_8_ 0x42001034 /* *@Address: 0xBE0E1034[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_Aksv_23_16_ 0x42001035 /* *@Address: 0xBE0E1034[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_Aksv_31_24_ 0x42001036 /* *@Address: 0xBE0E1034[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_Aksv_47_32_ 0x42001037 /* *@Address: 0xBE0E1038[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1038_DW_1038 0x48001038 /* *@Address: 0xBE0E1038[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: * An for mhl mode */ #define HDMIRX_R_mhl_An_7_0_ 0x42001038 /* *@Address: 0xBE0E1038[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_An_15_8_ 0x42001039 /* *@Address: 0xBE0E1038[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_An_23_16_ 0x4200103A /* *@Address: 0xBE0E1038[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_An_31_24_ 0x4200103B /* *@Address: 0xBE0E103C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_103C_DW_103C 0x4800103C /* *@Address: 0xBE0E103C[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_An_39_32_ 0x4200103C /* *@Address: 0xBE0E103C[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_An_47_40_ 0x4200103D /* *@Address: 0xBE0E103C[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_An_55_48_ 0x4200103E /* *@Address: 0xBE0E103C[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mhl_An_63_56_ 0x4200103F /* *@Address: 0xBE0E1040[31:0] *@Range: 0~4294967295 *@Default: 0x300010 *@Access: R/W *@Description: None */ #define HDMIRX_1040_DW_1040 0x48001040 /* *@Address: 0xBE0E1040[7:0] *@Range: 0~255 *@Default: 0x10 *@Access: R/W *@Description: * Ctrl num. If the number of the data that meet control period data is greater than ¡§Ctrl num¡¨, then control period locks. */ #define HDMIRX_R_ctrl_num 0x42001040 /* *@Address: 0xBE0E1040[15:8] *@Range: 0~255 *@Default: *@Access: R *@Description: * Unstable mhl lock counter */ #define HDMIRX_unstable_mhl_lock_cnt 0x42001041 /* *@Address: 0xBE0E1040[31:16] *@Range: 0~65535 *@Default: 0x30 *@Access: R/W *@Description: * When mode changes, engine will reset during this time.(40.69ns*48) */ #define HDMIRX_R_mode_chg_time_15_0_ 0x44101040 /* *@Address: 0xBE0E1044[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_1044_DW_1044 0x48001044 /* *@Address: 0xBE0E1044[15:0] *@Range: 0~65535 *@Default: 0x0 *@Access: R/W *@Description: None */ #define HDMIRX_R_mode_chg_time_31_16_ 0x44001044 /* *@Address: 0xBE0E1044[16] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * 1:mhl clk mode, path_en and muted are set by SW (1030[2],1030[3],1030[6:4]) */ #define HDMIRX_R_link_cbus 0x40401046 /* *@Address: 0xBE0E1044[24] *@Range: 0~1 *@Default: 0x0 *@Access: R/W *@Description: * Write 1, clear (refer to 1041) */ #define HDMIRX_clr_unstable_mhl_lock_cnt 0x40401047 /* *@Address: 0xBE0E0280[31:0] *@Range: 0~4294967295 *@Default: 0x888011c0 *@Access: *@Description: None */ #define CTRLI_31_0__DW_0280 0x48000280 /* *@Address: 0xBE0E0280[3:0] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: * PLL_CTRL */ #define HDMIRX_PLL_ICTRL_3_0_ 0x41000280 /* *@Address: 0xBE0E0280[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQ's I CTL[0] */ #define HDMIRX_EQ_ICTL0 0x40440280 /* *@Address: 0xBE0E0280[5] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * EQ's I CTL[1], 11/10/01/00 : 500u/400u/300u/200u */ #define HDMIRX_EQ_ICTL1 0x40450280 /* *@Address: 0xBE0E0280[7:6] *@Range: 0~3 *@Default: 0x1 *@Access: *@Description: * CKAFE's I ctrl 11/10/01/00 : 120u/100u/80u/60u */ #define HDMIRX_PHY_IB_CT_CK 0x40860280 /* *@Address: 0xBE0E0280[9:8] *@Range: 0~3 *@Default: 0x1 *@Access: *@Description: * DATAFE's I CTL 11/10/01/00 : 120u/100u/80u/60u */ #define HDMIRX_PHY_ICTL_DATSF_1_0_ 0x40800281 /* *@Address: 0xBE0E0280[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * DATAFE's BW ctrl 0/1 : wide/narrow */ #define HDMIRX_PHY_SF_CAP_SEL 0x40420281 /* *@Address: 0xBE0E0280[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * DATAFE's DC gain ctrl 0/1 : 1db/4db */ #define HDMIRX_PHY_SF_RSW 0x40430281 /* *@Address: 0xBE0E0280[13:12] *@Range: 0~3 *@Default: 0x1 *@Access: *@Description: * EQ's DC voltage ctrl 00/01/10/11 : 0.55/0.6/0.65/0.7 */ #define HDMIRX_BIAS_VREF_SF_SEL_1_0_ 0x40840281 /* *@Address: 0xBE0E0280[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PHY DIV ctl 0/1 : don't care / ¡Ò16 */ #define HDMIRX_PHY_DIVSLE2 0x40460281 /* *@Address: 0xBE0E0280[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL DIV ctl 0/1 : don't care / ¡Ò16 */ #define HDMIRX_PLL_DIVSEL2 0x40470281 /* *@Address: 0xBE0E0280[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQC0_[2:0] is EQ stg1 AC ctl 111->000 : AC gain strong -> week */ #define HDMIRX_PRE0_EQC0_0 0x40400282 /* *@Address: 0xBE0E0280[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQC0_[2:0] is EQ stg1 AC ctl 111->000 : AC gain strong -> week */ #define HDMIRX_PRE0_EQC0_1 0x40410282 /* *@Address: 0xBE0E0280[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQC0_[2:0] is EQ stg1 AC ctl 111->000 : AC gain strong -> week */ #define HDMIRX_PRE0_EQC0_2 0x40420282 /* *@Address: 0xBE0E0280[19] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * 1: fix eq value on fix_d*, 0: target eq value(pre*) */ #define HDMIRX_EQ_VAL_FIX 0x40430282 /* *@Address: 0xBE0E0280[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQC1_[2:0] is EQ stg2 AC ctl 111->000 : AC gain strong -> week */ #define HDMIRX_PRE0_EQC1_0 0x40440282 /* *@Address: 0xBE0E0280[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQC1_[2:0] is EQ stg2 AC ctl 111->000 : AC gain strong -> week */ #define HDMIRX_PRE0_EQC1_1 0x40450282 /* *@Address: 0xBE0E0280[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQC1_[2:0] is EQ stg2 AC ctl 111->000 : AC gain strong -> week */ #define HDMIRX_PRE0_EQC1_2 0x40460282 /* *@Address: 0xBE0E0280[23] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * PHY DIV reset => 0/1 : PD / Reset */ #define HDMIRX_PHY_DIV_RESETJ 0x40470282 /* *@Address: 0xBE0E0280[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQDC0_[2:0] is EQ stg1 DC ctl 111/011/001/000 : 10db/4.5db/1.3db/-2.5db */ #define HDMIRX_PRE0_EQDC0_0 0x40400283 /* *@Address: 0xBE0E0280[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQDC0_[2:0] is EQ stg1 DC ctl 111/011/001/000 : 10db/4.5db/1.3db/-2.5db */ #define HDMIRX_PRE0_EQDC0_1 0x40410283 /* *@Address: 0xBE0E0280[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQDC0_[2:0] is EQ stg1 DC ctl 111/011/001/000 : 10db/4.5db/1.3db/-2.5db */ #define HDMIRX_PRE0_EQDC0_2 0x40420283 /* *@Address: 0xBE0E0280[27] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * DATAFE's Power down : 0/1 : normal work/PD */ #define HDMIRX_PHY_PDACJ 0x40430283 /* *@Address: 0xBE0E0280[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQDC1_[2:0] is EQ stg2 DC ctl 111/011/001/000 : 10db/4.5db/1.6db/-1.5db */ #define HDMIRX_PRE0_EQDC1_0 0x40440283 /* *@Address: 0xBE0E0280[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQDC1_[2:0] is EQ stg2 DC ctl 111/011/001/000 : 10db/4.5db/1.6db/-1.5db */ #define HDMIRX_PRE0_EQDC1_1 0x40450283 /* *@Address: 0xBE0E0280[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQDC1_[2:0] is EQ stg2 DC ctl 111/011/001/000 : 10db/4.5db/1.6db/-1.5db */ #define HDMIRX_PRE0_EQDC1_2 0x40460283 /* *@Address: 0xBE0E0280[31] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * For DEMOPLL */ #define HDMIRX_PDACJ_CK 0x40470283 /* *@Address: 0xBE0E0284[31:0] *@Range: 0~4294967295 *@Default: 0x9900 *@Access: *@Description: None */ #define CTRLI_47_32__DW_0284 0x48000284 /* *@Address: 0xBE0E0284[4:0] *@Range: 0~31 *@Default: 0x0 *@Access: *@Description: * PLL Gain bit ctl */ #define HDMIRX_PLL_GB_4_0_ 0x41400284 /* *@Address: 0xBE0E0284[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL Gain bit ctl */ #define HDMIRX_PLL_GB_5 0x40450284 /* *@Address: 0xBE0E0284[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL LDO PD0 1/0 : normal / PD (change define from 331) */ #define HDMIRX_LDO_PWD 0x40460284 /* *@Address: 0xBE0E0284[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL LDO PD1 1/0 : normal / PD (change define from 331) */ #define HDMIRX_LDO_PWDE 0x40470284 /* *@Address: 0xBE0E0284[8] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * CTP's voltage compare PD, 0/1 : normal work/PD */ #define HDMIRX_PLL_PD_COMP 0x40400285 /* *@Address: 0xBE0E0284[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * CTP's voltage compare EN, 0/1 : disable/enable */ #define HDMIRX_PLL_EN_COMP 0x40410285 /* *@Address: 0xBE0E0284[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL REFCLK DIV => 0/1 : ¡Ò1 / ¡Ò2 */ #define HDMIRX_PLL_REFDIV 0x40420285 /* *@Address: 0xBE0E0284[11] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * PLL DIV mode sel => 0/1 : Demod/HDMI_MHL */ #define HDMIRX_DEMOD_EN 0x40430285 /* *@Address: 0xBE0E0284[12] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * PLL DIV RESET => 0/1 : PD/RESET */ #define HDMIRX_PLL_RESETJ 0x40440285 /* *@Address: 0xBE0E0284[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL KVCO CTL 0/1 : strong/week */ #define HDMIRX_PLL_EN_FDIV 0x40450285 /* *@Address: 0xBE0E0284[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL DIV PD in DEMOD 0/1 : PD / normal */ #define HDMIRX_PLL_PWDN_DEMOD 0x40460285 /* *@Address: 0xBE0E0284[15] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * PFD 's RESET 0/1 : PD/Reset */ #define HDMIRX_PLL_RSTN 0x40470285 /* *@Address: 0xBE0E0000[31:0] *@Range: 0~4294967295 *@Default: 0x7C0000F0 *@Access: *@Description: None */ #define CTRLI_79_48__DW_0000 0x48000000 /* *@Address: 0xBE0E0000[2:0] *@Range: 0~7 *@Default: 0x0 *@Access: *@Description: * Port enable 001/010/100 : port0/port1/port2 */ #define HDMIRX_PORT_EN_P2_0 0x40C00000 /* *@Address: 0xBE0E0000[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * HDMI bias power down : 0/1 : normal work/PD */ #define HDMIRX_COMP_PD 0x40430000 /* *@Address: 0xBE0E0000[6:4] *@Range: 0~7 *@Default: 0x7 *@Access: *@Description: * HDMI port termination on/off, 1/0 : on/off */ #define HDMIRX_PHY_RTT_EN_P_2_0_ 0x40C40000 /* *@Address: 0xBE0E0000[7] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * RTTREF's power down 0/1 : RTT cal/PD */ #define HDMIRX_PHY_RTTREFPD 0x40470000 /* *@Address: 0xBE0E0000[23:8] *@Range: 0~65535 *@Default: 0x0 *@Access: *@Description: * [0] EXTDIVSEL0 * [1] EXTDIVSEL1, 00/01/10/11: 1/2/4/8 * [2] MANRST4CTL, manual reset for CTL logic 0:normal 1:reset * [3] RSTJ, PLL RESET 0:reset 1:normal * [4] EXTDIVSELEN, enable EXTDIVSEL[1:0] 0:internal 1:external * [5] EXTPLLGBEN, enable EXTPLLGB[1:0] 0:internal 1:external * [6] LOCKRSTENJ, CDR reset by internal LOCK 0:enable 1:disable * [7] NOCHGRSTENJ, PLL reset by detect2 NO_CHANGE 0:enable 1:disable * [8] DIVDELAY0, DIV period bit-0 * [9] DIVDELAY1, DIV period bit-1 * [10] DIVDELAY2, DIV period bit-2, 000~111: 100~800uS * [11] DIV gain bit-0 * [12] DIV gain bit-1, 00/01/10/11: 1/0.5/0.33/0.25 * [13] DIVBACKENJ, DIV version in CTL, 0:A1 1:B0( A1: fixed 100uS & unbounded gain) * [14] GTTMDSCKENJ, TMDSCK gated by internal LOCK 0:enable 1:disable * [15] WDTENJ, LOCK auto reset by 1.6mS WDT 0:enable 1:disable */ #define HDMIRX_CTL_R_MORECTRLI_15_0_ 0x44080000 /* *@Address: 0xBE0E0000[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * De-bounce EN 0:disable 1:enable */ #define HDMIRX_CTL_R_LOCK_ABORT 0x40400003 /* *@Address: 0xBE0E0000[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * LOCK EN 0:disable 1:enable */ #define HDMIRX_CTL_R_LOCK_START 0x40410003 /* *@Address: 0xBE0E0000[26] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * PAT COMP ERROR_CNT reset 0:reset 1:normal */ #define HDMIRX_CTL_R_ERR_CLRN 0x40420003 /* *@Address: 0xBE0E0000[27] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * DETECT EN 0:disable 1:enable */ #define HDMIRX_CTL_R_DETECT_START 0x40430003 /* *@Address: 0xBE0E0000[31:28] *@Range: 0~15 *@Default: 0x7 *@Access: *@Description: * PAT COMP manual reset 0:reset 1:normal * PAT COMP reset by LOCK 0:enable 1:disable * Enable clock to PAT COMP 0:disable 1:normal * Inverse clock to PAT COMP EN 0:diable 1:enable */ #define HDMIRX_CTL_R_PC_CTRL_3_0_ 0x41040003 /* *@Address: 0xBE0E0004[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_111_80__DW_0004 0x48000004 /* *@Address: 0xBE0E0004[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC0_0 0x40400004 /* *@Address: 0xBE0E0004[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC0_1 0x40410004 /* *@Address: 0xBE0E0004[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC0_2 0x40420004 /* *@Address: 0xBE0E0004[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC1_0 0x40430004 /* *@Address: 0xBE0E0004[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC1_1 0x40440004 /* *@Address: 0xBE0E0004[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC1_2 0x40450004 /* *@Address: 0xBE0E0004[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC2_0 0x40460004 /* *@Address: 0xBE0E0004[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC2_1 0x40470004 /* *@Address: 0xBE0E0004[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQC2_2 0x40400005 /* *@Address: 0xBE0E0004[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC0_0 0x40410005 /* *@Address: 0xBE0E0004[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC0_1 0x40420005 /* *@Address: 0xBE0E0004[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC0_2 0x40430005 /* *@Address: 0xBE0E0004[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC1_0 0x40440005 /* *@Address: 0xBE0E0004[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC1_1 0x40450005 /* *@Address: 0xBE0E0004[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC1_2 0x40460005 /* *@Address: 0xBE0E0004[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC2_0 0x40470005 /* *@Address: 0xBE0E0004[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC2_1 0x40400006 /* *@Address: 0xBE0E0004[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE1_EQDC2_2 0x40410006 /* *@Address: 0xBE0E0004[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC0_0 0x40420006 /* *@Address: 0xBE0E0004[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC0_1 0x40430006 /* *@Address: 0xBE0E0004[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC0_2 0x40440006 /* *@Address: 0xBE0E0004[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC1_0 0x40450006 /* *@Address: 0xBE0E0004[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC1_1 0x40460006 /* *@Address: 0xBE0E0004[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC1_2 0x40470006 /* *@Address: 0xBE0E0004[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC2_0 0x40400007 /* *@Address: 0xBE0E0004[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC2_1 0x40410007 /* *@Address: 0xBE0E0004[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQC2_2 0x40420007 /* *@Address: 0xBE0E0004[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC0_0 0x40430007 /* *@Address: 0xBE0E0004[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC0_1 0x40440007 /* *@Address: 0xBE0E0004[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC0_2 0x40450007 /* *@Address: 0xBE0E0004[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC1_0 0x40460007 /* *@Address: 0xBE0E0004[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC1_1 0x40470007 /* *@Address: 0xBE0E0008[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_143_112__DW_0008 0x48000008 /* *@Address: 0xBE0E0008[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC1_2 0x40400008 /* *@Address: 0xBE0E0008[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC2_0 0x40410008 /* *@Address: 0xBE0E0008[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC2_1 0x40420008 /* *@Address: 0xBE0E0008[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE2_EQDC2_2 0x40430008 /* *@Address: 0xBE0E0008[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC0_0 0x40440008 /* *@Address: 0xBE0E0008[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC0_1 0x40450008 /* *@Address: 0xBE0E0008[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC0_2 0x40460008 /* *@Address: 0xBE0E0008[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC1_0 0x40470008 /* *@Address: 0xBE0E0008[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC1_1 0x40400009 /* *@Address: 0xBE0E0008[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC1_2 0x40410009 /* *@Address: 0xBE0E0008[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC2_0 0x40420009 /* *@Address: 0xBE0E0008[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC2_1 0x40430009 /* *@Address: 0xBE0E0008[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQC2_2 0x40440009 /* *@Address: 0xBE0E0008[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC0_0 0x40450009 /* *@Address: 0xBE0E0008[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC0_1 0x40460009 /* *@Address: 0xBE0E0008[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC0_2 0x40470009 /* *@Address: 0xBE0E0008[21:16] *@Range: 0~63 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTL_R_LOCK_RANGE_5_0_ 0x4180000A /* *@Address: 0xBE0E0008[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC1_0 0x4046000A /* *@Address: 0xBE0E0008[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC1_1 0x4047000A /* *@Address: 0xBE0E0008[27:24] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTL_R_LOCK_CNT_3_0_ 0x4100000B /* *@Address: 0xBE0E0008[31:28] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTL_R_UNLOCK_CNT_3_0_ 0x4104000B /* *@Address: 0xBE0E000C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_175_144__DW_000C 0x4800000C /* *@Address: 0xBE0E000C[5:0] *@Range: 0~63 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTL_R_UNLOCK_RANGE_5_0_ 0x4180000C /* *@Address: 0xBE0E000C[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC1_2 0x4046000C /* *@Address: 0xBE0E000C[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC2_0 0x4047000C /* *@Address: 0xBE0E000C[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * freq. detect boundary-1 for DIV # */ #define HDMIRX_CTL_R_FG_CNT_7_0_ 0x4200000D /* *@Address: 0xBE0E000C[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * freq. detect boundary-2 for DIV # */ #define HDMIRX_CTL_R_FH_CNT_7_0_ 0x4200000E /* *@Address: 0xBE0E000C[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * freq. detect boundary-3 for DIV # */ #define HDMIRX_CTL_R_FI_CNT_7_0_ 0x4200000F /* *@Address: 0xBE0E0010[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_207_176__DW_0010 0x48000010 /* *@Address: 0xBE0E0010[7:0] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * freq. detect boundary-4 for DIV # */ #define HDMIRX_CTL_R_FJ_CNT_7_0_ 0x42000010 /* *@Address: 0xBE0E0010[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * PAT COMP align cnt, 8'b0~8'b1*256+255: min.~max. */ #define HDMIRX_CTL_R_ALIGN_CNT_7_0_ 0x42000011 /* *@Address: 0xBE0E0010[23:16] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * freq. detect boundary-5 for DIV # */ #define HDMIRX_CTL_R_FK_CNT_7_0_ 0x42000012 /* *@Address: 0xBE0E0010[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * freq. detect boundary-6 for DIV # */ #define HDMIRX_CTL_R_FL_CNT_7_0_ 0x42000013 /* *@Address: 0xBE0E0014[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_239_208__DW_0014 0x48000014 /* *@Address: 0xBE0E0014[1:0] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: * Define channel for PAT COMP, 00/01/10/11: D2/D1/D0 */ #define HDMIRX_PATR_PATSEL_1_0_ 0x40800014 /* *@Address: 0xBE0E0014[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC2_1 0x40420014 /* *@Address: 0xBE0E0014[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE3_EQDC2_2 0x40430014 /* *@Address: 0xBE0E0014[31:4] *@Range: 0~268435455 *@Default: 0x0 *@Access: *@Description: * Define pattern for PAT COMP bit */ #define HDMIRX_CTL_R_PAT_27_0_ 0x47040014 /* *@Address: 0xBE0E0018[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_271_240__DW_0018 0x48000018 /* *@Address: 0xBE0E0018[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: * Define pattern for PAT COMP bit */ #define HDMIRX_CTL_R_PAT_59_28_ 0x48000018 /* *@Address: 0xBE0E001C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_303_272__DW_001C 0x4800001C /* *@Address: 0xBE0E001C[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * Mode_Sel_internal,Mode_select=> 0:HDMI mode, 1:MHL mode */ #define HDMIRX_HDMIP0_Mode_Sel_external 0x4040001C /* *@Address: 0xBE0E001C[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * Mode_Sel_mux, Mode_Sel_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP0_Mode_Sel_mux 0x4041001C /* *@Address: 0xBE0E001C[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * MHL_Mode_Sel_internal,Mode_select=> 0:24bit mode, 1:PP mode */ #define HDMIRX_HDMIP0_MHL_Mode_Sel_external 0x4042001C /* *@Address: 0xBE0E001C[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * MHL_Mode_Sel_mux, Mode_Sel_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP0_MHL_Mode_Sel_mux 0x4043001C /* *@Address: 0xBE0E001C[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * Mode_Sel_PLL_internal,Mode_select=> 0:HDMI mode, 1:MHL mode */ #define HDMIRX_HDMIP0_Mode_Sel_PLL_external 0x4044001C /* *@Address: 0xBE0E001C[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * Mode_Sel_PLL_mux, Mode_Sel_PLL_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP0_Mode_Sel_PLL_mux 0x4045001C /* *@Address: 0xBE0E001C[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * MHL_Mode_Sel_PLL_internal,Mode_select=> 0:24bit mode, 1:PP mode */ #define HDMIRX_HDMIP0_MHL_Mode_PLL_Sel_external 0x4046001C /* *@Address: 0xBE0E001C[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * MHL_Mode_Sel_PLL_mux, Mode_Sel_PLL_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP0_MHL_Mode_Sel_PLL_mux 0x4047001C /* *@Address: 0xBE0E001C[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P0_Rx_Sense_internal, Enable or Disable MHL_RTT=> 1:Enable, 0:Disable */ #define HDMIRX_HDMIP0_Rx_Sense_external 0x4040001D /* *@Address: 0xBE0E001C[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P0_Rx_Sense_mux, Rx_Sense_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP0_Rx_Sense_mux 0x4041001D /* *@Address: 0xBE0E001C[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P1_Rx_Sense_internal, Enable or Disable MHL_RTT=> 1:Enable, 0:Disable */ #define HDMIRX_HDMIP1_Rx_Sense_external 0x4042001D /* *@Address: 0xBE0E001C[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P1_Rx_Sense_mux, Rx_Sense_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP1_Rx_Sense_mux 0x4043001D /* *@Address: 0xBE0E001C[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P2_Rx_Sense_internal, Enable or Disable MHL_RTT=> 1:Enable, 0:Disable */ #define HDMIRX_HDMIP2_Rx_Sense_external 0x4044001D /* *@Address: 0xBE0E001C[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P2_Rx_Sense_mux, Rx_Sense_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP2_Rx_Sense_mux 0x4045001D /* *@Address: 0xBE0E001C[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQ's output DC value 00/01/10/11 = 0.764/0.733/0.672/0.611 */ #define HDMIRX_R_SP1_EQ_OUT_VREF0 0x4046001D /* *@Address: 0xBE0E001C[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * EQ's output DC value 00/01/10/11 = 0.764/0.733/0.672/0.611 */ #define HDMIRX_R_SP1_EQ_OUT_VREF1 0x4047001D /* *@Address: 0xBE0E001C[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTT_CM's setting */ #define HDMIRX_RTT_CMCTL_0_reg_ctl 0x4040001E /* *@Address: 0xBE0E001C[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTT_CM's setting */ #define HDMIRX_RTT_CMCTL_1_reg_ctl 0x4041001E /* *@Address: 0xBE0E001C[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTT_CM's setting */ #define HDMIRX_RTT_CMCTL_2_reg_ctl 0x4042001E /* *@Address: 0xBE0E001C[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTT_CM's setting */ #define HDMIRX_RTT_CMCTL_3_reg_ctl 0x4043001E /* *@Address: 0xBE0E001C[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * relationship of PHY DAT & DCK 0 / 1 :center / edge align */ #define HDMIRX_ALN_SEL 0x4044001E /* *@Address: 0xBE0E001C[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P0_Rx_Sense_TERM_internal, Enable or Disable MHL_RTT_Term=> 1:Enable, 0:Disable */ #define HDMIRX_PRE0_EQDC2_0 0x4040001F /* *@Address: 0xBE0E001C[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P0_Rx_Sense_TERM_mux, Rx_Sense_TERM_Mux=> 0 : external, 1 : internal */ #define HDMIRX_PRE0_EQDC2_1 0x4041001F /* *@Address: 0xBE0E001C[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P1_Rx_Sense_TERM_internal, Enable or Disable MHL_RTT_Term=> 1:Enable, 0:Disable */ #define HDMIRX_PRE0_EQDC2_2 0x4042001F /* *@Address: 0xBE0E001C[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P1_Rx_Sense_TERM_mux, Rx_Sense_TERM_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP1_Rx_Sense_TERM_mux 0x4043001F /* *@Address: 0xBE0E001C[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P2_Rx_Sense_TERM_internal, Enable or Disable MHL_RTT_Term=> 1:Enable, 0:Disable */ #define HDMIRX_HDMIP2_Rx_Sense_TERM_external 0x4044001F /* *@Address: 0xBE0E001C[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * P2_Rx_Sense_TERM_mux, Rx_Sense_TERM_Mux=> 0 : external, 1 : internal */ #define HDMIRX_HDMIP2_Rx_Sense_TERM_mux 0x4045001F /* *@Address: 0xBE0E001C[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP2 0x4046001F /* *@Address: 0xBE0E001C[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP3 0x4047001F /* *@Address: 0xBE0E0258[31:0] *@Range: 0~4294967295 *@Default: 0x40000 *@Access: *@Description: None */ #define CTRLI_335_304__DW_0258 0x48000258 /* *@Address: 0xBE0E0258[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * TMDSCK_CTL & TMDSCLK_PP sel => 1:TMDSCLK_PP, 0:TMDSCK_CTL */ #define HDMIRX_TMDSCLK_PP_SEL 0x40400258 /* *@Address: 0xBE0E0258[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * (to HDMI_TOP) * external TMDSCLK_PP's LOCK signal =>1: external, 0: CTL */ #define HDMIRX_external_gated_TMDSCLK 0x40410258 /* *@Address: 0xBE0E0258[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * select PLLRST_mode_chang from CTL or MODE_CHANGE =>1: Mode_chagne 0:CTL */ #define HDMIRX_PLLRESETJ_mode_sel_mux 0x40420258 /* *@Address: 0xBE0E0258[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * select HDMIRX_PLLRSTJ from CTL or MODE_CHANGE =>1:CTL 0:Mode_chang */ #define HDMIRX_HDMIRX_PLLRSTJ_SEL 0x40430258 /* *@Address: 0xBE0E0258[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * gate the HDMIRX_CDRRSTJ, 0: =0 , 1:=HDMIRX_CDRRSTJ_AND */ #define HDMIRX_HDMIRX_CDRRSTJ_CTL 0x40440258 /* *@Address: 0xBE0E0258[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * BYP_ENJ, Bypass CDRRSTJ from STABLE TIMER 0:bypass 1:normal */ #define HDMIRX_CDRRSTJ_SEL 0x40450258 /* *@Address: 0xBE0E0258[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * BYPRST_ENJ, Reset event(PLLRSTJ & CDRRSTJ) support ATE 0:inner loop 1:support */ #define HDMIRX_CTL_CDRRSTJ_sel 0x40460258 /* *@Address: 0xBE0E0258[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * when EQ_VAL_FIX =1 , EQ_CHAN_INDEP = 0 / 1 : adaptive eq decideed by D0 / D[2:0] indepadent */ #define HDMIRX_EQ_CHAN_INDP 0x40470258 /* *@Address: 0xBE0E0258[15:8] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * PLL DIV SEL for DEMOD */ #define HDMIRX_PLL_FEBDIV_7_0_ 0x42000259 /* *@Address: 0xBE0E0258[17:16] *@Range: 0~3 *@Default: 0x1 *@Access: *@Description: * source detect's vref 11/10/01/00 : NVDD33 - 0.25/0.15/0.075/0.05 */ #define HDMIRX_SD_VREF_SEL 0x4080025A /* *@Address: 0xBE0E0258[19:18] *@Range: 0~3 *@Default: 0x1 *@Access: *@Description: * DAT's Vref sel 11/10/01/00 : 1.1/1/0.8/0.7 */ #define HDMIRX_EQ_VDC_SEL 0x4082025A /* *@Address: 0xBE0E0258[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE0_EQC2_0 0x4044025A /* *@Address: 0xBE0E0258[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE0_EQC2_1 0x4045025A /* *@Address: 0xBE0E0258[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE0_EQC2_2 0x4046025A /* *@Address: 0xBE0E0258[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP4 0x4047025A /* *@Address: 0xBE0E0258[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_DN0 0x4040025B /* *@Address: 0xBE0E0258[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_DN1 0x4041025B /* *@Address: 0xBE0E0258[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_DN2 0x4042025B /* *@Address: 0xBE0E0258[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_CN 0x4043025B /* *@Address: 0xBE0E0258[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_DP0 0x4044025B /* *@Address: 0xBE0E0258[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_DP1 0x4045025B /* *@Address: 0xBE0E0258[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_DP2 0x4046025B /* *@Address: 0xBE0E0258[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_DISCON_CP 0x4047025B /* *@Address: 0xBE0E025C[31:0] *@Range: 0~255 *@Default: 0x40040000 *@Access: *@Description: None */ #define CTRLI_343_336__DW_025c 0x4200025c /* *@Address: 0xBE0E025C[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC2_0 0x4040025c /* *@Address: 0xBE0E025C[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC2_1 0x4041025c /* *@Address: 0xBE0E025C[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC2_2 0x4042025c /* *@Address: 0xBE0E025C[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC0_0 0x4043025c /* *@Address: 0xBE0E025C[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC0_1 0x4044025c /* *@Address: 0xBE0E025C[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC0_2 0x4045025c /* *@Address: 0xBE0E025C[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC1_0 0x4046025c /* *@Address: 0xBE0E025C[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC1_1 0x4047025c /* *@Address: 0xBE0E0260[31:0] *@Range: 0~4294967295 *@Default: 0x40040000 *@Access: *@Description: None */ #define CTRLI_375_344__DW_0260 0x48000260 /* *@Address: 0xBE0E0260[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC1_2 0x40400260 /* *@Address: 0xBE0E0260[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC2_0 0x40410260 /* *@Address: 0xBE0E0260[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC2_1 0x40420260 /* *@Address: 0xBE0E0260[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQDC2_2 0x40430260 /* *@Address: 0xBE0E0260[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * 0/1 : reg / RTT_CTL from ovsp */ #define HDMIRX_RTT_CMCTL_SEL 0x40440260 /* *@Address: 0xBE0E0260[7:5] *@Range: 0~7 *@Default: 0x0 *@Access: *@Description: * PD RTT_CM, 0/1 : turn off RTT_CM/turn on RTT_CM */ #define HDMIRX_P_2_0__CMCTL 0x40C50260 /* *@Address: 0xBE0E0260[10:8] *@Range: 0~7 *@Default: 0x0 *@Access: *@Description: * RTT comp thrreshold value */ #define HDMIRX_r_cmp_range_2_0_ 0x40C00261 /* *@Address: 0xBE0E0260[11] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_0 0x40430261 /* *@Address: 0xBE0E0260[12] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_1 0x40440261 /* *@Address: 0xBE0E0260[13] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_2 0x40450261 /* *@Address: 0xBE0E0260[14] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_3 0x40460261 /* *@Address: 0xBE0E0260[15] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_4 0x40470261 /* *@Address: 0xBE0E0260[16] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_5 0x40400262 /* *@Address: 0xBE0E0260[17] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_6 0x40410262 /* *@Address: 0xBE0E0260[18] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_7 0x40420262 /* *@Address: 0xBE0E0260[19] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * RTTCAL & CBUS ZSINK_CAL reset => 0/1 : PD/reset */ #define HDMIRX_mhl_resetj 0x40430262 /* *@Address: 0xBE0E0260[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTTCAL update the RTT initial value => 0/1 : not update / update */ #define HDMIRX_r_runtime_update 0x40440262 /* *@Address: 0xBE0E0260[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTTCAL signal sel => 0/1 : port0/port1 */ #define HDMIRX_r_cmp_in_sel 0x40450262 /* *@Address: 0xBE0E0260[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTT CAL digital PD 0/1 : normal work/PD */ #define HDMIRX_r_comp_pd 0x40460262 /* *@Address: 0xBE0E0260[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * RTT CAL EN => 0/1 dis/en */ #define HDMIRX_r_cal_en 0x40470262 /* *@Address: 0xBE0E0260[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * 0: The control periods of three channels are found, then the real control period is found. * 1: two of three control periods are found, then the real control period is found. */ #define HDMIRX_r_control_period_sel 0x40400263 /* *@Address: 0xBE0E0260[29:24] *@Range: 0~63 *@Default: 0x0 *@Access: *@Description: * RTT initial value */ #define HDMIRX_R_RTT_INI_5_0_ 0x41800263 /* *@Address: 0xBE0E0260[30] *@Range: 0~1 *@Default: 0x1 *@Access: *@Description: * DCK(to HDMITOP) is center or edge align : 0/1 , edge / center align */ #define HDMIRX_PHY_DESCKSEL 0x40460263 /* *@Address: 0xBE0E0260[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * ZSINK CAL enable => 0/1 : dis/en */ #define HDMIRX_r_zsink_cal_en 0x40470263 /* *@Address: 0xBE0E0264[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_407_376__DW_0264 0x48000264 /* *@Address: 0xBE0E0264[3:0] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_reg_dport_sel_3_0_ 0x41000264 /* *@Address: 0xBE0E0264[5:4] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: * reg_dport_sel_1_0_ */ #define HDMIRX_reg_dport_sel_5_4_ 0x40840264 /* *@Address: 0xBE0E0264[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_reg_dport_ext 0x40460264 /* *@Address: 0xBE0E0264[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_REG_CPS_CNT_CLEAR 0x40470264 /* *@Address: 0xBE0E0264[9:8] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_w_con_1_0_ 0x40800265 /* *@Address: 0xBE0E0264[11:10] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_w_con_3_2_ 0x40820265 /* *@Address: 0xBE0E0264[13:12] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_w_con5_4 0x40840265 /* *@Address: 0xBE0E0264[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_REG_CPS_CNT_TH0 0x40460265 /* *@Address: 0xBE0E0264[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_REG_CPS_CNT_TH1 0x40470265 /* *@Address: 0xBE0E0264[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_9 0x40400266 /* *@Address: 0xBE0E0264[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_10 0x40410266 /* *@Address: 0xBE0E0264[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_11 0x40420266 /* *@Address: 0xBE0E0264[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_12 0x40430266 /* *@Address: 0xBE0E0264[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_13 0x40440266 /* *@Address: 0xBE0E0264[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_14 0x40450266 /* *@Address: 0xBE0E0264[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_15 0x40460266 /* *@Address: 0xBE0E0264[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP_OVSP_16 0x40470266 /* *@Address: 0xBE0E0264[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC0_0 0x40400267 /* *@Address: 0xBE0E0264[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC0_1 0x40410267 /* *@Address: 0xBE0E0264[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC0_2 0x40420267 /* *@Address: 0xBE0E0264[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC1_0 0x40430267 /* *@Address: 0xBE0E0264[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC1_1 0x40440267 /* *@Address: 0xBE0E0264[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC1_2 0x40450267 /* *@Address: 0xBE0E0264[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC2_0 0x40460267 /* *@Address: 0xBE0E0264[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC2_1 0x40470267 /* *@Address: 0xBE0E0268[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_439_408__DW_0268 0x48000268 /* *@Address: 0xBE0E0268[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQC2_2 0x40400268 /* *@Address: 0xBE0E0268[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC0_0 0x40410268 /* *@Address: 0xBE0E0268[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC0_1 0x40420268 /* *@Address: 0xBE0E0268[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC0_2 0x40430268 /* *@Address: 0xBE0E0268[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC1_0 0x40440268 /* *@Address: 0xBE0E0268[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC1_1 0x40450268 /* *@Address: 0xBE0E0268[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC1_2 0x40460268 /* *@Address: 0xBE0E0268[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC2_0 0x40470268 /* *@Address: 0xBE0E0268[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC2_1 0x40400269 /* *@Address: 0xBE0E0268[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE4_EQDC2_2 0x40410269 /* *@Address: 0xBE0E0268[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC0_0 0x40420269 /* *@Address: 0xBE0E0268[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC0_1 0x40430269 /* *@Address: 0xBE0E0268[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC0_2 0x40440269 /* *@Address: 0xBE0E0268[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC1_0 0x40450269 /* *@Address: 0xBE0E0268[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC1_1 0x40460269 /* *@Address: 0xBE0E0268[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC1_2 0x40470269 /* *@Address: 0xBE0E0268[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC2_0 0x4040026A /* *@Address: 0xBE0E0268[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC2_1 0x4041026A /* *@Address: 0xBE0E0268[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQC2_2 0x4042026A /* *@Address: 0xBE0E0268[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC0_0 0x4043026A /* *@Address: 0xBE0E0268[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC0_1 0x4044026A /* *@Address: 0xBE0E0268[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC0_2 0x4045026A /* *@Address: 0xBE0E0268[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC1_0 0x4046026A /* *@Address: 0xBE0E0268[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC1_1 0x4047026A /* *@Address: 0xBE0E0268[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC1_2 0x4040026B /* *@Address: 0xBE0E0268[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC2_0 0x4041026B /* *@Address: 0xBE0E0268[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC2_1 0x4042026B /* *@Address: 0xBE0E0268[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE5_EQDC2_2 0x4043026B /* *@Address: 0xBE0E0268[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC0_0 0x4044026B /* *@Address: 0xBE0E0268[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC0_1 0x4045026B /* *@Address: 0xBE0E0268[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC0_2 0x4046026B /* *@Address: 0xBE0E0268[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC1_0 0x4047026B /* *@Address: 0xBE0E026C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_471_440__DW_026C 0x4800026C /* *@Address: 0xBE0E026C[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC1_1 0x4040026C /* *@Address: 0xBE0E026C[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC1_2 0x4041026C /* *@Address: 0xBE0E026C[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC2_0 0x4042026C /* *@Address: 0xBE0E026C[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC2_1 0x4043026C /* *@Address: 0xBE0E026C[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQC2_2 0x4044026C /* *@Address: 0xBE0E026C[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC0_0 0x4045026C /* *@Address: 0xBE0E026C[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC0_1 0x4046026C /* *@Address: 0xBE0E026C[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC0_2 0x4047026C /* *@Address: 0xBE0E026C[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC1_0 0x4040026D /* *@Address: 0xBE0E026C[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC1_1 0x4041026D /* *@Address: 0xBE0E026C[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC1_2 0x4042026D /* *@Address: 0xBE0E026C[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC2_0 0x4043026D /* *@Address: 0xBE0E026C[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC2_1 0x4044026D /* *@Address: 0xBE0E026C[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE6_EQDC2_2 0x4045026D /* *@Address: 0xBE0E026C[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC0_0 0x4046026D /* *@Address: 0xBE0E026C[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC0_1 0x4047026D /* *@Address: 0xBE0E026C[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC0_2 0x4040026E /* *@Address: 0xBE0E026C[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC1_0 0x4041026E /* *@Address: 0xBE0E026C[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC1_1 0x4042026E /* *@Address: 0xBE0E026C[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC1_2 0x4043026E /* *@Address: 0xBE0E026C[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC2_0 0x4044026E /* *@Address: 0xBE0E026C[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC2_1 0x4045026E /* *@Address: 0xBE0E026C[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQC2_2 0x4046026E /* *@Address: 0xBE0E026C[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC0_0 0x4047026E /* *@Address: 0xBE0E026C[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC0_1 0x4040026F /* *@Address: 0xBE0E026C[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC0_2 0x4041026F /* *@Address: 0xBE0E026C[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC1_0 0x4042026F /* *@Address: 0xBE0E026C[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC1_1 0x4043026F /* *@Address: 0xBE0E026C[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC1_2 0x4044026F /* *@Address: 0xBE0E026C[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC2_0 0x4045026F /* *@Address: 0xBE0E026C[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC2_1 0x4046026F /* *@Address: 0xBE0E026C[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE7_EQDC2_2 0x4047026F /* *@Address: 0xBE0E0270[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_503_472__DW_0270 0x48000270 /* *@Address: 0xBE0E0270[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC0_0 0x40400270 /* *@Address: 0xBE0E0270[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC0_1 0x40410270 /* *@Address: 0xBE0E0270[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC0_2 0x40420270 /* *@Address: 0xBE0E0270[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC1_0 0x40430270 /* *@Address: 0xBE0E0270[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC1_1 0x40440270 /* *@Address: 0xBE0E0270[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC1_2 0x40450270 /* *@Address: 0xBE0E0270[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC2_0 0x40460270 /* *@Address: 0xBE0E0270[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC2_1 0x40470270 /* *@Address: 0xBE0E0270[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQC2_2 0x40400271 /* *@Address: 0xBE0E0270[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC0_0 0x40410271 /* *@Address: 0xBE0E0270[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC0_1 0x40420271 /* *@Address: 0xBE0E0270[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC0_2 0x40430271 /* *@Address: 0xBE0E0270[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC1_0 0x40440271 /* *@Address: 0xBE0E0270[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC1_1 0x40450271 /* *@Address: 0xBE0E0270[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC1_2 0x40460271 /* *@Address: 0xBE0E0270[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC2_0 0x40470271 /* *@Address: 0xBE0E0270[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC2_1 0x40400272 /* *@Address: 0xBE0E0270[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE8_EQDC2_2 0x40410272 /* *@Address: 0xBE0E0270[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC0_0 0x40420272 /* *@Address: 0xBE0E0270[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC0_1 0x40430272 /* *@Address: 0xBE0E0270[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC0_2 0x40440272 /* *@Address: 0xBE0E0270[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC1_0 0x40450272 /* *@Address: 0xBE0E0270[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC1_1 0x40460272 /* *@Address: 0xBE0E0270[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_PRE9_EQC1_2 0x40470272 /* *@Address: 0xBE0E0270[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_comp_tm_7_0_ 0x42000273 /* *@Address: 0xBE0E0274[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_535_504__DW_0274 0x48000274 /* *@Address: 0xBE0E0274[23:0] *@Range: 0~16777215 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_comp_tm_31_8_ 0x46000274 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP6 0x42000277 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP7 0x42000277 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP8 0x42000277 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP9 0x42000277 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP10 0x42000277 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP11 0x42000277 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP12 0x42000277 /* *@Address: 0xBE0E0274[31:24] *@Range: 0~255 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP13 0x42000277 /* *@Address: 0xBE0E0278[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_567_536__DW_0278 0x48000278 /* *@Address: 0xBE0E0278[3:0] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_plsc_mtr_3_0_ 0x41000278 /* *@Address: 0xBE0E0278[7:4] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_mnsc_mtr_3_0_ 0x41040278 /* *@Address: 0xBE0E0278[12:8] *@Range: 0~31 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_reg_ovcps1_th_4_0_ 0x41400279 /* *@Address: 0xBE0E0278[15:13] *@Range: 0~7 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_tenbit_sel_2_0_ 0x40C50279 /* *@Address: 0xBE0E0278[19:16] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_reg_ovcps2_th_3_0_ 0x4100027A /* *@Address: 0xBE0E0278[21:20] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_bias_fc_1_0_ 0x4084027A /* *@Address: 0xBE0E0278[23:22] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_stb_rsc_1_0_ 0x4086027A /* *@Address: 0xBE0E0278[25:24] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_rst_con_1_0_ 0x4080027B /* *@Address: 0xBE0E0278[27:26] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_chan_sel_1_0_ 0x4082027B /* *@Address: 0xBE0E0278[30:28] *@Range: 0~7 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_bs_2_0_ 0x40C4027B /* *@Address: 0xBE0E0278[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_edon 0x4047027B /* *@Address: 0xBE0E027C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_599_568__DW_027C 0x4800027C /* *@Address: 0xBE0E027C[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * track_engine: LPF0 taps number(For up and dn) */ #define HDMIRX_taps_0 0x4040027C /* *@Address: 0xBE0E027C[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * track_engine: LPF0 taps number(For up and dn) */ #define HDMIRX_taps_1 0x4041027C /* *@Address: 0xBE0E027C[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_byp 0x4042027C /* *@Address: 0xBE0E027C[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * floating in OVSP */ #define HDMIRX_R_SP_OVSP_8 0x4043027C /* *@Address: 0xBE0E027C[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_ckdt 0x4044027C /* *@Address: 0xBE0E027C[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_pll_lck 0x4045027C /* *@Address: 0xBE0E027C[7:6] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_mode_1_0_ 0x4086027C /* *@Address: 0xBE0E027C[10:8] *@Range: 0~7 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_EQ_VAL_OFST_2_0 0x40C0027D /* *@Address: 0xBE0E027C[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_bp_fix 0x4043027D /* *@Address: 0xBE0E027C[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_de_lo 0x4044027D /* *@Address: 0xBE0E027C[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_rlxe_on 0x4045027D /* *@Address: 0xBE0E027C[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_ext_eq 0x4046027D /* *@Address: 0xBE0E027C[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_strth 0x4047027D /* *@Address: 0xBE0E027C[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * floating in HDMIPHY */ #define HDMIRX_R_SP14 0x4040027E /* *@Address: 0xBE0E027C[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_lowlmt 0x4041027E /* *@Address: 0xBE0E027C[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_vldchk 0x4042027E /* *@Address: 0xBE0E027C[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_byp10 0x4043027E /* *@Address: 0xBE0E027C[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_aft_eqs 0x4044027E /* *@Address: 0xBE0E027C[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_fc4char 0x4045027E /* *@Address: 0xBE0E027C[23:22] *@Range: 0~3 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_reg_eqms_en_1_0_ 0x4086027E /* *@Address: 0xBE0E027C[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_icrst_n 0x4040027F /* *@Address: 0xBE0E027C[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * gate the DCK to HDMITOP 0/1 : gated/normal */ #define HDMIRX_RST_1XCLK 0x4041027F /* *@Address: 0xBE0E027C[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_prstn 0x4042027F /* *@Address: 0xBE0E027C[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * PLL_CTP_PWDJ , set CTP to 0, toggle with PLL_RESETJ , 0/1 : CPT=0 / normal */ #define HDMIRX_R_SP5_PLL_CTP_PWDJ 0x4043027F /* *@Address: 0xBE0E027C[31:28] *@Range: 0~15 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_reg_rdout_sel_3_0_ 0x4104027F /* *@Address: 0xBE0E0430[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_631_600__DW_0430 0x48000430 /* *@Address: 0xBE0E0430[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC0_0 0x40400430 /* *@Address: 0xBE0E0430[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC0_1 0x40410430 /* *@Address: 0xBE0E0430[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC0_2 0x40420430 /* *@Address: 0xBE0E0430[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI603_floating 0x40430430 /* *@Address: 0xBE0E0430[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC1_0 0x40440430 /* *@Address: 0xBE0E0430[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC1_1 0x40450430 /* *@Address: 0xBE0E0430[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC1_2 0x40460430 /* *@Address: 0xBE0E0430[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI607_floating 0x40470430 /* *@Address: 0xBE0E0430[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC2_0 0x40400431 /* *@Address: 0xBE0E0430[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC2_1 0x40410431 /* *@Address: 0xBE0E0430[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQC2_2 0x40420431 /* *@Address: 0xBE0E0430[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI611_floating 0x40430431 /* *@Address: 0xBE0E0430[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC0_0 0x40440431 /* *@Address: 0xBE0E0430[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC0_1 0x40450431 /* *@Address: 0xBE0E0430[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC0_2 0x40460431 /* *@Address: 0xBE0E0430[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI615_floating 0x40470431 /* *@Address: 0xBE0E0430[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC1_0 0x40400432 /* *@Address: 0xBE0E0430[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC1_1 0x40410432 /* *@Address: 0xBE0E0430[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC1_2 0x40420432 /* *@Address: 0xBE0E0430[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI619_floating 0x40430432 /* *@Address: 0xBE0E0430[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC2_0 0x40440432 /* *@Address: 0xBE0E0430[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC2_1 0x40450432 /* *@Address: 0xBE0E0430[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D2_EQDC2_2 0x40460432 /* *@Address: 0xBE0E0430[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI623_floating 0x40470432 /* *@Address: 0xBE0E0430[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC0_0 0x40400433 /* *@Address: 0xBE0E0430[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC0_1 0x40410433 /* *@Address: 0xBE0E0430[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC0_2 0x40420433 /* *@Address: 0xBE0E0430[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI627_floating 0x40430433 /* *@Address: 0xBE0E0430[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC1_0 0x40440433 /* *@Address: 0xBE0E0430[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC1_1 0x40450433 /* *@Address: 0xBE0E0430[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC1_2 0x40460433 /* *@Address: 0xBE0E0430[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI631_floating 0x40470433 /* *@Address: 0xBE0E0434[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_663_632__DW_0434 0x48000434 /* *@Address: 0xBE0E0434[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC2_0 0x40400434 /* *@Address: 0xBE0E0434[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC2_1 0x40410434 /* *@Address: 0xBE0E0434[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQC2_2 0x40420434 /* *@Address: 0xBE0E0434[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI635_floating 0x40430434 /* *@Address: 0xBE0E0434[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC0_0 0x40440434 /* *@Address: 0xBE0E0434[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC0_1 0x40450434 /* *@Address: 0xBE0E0434[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC0_2 0x40460434 /* *@Address: 0xBE0E0434[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI639_floating 0x40470434 /* *@Address: 0xBE0E0434[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC1_0 0x40400435 /* *@Address: 0xBE0E0434[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC1_1 0x40410435 /* *@Address: 0xBE0E0434[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC1_2 0x40420435 /* *@Address: 0xBE0E0434[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI643_floating 0x40430435 /* *@Address: 0xBE0E0434[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC2_0 0x40440435 /* *@Address: 0xBE0E0434[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC2_1 0x40450435 /* *@Address: 0xBE0E0434[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D1_EQDC2_2 0x40460435 /* *@Address: 0xBE0E0434[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI647_floating 0x40470435 /* *@Address: 0xBE0E0434[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC0_0 0x40400436 /* *@Address: 0xBE0E0434[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC0_1 0x40410436 /* *@Address: 0xBE0E0434[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC0_2 0x40420436 /* *@Address: 0xBE0E0434[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI651_floating 0x40430436 /* *@Address: 0xBE0E0434[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC1_0 0x40440436 /* *@Address: 0xBE0E0434[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC1_1 0x40450436 /* *@Address: 0xBE0E0434[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC1_2 0x40460436 /* *@Address: 0xBE0E0434[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI655_floating 0x40470436 /* *@Address: 0xBE0E0434[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC2_0 0x40400437 /* *@Address: 0xBE0E0434[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC2_1 0x40410437 /* *@Address: 0xBE0E0434[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQC2_2 0x40420437 /* *@Address: 0xBE0E0434[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI659_floating 0x40430437 /* *@Address: 0xBE0E0434[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC0_0 0x40440437 /* *@Address: 0xBE0E0434[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC0_1 0x40450437 /* *@Address: 0xBE0E0434[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC0_2 0x40460437 /* *@Address: 0xBE0E0434[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI663_floating 0x40470437 /* *@Address: 0xBE0E0438[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_695_664__DW_0438 0x48000438 /* *@Address: 0xBE0E0438[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC1_0 0x40400438 /* *@Address: 0xBE0E0438[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC1_1 0x40410438 /* *@Address: 0xBE0E0438[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC1_2 0x40420438 /* *@Address: 0xBE0E0438[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI667_floating 0x40430438 /* *@Address: 0xBE0E0438[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC2_0 0x40440438 /* *@Address: 0xBE0E0438[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC2_1 0x40450438 /* *@Address: 0xBE0E0438[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_FIX_D0_EQDC2_2 0x40460438 /* *@Address: 0xBE0E0438[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_CTRLI671_floating 0x40470438 /* *@Address: 0xBE0E0438[12:8] *@Range: 0~31 *@Default: 0x0 *@Access: *@Description: * narrow_cnt pass threshold when adp_eqmode=0 , 0: 27bits, 1:26bits¡K26:1bit (decide adp_eqmode precision) */ #define HDMIRX_NCS_4_0 0x41400439 /* *@Address: 0xBE0E0438[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * adaptive eq value mode select 0: original(sweep eq until narrow_cnt < threshold) 1: sweep all eq_val and select best eq_val */ #define HDMIRX_ADP_EQMODE 0x40450439 /* *@Address: 0xBE0E0438[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_REG_RDOUT_SEL4 0x40460439 /* *@Address: 0xBE0E0438[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_REG_RDOUT_SEL5 0x40470439 /* *@Address: 0xBE0E0438[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: * CNT bit : 20 ~ 27 -> 12 ~27 */ #define HDMIRX_BS3 0x4040043A /* *@Address: 0xBE0E0438[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP17 0x4041043A /* *@Address: 0xBE0E0438[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP18 0x4042043A /* *@Address: 0xBE0E0438[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP19 0x4043043A /* *@Address: 0xBE0E0438[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP20 0x4044043A /* *@Address: 0xBE0E0438[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP21 0x4045043A /* *@Address: 0xBE0E0438[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP22 0x4046043A /* *@Address: 0xBE0E0438[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP23 0x4047043A /* *@Address: 0xBE0E0438[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP24 0x4040043B /* *@Address: 0xBE0E0438[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP25 0x4041043B /* *@Address: 0xBE0E0438[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP26 0x4042043B /* *@Address: 0xBE0E0438[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP27 0x4043043B /* *@Address: 0xBE0E0438[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP28 0x4044043B /* *@Address: 0xBE0E0438[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP29 0x4045043B /* *@Address: 0xBE0E0438[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP30 0x4046043B /* *@Address: 0xBE0E0438[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP31 0x4047043B /* *@Address: 0xBE0E043C[31:0] *@Range: 0~4294967295 *@Default: 0x0 *@Access: *@Description: None */ #define CTRLI_727_696__DW_043C 0x4800043C /* *@Address: 0xBE0E043C[0] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP32 0x4040043C /* *@Address: 0xBE0E043C[1] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP33 0x4041043C /* *@Address: 0xBE0E043C[2] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP34 0x4042043C /* *@Address: 0xBE0E043C[3] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP35 0x4043043C /* *@Address: 0xBE0E043C[4] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP36 0x4044043C /* *@Address: 0xBE0E043C[5] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP37 0x4045043C /* *@Address: 0xBE0E043C[6] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP38 0x4046043C /* *@Address: 0xBE0E043C[7] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP39 0x4047043C /* *@Address: 0xBE0E043C[8] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP40 0x4040043D /* *@Address: 0xBE0E043C[9] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP41 0x4041043D /* *@Address: 0xBE0E043C[10] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP42 0x4042043D /* *@Address: 0xBE0E043C[11] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP43 0x4043043D /* *@Address: 0xBE0E043C[12] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP44 0x4044043D /* *@Address: 0xBE0E043C[13] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP45 0x4045043D /* *@Address: 0xBE0E043C[14] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP46 0x4046043D /* *@Address: 0xBE0E043C[15] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP47 0x4047043D /* *@Address: 0xBE0E043C[16] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP48 0x4040043E /* *@Address: 0xBE0E043C[17] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP49 0x4041043E /* *@Address: 0xBE0E043C[18] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP50 0x4042043E /* *@Address: 0xBE0E043C[19] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP51 0x4043043E /* *@Address: 0xBE0E043C[20] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP52 0x4044043E /* *@Address: 0xBE0E043C[21] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP53 0x4045043E /* *@Address: 0xBE0E043C[22] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP54 0x4046043E /* *@Address: 0xBE0E043C[23] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP55 0x4047043E /* *@Address: 0xBE0E043C[24] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP56 0x4040043F /* *@Address: 0xBE0E043C[25] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP57 0x4041043F /* *@Address: 0xBE0E043C[26] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP58 0x4042043F /* *@Address: 0xBE0E043C[27] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP59 0x4043043F /* *@Address: 0xBE0E043C[28] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP60 0x4044043F /* *@Address: 0xBE0E043C[29] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP61 0x4045043F /* *@Address: 0xBE0E043C[30] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP62 0x4046043F /* *@Address: 0xBE0E043C[31] *@Range: 0~1 *@Default: 0x0 *@Access: *@Description: None */ #define HDMIRX_R_SP63 0x4047043F #endif