#include "drv_types.h" #include "sysreg.h" #include "hdmi_time.h" #include "../../module_include/drv_gpio.h" #pragma pack(push,1) typedef struct __SYSTEM_REG { union { UINT32 reg000_007[0x2]; struct { UINT32 VenderID: 16; UINT32 DeviceID: 16; UINT32 AuxVss: 8; UINT32 RevisionID: 8; UINT32 Information : 16; }; struct { UINT32 reg000_b00_b15: 16; UINT32 chipInfo: 32; UINT32 reg004_b16_b31: 16; }; }; //UINT8 reg008_033[0x2c]; //UINT8 reg008_017[0x10]; UINT8 reg008_00b[0x4]; union { UINT32 reg00c_00f; struct { UINT32 AUX_R_SPI_RST: 1; UINT32 AUX_UART_RST: 1; UINT32 AUX_I2C_RST: 1; UINT32 AUX_IR_RST: 1; UINT32 R_TSDEMUXA_RST: 1; UINT32 reserved_00c_b5: 1; UINT32 R_I2C_MASTER_MAIN_RST: 1; UINT32 R_VDEC_RST: 1; UINT32 AUX_R_ISOLATION_OFF_MFD: 1; UINT32 AUX_R_ISOLATION_OFF_FAL: 1; UINT32 reserved_00d_b2: 1; UINT32 R_VFA_RST: 1; UINT32 R_AUDIO_AVC_RST: 1; UINT32 R_UMC_RST: 1; UINT32 R_VIP_RST: 1; UINT32 R_AUDIO_RST: 1; UINT32 R_HDMI_RST: 1; UINT32 R_VD_RST: 1; UINT32 R_USB_RST: 1; UINT32 R_TT_RST: 1; UINT32 R_CA_RST: 1; UINT32 R_USB_SW_RST: 1; UINT32 R_USB_UTMI_RST: 1; UINT32 AUX_R_USBPLL_RST: 1; UINT32 AUX_ATV_AUDIO_DEC_RST: 1; UINT32 reserved_00f_b1: 1; UINT32 AUX_R_CPU0_RST: 1; UINT32 reserved_00f_b3: 1; UINT32 R_MFD_RST: 1; UINT32 reserved_00f_b5: 1; UINT32 reserved_00f_b6: 1; UINT32 AUX_R_CPU1_RSTN: 1; }; }; UINT8 reg010_017[0x8]; union { UINT32 reg018_01b; struct { UINT32 reg02C_b0_b5: 6; UINT32 R_CBUS_DRV_PD_P0: 2; UINT32 R_CBUS_DRV_PD_P1: 2; UINT32 R_CBUS_DRV_PD_P2: 2; UINT32 R_CBUS_DRV_P0: 2; UINT32 R_CBUS_DRV_P1: 2; UINT32 R_CBUS_DRV_P2: 2; UINT32 R_CBUS_VREF_SEL: 1; UINT32 R_CBUS_SR_PD: 1; UINT32 R_CBUS_PD_SEL: 3; UINT32 R_CBUS_EN_P0_CTL_0: 1; UINT32 R_CBUS_EN_P0_CTL_1: 1; UINT32 R_CBUS_EN_P0_CTL_2: 1; UINT32 R_CBUS_EN_P1_CTL_0: 1; UINT32 R_CBUS_EN_P1_CTL_1: 1; UINT32 R_CBUS_EN_P1_CTL_2: 1; UINT32 R_CBUS_EN_P2_CTL_0: 1; UINT32 R_CBUS_EN_P2_CTL_1: 1; UINT32 R_CBUS_EN_P2_CTL_2: 1; }; }; //UINT8 reg01c_02b[0x10]; UINT8 reg01c_01f[0x4]; union { UINT32 reg020_023; struct { UINT32 reg020_b0_b27: 28; UINT32 R_CBUS_EN_P0_CTL_3: 1 ; UINT32 R_CBUS_EN_P1_CTL_3: 1; UINT32 reg020_b30_b31: 2; }; }; //UINT8 reg024_02b[0x8]; UINT8 reg024_027[0x4]; union { UINT32 reg028_02b; struct { UINT32 reg028_b0_b26: 27; UINT32 R_CEC_DIODE_RES_PD: 1; UINT32 R_CEC_DIODE_RES: 4; }; }; union { UINT32 reg02C_02F; struct { UINT32 reg02C_b0_b20: 21; UINT32 AUX_HDMIC_EN: 1; UINT32 reg02C_b22_b28: 7; UINT32 AUX_R_CBUS_VREF_TN: 1; UINT32 AUX_R_CBUS_VREF_PD: 1; UINT32 R_TSBIST_RSTN: 1; }; }; UINT8 reg030_033[0x4]; union { UINT32 reg034_037; struct { UINT32 reg034_b0_b13: 14; UINT32 R_AUX_EN_HDMIC_SW5V: 1; UINT32 R_AUX_HDMIC_SW5V: 1; UINT32 R_AUX_EN_HDMIA_SW5V: 1; UINT32 R_AUX_HDMIA_SW5V: 1; UINT32 R_AUX_EN_HDMIB_SW5V: 1; UINT32 R_AUX_HDMIB_SW5V: 1; UINT32 reg034_b20_b23: 4; UINT32 R_ICLK_FROM_IMCLK: 1; UINT32 R_I2S_5VDET_SELJ: 1; UINT32 reg034_b26_b31: 6; }; }; union { UINT32 reg038_03B; struct { UINT32 reg038_b0_b2: 3; UINT32 R_AUX_HPD1_HIGH: 1; UINT32 R_AUX_HPD2_HIGH: 1; UINT32 R_AUX_HPD3_HIGH: 1; UINT32 reg038_b6_b26: 21; UINT32 R_AUX_HPD0_HIGH: 1; UINT32 reg038_b28_b31: 4; }; }; UINT8 reg_03C_0D3[0x98]; union { UINT32 reg0D4_0D7; struct { UINT32 reg0D4_b0_b6: 7; UINT32 HDMI_CD_SENSE: 1; UINT32 reg0D4_b8_b31: 24; }; }; //UINT8 reg_0D8_0E7[0x10]; //UINT8 reg_0D8_0E3[0xc]; UINT8 reg_0D8_0DF[0x8]; union { UINT32 reg0E0_0E3; struct { UINT32 R_ATE_Z_DISCOVER: 1; UINT32 R_ATE_Z_SINK: 1; UINT32 R_ATE_Z_DISCOVER_MUX_SEL: 1; UINT32 R_ATE_Z_SINK_MUX_SEL: 1; UINT32 R_CD_SENSE_SEL: 1; UINT32 R_CD_SENSE_ENA: 1; UINT32 reg0E0_b6_b31: 26; }; }; union { UINT32 reg0E4_0E7; struct { UINT32 HPD_P0_EN_DIS_CTL0: 1; UINT32 HPD_P0_EN_DIS_CTL1: 1; UINT32 HPD_P0_EN_DIS_CTL2: 1; UINT32 HPD_P0_EN_DIS_CTL3: 1; UINT32 HPD_P1_EN_DIS_CTL0: 1; UINT32 HPD_P1_EN_DIS_CTL1: 1; UINT32 HPD_P1_EN_DIS_CTL2: 1; UINT32 HPD_P1_EN_DIS_CTL3: 1; UINT32 HPD_DRV_1_0_VBUS: 2; UINT32 HPD_DRV_1_0_PD_VBUS: 2; UINT32 HPD_EN_PU_HPD: 1; UINT32 HPD_EN_PD_HPD: 1; UINT32 HPD_EN_PU_VBUS: 1; UINT32 HPD_EN_PD_VBUS: 1; UINT32 HPD_OE_P_2_0: 3; UINT32 reg0e4_b19: 1; UINT32 HPD_PUDELAY_1_0:2; UINT32 HPD_PDDELAY_1_0:2; UINT32 HPD_SPIN_0:1;// PortA's cbus buffer enable(0:disable, 1:enable ,pmos) UINT32 HPD_SPIN_1:1;// PortB's cbus buffer enable(0:disable, 1:enable ,pmos) UINT32 HPD_SPIN_2:1;// PortC's cbus buffer enable(0:disable, 1:enable ,pmos) UINT32 HPD_SPIN_4_3:2;//cbus tx mode change for port1:port0(0:origin, 1:resistance divider) UINT32 HPD_SPIN_5:1;// A port, 1: high-z mode HPD, 0: TX mode UINT32 HPD_SPIN_6:1;// B port, 1: high-z mode HPD, 0: TX mode UINT32 HPD_SPIN_7:1;// C port, 1: high-z mode HPD, 0: TX mode }; }; union { UINT32 reg0E8_0EB; struct { UINT32 Debug_Bit_A_Sel: 5; UINT32 reserved_b5: 1; UINT32 AUX_R_IO_CBUS_SELL: 2; UINT32 Debug_Bit_B_Sel: 5; UINT32 reserved_b13: 1; UINT32 AUX_R_IO_CBUS_SELH: 2; UINT32 Debug_Bit_C_Sel: 5; UINT32 reserved_b21: 1; UINT32 AUX_R_MLIOVREFISEL_b0_b1: 2; UINT32 Debug_Bit_D_Sel: 5; UINT32 reserved_b29: 1; UINT32 AUX_R_MLIOVREFISEL_b2_b3: 2; }; }; union { UINT32 reg0EC_0EF; struct { UINT32 Debug_Bit_E_Sel: 5; UINT32 reserved_b5_b7: 3; UINT32 Debug_Bit_F_Sel: 5; UINT32 reserved_b13_b15: 3; UINT32 Debug_Bit_G_Sel: 5; UINT32 AUX_R_CBUS_IO_SEL1: 1; UINT32 AUX_R_HPDIO_MAN_MODE: 1; UINT32 AUX_R_HPDIO_HDMI: 1; UINT32 Debug_Bit_H_Sel: 5; UINT32 AUX_R_CBUS_IO_SEL0: 1; UINT32 AUX_R_MHL_ACTIVE: 1; UINT32 AUX_R_CBUS_PDN: 1; }; }; UINT8 reg_F0_127[0x38]; union { UINT32 reg128_12B; UINT32 R_HDMISTC_INI_VALUE; }; union { UINT32 reg12C_12F; struct { UINT32 R_HDMISTC_ENA: 1; UINT32 R_HDMISTC_SPEED_SEL: 3; UINT32 R_MPEG_CH_SEL: 1; UINT32 R_AUDIO_SRC_TEST: 1; UINT32 R_AUDIO_SRC_SEL: 1; UINT32 reg12c_b07: 1; UINT32 R_HDMI_TMDSCLK_ENJ: 1; UINT32 R_HDMI_FUNCTEST: 1; UINT32 reg12c_b10_b31: 22; }; }; UINT8 reg130_14f[0x20]; union { UINT32 reg150_153; struct { UINT32 reserved_150_b0_b19: 20; UINT32 r_en_ARC_portA: 1; UINT32 r_en_ARC_portB: 1; UINT32 r_en_ARC_portC: 1; UINT32 r_en_ARC_portD: 1; UINT32 reserved_150_b24_b26: 3; UINT32 R_HDMIAC_SEL_D: 1; UINT32 R_HDMIAC_SEL_C: 1; UINT32 reserved_150_b29_b31: 3; }; }; UINT8 reg154_1AB[0x58]; union { UINT32 reg1AC_1AF; struct { UINT32 reserved_1AC_b0_b27: 28; UINT32 R_HPDIO_SEL: 3; UINT32 reserved_1AC_b31: 1; }; }; UINT8 reg1B0_214[0x65]; union { UINT8 reg215; struct { UINT8 reserved_215_b0_b7: 7; UINT8 R_DEMOD_PWDN_BG: 1; }; }; UINT8 reg216_227[0x12]; union { UINT32 reg228_22B; struct { UINT32 reserved_228_b0_b30: 31; UINT32 EN_AVI_V3: 1; }; }; UINT8 reg22C_253[0x28]; union { UINT32 reg254_257; struct { UINT32 reserved_254_b0_b23: 24; UINT32 R_BYPASS_MHL: 1; UINT32 R_DROP_LINE: 2; UINT32 R_DROP_POINT: 2; UINT32 reserved_254_b29_b30: 2; UINT32 R_HDMI_TMDS_CLK_DIV2_SRC: 1; }; }; } SYSTEM_REG; typedef struct __DDC_REG { UINT8 reg0000_0024[0x25]; union { UINT8 reg0025; struct { UINT8 PortA_Det5V_En:1; UINT8 Slave0Neg_tSUtHD:1; //I2C slave 0 negative setup/hold time support UINT8 unkown_0025_b2_b7:6; }; }; UINT8 reg0026_002b[0x06]; union { UINT8 reg002c_002d[0x02]; struct { UINT8 SlaveMMIOPush:1; UINT8 DDC_5V_in_count:4; //0: 1ms, 1: 125us, 2: 250us, 3: 500us, 4: 1ms, 5: 2ms, 6: 4ms, 7: 8ms, 8: 16ms, 9: 32ms, 10:64ms, 11: 100ms, else: 170ms UINT8 DDC_5V_out_count:4; //0: 170ms, 1: 125us, 2: 250us, 3: 500us, 4: 1ms, 5: 2ms, 6: 4ms, 7: 8ms, 8: 16ms, 9: 32ms, 10:64ms, 11: 100ms, else: 170ms UINT8 unkown_002c_002d_b9_bf:7; }; }; UINT8 reg002e_0030[0x03]; union { UINT8 reg0031; struct { UINT8 PortB_Det5V_En: 1; UINT8 Slave1Neg_tSUtHD:1; //I2C slave 1 negative setup/hold time support UINT8 unkown_0031_b2_b7:6; }; }; UINT8 reg0032_004e[0x1d]; union { UINT8 reg004f; struct { UINT8 PortA_Det5V_mode: 2; //00,11:detect SCL and SDA ; 01:detect SCL ; 10:detect SDA UINT8 PortB_Det5V_mode: 2; //00,11:detect SCL and SDA ; 01:detect SCL ; 10:detect SDA }; }; UINT8 reg0050_0073[0x24]; union { UINT8 reg0074_0077[0x4]; struct { UINT8 SlaveBaseAddr0:8 ; //The read/write base address of slave 0 UINT8 SlaveBaseAddr1:8 ; //The read/write base address of slave 1 UINT8 SlaveBaseAddr2:8 ; //The read/write base address of slave 2 UINT8 unkown_0077_b24_b31:8; }; }; UINT8 reg0078_008f[0x18]; union { UINT8 reg0090_0091[0x02]; struct { UINT8 Slave0_timeout :8; //I2C slave 0 non-idle timeout UINT8 Slave0_rd_block_cnt:8; //I2C slave 0 count of 128B blocks read }; }; UINT8 reg0092_0093[0x02]; union { UINT8 reg0094_0095[0x02]; struct { UINT8 Slave1_timeout :8; //I2C slave 1 non-idle timeout UINT8 Slave1_rd_block_cnt:8; //I2C slave 1 count of 128B blocks read }; }; UINT8 reg0096_0124[0x8f]; union { UINT8 reg0125; struct { UINT8 PortC_Det5V_En:1; UINT8 Slave3Neg_tSUtHD:1; //I2C slave 3 negative setup/hold time support UINT8 unkown_0125_b2_b7:6; }; }; UINT8 reg0126_012b[0x6]; union { UINT8 reg012c_012d[0x02]; struct { UINT8 Slave345_MMIOPush:1; UINT8 Slave345_DDC_5V_in_count:4; //0: 1ms, 1: 125us, 2: 250us, 3: 500us, 4: 1ms, 5: 2ms, 6: 4ms, 7: 8ms, 8: 16ms, 9: 32ms, 10:64ms, 11: 100ms, else: 170ms UINT8 Slave345_DDC_5V_out_count:4; //0: 170ms, 1: 125us, 2: 250us, 3: 500us, 4: 1ms, 5: 2ms, 6: 4ms, 7: 8ms, 8: 16ms, 9: 32ms, 10:64ms, 11: 100ms, else: 170ms UINT8 unkown_012c_012d_b9_bf:7; }; }; UINT8 reg012e_014e[0x21]; union { UINT8 reg014f; struct { UINT8 PortC_Det5V_mode: 2; //00,11:detect SCL and SDA ; 01:detect SCL ; 10:detect SDA UINT8 unkown_0142_b2_b7:6; }; }; UINT8 reg0150_0173[0x24]; union { UINT8 reg0174_0177[0x4]; struct { UINT8 SlaveBaseAddr3:8 ; //The read/write base address of slave 3 UINT8 SlaveBaseAddr4:8 ; //The read/write base address of slave 4 UINT8 SlaveBaseAddr5:8 ; //The read/write base address of slave 5 UINT8 unkown_0177_b24_b31:8; }; }; UINT8 reg0178_018f[0x18]; union { UINT8 reg0190_0191[0x02]; struct { UINT8 Slave3_timeout :8; //I2C slave 3 non-idle timeout UINT8 Slave3_rd_block_cnt:8; //I2C slave 3 count of 128B blocks read }; }; } DDC_REG; #pragma pack(pop) #define SYSTEM_MMIO_BASE 0xBE000000 static volatile SYSTEM_REG *sysreg = (SYSTEM_REG*)SYSTEM_MMIO_BASE; #define DDC_MMIO_BASE 0xBE060000 static volatile DDC_REG *ddcreg = (DDC_REG*)DDC_MMIO_BASE; void sysset_DDC_PortA_Det5V_En(BOOL en) { ddcreg->PortA_Det5V_En = en; } void sysset_DDC_PortB_Det5V_En(BOOL en) { ddcreg->PortB_Det5V_En = en; } void sysset_DDC_PortC_Det5V_En(BOOL en) { ddcreg->PortC_Det5V_En = en; } UINT8 sysget_DDC_non_idle_timeout(HDMI_PORT_T port) { if(HDMI_PORT_A == port){return ddcreg->Slave0_timeout;} if(HDMI_PORT_B == port){return ddcreg->Slave1_timeout;} if(HDMI_PORT_C == port){return ddcreg->Slave3_timeout;} return 0; } UINT8 sysget_DDC_rd_block_cnt(HDMI_PORT_T port) { if(HDMI_PORT_A == port){return ddcreg->Slave0_rd_block_cnt;} if(HDMI_PORT_B == port){return ddcreg->Slave1_rd_block_cnt;} if(HDMI_PORT_C == port){return ddcreg->Slave3_rd_block_cnt;} return 0; } UINT8 sysget_DDC_BaseAddr(HDMI_PORT_T port) { if(HDMI_PORT_A == port){return ddcreg->SlaveBaseAddr0;} if(HDMI_PORT_B == port){return ddcreg->SlaveBaseAddr1;} if(HDMI_PORT_C == port){return ddcreg->SlaveBaseAddr3;} return 0; } void sysset_hdmi_hpd_detection(void) { ddcreg->PortA_Det5V_En = 0; ddcreg->PortB_Det5V_En = 0; ddcreg->PortC_Det5V_En = 0; //For S2 P531 Only have DDC_SDA_%V_Det, sysreg->R_I2S_5VDET_SELJ = 1; //Port_A: //Be06004F[1:0] //00,11: detect SCL and SDA //01: detect SCL //10: detect SDA ddcreg->PortA_Det5V_mode = 2; //Port_B: //Be06004F[3:2] //00,11: detect SCL and SDA //01: detect SCL //10: detect SDA ddcreg->PortB_Det5V_mode = 2; //Be060025[0], port A // 0:disable 5V detection // 1:enable 5V detection ddcreg->PortA_Det5V_En = 1; ddcreg->Slave0Neg_tSUtHD = 1; //Be060031[0], port B // 0:disable 5V detection // 1:enable 5V detection ddcreg->PortB_Det5V_En = 1; ddcreg->Slave1Neg_tSUtHD = 1; //Port_C: //Be060142[1:0] //00,11: detect SCL and SDA //01: detect SCL //10: detect SDA ddcreg->PortC_Det5V_mode = 2; //Be060125[0], port C // 0:disable 5V detection // 1:enable 5V detection ddcreg->PortC_Det5V_En = 1; ddcreg->Slave3Neg_tSUtHD = 1; //be06002c[4:1] //in_count //0: 1ms, 1: 125us, 2: 250us, 3: 500us, 4: 1ms, 5: 2ms, 6: 4ms, 7: 8ms, 8: 16ms, 9: 32ms, 10:64ms, 11: 100ms, else: 170ms ddcreg->DDC_5V_in_count = 2; //SONY BDP-S360 SDA high period is about 290us, low period is about 300ms ddcreg->Slave345_DDC_5V_in_count= 2; sysreg->R_AUX_HDMIA_SW5V = 0; //SW 5V port A Level sysreg->R_AUX_EN_HDMIA_SW5V = 1; //SW 5V port A Enable sysreg->R_AUX_HDMIB_SW5V = 0; //SW 5V port B Level sysreg->R_AUX_EN_HDMIB_SW5V = 1; //SW 5V port B Enable sysreg->R_AUX_HDMIC_SW5V = 0; //SW 5V port C Level sysreg->R_AUX_EN_HDMIC_SW5V = 1; //SW 5V port C Enable } void sysset_hdmi_hpd_a(DRV_HPD_LEVEL_e eLevel) { if(eLevel == DRV_HPD_LEVEL_HIGH) { sysreg->R_AUX_HPD0_HIGH = 1; } else { sysreg->R_AUX_HPD0_HIGH = 0; } } void sysset_hdmi_hpd_b(DRV_HPD_LEVEL_e eLevel) { if(eLevel == DRV_HPD_LEVEL_HIGH) { sysreg->R_AUX_HPD1_HIGH = 1; } else { sysreg->R_AUX_HPD1_HIGH = 0; } } void sysset_hdmi_hpd_c(DRV_HPD_LEVEL_e eLevel) { sysreg->HPD_EN_PD_HPD = 0;//For 533 C port only HPD_P2 pull down enable 0/1 = disable / enable output low driver if(eLevel == DRV_HPD_LEVEL_HIGH) { sysreg->R_AUX_HPD2_HIGH = 1; } else { sysreg->R_AUX_HPD2_HIGH = 0; } } void sysset_hdmi_rst(BOOL bEnable) { sysreg->R_HDMI_RST = bEnable ? 1 : 0; } void sysset_hdmi_tmdsclk(BOOL bEnable) { sysreg->R_HDMI_TMDSCLK_ENJ = bEnable ? 1 : 0; } void sysset_hdmi_stcInitValue(UINT32 value) { sysreg->R_HDMISTC_INI_VALUE = value; } void sysset_hdmi_stcclk(void) { /* Enable HDMI stc clock */ sysreg->R_HDMISTC_ENA = 1; sysreg->R_MPEG_CH_SEL = 1; sysreg->R_AUDIO_SRC_TEST = 0; sysreg->R_AUDIO_SRC_SEL = 1; sysreg->reg12c_b07 = 0; } void sysset_cec_arc(BOOL enable) { sysreg->r_en_ARC_portA = enable ? 1 : 0; sysreg->r_en_ARC_portB = enable ? 1 : 0; sysreg->r_en_ARC_portC = enable ? 1 : 0; sysreg->r_en_ARC_portD = enable ? 1 : 0; if(enable) { *((u8 *)0xbe0f0650) = (*((u8 *)0xbe0f0650) &0xF7) | 0x08; //Set Bit:3 IO driving strength 1 for 0025759: [ARC]HEACT 5-12 Signal Amplitude Test } else { *((u8 *)0xbe0f0650) = (*((u8 *)0xbe0f0650) &0xF7) | 0x00; } } void sysset_cbus_port_sel(HDMI_PORT_T port) { switch (port) { case HDMI_PORT_A: sysreg->AUX_R_CBUS_IO_SEL0 = 0;//Select Port:A CBUS sysreg->AUX_R_CBUS_IO_SEL1 = 0;//Select Port:A CBUS break; case HDMI_PORT_B: sysreg->AUX_R_CBUS_IO_SEL0 = 1;//Select Port:B CBUS sysreg->AUX_R_CBUS_IO_SEL1 = 0;//Select Port:B CBUS break; case HDMI_PORT_C: sysreg->AUX_R_CBUS_IO_SEL0 = 0;//Select Port:C CBUS sysreg->AUX_R_CBUS_IO_SEL1 = 1;//Select Port:C CBUS break; default: break; } } void sysset_VbusEnable(BOOL en) { // 131 do not have Vbus Enable pin //0xbe0000e5[6] 533 sysreg->HPD_EN_PU_VBUS = 0;//533 GPIO's EN Set as GPO //0xbe0000e5[7] 533 sysreg->HPD_EN_PD_VBUS = en;//533 GPIO's A Set output value } void sysset_VbusToggle(void) { sysreg->R_CD_SENSE_ENA = 1; sysreg->R_CD_SENSE_SEL = 1; GPIOWriteFun(GPIO_0, 0); HDMI_DelayMs(1000); GPIOWriteFun(GPIO_0, 1); GPIOReadFun(GPIO_0); sysreg->R_CD_SENSE_SEL = 0; } BOOL sysset_Get_CD_SENSE_SEL (void) { BOOL CD_SENSE_SEL; CD_SENSE_SEL =sysreg->R_CD_SENSE_SEL; return(CD_SENSE_SEL); } void sysset_Set_CD_SENSE_VALUE(int cfg) { if(cfg == CD_SENSE_CFG_INTERNAL_HIGH) { sysreg->R_CD_SENSE_ENA = 1; sysreg->R_CD_SENSE_SEL = 1; } if(cfg == CD_SENSE_CFG_INTERNAL_LOW) { sysreg->R_CD_SENSE_ENA = 0; sysreg->R_CD_SENSE_SEL = 1; } if(cfg == CD_SENSE_CFG_EXTERNAL) { //sysreg->R_CD_SENSE_ENA = 0; sysreg->R_CD_SENSE_SEL = 0; } } #ifdef CONFIG_HDMI_SUPPORT_MHL extern BOOL MHL_CTS; #endif void sysset_HDMI_MHL_CBUS_EN_CTS_CTL(BOOL fEn) { #ifdef CONFIG_HDMI_SUPPORT_MHL if(CONFIG_HDMI_MHL_PORT==0) { if(MHL_CTS==TRUE) { // 1K sysreg->HPD_P0_EN_DIS_CTL0= 1; sysreg->HPD_P0_EN_DIS_CTL1= 1; sysreg->HPD_P0_EN_DIS_CTL2= 0; sysreg->HPD_P0_EN_DIS_CTL3= 0; // 100k sysreg->R_CBUS_EN_P0_CTL_0= 1; sysreg->R_CBUS_EN_P0_CTL_1= 1; sysreg->R_CBUS_EN_P0_CTL_2= 1; sysreg->R_CBUS_EN_P0_CTL_3= 0; } else { // 1K sysreg->HPD_P0_EN_DIS_CTL0= 1; sysreg->HPD_P0_EN_DIS_CTL1= 1; sysreg->HPD_P0_EN_DIS_CTL2= 0; sysreg->HPD_P0_EN_DIS_CTL3= 0; // 100k sysreg->R_CBUS_EN_P0_CTL_0= 1; sysreg->R_CBUS_EN_P0_CTL_1= 1; sysreg->R_CBUS_EN_P0_CTL_2= 1; sysreg->R_CBUS_EN_P0_CTL_3= 0; } sysreg->R_CBUS_EN_P1_CTL_0= 1; sysreg->R_CBUS_EN_P1_CTL_1= 1; sysreg->R_CBUS_EN_P1_CTL_2= 1; sysreg->R_CBUS_EN_P1_CTL_3= 1; sysreg->HPD_P1_EN_DIS_CTL0= 1; sysreg->HPD_P1_EN_DIS_CTL1= 1; sysreg->HPD_P1_EN_DIS_CTL2= 1; sysreg->HPD_P1_EN_DIS_CTL3= 1; } else if(CONFIG_HDMI_MHL_PORT==1) { sysreg->R_CBUS_EN_P0_CTL_0= 1; sysreg->R_CBUS_EN_P0_CTL_1= 1; sysreg->R_CBUS_EN_P0_CTL_2= 1; sysreg->R_CBUS_EN_P0_CTL_3= 1; sysreg->HPD_P0_EN_DIS_CTL0= 1; sysreg->HPD_P0_EN_DIS_CTL1= 1; sysreg->HPD_P0_EN_DIS_CTL2= 1; sysreg->HPD_P0_EN_DIS_CTL3= 1; if(MHL_CTS==TRUE) { // 1K sysreg->HPD_P1_EN_DIS_CTL0= 1; sysreg->HPD_P1_EN_DIS_CTL1= 1; sysreg->HPD_P1_EN_DIS_CTL2= 0; sysreg->HPD_P1_EN_DIS_CTL3= 0; // 100k sysreg->R_CBUS_EN_P1_CTL_0= 1; sysreg->R_CBUS_EN_P1_CTL_1= 1; sysreg->R_CBUS_EN_P1_CTL_2= 1; sysreg->R_CBUS_EN_P1_CTL_3= 0; } else { // 1K sysreg->HPD_P1_EN_DIS_CTL0= 1; sysreg->HPD_P1_EN_DIS_CTL1= 1; sysreg->HPD_P1_EN_DIS_CTL2= 0; sysreg->HPD_P1_EN_DIS_CTL3= 0; // 100k sysreg->R_CBUS_EN_P1_CTL_0= 1; sysreg->R_CBUS_EN_P1_CTL_1= 1; sysreg->R_CBUS_EN_P1_CTL_2= 1; sysreg->R_CBUS_EN_P1_CTL_3= 0; } } #endif } void sysset_Cbus_Init(void) { sysreg->R_CBUS_DRV_PD_P0= 1; sysreg->R_CBUS_DRV_PD_P1= 1; sysreg->R_CBUS_DRV_PD_P2= 2;//331 control VBUS's DRV sysreg->R_CBUS_DRV_P0= 1; sysreg->R_CBUS_DRV_P1= 1; sysreg->HPD_DRV_1_0_VBUS=2;//533 control VBUS's DRV sysreg->R_CBUS_VREF_SEL= 1; sysreg->R_CBUS_SR_PD= 0;//20140813 Enable 331A1 ECO for MHL CTS 4.3.10.2 //sysreg->R_CBUS_PD_SEL= 0; sysreg->AUX_R_CBUS_VREF_PD= 0; sysreg->AUX_R_CBUS_VREF_TN= 1; sysreg->AUX_R_IO_CBUS_SELH= 1;//20170214 ECO for MHL CTS 4.3.13.1 & 4.3.16.1 sysreg->AUX_R_IO_CBUS_SELL= 0; sysreg->R_CBUS_EN_P1_CTL_3= 1; sysreg->R_CBUS_EN_P0_CTL_3= 1; //sysreg->R_CBUS_EN_P2_CTL_2= 0; //sysreg->R_CBUS_EN_P2_CTL_1 = 0;//Set as GPO //sysreg->R_CBUS_EN_P2_CTL_0 = 0;//Set output value //*((u8 *)0xbe0f0628) = (*((u8 *)0xbe0f0628)&0xFE) | 0x1 ;//For CD-SENSE current leakage issue, PDE1A1J IN P331, NPDE1A1J IN P531. PDE1A1J CAN'T SET PD =1 IN INPUT MODE /* CBUS Resistance Setting */ //sysreg->R_ATE_Z_DISCOVER = 1; //sysreg->R_ATE_Z_SINK = 0; //sysreg->R_CD_SENSE_ENA = 1; if(GPIOGetValueByPinFunc(GPIO_PIN_MHL_CD_SENSE_DETECT)==0) { sysset_VbusEnable(0); } #ifdef CONFIG_HDMI_MHL_PORT sysset_HDMI_MHL_CBUS_EN_CTS_CTL(FALSE); #else sysreg->R_CBUS_EN_P0_CTL_0= 0; sysreg->R_CBUS_EN_P0_CTL_1= 0; sysreg->R_CBUS_EN_P0_CTL_2= 0; sysreg->R_CBUS_EN_P0_CTL_3= 0; sysreg->R_CBUS_EN_P1_CTL_0= 0; sysreg->R_CBUS_EN_P1_CTL_1= 0; sysreg->R_CBUS_EN_P1_CTL_2= 0; sysreg->R_CBUS_EN_P1_CTL_3= 0; #endif } void sysset_HDMI_Downscale(BOOL en) { sysreg->R_BYPASS_MHL = en; } void sysset_HDMI_HPD_1K_Init(void) { #ifdef HDMI_HPD_USE_1K_OHM sysreg->R_CBUS_DRV_P0= 1; sysreg->R_CBUS_DRV_P1= 1; sysreg->R_CBUS_DRV_P2= 3; #else sysreg->R_CBUS_DRV_P0= 1; sysreg->R_CBUS_DRV_P1= 1; sysreg->R_CBUS_DRV_P2= 3; #endif } void sysset_HDMI_HPD_1K_OnOff(HDMI_PORT_T ePort, BOOL fOn) { if(ePort == HDMI_PORT_A) { if(fOn == TRUE) //sysreg->R_CBUS_DRV_P0= 0; sysreg->HPD_SPIN_0= 0; else //sysreg->R_CBUS_DRV_P0= 2;//For MHL CBus driving sysreg->HPD_SPIN_0= 1;//For HPD driving } else if(ePort == HDMI_PORT_B) { if(fOn == TRUE) //sysreg->R_CBUS_DRV_P1= 0; sysreg->HPD_SPIN_1= 0; else //sysreg->R_CBUS_DRV_P1= 2;//For MHL CBus driving sysreg->HPD_SPIN_1= 1;//For HPD driving } else if(ePort == HDMI_PORT_C) { if(fOn == TRUE) //sysreg->R_CBUS_DRV_P2= 0; sysreg->HPD_SPIN_2= 0; else //sysreg->R_CBUS_DRV_P2= 2;//For MHL CBus driving sysreg->HPD_SPIN_2= 1;//For HPD driving } } void sysset_HDMI_HPD_HIGH_Z_MODE(HDMI_PORT_T ePort, BOOL fOn) { if(ePort == HDMI_PORT_A) { if(fOn == TRUE) sysreg->HPD_SPIN_5= 1; else sysreg->HPD_SPIN_5= 0; } else if(ePort == HDMI_PORT_B) { if(fOn == TRUE) sysreg->HPD_SPIN_6= 1; else sysreg->HPD_SPIN_6= 0; } else if(ePort == HDMI_PORT_C) { if(fOn == TRUE) sysreg->HPD_SPIN_7= 1; else sysreg->HPD_SPIN_7= 0; } } void sysset_HDMI_SW5V(HDMI_PORT_T port, BOOL en) { printk("[H] %s port:%d=%d\n", __FUNCTION__, port, en); switch (port) { case HDMI_PORT_A: if(en == TRUE) //turn on portA SW 5V, turn off portA 5V detection { sysreg->R_AUX_HDMIA_SW5V = 1; //SW 5V port A Level sysreg->R_AUX_EN_HDMIA_SW5V = 1; //SW 5V port A Enable //ddcreg->PortA_Det5V_En = 0; //turn off DDC 5V detection } else //turn on portA 5V detection, turn off portA SW 5V { ddcreg->PortA_Det5V_En = 1; //turn on DDC 5V detection HDMI_DelayMs(10); sysreg->R_AUX_EN_HDMIA_SW5V = 0; //SW 5V port A Enable //sysreg->R_AUX_HDMIA_SW5V = 0; //SW 5V port A Level } break; case HDMI_PORT_B: if(en == TRUE) { sysreg->R_AUX_HDMIB_SW5V = 1; //SW 5V port B Level sysreg->R_AUX_EN_HDMIB_SW5V = 1; //SW 5V port B Enable //ddcreg->PortB_Det5V_En = 0; //turn off DDC 5V detection } else { ddcreg->PortB_Det5V_En = 1; //turn on DDC 5V detection HDMI_DelayMs(10); sysreg->R_AUX_EN_HDMIB_SW5V = 0; //SW 5V port B Enable //sysreg->R_AUX_HDMIB_SW5V = 0; //SW 5V port B Level } break; case HDMI_PORT_C: if(en == TRUE) { sysreg->R_AUX_EN_HDMIC_SW5V = 1; //SW 5V port C Enable sysreg->R_AUX_HDMIC_SW5V = 1; //SW 5V port C Level //ddcreg->PortC_Det5V_En = 0; //turn off DDC 5V detection } else { ddcreg->PortC_Det5V_En = 1; //turn on DDC 5V detection HDMI_DelayMs(10); sysreg->R_AUX_EN_HDMIC_SW5V = 0; //SW 5V port C Enable //sysreg->R_AUX_HDMIC_SW5V = 0; //SW 5V port C Level } break; default: break; } } void sysset_HDMI_MHL_CBus_OFF(void) { #ifdef CONFIG_HDMI_MHL_PORT if(CONFIG_HDMI_MHL_PORT==0) { sysreg->R_CBUS_DRV_PD_P0= 0; } else if(CONFIG_HDMI_MHL_PORT==1) { sysreg->R_CBUS_DRV_PD_P1= 0; } #endif } void sysset_HDMI_MHL_CBus_ON(void) { #ifdef CONFIG_HDMI_MHL_PORT if(CONFIG_HDMI_MHL_PORT==0) { sysreg->R_CBUS_DRV_PD_P0= 1; } else if(CONFIG_HDMI_MHL_PORT==1) { sysreg->R_CBUS_DRV_PD_P1= 1; } #endif } void sysset_DEMOD_BG_POWER_DOWN(BOOL fPD) { if(fPD == TRUE) sysreg->R_DEMOD_PWDN_BG= 1; else sysreg->R_DEMOD_PWDN_BG= 0; } void sysset_HDMI_EN_AVI_V3(BOOL bEnable) { sysreg->EN_AVI_V3 = bEnable ? 1 : 0; } void sysset_HDMI_CEC_DIODE_ON(void) { sysreg->R_CEC_DIODE_RES = 9; sysreg->R_CEC_DIODE_RES_PD = 0; } void sysset_Cbus_Z_CBUS_SINK_DISCOVER(INT8 cfg) { if(cfg==Z_CBUS_SINK_DISCOVER_CFG_HARDWARE_AUTO) { //sysreg->R_ATE_Z_DISCOVER = 0; sysreg->R_ATE_Z_DISCOVER_MUX_SEL = 0; } else if(cfg==Z_CBUS_SINK_DISCOVER_CFG_ON) { sysreg->R_ATE_Z_DISCOVER = 1; sysreg->R_ATE_Z_DISCOVER_MUX_SEL = 1; } else if(cfg==Z_CBUS_SINK_DISCOVER_CFG_OFF) { sysreg->R_ATE_Z_DISCOVER = 0; sysreg->R_ATE_Z_DISCOVER_MUX_SEL = 1; } } void sysset_Cbus_Z_CBUS_SINK_ON(INT8 cfg) { if(cfg==Z_CBUS_SINK_ON_CFG_HARDWARE_AUTO) { //sysreg->R_ATE_Z_SINK = 0; sysreg->R_ATE_Z_SINK_MUX_SEL = 0; } else if(cfg==Z_CBUS_SINK_ON_CFG_ON) { sysreg->R_ATE_Z_SINK = 1; sysreg->R_ATE_Z_SINK_MUX_SEL = 1; } else if(cfg==Z_CBUS_SINK_ON_CFG_OFF) { sysreg->R_ATE_Z_SINK = 0; sysreg->R_ATE_Z_SINK_MUX_SEL = 1; } }