#ifndef _DRV_I2C_MAIN_H_
#define _DRV_I2C_MAIN_H_

#include <linux/module.h>
//#include <linux/devfs_fs_kernel.h>
#include <linux/cdev.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/ioctl.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/semaphore.h>
#include <linux/workqueue.h>
#include <asm/io.h>
#include <drv_i2c.h>
#include <drv_debug.h>

typedef void *	PVOID;

#define I2C_SOFTWARE_MODE_MASTER				1
#define I2C_HARDWARE_MODE_MASTER				2
#define I2C_MODE							I2C_HARDWARE_MODE_MASTER
/*******************************************************************************
*******************************************************************************/


#ifdef INIT_BY_KMF
#define DebugPrint(fmt,args...)				do{if(*pdbgconf1&DBGCFG_I2C) printk(KERN_DEBUG "[I2C]" fmt "\n",## args);}while(0)
#define DbgFunPrint(fmt,args...)			do{if(*pdbgconf1&DBGCFG_I2C) printk(KERN_DEBUG "[I2C]%s %i: " fmt "\n",__FUNCTION__,__LINE__,## args);}while(0)
#else
#define DebugPrint(fmt,args...)				printk(KERN_NOTICE "[I2C]" fmt "\n",## args)
#define DbgFunPrint(fmt,args...)			printk(KERN_NOTICE "[I2C]%s %i: " fmt "\n",__FUNCTION__,__LINE__,## args)
#endif

static inline INT32 cmd_list_is_last(const struct list_head *list,
				const struct list_head *head)
{
	return list->next == head;
}


#define MmioWriteFun(Address,Data)			writel(Data,(void *)(Address))
#define MmioReadFun(Address)				readl((void *)(Address))
#define MmioWriteWordFun(Address,Data)		writew(Data,(void *)(Address))
#define MmioReadWordFun(Address)			readw((void *)(Address))
#define mReadByteFun(Address)				readb((void *)(Address))
#define mWriteByteFun(Address,Data)			writeb(Data,(void *)(Address))

#define INTERRUPT_ENABLE					1
#define ONE_BYTE_INTERRUPT					0
#define SOFTWARE_MODE_MASTER				0

#define MASTER_A_IRQ_FINAL					58
#define MASTER_B_IRQ_FINAL					57


#define STATUS_SUCCESS						0
#define STATUS_DEVICE_ID_ERROR				1
#define STATUS_DATA_ERROR					2
#define STATUS_SYSTEM_ERROR					3

#define M0_CONTROL0							0xBE070000
#define M0_CONTROL1							0xBE070004
#define M0_DATA0							0xBE070008
#define M0_DATA1							0xBE07000C
#define M0_BASE_ADDRESS						0xBE070064
#define M0_DATA_LENGTH						0xBE07006C
#define M0_BUS_STATUS						0xBE070010

#define M1_CONTROL0							0xBE110000
#define M1_CONTROL1							0xBE110004
#define M1_DATA0							0xBE110008
#define M1_DATA1							0xBE11000C
#define M1_BASS_ADDRESS						0xBE110064
#define M1_DATA_LENGTH						0xBE11006C
#define M1_BUS_STATUS						0xBE110010

#define MX_CONTROL0_SCL_25K                 0x000000c0//0x00000020
#define MX_CONTROL0_SCL_100K				0x00000050//0x00000020
#define MX_CONTROL0_SCL_400K				0x0000000B//0x0000000D//0x0000800D
#define MX_CONTROL0_SCL_300K				0x00000010
#define MX_CONTROL0_SCL_200K				0x00000017
#define MX_CONTROL0_ASYNC_RESET				0x00020000
#define MX_CONTROL0_MASTER_EN				0x00800000
#define MX_CONTROL0_INT_EN					0x00400000 // Interrupt enable
#define MX_CONTROL0_ONE_BYTE_INT			0x00200000 // One Byte Interrupt
#define MX_CONTROL0_INT						0x04000000 // Interrupt bit
#define MX_CONTROL0_INT_CLEAR				0x08000000 // Interrupt bit clear
#define MX_CONTROL0_NO_ADDRESS				0x10000000 // Without base address
#define MX_CONTROL0_ADDR_INT_DISABLE			0x20000000 // disable base address interrupt
#define MX_CONTROL0_BUSY_WAIT_EN				0x80000000 //20110428 lwhite add

//#define I2C_BUS_STATUS_M0_BUSY				0x01000000
//#define I2C_BUS_STATUS_M1_BUSY				0x02000000
#define I2C_BUS_STATUS_BUSY				0x01000000

#define SW_MASTER0							0xBE070100
#define SW_MASTER1							0xBE070102
#define SW_MASTER_SCL_OUT					0x0001		// Useless
#define SW_MASTER_SDA_OUT					0x0002		// Useless
#define SW_MASTER_SCL_OUT_OEN				0x0004
#define SW_MASTER_SDA_OUT_OEN				0x0008
#define SW_MASTER_SCL_IN					0x0010
#define SW_MASTER_SDA_IN					0x0020
#define SW_MASTER_ENABLE					0x0040

#define SW_MASTER_100K						8	// udelay(8)
#define SW_MASTER_400K						2	// udelay(2)

#define MASTER_NUMBER						2
#define I2C_TIME_OUT						(jiffies+HZ/25)

typedef enum
{
	I2C_SPIN_LOCK_QUEUE=0,

	I2C_SPIN_LOCK_MAX
}I2C_SPIN_LOCK;

#if INTERRUPT_ENABLE
typedef struct _INTERRUPT_INFORMATION_
{
	UINT8*				pBuffer;
	UINT16				Length;
	UINT16				Completed;
	UINT8				bRead;
}INT_INFO,*PINT_INFO;
#endif

typedef struct _QUEUE_I2C_
{
	UINT8				Mx;
	UINT8				DeviceID;
	UINT8				AddrType;
	UINT8				Speed;
	UINT32				Address;
	struct list_head	list;
	UINT16				Length;
	UINT8				Data[1];
}QUEUE_I2C,*PQUEUE_I2C;

typedef struct _I2C_CMD_LIST_
{
	INT8					bRead;
	UINT8				Mx;
	UINT8				DeviceID;
	UINT8				AddrType;
	UINT8				Speed;
	UINT32				Address;
	struct list_head	list;
	UINT16				Length;
	UINT8				Data[1];
}I2C_CMD_LIST,*PI2C_CMD_LIST;

typedef struct _I2C_DEV_
{
	struct semaphore		I2cMutex[MASTER_NUMBER];
	struct semaphore		GPIOI2cMutex;
	struct semaphore		GPIOXI2cMutex;
	INT32						InterruptCounter[MASTER_NUMBER];
	struct cdev				cdev;
#if (I2C_MODE==I2C_HARDWARE_MODE_MASTER) && INTERRUPT_ENABLE
	struct completion		Comp[MASTER_NUMBER];
	//struct timer_list		ResetTimer[MASTER_NUMBER];
	INT_INFO				IntInfo[MASTER_NUMBER];
#endif
	UINT8					Status[MASTER_NUMBER];
	struct list_head		pQueueWriteList;
	struct workqueue_struct	*i2cWorkQueue;
	struct work_struct		QueueWork;
	spinlock_t				Spinlock[I2C_SPIN_LOCK_MAX];
}I2C_DEV,*PI2C_DEV;

#endif // end of #ifndef _DRV_I2C_MAIN_H_