UTS6710/aps/customer/s2tek/public/panel/QD15XR01_JTR150V2_1024X768/panel_setting.h

#define	PANEL_TYPE	QD15XR01_JTR150V2

/*******************************************************************************
* Power Sequence
********************************************************************************/
#define	PANEL_POWERENABLE_TO_LVDS_POWERON_T2	0
#define	PANEL_LVDS_DATAEN_TO_BLEN_T3	500
#define	PANEL_BLOFF_TO_LVDS_POWER_DOWN_T4	200
#define	PANEL_LVDS_POWER_DOWN_TO_PANEL_POWER_OFF_T5	12



/*******************************************************************************
* Panel Spec(DEC)
********************************************************************************/
#define	PANEL_PCLK	76.00
#define	PANEL_PCLK_PAL	47.00
#define	PANEL_PCLK_MAX	86.00
#define	PANEL_PCLK_MIN	50.00

#define	PANEL_WIDTH	1024
#define	PANEL_HEIGHT	768

#define	PANEL_MAX_HTOTAL	2048
#define	PANEL_TYP_HTOTAL	1572
#define	PANEL_TYP_HTOTAL_PAL	812
#define	PANEL_MIN_HTOTAL	1312

#define	PANEL_MAX_VTOTAL	875
#define	PANEL_TYP_VTOTAL	806
#define	PANEL_TYP_VTOTAL_PAL	1141
#define	PANEL_MIN_VTOTAL	784

//0: NoInvert, 1: Invert
#define	PANEL_INVERT	0
//0: NoSwap, 1: Swap
#define	PANEL_LVDS_SWAP	0
//1: Single, 2: Dual 
#define	PANEL_CHANNEL_NUM	1
//6: 6 bit, 8: 8 bit, 10: 10 bit, 12: 12 bit 
#define	PANEL_COLOR_DEPTH	8
//0: JEDIA, 1: VESA(LSB), 2: VESA(MSB)
#define	PANEL_LVDS_TYPE	2
//0: LVDS, 1: DP
#define	PANEL_INTERFACE	0
//0: H/VSyncEn(default), 1:H/VSyncDis
#define	PANEL_HVSYNC_EN	0
//0: High Active, 1: Low Active
#define	PANEL_HSYNC_POLARITY	0
//0: High Active, 1: Low Active
#define	PANEL_VSYNC_POLARITY	0
/*******************************************************************************
* Panel Setting
********************************************************************************/
//60Hz
#define	PANEL_PLL_REFDIV_60HZ	0
#define	PANEL_PLL_NDIV_60HZ	43
#define	PANEL_PLL_TXDIV_60HZ	1
#define	PANEL_PLL_FDDIV_60HZ	13

#define	PANEL_HSYNC_START_60HZ	1
#define	PANEL_HSYNC_END_60HZ	5
#define	PANEL_HVALID_START_60HZ	153
#define	PANEL_HVALID_END_60HZ	665

#define	PANEL_VSYNC_START_60HZ	1
#define	PANEL_VSYNC_END_60HZ	7
#define	PANEL_VVALID_START_60HZ	42
#define	PANEL_VVALID_END_60HZ	810

#define	PANEL_HTOTAL_60HZ	785
#define	PANEL_VTOTAL_60HZ	811
#define	PANEL_MAX_VTOTAL_60HZ	864


//50Hz
#define	PANEL_PLL_REFDIV_50HZ	0
#define	PANEL_PLL_NDIV_50HZ	43
#define	PANEL_PLL_TXDIV_50HZ	1
#define	PANEL_PLL_FDDIV_50HZ	13

#define	PANEL_HSYNC_START_50HZ	1
#define	PANEL_HSYNC_END_50HZ	5
#define	PANEL_HVALID_START_50HZ	153
#define	PANEL_HVALID_END_50HZ	665

#define	PANEL_VSYNC_START_50HZ	1
#define	PANEL_VSYNC_END_50HZ	7
#define	PANEL_VVALID_START_50HZ	42
#define	PANEL_VVALID_END_50HZ	810

#define	PANEL_HTOTAL_50HZ	785
#define	PANEL_VTOTAL_50HZ	970
#define	PANEL_MAX_VTOTAL_50HZ	1023


//48Hz
#define	PANEL_PLL_REFDIV_48HZ	0
#define	PANEL_PLL_NDIV_48HZ	0
#define	PANEL_PLL_TXDIV_48HZ	0
#define	PANEL_PLL_FDDIV_48HZ	0

#define	PANEL_HSYNC_START_48HZ	0
#define	PANEL_HSYNC_END_48HZ	0
#define	PANEL_HVALID_START_48HZ	0
#define	PANEL_HVALID_END_48HZ	0

#define	PANEL_VSYNC_START_48HZ	0
#define	PANEL_VSYNC_END_48HZ	0
#define	PANEL_VVALID_START_48HZ	0
#define	PANEL_VVALID_END_48HZ	0

#define	PANEL_HTOTAL_48HZ	0
#define	PANEL_VTOTAL_48HZ	0
#define	PANEL_MAX_VTOTAL_48HZ	0

/*******************************************************************************
* Panel Backlight Mapping
********************************************************************************/
//Hz
#define	PANEL_PWM_FREQ	200
//0 : NoInvert, 1 : Invert
#define	PANEL_BL_INVERT	0
//0 : NoRef VSync, 1 : RefVSync
#define	PANEL_PWM_REF_VSYNC	0
//0 : PixelClock, 1 : 24576KHz(default)
#define	PANEL_PWM_SRC	1

#define	PANEL_PWM_DUTY_MIN	20
#define	PANEL_PWM_DUTY_MAX	100

#define DYNAMICBACKLIGHT_OSD_MIN 20
#define DYNAMICBACKLIGHT_OSD_MAX 100
#define DYNAMICBACKLIGHT_OSD_NORMAL 86