UTS6710/boot/include/rom_def.h

#ifndef _ROM_DEF
#define _ROM_DEF

/*** ***********************************************************
*  rom_def.h
*
* 1. define all hw regsiter & system define here
* 2. compiler option please refer CCopts.h
*
************************************************************************/

/* REGs 0xbe00000x */
		#define SysAuxRegAddr				0xbe000000
		#define RevisionID_MMIOAddr 				0xbe000005
			#define RevisionID_A0						0x10
			#define RevisionID_A1						0x11
			#define RevisionID_B0						0x20
			#define RevisionID_C0						0x30
			#define RevisionID_C1						0x31
			#define RevisionID_CA						0x38

		#define PowerSequence_HWSetAddress					0xbe000008
			#define PowerSequence_SetMainPowerOnBit 			(1<<0)
			#define PowerSequence_ReadMainPowerOKBit			(1<<1)
			#define PowerSequence_SelectMainClk 					(1<<4)//(1<<2)
			#define PowerSequence_MainPowerResetStatus			(1<<3)
			#define PowerSequence_SetDRAMS3ContrlBit			(1<<29)//(1<<4)
			#define PowerSequence_SW_STM_EnableBit				(1<<5)
			#define PowerSequence_SW_WarmWatchDog_ExpiredBit	(1<<6)
		#if P330_8051
			#define PowerSequence_P330							(1<<11)
		#endif
			#define PowerSequence_Runtime_UpdateBit 			(1<<12)//(1<<7) // change CPU freq without Reset
		#define PwrRegsOffsetA				0xa
			#define AUX_R_SW_VDET_ENA						(1<<1)
			#define AUX_R_LDO_AUX_VCTL						(2<<2) //0=1v, 1=1.05v, 2=1.1v, 3=ivdd (531 a1)

		#define	HWDevResetMMIO						0xbe00000c
			#define	CPU1_RSTN_Bit							(1<<31)
			#define	UMCR_DIV_SYNR_RSTN_Bit					(1<<30)
			#define	SPI_RST_Bit								(1<<0)
            #define R_i2c_rst                               (1<<2)
			#define R_i2c_MASTER_MAIN_rst					(1<<6)
		#if P330_8051
			#define AUX_R_CPU0_RST							(1<<26)
		#endif
			#define	Aux_r_usbpll_rst						(1<<23)
			#define 	R_usb_utmi_rst							(1<<22)
			#define	R_usb_rst								(1<<18)
			#define	R_vip_rst								(1<<14)
			#define	R_umc_rst								(1<<13)
			#define 	R_ca_rst                                (1<<20)

/*REGs 0xbe00001x */
		#define	SPI_CTL_REG		0xbe000010
			#define 	SPI_Encrypt	(1<<1)


		#define	OFFSET_2		0x02
			#define 	SPI_CS1_DRV	(1<<4)
			#define 	SPI_CS0_DRV	(1<<3)
			#define	SPI_DO_DRV		(1<<2)
			#define 	SPI_DI_DRV	(1<<1)
			#define	SPI_CK_DRV		(1<<0)

		#define	UART_RX_REG	0xbe000014
			#define	UART_RX_PULLUPJ		(1<<1)
			#define	UART_RX_PULLLOW		(1<<2)

/*REGs 0xbe00002x */
		#define	DBG_PM	(0x20)
		#define R_F24576K_CLKDIV_RSTN	(15)
		#define R_F24576K_DIV	(16)

/*REGs 0xbe00003x */
		#define R_AUX_MISC 				0xbe000034
#if (CONFIG_CHIPID == 0x330)
			#define	AUX_R_LVDS_INI_PD						0xfff		//[11-0] 365 Aux-domain LVDS Power-Down bit; set '1' to power-down the LVDS
#endif
		#define R_AUX_MISC_38			0xbe000038
			#define AUX_R_SEL_24M_AS_PWMCLK			(1<<1)
			#define R_AUX_YPPFBI_AS_GPIO			(1<<6)	//1: Enable YPPFBI[1:0] as GPIO[44:43]

		#define SoftMMIO_UpdateMode					0xbe00003c
			#define Mode_F4_update						0x20
			#define Mode_F3_update						0x30
			#define Mode_F5_update 						0x50
			#define Mode_F6_update						0x60
			#define Mode_OTA_update						0x70
			#define Mode_PWR_update						0x80
			#define Mode_PowerPlusKeypad_update			0x90

/*REGs 0xbe00004x */
#if C0_count_delay
		#define	c0count_per_msec_reg				0xbe000040
#endif

		#define P8051_CEC_HANDLER_reg				0xbe000044
		// 0xbe000044, not use, /kernel/linux/drivers/net/sis190.c
		// 0xbe000048, not use, /kernel/linux/arch/mips/sis358/suspend.h
		#define SISPTF_REGISTER						0xbe00004c	// STORE_MSG_TO_USB

/*REGs 0xbe00005x */
	#define SoftwareMMIO_PowerSequenceStatus			0xbe000054
		#define reserve_54_0 									(1<<0)	//not use
		#define P330_Enable_OffEvent						(1<<3)
		#define PowerSequence_EntryOffEventFlag 			(1<<4)
#define SoftwareMMIO_PowerSequencesetACPlugIn			0xbe000055
			/* AC Plug -in  */
	#define   ACPlugIn_CheckFirstTimebit						(1<<0)
			/* Bootrin menu SoftwareMMIO_PowerSequencesetACPlugIn[3..1] */
	#define SoftwareMMIO_BootingMenu_CommandMask		(0xf<<1)
	#define BootingMenu_RunDebugShell						(8<<1)
	#define BootingMenu_DDRChange						(7<<1)
	#define BootingMenu_PanelSelection_Command				(6<<1)
	#define BootingMenu_UpdatedFlash_Command				(5<<1)
	#define BootingMenu_WiteMMIO_Command				(4<<1)
	#define BootingMenu_DramType_Command				(3<<1)
	#define BootingMenu_Memory_Command					(2<<1)
	#define BootingMenu_LoadLinux_Command				(1<<1)

/*REGs 0xbe000058[0]~[17] */
#define  REG_528			0xbe000058


#define  RTC_REG_526			0xbe0f0526

	/*REGs 0xbe00006x */
#define KMF_BR_NORFLASH_ADDRESS				(0xbe000068)	// 8051 will search kmf/bootrom share data flash addrss
	/*REGs 0xbe00008x */
#if Multi_Panelset
	#define Multi_Panelset_Reg		0xbe000084
#endif

#if RTC_REG_enable
	#define Kmf_Data_RTC_REG_L		(0xbe000088)
	#define Kmf_Data_RTC_REG_H		(0xbe00008c)
#endif

/* REGs 0xbe0000dx */
		#define SIS326_PwrSeqHWStatus_MMIOReg						0xBE0000DC
			#define SIS326_PwrSeqHWStatus_AuxCPU0Ready 			0x0000ffff
			#define SIS326_PwrSeqHWStatus_MainPwrReady			0x000f0000
			#define SIS326_PwrSeqHWStatus_MainPLLReady			0x00f00000
			#define SIS326_PwrSeqHWStatus_MainPLLLockReady		0x00100000
			#define SIS326_PwrSeqHWStatus_MCLKDLLReady			0x00200000
			#define SIS326_PwrSeqHWStatus_MainPowerOk			0x00020000
			#define SIS326_PwrSeqHWStatus_CPU1MemReady			0x0f000000
			#define SIS326_PwrSeqHWStatus_VIPAudioReady			0xf0000000
			#define SIS326_PwrSeqHWStatus_AuxCPU0Ready_Value 	0x00007777
			#define SIS326_PwrSeqHWStatus_MainPwrReady_Value	0x76477777//0x00077777
			#define SIS326_PwrSeqHWStatus_MainCLKSReady_Value	0x00577777 //0x00777777
			#define SIS326_PwrSeqHWStatus_UMCResetOK_Value		0x05577777 //0x05777777
			//#define SIS326_PwrSeqHWStatus_CPU1MemReady_Value	0x07777777
			#define SIS326_PwrSeqHWStatus_CPU1MemReady_Value	0x05577777 //0x05777777	// for A0 version : CPU1 reset invert
			#define SIS326_PwrSeqHWStatus_CPU1MemReady_Mask	0x07777777	// for A0 version : CPU1 reset invert
			#define SIS326_PwrSeqHWStatus_VIPAudioReady_Value	0x77577777//0x77777777

/* REGs 0xbe00010x */

		#define	R_StartAddress		0xbe000100
		#define	R_StartAddress_100	0xbe000100
			#define	R_Clk_MMIO_0x4		0x04			// Main PLL
			#define	R_Clk_MMIO_0x8		0x08			// Main DIV
			#define	R_Clk_MMIO_0xc		0x0c			// TSIO_CTRL & ICLK_DIV
			#define	R_Clk_MMIO_0x10	0x10
			#define	R_Clk_MMIO_0x14	0x14
			#define	R_Clk_MMIO_0x18	0x18
			#define	R_Clk_MMIO_0x1c	0x1C
			#define	R_Clk_MMIO_0x20	0x20
			#define	R_Clk_MMIO_0x4c	0x4c			//Main cpu Clock

			#define	SIFCLK_DIV_466		(0x18<<16)	//Audio
			#define	SIFCLK_DIV_533		(0x1C<<16)	//Audio
			#define	SIFCLK_DIV_608		(0x20<<16)
			#define	SIFCLK_DIV_663		(0x23<<16)
			#define	SIFCLK_DIV_700		(0x25<<16)
			#define	SIFCLK_DIV_740		(0x27<<16)
			#define	SIFCLK_DIV_9861_750		(0x27<<16)	// 1.5G / DIV
		#if Media_TV_Only	//media TV
			#define	SIFCLK_DIV_MEDIA_480		(0x19<<16)	//Audio
			#define	SIFCLK_DIV_MEDIA_497		(0x1a<<16)	//Audio
			#define	SIFCLK_DIV_MEDIA_516		(0x1b<<16)
		#endif
			#define VCLK_DIV		(4<<16)
			#define VCLK_DIV_800	(3<<16)
			#define VCLK_DIV_1008	(3<<16) //SiS9565 H.265
			#define VCLK_DIV_1179	(4<<16)
			#define VCLK_DIV_1352	(5<<16) //org(5<<16) 2011.08.17 H/W recommend
			#define VCLK_DIV_1548	(6<<16) //SiS9861 H.264
        #ifdef CONFIG_PLL_FRACTIONAL_MODE
			#define YPP_ADC_DIV	    (0x1d<<16) 
        #else
			#define YPP_ADC_DIV	    (0x1d<<16) 
        #endif

			#define NFCLK_DIV_RSTN		(0x1<<31)

			#define NFCLK_DIV_800		(0xe<<24)
			#define NFCLK_DIV_1008		(0xe<<24)//(0xb<<24)
			#define NFCLK_DIV_1179		(0xe<<24)
			#define NFCLK_DIV_1352		(0x10<<24)
			#define NFCLK_DIV_1548		(0xa<<24)

			#define CARDRCLK_DIV_800	0x15
			#define CARDRCLK_DIV_1008	0x15
			#define CARDRCLK_DIV_1179	0x15
			#define CARDRCLK_DIV_1352	0x1a
			#define CARDRCLK_DIV_1548	0x1f

			#define BCRCLK_DIV_9861 	0x1f

			#define	R_BLTCLK_DIV		24
			#define BLTCLK_DIV_83		(0x83)
			#define BLTCLK_DIV_84		(0x84)
			#define BLTCLK_DIV_85		(0x85)
			#define BLTCLK_DIV_86		(0x86)

		#define MIAN_DIV   						0xbe000108
			#define	CCLK_DIV_330_4				(0x03)
			#define	CCLK_DIV_330_3				(0x02)
			#define	CCLK_DIV_330_2				(0x01)
					/* DDR-800 CPU0 DIV */
			#define	CCLK_DIV_330_800_405		(0x01)		//811/(1+1)=405.504MHz
					/* DDR-1008 CPU0 DIV */
			#define	CCLK_DIV_330_1008_252		(0x03)		//1008/(3+1)=252.0MHz
			#define	CCLK_DIV_330_1008_336		(0x02)		//1008/(2+1)=336.0MHz
					/* DDR-1179 CPU0 DIV */
			#define CCLK_DIV_330_1179_236       	(0x04) 		//1179/(4+1)=235.8MHz
			#define CCLK_DIV_330_1179_295		(0x03)		//1179/(3+1)=294.75MHz
			#define CCLK_DIV_330_1179_393       	(0x02) 		//1179/(2+1)=393MHz
					/* DDR-1352 CPU0 DIV */
			#define CCLK_DIV_330_1352_225		(0x05)		//1352/(5+1)=225.3MHz
			#define CCLK_DIV_330_1352_270		(0x04)		//1352/(4+1)=270.4MHz
			#define CCLK_DIV_330_1352_338		(0x03)		//1352/(3+1)=338.0MHz
			#define CCLK_DIV_330_1352_450		(0x02)		//1352/(2+1)=450.6MHz
					/* DDR-1400 CPU0 DIV */
			#define CCLK_DIV_330_1400_350		(0x03)		//1400.832/(3+1)=350.208MHz
					/* DDR-1548 CPU0 DIV */
			#define CCLK_DIV_330_1548_221		(0x06)		//1548/(6+1)=221.143MHz

			#define	CCLK_DIV_VALID		(1<<7)
			#define	CCLK_DIV_MAIN_RST	(1<<5)

				/* 0xbe000108[6:0] CPUCLK_POST_DIV */
			#define CPU_CLK_DIV_RSTN			(1<<7)
				/* 0xbe000108[14:8] MMIOCLK_POST_DIV */
			#define	MMIO_CLK_DIV_9				(0x8<<8)	//[14~8]
			#define	MMIO_CLK_DIV_10				(0x9<<8)	//[14~8]
			#define	MMIO_CLK_DIV_11				(0xa<<8)	//[14~8]
			#define	MMIO_CLK_DIV_12				(0xb<<8)	//[14~8]
			/* 0xbe000108[16:20] ECLK_POST_DIV */
			#define	ECLK_DIV_9					(0x8<<16)	//[22~16]
			#define	ECLK_DIV_12				(0xb<<16)	//[22~16]
            /* 0xbe000108[23] R_CPU_CLK_MUX_SEL */
            #define R_CPU_CLK_MUX_SEL           (0x1<<23)
			/* 0xbe000108[28:24] SPICLK_POST_DIV */
#ifdef CONFIG_SUPPORT_ROMTER
			#define	SPICLK_DIV_9				(0x1f<<24)	//[30~24]
			#define	SPICLK_DIV_800				(0x1f<<24)
			#define	SPICLK_DIV_1008				(0x1f<<24)	//[30~24]
			#define	SPICLK_DIV_1179				(0x1f<<24)
			#define	SPICLK_DIV_1352				(0x1f<<24)
			#define	SPICLK_DIV_1400				(0x1f<<24)
			#define	SPICLK_DIV_1548				(0x1f<<24)
#else
			#define	SPICLK_DIV_9				(0x8<<24)	//[30~24]
			#define	SPICLK_DIV_12				(0xb<<24)	//[30~24]
			#define	SPICLK_DIV_800				(0x7<<24)
			#define	SPICLK_DIV_1008				(0xa<<24)	//[30~24]
			#define	SPICLK_DIV_1179				(0xb<<24)
			#define	SPICLK_DIV_1352				(0xc<<24)
			#define	SPICLK_DIV_1400				(0xc<<24)
			#define	SPICLK_DIV_1548				(0xf<<24)
#endif
			#define	ICLK_DIV_Mask	(0x1ff<<0)	// be00010c bit[8:0]
			#define	ICLK_DIV_Reset1	(1<<12)	//SiS365 Option be00010c bit[12]
			#define	ICLK_DIV_Reset2	(1<<13)	//SiS365 Option be00010c bit[13]
			#define	ICLK_DIV_Reset3	(1<<9)	//SiS365 Option be00010c bit[9]

			#define	ICLK_RSTN		(1 << 23)	// be0001b0 bit[23]
			#define	R_IPCLK_DIV		(24)
			#define IPCLK_DIV_800  	(0x04)
			#define IPCLK_DIV_5  	(0x04)
			#define IPCLK_DIV_1008  (0x05)
			#define IPCLK_DIV_1179  (0x05)
			#define IPCLK_DIV_1352	(0x06)
			#define IPCLK_DIV_1548	(0x08)


			#define VIPX2ICLK_DIV_5    (0x04)
			#define VIPX2ICLK_DIV_800  (0x04)
			#define VIPX2ICLK_DIV_1008 (0x05)
			#define VIPX2ICLK_DIV_1179 (0x05)
			#define VIPX2ICLK_DIV_1352 (0x06)
			#define VIPX2ICLK_DIV_1548 (0x08)

/* REGs 0xbe00011x */
		#define	CLKFrq_Detection_SetAddr				0xbe000113	//clk det
#if (CONFIG_CHIPID == 0x131) || (CONFIG_CHIPID == 0x8506) || (CONFIG_CHIPID == 0x6710)
			#define	CLKFrq_CPU0_Detection				0xba//0x10
			#define	CLKFrq_CPU1_Detection				0x18//0x92
			#define	CLKFrq_ECLK_Detection				0x28
			#define	CLKFrq_LVDSDCLK_Detection			0x58
			#define	CLKFrq_MCLK_Detection				0x38//0xA0 is for the AUDIOCLK
			#define	CLKFrq_SPICLK_Detection				0xF8
			#define	CLKFrq_MMIOCLK_Detection			0x3a
			#define	CLKFrq_HSD_CLK_Detection			0xca
#else
			#define	CLKFrq_CPU0_Detection				0xb2//0x10
			#define	CLKFrq_CPU1_Detection				0x10//0x92
			#define	CLKFrq_ECLK_Detection				0x20
			#define	CLKFrq_LVDSDCLK_Detection			0x50
			#define	CLKFrq_MCLK_Detection				0x30//0xA0 is for the AUDIOCLK
			#define	CLKFrq_SPICLK_Detection				0xF0
			#define	CLKFrq_MMIOCLK_Detection			0x32
			#define	CLKFrq_HSD_CLK_Detection			0xc2
#endif


		#define R_LVDS_PHY								0x1c
			#define	R_BLTCLK_DIV_RSTN				(31)
			#define R_LVDS_PWDL 						(1<<13) // MainPwr-domain LVDS(L) Power-Down bit; 0: normal, 1: power down
			#define R_LVDS_PWDR 						(1<<12) // MainPwr-domain LVDS(R) Power-Down bit; 0: normal, 1: power down
		#define R_LVDS_PLL								0xbe000120	//LVDS_PLL
			#define R_LVDS_PLL_PWDN 					(1<<26) 	//LVDS_PLL_PWDN
		#define R_AU_DIVA_DIVB							0x30
			#define SIFCLK_POST_DIV 					(0x1ff<<16)
/* REGs 0xbe00012x */
		#define R_LVDS_Mapping					0x24
		#define	R_HDMI_TEST								0x2c
			#define	R_VCLK_div_rstn						(1<<25)
/* REGs 0xbe00013x */
		#define R_Audio_IO_Reg						0x3c
			#define R_I2S_MCKO_OEJ			(1<<0)
			#define R_I2S_OEJ				(1<<8)
			#define R_I2S_SD0_OEJ			(1<<18)
			/* REGs 0xbe000130 */
			#define	AU_BRCLK_POST_DIV	(0)
			#define	R_AU_DIVA_RSTN		(11)
/* REGs 0xbe00014x */
		#define R_ROSC_MMIO 						0xbe000140
			#define R_ROSC_ENA								(1<<0)
/* REGs 0xbe00015x */
		#define	R_DDRDLL_TSIO				0x54
		#define	MCLK_DIV_YPP200M			0x58
		#define	MCLK_DIV_YPP200M_RSTN	(1<<7)
/* REGs 0xbe00018x */
		#define	R_GTJ						0x80
			#define R_GTJ_I2SMCK			(1<<21)
		#define R_MEMSDM					0x88
		#define R_AUDIO						0x88
		#define R_MCLK						0x8c
			#define	MCLK_DIV_5				(4)
			#define	MCLK_DIV_6				(5)
			#define	MCLK_DIV_7				(6)
			#define	MCLK_DIV_8				(7)
			#define	R_MCLK_DIV_RSTN			(11)
			#define R_APLL_DIVATV_DIV	(16)
			#define	R_URCLK_DIV				(16)
			#define	R_URCLK_DIV_RSTN		(23)
			#define	R_APLL_DIVATV_RSTN	(24)
/* REGs 0xbe00019x */
		#define	DMOD						0x94
			#define	R_EN_DMJTAG				(1<<18)
		#define GMAC									0xbe000198
			#define R_XRMII50M_OEJ					(1<<9)
			#define GMACIO_DRVP 						(0x01<<16)
			#define GMACIO_DRVN 					(0x01<<24)
/* REGs 0xbe0001ax */
		#define MEMPLL   					0xa4
		#define R_MEM_SDMMAX				0xa8
		#define PLL_PHY   					0xac
		#define	U_MEM_DIV_RSTN			(1<<13)
			#define	R_LVDS_PLL_PWDN		(1<<26)		//LVDS_PLL_PWDN
			#define	R_MAIN_CLKDIV_RSTN		(1<<31)
/* REGs 0xbe0001bx */
		#define	R_IPCLK						0xb4
		#define	R_CPUPLL					0xb8
			#define	CPUPLL_MUL_9861_750			0xc322202c//0xc966203b //0xe788003c	//750MHz
			#define	CPUPLL_MUL_9861_884			0xc9662023	// (35+1)*24.576 = 884.736
		#define 	CPUBCLK  						0xbc
			#define	R_CPLL_PDIV_RSTN			(1 << 2)
			#define	R_CPLL_RSTN				(1 << 1)
			#define	R_CPLL_PWDN				(1 << 0)
			#define	R_MAIN2CPLL_SEL			(1 << 14)
			#define	CPUBCLK_POST_DIV		(16)
			#define CPUCLK_DIV_2 	 	(0x01)
			#define CPUCLK_DIV_3 	 	(0x02)
			#define CPUCLK_DIV_4 	 	(0x03)
			#define CPUCLK_DIV_5 	 	(0x04)

			#define CPUBCLK_DIV_RST  	 	 	(0x01<<23)

			#define R_MAIN2CPLL_RST 			(1<<15)

/* REGs 0xbe0001cx */
			#define	CLKFrq_Detection_GetValueaddr		0xbe0001c0  	//clk det

		#define	R_StartAddress_200					0xbe000200
/* REGs 0xbe00021x */
/* REGs 0xbe00022x */
		#define R_HSDCLK_SDCLK_DLY					0xbe000220
			#define R_HSDCLKDLY_RST 					(1<<22)
			#define R_HSDCLKDLY_ENA 					(1<<20)
		#define R_HDMITX							0x28
		#define U_DEMOD_49M_DIV				0x2c
		#define U_DEMOD_49M_DIV_RSTN	(1<<8)
/* REGs 0xbe00024x */
		#define R_DPLL								0x40
			#define R_VDEC_ROSCK_DIV2					(1<<31)
			#define R_VDEC_SEL_ROSCK					(1<<30)
			#define R_VDEC_ROSCK_CTRL_RSTN				(1<<29)
			#define R_VDEC_ROSCK_RSTN					(1<<28)
			#define R_UCCP_ROSCK_CTRL_RSTN				(1<<13)
			#define	R_UCCP_ROSCK_RSTN					(1<<12)
			#define R_UCCP_ROSCK_TGT					(0x1ff)
		#define	R_VDEC								0x42

		#define R_CCLK_ROSCK						0x44
			#define R_CCLKB_SEL_ROSCK					(1<<15)
			#define R_CCLKA_SEL_ROSCK					(1<<14)
			#define R_CCLKA_ROSCK_CTRL_RSTN				(1<<13)
			#define R_CCLKA_ROSCK_RSTN					(1<<12)
			#define R_CCLKA_ROSCK_TGT					(0x1ff)

		#define R_LDO								0x4c
			#define R_LDO_Mask							(0xff)
			#define R_CPU_LDO_PWDE_ENJ					(1<<7)
			#define R_CPU_LDO_PWD_ENJ					(1<<6)
			#define R_LVDS_LDO_PWDE_ENJ 				(1<<3)
			#define R_LVDS_LDO_PWD_ENJ					(1<<2)
			#define R_MEM_LDO_PWDE_ENJ					(1<<1)
			#define R_MEM_LDO_PWD_ENJ					(1<<0)


/* REGs 0xbe00025x */
		#define R_LVDS_CH0							0x58
			#define R_LDO_BGDIV_Mask					(0xf<<28)
#if (CONFIG_CHIPID == 0x131) || (CONFIG_CHIPID == 0x8506) || (CONFIG_CHIPID == 0x6710)
			#define R_LDO_BGDIV						(0xa<<28)
#elif (CONFIG_CHIPID != 0x330)
			#define R_LDO_BGDIV						(0x2<<28)
#else
			#define R_LDO_BGDIV						(0x9<<28)	// make VBG12OUT=1.2V for MEMPLL working under the correct voltage
#endif
			#define R_LDO_BGDIVB_Mask					(0xf<<24)
#if (CONFIG_CHIPID == 0x131) || (CONFIG_CHIPID == 0x8506) || (CONFIG_CHIPID == 0x6710) 
			#define R_LDO_BGDIVB						(0x8<<24)
#else
			#define R_LDO_BGDIVB						(0xc<<24)
#endif
#if (CONFIG_CHIPID != 0x330)
    #if (CONFIG_CHIPID != 0x533)
		#define R_LVDS_PDCTL						0x25c	//0xbe00025c
    #else
        #define R_LVDS_PDCTL						0xec	//0xbe0000ec
    #endif
			#define	_R_LVDS_PD						0x3fff		//[13-0]  LVDS Power-Down bit
#endif
/* REGs 0xbe0100xx */
		#define 	HOST_MMIO_Address		0xbe010000
			#define CPU1_Initoffset		0x00c
			#define DDRA_Size_Offset		0x130
				#define 	HOST_CHA_DRAM_NA		0x0
				#define 	HOST_CHA_DRAM_64M	0x01
				#define 	HOST_CHA_DRAM_128M	0x02
				#define 	HOST_CHA_DRAM_256M	0x04
				#define 	HOST_CHA_DRAM_512M	0x08
			#if(CONFIG_DRAMSIZE == 128)
				#define 	HOST_CHA_DRAM_SIZE	HOST_CHA_DRAM_128M	//set CHA 512M for shadow memory.(0x9axx)
			#elif(CONFIG_DRAMSIZE == 64)
				#define 	HOST_CHA_DRAM_SIZE	HOST_CHA_DRAM_64M	//set CHA 512M for shadow memory.(0x9axx)
			#elif(CONFIG_DRAMSIZE == 256)
				#define 	HOST_CHA_DRAM_SIZE	HOST_CHA_DRAM_256M	//set CHA 512M for shadow memory.(0x9axx)
			#endif

	#define CPU0_InterruptRequestEnable1_MMIOAddress		0xbe010100
	#define CPU0_InterruptRequestEnable2_MMIOAddress		0xbe010104
		#define 	CEC_INT_Enablebit			(1 << (34 - 32))
		#define 	HDMI_INT_Enablebit			(1 << (35 - 32))
		#define GPIO_INT_Enablebit		(1 << (44 - 32))
		#define IRQ_CPU0_CNT			(1 << (47 - 32))
		#define UART_INT_Enablebit		(1 << (53 - 32))
		#define IR_INT_Enablebit			(1 << (59 - 32))	//(1<<(42-32))
		#define IRQ_TIMER0			(1 << (61 - 32))
		#define 	IRQ_AUDIO_SW			(1 << (63 - 32))
	#define CPU1_InterruptRequestEnable1_MMIOAddress		0xbe010108
	#define CPU1_InterruptRequestEnable2_MMIOAddress		0xbe01010C
		  /* Virtual Interrupt and Priority */
	#define CPU_InterruptPriority1_MMIOAddress		0xbe010110
	#define CPU_InterruptPriority2_MMIOAddress		0xbe010114
		  /* Software Controller Interrupt . i.e. driving Interrupt by software */
	#define CPU0_SWControllerInterrupt1_MMIOAddress 		0xbe010118
	#define CPU0_SWControllerInterrupt2_MMIOAddress 		0xbe01011C
	#define CPU1_SWControllerInterrupt1_MMIOAddress 		0xbe010120
	#define CPU1_SWControllerInterrupt2_MMIOAddress 		0xbe010124
		 /* Shadow set setting */
	#define Interrupt_ShadowSet_EICSS_MMIOAddress			0xbe010128
	#define CPU0_ShadowSet_EICSS							1
	#define CPU1_ShadowSet_EICSS							(1<<8)

	/*Memory CTL	*/
	#define MEMORY_CTL_REG_BASE 		0xbe020000
		#define r_chX_cke_ena			(1<<4)	//CKE mode :0: force low / 1: normal

/*REGs 0xbe02xxxx */
	#define DRAM_330_size_reg		0xbe020910

/*REGs 0xbe06xxxx */
	#define EDID_BaseAddress	0xbe060000
	#define EDID_slave0_ID		0xbe060024

/*REGs 0xbe0axxxx */
	#define FlashMMIO_BaseAddress						0xbe0a0000
	#define FlashMMIO_FlashEndaddr					0xbe0a00c0
	#define FlashMMIO_Status							0xbe0a0080
		#define   FlashMMIO_INTDriverBit						(1<<7)
	#define FlashMMIO_DRAMAddr						0xbe0a0060
	#define FlashMMIO_FlashAddr 						0xbe0a0040
	#define FlashMMIO_Command						0xbe0a0020
	#define FlashMMIO_Fired 							0xbe0a00e0
		#define FlashMMIO_DefaultValue						0x00000018
		#define FlashMMIO_ReadID							0x05170018
		#define FlashMMIO_DMA_FtoD						0x0b170018
		#define FlashMMIO_DMA_DtoF						0x0a170018
		#define   FlashMMIO_Erase							0x03170018
		#define   FlashMMIO_ChipErase						0x04170018
		#define   FlashMMIO_NullOperation						0x00170018
		#define FlashMMIO_ClearINT							0x00170098

		#define FlashMMIO_Protect_ClearINT					0x00100098
		#define FlashMMIO_UnProtect_ClearINT				0x00170098

		#define FlashMMIO_ProtectSection				((0x0e)<<8)
						/* 0xbe0a:0020[14..8]
							0x0e: All
							0x0c: Upper 1/2 flashsize
							0x0a: Upper 1/4 flashsize
							0x08: Upper 1/8 flashsize
							0x06: Upper 1/16 flashsize
							0x04: Upper 1/32 flashsize
							0x02: Upper 1/64 flashsize
							0x00: None
						*/
		#define FlashMMIO_ProtectCMD					(0x06104018+ FlashMMIO_ProtectSection)
		#define FlashMMIO_UnProtectCMD					0x06170018

		#define FlashMMIO_ProtectCMD_Part1					(0x06100018+ FlashMMIO_ProtectSection)
		#define FlashMMIO_ProtectCMD_Part2					(0x06104018+ FlashMMIO_ProtectSection)
		#define FlashMMIO_UnProtectCMD_Part1					0x06170e18
		#define FlashMMIO_UnProtectCMD_Part2					0x06170018
		#define FlashMMIO_ProtectCheck_Part1				0x07170018		// Magic add for NOR flash protect check

    		// Data Flash
		#define FlashMMIO_DataFlash_ProtectSection				((0x0e)<<8)
						/* 0xbe0a:0020[14..8]
							0x0e: All
							0x0c: Upper 1/2 flashsize
							0x0a: Upper 1/4 flashsize
							0x08: Upper 1/8 flashsize
							0x06: Upper 1/16 flashsize
							0x04: Upper 1/32 flashsize
							0x02: Upper 1/64 flashsize
							0x00: None
						*/
		#define FlashMMIO_DataFlash_ProtectCMD		(0x06204018+FlashMMIO_DataFlash_ProtectSection)
		#define FlashMMIO_DataFlash_ProtectCMD_Part1		(0x06200018+FlashMMIO_DataFlash_ProtectSection)
		#define FlashMMIO_DataFlash_ProtectCMD_Part2		(0x06204018+FlashMMIO_DataFlash_ProtectSection)

		#define FlashMMIO_DataFlash_UnProtectCMD		0x06270018
		#define FlashMMIO_DataFlash_UnProtectCMD_Part1		0x06270e18
		#define FlashMMIO_DataFlash_UnProtectCMD_Part2		0x06270018
		#define FlashMMIO_DataFlash_DMA_FtoD					0x0b270018
		#define FlashMMIO_DataFlash_DMA_DtoF					0x0a270018
		#define   FlashMMIO_DataFlash_Erase 					0x03270018
		#define   FlashMMIO_DataFlash_ChipErase 				0x04270018
		#define   FlashMMIO_DataFlash_NullOperation 			0x00270018

		#define FlashMMIO_DataFlash_ClearINT					0x00270098
		#define FlashMMIO_DataFlash_Protect_ClearINT		0x00200098
		#define FlashMMIO_DataFlash_UnProtect_ClearINT		0x00270098
		#define FlashMMIO_DataFlash_ReadID					0x05270018
		#define FlashMMIO_DataFlash_DefaultValue				0x00000018

/*REGs 0xbe0dxxxx */
		#define	UART_BASE	0xbe0d0000
		#define	UART_00		0x00
		#define	UART_04		0x04
		#define	UART_08		0x08
		#define	UART_09		0x09
			#define	UartTxPushLow		(1<<6)
		#define	UART_0c		0x0c
		#define	UART_10		0x10
		#define	UART_14		0x14
		#define	UART_18		0x18
		#define	UART_1c		0x1c



/*REGs 0xbe0f010x */

		#define PWM0_PeriodReg					0xbe0f0100
		#define PWM1_PeriodReg					0xbe0f0108
		#define PWM2_BackLightLevel_PeriodReg		0xbe0f0110
		#define PWM3_BackLightLevel_PeriodReg		0Xbe0f0118

		#define PWM0_CtrlReg						0xbe0f0104
		#define PWM1_CtrlReg						0xbe0f010c
		#define PWM2_BackLightLevel_CtrlReg 		0xbe0f0114
		#define PWM3_BackLightLevel_CtrlReg 		0xbe0f011c
			#define PWM_Enable_Bit					(1 << 31)	// 0: disable pwm, 1: enable pwm
			#define PWM_Inverse_Bit 					(1 << 30)	// set 1 to inverse the pwm output waveform
			#define PWM_Duty_Mask				0x3fffffff	// 1 unit = 40.69 ns (using 24.576MHz clock)
			// NOTE : The LED Light twinkle frequency = PWM_Period_Value / PWM_Duty_Value

		#define PWM3_Reserved_PeriodReg 			0xbe0f0118
		#define PWM3_Reserved_CtrlReg			0xbe0f011c

/*REGs 0xbe0f020x */
		#define TMR0_CtrlReg		0xbe0f0200
		#define TMR1_CtrlReg		0xbe0f0204
		#define TMR2_CtrlReg		0xbe0f0208
			#define TMR_Active_EN	(1<<31)
			#define TMR_AutoLoad_EN	(1<<30)
			#define TMR_Int_EN		(1<<29)
			#define TMR_IntClear	(1<<28)
		#define TMR2_CountOutReg	0xbe0f0210

/*REGs 0xbe0f030x */
		#define WDT_MMIO				0xbe0f0000
		#define WDT0_Control_Offset 	0x300
			#define WDT0_DisableBit 	(1<<31)
			#define WDT0_RefreshBit 	(1<<30)
			#define WDT1_RefreshBit 	(1<<29)
			#define WDT2_RefreshBit 	(1<<28)

		#define WDT1_Control_Offset 	0x304
			#define WDT1_EnableBit				(1<<31)
			#define WDT1_TimeoutSelBit			(3<<29)
				#define WDT1_TimeoutSel 		(3<<29) /* 1:Warm Reset, 2:Cold Reset, 3: RTC Reset*/
				#define WDT1_WarmReset		0x20000000	// (1<<29)
				#define WDT1_ColdReset		0x40000000	// (2<<29)
				#define WDT1_RTCReset		0x60000000	// (3<<29)
			#define WDT1_CountDownValueBit	(0x1fffffff<<0)
				#define WDT1_CountDownValue (0x100<<0)	 /* Unit: u(s) , 1u~6 hours*/

		#define WDT2_Control_Offset 	0x308
			#define WDT2_EnableBit				(1<<31)
			#define WDT2_TimeoutSelBit			(3<<29)
				#define WDT2_TimeoutSel 		(3<<29) /* 1:Warm Reset, 2:Cold Reset, 3: RTC Reset*/
				#define WDT2_WarmReset		0x20000000	// (1<<29)
				#define WDT2_ColdReset		0x40000000	// (2<<29)
				#define WDT2_RTCReset		0x60000000	// (3<<29)
			#define WDT2_CountDownValueBit	(0x1fffffff<<0)
				#define WDT2_CountDownValue (0x100<<0)	 /* Unit: m(s) , 1m to 6.2 days*/

		#define WDT3_Control_Offset 	0x30C
			#define WDT3_WarmReset	0xD123ABCD
			#define WDT3_ColdReset		0xE123ABCE
			#define WDT3_RTCReset		0xF123ABCF




/*REGs 0xbe0f050x */
		#define RTC_REG_500 	0xbe0f0500	//free now
		#define RTC_REG_504 	0xbe0f0504	//freenow
		#define RTC_REG_508 	0xbe0f0508	//free now
		#define RTC_REG_50c 	0xbe0f050c	//free now

/* REGs 0xbe0f051x */
		#define UMF_flag			0xbe0f0510
			#define CEC_data0			0x0
			#define CEC_data1			0x1
			#define RTC_WakeUpdata	0x2 //free now.
			#define UMF_flag_Misc		0x3 //free now.


		#define RebootCounter					0xbe0f0514
		#define RTC_REG_518 					0xbe0f0518//free now
		#define RTC_REG_51c 					0xbe0f051c//free now

/* REGs 0xbe0f052x */
		#define  Aux_Non_Volatitle_Address				0xbe0f0520
			#define  WDT_ColdRest_Flag						(1<<0)
			#define  UMF_USB_update 						(1<<1) //UMF will set 1 and do USB-update
			#define  WDT_ColdRest							(1<<2) //1:ColdRest/0:No ColdRest
			#define  OTA_update_flag						(1<<3)
			#define  AC_PlugIn_FirstTime					(1<<4) //for UMF to check AC_PlugIn_FirstTime or not
			#define  PowerSequence_WaitVGASyncEnableFlag	(1<<5) //UMF set this flag if idle power off @ PC source
			#define  BootingMenu_1Time_Enable				(1<<6)//F2
			#define  AutoPowerOn_1Time_Enable				(1<<7)
		#define  OnEvent_INT_Status_MMIOAddress 		0xbe0f0521
			#define  Special_FileBit0						(1<<0)
			#define  Special_FileBit1						(1<<1)
			#define  OnEvent_INT_OnEventStatusBit			(1<<7)	//==> 0X set by the UMF if the Kernel turns off normally
			#define  OnEvent_INT_VGASyncDrivingBit			(1<<6)	// set by the UMF if the Kernel turns off from the VGA (PC mode) source normally, but.. why we need this?
		#define  OffEvent_INT_Status_MMIOAddress		0xbe0f0522
			#define  OffEvent_INT_OnEventStatusBit			(1<<7)	// set to record the power-on request; checked and read by both the BootROM & the UMF
			#define  OffEvent_INT_VGASyncDrivingBit 		(1<<6)	// set to record the VGA-WakeUp request; checked and read by the UMF
			#define  OffEvent_INT_CECDrivingBit 			(1<<5)
			#define  OffEvent_INT_AndroidUpdate_DrivingBit	(1<<4)
			#define  OffEvent_INT_RTCWakeUpDrivingBit		(1<<3)
			#define  OffEvent_INT_PWRBTNDrivingBit			(1<<2)
			#define  OffEvent_INT_UARTDrivingBit			(1<<1)	// Press 'F1' to trigger the "Pwr-On-with-Default-Setting" mode
			#define  OffEvent_INT_IRDrivingBit				(1<<0)
		#define  RTC_REG_523							0xbe0f0523
			#define  SilentUpdate 							(1<<0)	// silence power check booting
			#define  CEC_8051_OneTouchPlayEnable			(1<<1)	//8051 enable one touch play if set
			#define  SpecialFileCheckBit					(1<<2)	// silence power check booting
			#define  FAC_UPDTAE_AP_Bit						(1<<3)	// silence power check booting
			#define  DirectBootAfterUpdate					(1<<4)	// if update success then direct bootup
			#define  AGING_TEST_DONE_BIT                    (1<<5)  // if aging test done than set this bit
			#define  IO_on_USB_BIT                    		(1<<6)  // if boot by L1, read/write data on usb (not flash)
			#define  FAC_REMOTE                    			(1<<7)  
		#define  RTC_REG_524						0xbe0f0524
			#define  CodeCompleteCheckBit					(1<<0)	//
			//#define  EnforceResetBit							(1<<1)	//
			#define  RebootDoneBit							(1<<2)	//
            #define  MIPSStandbyModeBit         			(1<<3)
			#define  Keypad0CheckBit         				(1<<4)
			#define  Keypad1CheckBit         				(1<<5)
			#define  KeypadIntCheckBit       			  	(1<<6)
		#define  RTC_REG_526						0xbe0f0526
			#define  HdmiAWakeup							(1<<0)	//
			#define  HdmiBWakeup							(1<<1)	//
			#define  HdmiCWakeup							(1<<2)	//
			#define  BootingLogo							(1<<3)	//
			#define  UsingNand							(1<<4)
			#define  NandSysUpdate						(1<<5)
			#define  VGAWakeup						(1<<6)
			#define  AC_FACTORY						(1<<7)
			#define PowerSequence_ModeMask	0x6
#ifdef CONFIG_SUPPORT_SYSTEM_STANDBYTIME
		#define  RTC_REG_527						0xbe0f0527
		    /* [0:7] 1 bytes for store offtime ; time conut unit:30 minutes */
#endif
/* REGs 0xbe13xxxx */

		#define USB_MMIO_StartAddr					0xbe138000
			#define USB_OHCI_IOConfig_Value				0x00002000
			#define USB_PHY0								0xbe0001ac
			#define USB_PHY								0xbe0001b4
			#define USB_XHCI_OPTION					0xbe00024c
			/* USB EHCI I/O configuration */	// 20080520
			#define	USB_EHCI_IOConfig1_MMIOAddr			0xbe128044
			#define	USB_EHCI_IOConfig1_Value		0x08000060
			#define	USB_EHCI_IOConfig2_MMIOAddr			0xbe128048
			#define	USB_EHCI_IOConfig2_Value		0x0c35296f//0x003AADD6//0x0012ADD6
			#define USB_EHCI_IOConfig3_MMIOAddr			0xbe12804c
			#define USB_EHCI_IOConfig3_Value 		0x0000e370
#if (CONFIG_CHIPID == 0x131 || CONFIG_CHIPID == 0x8506 || CONFIG_CHIPID == 0x6710)
			#define USB_HOST_CLK                    0x00007530//30MHz
#endif

/* REGs 0xbe1cxxxx */
		#define BRVIP_BASE_ADDRESS					0xbe1c0000

/* FLASH 0xbc000000 */
		#define 	CodeFlash_Redir_BaseAddress			0xBC000000
		#define	SysConfigs		0xbc000000	//SysCon_Cur_FlashStarAddr
			#define 	SysCon_DRAMFrq			0x28
			#define 	SysCon_MCLK_DIV 		0x29
			#define 	SysCon_CPUBCLK			0x2a
			#define 	SysCon_TGT				0x2b
			#define 	SysCon_MEMPLL			0x2c
			#define 	SysCon_CPLL				0x30
			#define 	SysCon_SSC1 			0x34
			#define 	SysCon_SSC2 			0x36
			#define 	SysCon_MAIN_DIV 		0x38

			#define 	SysCon_R_ICLK_POST_DIV	0x3c
			#define 	SysCon_R_IPCLK_DIV		0x3d
			#define 	SysCon_R_CARDRCLK_DIV	0x3e
			#define 	SysCon_R_BLTCLK_DIV 	0x3f

			#define 	SysCon_PHY_00			0x40
			#define 	SysCon_PHY_04			0x44
			#define 	SysCon_PHY_08			0x48
			#define 	SysCon_PHY_0c			0x4c

			#define 	SysCon_PHY_10			0x50
			#define 	SysCon_PHY_14			0x54
			#define 	SysCon_PHY_18			0x58
			#define 	SysCon_PHY_1C			0x5c
			#define 	SysCon_MCTL_00			0x60
			#define 	SysCon_MCTL_04			0x64
			#define 	SysCon_MCTL_110 		0x68
			#define 	SysCon_MCTL_200 		0x6c
			#define 	SysCon_MCTL_208 		0x70
			#define 	SysCon_MCTL_210 		0x74
			#define 	SysCon_MCTL_20f 		0x78
			#define 	SysCon_PHY_16			0x79
			#define 	SysCon_EDQS_LOOP		0x7a	
			#define 	SysCon_MCTL_300 		0x7c

/* FLASH 0xbc010000 */
		#define 	VersionAddress				0xBC010020	/* version @ 8051 */

#if 0
		#define  OptionData_StartAddr						0xbc040080
			#define OptionData_LED_PWM_Addr 					(OptionData_StartAddr + 0x1e5)
				#define OptionData_LED_PWM_INV_Offset					7

			#define  OptionData_LED_GPIO_Addr						(OptionData_StartAddr + 0x1e4)
				#define  OptionData_LED_GPIO_INV_Offset 				7

			#define  Custom_IR_StartAddr							(OptionData_StartAddr)
				#define  Custom_IR_Protocol 							0x0 	/* Byte: */
				#define  Custom_IR_Pwr0Addr 							0x1 	/* Byte: */
				#define  Custom_IR_Pwr0Data 							0x2 	/* Byte: */
				#define  Custom_IR_Pwr1Addr 							0x3 	/* Byte: */
				#define  Custom_IR_Pwr1Data 							0x4 	/* Byte: */
			#if IR_EXTEND
				#define  Custom_IR_Pwr0Addr_								0x5 	/* Byte: */
				#define  Custom_IR_Pwr1Addr_								0x6 	/* Byte: */
			#endif
			#define  Custom_LED_StartAddr							(OptionData_StartAddr + 0x499)
			#define  Custom_LED_ShadowAddr						(OptionData_ShadowAddr + 0x499)
				#define  Custom_LED_EntryOFF							0x0 	/* Byte: */
				#define  Custom_LED_OFF 								0x2 	/* Byte: */
				#define  Custom_LED_EntryOn 							0x4 	/* Byte: */
				#define  Custom_LED_SysCon_LED_Custom_LED_DPMSON	0x5 	/* Byte: */
				#define  Custom_LED_LogoOn								0x6 	/* Byte: */
				#define  Custom_LED_EntryLinux							0x8 	/* Byte: */
				#define  Custom_LED_AllReady							0xa 	/* Byte: */
				#define  Custom_LED_ColorMask								0xc0	//0xf0 ?
				#define  Custom_LED_Green									0x80
				#define  Custom_LED_Red 									0x40
				#define  Custom_LED_Orange									(Custom_LED_Green | Custom_LED_Red)
				#define  Custom_LED_PeriodLevelMask 						0x0f
				#define  Custom_LED_PeriodLevelMax							Custom_LED_PeriodLevelMask


			#define  Custom_HDMI_info									(OptionData_StartAddr + 0x4c3)
			#define  Custom_HDMISwitchMap								0x0 	/* Byte: */
			#define  Custom_HDMIPortMap 								0x1 	/* WORD: */
#endif

/* FLASH 0xbc080000 */

		//#define KMFBR_ShareData_StartAddress		0xbc085400

/* FLASH 0xbc0d0000 */


/* Dram:  0xa0000000 */
	//audio comq buffer, overlap bootrom code. carefuly use it. gaia
	#define CMDQ_INFO_ADDR						(0xa0000200)	//#define SISCMDQ_INFO_ADDR	(0xba00d800)
		#define  AUDIO_RESERVED_MEM_reg_reg 			0xbe090200	//2013.09.24 audio rom get reserve memory address from this reg

/* Dram: Shadow 0x9a000000 (please remove it later)*/
	#define	CPU0_ISR_Address_cached				0x80050000
	#define	CPU1_ISR_Address_cached				0x80051000
	#define	CPU0_ISR_Address					0xa0050000
	#define	CPU1_ISR_Address					0xa0051000

/* Dram: Shadow 0x9a010000 (please remove it later)*/
	#define RESERV					0xa0052000
	#define RESERV2					0xa0052004

/* Dram: Shadow 0x9a010000 (please remove it later)*/
			/* CPU1 Ready Flag */
	#define	CPU_SyncStatus					0xa0052100//0xba010148
		#define	CPU1_Status_AudioCodeReady			(1<<0)
		#define	CPU1_Status_EnterLinux			(1<<1)	//
		#define CPU1_Status_LoadKernelReady			(1<<2)	// Magic 2011.10.03
		#define	CPU1_Status_MoveKernelFromNandOK	(1<<3)	// TH 2012.0515
		#define	CPU1_Status_SecondLogoDisplay		(1<<4)


	#define MEMSIZE_INFO_ADDR			0xa0052108//0xba026078	// the address of the memory size info (which is saved by the BootLoader/BootROM)
		#define PANELSIZE_INFO_ADDR 		0xa0052109//0xba026079	// the address of the panel size info (which is saved by the BootLoader/BootROM)
		#define BOARD_INFO_ADDR 		0xa005210b//0xba02607b	// the address of the board info (which is saved by the BootLoader/BootROM)
		#define PROJECTID_ADDR			0xa005210c//0xba02607c	// the address of the Project ID of current kernel version (which is saved by the BootLoader/BootROM)
		//#define AUDIO_RESMEM_ADDR		0xa0032110//0xba026090// the address of the data - "Address of the Reserved Memory for the AudioROM"
			#define AUDIO_RESMEM_DEFAULT_ADDR	(RMEM_START_ADDR+0xa0000000)	// default uncached address of the reserved memory for the AudioROM

		#define CPU1_ShutdownSync			0xa0052114//0xba026094
		#define KNL_INITRD_ADDR 				0xa005211c//0xba02609c	//(SysCon_Cur_MemStarAddr + SysCon_KNL_InitRDAddr)	// the address of the unpacked initramfs cpio data for the Kernel
			#define LOGO_SHOW_BUF_SIZE		5888*1200//8294400 //2015.11.18 (1920 x 1080) x 4 = 8294400 , totally four buffers, Y,U,V,UV
			#define LOGO_SHOW_BUF 	(((CONFIG_DRAMSIZE)*1024*1024)-LOGO_SHOW_BUF_SIZE + 0xa0000000)//0xa3753000	// default address of the unpacked initramfs cpio data for the Kernel
			/* INITRD | LOGO_BUF ( |<END>*/
	#define BootParameter_AudioAddress				0xa0052120//0xba011000
		#define BootParameter_AudioStatus				0x0
		#define BootParameter_AudioMemStartaddress		0x4
		#define BootParameter_AudioMemUsingSize 		0x8
		#define BootParameter_AudioISREntryAddress		0xc
		#define BootParameter_AudioROM_GP			0x10
		#define BootParameter_AudioROM_SP			0x14

/* Dram: Shadow 0x9a020000 (please remove it later)*/

	#define  OptionData_ShadowAddr				0xa0052200//0x9a062000
		#define OptionData_Size					SPI_OPTION_DATA_SIZE
		#define OptionData_GPIO_ShadowAddr				(OptionData_ShadowAddr + 0xa4)	//SysCon_Cur_FlashStarAddr
		#define OptionData_GPIO_USAGE_ShadowAddr		(OptionData_GPIO_ShadowAddr + 0x100)
			#define GPIO_MainEnable								(1<<5)
			#define GPIO_MainMode								(1<<6)
			#define GPIO_MainValue								(1<<7)
			#define GPIO_MainInternalPU							(1<<0)
			#define GPIO_MainInternalPD							(1<<1)
		#define Option_IRset_ShadowAddr			(OptionData_ShadowAddr + 72)	// 0~71 Aus GPIO table
	#if 0
		#define Option_GreenLED_ShadowAddr		(Option_IRset_ShadowAddr + 0x90)
		#define Option_RedLED_ShadowAddr		(Option_IRset_ShadowAddr + 0x91)
		#define Option_LEDOnStatus_ShadowAddr	(Option_IRset_ShadowAddr + 0x92)
		#define Option_LEDOffStatus_ShadowAddr	(Option_IRset_ShadowAddr + 0x93)
		#define Option_PanelPWROnGPIONum_ShadowAddr		(Option_IRset_ShadowAddr + 0x94)
		#define Option_PanelBackLightGPIONum_ShadowAddr	(Option_IRset_ShadowAddr + 0x95)
		#define Option_PanelPWMNum_ShadowAddr			(Option_IRset_ShadowAddr + 0x96)
		#define Option_DVD_IROUT_GPIO_NO				(Option_IRset_ShadowAddr + 0x97)
	#endif

	#define PanelSet_ShadowAddress				0xa0053000//0xba062c00

	//todo: tel drive, do it self #define SPI_HDCPKEY_SHADOWADDR				0x9a069800

	#define	kernel_header_ShadowAddress			0xa0053800//0xba076200
	#define KMFBR_ShareData_ShadowAddress		0xa0053880//0xba076000	//todo, search algorithm
#if 0
		#define AlarmAddr0		 						0x0c
		#define UMF_EnableUARTA					(KMFBR_ShareData_ShadowAddress + 0x09)	// 0xbc0ba009		// 2011.11.10
		#define UMF_HideBootLogo				(24)	// hide logo while HideBootLogo==0x62
		#define UMF_LVDSEnable					(25)
		#define UMF_LVDSFormat					(0x1c)	// 1c-3f
		#define UMF_PwmFreq						(0x40)
#endif
	/* VIP Table */
	#define	VipTable_ShadowAddress				(KMFBR_ShareData_ShadowAddress + 256)//0xa0054000
		#define VipTable_ShadowSize					(160*1024)
	/* Gamma Table */
	#define GammaTable_ShaodwAddress				(VipTable_ShadowAddress+VipTable_ShadowSize)//0xa0072000
		#define GammaTable_ShaodwSize				(13*1024)
	/* ColorLUT Table */
	#define ColorLUTTable_ShadowAddress			(GammaTable_ShaodwAddress+GammaTable_ShaodwSize)//0xa0075400	
		#define ColorLUTTable_ShaodwSize				(256*1024)
	#define SPI_EDID_ShadowAddress			(ColorLUTTable_ShadowAddress + ColorLUTTable_ShaodwSize)//0xa00c5400
		#define SPI_EDID_ShaodwSize				(1*1024)
	#define SPI_HDCPKEY_ShadowAddress			(SPI_EDID_ShadowAddress + SPI_EDID_ShaodwSize)//0xa00c5800
		#define SPI_HDCPKEY_ShaodwSize				(1*1024)
	#define SPI_Custable_ShadowAddress			(SPI_HDCPKEY_ShadowAddress + SPI_HDCPKEY_ShaodwSize)//0xa00c5c00


#ifndef CONFIG_GCOV_KERNEL_SUPPORT
		#ifdef CONFIG_CHIP_8501
			#define SIM_MALLOC_POOL1_START			0xa0700000	//after kernel (about 9M)
		#else
			#define SIM_MALLOC_POOL1_START			0xa0a00000	//after kernel (about 9M)
		#endif
#else
		 #define SIM_MALLOC_POOL1_START                  0xa0d00000
#endif
#ifdef CONFIG_SUPPORT_TCON
		#define SIM_MALLOC_POOL2_START			0xa1300000	//skip 0xa0100000 + knl core size (about 6M) + audio rom (1.5M) + TCON (1.5M) 
#else		
		#define SIM_MALLOC_POOL2_START			0xa1200000	//skip 0xa0100000 + knl core size (about 6M) + audio rom (2M)
#endif
		#define SIM_MALLOC_POOL1_SIZE			(0xa1000000 - SIM_MALLOC_POOL1_START)	//before audio rom

	#define 	AudioInitStartEntryAddress				0x81000000//0x9a0f0000	// cached



/* MIPS flash address */
#define Booting_BaseAddress					0xBFC00000
#define Booting_CachedBaseAddress			0x9FC00000
#define Shadow_NonCacheBaseAddress		0xBA000000
#define Shadow_BaseAddress					0x9A000000


#define 	DMA512M_Mask			0x1fffffff		//MIPS 512M limit mask (CHIP >= 9565 )

//#define	_sp						(0x80000000+2048)	//2k
#define _ROUND_UP( dividend, divisor ) ( ( (dividend) + (divisor-1) ) / (divisor) )
#define ROUND_64K_ALIGNMENT( dividend ) ( _ROUND_UP( dividend, 64*1024 )*64*1024 )

#define __cpu0     __attribute__((__section__(".cpu0.text")))
#define __cpu0_data     __attribute__((__section__(".cpu0.data")))

#endif