UTS6710/boot/include/rom_macro.h

/*** ***********************************************************
*  rom_macro.h
*  
* 1. define all macros here
* 
* 
************************************************************************/
#ifndef _ROM_MACRO
#define _ROM_MACRO
#ifdef __ASSEMBLY__
#include <rom_def.h>

#define BIT00   (1<<0)
#define BIT01   (1<<1)
#define BIT02   (1<<2)
#define BIT03   (1<<3)
#define BIT04   (1<<4)
#define BIT05   (1<<5)
#define BIT06   (1<<6)
#define BIT07   (1<<7)
#define BIT08   (1<<8)
#define BIT09   (1<<9)
#define BIT10   (1<<10)
#define BIT11   (1<<11)
#define BIT12   (1<<12)
#define BIT13   (1<<13)
#define BIT14   (1<<14)
#define BIT15   (1<<15)
#define BIT16   (1<<16)
#define BIT17   (1<<17)
#define BIT18   (1<<18)
#define BIT19   (1<<19)
#define BIT20   (1<<20)
#define BIT21   (1<<21)
#define BIT22   (1<<22)
#define BIT23   (1<<23)
#define BIT24   (1<<24)
#define BIT25   (1<<25)
#define BIT26   (1<<26)
#define BIT27   (1<<27)
#define BIT28   (1<<28)
#define BIT29   (1<<29)
#define BIT30   (1<<30)
#define BIT31   (1<<31)

#define AUX_BASE_USE_REG s0
#define MAIN1_BASE_USE_REG s1
#define MAIN2_BASE_USE_REG s2
#define ROM_DATA_BASE_USE_REG s3
#define DRAM_PHY_BASE_USE_REG s4
#define DRAM_CTRL_BASE_USE_REG s5

.macro  MACRO_NONE
.endm

.macro  B1B 
    78:
        b       78b
        nop
.endm


.macro  LOOP_DELAY, DELAY
        li      v0, \DELAY
    79:
        bnez        v0, 79b
        addiu   v0, -1
.endm
.macro  WD_DIS_WATCHDOG0
        /* Disable Watch dog 0, which is default enabled */
        li      t0, WDT_MMIO
        lw      t1, WDT0_Control_Offset(t0)
        or      t1, WDT0_DisableBit
        sw      t1, WDT0_Control_Offset(t0)
.endm

.macro  WD_EN_WATCHDOG3, WDT3_ResetType
        /* sis326 Enable Dog 3 to Warm/Cold/RTC reset */
        li      t0, WDT_MMIO
        li      t1, \WDT3_ResetType // it could be set to WDT3_WarmReset, WDT3_ColdReset, or WDT3_RTCReset
        sw      t1, WDT3_Control_Offset(t0)
.endm

.macro  WD_EN_WATCHDOG1, WDT1_ResetType, WDT1_TimeTicks
        /* sis326 Enable Dog 1 to Warm/Cold/RTC reset and set TimeTickets*/
        //li        v0, WDT_MMIO
        //li        v1, (\WDT1_ResetType | \WDT1_TimeTicks | WDT1_EnableBit)
        //sw        v1, WDT1_Control_Offset(v0)

        li      v0, WDT_MMIO
        lw      v1, WDT1_Control_Offset(v0)
        and     v1, ~(0x80000000)
        sw      v1, WDT1_Control_Offset(v0) //disable WDT1 first

        li      v1, (\WDT1_ResetType | \WDT1_TimeTicks)
        sw      v1, WDT1_Control_Offset(v0)

        or      v1, WDT1_EnableBit
        sw      v1, WDT1_Control_Offset(v0)
.endm

.macro  WD_EN_WATCHDOG2, WDT2_ResetType, WDT2_TimeTicks
        /* sis326 Enable Dog 2 to Warm/Cold/RTC reset and set TimeTickets*/
        //li        v0, WDT_MMIO
        //li        v1, (\WDT2_ResetType | \WDT2_TimeTicks | WDT2_EnableBit)
        //sw        v1, WDT2_Control_Offset(v0)

        li      v0, WDT_MMIO
        lw      v1, WDT2_Control_Offset(v0)
        and     v1, ~(0x80000000)
        sw      v1, WDT2_Control_Offset(v0) //disable WDT2 first
        
        li      v1, (\WDT2_ResetType | \WDT2_TimeTicks) 
        sw      v1, WDT2_Control_Offset(v0)

        or      v1, WDT2_EnableBit
        sw      v1, WDT2_Control_Offset(v0)
.endm

.macro  WD_RE_WATCHDOG1
        /* Refresh Watch dog 1 */
        li      v0, WDT_MMIO
        lw      v1, WDT0_Control_Offset(v0)
        or      v1, WDT1_RefreshBit
        sw      v1, WDT0_Control_Offset(v0)
.endm

.macro  WD_RE_WATCHDOG2
        /* Refresh Watch dog 2 */
        li      v0, WDT_MMIO
        lw      v1, WDT0_Control_Offset(v0)
        or      v1, WDT2_RefreshBit
        sw      v1, WDT0_Control_Offset(v0)
.endm
.macro  WD_DIS_WATCHDOG1
        /* Disable Watch dog 1 */
        li      v0, WDT_MMIO
        lw      v1, WDT1_Control_Offset(v0)
        and     v1, ~(WDT1_EnableBit)
        sw      v1, WDT1_Control_Offset(v0)
.endm

.macro  WD_DIS_WATCHDOG2
        /* Disable Watch dog 2 */
        li      v0, WDT_MMIO
        lw      v1, WDT2_Control_Offset(v0)
        and     v1, ~(WDT2_EnableBit)
        sw      v1,  WDT2_Control_Offset(v0)
.endm

.macro  CPU_DIS_CPU1
        li      t0, HWDevResetMMIO
        lw      t1, 0(t0)
        or      t1, CPU1_RSTN_Bit
        xor     t1, CPU1_RSTN_Bit
        sw      t1, 0x0(t0)
.endm

.macro  CPU_EN_CPU1
        li      t0, HWDevResetMMIO
        lw      t1, 0(t0)
        or      t1, CPU1_RSTN_Bit
        sw      t1, 0x0(t0)
.endm

.macro  rom_setting_read8, data_offset, data_in
        lbu      \data_in, \data_offset(ROM_DATA_BASE_USE_REG)
.endm

.macro  rom_setting_read16, data_offset, data_in
        lh      \data_in, \data_offset(ROM_DATA_BASE_USE_REG)
.endm

.macro  rom_setting_read32, data_offset, data_in
        lw      \data_in, \data_offset(ROM_DATA_BASE_USE_REG)
.endm

.macro  aux_write8, aux_offset, value
        li      t0, \value
        sb      t0, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_write16, aux_offset, value
        li      t0, \value
        sh      t0, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_write32, aux_offset, value
        li      t0, \value
        sw      t0, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_read8, aux_offset, ret_value_reg
        lbu      \ret_value_reg, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_read16, aux_offset, ret_value_reg
        lh      \ret_value_reg, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_read32, aux_offset, ret_value_reg
        lw      \ret_value_reg, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_mask8, aux_offset, mask
        li      t0, \mask
        lbu      t1, \aux_offset(AUX_BASE_USE_REG)
        or      t1, t1, t0
        sb      t1, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_mask32, aux_offset, mask
        li      t0, \mask
        lw      t1, \aux_offset(AUX_BASE_USE_REG)
        or      t1, t1, t0
        sw      t1, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_unmask8, aux_offset, unmask
        li      t0, ~\unmask
        lbu      t1, \aux_offset(AUX_BASE_USE_REG)
        and     t1, t1, t0
        sb      t1, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_unmask32, aux_offset, unmask
        li      t0, ~\unmask
        lw      t1, \aux_offset(AUX_BASE_USE_REG)
        and     t1, t1, t0
        sw      t1, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_clear_and_set8, aux_offset, unmask, mask
        lbu     t1, \aux_offset(AUX_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sb		t1, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_clear_and_set16, aux_offset, unmask, mask
        lh      t1, \aux_offset(AUX_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sh		t1, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  aux_clear_and_set32, aux_offset, unmask, mask
        lw      t1, \aux_offset(AUX_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sw		t1, \aux_offset(AUX_BASE_USE_REG)
.endm

.macro  main1_write8, main_offset, value
        li      t0, \value
        sb      t0, \main_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_write16, main_offset, value
        li      t0, \value
        sh      t0, \main_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_write32, main_offset, value
        li      t0, \value
        sw      t0, \main_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_read8, main1_offset, ret_value_reg
        lbu      \ret_value_reg, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_read16, main1_offset, ret_value_reg
        lh      \ret_value_reg, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_read32, main1_offset, ret_value_reg
        lw      \ret_value_reg, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_mask8, main_offset, mask
        li      t0, \mask
        lbu      t1, \main_offset(MAIN1_BASE_USE_REG)
        or      t1, t1, t0
        sb      t1, \main_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_mask32, main_offset, mask
        li      t0, \mask
        lw      t1, \main_offset(MAIN1_BASE_USE_REG)
        or      t1, t1, t0
        sw      t1, \main_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_unmask8, main_offset, unmask
        li      t0, ~\unmask
        lbu      t1, \main_offset(MAIN1_BASE_USE_REG)
        and     t1, t1, t0
        sb      t1, \main_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_unmask32, main_offset, unmask
        li      t0, ~\unmask
        lw      t1, \main_offset(MAIN1_BASE_USE_REG)
        and     t1, t1, t0
        sw      t1, \main_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_clear_and_set8, main1_offset, unmask, mask
        lbu     t1, \main1_offset(MAIN1_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sb		t1, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_clear_and_set16, main1_offset, unmask, mask
        lh      t1, \main1_offset(MAIN1_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sh		t1, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_clear_and_set32, main1_offset, unmask, mask
        lw      t1, \main1_offset(MAIN1_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sw		t1, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_rom_value_set8, main1_offset, rom_offset
        lbu     t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sb      t1, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_rom_value_set16, main1_offset, rom_offset
        lh      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sh      t1, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main1_rom_value_set32, main1_offset, rom_offset
        lw      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sw      t1, \main1_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main2_write8, main2_offset, value
        li      t0, \value
        sb      t0, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_write16, main2_offset, value
        li      t0, \value
        sh      t0, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_write32, main2_offset, value
        li      t0, \value
        sw      t0, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_read8, main2_offset, ret_value_reg
        lbu      \ret_value_reg, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_read16, main2_offset, ret_value_reg
        lh      \ret_value_reg, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_read32, main2_offset, ret_value_reg
        lw      \ret_value_reg, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_mask8, main2_offset, mask
        li      t0, \mask
        lbu      t1, \main2_offset(MAIN2_BASE_USE_REG)
        or      t1, t1, t0
        sb      t1, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_mask32, main2_offset, mask
        li      t0, \mask
        lw      t1, \main2_offset(MAIN2_BASE_USE_REG)
        or      t1, t1, t0
        sw      t1, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_unmask8, main2_offset, unmask
        li      t0, ~\unmask
        lbu      t1, \main2_offset(MAIN2_BASE_USE_REG)
        and     t1, t1, t0
        sb      t1, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_unmask32, main2_offset, unmask
        li      t0, ~\unmask
        lw      t1, \main2_offset(MAIN2_BASE_USE_REG)
        and     t1, t1, t0
        sw      t1, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_clear_and_set8, main2_offset, unmask, mask
        lbu     t1, \main2_offset(MAIN2_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sb		t1, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_clear_and_set16, main2_offset, unmask, mask
        lh      t1, \main2_offset(MAIN2_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sh		t1, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_clear_and_set32, main2_offset, unmask, mask
        lw      t1, \main2_offset(MAIN2_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sw		t1, \main2_offset(MAIN2_BASE_USE_REG)
.endm

.macro  main2_rom_value_set8, main2_offset, rom_offset
        lbu     t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sb      t1, \main2_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main2_rom_value_set16, main2_offset, rom_offset
        lh      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sh      t1, \main2_offset(MAIN1_BASE_USE_REG)
.endm

.macro  main2_rom_value_set32, main2_offset, rom_offset
        lw      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sw      t1, \main2_offset(MAIN1_BASE_USE_REG)
.endm

.macro  phy_write8, phy_offset, value
        li      t0, \value
        sb      t0, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_write16, phy_offset, value
        li      t0, \value
        sh      t0, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_write32, phy_offset, value
        li      t0, \value
        sw      t0, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_read8, phy_offset, ret_value_reg
        lbu      \ret_value_reg, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_read16, phy_offset, ret_value_reg
        lh      \ret_value_reg, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_read32, phy_offset, ret_value_reg
        lw      \ret_value_reg, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_mask8, phy_offset, mask
        li      t0, \mask
        lbu      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
        or      t1, t1, t0
        sb      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_mask32, phy_offset, mask
        li      t0, \mask
        lw      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
        or      t1, t1, t0
        sw      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_unmask8, phy_offset, unmask
        li      t0, ~\unmask
        lbu      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
        and     t1, t1, t0
        sb      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_unmask32, phy_offset, unmask
        li      t0, ~\unmask
        lw      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
        and     t1, t1, t0
        sw      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_clear_and_set8, phy_offset, unmask, mask
        lbu     t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sb		t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_clear_and_set16, phy_offset, unmask, mask
        lh      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sh		t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_clear_and_set32, phy_offset, unmask, mask
        lw      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sw		t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_rom_value_set8, phy_offset, rom_offset
        lbu     t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sb      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_rom_value_set16, phy_offset, rom_offset
        lh      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sh      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  phy_rom_value_set32, phy_offset, rom_offset
        lw      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sw      t1, \phy_offset(DRAM_PHY_BASE_USE_REG)
.endm

.macro  ctrl_write8, ctrl_offset, value
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        li      t0, \value
        sb      t0, 0(t1)
.endm

.macro  ctrl_write16, ctrl_offset, value
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        li      t0, \value
        sh      t0, 0(t1)
.endm

.macro  ctrl_write32, ctrl_offset, value
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        li      t0, \value
        sw      t0, 0(t1)
.endm

.macro  ctrl_read8, ctrl_offset, ret_value_reg
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lbu      \ret_value_reg, 0(t1)
.endm

.macro  ctrl_read16, ctrl_offset, ret_value_reg
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lh      \ret_value_reg, 0(t1)
.endm

.macro  ctrl_read32, ctrl_offset, ret_value_reg
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lw      \ret_value_reg, 0(t1)
.endm

.macro  ctrl_mask8, ctrl_offset, mask
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        li      t0, \mask
        lbu     t2, 0(t1)
        or      t2, t2, t0
        sb      t2, 0(t1)
.endm

.macro  ctrl_mask32, ctrl_offset, mask
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        li      t0, \mask
        lw      t2, 0(t1)
        or      t2, t2, t0
        sw      t2, 0(t1)
.endm

.macro  ctrl_unmask8, ctrl_offset, unmask
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        li      t0, ~\unmask
        lbu     t2,  0(t1)
        and     t2,t2, t0
        sb      t2,  0(t1)
.endm

.macro  ctrl_unmask32, ctrl_offset, unmask
        addiu   t1, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        li      t0, ~\unmask
        lw      t2, 0(t1)
        and     t2, t2, t0
        sw      t2, 0(t1)
.endm

.macro  ctrl_clear_and_set8, ctrl_offset, unmask, mask
        addiu   t2, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lbu     t1, 0(t2)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sb		t1, 0(t2)
.endm

.macro  ctrl_clear_and_set16, ctrl_offset, unmask, mask
        addiu   t2, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lh      t1, 0(t2)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sh		t1, 0(t2)
.endm

.macro  ctrl_clear_and_set32, ctrl_offset, unmask, mask
        addiu   t2, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lw      t1, 0(t2)
        li      t0, ~\unmask
        and     t1, t1, t0
		li      t0, \mask
        or      t1, t1, t0
		sw		t1, 0(t2)
.endm

.macro  ctrl_rom_value_set8, ctrl_offset, rom_offset
        addiu   t0, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lbu     t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sb      t1, 0(t0)
.endm

.macro  ctrl_rom_value_set16, ctrl_offset, rom_offset
        addiu   t0, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lh      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sh      t1, 0(t0)
.endm

.macro  ctrl_rom_value_set32, ctrl_offset, rom_offset
        addiu   t0, DRAM_CTRL_BASE_USE_REG, \ctrl_offset
        lw      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sw      t1, 0(t0)
.endm

.macro  write8_i, reg, value
        li      t0, \value
        li      t1, \reg
        sb      t0, 0(t1)
.endm

.macro  write16_i, reg, value
        li      t0, \value
        li      t1, \reg
        sh      t0, 0(t1)
.endm

.macro  write32_i, reg, value
        li      t0, \value
        li      t1, \reg
        sw      t0, 0(t1)
.endm

.macro  write8_r, reg, value_reg
        li      t1, \reg
        sb      \value_reg, 0(t1)
.endm

.macro  write16_r, reg, value_reg
        li      t1, \reg
        sh      \value_reg, 0(t1)
.endm

.macro  write32_r, reg, value_reg
        li      t1, \reg
        sw      \value_reg, 0(t1)
.endm

.macro  read8, reg, ret_vaule_reg
        li      t0, \reg
        lbu      \ret_vaule_reg, 0(t0)
.endm

.macro  read16, reg, ret_vaule_reg
        li      t0, \reg
        lhu     \ret_vaule_reg, 0(t0)
.endm

.macro  read32, reg, ret_vaule_reg
        li      t0, \reg
        lw      \ret_vaule_reg, 0(t0)
.endm

.macro  mask8, reg, mask
        li      t0, \mask
        li      t1, \reg
        lbu      t2, 0(t1)
        or      t2, t2, t0
        sb      t2, 0(t1)
.endm

.macro  mask32, reg, mask
        li      t0, \mask
        li      t1, \reg
        lw      t2, 0(t1)
        or      t2, t2, t0
        sw      t2, 0(t1)
.endm

.macro  unmask8, reg, unmask
        li      t0, ~\unmask
        li      t1, \reg
        lbu      t2, 0(t1)
        and     t2, t2, t0
        sb      t2, 0(t1)
.endm

.macro  unmask32, reg, unmask
        li      t0, ~\unmask
        li      t1, \reg
        lw      t2, 0(t1)
        and     t2, t2, t0
        sw      t2, 0(t1)
.endm

.macro  clear_and_set_bit, ret_value_reg, unmask, mask
        li      t0, ~\unmask
        and     \ret_value_reg, \ret_value_reg, t0
		li      t0, \mask
        or      \ret_value_reg, \ret_value_reg, t0
.endm

.macro  rom_value_set8, reg, rom_offset
        li      t0, \reg
        lbu     t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sb      t1, 0(t0)
.endm

.macro  rom_value_set16, reg, rom_offset
        li      t0, \reg
        lh      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sh      t1, 0(t0)
.endm

.macro  rom_value_set32, reg, rom_offset
        li      t0, \reg
        lw      t1, \rom_offset(ROM_DATA_BASE_USE_REG)
		sw      t1, 0(t0)
.endm


#endif /* __ASSEMBLY__ */

#endif /* _ROM_MACRO */