UTS6710/drivers/IR/ir9561.h

#ifndef _IR_H
#define _IR_H

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/nmi.h>
#include <linux/mutex.h>
#include <asm/io.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/input.h>
#include <linux/workqueue.h>
#include <linux/version.h>
#include <drv_devices.h>
#ifndef INIT_BY_KMF
#define DBG_MSG1(id, fmt,args...)  do{ printk(KERN_DEBUG " " fmt, ## args); }while(0)
  #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
    #include <drv_dev.h>
  #else
    #include <asm-mips/mips-boards/sisdev.h> //Change the location of sisdev.h to sis516
  #endif
  #define AndroidtoTV(void)
 // #define kmf_register_platformfunc(MODULEID_IR, SiS_IR_Suspend, SiS_IR_Resume) 
#else
#include <drv_debug.h>
#include <drv_platform.h>
#endif
#include <drv_ir_def.h>
#include "irexport.h"

#define MMIOBASE_IR		0xBE080000
#define MMIOBASE_IR2		0xBE080500
#define IRQ_IR			59
#define SIS326_IR_REG_NUM	(0x5c/4)	// = 0x4C / 4

/*******************************************************************************
*******************************************************************************/
#define STATUS_SUCCESS					0
#define STATUS_DEVICE_ID_ERROR			1
#define STATUS_DATA_ERROR				2
#define STATUS_SYSTEM_ERROR				3

#define DebugPrint(fmt,args...)		printk(KERN_NOTICE fmt "\n",## args)


typedef struct _IRDEV {
	UINT8*				mmio_vbase;
	UINT8*				mmio_vbase2;
	int					irq;
	ULONG				flagINT0;
	struct cdev			cdev;
	IR_IOC_IOData		dataBuf;	
#if IR_Auto_Test
	Message				userMessage;
#endif
}IRDEV, *IRDEVPTR;

typedef struct _IR_Hardware_Parameter{
	union{
		ULONG dwValue[SIS326_IR_REG_NUM];	// 0x00 ~ 0x4b
		struct{
			union{	// 0x00 ~ 0x03 IR ID Registers
				ULONG Value00;
				struct{
					// 0x00 ~ 0x01
					ULONG DeviceID:16;
					// 0x02
					ULONG VersionID:8;
					// 0x03
					ULONG Reserved03:8;
				} Reg00;
			};
			union{	// 0x04 ~ 0x07
				ULONG Value04;
				struct{
					// 0x04 IR Protocol Registers
					ULONG reg_rc5_en:1;	// Enable Philips RC-5 decoding
					ULONG reg_sirc_en:1;	// Enable Sony SIRC decoding
					ULONG reg_nec_en:1;	// Enable NEC decoding
					ULONG reg_jvc_en:1;	// Enable JVC decoding
					ULONG reg_rc6_en:1;	// Enable Philips RC-6 decoding
					ULONG Reserved04:3;
					// 0x05 ~ 0x06 IR Global Option Registers
					ULONG reg_reorder_en:1;
					ULONG reg_key_prs_cnt_en:1;
					ULONG reg_intr_every_pkt_en:1;	// Enable interrupts for all packets (old path)
					ULONG Reserved05:5;
					ULONG reg_filt_lnth:6;
					ULONG Reserved06:1;
					ULONG reg_polarity:1;	// Inverse input polarity of IR decoder
					// 0x07 IR Address / Command Length Registers
					ULONG reg_cmd_lnth:4;	// Custom code, command length
					ULONG reg_adr_lnth:4;	// Data code, address length
				} Reg04;
			};
			union{	// 0x08 ~ 0x0b
				ULONG Value08;
				struct{
					ULONG Reserved:32;
				} Reg08;
			};
			union{	// 0x0c ~ 0x0f
				ULONG Value0C;
				struct{
					// 0x0c ~ 0x0d IR Decoder Received Data Registers
					ULONG reg_cmd:8;	// Command code (Raw bit-stream if reg_reorder_en = 0) ; Valid if reg_single_sts = 1
					ULONG reg_adr:8;	// Address code (Raw bit-stream if reg_reorder_en = 0) ; Valid if reg_single_sts = 1
					// 0x0e IR Interrupt Status Registers
					ULONG reg_intr_sts:1;	// IR global interrupt status; Write 1 Clear
					ULONG reg_single_sts:1;	// Single key interrupt status
					ULONG reg_rpt_start_sts:1;	// Repeating key start interrupt status
					ULONG reg_rpt_end_sts:1;	// Repeating key end interrupt status
					ULONG reg_rpt_sts:1;	// Repeating key interrupt status (Keep sending interrupts)
					ULONG Reserved0E:3;
					// 0x0f Number of Interrupts in Queue
					ULONG reg_cmdq_cnt:5;	// Number of remaining interrupts in queue
					ULONG Reserved0F:3;
				} Reg0C;
			};
			union{	// 0x10 ~ 0x13
				ULONG Value10;
				struct{
					ULONG Reserved:32;
				} Reg10;
			};
			union{	// 0x14 ~ 0x17
				ULONG Value14;
				struct{
					ULONG Reserved:32;
				} Reg14;
			};
			union{	// 0x18 ~ 0x1b
				ULONG Value18;
				struct{
					ULONG Reserved:32;
				} Reg18;
			};
			union{	// 0x1c ~ 0x1f
				ULONG Value1C;
				struct{
					ULONG Reserved:32;
				} Reg1C;
			};
			union{	// 0x20 ~ 0x23
				ULONG Value20;
				struct{
					ULONG Reserved:32;
				} Reg20;
			};
			union{	// 0x24 ~ 0x27
				ULONG Value24;
				struct{
					ULONG Reserved:32;
				} Reg24;
			};
			union{	// 0x28 ~ 0x2b
				ULONG Value28;
				struct{
					ULONG Reserved:32;
				} Reg28;
			};
			union{	// 0x2c ~ 0x2f
				ULONG Value2C;
				struct{
					ULONG Reserved:32;
				} Reg2C;
			};
			union{	// 0x30 ~ 0x33
				ULONG Value30;
				struct{
					ULONG Reserved:32;
				} Reg30;
			};
			union{	// 0x34 ~ 0x37
				ULONG Value34;
				struct{
					ULONG Reserved:32;
				} Reg34;
			};
			union{	// 0x38 ~ 0x3b
				ULONG Value38;
				struct{
					ULONG Reserved:32;
				} Reg38;
			};
			union{	// 0x3c ~ 0x3f
				ULONG Value3C;
				struct{
					ULONG Reserved:32;
				} Reg3C;
			};
			union{	// 0x40 ~ 0x43
				ULONG Value40;
				struct{
					ULONG Reserved:32;
				} Reg40;
			};
			union{	// 0x44 ~ 0x47
				ULONG Value44;
				struct{
					ULONG Reserved:32;
				} Reg44;
			};
			union{	// 0x48 ~ 0x4b
				ULONG Value48;
				struct{
					ULONG Reserved:32;
				} Reg48;
			};
			union{	// 0x4c ~ 0x4f
				ULONG Value4C;
				struct{
					ULONG Reserved:32;
				} Reg4C;
			};
			union{	// 0x50 ~ 0x53
				ULONG Value50;
				struct{
					ULONG Reserved:32;
				} Reg50;
			};
			union{	// 0x54 ~ 0x57
				ULONG Value54;
				struct{
					ULONG Reserved:32;
				} Reg54;
			};	
			union{	// 0x58 ~ 0x5B
				ULONG Value58;
				struct{
					ULONG Reserved:32;
				} Reg58;
			};
		} Registers;
	};
}IR_Hardware_Parameter;

typedef struct _IRdatas{
	union{	
		ULONG Value;
		struct{
			ULONG reg_cmd:8;	// Command code (Raw bit-stream if reg_reorder_en = 0) ; Valid if reg_single_sts = 1
			ULONG reg_adr:8;	// Address code (Raw bit-stream if reg_reorder_en = 0) ; Valid if reg_single_sts = 1
			// 0x0e IR Interrupt Status Registers
			ULONG reg_intr_sts:1;	// IR global interrupt status; Write 1 Clear
			ULONG reg_single_sts:1;	// Single key interrupt status
			ULONG reg_rpt_start_sts:1;	// Repeating key start interrupt status
			ULONG reg_rpt_end_sts:1;	// Repeating key end interrupt status
			ULONG reg_rpt_sts:1;	// Repeating key interrupt status (Keep sending interrupts)
			ULONG Reserved0E:3;
			// 0x0f Number of Interrupts in Queue
			ULONG reg_cmdq_cnt:5;	// Number of remaining interrupts in queue
			ULONG Reserved0F:3;
		} Reg;
	};
	} IRdatas;
//function
void sisir_initfun(void);
void sisir_exitfun(IRDEVPTR pir);
void sisir_isrfun(UINT8* mmiobase, UINT8* mmiobase2, IR_IOC_IOData* dataBuf);


int IRHandlerInit(void);

#endif // end of #ifndef _IR_H