UTS6710/drivers/adc/6710/adc_hw.c

#include "adc_global.h"
#include "adc_hw.h"

void ADC_Clear_Interrupt(UINT16 usValue)
{
    //printk(KERN_EMERG" ## Clear Interrupt 0x%x ##\n", usValue);
	ADC_Write(ADC_REG_int_clear_byte, usValue);
}

void ADC_Interrupt(BOOL bStatus, UINT16 usValue)
{
    //printk(KERN_EMERG" ## Set Interrupt [%s] = 0x%x ##\n", bStatus?"TRUE":"FALSE", usValue);
	if(gAdcAp.bDisableInterrupt)
		bStatus = DISABLE;

	if(bStatus == ENABLE)
		ADC_Write(ADC_REG_int_mask_byte, ~usValue);
	else
		ADC_Write(ADC_REG_int_mask_byte, 0xffff);
}

#ifdef CONFIG_DDC_CI_SUPPORT
void DRV_ADC_Get_DDCCI_OSDPhase(UINT8 *Phase)
{
    *Phase = sAdcInfo.DDCCI_OSDPhase;
}
EXPORT_SYMBOL(DRV_ADC_GetPhase);

void DRV_ADC_Get_DDCCI_OSDClock(UINT8 *Clock)
{
    *Clock = sAdcInfo.DDCCI_OSDClock;
}
EXPORT_SYMBOL(DRV_ADC_GetPhase);
#endif

void ADC_SetPhaseDirdect (UINT8 ucPhaseValue)
{
	ADC_Write(ADC_REG_pll_phase_r_sel, ucPhaseValue);
	ADC_Write(ADC_REG_pll_phase_g_sel, ucPhaseValue);
	ADC_Write(ADC_REG_pll_phase_b_sel, ucPhaseValue);
}

void DRV_ADC_GetPhase(UINT8 *bPhase)
{
    *bPhase=ADC_Read(ADC_REG_pll_phase_r_sel);
}
EXPORT_SYMBOL(DRV_ADC_GetPhase);

void DRV_ADC_SetPhase(INT8 scPhaseValue)
{
	UINT8	ucDelay;
	UINT16	usInterruptStatus;

	//when inputmode is nosignal, ADC_DetectTiming.ucVFrequency=0 will get the Kernel Panic
	if((sAdcInfo.ucInputMode == UNSUPPORT_MODE) || (sAdcInfo.ucInputMode == NOSIGNAL_MODE))
		return;

	ucDelay = 500*3/(ADC_DetectTiming.ucVFrequency+1);
	sAdcInfo.ucUserPhase = scPhaseValue;//(((scPhaseValue - scOsdMin)* 100000) /((( scOsdMax - scOsdMin)+1) * 100000 /32 ));

	usInterruptStatus = ADC_Read(ADC_REG_int_mask_byte);
    if( (sAdcInfo.ucSource != Adc_kSourceVGA) && ((usInterruptStatus & 0x80) == 0x80) )
    {
        printk(KERN_EMERG"#### Interrupt Disabled!! Skip @ [%s] ####\n", __FUNCTION__);
        return;
    }
	ADC_Write(ADC_REG_int_mask_byte, usInterruptStatus|0x80);
	ADC_Interrupt(DISABLE, 0);

	ADC_SetPhaseDirdect(sAdcInfo.ucUserPhase);

	ADC_DelayMS(ucDelay);

	ADC_Clear_Interrupt(0x80);
	ADC_Write(ADC_REG_int_mask_byte, usInterruptStatus);

}
EXPORT_SYMBOL(DRV_ADC_SetPhase);

void ADC_SetGainDirdect(UINT8 ucColor, UINT32 uwValue) //0~511
{
	if(uwValue > 511)
		uwValue = 511;

	switch(ucColor)
	{
		case RED:
			ADC_Write(ADC_REG_lcg_rmp1, (uwValue>>6)&0x7);
			ADC_Write(ADC_REG_lcg_rmp2, uwValue&0x3f);
			break;
		case GREEN:
			ADC_Write(ADC_REG_lcg_gmp1, (uwValue>>6)&0x7);
			ADC_Write(ADC_REG_lcg_gmp2, uwValue&0x3f);
			break;
		case BLUE:
			ADC_Write(ADC_REG_lcg_bmp1, (uwValue>>6)&0x7);
			ADC_Write(ADC_REG_lcg_bmp2, uwValue&0x3f);
			break;
	}
}

void DRV_ADC_SetGain(UINT8 ucColor, UINT32 scColorGain) //0~511
{
	switch(ucColor)
	{
		case RED:
			ADC_SetGainDirdect(RED, scColorGain);
			break;
		case GREEN:
			ADC_SetGainDirdect(GREEN, scColorGain);
			break;
		case BLUE:
			ADC_SetGainDirdect(BLUE, scColorGain);
			break;
	}
}
EXPORT_SYMBOL(DRV_ADC_SetGain);

UINT16 ADC_GetGain(UINT8 ucColor)
{
	UINT16 ulColorGain=0;

	switch(ucColor)
	{
		case RED:
			ulColorGain |= (ADC_Read(ADC_REG_lcg_rmp1)&0x7)<<6;
			ulColorGain |= ADC_Read(ADC_REG_lcg_rmp2)&0x3f;
			break;
		case GREEN:
			ulColorGain |= (ADC_Read(ADC_REG_lcg_gmp1)&0x7)<<6;
			ulColorGain |= ADC_Read(ADC_REG_lcg_gmp2)&0x3f;
			break;
		case BLUE:
			ulColorGain |= (ADC_Read(ADC_REG_lcg_bmp1)&0x7)<<6;
			ulColorGain |= ADC_Read(ADC_REG_lcg_bmp2)&0x3f;
			break;
		default:
			ulColorGain = 256;
	}

	return ulColorGain;
}

void ADC_SetOffsetDirdect(UINT8 ucColor, UINT32 uwValue)// -255 ~ 255
{
	if(uwValue > 255)
		uwValue = 255;

	switch(ucColor)
	{
		case RED:
			ADC_Write(ADC_REG_dofst_r_7to0, uwValue&0xff);
			break;
		case GREEN:
			ADC_Write(ADC_REG_dofst_g_7to6, ((uwValue>>6)&0x3));
			ADC_Write(ADC_REG_dofst_g_5to0, uwValue&0x3f);
			break;
		case BLUE:
			ADC_Write(ADC_REG_dofst_b_7to4, ((uwValue>>4)&0xf));
			ADC_Write(ADC_REG_dofst_b_3to0, uwValue&0xf);
			break;
	}
}

void DRV_ADC_SetOffset(UINT8 ucColor, INT16 scColorOffset)   // 0 ~ 511
{
	UINT32 ulOffsetValue = 0;

	switch(ucColor)
	{
		case RED:
			if(scColorOffset > 255)
			{
				ADC_Write(ADC_REG_dofst_r, 1);
				ulOffsetValue = scColorOffset - 255;
			}
			else
			{
				ADC_Write(ADC_REG_dofst_r, 0);
				ulOffsetValue = abs(scColorOffset- 255);
			}
			break;
		case GREEN:
			if(scColorOffset > 255)
			{
				ADC_Write(ADC_REG_dofst_g, 1);
				ulOffsetValue = scColorOffset - 255;
			}
			else
			{
				ADC_Write(ADC_REG_dofst_g, 0);
				ulOffsetValue = abs(scColorOffset- 255);
			}
			break;
		case BLUE:
			if(scColorOffset > 255)
			{
				ADC_Write(ADC_REG_dofst_b, 1);
				ulOffsetValue = scColorOffset - 255;
			}
			else
			{
				ADC_Write(ADC_REG_dofst_b, 0);
				ulOffsetValue = abs(scColorOffset- 255);
			}
			break;
	}

	switch(ucColor)
	{
		case RED:
			ADC_SetOffsetDirdect(RED, ulOffsetValue);
			break;
		case GREEN:
			ADC_SetOffsetDirdect(GREEN, ulOffsetValue);
			break;
		case BLUE:
			ADC_SetOffsetDirdect(BLUE, ulOffsetValue);
			break;
	}
}
EXPORT_SYMBOL(DRV_ADC_SetOffset);

UINT16 ADC_GetOffset(UINT8 ucColor)
{
	UINT32 ulColorOffset=0;

	switch(ucColor)
	{
		case RED:
			ulColorOffset |= ADC_Read(ADC_REG_dofst_r_7to0)&0xff;
			break;
		case GREEN:
			ulColorOffset |= (ADC_Read(ADC_REG_dofst_g_7to6)&0x3)<<6;
			ulColorOffset |= ADC_Read(ADC_REG_dofst_g_5to0)&0x3f;
			break;
		case BLUE:
			ulColorOffset |= (ADC_Read(ADC_REG_dofst_b_7to4)&0xf) <<4;
			ulColorOffset |= ADC_Read(ADC_REG_dofst_b_3to0)&0xf;
			break;
		default:
			ulColorOffset = 256;
	}

	return ulColorOffset;
}

void DRV_ADC_SetHTotal(UINT16 usHTotal)
{
	BOOL bHsOutEnable=FALSE;
	UINT16 usRegPllMul;

	ADC_DebugMsg("%s %d\n", __FUNCTION__,__LINE__);
	ADC_DebugMsg("HTotal = %d\n", usHTotal);

	if( sAdcInfo.ucSource!=Adc_kSourceVGA )
	{
		if( (ADC_Read(ADC_REG_int_mask_byte)&0x80)==0 )
		{
			bHsOutEnable = TRUE;
			ADC_Write(ADC_REG_int_mask_byte, ADC_Read(ADC_REG_int_mask_byte)|0x0080);
		}
	}

	usRegPllMul = usHTotal-1;

	ADC_Write(ADC_REG_pll_febdiv_7to0, (usRegPllMul&0xff));
	ADC_Write(ADC_REG_pll_febdiv_11to8, (usRegPllMul&0xf00)>>8);

	//ADC_DelayMS(24);

	if( bHsOutEnable )
	{
		ADC_Write(ADC_REG_int_mask_byte, ADC_Read(ADC_REG_int_mask_byte)&(~0x0080));
	}
}
EXPORT_SYMBOL(DRV_ADC_SetHTotal);

void ADC_PllSetting(UINT8 ucPixelClock, UINT16 usHTotal)
{
	UINT8 ucRegPllDiv, ucRegPllGb=0, ucRegPlli2ctrl, ucRegPllictrl, ucRegPllDivb=0, ucPllDiva[]={1, 2, 4,8}, ucPllDivb[]={2, 3, 4, 5};
	UINT16 usVCO, usFebDiv=0, usPxDiv=0;

//   pixel clock < 40MHz, the 0xbe150058 is setting to 0x22
//   pixel 40MHz <= clock < 80MHz, the 0xbe150058 is setting to 0x55
//   pixel clock >= 80MHz, the 0xbe150058 is setting to 0x99
	if( ucPixelClock < 40 )
	{
		ADC_Write(ADC_REG_sch_pbw_ctrl, 2);
		ADC_Write(ADC_REG_sch_ref_pbw_ctrl, 2);
	}
	else if( ucPixelClock >= 40 &&  ucPixelClock < 80 )
	{
		ADC_Write(ADC_REG_sch_pbw_ctrl, 5);
		ADC_Write(ADC_REG_sch_ref_pbw_ctrl, 5);
	}
	else if( ucPixelClock >= 80 )
	{
		ADC_Write(ADC_REG_sch_pbw_ctrl, 9);
		ADC_Write(ADC_REG_sch_ref_pbw_ctrl, 9);
	}

	//Keep VCO range 900~1330M Hz by 20120822
	if(ucPixelClock < 19)
		ucRegPllDiv = 3;
	else if(ucPixelClock < 38)
		ucRegPllDiv = 2;
	else if(ucPixelClock < 76)
		ucRegPllDiv = 1;
	else
		ucRegPllDiv = 0;

	if(ucPixelClock < 28)
		ucRegPllDivb = 1;
	else if(ucPixelClock < 38)
		ucRegPllDivb = 0;
	else if(ucPixelClock < 56)
		ucRegPllDivb = 1;
	else if(ucPixelClock < 76)
		ucRegPllDivb = 0;
	else if(ucPixelClock < 112)
		ucRegPllDivb = 1;
	else
		ucRegPllDivb = 0;

	usPxDiv = ucPllDiva[ucRegPllDiv]*ucPllDivb[ucRegPllDivb]*4 - 1;
	usVCO = ucPixelClock*(usPxDiv+1);
	if(ADC_Read(GLB_REG_VADC_REF_SEL_24M))
		usFebDiv = (usVCO*1000)/CRYSTAL_CLK -1;
	else
		usFebDiv = (usVCO*1000)/System_CLK -1;

	//PLL charge pump, set PLL band width
	if( ucPixelClock<60 )
	{
		ucRegPlli2ctrl=3;
		ucRegPllictrl=3;
	}
	else
	{
		ucRegPlli2ctrl=0xb;
		ucRegPllictrl=0xb;
	}

	if ( ( usVCO >= 900) && (usVCO < 1100) )
	{
		ADC_Write(ADC_REG_dco_gb, 0x4);
		ADC_Write(ADC_REG_dco_ictrl, 0x5);
	}
	else if ( ( usVCO >= 1100 ) && ( usVCO < 1400) )
	{
		ADC_Write(ADC_REG_dco_gb, 0x4);
		ADC_Write(ADC_REG_dco_ictrl, 0x5);
	}
	else
	{
		ADC_Write(ADC_REG_dco_gb, 0x4);
		ADC_Write(ADC_REG_dco_ictrl, 0x5);
	}

	//ADC_Write(ADC_REG_cs2_pll_sw_rst, 0x1);
	//ADC_Write(ADC_REG_pll_pwdn, 0);
	ADC_Write(ADC_REG_pdiv_rstn, 0);
	ADC_Write(ADC_REG_pll_gb_vb, (ucRegPllGb&0x7));
	ADC_Write(ADC_REG_pll_gb_MSBs, (ucRegPllGb&0x18)>>3);
	ADC_Write(ADC_REG_pll_i2ctrl, (ucRegPlli2ctrl&0x7));
	ADC_Write(ADC_REG_pll_i2ctrl_MSBs, (ucRegPlli2ctrl&0x018)>>3);
	ADC_Write(ADC_REG_pll_ictrl, (ucRegPllictrl&0x7));
	ADC_Write(ADC_REG_pll_ictrl_MSBs, (ucRegPllictrl&0x18)>>3);
	DRV_ADC_SetHTotal(usHTotal);
	ADC_Write(ADC_REG_pll_div_sel, ucRegPllDiv);
	ADC_Write(ADC_REG_pll_hsync_pw, 0xf);
	ADC_Write(ADC_REG_pll_12v, 2);
	ADC_Write(ADC_REG_PLL12V, 0xa);
	ADC_Write(ADC_REG_dco_refdiv, 0x08);	// 0x147[4:0]	
	//ADC_Write(ADC_REG_pll_pwdn, 1);
	//ADC_Write(ADC_REG_cs2_pll_sw_rst, 0x0);
	ADC_Write(ADC_REG_pdiv_rstn, 1);
	ADC_Write(ADC_REG_pll_pdiv_en, 0);
	ADC_Write(ADC_REG_pll_divb_sel, ucRegPllDivb);
	ADC_Write(ADC_REG_dco_febdiv, usFebDiv);
	ADC_Write(ADC_REG_dlpll_pxdiv, usPxDiv);
}

void ADC_CheckPllResetSequence(UINT8 ucPixelClock, UINT16 usHTotal)
{
	ADC_DebugMsg("%s %d\n", __FUNCTION__,__LINE__);

	/// Analog PLL
	// Reset all PLL functions
	ADC_Write(ADC_REG_ldo_pwde, 1);				// 0x14a[1]
	ADC_Write(ADC_REG_ldo_pwd, 1);				// 0x14a[0]
	ADC_Write(ADC_REG_cs2_pll_sw_rst, 0x1);		// 0x1a[0]
	ADC_Write(ADC_REG_pll_pwdn, 0);				// 0x32[1]
	ADC_Write(ADC_REG_dco_pdiv_rstj , 0x0);		// 0x144[6]

	ADC_PllSetting(ucPixelClock, usHTotal);
	
	// Enable all PLL functions
	ADC_Write(ADC_REG_ldo_pwde, 0);				// 0x14a[1]
	ADC_Write(ADC_REG_ldo_pwd, 0);				// 0x14a[0]
	udelay(10);
	ADC_Write(ADC_REG_cs2_pll_sw_rst, 0x0);		// 0x1a[0]
	ADC_Write(ADC_REG_pll_pwdn, 1);				// 0x32[1]
	udelay(20);
	ADC_Write(ADC_REG_dco_pdiv_rstj , 0x1);		// 0x144[6]
	
	/// Digital PLL
	//PLL SDM reset
	ADC_Write(ADC_REG_sdmresetj, 0);
	ADC_Write(ADC_REG_sdmresetj, 1);

	udelay(100);

	//PLL Line_div & Pixel_div reset
	ADC_Write(ADC_REG_dlpll_pdiv_rstj, 0);
	ADC_Write(ADC_REG_dlpll_pdiv_rstj, 1);

	// PLL 3-channel phase divider reset
	ADC_Write(ADC_REG_cs2_pdiv_sw_rst_ctrl, 0);
	ADC_Write(ADC_REG_pdiv_rstn, 0);
	ADC_Write(ADC_REG_pdiv_rstn, 1);

	ADC_DelayMS(1);
}

void ADC_SOG_Slicer_Backup(void)
{
	ADC_Write(ADC_REG_cs2_sog_sw_rst, 0x1);
	ADC_Write(ADC_REG_cs2_sog_sw_rst, 0x0);
}

void ADC_Coast_Gen_Backup(void)
{
	// 2010/12/30 modify by patrick
	ADC_Write(ADC_REG_adi_reset, 1);
	ADC_Write(ADC_REG_adi_reset, 0);
}

UINT32 ADC_InputSrcPinYvalue(UINT32 iPin)
{
	switch (iPin)
	{
		case INPUT_PIN_AV_Y1:
		case INPUT_PIN_AV_Y_ON_G1:
			return 0x1;
		case INPUT_PIN_AV_Y2:
		case INPUT_PIN_AV_Y_ON_G2:
			return 0x2;
		case INPUT_PIN_AV_Y3:
		case INPUT_PIN_AV_Y_ON_G3:
			return 0x3;
		default:
			return 0;
	}
}

void DRV_ADC_YCInitSetting(int iInputSource)
{
	ADC_DebugMsg("%s %d\n", __FUNCTION__,__LINE__);

    ADC_Write(GLB_REG_VCLK_DIV_RSTN, 1 );     // Set ADC_PLL reference divider reset as normal mode
    
	ADC_Write(GLB_REG_global_reset, 0);
	udelay(1000);
	ADC_Write(GLB_REG_global_reset, 1);

    DRV_ADC_YppShareBandGap_Power(TRUE);  // power on MVADC's BGP (default value is 0 after global reset)
    
	switch(iInputSource)
	{
		case ADC_SV_INPUT_CHANNEL:

			if (iInputSource == ADC_SV_INPUT_CHANNEL)
			{
				ADC_DebugMsg("Source SV: pin on Y%d_CHANNEL...\n", ADC_InputSrcPinYvalue(adc_InputSrcPin.svideo.y_pin));

				if (adc_InputSrcPin.svideo.c_pin == INPUT_PIN_AV_Y0_C0)
				{
					ADC_DebugMsg("Source SV: C on G3_CHANNEL...\n");

					//C on G chel
					ADC_Write(ADC_REG_lcg_gch_sel, 0x3);

					//off R B chel
					ADC_Write(ADC_REG_sch_pwdn_r, 0x1);
					ADC_Write(ADC_REG_sch_pwdn_b, 0x1);
				}
				else
				{
					ADC_DebugMsg("Source SV: C on R3_CHANNEL...\n");

					//C on R chel
					ADC_Write(ADC_REG_lcg_rch_sel, 0x3);

					//off G B chel
					ADC_Write(ADC_REG_sch_pwdn_g, 0x1);
					ADC_Write(ADC_REG_sch_pwdn_b, 0x1);
				}

				ADC_Write(ADC_REG_y_chsel, ADC_InputSrcPinYvalue(adc_InputSrcPin.svideo.y_pin));
			}

			ADC_Write(ADC_REG_g_sb2, 0x8);
			ADC_Write(ADC_REG_sch_pbw_ctrl, 0xf);
			ADC_Write(ADC_REG_sch_ref_pbw_ctrl, 0xf);
			ADC_Write(ADC_REG_R_SYPP120, 1);
			ADC_Write(ADC_REG_R_SYPP121, 0);
			ADC_Write(ADC_REG_R_SCVBS12, 0);
			ADC_Write(ADC_REG_G_SCVBS12, 0x1);
			ADC_Write(ADC_REG_av_r_pg12v1, 0);
			ADC_Write(ADC_REG_av_g_pg12v1, 0);

			ADC_Write(ADC_REG_av_g_pg12v2, 1);

			break;
        case ADC_AV1_INPUT_CHANNEL:
        case ADC_AV2_INPUT_CHANNEL:
    	case ADC_AV_ON_G_CHANNEL:

			if ( ( adc_InputSrcPin.cvbs.pin == INPUT_PIN_AV_Y1) || ( adc_InputSrcPin.cvbs.pin == INPUT_PIN_AV_Y2) || ( adc_InputSrcPin.cvbs.pin == INPUT_PIN_AV_Y3) || ( adc_InputSrcPin.cvbs.pin == INPUT_PIN_AV_Y4))
			{
				ADC_DebugMsg("Source AV: pin on Y%d_CHANNEL...\n", ADC_InputSrcPinYvalue(adc_InputSrcPin.cvbs.pin));

				if (iInputSource == ADC_AV1_INPUT_CHANNEL)
				{
					ADC_DebugMsg("Input AV1 Init Setting...\n");

					ADC_Write(ADC_REG_lcg_rch_sel, 1);
					ADC_Write(ADC_REG_lcg_gch_sel, 1);
					ADC_Write(ADC_REG_lcg_bch_sel, 1);
				}
				else if (iInputSource == ADC_AV2_INPUT_CHANNEL)
				{
					ADC_DebugMsg("Input AV2 Init Setting...\n");

					ADC_Write(ADC_REG_lcg_rch_sel, 2);
					ADC_Write(ADC_REG_lcg_gch_sel, 2);
					ADC_Write(ADC_REG_lcg_bch_sel, 2);
				}
				else
				{
					ADC_DebugMsg("Input AV3 Init Setting...\n");

					ADC_Write(ADC_REG_lcg_rch_sel, 3);
					ADC_Write(ADC_REG_lcg_gch_sel, 3);
					ADC_Write(ADC_REG_lcg_bch_sel, 3);
				}

				//Y chel select
				ADC_Write(ADC_REG_y_chsel, ADC_InputSrcPinYvalue(adc_InputSrcPin.cvbs.pin) );

				//off R G B chel
				ADC_Write(ADC_REG_sch_pwdn_r, 0x1);
				ADC_Write(ADC_REG_sch_pwdn_g, 0x1);
				ADC_Write(ADC_REG_sch_pwdn_b, 0x1);
				ADC_Write(ADC_REG_av_g_pg12v1, 0);	// ADC MDAC OP current (0: Large current / 1: Small current)
				ADC_Write(ADC_REG_av_g_pg12v2, 1);
			}
			else
			{
				ADC_DebugMsg("Source AV: pin on G%d_CHANNEL...\n", ADC_InputSrcPinYvalue(adc_InputSrcPin.cvbs.pin));

				ADC_Write(ADC_REG_lcg_rch_sel, 0);
				ADC_Write(ADC_REG_lcg_gch_sel, ADC_InputSrcPinYvalue(adc_InputSrcPin.cvbs.pin));
				ADC_Write(ADC_REG_lcg_bch_sel, 0);
				ADC_Write(ADC_REG_sch_pbw_ctrl, 0xf);
				ADC_Write(ADC_REG_sch_ref_pbw_ctrl, 0xf);
				
				// Power on RGB channel
				ADC_Write(ADC_REG_sch_pwdn_r, 0x1);
				ADC_Write(ADC_REG_sch_pwdn_g, 0x0);
				ADC_Write(ADC_REG_sch_pwdn_b, 0x1);
				
				ADC_Write(ADC_REG_pwdny, 1);
				
				// Setup RGN channel ADC common mode
				ADC_Write(ADC_REG_lcg_r33vcm_sel, 0x7);
				ADC_Write(ADC_REG_lcg_g33vcm_sel, 0x7);
				ADC_Write(ADC_REG_lcg_b33vcm_sel, 0x7);
				ADC_Write(ADC_REG_g_12vcm_sel, 0x4);
				
				ADC_Write(ADC_REG_R_SYPP120, 0);
				ADC_Write(ADC_REG_R_SYPP121, 0);
				ADC_Write(ADC_REG_R_SCVBS12, 0);
				ADC_Write(ADC_REG_G_SYPP120, 0);
				ADC_Write(ADC_REG_G_SYPP121, 0);
				ADC_Write(ADC_REG_G_SCVBS12, 1);
				ADC_Write(ADC_REG_B_SYPP120, 0);
				ADC_Write(ADC_REG_B_SYPP121, 0);
                ADC_Write(ADC_REG_b_scvbs12, 0);
                
				ADC_Write(ADC_REG_CHR_SIFCLK_SEL, 0);
				ADC_Write(ADC_REG_av_g_pg12v1, 0);	// ADC MDAC OP current (0: Large current / 1: Small current)
				ADC_Write(ADC_REG_av_g_pg12v2, 0);
				ADC_Write(ADC_REG_gcvbsen, 1);
				ADC_Write(ADC_REG_pll_div_sel, 0);
				ADC_Write(ADC_REG_pll_divb_sel, 0);//ADC_Write(ADC_REG_pll_divb_sel, 1);
				ADC_Write(ADC_REG_pll_ref_sel, 2);
			}

			break;
		default:
			ADC_DebugMsg("Do Not Need ADC Init Setting...\n");
			break;
	}

	ADC_Write(ADC_REG_ext_clk_muxsel, 0x1);// 0xa7[5:4] ADC_Write(ADC_REG_ext_clk_muxsel, 0x1);
	ADC_Write(ADC_REG_pll_extpclk_sel, 0); // 0x39[4]
	ADC_Write(GLB_REG_VADC_REF_SEL_24M, 0);	// 0xbe000149[6] 24 MHz reference selector. 0: CPLL,  1: Crystal 24M
	
	// Y chel setting
	ADC_Write(ADC_REG_y_ffadj12v, 0x1);
	ADC_Write(ADC_REG_clamp_mode_y, 0x1);
	ADC_Write(ADC_REG_y_mp10y, 0);
	ADC_Write(ADC_REG_y_pga12v1, 0);
	
	// Pull down unused RGB 
	ADC_Write(ADC_REG_r_pden12v, 1);
	ADC_Write(ADC_REG_g_pden12v, 1);
	ADC_Write(ADC_REG_b_pden12v, 1);
	ADC_Write(ADC_REG_r_tswmiden12v, 1);
	ADC_Write(ADC_REG_g_tswmiden12v, 1);
	ADC_Write(ADC_REG_b_tswmiden12v, 1);

	ADC_Write(ADC_REG_y_pga12v2_bit4, 0);
	ADC_Write(ADC_REG_y_pga12v3, 0);
	ADC_Write(ADC_REG_y_sb2, 0);
	ADC_Write(ADC_REG_y_sb1, 0xc);
	ADC_Write(ADC_REG_y_sypp12, 0);
	ADC_Write(ADC_REG_y_clamp_en, 0x1);
	ADC_Write(ADC_REG_y_scvbs12, 1);
	ADC_Write(ADC_REG_sog_ch1_sel, 1);
	ADC_Write(ADC_REG_rwclampeco, 1);

	//Differential mode setting
	ADC_Write(ADC_REG_y_pden12v, 0);
	ADC_Write(ADC_REG_y_refch12v, 3);
	ADC_Write(ADC_REG_y_tswmiden12v, 1);
	ADC_Write(ADC_REG_y_refclampsel12v, 0);
	ADC_Write(ADC_REG_y_intrefen12v, 1);
	ADC_Write(ADC_REG_av_r_pg12v2, 1);
	ADC_Write(ADC_REG_av_b_pg12v2, 1);
	ADC_Write(ADC_REG_r_refch12v, 2);
	ADC_Write(ADC_REG_g_refch12v, 2);
	ADC_Write(ADC_REG_b_refch12v, 2);
	ADC_Write(ADC_REG_r_lpfmod12v, 0);
	ADC_Write(ADC_REG_g_lpfmod12v, 0);
	ADC_Write(ADC_REG_b_lpfmod12v, 0);
	ADC_Write(ADC_REG_r_refclampsel12v, 1);
	ADC_Write(ADC_REG_g_refclampsel12v, 0);
	ADC_Write(ADC_REG_b_refclampsel12v, 1);
	ADC_Write(ADC_REG_r_intrefen12v, 1);
	ADC_Write(ADC_REG_g_intrefen12v, 1);
	ADC_Write(ADC_REG_b_intrefen12v, 1);
	ADC_Write(ADC_REG_epdy_12v, 0);

	//enable VBG from Audio
	ADC_Write(ADC_REG_cal_manual_en, 0);
    ADC_Write(ADC_REG_cal_manual_th, 0x00);
	ADC_Write(ADC_REG_cal_sw_ctrl_en, 1);
	ADC_Write(ADC_REG_cal_sw_ctrl_th, 0x0b);

	//disable auto source select
	ADC_Write(ADC_REG_ss_mode, 0x1);

#ifdef CONFIG_BOE_HV430FHB_N40
	// Cannot pull down due to Tcon_7 and VGA_R are bonded on N40 panel
	ADC_Write(ADC_REG_r_epd12v, 0x0);
#else
	//Enalbe YPP F switch function
	ADC_Write(ADC_REG_r_epd12v, 0x1);
#endif
	//SOG comparator power down
	ADC_Write(ADC_REG_sog_pwdn,1);

	//Enable LPF
	ADC_Write(ADC_REG_y_scvbs12, 0x2);
	ADC_Write(ADC_REG_lpfmod12v, 0x1);

	//clamp
    ADC_Write(ADC_REG_adc_mode, 0x1);	
    ADC_Write(ADC_REG_clamp_mode, 1);
    ADC_Write(ADC_REG_y_pga12v2_bit0to3, 0);		
	
}

void DRV_ADC_PLL100MHzToCVD2(void)
{
	ADC_DebugMsg("%s %d\n", __FUNCTION__,__LINE__);

	//set PLL power
	ADC_Write(ADC_REG_vbg_sel, 0x3);

	//pll hardware reset disable
	ADC_Write(ADC_REG_cs2_pll_rst_sel, 0x1);

	// Reset all PLL functions
	ADC_Write(ADC_REG_cs2_pll_sw_rst, 1);		// 0x1a[0]
	ADC_Write(ADC_REG_dco_pdiv_rstj , 0x0);		// 0x144[6]
	ADC_Write(ADC_REG_ldo_pwd, 1);				// 0x14a[0]
	ADC_Write(ADC_REG_ldo_pwde, 1);				// 0x14a[1]
	//ADC_Write(ADC_REG_pll_rstn, 0);			// 0x32[0]
	ADC_Write(ADC_REG_pll_pwdn, 0);				// 0x32[1]

	ADC_Write(ADC_REG_ext_clk_muxsel, 0x1);		// ADC_Write(ADC_REG_ext_clk_muxsel, 0x2);
	ADC_Write(ADC_REG_dco_en_fdiv, 0x0);
	ADC_Write(ADC_REG_dco_febdiv, 0x2f);		// 0x143[7:0]
	ADC_Write(ADC_REG_dco_gb, 0x04);				// 0x144[5:0]
	ADC_Write(ADC_REG_dco_ictrl, 0x05);			// 0x145[7:0]
	ADC_Write(ADC_REG_dlpll_pxdiv, 0xb);
	ADC_Write(ADC_REG_dco_refdiv, 0x08);			// 0x147[4:0]
	
	//R-channel clock divider setting
	ADC_Write(ADC_REG_pll_div_sel, 0);
	ADC_Write(ADC_REG_pll_divb_sel, 1);

	//LN_div msb
	ADC_Write(ADC_REG_r_pll_opi, 0);

	// Enable all PLL functions
	//ADC_Write(ADC_REG_ldo_pwd, 0);		// 0x14a[0]
	//ADC_Write(ADC_REG_pll_rstn, 1);		// 0x32[0]
	//ADC_Write(ADC_REG_pll_pwdn, 1);		// 0x32[1]
	
	// For preventing Vcpt floating, PFD reset should be triggered before toggling DCO LPF
	ADC_Write(ADC_REG_cs2_pll_sw_rst, 0x1);		// 0x1a[0]	
	ADC_Write(ADC_REG_cs2_pll_sw_rst, 0x0);		// 0x1a[0]	
	
	//ADC_Write(ADC_REG_dco_pdiv_rstj , 0x1);		// 0x144[6]
		
	// Enable all PLL functions
	ADC_Write(ADC_REG_ldo_pwde, 0);				// 0x14a[1]
	ADC_Write(ADC_REG_ldo_pwd, 0);				// 0x14a[0]
	udelay(10);
	ADC_Write(ADC_REG_cs2_pll_sw_rst, 0x0);		// 0x1a[0]
	ADC_Write(ADC_REG_pll_pwdn, 1);				// 0x32[1]
	udelay(20);
	ADC_Write(ADC_REG_dco_pdiv_rstj , 0x1);		// 0x144[6]

	// DCO LPF
	ADC_Write(ADC_REG_dco_en_fdiv, 0x1);

	ADC_Write(ADC_REG_pdiv_rstn, 0x1);
	ADC_Write(ADC_REG_pll_pdiv_en, 0);
	ADC_Write(ADC_REG_pll_ref_sel, 0x2);
	
	ADC_DelayMS(1);
	ADC_Write(ADC_REG_dlpll_pdiv_rstj, 0x0);
	//ADC_Write(ADC_REG_dlpll_pdiv_rstj, 0x1);
	
	//ADC_Write(ADC_REG_dco_bx2, 0);
    //ADC_Write(ADC_REG_dco_bx2, 0x1);
	
	ADC_Write(ADC_REG_pll_phase_r_sel, 0x8);
	ADC_Write(ADC_REG_pll_phase_g_sel, 0xc);
	ADC_Write(ADC_REG_pll_phase_b_sel, 0x10);
	
	// Preventing PLL lock failed, additional DCO LPF power down and then trigger again.
	//ADC_Write(ADC_REG_ldo_pwde, 1);		// 0x14a[1]
	//	udelay(10);
	//ADC_Write(ADC_REG_ldo_pwde, 0);		// 0x14a[1]
}

void DRV_ADC_Pll_Divider_Power(BOOL Enable)
{
	// Provide for the stability of 100MHz on AV source when power on.
	ADC_Write(ADC_REG_dlpll_pdiv_rstj, Enable);	
	// Set ADC_PLL reference divider reset as normal mode
	ADC_Write(GLB_REG_VCLK_DIV_RSTN, Enable);
	ADC_DebugMsg("Turn %s ADC PLL divider.\n", Enable?"On":"Off");
}

void DRV_ADC_YppShareBandGap_Power(BOOL Enable)
{
    if(Enable)  // turn on MVADC's bandgap
        ADC_Write(ADC_REG_vbg_pwdn,0);
    else        // turn off MVADC's bandgap
        ADC_Write(ADC_REG_vbg_pwdn,1);
}