UTS6710/drivers/hdmi/6710/reg_cec_def.h

#ifndef _REG_CEC_DEF_H_
#define _REG_CEC_DEF_H_
/*
 *@Address: 0xBE1E0000[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R
 *@Description: None
*/
#define CEC_0000_DW_0000		0x58000000

/*
 *@Address: 0xBE1E0000[7:0]
 *@Range: 0~255
 *@Default: 
 *@Access: R
 *@Description:
 *	Rx FIFO datablock
*/
#define CEC_rxData		0x52000000

/*
 *@Address: 0xBE1E0000[8]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	check datablock Start bit
*/
#define CEC_rxData_EOM		0x50400001

/*
 *@Address: 0xBE1E0000[9]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	check datablock ACK
*/
#define CEC_rxData_ACK		0x50410001

/*
 *@Address: 0xBE1E0000[10]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	check datablock EOM
*/
#define CEC_rxData_sbit		0x50420001

/*
 *@Address: 0xBE1E0000[11]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_R_INTR_Status_rx_ddc5v_2_rise		0x50430001

/*
 *@Address: 0xBE1E0000[12]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	Rx FIFO POP process is finished
*/
#define CEC_Rx_FIFO_POP_done		0x50440001

/*
 *@Address: 0xBE1E0000[13]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_R_INTR_Status_rx_ddc5v_2_fall		0x50450001

/*
 *@Address: 0xBE1E0000[14]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_R_INTR_Status_rx_ddc5v_3_rise		0x50460001

/*
 *@Address: 0xBE1E0000[15]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_R_INTR_Status_rx_ddc5v_3_fall		0x50470001

/*
 *@Address: 0xBE1E0000[16]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_tx_noarbit		0x50400002

/*
 *@Address: 0xBE1E0000[17]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_tx_noack		0x50410002

/*
 *@Address: 0xBE1E0000[18]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_tx_eom_done		0x50420002

/*
 *@Address: 0xBE1E0000[19]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_rfifo_overflow		0x50430002

/*
 *@Address: 0xBE1E0000[20]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_rfifo_ready		0x50440002

/*
 *@Address: 0xBE1E0000[21]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_rx_pop_done		0x50450002

/*
 *@Address: 0xBE1E0000[22]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_rx_discon		0x50460002

/*
 *@Address: 0xBE1E0000[23]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_rx_eom		0x50470002

/*
 *@Address: 0xBE1E0000[24]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_ddc5v_0_rise		0x50400003

/*
 *@Address: 0xBE1E0000[25]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_ddc5v_0_fall		0x50410003

/*
 *@Address: 0xBE1E0000[26]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_ddc5v_1_rise		0x50420003

/*
 *@Address: 0xBE1E0000[27]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	interrupt (write 1 clear)
*/
#define CEC_ists_ddc5v_1_fall		0x50430003

/*
 *@Address: 0xBE1E0000[30:28]
 *@Range: 0~7
 *@Default: 
 *@Access: R
 *@Description:
 *	number of Rx FIFO
*/
#define CEC_Rx_FIFO_count		0x50C40003

/*
 *@Address: 0xBE1E0000[31]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	status of Rx FIFO overflow
*/
#define CEC_Rx_FIFO_overflow		0x50470003


/*
 *@Address: 0xBE1E0004[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0004_DW_0004		0x58000004

/*
 *@Address: 0xBE1E0004[3:0]
 *@Range: 0~15
 *@Default: 
 *@Access: R/W
 *@Description:
 *	which block is the EOM
*/
#define CEC_Block_XX_EOM		0x51000004

/*
 *@Address: 0xBE1E0004[4]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	Header block is the EOM
*/
#define CEC_Header_EOM		0x50440004

/*
 *@Address: 0xBE1E0004[8]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	Tx Start transmitting
*/
#define CEC_TransmissionStart		0x50400005

/*
 *@Address: 0xBE1E0004[12]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	POP Rx FIFO data
*/
#define CEC_Rx_FIFO_POP		0x50440005

/*
 *@Address: 0xBE1E0004[19:16]
 *@Range: 0~15
 *@Default: 
 *@Access: R/W
 *@Description:
 *	define follower address
*/
#define CEC_HEADER_follower		0x51000006

/*
 *@Address: 0xBE1E0004[23:20]
 *@Range: 0~15
 *@Default: 
 *@Access: R/W
 *@Description:
 *	define initiator address
*/
#define CEC_HEADER_initiator		0x51040006

/*
 *@Address: 0xBE1E0004[27:24]
 *@Range: 0~15
 *@Default: 
 *@Access: R/W
 *@Description:
 *	adjust ddc5v strobe frequency, in cec_hw.h is reserved
*/
#define CEC_R_strobe_ddc5v_cnt		0x51000007

/*
 *@Address: 0xBE1E0004[28]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	reset fifo
*/
#define CEC_rfifo_rst		0x50440007

/*
 *@Address: 0xBE1E0004[30]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	reduce simulation time
*/
#define CEC_R_testmode		0x50460007


/*
 *@Address: 0xBE1E0008[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0008_DW_0008		0x58000008

/*
 *@Address: 0xBE1E0008[0]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_tx_noarbit
*/
#define CEC_ien_tx_noarbit		0x50400008

/*
 *@Address: 0xBE1E0008[1]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_tx_noack
*/
#define CEC_ien_tx_noack		0x50410008

/*
 *@Address: 0xBE1E0008[2]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_tx_eom_done
*/
#define CEC_ien_tx_eom_done		0x50420008

/*
 *@Address: 0xBE1E0008[3]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_rfifo_overflow
*/
#define CEC_ien_rfifo_overflow		0x50430008

/*
 *@Address: 0xBE1E0008[4]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_rfifo_ready
*/
#define CEC_ien_rfifo_ready		0x50440008

/*
 *@Address: 0xBE1E0008[5]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_rx_pop_done
*/
#define CEC_ien_rx_pop_done		0x50450008

/*
 *@Address: 0xBE1E0008[6]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_rx_discon
*/
#define CEC_ien_rx_discon		0x50460008

/*
 *@Address: 0xBE1E0008[7]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ien_rx_eom
*/
#define CEC_ien_rx_eom		0x50470008

/*
 *@Address: 0xBE1E0008[8]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_0_rise
*/
#define CEC_ien_ddc5v_0_rise		0x50400009

/*
 *@Address: 0xBE1E0008[9]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_0_fall
*/
#define CEC_ien_ddc5v_0_fall		0x50410009

/*
 *@Address: 0xBE1E0008[10]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_1_rise
*/
#define CEC_ien_ddc5v_1_rise		0x50420009

/*
 *@Address: 0xBE1E0008[11]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_1_fall
*/
#define CEC_ien_ddc5v_1_fall		0x50430009

/*
 *@Address: 0xBE1E0008[15:12]
 *@Range: 0~15
 *@Default: 
 *@Access: R/W
 *@Description:
 *	arbitration times (strobe_en)
*/
#define CEC_R_tx_arbit_th		0x51040009

/*
 *@Address: 0xBE1E0008[30:16]
 *@Range: 0~32767
 *@Default: 
 *@Access: R/W
 *@Description:
 *	The response address. 
 *	Default value for TV is [0] = 1
*/
#define CEC_R_res_adr		0x53D00008


/*
 *@Address: 0xBE1E000C[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_000C_DW_000C		0x5800000C

/*
 *@Address: 0xBE1E000C[0]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable cec line
*/
#define CEC_R_cec_en		0x5040000C

/*
 *@Address: 0xBE1E000C[1]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	improvement in wait_newframe, in cec_hw.h is reserved
*/
#define CEC_R_freetime		0x5041000C

/*
 *@Address: 0xBE1E000C[2]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	use strict data bit FSM
*/
#define CEC_R_dbit_strict		0x5042000C

/*
 *@Address: 0xBE1E000C[3]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	data bit discontinuous
*/
#define CEC_R_dbit_discon_reset		0x5043000C

/*
 *@Address: 0xBE1E000C[7:4]
 *@Range: 0~15
 *@Default: 
 *@Access: R/W
 *@Description:
 *	adjust strobe frequency
*/
#define CEC_R_strobe_cnt		0x5104000C

/*
 *@Address: 0xBE1E000C[9:8]
 *@Range: 0~3
 *@Default: 
 *@Access: R/W
 *@Description:
 *	affects fifo ready time
*/
#define CEC_R_rfifo_th		0x5080000D

/*
 *@Address: 0xBE1E000C[12]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	provide  flow control
*/
#define CEC_R_flow_ctl		0x5044000D

/*
 *@Address: 0xBE1E000C[13]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	default 0=> tx_active works, in cec_hw.h is reserved
*/
#define CEC_R_tx_active_ctl		0x5045000D

/*
 *@Address: 0xBE1E000C[14]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	rx receive all data (for test)
*/
#define CEC_R_rx_all		0x5046000D

/*
 *@Address: 0xBE1E000C[15]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	rx receive broadcast data
*/
#define CEC_R_rx_broadcast		0x5047000D

/*
 *@Address: 0xBE1E000C[18:16]
 *@Range: 0~7
 *@Default: 
 *@Access: R/W
 *@Description:
 *	define retry times
*/
#define CEC_R_retry_th		0x50C0000E

/*
 *@Address: 0xBE1E000C[19]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	Error handling
*/
#define CEC_R_errbit_short		0x5043000E

/*
 *@Address: 0xBE1E000C[20]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	clear rfifo overflow satuation
*/
#define CEC_clr_rfifo_overflow		0x5044000E

/*
 *@Address: 0xBE1E000C[21]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	1 => Error handling works
*/
#define CEC_R_errhandle_mode		0x5045000E

/*
 *@Address: 0xBE1E000C[23:22]
 *@Range: 0~3
 *@Default: 
 *@Access: R/W
 *@Description:
 *	Error handling's items
*/
#define CEC_R_errhandle_range		0x5086000E

/*
 *@Address: 0xBE1E000C[31:24]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	p338 CEC revision ID
*/
#define CEC_CEC_revision_ID_01		0x5200000F


/*
 *@Address: 0xBE1E0010[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0010_DW_0010		0x58000010

/*
 *@Address: 0xBE1E0010[7:0]
 *@Range: 0~255
 *@Default: 0x26
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_bit_tran_period		0x52000010

/*
 *@Address: 0xBE1E0010[15:8]
 *@Range: 0~255
 *@Default: 0x26
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_dbit_high_min_period		0x52000011

/*
 *@Address: 0xBE1E0010[23:16]
 *@Range: 0~255
 *@Default: 0x30
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_dbit_low_min_period		0x52000012

/*
 *@Address: 0xBE1E0010[31:24]
 *@Range: 0~255
 *@Default: 0x22
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_dbit_end_min_peiord		0x52000013


/*
 *@Address: 0xBE1E0014[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0014_DW_0014		0x58000014

/*
 *@Address: 0xBE1E0014[7:0]
 *@Range: 0~255
 *@Default: 0x43
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_dbit_end_max_period		0x52000014

/*
 *@Address: 0xBE1E0014[15:8]
 *@Range: 0~255
 *@Default: 0x48
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_sbit_tran_min_period		0x52000015

/*
 *@Address: 0xBE1E0014[23:16]
 *@Range: 0~255
 *@Default: 0x26
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_sbit_end_min_period		0x52000016

/*
 *@Address: 0xBE1E0014[31:24]
 *@Range: 0~255
 *@Default: 0x73
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_retryframe_period		0x52000017


/*
 *@Address: 0xBE1E0018[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0018_DW_0018		0x58000018

/*
 *@Address: 0xBE1E0018[7:0]
 *@Range: 0~255
 *@Default: 0x65
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_rx_dbit_latch_period		0x52000018

/*
 *@Address: 0xBE1E0018[15:8]
 *@Range: 0~255
 *@Default: 0x60
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_rx_dbit_end_min_period		0x52000019

/*
 *@Address: 0xBE1E0018[23:16]
 *@Range: 0~255
 *@Default: 0x43
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_rx_dbit_end_max_period		0x5200001A

/*
 *@Address: 0xBE1E0018[31:24]
 *@Range: 0~255
 *@Default: 0x3a
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_newframe_preiod		0x5200001B


/*
 *@Address: 0xBE1E001C[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_001C_DW_001C		0x5800001C

/*
 *@Address: 0xBE1E001C[7:0]
 *@Range: 0~255
 *@Default: 0x1d
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_tx_dbit_high_period		0x5200001C

/*
 *@Address: 0xBE1E001C[15:8]
 *@Range: 0~255
 *@Default: 0x2b
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_tx_dbit_low_period		0x5200001D

/*
 *@Address: 0xBE1E001C[23:16]
 *@Range: 0~255
 *@Default: 0x2b
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_tx_dbit_end_period		0x5200001E

/*
 *@Address: 0xBE1E001C[31:24]
 *@Range: 0~255
 *@Default: 0x3e
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_tx_sbit_tran_period		0x5200001F


/*
 *@Address: 0xBE1E0020[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0020_DW_0020		0x58000020

/*
 *@Address: 0xBE1E0020[7:0]
 *@Range: 0~255
 *@Default: 0x26
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_tx_sbit_end_period		0x52000020

/*
 *@Address: 0xBE1E0020[15:8]
 *@Range: 0~255
 *@Default: 0x48
 *@Access: R/W
 *@Description:
 *	count number
*/
#define CEC_timer_conframe_period		0x52000021

/*
 *@Address: 0xBE1E0020[16]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	manual control
*/
#define CEC_R_hpd_val_0		0x50400022

/*
 *@Address: 0xBE1E0020[17]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	manual control
*/
#define CEC_R_hpd_val_1		0x50410022

/*
 *@Address: 0xBE1E0020[18]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	manual mode
*/
#define CEC_R_hpd_man		0x50420022

/*
 *@Address: 0xBE1E0020[19]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	manual control
*/
#define CEC_R_hpd_val_2		0x50430022

/*
 *@Address: 0xBE1E0020[20]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	manual control
*/
#define CEC_R_hpd_val_3		0x50440022

/*
 *@Address: 0xBE1E0020[24]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_2_rise
*/
#define CEC_R_INTR_en_rx_ddc5v_2_rise		0x50400023

/*
 *@Address: 0xBE1E0020[25]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_2_fall
*/
#define CEC_R_INTR_en_rx_ddc5v_2_fall		0x50410023

/*
 *@Address: 0xBE1E0020[26]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_3_rise
*/
#define CEC_R_INTR_en_rx_ddc5v_3_rise		0x50420023

/*
 *@Address: 0xBE1E0020[27]
 *@Range: 0~1
 *@Default: 
 *@Access: R/W
 *@Description:
 *	enable ddc5v_3_fall
*/
#define CEC_R_INTR_en_rx_ddc5v_3_fall		0x50430023


/*
 *@Address: 0xBE1E0024[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0024_DW_0024		0x58000024

/*
 *@Address: 0xBE1E0024[7:0]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock00		0x52000024

/*
 *@Address: 0xBE1E0024[15:8]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock01		0x52000025

/*
 *@Address: 0xBE1E0024[23:16]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock02		0x52000026

/*
 *@Address: 0xBE1E0024[31:24]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock03		0x52000027


/*
 *@Address: 0xBE1E0028[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0028_DW_0028		0x58000028

/*
 *@Address: 0xBE1E0028[7:0]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock04		0x52000028

/*
 *@Address: 0xBE1E0028[15:8]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock05		0x52000029

/*
 *@Address: 0xBE1E0028[23:16]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock06		0x5200002A

/*
 *@Address: 0xBE1E0028[31:24]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock07		0x5200002B


/*
 *@Address: 0xBE1E002C[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_002C_DW_002C		0x5800002C

/*
 *@Address: 0xBE1E002C[7:0]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock08		0x5200002C

/*
 *@Address: 0xBE1E002C[15:8]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock09		0x5200002D

/*
 *@Address: 0xBE1E002C[23:16]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock10		0x5200002E

/*
 *@Address: 0xBE1E002C[31:24]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock11		0x5200002F


/*
 *@Address: 0xBE1E0030[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R/W
 *@Description: None
*/
#define CEC_0030_DW_0030		0x58000030

/*
 *@Address: 0xBE1E0030[7:0]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock12		0x52000030

/*
 *@Address: 0xBE1E0030[15:8]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock13		0x52000031

/*
 *@Address: 0xBE1E0030[23:16]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock14		0x52000032

/*
 *@Address: 0xBE1E0030[31:24]
 *@Range: 0~255
 *@Default: 
 *@Access: R/W
 *@Description:
 *	datablock from mmio
*/
#define CEC_DataBlock15		0x52000033


/*
 *@Address: 0xBE1E0034[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: R
 *@Description: None
*/
#define CEC_0034_DW_0034		0x58000034

/*
 *@Address: 0xBE1E0034[0]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	rfifo is empry in mmclk domain
*/
#define CEC_rfifo_empty		0x50400034

/*
 *@Address: 0xBE1E0034[2]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	ddc5v_2 out in mmclk domain
*/
#define CEC_ddc5v_2		0x50420034

/*
 *@Address: 0xBE1E0034[3]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	ddc5v_3 out in mmclk domain
*/
#define CEC_ddc5v_3		0x50430034

/*
 *@Address: 0xBE1E0034[4]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	CEC_in  in sclk domain
*/
#define CEC_cec_in_sclk		0x50440034

/*
 *@Address: 0xBE1E0034[5]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	CEC_out in sclk domain
*/
#define CEC_cec_out_sclk		0x50450034

/*
 *@Address: 0xBE1E0034[6]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	ddc5v_0 out in mmclk domain
*/
#define CEC_ddc5v_0		0x50460034

/*
 *@Address: 0xBE1E0034[7]
 *@Range: 0~1
 *@Default: 
 *@Access: R
 *@Description:
 *	ddc5v_1 out in mmclk domain
*/
#define CEC_ddc5v_1		0x50470034

/*
 *@Address: 0xBE1E0034[14:8]
 *@Range: 0~127
 *@Default: 
 *@Access: R
 *@Description:
 *	tx FSM state in sclk domain
*/
#define CEC_tx_state		0x51C00035

/*
 *@Address: 0xBE1E0034[20:16]
 *@Range: 0~31
 *@Default: 
 *@Access: R
 *@Description:
 *	rx FSM state in sclk domain
*/
#define CEC_rx_state		0x51400036

/*
 *@Address: 0xBE1E0034[28:24]
 *@Range: 0~31
 *@Default: 
 *@Access: R
 *@Description:
 *	tx data read pointer (sclk)
*/
#define CEC_tdata_rptr_sclk		0x51400037


#endif