UTS6710/drivers/hdmi/6710/reg_hdmirx_cbus_def.h

#ifndef _REG_HDMIRX_CBUS_DEF_H_
#define _REG_HDMIRX_CBUS_DEF_H_
/*
 *@Address: 0xBE290000[31:0]
 *@Range: 0~4294967295
 *@Default: 0x203100
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0000_DW_0000		0x68000000

/*
 *@Address: 0xBE290000[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Identify current connected and power state
*/
#define HDMIRX_CBUS_r_dev_state		0x62000000

/*
 *@Address: 0xBE290000[15:8]
 *@Range: 0~255
 *@Default: 0x20
 *@Access: r/w
 *@Description:
 *	Identify level of MHL spec supported.
*/
#define HDMIRX_CBUS_r_mhl_version		0x62000001

/*
 *@Address: 0xBE290000[23:16]
 *@Range: 0~255
 *@Default: 0x31
 *@Access: r/w
 *@Description:
 *	Identify the type of MHL system
*/
#define HDMIRX_CBUS_r_dev_cat		0x62000002

/*
 *@Address: 0xBE290000[31:24]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	High-order byte of Adopter identifier, assigned by MHL, LLC
*/
#define HDMIRX_CBUS_r_adopter_id_h		0x62000003


/*
 *@Address: 0xBE290004[31:0]
 *@Range: 0~4294967295
 *@Default: 0x13f00
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0004_DW_0004		0x68000004

/*
 *@Address: 0xBE290004[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Low-order byte of Adopter identifier, assigned by MHL, LLC
*/
#define HDMIRX_CBUS_r_adopter_id_l		0x62000004

/*
 *@Address: 0xBE290004[15:8]
 *@Range: 0~255
 *@Default: 0x3f
 *@Access: r/w
 *@Description:
 *	List of link modes supported of video.
*/
#define HDMIRX_CBUS_r_vid_link_mode		0x62000005

/*
 *@Address: 0xBE290004[23:16]
 *@Range: 0~255
 *@Default: 0x01
 *@Access: r/w
 *@Description:
 *	List of link modes supported of audio.
*/
#define HDMIRX_CBUS_r_aud_link_mode		0x62000006

/*
 *@Address: 0xBE290004[31:24]
 *@Range: 0~255
 *@Default: 0x00
 *@Access: r/w
 *@Description:
 *	List of video types supported.
*/
#define HDMIRX_CBUS_r_video_type		0x62000007


/*
 *@Address: 0xBE290008[31:0]
 *@Range: 0~4294967295
 *@Default: 0x70f47
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0008_DW_0008		0x68000008

/*
 *@Address: 0xBE290008[7:0]
 *@Range: 0~255
 *@Default: 0x47
 *@Access: r/w
 *@Description:
 *	Map of logical device types.
*/
#define HDMIRX_CBUS_r_log_dev_map		0x62000008

/*
 *@Address: 0xBE290008[15:8]
 *@Range: 0~255
 *@Default: 0x0f
 *@Access: r/w
 *@Description:
 *	Upper bound of MHL link bandwidth.
*/
#define HDMIRX_CBUS_r_bandwidth		0x62000009

/*
 *@Address: 0xBE290008[23:16]
 *@Range: 0~255
 *@Default: 0x07
 *@Access: r/w
 *@Description:
 *	Set flag for each MHL optional feature.
*/
#define HDMIRX_CBUS_r_feature_flag		0x6200000A

/*
 *@Address: 0xBE290008[31:24]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	High-order byte of system identifier, assigned by Adopter.
*/
#define HDMIRX_CBUS_r_device_id_h		0x6200000B


/*
 *@Address: 0xBE29000C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x331000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_000C_DW_000C		0x6800000C

/*
 *@Address: 0xBE29000C[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Low-order byte of system identifier, assigned by Adopter.
*/
#define HDMIRX_CBUS_r_device_id_l		0x6200000C

/*
 *@Address: 0xBE29000C[15:8]
 *@Range: 0~255
 *@Default: 0x10
 *@Access: r/w
 *@Description:
 *	Total count of Scratchpad Registers.
*/
#define HDMIRX_CBUS_r_scratchpad_size		0x6200000D

/*
 *@Address: 0xBE29000C[23:16]
 *@Range: 0~255
 *@Default: 0x33
 *@Access: r/w
 *@Description:
 *	Total count of interrupt and status registers.
*/
#define HDMIRX_CBUS_r_int_stat_size		0x6200000E


/*
 *@Address: 0xBE290020[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0020_DW_0020		0x68000020

/*
 *@Address: 0xBE290020[4:0]
 *@Range: 0~31
 *@Default: 0
 *@Access: r
 *@Description:
 *	Device register change.
 *	[0]:DCAP_CHG.
 *	[1]:DSCR_CHG.
 *	[2]:REQ_WRT.
 *	[3]:GRT_WRT.
 *	[4]:3D_REQ.
*/
#define HDMIRX_CBUS_r_drc_intr_status		0x61400020

/*
 *@Address: 0xBE290020[9:8]
 *@Range: 0~3
 *@Default: 0
 *@Access: r
 *@Description:
 *	[0]: reserved.
 *	[1]: EDID content change on virtual DDC channel.
*/
#define HDMIRX_CBUS_r_dsc_intr_status		0x60800021


/*
 *@Address: 0xBE290030[31:0]
 *@Range: 0~4294967295
 *@Default: 0x300
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0030_DW_0030		0x68000030

/*
 *@Address: 0xBE290030[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r
 *@Description:
 *	DCAP_RDY: source capability register values are stable.
*/
#define HDMIRX_CBUS_r_connected_rdy_status		0x60400030

/*
 *@Address: 0xBE290030[12:8]
 *@Range: 0~31
 *@Default: 0x03
 *@Access: r
 *@Description:
 *	LINK_MODE :
 *	[2:0]: CLK_MODE : 
 *	3¡¦b011:normal clock.
 *	3¡¦b010:packedpixel clock.
 *	Others: reserved.
 *	[3]: PATH_EN:
 *	0:TMDS path isn¡¦t in use.
 *	[4]: MUTED:
 *	    1:Device¡¦s content stream is muted.
*/
#define HDMIRX_CBUS_r_link_mode_status		0x61400031

/*
 *@Address: 0xBE290030[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	Device status registers 0032
*/
#define HDMIRX_CBUS_r_device_status_32R		0x62000032

/*
 *@Address: 0xBE290030[31:24]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	Device status registers 0033
*/
#define HDMIRX_CBUS_r_device_status_33R		0x62000033


/*
 *@Address: 0xBE290040[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0040_DW_0040		0x68000040

/*
 *@Address: 0xBE290040[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r
 *@Description:
 *	Device Scratchpad Registers
*/
#define HDMIRX_CBUS_r_scratchpad_dataa		0x68000040


/*
 *@Address: 0xBE290044[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0044_DW_0044		0x68000044

/*
 *@Address: 0xBE290044[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r
 *@Description:
 *	Device Scratchpad Registers
*/
#define HDMIRX_CBUS_r_scratchpad_datab		0x68000044


/*
 *@Address: 0xBE290048[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0048_DW_0048		0x68000048

/*
 *@Address: 0xBE290048[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r
 *@Description:
 *	Device Scratchpad Registers
*/
#define HDMIRX_CBUS_r_scratchpad_datac		0x68000048


/*
 *@Address: 0xBE29004C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_004C_DW_004C		0x6800004C

/*
 *@Address: 0xBE29004C[31:2]
 *@Range: 0~1073741823
 *@Default: 0
 *@Access: r
 *@Description:
 *	Device Scratchpad Registers
*/
#define HDMIRX_CBUS_r_scratchpad_datad		0x6782004C


/*
 *@Address: 0xBE290080[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0080_DW_0080		0x68000080

/*
 *@Address: 0xBE290080[15:0]
 *@Range: 0~65535
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Device Scratchpad Registers data valid.
*/
#define HDMIRX_CBUS_r_scratchpad_data_valid		0x64000080


/*
 *@Address: 0xBE290100[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0100_DW_0100		0x68000100

/*
 *@Address: 0xBE290100[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	READ_DEVCAP command: request
*/
#define HDMIRX_CBUS_r_red_devc_req		0x60400100

/*
 *@Address: 0xBE290100[15:8]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	READ_DEVCAP command: offset
*/
#define HDMIRX_CBUS_r_red_devc_offset		0x62000101

/*
 *@Address: 0xBE290100[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	READ_DEVCAP command: return value.
*/
#define HDMIRX_CBUS_r_red_devc_data_reg		0x62000102

/*
 *@Address: 0xBE290100[27:24]
 *@Range: 0~15
 *@Default: 0
 *@Access: r
 *@Description:
 *	READ_DEVCAP command: fail
 *	[3]:msc_s_nack_event,
 *	[2]:msc_s_abort_event,
 *	[1]:red_devc_offset_invalid,
 *	[0]:red_devc_fail
*/
#define HDMIRX_CBUS_r_red_devc_fail_reg		0x61000103


/*
 *@Address: 0xBE290110[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0110_DW_0110		0x68000110

/*
 *@Address: 0xBE290110[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_STATE command: request
*/
#define HDMIRX_CBUS_r_wrt_stat_req		0x60400110

/*
 *@Address: 0xBE290110[11:8]
 *@Range: 0~15
 *@Default: 0
 *@Access: r
 *@Description:
 *	WRITE_STATE command: fail
 *	[3]:msc_s_nack_event,
 *	[2]:msc_s_abort_event,
 *	[1]:wrt_stat_offset_invalid,
 *	[0]:wrt_stat_fail
*/
#define HDMIRX_CBUS_r_wrt_stat_fail_reg		0x61000111


/*
 *@Address: 0xBE290120[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0120_DW_0120		0x68000120

/*
 *@Address: 0xBE290120[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_STATE command: offset
*/
#define HDMIRX_CBUS_r_wrt_stat_offset_i		0x62000120

/*
 *@Address: 0xBE290120[15:8]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_STATE command: value
*/
#define HDMIRX_CBUS_r_wrt_stat_din		0x62000121


/*
 *@Address: 0xBE290140[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0140_DW_0140		0x68000140

/*
 *@Address: 0xBE290140[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_BURST command : request
*/
#define HDMIRX_CBUS_r_wrt_burst_req		0x60400140

/*
 *@Address: 0xBE290140[11:8]
 *@Range: 0~15
 *@Default: 
 *@Access: r
 *@Description:
 *	WRITE_ BURST command: fail
 *	[3]:msc_s_nack_event,
 *	[2]:msc_s_abort_event,
 *	[1]:wrt_burst_offset_invalid,
 *	[0]:wrt_burst_fail
*/
#define HDMIRX_CBUS_r_wrt_burst_fail_reg		0x61000141

/*
 *@Address: 0xBE290140[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_ BURST command: offset
*/
#define HDMIRX_CBUS_r_wrt_burst_offset_i		0x62000142


/*
 *@Address: 0xBE290144[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0144_DW_0144		0x68000144

/*
 *@Address: 0xBE290144[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_ BURST command: 
 *	data [31:0]
*/
#define HDMIRX_CBUS_r_wrt_burst_dina		0x68000144


/*
 *@Address: 0xBE290148[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0148_DW_0148		0x68000148

/*
 *@Address: 0xBE290148[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_ BURST command:
 *	data [63:32]
*/
#define HDMIRX_CBUS_r_wrt_burst_dinb		0x68000148


/*
 *@Address: 0xBE29014C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_014C_DW_014C		0x6800014C

/*
 *@Address: 0xBE29014C[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_ BURST command:
 *	data [95:64]
*/
#define HDMIRX_CBUS_r_wrt_burst_dinc		0x6800014C


/*
 *@Address: 0xBE290150[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0150_DW_0150		0x68000150

/*
 *@Address: 0xBE290150[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_ BURST command:
 *	data [127:96]
*/
#define HDMIRX_CBUS_r_wrt_burst_dind		0x68000150


/*
 *@Address: 0xBE290154[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0154_DW_0154		0x68000154

/*
 *@Address: 0xBE290154[4:0]
 *@Range: 0~31
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_ BURST command:
 *	The number of data will be sent.
*/
#define HDMIRX_CBUS_r_wrt_burst_num		0x61400154


/*
 *@Address: 0xBE290180[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0180_DW_0180		0x68000180

/*
 *@Address: 0xBE290180[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Clear scratchpad registers
*/
#define HDMIRX_CBUS_r_scratchpad_clear		0x60400180


/*
 *@Address: 0xBE2901A0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_01A0_DW_01A0		0x680001A0

/*
 *@Address: 0xBE2901A0[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	SET_HPD command: request
*/
#define HDMIRX_CBUS_r_set_hpd_req		0x604001A0

/*
 *@Address: 0xBE2901A0[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	SET_HPD command: fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: set_hpd_fail
*/
#define HDMIRX_CBUS_r_set_hpd_fail_reg		0x60C001A1


/*
 *@Address: 0xBE2901B0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_01B0_DW_01B0		0x680001B0

/*
 *@Address: 0xBE2901B0[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	CLR_HPD command: request
*/
#define HDMIRX_CBUS_r_clr_hpd_req		0x604001B0

/*
 *@Address: 0xBE2901B0[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	CLR_HPD command: fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: clr_hpd_fail
*/
#define HDMIRX_CBUS_r_clr_hpd_fail_reg		0x60C001B1


/*
 *@Address: 0xBE2901C0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_01C0_DW_01C0		0x680001C0

/*
 *@Address: 0xBE2901C0[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_STATE command: request
*/
#define HDMIRX_CBUS_r_get_state_req		0x604001C0

/*
 *@Address: 0xBE2901C0[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_STATE command: fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: get_state_fail
*/
#define HDMIRX_CBUS_r_get_state_fail_reg		0x60C001C1

/*
 *@Address: 0xBE2901C0[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_STATE command: data
*/
#define HDMIRX_CBUS_r_get_state_data		0x620001C2


/*
 *@Address: 0xBE2901D0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_01D0_DW_01D0		0x680001D0

/*
 *@Address: 0xBE2901D0[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_VENDOR_ID command: request
*/
#define HDMIRX_CBUS_r_get_ven_id_req		0x604001D0

/*
 *@Address: 0xBE2901D0[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_VENDOR_ID command: fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: get_ven_id_fail
*/
#define HDMIRX_CBUS_r_get_ven_id_fail_reg		0x60C001D1

/*
 *@Address: 0xBE2901D0[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_VENDOR_ID command: data
*/
#define HDMIRX_CBUS_r_get_ven_id_data		0x620001D2


/*
 *@Address: 0xBE2901D4[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_01D4_DW_01D4		0x680001D4

/*
 *@Address: 0xBE2901D4[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Our ID
*/
#define HDMIRX_CBUS_r_vendor_id		0x620001D4


/*
 *@Address: 0xBE2901E0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_01E0_DW_01E0		0x680001E0

/*
 *@Address: 0xBE2901E0[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_DDC_ERRORCODE command: request
*/
#define HDMIRX_CBUS_r_get_ddc_err_req		0x604001E0

/*
 *@Address: 0xBE2901E0[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_DDC_ERRORCODE command: 
 *	fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: get_ddc_err_fail
*/
#define HDMIRX_CBUS_r_get_ddc_err_fail_reg		0x60C001E1

/*
 *@Address: 0xBE2901E0[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_DDC_ERRORCODE command: 
 *	data
*/
#define HDMIRX_CBUS_r_get_ddc_err_data		0x620001E2


/*
 *@Address: 0xBE2901F0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_01F0_DW_01F0		0x680001F0

/*
 *@Address: 0xBE2901F0[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_MSC_ERRORCODE command: request
*/
#define HDMIRX_CBUS_r_get_msc_err_req		0x604001F0

/*
 *@Address: 0xBE2901F0[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_ MSC _ERRORCODE command: 
 *	fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: get_msc_err_fail
*/
#define HDMIRX_CBUS_r_get_msc_err_fail_reg		0x60C001F1

/*
 *@Address: 0xBE2901F0[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_ MSC _ERRORCODE command: 
 *	data
*/
#define HDMIRX_CBUS_r_get_msc_err_data		0x620001F2


/*
 *@Address: 0xBE290200[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0200_DW_0200		0x68000200

/*
 *@Address: 0xBE290200[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_SRC1_ERRORCODE command: request
*/
#define HDMIRX_CBUS_r_get_src1_err_req		0x60400200

/*
 *@Address: 0xBE290200[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_ SRC1_ERRORCODE command: 
 *	fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: get_src1_err_fail
*/
#define HDMIRX_CBUS_r_get_src1_err_fail_reg		0x60C00201

/*
 *@Address: 0xBE290200[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_ SRC1_ERRORCODE command: 
 *	data
*/
#define HDMIRX_CBUS_r_get_src1_err_data		0x62000202


/*
 *@Address: 0xBE290210[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0210_DW_0210		0x68000210

/*
 *@Address: 0xBE290210[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_SRC3_ERRORCODE command: request
*/
#define HDMIRX_CBUS_r_get_src3_err_req		0x60400210

/*
 *@Address: 0xBE290210[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_ SRC3_ERRORCODE command: 
 *	fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: get_src3_err_fail
*/
#define HDMIRX_CBUS_r_get_src3_err_fail_reg		0x60C00211

/*
 *@Address: 0xBE290210[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	GET_ SRC3_ERRORCODE command: data
*/
#define HDMIRX_CBUS_r_get_src3_err_data		0x62000212


/*
 *@Address: 0xBE290300[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0300_DW_0300		0x68000300

/*
 *@Address: 0xBE290300[0]
 *@Range: 0~1
 *@Default: 
 *@Access: 
 *@Description:
 *	RAP command: request
*/
#define HDMIRX_CBUS_r_rap_cmd_req		0x60400300

/*
 *@Address: 0xBE290300[10:8]
 *@Range: 0~7
 *@Default: 
 *@Access: 
 *@Description:
 *	RAP command: 
 *	fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: rap_cmd_fail: no rapk, command fail.
*/
#define HDMIRX_CBUS_r_rap_cmd_fail_reg		0x60C00301

/*
 *@Address: 0xBE290300[23:16]
 *@Range: 0~255
 *@Default: 
 *@Access: 
 *@Description:
 *	RAP command: 
 *	¡¥h00:poll
 *	¡¥h10: change to CONTENT_ON state
 *	¡¥h11: change to CONTENT_OFF state.
*/
#define HDMIRX_CBUS_r_rap_cmd_code		0x62000302

/*
 *@Address: 0xBE290300[31:24]
 *@Range: 0~255
 *@Default: 
 *@Access: 
 *@Description:
 *	RAP command:
 *	RAPK data (status codes)from source acknowledges RAP cmd of sink.
*/
#define HDMIRX_CBUS_r_rap_cmd_rapk		0x62000303


/*
 *@Address: 0xBE290304[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0304_DW_0304		0x68000304

/*
 *@Address: 0xBE290304[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	RAPK command: request
*/
#define HDMIRX_CBUS_r_rap_act_ack_req		0x60400304

/*
 *@Address: 0xBE290304[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r
 *@Description:
 *	RAPK command: 
 *	fail
 *	[2]:msc_s_nack_event,
 *	[1]:msc_s_abort_event,
 *	[0]: rap_act_ack_fail
*/
#define HDMIRX_CBUS_r_rap_act_ack_fail_reg		0x60C00305

/*
 *@Address: 0xBE290304[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	RAPK command: 
 *	Request action protocol status codes.
 *	¡¥h00: No error.
 *	¡¥h01: Unrecognized Action code
 *	¡¥h02: Unsupported Action code
 *	¡¥h03: Responder Busy
*/
#define HDMIRX_CBUS_r_rap_act_ack_code		0x62000306


/*
 *@Address: 0xBE290308[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0308_DW_0308		0x68000308

/*
 *@Address: 0xBE290308[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	RAP code of source.
 *	¡¥h00:poll
 *	¡¥h10: change to CONTENT_ON state
 *	¡¥h11: change to CONTENT_OFF state.
*/
#define HDMIRX_CBUS_r_rap_act_code		0x62000308


/*
 *@Address: 0xBE290400[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0400_DW_0400		0x68000400

/*
 *@Address: 0xBE290400[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	RCP command: request
*/
#define HDMIRX_CBUS_r_rcp_cmd_req		0x60400400

/*
 *@Address: 0xBE290400[11:8]
 *@Range: 0~15
 *@Default: 0
 *@Access: r
 *@Description:
 *	RCP command: 
 *	fail
 *	[3]:msc_s_nack_event,
 *	[2]:msc_s_abort_event,
 *	[1]:rcp_cmd_ineffect_code
 *	[0]: rcp_cmd_fail
*/
#define HDMIRX_CBUS_r_rcp_cmd_fail_reg		0x61000401

/*
 *@Address: 0xBE290400[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	RCP command: 
 *	RCP key codes. Refer to MHL spec.
*/
#define HDMIRX_CBUS_r_rcp_cmd_code		0x62000402

/*
 *@Address: 0xBE290400[31:24]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	RCP command: 
 *	It is RCPK key code from source to confirm RCP cmd.
*/
#define HDMIRX_CBUS_r_rcp_cmd_rcpk_code_from_src		0x62000403


/*
 *@Address: 0xBE290404[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0404_DW_0404		0x68000404

/*
 *@Address: 0xBE290404[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	RCP command: 
 *	It is RCPE status code from source to confirm RCP command error.
*/
#define HDMIRX_CBUS_r_rcp_cmd_rcpe_statuscode_from_src		0x62000404


/*
 *@Address: 0xBE290420[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0420_DW_0420		0x68000420

/*
 *@Address: 0xBE290420[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	It is a request command of read-trigger to read rcp data in fifo that is sent from source.
*/
#define HDMIRX_CBUS_r_rcp_act_ack		0x60400420

/*
 *@Address: 0xBE290420[15:8]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	RCP data (key id) from source.
*/
#define HDMIRX_CBUS_r_rcp_act_code		0x62000421

/*
 *@Address: 0xBE290420[20:16]
 *@Range: 0~31
 *@Default: 0
 *@Access: r
 *@Description:
 *	The total number of RCP data (key ID) in fifo.
*/
#define HDMIRX_CBUS_r_rcp_act_num		0x61400422


/*
 *@Address: 0xBE290430[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0000221F
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0430_DW_0430		0x68000430

/*
 *@Address: 0xBE290430[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0000221F
 *@Access: r/w
 *@Description:
 *	RCP key codes enable. About more detailed key ID, please refer to spec.
 *	430[0]=1
 *	key ID 7¡¥h00 function exist.
 *	430[1]=1
 *	key ID 7¡¥h01 function exist.
 *	¡K¡K¡K¡K.
 *	43C[31]=1:
 *	key ID 7¡¥h7F function exist.
*/
#define HDMIRX_CBUS_r_rcp_vd_key_mapa		0x68000430


/*
 *@Address: 0xBE290434[31:0]
 *@Range: 0~4294967295
 *@Default: 0x000F0BFF
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0434_DW_0434		0x68000434

/*
 *@Address: 0xBE290434[31:0]
 *@Range: 0~4294967295
 *@Default: 0x000F0BFF
 *@Access: r/w
 *@Description:
 *	RCP key codes enable. About more detailed key ID, please refer to spec.
 *	430[0]=1
 *	key ID 7¡¥h00 function exist.
 *	430[1]=1
 *	key ID 7¡¥h01 function exist.
 *	¡K¡K¡K¡K.
 *	43C[31]=1:
 *	key ID 7¡¥h7F function exist.
*/
#define HDMIRX_CBUS_r_rcp_vd_key_mapb		0x68000434


/*
 *@Address: 0xBE290438[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0438_DW_0438		0x68000438

/*
 *@Address: 0xBE290438[31:0]
 *@Range: 0~4294967295
 *@Default: 0x00001FFE
 *@Access: r/w
 *@Description:
 *	RCP key codes enable. About more detailed key ID, please refer to spec.
 *	430[0]=1
 *	key ID 7¡¥h00 function exist.
 *	430[1]=1
 *	key ID 7¡¥h01 function exist.
 *	¡K¡K¡K¡K.
 *	43C[31]=1:
 *	key ID 7¡¥h7F function exist.
*/
#define HDMIRX_CBUS_r_rcp_vd_key_mapc		0x68000438


/*
 *@Address: 0xBE29043C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0000007F
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_043C_DW_043C		0x6800043C

/*
 *@Address: 0xBE29043C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0000007F
 *@Access: r/w
 *@Description:
 *	RCP key codes enable. About more detailed key ID, please refer to spec.
 *	430[0]=1
 *	key ID 7¡¥h00 function exist.
 *	430[1]=1
 *	key ID 7¡¥h01 function exist.
 *	¡K¡K¡K¡K.
 *	43C[31]=1:
 *	key ID 7¡¥h7F function exist.
*/
#define HDMIRX_CBUS_r_rcp_vd_key_mapd		0x6800043C


/*
 *@Address: 0xBE290500[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0500_DW_0500		0x68000500

/*
 *@Address: 0xBE290500[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP command: request
*/
#define HDMIRX_CBUS_r_ucp_cmd_req		0x60400500

/*
 *@Address: 0xBE290500[11:8]
 *@Range: 0~15
 *@Default: 0
 *@Access: r
 *@Description:
 *	UCP command: 
 *	fail
 *	[3]:msc_s_nack_event,
 *	[2]:msc_s_abort_event,
 *	[1]:ucp_cmd_ineffect_code
 *	[0]: ucp_cmd_fail
*/
#define HDMIRX_CBUS_r_ucp_cmd_fail_reg		0x61000501

/*
 *@Address: 0xBE290500[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP command: 
 *	UCP character code.
*/
#define HDMIRX_CBUS_r_ucp_cmd_code		0x62000502

/*
 *@Address: 0xBE290500[31:24]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	UCP command: 
 *	It is UCPK key code from source to confirm UCP cmd.
*/
#define HDMIRX_CBUS_r_ucp_cmd_ucpk_code_from_src		0x62000503


/*
 *@Address: 0xBE290504[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0504_DW_0504		0x68000504

/*
 *@Address: 0xBE290504[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	UCP command: 
 *	It is UCPE status code from source to confirm UCP command error.
*/
#define HDMIRX_CBUS_r_ucp_cmd_ucpe_statuscode_from_src		0x62000504


/*
 *@Address: 0xBE290520[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0520_DW_0520		0x68000520

/*
 *@Address: 0xBE290520[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	It is a request command of read-trigger to read ucp data in fifo that is sent from source.
*/
#define HDMIRX_CBUS_r_ucp_act_ack		0x60400520

/*
 *@Address: 0xBE290520[15:8]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	UCP code from source.
*/
#define HDMIRX_CBUS_r_ucp_act_code		0x62000521

/*
 *@Address: 0xBE290520[20:16]
 *@Range: 0~31
 *@Default: 0
 *@Access: r
 *@Description:
 *	The total number of UCP data in fifo.
*/
#define HDMIRX_CBUS_r_ucp_act_num		0x61400522


/*
 *@Address: 0xBE290530[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0530_DW_0530		0x68000530

/*
 *@Address: 0xBE290530[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0x00~8'h1F.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_mapa		0x68000530


/*
 *@Address: 0xBE290534[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0534_DW_0534		0x68000534

/*
 *@Address: 0xBE290534[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0x20~8'h3F.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_mapb		0x68000534


/*
 *@Address: 0xBE290538[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0538_DW_0538		0x68000538

/*
 *@Address: 0xBE290538[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0x40~8'h5F.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_mapc		0x68000538


/*
 *@Address: 0xBE29053C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_053C_DW_053C		0x6800053C

/*
 *@Address: 0xBE29053C[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0x60~8'h7F.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_mapd		0x6800053C


/*
 *@Address: 0xBE290540[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0540_DW_0540		0x68000540

/*
 *@Address: 0xBE290540[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0x80~8'h9F.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_mape		0x68000540


/*
 *@Address: 0xBE290544[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0544_DW_0544		0x68000544

/*
 *@Address: 0xBE290544[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0xA0~8'hBF.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_mapf		0x68000544


/*
 *@Address: 0xBE290548[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0548_DW_0548		0x68000548

/*
 *@Address: 0xBE290548[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0xC0~8'hDF.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_mapg		0x68000548


/*
 *@Address: 0xBE29054C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_054C_DW_054C		0x6800054C

/*
 *@Address: 0xBE29054C[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP character code bits.
 *	supporting UCP code 0xE0~8'hFF.
*/
#define HDMIRX_CBUS_r_ucp_vd_key_maph		0x6800054C


/*
 *@Address: 0xBE290600[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0600_DW_0600		0x68000600

/*
 *@Address: 0xBE290600[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	EDID address from source .
*/
#define HDMIRX_CBUS_r_EDID_adr		0x62000600

/*
 *@Address: 0xBE290600[15:8]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	EDID segment value.
*/
#define HDMIRX_CBUS_r_EDID_seg		0x62000601

/*
 *@Address: 0xBE290600[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	EDID data that source want.
*/
#define HDMIRX_CBUS_r_EDID_dout		0x62000602


/*
 *@Address: 0xBE290604[31:0]
 *@Range: 0~4294967295
 *@Default: 0x600000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0604_DW_0604		0x68000604

/*
 *@Address: 0xBE290604[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Software controls EDID read. 
 *	1: enable. The registers related to software are 0600, 0601, 0602 and 0F1B.
*/
#define HDMIRX_CBUS_r_dcc_software_ctrl		0x60400604

/*
 *@Address: 0xBE290604[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: enable DDC segment function.
*/
#define HDMIRX_CBUS_r_ddc_seg_en		0x60400605

/*
 *@Address: 0xBE290604[23:16]
 *@Range: 0~255
 *@Default: 0x60
 *@Access: r/w
 *@Description:
 *	Segment ID.
*/
#define HDMIRX_CBUS_r_ddc_seg_id		0x62000606

/*
 *@Address: 0xBE290604[31:24]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Segment read max value.
*/
#define HDMIRX_CBUS_r_ddc_seg_max		0x62000607


/*
 *@Address: 0xBE290608[31:0]
 *@Range: 0~4294967295
 *@Default: 0x74A0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0608_DW_0608		0x68000608

/*
 *@Address: 0xBE290608[7:0]
 *@Range: 0~255
 *@Default: 0xA0
 *@Access: r/w
 *@Description:
 *	EDID ID
*/
#define HDMIRX_CBUS_r_ddc_edid_id		0x62000608

/*
 *@Address: 0xBE290608[15:8]
 *@Range: 0~255
 *@Default: 0x74
 *@Access: r/w
 *@Description:
 *	HDCP ID
*/
#define HDMIRX_CBUS_r_ddc_hdcp_id		0x62000609


/*
 *@Address: 0xBE290700[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0700_DW_0700		0x68000700

/*
 *@Address: 0xBE290700[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	DDC address from source
*/
#define HDMIRX_CBUS_r_OTHR_adr		0x62000700

/*
 *@Address: 0xBE290700[15:8]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	DDC segment value
*/
#define HDMIRX_CBUS_r_OTHR_seg		0x62000701

/*
 *@Address: 0xBE290700[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r
 *@Description:
 *	1:DDC device write
 *	0: DDC device read
*/
#define HDMIRX_CBUS_r_OTHR_wrt		0x60400702

/*
 *@Address: 0xBE290700[31:24]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	DDC device data from source
*/
#define HDMIRX_CBUS_r_OTHR_din		0x62000703


/*
 *@Address: 0xBE290704[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0704_DW_0704		0x68000704

/*
 *@Address: 0xBE290704[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	DDC device data that source want.
*/
#define HDMIRX_CBUS_r_OTHR_dout		0x62000704


/*
 *@Address: 0xBE290708[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0708_DW_0708		0x68000708

/*
 *@Address: 0xBE290708[8:0]
 *@Range: 0~511
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	DDC device ID
*/
#define HDMIRX_CBUS_r_ddc_othr_id		0x62400708


/*
 *@Address: 0xBE290820[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0820_DW_0820		0x68000820

/*
 *@Address: 0xBE290820[7:0]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	DDC error for source command.
*/
#define HDMIRX_CBUS_r_ddc_errcode		0x62000820

/*
 *@Address: 0xBE290820[15:8]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	0ABB[0]=0 : 
 *	MSC error for source command
 *	0ABB[0]=1 : 
 *	MSC error for sink command
*/
#define HDMIRX_CBUS_r_msc_errcode		0x62000821

/*
 *@Address: 0xBE290820[23:16]
 *@Range: 0~255
 *@Default: 0
 *@Access: r
 *@Description:
 *	MSC error for sink command
*/
#define HDMIRX_CBUS_r_msc_s_errcode		0x62000822


/*
 *@Address: 0xBE290828[31:0]
 *@Range: 0~4294967295
 *@Default: 0x10000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0828_DW_0828		0x68000828

/*
 *@Address: 0xBE290828[1:0]
 *@Range: 0~3
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	[0] =1 :enable link incomplete package detection
 *	[1]=1 :enable link retry exceeded detection
*/
#define HDMIRX_CBUS_r_lnk_err_ctrl		0x60800828

/*
 *@Address: 0xBE290828[10:8]
 *@Range: 0~7
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:Recover to original timer.
 *	0:disable.
 *	[0]:msc_s_timer_insurance
 *	[1]:msc_r_timer_insurance
 *	[2]:ddc_timer_insurance
*/
#define HDMIRX_CBUS_r_timer_insurance_reg		0x60C00829

/*
 *@Address: 0xBE290828[16]
 *@Range: 0~1
 *@Default: 1
 *@Access: r/w
 *@Description:
 *	1: abort package is not restricted by timer.
*/
#define HDMIRX_CBUS_r_send_abort_pkt_timer_ignored		0x6040082A


/*
 *@Address: 0xBE29082C[31:0]
 *@Range: 0~4294967295
 *@Default: 2458
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_082C_DW_082C		0x6800082C

/*
 *@Address: 0xBE29082C[21:0]
 *@Range: 0~4194303
 *@Default: 2458
 *@Access: r/w
 *@Description:
 *	Base time counter.
 *	(1/24.576)*2458*1/1000=0.1ms
*/
#define HDMIRX_CBUS_r_base_timer_reg		0x6580082C


/*
 *@Address: 0xBE290830[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0830_DW_0830		0x68000830

/*
 *@Address: 0xBE290830[10:0]
 *@Range: 0~2047
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	MSC requester engine: pkt_sender_timeout = Base time * 1000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_msc_s_pkt_sender_timeout_reg		0x62C00830


/*
 *@Address: 0xBE290834[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0834_DW_0834		0x68000834

/*
 *@Address: 0xBE290834[10:0]
 *@Range: 0~2047
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	MSC requester engine:
 *	pkt_receiver_timeout = Base time * 1000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_msc_s_pkt_receiver_timeout_reg		0x62C00834


/*
 *@Address: 0xBE290838[31:0]
 *@Range: 0~4294967295
 *@Default: 3200
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0838_DW_0838		0x68000838

/*
 *@Address: 0xBE290838[11:0]
 *@Range: 0~4095
 *@Default: 3200
 *@Access: r/w
 *@Description:
 *	MSC requester engine:
 *	command sender timeout = Base time * 3200.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_msc_s_cmd_sender_timeout_reg		0x63000838


/*
 *@Address: 0xBE29083C[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_083C_DW_083C		0x6800083C

/*
 *@Address: 0xBE29083C[10:0]
 *@Range: 0~2047
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	MSC responder engine:
 *	pkt_sender_timeout = Base time * 1000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_msc_r_pkt_sender_timeout_reg		0x62C0083C


/*
 *@Address: 0xBE290840[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0840_DW_0840		0x68000840

/*
 *@Address: 0xBE290840[10:0]
 *@Range: 0~2047
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	MSC responder engine:
 *	pkt_receiver_timeout = Base time * 1000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_msc_r_pkt_receiver_timeout_reg		0x62C00840


/*
 *@Address: 0xBE290844[31:0]
 *@Range: 0~4294967295
 *@Default: 3200
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0844_DW_0844		0x68000844

/*
 *@Address: 0xBE290844[11:0]
 *@Range: 0~4095
 *@Default: 3200
 *@Access: r/w
 *@Description:
 *	MSC responder engine:
 *	Command receiver timeout = Base time * 3200.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_msc_r_cmd_receiver_timeout_reg		0x63000844


/*
 *@Address: 0xBE290848[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0848_DW_0848		0x68000848

/*
 *@Address: 0xBE290848[10:0]
 *@Range: 0~2047
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	DDC pkt_sender_timeout = Base time * 1000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_ddc_pkt_sender_timeout_reg		0x62C00848


/*
 *@Address: 0xBE29084C[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_084C_DW_084C		0x6800084C

/*
 *@Address: 0xBE29084C[10:0]
 *@Range: 0~2047
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	DDC pkt_receiver_timeout = Base time * 1000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_ddc_pkt_receiver_timeout_reg		0x62C0084C


/*
 *@Address: 0xBE290850[31:0]
 *@Range: 0~4294967295
 *@Default: 10000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0850_DW_0850		0x68000850

/*
 *@Address: 0xBE290850[13:0]
 *@Range: 0~16383
 *@Default: 10000
 *@Access: r/w
 *@Description:
 *	Wait time for RAPK = Base time * 10000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_rap_wait_timeout_reg		0x63800850


/*
 *@Address: 0xBE290854[31:0]
 *@Range: 0~4294967295
 *@Default: 10000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0854_DW_0854		0x68000854

/*
 *@Address: 0xBE290854[13:0]
 *@Range: 0~16383
 *@Default: 10000
 *@Access: r/w
 *@Description:
 *	Wait time for RCPK or RCPE = Base time * 10000.
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_rcp_wait_timeout_reg		0x63800854


/*
 *@Address: 0xBE290858[31:0]
 *@Range: 0~4294967295
 *@Default: 10000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0858_DW_0858		0x68000858

/*
 *@Address: 0xBE290858[13:0]
 *@Range: 0~16383
 *@Default: 10000
 *@Access: r/w
 *@Description:
 *	Wait time for UCPK or UCPE = Base time * 10000.
 *	Refer to MHL spec. 13.10.3, 7.8.2 and 7.8.3
*/
#define HDMIRX_CBUS_r_ucp_wait_timeout_reg		0x63800858


/*
 *@Address: 0xBE29085C[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_085C_DW_085C		0x6800085C

/*
 *@Address: 0xBE29085C[10:0]
 *@Range: 0~2047
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	Delay from CLR_HPD to SET_HPD = Base time * 1000
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_hpd_width_timeout_reg		0x62C0085C


/*
 *@Address: 0xBE290AA0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0AA0_DW_0AA0		0x68000AA0

/*
 *@Address: 0xBE290AA0[11:0]
 *@Range: 0~4095
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_debug_sel		0x63000AA0


/*
 *@Address: 0xBE290AA8[31:0]
 *@Range: 0~4294967295
 *@Default: 1
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0AA8_DW_0AA8		0x68000AA8

/*
 *@Address: 0xBE290AA8[0]
 *@Range: 0~1
 *@Default: 1
 *@Access: r/w
 *@Description:
 *	1:Cbus translation layer reset
*/
#define HDMIRX_CBUS_r_reset_reg		0x60400AA8


/*
 *@Address: 0xBE290AB0[31:0]
 *@Range: 0~4294967295
 *@Default: 1000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0AB0_DW_0AB0		0x68000AB0

/*
 *@Address: 0xBE290AB0[15:0]
 *@Range: 0~65535
 *@Default: 1000
 *@Access: r/w
 *@Description:
 *	Delay from timeout of MSC command or package. Stop sending msc command and wait time for MSC channel that is free.
*/
#define HDMIRX_CBUS_r_block_msc_scmd_reg		0x64000AB0


/*
 *@Address: 0xBE290AB4[31:0]
 *@Range: 0~4294967295
 *@Default: 20000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0AB4_DW_0AB4		0x68000AB4

/*
 *@Address: 0xBE290AB4[15:0]
 *@Range: 0~65535
 *@Default: 20000
 *@Access: r/w
 *@Description:
 *	Delay from ABORT to next command =  Base time * 20000
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_r_abort_next_reg		0x64000AB4


/*
 *@Address: 0xBE290AB8[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0AB8_DW_0AB8		0x68000AB8

/*
 *@Address: 0xBE290AB8[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: retry rap command when nack-event occurs.
*/
#define HDMIRX_CBUS_r_rap_auto_nack_retry		0x60400AB8

/*
 *@Address: 0xBE290AB8[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: retry rcp command when nack-event occurs.
*/
#define HDMIRX_CBUS_r_rcp_auto_nack_retry		0x60400AB9

/*
 *@Address: 0xBE290AB8[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: retry ucp command when nack-event occurs.
*/
#define HDMIRX_CBUS_r_ucp_auto_nack_retry		0x60400ABA

/*
 *@Address: 0xBE290AB8[24]
 *@Range: 0~1
 *@Default: 0

 *@Access: r/w
 *@Description:
 *	0ABB[0]=0 : 
 *	MSC error of source command
 *	0ABB[0]=1 : 
 *	MSC error of sink command
 *	Refer to 0821[7:0]
*/
#define HDMIRX_CBUS_r_cmd_msc_errorcode_update_en		0x60400ABB


/*
 *@Address: 0xBE290ABC[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0ABC_DW_0ABC		0x68000ABC

/*
 *@Address: 0xBE290ABC[20:0]
 *@Range: 0~2097151
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: unsupported MSC receiver command.
 *	[0]:WRITE_CMD
 *	[1]:READ_DEVCAP
 *	[2]:GET_STATE
 *	[3]: GET_VENDOR_ID
 *	[4]: SET_HPD (useless)
 *	[5]: CLR_HPD (useless)
 *	[6]: MSC_MSG
 *	[7]: WRITE_BURST
 *	[8]: GET_SRC1_ERRORCODE
 *	[9]: GET_DDC_ERRORCODE
 *	[10]: GET_MSC_ERRORCODE
 *	[11]: GET_SRC3_ERRORCODE
 *	[12]: MSGE
 *	[13]: RAP
 *	[14]: RAPK
 *	[15]: RCPE
 *	[16]: RCP
 *	[17]: RCPK
 *	[18]: UCP
 *	[19]: UCPK
 *	[20]: UCPE
*/
#define HDMIRX_CBUS_r_msc_receive_cmd_disable		0x65400ABC


/*
 *@Address: 0xBE290AC0[31:0]
 *@Range: 0~4294967295
 *@Default: 10000
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0AC0_DW_0AC0		0x68000AC0

/*
 *@Address: 0xBE290AC0[15:0]
 *@Range: 0~65535
 *@Default: 10000
 *@Access: 
 *@Description:
 *	Delay from NACK to MSC_MSG to sending next MSC_MSG command =  Base time * 10000
 *	Refer to MHL spec. 13.10.3
*/
#define HDMIRX_CBUS_R_msc_nack_retry_next_reg		0x64000AC0


/*
 *@Address: 0xBE290EE0[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0EE0_DW_0EE0		0x68000EE0

/*
 *@Address: 0xBE290EE0[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r
 *@Description:
 *	Interrupt status
 *	[31]:device_status3_intr, check 0033
 *	[30]:device_status2_intr,check 0032
 *	[29]:OTHR_cmd_intr, Check 0702[0]
 *	[28]:msge_act_intr,
 *	[27]:EDID_rd_intr, Check 0600
 *	[26]:ucp_act_intr, Check 0F1A
 *	[25]:ucp_cmd_intr,  Check 0501
 *	[24]:rcp_act_intr, Check 0F18
 *	[23]:rcp_cmd_intr, Check 0401
 *	[22]:rap_act_intr,  Check 0308
 *	[21]:rap_act_ack_intr, Check 0305
 *	[20]:rap_cmd_intr, Check 0301
 *	[19]:get_src3_err_intr, Check 0211
 *	[18]:get_src1_err_intr, Check 0201
 *	[17]:get_msc_err_intr, Check 01F1
 *	[16]:get_ddc_err_intr, Check 01E1
 *	[15]:get_ven_id_intr, Check 01D1
 *	[14]:get_state_intr, Check 01C1
 *	[13]:clr_hpd_intr,  Check 01B1
 *	[12]:set_hpd_intr, Check 01A1
 *	[11]:reserved,
 *	[10]:wrt_burst_intr, Check 0141
 *	[9]:link_mode_intr, Check 0031
 *	[8]:connected_rdy_intr, Check 0030
 *	[7]:wrt_stat_intr, Check 0111[3:0]
 *	[6]:edid_chg_intr,
 *	[5]:req_3d_intr, Check 0020
 *	[4]:grt_wrt_intr, Check 0020
 *	[3]:req_wrt_intr, Check 0020
 *	[2]:dscr_chg_intr, Check 0020
 *	[1]:dcap_chg_intr, Check 0020
 *	[0]:red_devc_intr, Check 0103[3:0]
*/
#define HDMIRX_CBUS_r_intr_status1		0x68000EE0


/*
 *@Address: 0xBE290EE8[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0EE8_DW_0EE8		0x68000EE8

/*
 *@Address: 0xBE290EE8[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r
 *@Description:
 *	Interrupt status
 *	[31:16]:reserved, 
 *	[15]:device_int37_intr,
 *	[14]:device_int36_intr,
 *	[13]:device_int35_intr,
 *	[12]:device_int34_intr,
 *	[11]:device_int33_intr,
 *	[10]:device_int32_intr,
 *	[9]:device_int31_intr,
 *	[8]:device_int30_intr,
 *	[7]:device_int27_intr,
 *	[6]:device_int26_intr,
 *	[5]:device_int25_intr,
 *	[4]:device_int24_intr,
 *	[3]:device_int23_intr,
 *	[2]:device_int22_intr,
 *	[1]:device_int21_intr,
 *	[0]:device_int20_intr,
*/
#define HDMIRX_CBUS_r_intr_status2		0x68000EE8


/*
 *@Address: 0xBE290F00[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F00_DW_0F00		0x68000F00

/*
 *@Address: 0xBE290F00[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	READ_DEVCAP command:  
 *	clear interrupt . Check 0103[3:0]
*/
#define HDMIRX_CBUS_r_red_devc_intr		0x60400F00

/*
 *@Address: 0xBE290F00[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	DCAP_CHG(Device Capability Register value changed) : clear interrupt
*/
#define HDMIRX_CBUS_r_dcap_chg_intr		0x60400F01

/*
 *@Address: 0xBE290F00[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	DSCR_CHG(Device Scratchpad Register value changed) : clear interrupt
*/
#define HDMIRX_CBUS_r_dscr_chg_intr		0x60400F02

/*
 *@Address: 0xBE290F00[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	REQ_WRT(Request-to-Write) : clear interrupt
*/
#define HDMIRX_CBUS_r_req_wrt_intr		0x60400F03


/*
 *@Address: 0xBE290F04[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F04_DW_0F04		0x68000F04

/*
 *@Address: 0xBE290F04[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GRT_WRT(Grant-to-Write) : clear interrupt
*/
#define HDMIRX_CBUS_r_grt_wrt_intr		0x60400F04

/*
 *@Address: 0xBE290F04[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	3D_REG(Request for 3D information): clear interrupt
*/
#define HDMIRX_CBUS_r_req_3d_intr		0x60400F05

/*
 *@Address: 0xBE290F04[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	It indicates that opposite device¡¦s EDID content changes : clear interrupt (useless on sink device.)
*/
#define HDMIRX_CBUS_r_edid_chg_intr		0x60400F06

/*
 *@Address: 0xBE290F04[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_STATE command: clear interrupt. Check 0111[3:0]
*/
#define HDMIRX_CBUS_r_wrt_stat_intr		0x60400F07


/*
 *@Address: 0xBE290F08[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F08_DW_0F08		0x68000F08

/*
 *@Address: 0xBE290F08[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	DCAP_RDY: clear interrupt. Check 0030[0]
*/
#define HDMIRX_CBUS_r_connected_rdy_intr		0x60400F08

/*
 *@Address: 0xBE290F08[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	LINK_MODE : clear interrupt.
 *	Check 0031
*/
#define HDMIRX_CBUS_r_link_mode_intr		0x60400F09

/*
 *@Address: 0xBE290F08[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	WRITE_ BURST command:  clear interrupt. Check 0141.
*/
#define HDMIRX_CBUS_r_wrt_burst_intr		0x60400F0A


/*
 *@Address: 0xBE290F0C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F0C_DW_0F0C		0x68000F0C

/*
 *@Address: 0xBE290F0C[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	SET_HPD command: clear interrupt. Check 01A1.
*/
#define HDMIRX_CBUS_r_set_hpd_intr		0x60400F0C

/*
 *@Address: 0xBE290F0C[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	CLR_HPD command: clear interrupt. Check 01B1.
*/
#define HDMIRX_CBUS_r_clr_hpd_intr		0x60400F0D

/*
 *@Address: 0xBE290F0C[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_STATE command:  
 *	clear interrupt. Check 01C1.
*/
#define HDMIRX_CBUS_r_get_state_intr		0x60400F0E

/*
 *@Address: 0xBE290F0C[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_VENDOR_ID command:  
 *	clear interrupt. Check 01D1.
*/
#define HDMIRX_CBUS_r_get_ven_id_intr		0x60400F0F


/*
 *@Address: 0xBE290F10[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F10_DW_0F10		0x68000F10

/*
 *@Address: 0xBE290F10[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_DDC_ERRORCODE command:  
 *	clear interrupt. Check 01E1.
*/
#define HDMIRX_CBUS_r_get_ddc_err_intr		0x60400F10

/*
 *@Address: 0xBE290F10[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_ MSC _ERRORCODE command:  
 *	clear interrupt. Check 01F1.
*/
#define HDMIRX_CBUS_r_get_msc_err_intr		0x60400F11

/*
 *@Address: 0xBE290F10[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_ SRC1_ERRORCODE command:  
 *	clear interrupt. Check 0201.
*/
#define HDMIRX_CBUS_r_get_src1_err_intr		0x60400F12

/*
 *@Address: 0xBE290F10[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	GET_ SRC3_ERRORCODE command:  
 *	clear interrupt. Check 0211.
*/
#define HDMIRX_CBUS_r_get_src3_err_intr		0x60400F13


/*
 *@Address: 0xBE290F14[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F14_DW_0F14		0x68000F14

/*
 *@Address: 0xBE290F14[0]
 *@Range: 0~1
 *@Default: 
 *@Access: 
 *@Description:
 *	RAP command:  
 *	clear interrupt. Check 0301 & 0303
*/
#define HDMIRX_CBUS_r_rap_cmd_intr		0x60400F14

/*
 *@Address: 0xBE290F14[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	RAPK command:  
 *	clear interrupt. Check 0305.
*/
#define HDMIRX_CBUS_r_rap_act_ack_intr		0x60400F15

/*
 *@Address: 0xBE290F14[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	RAP code of source. Clear Interrupt of RAP code of source. Check 0308
*/
#define HDMIRX_CBUS_r_rap_act_intr		0x60400F16

/*
 *@Address: 0xBE290F14[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	RCP command: 
 *	clear interrupt. Check 0401,0403,0404.
*/
#define HDMIRX_CBUS_r_rcp_cmd_intr		0x60400F17


/*
 *@Address: 0xBE290F18[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F18_DW_0F18		0x68000F18

/*
 *@Address: 0xBE290F18[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	It indicates that there are RCP data in fifo.
*/
#define HDMIRX_CBUS_r_rcp_act_intr		0x60400F18

/*
 *@Address: 0xBE290F18[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	UCP command: 
 *	clear interrupt. Check 0501,0503,0504.
*/
#define HDMIRX_CBUS_r_ucp_cmd_intr		0x60400F19

/*
 *@Address: 0xBE290F18[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Clear interrupt. It indicates that there are UCP data in fifo.
*/
#define HDMIRX_CBUS_r_ucp_act_intr		0x60400F1A

/*
 *@Address: 0xBE290F18[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Clear Interrupt of EDID read.
*/
#define HDMIRX_CBUS_r_EDID_rd_intr		0x60400F1B


/*
 *@Address: 0xBE290F1C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F1C_DW_0F1C		0x68000F1C

/*
 *@Address: 0xBE290F1C[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	clear interrupt for read or write. Check 0702[0].
*/
#define HDMIRX_CBUS_r_OTHR_cmd_intr		0x60400F1C

/*
 *@Address: 0xBE290F1C[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Clear interrupt of MSC_MSG error sub-command from source. It indicates the error sub-command from sink occurs .
*/
#define HDMIRX_CBUS_r_msge_act_intr		0x60400F1D

/*
 *@Address: 0xBE290F1C[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Device status registers 0032: clear interrupt
*/
#define HDMIRX_CBUS_r_device_status2_intr		0x60400F1E

/*
 *@Address: 0xBE290F1C[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Device status registers 0033: clear
 *	interrupt
*/
#define HDMIRX_CBUS_r_device_status3_intr		0x60400F1F


/*
 *@Address: 0xBE290F20[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F20_DW_0F20		0x68000F20

/*
 *@Address: 0xBE290F20[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Device interrupt Register 0x22: clear interrupt
*/
#define HDMIRX_CBUS_r_device_int20_intr		0x60400F20

/*
 *@Address: 0xBE290F20[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int21_intr		0x60400F21

/*
 *@Address: 0xBE290F20[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int22_intr		0x60400F22

/*
 *@Address: 0xBE290F20[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int23_intr		0x60400F23


/*
 *@Address: 0xBE290F24[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F24_DW_0F24		0x68000F24

/*
 *@Address: 0xBE290F24[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int24_intr		0x60400F24

/*
 *@Address: 0xBE290F24[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int25_intr		0x60400F25

/*
 *@Address: 0xBE290F24[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int26_intr		0x60400F26

/*
 *@Address: 0xBE290F24[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int27_intr		0x60400F27


/*
 *@Address: 0xBE290F28[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F28_DW_0F28		0x68000F28

/*
 *@Address: 0xBE290F28[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Device interrupt Register 0x23: clear interrupt
*/
#define HDMIRX_CBUS_r_device_int30_intr		0x60400F28

/*
 *@Address: 0xBE290F28[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int31_intr		0x60400F29

/*
 *@Address: 0xBE290F28[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int32_intr		0x60400F2A

/*
 *@Address: 0xBE290F28[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int33_intr		0x60400F2B


/*
 *@Address: 0xBE290F2C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0F2C_DW_0F2C		0x68000F2C

/*
 *@Address: 0xBE290F2C[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int34_intr		0x60400F2C

/*
 *@Address: 0xBE290F2C[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int35_intr		0x60400F2D

/*
 *@Address: 0xBE290F2C[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int36_intr		0x60400F2E

/*
 *@Address: 0xBE290F2C[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description: None
*/
#define HDMIRX_CBUS_r_device_int37_intr		0x60400F2F


/*
 *@Address: 0xBE290FF0[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0FF0_DW_0FF0		0x68000FF0

/*
 *@Address: 0xBE290FF0[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Interrupt enable.
 *	Refer to 0EE0
*/
#define HDMIRX_CBUS_r_intr_en1		0x68000FF0


/*
 *@Address: 0xBE290FF8[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_TRANS_0FF8_DW_0FF8		0x68000FF8

/*
 *@Address: 0xBE290FF8[31:0]
 *@Range: 0~4294967295
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Interrupt enable.
 *	Refer to 0EE8
*/
#define HDMIRX_CBUS_r_intr_en2		0x68000FF8


/*
 *@Address: 0xBE298000[31:0]
 *@Range: 0~4294967295
 *@Default: 0x20
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8000_DW_8000		0x68008000

/*
 *@Address: 0xBE298000[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:Cbus link layer reset
*/
#define HDMIRX_CBUS_cfg_cbus_reset		0x60408000

/*
 *@Address: 0xBE298000[1]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:debounce reset
*/
#define HDMIRX_CBUS_cfg_debounce_reset		0x60418000

/*
 *@Address: 0xBE298000[2]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:buffers reset
*/
#define HDMIRX_CBUS_cfg_buf_reset		0x60428000

/*
 *@Address: 0xBE298000[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	0:sink type;1:source (for simulation)
*/
#define HDMIRX_CBUS_cfg_cbus_typ		0x60408001

/*
 *@Address: 0xBE298000[9]
 *@Range: 0~1
 *@Default: 1
 *@Access: r/w
 *@Description:
 *	1:bypass buffer (bypass sw mode)
*/
#define HDMIRX_CBUS_cfg_bypass_cmd_data_buf		0x60418001

/*
 *@Address: 0xBE298000[10]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:start CBUS float (sink1->sink5)
*/
#define HDMIRX_CBUS_cfg_cbus_reinit		0x60428001

/*
 *@Address: 0xBE298000[11]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	When sink detects invalid discovery pulses,
 *	0:re-detect the discovery with a new wake up pulse sequence.
 *	1:re-detect without a new wake up pulse sequence
*/
#define HDMIRX_CBUS_cfg_discv_opt		0x60438001

/*
 *@Address: 0xBE298000[12]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Cbus path enable (sw mode)
 *	1: path enable
*/
#define HDMIRX_CBUS_cfg_cbus_pathen		0x60448001

/*
 *@Address: 0xBE298000[18:16]
 *@Range: 0~7
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Debug port selection
*/
#define HDMIRX_CBUS_cfg_debug_port_sel		0x60C08002


/*
 *@Address: 0xBE298004[31:0]
 *@Range: 0~4294967295
 *@Default: 440000
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8004_DW_8004		0x68008004

/*
 *@Address: 0xBE298004[21:0]
 *@Range: 0~4194303
 *@Default: 440000
 *@Access: r/w
 *@Description:
 *	Tsrc_wake_pulse_width_1 min(18ms/40.69ns)
*/
#define HDMIRX_CBUS_cfg_wake_pulse_w1_min		0x65808004


/*
 *@Address: 0xBE298008[31:0]
 *@Range: 0~4294967295
 *@Default: 550000
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8008_DW_8008		0x68008008

/*
 *@Address: 0xBE298008[21:0]
 *@Range: 0~4194303
 *@Default: 550000
 *@Access: r/w
 *@Description:
 *	Tsrc_wake_pulse_width_1 max(22ms/40.69ns)
*/
#define HDMIRX_CBUS_cfg_wake_pulse_w1_max		0x65808008


/*
 *@Address: 0xBE29800C[31:0]
 *@Range: 0~4294967295
 *@Default: 1320000
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_800C_DW_800C		0x6800800C

/*
 *@Address: 0xBE29800C[21:0]
 *@Range: 0~4194303
 *@Default: 1320000
 *@Access: r/w
 *@Description:
 *	Tsrc_wake_pulse_width_2 min(54ms/40.69ns)
*/
#define HDMIRX_CBUS_cfg_wake_pulse_w2_min		0x6580800C


/*
 *@Address: 0xBE298010[31:0]
 *@Range: 0~4294967295
 *@Default: 1650000
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8010_DW_8010		0x68008010

/*
 *@Address: 0xBE298010[21:0]
 *@Range: 0~4194303
 *@Default: 1650000
 *@Access: r/w
 *@Description:
 *	Tsrc_wake_pulse_width_2 max(66ms/40.69ns)
*/
#define HDMIRX_CBUS_cfg_wake_pulse_w2_max		0x65808010


/*
 *@Address: 0xBE298014[31:0]
 *@Range: 0~4294967295
 *@Default: 1720
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8014_DW_8014		0x68008014

/*
 *@Address: 0xBE298014[11:0]
 *@Range: 0~4095
 *@Default: 1720
 *@Access: r/w
 *@Description:
 *	Tsink_pulse_width min(70us/40.69ns)
*/
#define HDMIRX_CBUS_cfg_discv_width_min		0x63008014


/*
 *@Address: 0xBE298018[31:0]
 *@Range: 0~4294967295
 *@Default: 3250
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8018_DW_8018		0x68008018

/*
 *@Address: 0xBE298018[11:0]
 *@Range: 0~4095
 *@Default: 3250
 *@Access: r/w
 *@Description:
 *	Tsink_pulse_width max
 *	(130us/40.69)
*/
#define HDMIRX_CBUS_cfg_discv_width_max		0x63008018


/*
 *@Address: 0xBE29801C[31:0]
 *@Range: 0~4294967295
 *@Default: 1250000
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_801C_DW_801C		0x6800801C

/*
 *@Address: 0xBE29801C[21:0]
 *@Range: 0~4194303
 *@Default: 1250000
 *@Access: r/w
 *@Description:
 *	Tsink_cbus_float (50ms/40.69ns)
*/
#define HDMIRX_CBUS_cfg_cbus_float_min		0x6580801C


/*
 *@Address: 0xBE298020[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8020_DW_8020		0x68008020

/*
 *@Address: 0xBE298020[12:0]
 *@Range: 0~8191
 *@Default: 5120
 *@Access: r/w
 *@Description:
 *	Tsink_cbus_disconn (210us/40.69)
*/
#define HDMIRX_CBUS_cfg_cbus_disconn_max		0x63408020

/*
 *@Address: 0xBE298020[20:16]
 *@Range: 0~31
 *@Default: 5
 *@Access: r/w
 *@Description:
 *	Nsink_pulse_count
*/
#define HDMIRX_CBUS_cfg_discv_cyc		0x61408022


/*
 *@Address: 0xBE298024[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8024_DW_8024		0x68008024

/*
 *@Address: 0xBE298024[5:0]
 *@Range: 0~63
 *@Default: 24
 *@Access: r/w
 *@Description:
 *	One bit time (1000ns/40.69ns)
*/
#define HDMIRX_CBUS_cfg_txclk_div		0x61808024

/*
 *@Address: 0xBE298024[13:8]
 *@Range: 0~63
 *@Default: 19
 *@Access: r/w
 *@Description:
 *	Bit time min (800ns/40.69ns)
*/
#define HDMIRX_CBUS_cfg_bittime_min		0x61808025

/*
 *@Address: 0xBE298024[21:16]
 *@Range: 0~63
 *@Default: 30
 *@Access: r/w
 *@Description:
 *	Bit time max
 *	(1200ns/40.69ns)
*/
#define HDMIRX_CBUS_cfg_bittime_max		0x61808026

/*
 *@Address: 0xBE298024[31:24]
 *@Range: 0~255
 *@Default: 90
 *@Access: r/w
 *@Description:
 *	Duty cycle of SYNC bit (min)
 *	1.4/2*128
*/
#define HDMIRX_CBUS_cfg_syncduty_min		0x62008027


/*
 *@Address: 0xBE298028[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8028_DW_8028		0x68008028

/*
 *@Address: 0xBE298028[7:0]
 *@Range: 0~255
 *@Default: 102
 *@Access: r/w
 *@Description:
 *	Duty cycle of SYNC bit (max)
 *	1.6/2*128
*/
#define HDMIRX_CBUS_cfg_syncduty_max		0x62008028

/*
 *@Address: 0xBE298028[21:16]
 *@Range: 0~63
 *@Default: 11
 *@Access: r/w
 *@Description:
 *	Ack bit drive low time: start (500ns/40.69ns)-1
*/
#define HDMIRX_CBUS_cfg_ack0_start		0x6180802A

/*
 *@Address: 0xBE298028[29:24]
 *@Range: 0~63
 *@Default: 24
 *@Access: r/w
 *@Description:
 *	Ack bit drive low time: end (1000ns/40.69ns)
*/
#define HDMIRX_CBUS_cfg_ack0_end		0x6180802B


/*
 *@Address: 0xBE29802C[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_802C_DW_802C		0x6800802C

/*
 *@Address: 0xBE29802C[5:0]
 *@Range: 0~63
 *@Default: 5
 *@Access: r/w
 *@Description:
 *	Tsink_arbitrate { cfg_cbus_arb ,11¡¦h7ff}
*/
#define HDMIRX_CBUS_cfg_cbus_arb		0x6180802C

/*
 *@Address: 0xBE29802C[13:8]
 *@Range: 0~63
 *@Default: 63
 *@Access: r/w
 *@Description:
 *	Threshold value that Sink receives error bit time data
*/
#define HDMIRX_CBUS_cfg_cbus_rxerr		0x6180802D


/*
 *@Address: 0xBE298030[31:0]
 *@Range: 0~4294967295
 *@Default: 1
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8030_DW_8030		0x68008030

/*
 *@Address: 0xBE298030[0]
 *@Range: 0~1
 *@Default: 1
 *@Access: r/w
 *@Description:
 *	1:wake up interrupt enable
*/
#define HDMIRX_CBUS_cfg_wake_int_en		0x60408030

/*
 *@Address: 0xBE298030[1]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:discovery interrupt enable
*/
#define HDMIRX_CBUS_cfg_discv_int_en		0x60418030

/*
 *@Address: 0xBE298030[2]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:connected interrupt enable
*/
#define HDMIRX_CBUS_cfg_connt_int_en		0x60428030

/*
 *@Address: 0xBE298030[3]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: attach interrupt enable
*/
#define HDMIRX_CBUS_cfg_attach_int_en		0x60438030

/*
 *@Address: 0xBE298030[4]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: detach interrupt enable
*/
#define HDMIRX_CBUS_cfg_detach_int_en		0x60448030

/*
 *@Address: 0xBE298030[5]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:tx fifo empty interrupt enable
*/
#define HDMIRX_CBUS_cfg_txff_empty_int_en		0x60458030

/*
 *@Address: 0xBE298030[6]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:tx fifo prefull interrupt enable
*/
#define HDMIRX_CBUS_cfg_txff_prefull_int_en		0x60468030

/*
 *@Address: 0xBE298030[7]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:rx fifo has data interrupt enable
*/
#define HDMIRX_CBUS_cfg_rxff_hv_data_int_en		0x60478030

/*
 *@Address: 0xBE298030[8]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse wake up int. polarity
*/
#define HDMIRX_CBUS_cfg_wake_int_pol		0x60408031

/*
 *@Address: 0xBE298030[9]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse discovery int. polarity
*/
#define HDMIRX_CBUS_cfg_discv_int__pol		0x60418031

/*
 *@Address: 0xBE298030[10]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse connected int. polarity
*/
#define HDMIRX_CBUS_cfg_connt_int__pol		0x60428031

/*
 *@Address: 0xBE298030[11]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse attach int. polarity
*/
#define HDMIRX_CBUS_cfg_attach_int__pol		0x60438031

/*
 *@Address: 0xBE298030[12]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse detach int. polarity
*/
#define HDMIRX_CBUS_cfg_detach_int__pol		0x60448031

/*
 *@Address: 0xBE298030[13]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse txff empty int. polarity
*/
#define HDMIRX_CBUS_cfg_txff_empty_int__pol		0x60458031

/*
 *@Address: 0xBE298030[14]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse txff prefull int. polarity
*/
#define HDMIRX_CBUS_cfg_txff_prefull_int__pol		0x60468031

/*
 *@Address: 0xBE298030[15]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse rxff has data int. polarity
*/
#define HDMIRX_CBUS_cfg_rxff_hv_data_int__pol		0x60478031

/*
 *@Address: 0xBE298030[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:txerr interrupt enable
*/
#define HDMIRX_CBUS_cfg_cbus_txerr_int_en		0x60408032

/*
 *@Address: 0xBE298030[17]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse txerr int. polarity
*/
#define HDMIRX_CBUS_cfg_cbus_txerr_int_pol		0x60418032

/*
 *@Address: 0xBE298030[18]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	txerr int. it means that re-try number is greater than Nretry.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_txerr_int_p		0x60428032

/*
 *@Address: 0xBE298030[20]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *  1: src_disconnected_int enable
*/
#define HDMIRX_CBUS_cfg_src_disconnected_int_en     0x60448032

/*
 *@Address: 0xBE298030[21]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *  1: inverse src_disconnected_int  polarity
*/
#define HDMIRX_CBUS_cfg_src_disconnected_int_pol        0x60458032

/*
 *@Address: 0xBE298030[22]
 *@Range: 0~1
 *@Default: 0
 *@Access: r
 *@Description:
 *  1: src disconnect int. It means the source disconnected cbus.(write 1 clear)
*/
#define HDMIRX_CBUS_cfg_src_disconnected_int_p      0x60468032

/*
 *@Address: 0xBE298030[24]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *  1: cbus translation rst int enable.
*/
#define HDMIRX_CBUS_cfg_cbus_translation_rst_int_en     0x60408033

/*
 *@Address: 0xBE298030[25]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *  1: inverse cbus_translation_rst_int polarity.
*/
#define HDMIRX_CBUS_cfg_cbus_translation_rst_int_pol        0x60418033

/*
 *@Address: 0xBE298030[26]
 *@Range: 0~1
 *@Default: 0
 *@Access: r
 *@Description:
 *  1: It mean you shall reset cbus translation layer to clean the useless cmds.(write 1 clear)
*/
#define HDMIRX_CBUS_cfg_cbus_translation_rst_int_p      0x60428033




/*
 *@Address: 0xBE298034[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8034_DW_8034		0x68008034

/*
 *@Address: 0xBE298034[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	wake up int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_wake_int_p		0x60408034

/*
 *@Address: 0xBE298034[1]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	discovery int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_discv_int__p		0x60418034

/*
 *@Address: 0xBE298034[2]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	connected int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_connt_int__p		0x60428034

/*
 *@Address: 0xBE298034[3]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	attach int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_attach_int__p		0x60438034

/*
 *@Address: 0xBE298034[4]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	detach int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_detach_int__p		0x60448034

/*
 *@Address: 0xBE298034[5]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	txff empty int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_txff_empty_int__p		0x60458034

/*
 *@Address: 0xBE298034[6]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	txff prefull int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_txff_prefull_int__p		0x60468034

/*
 *@Address: 0xBE298034[7]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	rxff has data int.
 *	Write 1 to clear.
*/
#define HDMIRX_CBUS_rxff_hv_data_int__p		0x60478034

/*
 *@Address: 0xBE298034[10:8]
 *@Range: 0~7
 *@Default: 3
 *@Access: r/w
 *@Description:
 *	Tx fifo pre-full threshold
*/
#define HDMIRX_CBUS_cfg_fifo_prefull_thd		0x60C08035


/*
 *@Address: 0xBE298038[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8038_DW_8038		0x68008038

/*
 *@Address: 0xBE298038[11:0]
 *@Range: 0~4095
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Cpu sends data/cmds
*/
#define HDMIRX_CBUS_link_layer_cmd		0x63008038


/*
 *@Address: 0xBE29803C[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_803C_DW_803C		0x6800803C

/*
 *@Address: 0xBE29803C[10:0]
 *@Range: 0~2047
 *@Default: 0
 *@Access: r
 *@Description:
 *	Cpu receives data
*/
#define HDMIRX_CBUS_link_layer_data		0x62C0803C


/*
 *@Address: 0xBE298040[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8040_DW_8040		0x68008040

/*
 *@Address: 0xBE298040[13:0]
 *@Range: 0~16383
 *@Default: 0
 *@Access: r
 *@Description:
 *	Cmds/data which are sand from txff out
*/
#define HDMIRX_CBUS_link_layer_cmdfromffo		0x63808040


/*
 *@Address: 0xBE298044[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8044_DW_8044		0x68008044

/*
 *@Address: 0xBE298044[7:0]
 *@Range: 0~255
 *@Default: 50
 *@Access: r/w
 *@Description:
 *	Indicate cd_sense is high or low if its continuous 1/0 value is greater than this value
*/
#define HDMIRX_CBUS_cfg_debounce_sample_number		0x62008044

/*
 *@Address: 0xBE298044[9:8]
 *@Range: 0~3
 *@Default: 1
 *@Access: r/w
 *@Description:
 *	Select sampling clk
 *	00:mhlclk*512
 *	01: mhlclk*1024
 *	10:mhlclk*2048
 *	11: mhlclk*4096
*/
#define HDMIRX_CBUS_cfg_debounce_sel_sample_clk		0x60808045

/*
 *@Address: 0xBE298044[12]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: inverse cd_sense-in polarity
 *	We need cd_sense=1 when cable attachs.
*/
#define HDMIRX_CBUS_cfg_cdsense_in_inverse_polarity		0x60448045


/*
 *@Address: 0xBE298048[31:0]
 *@Range: 0~4294967295
 *@Default: 0x0
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8048_DW_8048		0x68008048

/*
 *@Address: 0xBE298048[0]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:sw controls and decides if the cmds/data send or not when txerr occurs.
*/
#define HDMIRX_CBUS_cfg_cpu_ctrl_cbus_retry_err		0x60408048

/*
 *@Address: 0xBE298048[1]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1:When 8048[0]=1 & 8032[2]=1, clean all values in tx buffer
*/
#define HDMIRX_CBUS_cfg_rst_tx_buff		0x60418048

/*
 *@Address: 0xBE298048[2]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: When 8048[0]=1 & 8032[2]=1, don¡¦t care the txerr and keep on sending next cmd/data
*/
#define HDMIRX_CBUS_Cfg_bypass_retry_err		0x60428048


/*
 *@Address: 0xBE29804C[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_804C_DW_804C		0x6800804C

/*
 *@Address: 0xBE29804C[4:0]
 *@Range: 0~31
 *@Default: 24
 *@Access: r/w
 *@Description:
 *	Nmax
*/
#define HDMIRX_CBUS_cfg_n_max		0x6140804C

/*
 *@Address: 0xBE29804C[13:8]
 *@Range: 0~63
 *@Default: 31
 *@Access: r/w
 *@Description:
 *	Nretry-1
*/
#define HDMIRX_CBUS_cfg_n_retry		0x6180804D

/*
 *@Address: 0xBE29804C[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Treq_cont
*/
#define HDMIRX_CBUS_cfg_req_cont		0x6040804E

/*
 *@Address: 0xBE29804C[22:20]
 *@Range: 0~7
 *@Default: 2
 *@Access: r/w
 *@Description:
 *	Treq_opp+1
*/
#define HDMIRX_CBUS_cfg_req_opp		0x60C4804E

/*
 *@Address: 0xBE29804C[26:24]
 *@Range: 0~7
 *@Default: 3
 *@Access: r/w
 *@Description:
 *	Tresp_hold-2 for ack
 *	(select Tresp_hold=5)
*/
#define HDMIRX_CBUS_cfg_resp_hold_a		0x60C0804F

/*
 *@Address: 0xBE29804C[30:28]
 *@Range: 0~7
 *@Default: 2
 *@Access: r/w
 *@Description:
 *	Tresp_hold-3 for Nack
*/
#define HDMIRX_CBUS_cfg_resp_hold_b		0x60C4804F


/*
 *@Address: 0xBE298050[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8050_DW_8050		0x68008050

/*
 *@Address: 0xBE298050[3:0]
 *@Range: 0~15
 *@Default: 7
 *@Access: r/w
 *@Description:
 *	Treq_hold-1
*/
#define HDMIRX_CBUS_cfg_req_hold		0x61008050

/*
 *@Address: 0xBE298050[7:4]
 *@Range: 0~15
 *@Default: 11
 *@Access: r/w
 *@Description:
 *	Twait_arb-1
*/
#define HDMIRX_CBUS_cfg_wait_arb		0x61048050

/*
 *@Address: 0xBE298050[8]
 *@Range: 0~1
 *@Default: 1
 *@Access: r/w
 *@Description:
 *	1:Increase sampling range to sample ack-bit low
*/
#define HDMIRX_CBUS_cfg_wide_sampling_for_ack		0x60408051

/*
 *@Address: 0xBE298050[16]
 *@Range: 0~1
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	1: having vbus, 0:no vbus
*/
#define HDMIRX_CBUS_cfg_sw_ctrl_vbus		0x60408052

/*
 *@Address: 0xBE298050[25:24]
 *@Range: 0~3
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	00: vbus = cd_sense
 *	01: vbus = cd_sense && timeout (8054[21:0])
 *	10: vbus = cd_sense && timeout && not in standby mode.
 *	11:vbus = cd_sense && cfg_sw_ctrl_vbus
*/
#define HDMIRX_CBUS_cfg_sink_vbus_ctrl		0x60808053


/*
 *@Address: 0xBE298054[31:0]
 *@Range: 0~4294967295
 *@Default: 
 *@Access: 
 *@Description: None
*/
#define CBUS_LINK_8054_DW_8054		0x68008054

/*
 *@Address: 0xBE298054[21:0]
 *@Range: 0~4194303
 *@Default: 0
 *@Access: r/w
 *@Description:
 *	Delay time for turning on vbus when cd_sense=1
 *	(delay= N*40.69ns)
*/
#define HDMIRX_CBUS_cfg_time_sink_vbus_en		0x65808054


#endif