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- #
- # Makefile template
- #
- KERNELDIR ?= ../../kernel/linux/
- ################################################################################
- PWD ?= $(shell pwd)
- ifeq ($(KERNELRELEASE),)
- all:
- $(MAKE) -C $(KERNELDIR) M=$(PWD) modules
- clean:
- $(MAKE) -C $(KERNELDIR) M=$(PWD) clean
- else
- include $(KBUILD_EXTMOD)/../Makefile.toolchain
- include $(KBUILD_EXTMOD)/../Makefile.project
- include $(KBUILD_EXTMOD)/Makefile.in
- obj-m := $(mods)
- # undef xxx-objs if $(xxx-objs) only contain xxx.o (contain only 1 object and the name is matched as target)
- # undef_prefix_match(): undefine $(1) if $(1) and $($(1)) have the same prefix
- # parameter $(1) is like xxx-objs, which is a name of variable, contaion only one string in it.
- undef_prefix_match = $(if $(findstring $(1:-objs=).o,$($(1))),$(1)=)
- # find_only_one_obj(): if the number of string in $(1) is only one, then undefine it.
- # parameter $(1) is like xxx-objs, which is a name of variable.
- find_only_one_obj = $(if $(filter 1,$(words $($(1)))),$(call undef_prefix_match,$(1)))
- # check each module (xxx-objs)
- # note: if the line begins with a TAB character and doesn't appear
- # to be a legal make command (such as a variable assignment)
- # Error `commands commence before first target. Stop.' will happen
- # so do not use TAB instead of space
- $(foreach mod_obj,$(mods:%.o=%-objs),$(eval $(call find_only_one_obj,$(mod_obj))))
- endif
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