drv_spi_flashalloc_external.h 2.5 KB

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  1. #ifndef _DRV_SPI_FLASHALLOC_EXTERNAL_H
  2. #define _DRV_SPI_FLASHALLOC_EXTERNAL_H
  3. #ifndef _CCOPTS_
  4. #include <project.h>
  5. #endif
  6. #include "drv_spi_flash_module_index.h"
  7. /* Nor-Flash base address */
  8. #define SPI_CODEFLASH_BASEADDR 0xBC000000
  9. #define SPI_DATAFLASH_BASEADDR 0xBF000000
  10. #if (CONFIG_CODE_FLASH_SIZE <= 1024)
  11. #define SPI_IS_WITH_NANDFLASH 1
  12. #else
  13. #define SPI_IS_WITH_NANDFLASH 0
  14. #endif
  15. #if 1
  16. #define TAG_LENGTH 12
  17. #define FLASH_HEAD_SIZE sizeof(mtab_head_s)
  18. typedef struct _mtab_head_s
  19. {
  20. char sys_tag[TAG_LENGTH]; /* ascii */
  21. unsigned int size;
  22. #ifdef CONFIG_SUPPORT_FLASH_MODULE_CRC_CHECK
  23. unsigned int data_size;
  24. unsigned int crc;
  25. unsigned int reserve1;
  26. unsigned int reserve2;
  27. #endif
  28. }mtab_head_s;
  29. #define SPI_8051_CODE_ADDR (0x10000)
  30. #define SPI_OPTION_DATA_ADDR (SPI_8051_CODE_ADDR+CONFIG_8051_CODE_SIZE)
  31. #define SPI_OPTION_DATA_SIZE 480
  32. #define SPI_OUIBOOTINFO_ADDR (SPI_OPTION_DATA_ADDR+SPI_OPTION_DATA_SIZE)
  33. #if (defined(CONFIG_SPI_SFS) || defined(SPI_IS_WITH_NANDFLASH))
  34. //reserve 0x01~0x0f
  35. #define SPI_ADCDATA_FLASHID (0x01) //12k
  36. #define SPI_KMFSHARE_FLASHID (0x02) //1k
  37. #define SPI_CIDATA_FLASHADDR (0x03) //need to remove
  38. #define SPI_RRTTABLE_FLASHADDR (0x04) //need to remove
  39. #define SPI_BOOTSHARE_FLASHID (0x05) //customer used
  40. //for nvm data
  41. #define SPI_NVMDATA_FLASHID (0x10)
  42. #endif
  43. #if 0
  44. /* please remove these definitions , 2013.05.13 Gaia */
  45. #if ( SPI_IS_WITH_NANDFLASH )
  46. #define SPI_MENUDEFAULT_FLASHSIZE (11*1024)
  47. #else
  48. #define SPI_MENUDEFAULT_FLASHSIZE (3*1024)
  49. #define SPI_PICTUREDEFAULT_FLASHSIZE (3*1024)
  50. #define SPI_AUDIODEFAULT_FLASHSIZE (2*1024)
  51. #endif
  52. #define SPI_TX_HDCPKEY_SHADOWADDR 0x9A069800
  53. #if ( SPI_IS_WITH_NANDFLASH )
  54. #define SPI_NAND_DPTT_SHADOWADDR 0x9A2F0000
  55. #endif
  56. #define SPI_MAC_SHADOWADDR 0x9A069C00
  57. #define SPI_KMFSHARE_SHADOWADDR 0x9A076000
  58. #define SPI_KERNEL_FLASHADDR (0xbc120000)
  59. #define SPI_KERNELPART1END_FLASHADDR (0xbc000000+(CONFIG_CODE_FLASH_SIZE*1024))
  60. #define SPI_KERNELPART2_FLASHADDR (0x0) /* usbupdate.h */
  61. #define SPI_KERNELPART2END_FLASHADDR (0x0) /* usbupdate.h */
  62. #define SPI_KERNELPART1_FLASHSIZE (5000*1024)//(4244*1024)
  63. #define SPI_KERNELPART2_FLASHSIZE (0)
  64. #define SPI_KERNEL_FLASHSIZE (SPI_KERNELPART1_FLASHSIZE+SPI_KERNELPART2_FLASHSIZE)
  65. // #define SPI_LOGO_SHADOWSIZE (320*1024)
  66. #define SPI_RRTTABLE2_FLASHSIZE (0*1024)
  67. #define SPI_LOGO2_FLASHSIZE (0*1024)
  68. //#define SPI_RRTLOCK_FLASHSIZE (4*1024)
  69. #define SPI_RRTTABLE_FLASHSIZE (288*1024)
  70. #endif
  71. #endif
  72. #endif // _DRV_SPI_FLASHALLOC_H