UTS6710/drivers/module_include/drv_gated_clk.h

#ifndef _DRV_GATED_CLK_H_
#define _DRV_GATED_CLK_H_

#define GATED_STOP_CLK		1
#define GATED_PASS_CLK		0

// HW Gated Clock Module List
enum
{
	GATED_F24MCLK_ATV=0,		// 0xbe000180[0] : Stop CVD2 and TT's 24MHz Clock
	GATED_F24MCLK_DTV,		// 0xbe000180[1] : Stop DeMUX, RAMShare and VOF's 24MHz Clock
	GATED_F24MCLK_YPPADC,	// 0xbe000180[2] : Stop YPPADC's 24MHz Clock
	GATED_F24MCLK_HDMI,		// 0xbe000180[3] : Stop HDMI_Logic's 24MHz Clock
	GATED_F24MCLK_I2CM,		// 0xbe000180[4] : Stop I2C_Master's 24MHz Clock
	GATED_F24MCLK_USB,		// 0xbe000180[5] : Stop USB's 24MHz Clock
	GATED_MCLK_CARDR,			// 0xbe000180[6] : Stop SD-card reader's MCLK	//for different chip need to check
	GATED_MCLK_GMAC,			// 0xbe000180[7] : Stop GMAC's MCLK	//for different chip need to check
	
	GATED_MCLK_ATV,			// 0xbe000180[8] : Stop CVD2's MCLK
	GATED_MCLK_DTV,			// 0xbe000180[9] : Stop DeMUX, RAMShare and VOF's MCLK
	GATED_MCLK_HDMI,			// 0xbe000180[10] : Stop HDMI's MCLK
	GATED_MCLK_USB,			// 0xbe000180[11] : Stop USB's MCLK
	GATED_DMA_CLK,			// 0xbe000180[12] : DMA/CLK
	GATED_MCLK_BLT,			// 0xbe000180[13] : Stop BLT's MCLK (control by BLT driver)
	GATED_MMIOCLK_YPP,		// 0xbe000180[14] : Stop MMIO Clock for YPP and CVD2
	GATED_ICLK_VIP,			// 0xbe000180[15] : Stop VIP's ICLK (only OFF in progressive mode)
	GATED_MMIOCLK_BLT,		// 0xbe000180[16] : Stop BLT's MMIOCLK (control by BLT driver)
	GATED_BLTCLK_BLT,			// 0xbe000180[17] : Stop BLT's BLTCLK (control by BLT driver)
	#if (CONFIG_CHIPID == 0x6710) || (CONFIG_CHIPID == 0x131) || (CONFIG_CHIPID == 0x533) ||(CONFIG_CHIPID == 0x8506)
	GATED_ECLK_AUDIO,			// 0xbe000180[18] : Stop DTV's ECLK (not affect Audio_TX)
	#else
	GATED_ECLK_DTV,				// 0xbe000180[18] : Stop Audio ECLK 	
	#endif 
	GATED_PCRTSTCLK_DEMUX,	// 0xbe000180[19] : Stop DeMUX's PCRTSTCLK
	GATED_F12MCLK_CKDET,		// 0xbe000180[20] : Stop Clock_Detect's F12MCLK
	GATED_I2SMCK_DAMP,		// 0xbe000180[21] : Stop I2SMCK Output for DAMP (by AP)
	GATED_TSCLK_DEMUX,		// 0xbe000180[22] : Stop DeMUX's TS_CLK
	GATED_CVD2_VDCLK,			// 0xbe000180[23] : Stop CVD2's VDCLK
	GATED_36MCLK_SIFAFE,		// 0xbe000180[24] : Stop SIFAFE's 36MCLK
	GATED_36MCLK_SIFDEC,		// 0xbe000180[25] : Stop SIF_Decoder's 36MCLK
	GATED_DVCLK_YPPADC,		// 0xbe000180[26] : Stop ResyncFIFO, VIP's DVCLK
	GATED_USB_CLKDR,			// 0xbe000180[27] : Stop USB11's DRCLK
	GATED_USB_CLK12,			// 0xbe000180[28] : Stop USB11's 12MHz Clock
	GATED_USB_CLK120,			// 0xbe000180[29] : Stop USB20's 120MHz Clock
	GATED_USB_CLK30,			// 0xbe000180[30] : Stop USB20's 30MHz Clock
	GATED_USB_CLK48,			// 0xbe000180[31] : Stop USB_UTMI 48MHz Clock

	GATED_VCLK_DTV,			// 0xbe000184[0] : Stop H264.VCLK Clock
	GATED_NFCLK,				// 0xbe000184[1] : Stop NFC's (NAND-Flash Controller) Clock
	#if (CONFIG_CHIPID == 0x8506)
	GATED_F24MCLK_HUM,          // 0xbe000184[2]
    #else
	GATED_BCRCLK,				// 0xbe000184[2] : Stop BCR's (Bootable Card-Reader) Clock
    #endif
	GATED_ADMOD1M_CLK,		// 0xbe000184[3] : ...
	GATED_ADMOD49M_CLK,		// 0xbe000184[4] : ...
	GATED_DMAFE49M_CLK,		// 0xbe000184[5] : ...
	GATED_DMAFE36M_CLK,		// 0xbe000184[6] : ...
	#if (CONFIG_CHIPID == 0x8506)
	GATED_MCLK_HUM,			// 0xbe000184[7] : ...
    #else
	GATED_MCLK_UCCP,			// 0xbe000184[7] : ...
    #endif
	GATED_CRACLK,				// 0xbe000184[8] : Stop CRA's (Card-Reader A) Clock
	GATED_GMACGRX_INV_CLK,	// 0xbe000184[9] : ...
	GATED_GMACGTX_CLK,		// 0xbe000184[10] : ...
	GATED_GMACGRX_CLK,		// 0xbe000184[11] : ...
	GATED_GMACTX_CLK,			// 0xbe000184[12] : ...
	GATED_GMACRX_CLK,			// 0xbe000184[13] : ...
	GATED_MMIOCLK_CA,			// 0xbe000184[14] : Stop CA's MMIO Clock
	GATED_MCLK_CA,			// 0xbe000184[15] : Stop CA's MCLK
	GATED_MCLK_NFC,			// 0xbe000184[16] : Stop NFC's MCLK
	GATED_RESERVED17,		// 0xbe000184[17] : For 9565 only; 3D-Graphic clock
	GATED_RESERVED18,		// 0xbe000184[18] : For 9565 only; 3D-Graphic clock
	GATED_DMOD_CLK,			// 0xbe000184[19] : ...
	GATED_MCLK_CSI,			// 0xbe000184[20] : ...
	GATED_VENC_MAINCLK,		// 0xbe000184[21] : ...
	GATED_VENC_MEMCLK,		// 0xbe000184[22] : ...
	GATED_VENC_SYSCLK,		// 0xbe000184[23] : ...
	GATED_F24MCLK_DTVCIP,		// 0xbe000184[24] : ...
	GATED_F24MCLK_DTVPARSER,	// 0xbe000184[25] : ...
	GATED_F24MCLK_DTVPS,		// 0xbe000184[26] : ...
	GATED_F24MCLK_DTVREC,	// 0xbe000184[27] : ...
	GATED_MCLK_DTVPS,			// 0xbe000184[28] : ...
	GATED_MCLK_DTVREC,		// 0xbe000184[29] : ...
	GATED_MCLK_VENC,			// 0xbe000184[30] : ...
	GATED_F24MCLK_DEMOD,		// 0xbe000184[31] : ...


	GATED_CLK_MAX
};

enum
{	
    CPUACLK,
    CPUBCLK,
    MMIOCLK,
    MCLK,
    X2ICLK,
    BLKCLK,
    SPICLK,
    ECLK,
    YPP200MCLK,
    URCLK,
    DMODCLK,
    ADMOD49MCLK,
    AUADCCLK,
    AU36MCLK,
    AUBRCLK,
    PREPLL_CLK,
    CPLL_CLK,
	CLK_MAX
};

void drv_gated_clk_ctrl(unsigned int gated_pin, unsigned int ctrl);	// control gated clock bits in 0xbe000180
#define drv_gated_clk_ctrl2	drv_gated_clk_ctrl
//void drv_gated_clk_ctrl2(unsigned int gated_pin, unsigned int ctrl);	// control gated clock bits in 0xbe000184
void drv_gated_spiclk_ctrl(unsigned int ctrl);	// Stop SPI's Clock (AUX)
void drv_gated_pcclk_ctrl(unsigned int ctrl);	// Stop CPU Performance Counter's Clock (AUX)
void drv_gated_uartclk_ctrl(unsigned int ctrl);	// Stop UART's Clock (AUX)
void drv_gated_cecclk_ctrl(unsigned int ctrl);	// Stop CEC's Clock (AUX)
void drv_gated_hdmi_tmdsclk_ctrl(unsigned int ctrl);	// Stop HDMI_TMDS_CLK
unsigned int drv_get_device_clock(int device_id);
#endif //_DRV_GATED_CLK_H_