drv_mir.h 3.0 KB

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  1. /******************************************************************************/
  2. /**
  3. *
  4. * @file drv_mir.h
  5. *
  6. * @brief This file specifies the APIs provided to control MIR(TV Out)
  7. *
  8. * @note Copyright (c) 2013 S2 Technology Co., Ltd. \n
  9. * All rights reserved.
  10. *
  11. * @author
  12. *
  13. ******************************************************************************/
  14. #ifndef __DRV_MIR_H__
  15. #define __DRV_MIR_H__
  16. /*******************************************************************************
  17. * Header include
  18. ******************************************************************************/
  19. #include "drv_types.h"
  20. #ifdef CONFIG_ENABLE_MIR
  21. typedef struct _MIR_OUTPUT_TIMING
  22. {
  23. UINT32 ulHTotal;
  24. UINT32 ulVTotal;
  25. UINT32 ulHSyncStart;
  26. UINT32 ulHSyncEnd;
  27. UINT32 ulVSyncStart;
  28. UINT32 ulVSyncEnd;
  29. UINT32 ulHStart;
  30. UINT32 ulHEnd;
  31. UINT32 ulVStart;
  32. UINT32 ulVEnd;
  33. UINT32 ulVSyncStart_i;
  34. UINT32 ulVSyncEnd_i;
  35. UINT32 ulVStart_i;
  36. UINT32 ulVEnd_i;
  37. }_MIR_OUTPUT_TIMING,*p_MIR_OUTPUT_TIMING;
  38. void DRV_MIR_Reset(BOOL fEnable);
  39. void DRV_MIR_DisplayEn(BOOL fEnable);
  40. void DRV_MIR_MemoryRead_CbCr_YC_Swap(BOOL fCbCrEnable,BOOL fYCEnable);
  41. void DRV_MIR_MemoryWrite_CbCr_YC_Swap(BOOL fCbCrEnable,BOOL fYCEnable);
  42. void DRV_MIR_DPY_HSyncStartShift(UINT16 HSyncStartShift);
  43. void DRV_MIR_SetDisplayWindow(_MIR_OUTPUT_TIMING *pWindow);
  44. void DRV_MIR_Panel_Enable(BOOL fEnable);
  45. void DRV_MIR_SetPanelWindow(_MIR_OUTPUT_TIMING *pWindow);
  46. void DRV_MIR_SetDisplayWindow_Interlace(_MIR_OUTPUT_TIMING *pWindow);
  47. void DRV_MIR_Panel_NO_HVSync(BOOL fHSyncEnable,BOOL fVSyncEnable);
  48. void DRV_MIR_Clock(UINT8 *eMode);
  49. void DRV_MIR_SingleToDual_Enable(BOOL fEnable);
  50. void DRV_MIR_Function_Enable(BOOL fEnable);
  51. void DRV_MIR_SetSlrHVFactor(UINT32 HFactor, UINT32 VFactor);
  52. void DRV_MIR_SlrInHVSize(UINT32 HSize, UINT32 VSize);
  53. void DRV_MIR_SlrOutHVSize(UINT32 HSize, UINT32 VSize);
  54. void DRV_MIR_PostScalarInterlaceEn(BOOL fEnable);
  55. void DRV_MIR_PreScalarInterlaceEn(BOOL fEnable);
  56. void DRV_MIR_SetSlrConfig(UINT16 Config);
  57. void DRV_MIR_SetMemoryWidth(UINT32 Width);
  58. void DRV_MIR_Tearing_TH(UINT32 Value);
  59. void DRV_MIR_LCK_Shift(UINT16 Value);
  60. void DRV_MIR_Delay_Shift(BOOL fEnable);
  61. UINT16 DRV_MIR_GetHFactor(void);
  62. void DRV_MIR_SetMemoryReadWriteEn(BOOL fEnable);
  63. UINT16 DRV_MIR_GetSlrConfig(void);
  64. void DRV_MIR_SetMemoryPitch(UINT32 Value);
  65. void DRV_MIR_SetMemoryBurst(UINT8 Value);
  66. void DRV_MIR_SetMemoryAddrControlEn(BOOL fEnable, UINT32 RMemAddr, UINT32 WMemAddr);
  67. void DRV_MIR_YCCToRGB_Enable(BOOL fEnable);
  68. void DRV_MIR_444To422_Enable(BOOL fEnable);
  69. void DRV_MIR_422To444_Enable(BOOL fEnable);
  70. void DRV_MIR_422To444_INT(BOOL fEnable);
  71. void DRV_MIR_444To422_INT(BOOL fEnable);
  72. void DRV_MIR_SetMemoryBufferNumber(UINT8 Value);
  73. void DRV_MIR_SetMemoryBufferTopAddress(UINT32 MemAddr0,UINT32 MemAddr1,UINT32 MemAddr2,UINT32 MemAddr3);
  74. void DRV_MIR_SetMemoryBufferBottomAddress(UINT32 MemAddr0,UINT32 MemAddr1,UINT32 MemAddr2,UINT32 MemAddr3);
  75. void DRV_MIR_RGBToYCC_Enable(BOOL fEnable);
  76. void DRV_MIR_OSDOutput_Enable(BOOL fEnable);
  77. #endif
  78. #endif