UTS6710/drivers/adc/6710/adc_global.h

#ifndef _ADC_GLOBAL_H_
#define _ADC_GLOBAL_H_
//=================================================================================================
// Header files area
//=================================================================================================
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <asm/uaccess.h>
#include <asm/irq.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/version.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include <linux/wait.h>

#include <project.h>
#include <Customization.h>
#include <drv_spi.h>
#include <drv_gpio.h>
#include <drv_i2c.h>
#include <drv_debug.h>
#include <drv_platform.h>
#include "drv_types.h"
#include <drv_gated_clk.h>
#include <drv_adc_internal.h>
#include <drv_adc_external.h>

#include <drv_vip_internal.h>
//#include <pthread.h>
#include <drv_cvd2_internal.h>

#ifdef DRV_ENABLE_TUNER
	#include "drv_tuner_internal.h"
#endif

#include "drv_event.h"
#include "drv2kmf.h"
#include "drv_kmf_interface.h"

#include "adc_reg.h"
#include "adc_device.h"
#include "adc_hw.h"

//=================================================================================================
// Macro definition area
//=================================================================================================
#define I2CWriteADCFun(DeviceID,Address,Data,pStatus)	DRV_I2C_M0_WRITE_BYTE_100K(DeviceID,Address,Data,pStatus)
#define I2CReadADCFun(DeviceID,Address,pStatus)		DRV_I2C_M0_READ_BYTE_100K(DeviceID,Address,pStatus)

#ifdef CONFIG_CRYSTAL_USE_24MHZ
	#define System_CLK	24000
	// ADC adopts Crystal clock 
	#define CRYSTAL_CLK 24000					
	// (System_CLK/CRYSTAL_CLK)*1000
	#define SYS_CRYS_CLK_RATIO_PRECISE_3 1000	
#else
	#define System_CLK	24576
	// ADC adopts Crystal clock which is not the same as System clock since 131 chip
	#define CRYSTAL_CLK 24000					// CPU PLL
	#define SYS_CRYS_CLK_RATIO_PRECISE_3 1024	// CPU PLL  // (System_CLK/CRYSTAL_CLK)*1000
    
    //#define CRYSTAL_CLK 24576					// Pre PLL  
	//#define SYS_CRYS_CLK_RATIO_PRECISE_3 1000	// Pre PLL  // (System_CLK/CRYSTAL_CLK)*1000
#endif

#ifdef CONFIG_SUPPORT_DEBUG_MESSAGE
    #define ADC_DebugMsg(fmt, args...) DBG_MSG1(DBGCFG_ADC, "ADC] "fmt,## args)
	//#define ADC_ReleaseMsg(fmt, args...) RELEASE_MSG1(" [ADC] "fmt, ## args)
    #define COLOR_PRINT(color, fmt, args...) { if(color == RED) DBG_MSG1(DBGCFG_ADC, "\e[1;31mADC] "fmt "\e[0m",## args); \
										   if(color == GREEN) DBG_MSG1(DBGCFG_ADC, "\e[1;32mADC] "fmt "\e[0m",## args); \
										   if(color == BLUE) DBG_MSG1(DBGCFG_ADC, "\e[1;34mADC] "fmt "\e[0m",## args); }
#else
	#define ADC_DebugMsg(fmt, args...)
	#define ADC_ReleaseMsg(fmt, args...)
#endif

//Watch dog
#define ADC_WATCHDOG
#define WATCH_DOG_ADR 0xbe0f0300
#ifdef ADC_WATCHDOG
	#define ADC_ClearWatchDog set_bit(28, (void *)(WATCH_DOG_ADR));
#else
	#define ADC_ClearWatchDog
#endif

//IRQ
#define ADC_SYNC_IRQ				12
#define ADC_VGA_WAKEUP_IRQ          19
#define ADC_VIP_SYNC_IRQ			33

#define	GainYCodeDiff		6110		// G and Sog share pin target = [Diff of 533] * [High-Low ratio] = 6110 	
//#define	GainYCodeDiff		6008		// (235.75-16)/1.045 * ((1.05V-0.55V)/0.700) *4*10*
#define	GainCbCrCodeDiff		6124		// (240-16)/1.045 * ((1.05V-0.55V)/0.700) *4*10
#define	GainRGBCodeDiff		6950		// 0~255		
//#define	GainRGBCodeDiff		6562		// (250-5) * ((1.05V-0.55V)/0.700) *4*10   modify by patrick
//#define	GainRGBCodeDiff		6699		// (250-5)/1.045 * ((1.05V-0.55V)/0.700) *4*10
#define	GainScartCodeDiff	6699		//(250-5)/1.045 * ((1.05V-0.55V)/0.700) *4*10

//#define	OffsetRGBTarget		10*4*10
#define	OffsetRGBTarget		20 			// 0~255	
//#define	OffsetRGBTarget		5*4*10
#define	OffsetYTarget		17*4*10
//#define	OffsetCbCrTarget		5140	//(128+0.5)*4*10
#define	OffsetCbCrTarget	128*4*10	//5120

#define ADI_CENTERING_HOR_DELAY 	10	// HW horizontal active starting position delay for image centering procedure

//=================================================================================================
// Data structure type definition
//=================================================================================================
enum{
	RED=0,
	GREEN,
	BLUE,
	MaxColor
};

enum ADC_TimerType{
	TimerVsyncloss,
	TimerSignaloff,
	TimerModeChange,
	TimerTunerStrength,
};

#ifndef BIT0
enum {
    BIT0 				= 0x01,
    BIT1 				= 0x02,
    BIT2 				= 0x04,
    BIT3 				= 0x08,
    BIT4 				= 0x10,
    BIT5 				= 0x20,
    BIT6 				= 0x40,
    BIT7 				= 0x80
};
#endif

enum {
	Current_state_Failed=0,
	Csync_stable_i2_failed,
	VIP_No_Signal,
	Unsupported_Timing,
	Unstable_Timing_Setting,
	Mode_Change_Again,
	Mode_Change_Stable,
};

enum ADC_InterruptEvent
{
	CheckSogWidth,
	ResearchSogThreshold,
	ResetCoast,
	HandlerHSOut,
	CheckSyncStable,
	TotalInterruptEvent,
};

enum {
	ADCMSG_INPUTPATHSTATUS,
	NOTICEMSG_ADC_TURNOFFSOUND,
};

enum{
    SOURCE_VGA=0,
    SOURCE_COMPONENT1,
    SOURCE_COMPONENT2
};

typedef enum {
	ReturntoIdleEvent,
	MaxEvent
}ADC_EVENT;

typedef enum {
	HSYNC_POLARITY=0,
	VSYNC_POLARITY
}ADC_SyncPolarity_t;

typedef struct
{
	UINT8 ucSel1Gpio;
	UINT8 ucSel1GpioStatus;
	UINT8 ucSel2Gpio;
	UINT8 ucSel2GpioStatus;
} ADC_MuxGpio_t;

typedef struct _ADC_CONTEXT_ {
	UINT32		BaseAddress;
	UINT8		IrqNumber;
	void		(*ADCStateFun)(struct _ADC_CONTEXT_ *,ADC_EVENT);
}ADC_CONTEXT,*PADC_CONTEXT;

typedef struct _adc_ioctl_data
{
	BOOL bChangeFlow;
	UINT32 ucMatchTablePtr;
	UINT32 ucPhase;
	UINT32 ucColor;
	UINT32 ulPosition;
	UINT32 ulData;
	UINT32 ulTimes;
	UINT32 ulTargetValue[3];
	UINT32 ulClock;
}adc_ioctl_data, *pAdc_ioctl_data;

typedef struct _adc_ap_data
{
	BOOL bAutoFlow;
	BOOL bApUse;
	BOOL bDisableInterrupt;
	UINT8 ucMatchTable;
	UINT8 ucColor;
	UINT8 ucPhase;
	UINT32 ulApPosition;
	UINT32 ulData;
	UINT32 ulTimes;
	UINT32 ulTargetValue[3];
}adc_ap_data;

typedef struct _WhiteBalanceDebugMessage
{
	UINT32 ulCurrentSearch;
	UINT32 ulCurrentSearchValue;
	UINT32 ulDelta;
	UINT32 ulLowValue;
	UINT32 ulHighValue;
}WBDbgMsg;

typedef struct
{
	VesaTiming* pYppVideoTimingTable;
	UINT32 YppVideoTimingTblSize;
	VesaTiming* pVgaVideoTimingTable;
	UINT32 VgaVideoTimingTblSize;
	VesaTiming* pScartVideoTimingTable;
	UINT32 ScartVideoTimingTblSize;
}stADCTimingTable;

#endif  // End of #ifndef _ADC_GLOBAL_H_

//=================================================================================================
// External function list
//=================================================================================================
extern UINT32 ADC_Read(UINT32 uiAdr);
extern void ADC_Write(UINT32 uiAdr, UINT32 uiDat);
extern void ADC_DelayMS(UINT32 ulDelayMS );

//=================================================================================================
// External variable list
//=================================================================================================
extern AdcInfo sAdcInfo;
extern adc_ap_data gAdcAp;
extern INT32 iEnlargeWidthRate;
extern VesaTiming ADC_DetectTiming;
extern InputVideoConf_st adc_InputSrcPin;